1 // SPDX-License-Identifier: GPL-2.0
2 /* Marvell OcteonTx2 RVU Admin Function driver
4 * Copyright (C) 2018 Marvell International Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #include <linux/types.h>
12 #include <linux/module.h>
13 #include <linux/pci.h>
17 #include "lmac_common.h"
19 #include "rvu_trace.h"
21 struct cgx_evq_entry {
22 struct list_head evq_node;
23 struct cgx_link_event link_event;
26 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \
27 static struct _req_type __maybe_unused \
28 *otx2_mbox_alloc_msg_ ## _fn_name(struct rvu *rvu, int devid) \
30 struct _req_type *req; \
32 req = (struct _req_type *)otx2_mbox_alloc_msg_rsp( \
33 &rvu->afpf_wq_info.mbox_up, devid, sizeof(struct _req_type), \
34 sizeof(struct _rsp_type)); \
37 req->hdr.sig = OTX2_MBOX_REQ_SIG; \
39 trace_otx2_msg_alloc(rvu->pdev, _id, sizeof(*req)); \
46 bool is_mac_feature_supported(struct rvu *rvu, int pf, int feature)
51 if (!is_pf_cgxmapped(rvu, pf))
54 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
55 cgxd = rvu_cgx_pdata(cgx_id, rvu);
57 return (cgx_features_get(cgxd) & feature);
60 /* Returns bitmap of mapped PFs */
61 static u16 cgxlmac_to_pfmap(struct rvu *rvu, u8 cgx_id, u8 lmac_id)
63 return rvu->cgxlmac2pf_map[CGX_OFFSET(cgx_id) + lmac_id];
66 int cgxlmac_to_pf(struct rvu *rvu, int cgx_id, int lmac_id)
70 pfmap = cgxlmac_to_pfmap(rvu, cgx_id, lmac_id);
72 /* Assumes only one pf mapped to a cgx lmac port */
76 return find_first_bit(&pfmap, 16);
79 static u8 cgxlmac_id_to_bmap(u8 cgx_id, u8 lmac_id)
81 return ((cgx_id & 0xF) << 4) | (lmac_id & 0xF);
84 void *rvu_cgx_pdata(u8 cgx_id, struct rvu *rvu)
86 if (cgx_id >= rvu->cgx_cnt_max)
89 return rvu->cgx_idmap[cgx_id];
92 /* Return first enabled CGX instance if none are enabled then return NULL */
93 void *rvu_first_cgx_pdata(struct rvu *rvu)
95 int first_enabled_cgx = 0;
98 for (; first_enabled_cgx < rvu->cgx_cnt_max; first_enabled_cgx++) {
99 cgxd = rvu_cgx_pdata(first_enabled_cgx, rvu);
107 /* Based on P2X connectivity find mapped NIX block for a PF */
108 static void rvu_map_cgx_nix_block(struct rvu *rvu, int pf,
109 int cgx_id, int lmac_id)
111 struct rvu_pfvf *pfvf = &rvu->pf[pf];
114 p2x = cgx_lmac_get_p2x(cgx_id, lmac_id);
115 /* Firmware sets P2X_SELECT as either NIX0 or NIX1 */
116 pfvf->nix_blkaddr = BLKADDR_NIX0;
117 if (p2x == CMR_P2X_SEL_NIX1)
118 pfvf->nix_blkaddr = BLKADDR_NIX1;
121 static int rvu_map_cgx_lmac_pf(struct rvu *rvu)
123 struct npc_pkind *pkind = &rvu->hw->pkind;
124 int cgx_cnt_max = rvu->cgx_cnt_max;
125 int pf = PF_CGXMAP_BASE;
126 unsigned long lmac_bmap;
127 int size, free_pkind;
134 if (cgx_cnt_max > 0xF || MAX_LMAC_PER_CGX > 0xF)
138 * An additional entry is required since PF id starts from 1 and
139 * hence entry at offset 0 is invalid.
141 size = (cgx_cnt_max * MAX_LMAC_PER_CGX + 1) * sizeof(u8);
142 rvu->pf2cgxlmac_map = devm_kmalloc(rvu->dev, size, GFP_KERNEL);
143 if (!rvu->pf2cgxlmac_map)
146 /* Initialize all entries with an invalid cgx and lmac id */
147 memset(rvu->pf2cgxlmac_map, 0xFF, size);
149 /* Reverse map table */
150 rvu->cgxlmac2pf_map = devm_kzalloc(rvu->dev,
151 cgx_cnt_max * MAX_LMAC_PER_CGX * sizeof(u16),
153 if (!rvu->cgxlmac2pf_map)
156 rvu->cgx_mapped_pfs = 0;
157 for (cgx = 0; cgx < cgx_cnt_max; cgx++) {
158 if (!rvu_cgx_pdata(cgx, rvu))
160 lmac_bmap = cgx_get_lmac_bmap(rvu_cgx_pdata(cgx, rvu));
161 for_each_set_bit(iter, &lmac_bmap, MAX_LMAC_PER_CGX) {
162 lmac = cgx_get_lmacid(rvu_cgx_pdata(cgx, rvu),
164 rvu->pf2cgxlmac_map[pf] = cgxlmac_id_to_bmap(cgx, lmac);
165 rvu->cgxlmac2pf_map[CGX_OFFSET(cgx) + lmac] = 1 << pf;
166 free_pkind = rvu_alloc_rsrc(&pkind->rsrc);
167 pkind->pfchan_map[free_pkind] = ((pf) & 0x3F) << 16;
168 rvu_map_cgx_nix_block(rvu, pf, cgx, lmac);
169 rvu->cgx_mapped_pfs++;
170 rvu_get_pf_numvfs(rvu, pf, &numvfs, &hwvfs);
171 rvu->cgx_mapped_vfs += numvfs;
178 static int rvu_cgx_send_link_info(int cgx_id, int lmac_id, struct rvu *rvu)
180 struct cgx_evq_entry *qentry;
184 qentry = kmalloc(sizeof(*qentry), GFP_KERNEL);
188 /* Lock the event queue before we read the local link status */
189 spin_lock_irqsave(&rvu->cgx_evq_lock, flags);
190 err = cgx_get_link_info(rvu_cgx_pdata(cgx_id, rvu), lmac_id,
191 &qentry->link_event.link_uinfo);
192 qentry->link_event.cgx_id = cgx_id;
193 qentry->link_event.lmac_id = lmac_id;
198 list_add_tail(&qentry->evq_node, &rvu->cgx_evq_head);
200 spin_unlock_irqrestore(&rvu->cgx_evq_lock, flags);
202 /* start worker to process the events */
203 queue_work(rvu->cgx_evh_wq, &rvu->cgx_evh_work);
208 /* This is called from interrupt context and is expected to be atomic */
209 static int cgx_lmac_postevent(struct cgx_link_event *event, void *data)
211 struct cgx_evq_entry *qentry;
212 struct rvu *rvu = data;
214 /* post event to the event queue */
215 qentry = kmalloc(sizeof(*qentry), GFP_ATOMIC);
218 qentry->link_event = *event;
219 spin_lock(&rvu->cgx_evq_lock);
220 list_add_tail(&qentry->evq_node, &rvu->cgx_evq_head);
221 spin_unlock(&rvu->cgx_evq_lock);
223 /* start worker to process the events */
224 queue_work(rvu->cgx_evh_wq, &rvu->cgx_evh_work);
229 static void cgx_notify_pfs(struct cgx_link_event *event, struct rvu *rvu)
231 struct cgx_link_user_info *linfo;
232 struct cgx_link_info_msg *msg;
236 linfo = &event->link_uinfo;
237 pfmap = cgxlmac_to_pfmap(rvu, event->cgx_id, event->lmac_id);
240 pfid = find_first_bit(&pfmap, 16);
241 clear_bit(pfid, &pfmap);
243 /* check if notification is enabled */
244 if (!test_bit(pfid, &rvu->pf_notify_bmap)) {
245 dev_info(rvu->dev, "cgx %d: lmac %d Link status %s\n",
246 event->cgx_id, event->lmac_id,
247 linfo->link_up ? "UP" : "DOWN");
251 /* Send mbox message to PF */
252 msg = otx2_mbox_alloc_msg_cgx_link_event(rvu, pfid);
255 msg->link_info = *linfo;
256 otx2_mbox_msg_send(&rvu->afpf_wq_info.mbox_up, pfid);
257 err = otx2_mbox_wait_for_rsp(&rvu->afpf_wq_info.mbox_up, pfid);
259 dev_warn(rvu->dev, "notification to pf %d failed\n",
264 static void cgx_evhandler_task(struct work_struct *work)
266 struct rvu *rvu = container_of(work, struct rvu, cgx_evh_work);
267 struct cgx_evq_entry *qentry;
268 struct cgx_link_event *event;
272 /* Dequeue an event */
273 spin_lock_irqsave(&rvu->cgx_evq_lock, flags);
274 qentry = list_first_entry_or_null(&rvu->cgx_evq_head,
275 struct cgx_evq_entry,
278 list_del(&qentry->evq_node);
279 spin_unlock_irqrestore(&rvu->cgx_evq_lock, flags);
281 break; /* nothing more to process */
283 event = &qentry->link_event;
286 cgx_notify_pfs(event, rvu);
291 static int cgx_lmac_event_handler_init(struct rvu *rvu)
293 unsigned long lmac_bmap;
294 struct cgx_event_cb cb;
298 spin_lock_init(&rvu->cgx_evq_lock);
299 INIT_LIST_HEAD(&rvu->cgx_evq_head);
300 INIT_WORK(&rvu->cgx_evh_work, cgx_evhandler_task);
301 rvu->cgx_evh_wq = alloc_workqueue("rvu_evh_wq", 0, 0);
302 if (!rvu->cgx_evh_wq) {
303 dev_err(rvu->dev, "alloc workqueue failed");
307 cb.notify_link_chg = cgx_lmac_postevent; /* link change call back */
310 for (cgx = 0; cgx <= rvu->cgx_cnt_max; cgx++) {
311 cgxd = rvu_cgx_pdata(cgx, rvu);
314 lmac_bmap = cgx_get_lmac_bmap(cgxd);
315 for_each_set_bit(lmac, &lmac_bmap, MAX_LMAC_PER_CGX) {
316 err = cgx_lmac_evh_register(&cb, cgxd, lmac);
319 "%d:%d handler register failed\n",
327 static void rvu_cgx_wq_destroy(struct rvu *rvu)
329 if (rvu->cgx_evh_wq) {
330 flush_workqueue(rvu->cgx_evh_wq);
331 destroy_workqueue(rvu->cgx_evh_wq);
332 rvu->cgx_evh_wq = NULL;
336 int rvu_cgx_init(struct rvu *rvu)
341 /* CGX port id starts from 0 and are not necessarily contiguous
342 * Hence we allocate resources based on the maximum port id value.
344 rvu->cgx_cnt_max = cgx_get_cgxcnt_max();
345 if (!rvu->cgx_cnt_max) {
346 dev_info(rvu->dev, "No CGX devices found!\n");
350 rvu->cgx_idmap = devm_kzalloc(rvu->dev, rvu->cgx_cnt_max *
351 sizeof(void *), GFP_KERNEL);
355 /* Initialize the cgxdata table */
356 for (cgx = 0; cgx < rvu->cgx_cnt_max; cgx++)
357 rvu->cgx_idmap[cgx] = cgx_get_pdata(cgx);
359 /* Map CGX LMAC interfaces to RVU PFs */
360 err = rvu_map_cgx_lmac_pf(rvu);
364 /* Register for CGX events */
365 err = cgx_lmac_event_handler_init(rvu);
369 mutex_init(&rvu->cgx_cfg_lock);
371 /* Ensure event handler registration is completed, before
372 * we turn on the links
376 /* Do link up for all CGX ports */
377 for (cgx = 0; cgx <= rvu->cgx_cnt_max; cgx++) {
378 cgxd = rvu_cgx_pdata(cgx, rvu);
381 err = cgx_lmac_linkup_start(cgxd);
384 "Link up process failed to start on cgx %d\n",
391 int rvu_cgx_exit(struct rvu *rvu)
393 unsigned long lmac_bmap;
397 for (cgx = 0; cgx <= rvu->cgx_cnt_max; cgx++) {
398 cgxd = rvu_cgx_pdata(cgx, rvu);
401 lmac_bmap = cgx_get_lmac_bmap(cgxd);
402 for_each_set_bit(lmac, &lmac_bmap, MAX_LMAC_PER_CGX)
403 cgx_lmac_evh_unregister(cgxd, lmac);
406 /* Ensure event handler unregister is completed */
409 rvu_cgx_wq_destroy(rvu);
413 /* Most of the CGX configuration is restricted to the mapped PF only,
414 * VF's of mapped PF and other PFs are not allowed. This fn() checks
415 * whether a PFFUNC is permitted to do the config or not.
417 static bool is_cgx_config_permitted(struct rvu *rvu, u16 pcifunc)
419 if ((pcifunc & RVU_PFVF_FUNC_MASK) ||
420 !is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc)))
425 void rvu_cgx_enadis_rx_bp(struct rvu *rvu, int pf, bool enable)
427 struct mac_ops *mac_ops;
431 if (!is_pf_cgxmapped(rvu, pf))
434 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
435 cgxd = rvu_cgx_pdata(cgx_id, rvu);
437 mac_ops = get_mac_ops(cgxd);
438 /* Set / clear CTL_BCK to control pause frame forwarding to NIX */
440 mac_ops->mac_enadis_rx_pause_fwding(cgxd, lmac_id, true);
442 mac_ops->mac_enadis_rx_pause_fwding(cgxd, lmac_id, false);
445 int rvu_cgx_config_rxtx(struct rvu *rvu, u16 pcifunc, bool start)
447 int pf = rvu_get_pf(pcifunc);
450 if (!is_cgx_config_permitted(rvu, pcifunc))
453 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
455 cgx_lmac_rx_tx_enable(rvu_cgx_pdata(cgx_id, rvu), lmac_id, start);
460 void rvu_cgx_disable_dmac_entries(struct rvu *rvu, u16 pcifunc)
462 int pf = rvu_get_pf(pcifunc);
463 int i = 0, lmac_count = 0;
468 if (!is_cgx_config_permitted(rvu, pcifunc))
471 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
472 cgx_dev = cgx_get_pdata(cgx_id);
473 lmac_count = cgx_get_lmac_cnt(cgx_dev);
474 max_dmac_filters = MAX_DMAC_ENTRIES_PER_CGX / lmac_count;
476 for (i = 0; i < max_dmac_filters; i++)
477 cgx_lmac_addr_del(cgx_id, lmac_id, i);
479 /* As cgx_lmac_addr_del does not clear entry for index 0
480 * so it needs to be done explicitly
482 cgx_lmac_addr_reset(cgx_id, lmac_id);
485 int rvu_mbox_handler_cgx_start_rxtx(struct rvu *rvu, struct msg_req *req,
488 rvu_cgx_config_rxtx(rvu, req->hdr.pcifunc, true);
492 int rvu_mbox_handler_cgx_stop_rxtx(struct rvu *rvu, struct msg_req *req,
495 rvu_cgx_config_rxtx(rvu, req->hdr.pcifunc, false);
499 static int rvu_lmac_get_stats(struct rvu *rvu, struct msg_req *req,
502 int pf = rvu_get_pf(req->hdr.pcifunc);
503 struct mac_ops *mac_ops;
504 int stat = 0, err = 0;
505 u64 tx_stat, rx_stat;
509 if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
512 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_idx, &lmac);
513 cgxd = rvu_cgx_pdata(cgx_idx, rvu);
514 mac_ops = get_mac_ops(cgxd);
517 while (stat < mac_ops->rx_stats_cnt) {
518 err = mac_ops->mac_get_rx_stats(cgxd, lmac, stat, &rx_stat);
521 if (mac_ops->rx_stats_cnt == RPM_RX_STATS_COUNT)
522 ((struct rpm_stats_rsp *)rsp)->rx_stats[stat] = rx_stat;
524 ((struct cgx_stats_rsp *)rsp)->rx_stats[stat] = rx_stat;
530 while (stat < mac_ops->tx_stats_cnt) {
531 err = mac_ops->mac_get_tx_stats(cgxd, lmac, stat, &tx_stat);
534 if (mac_ops->tx_stats_cnt == RPM_TX_STATS_COUNT)
535 ((struct rpm_stats_rsp *)rsp)->tx_stats[stat] = tx_stat;
537 ((struct cgx_stats_rsp *)rsp)->tx_stats[stat] = tx_stat;
543 int rvu_mbox_handler_cgx_stats(struct rvu *rvu, struct msg_req *req,
544 struct cgx_stats_rsp *rsp)
546 return rvu_lmac_get_stats(rvu, req, (void *)rsp);
549 int rvu_mbox_handler_rpm_stats(struct rvu *rvu, struct msg_req *req,
550 struct rpm_stats_rsp *rsp)
552 return rvu_lmac_get_stats(rvu, req, (void *)rsp);
555 int rvu_mbox_handler_cgx_fec_stats(struct rvu *rvu,
557 struct cgx_fec_stats_rsp *rsp)
559 int pf = rvu_get_pf(req->hdr.pcifunc);
563 if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
565 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_idx, &lmac);
567 cgxd = rvu_cgx_pdata(cgx_idx, rvu);
568 return cgx_get_fec_stats(cgxd, lmac, rsp);
571 int rvu_mbox_handler_cgx_mac_addr_set(struct rvu *rvu,
572 struct cgx_mac_addr_set_or_get *req,
573 struct cgx_mac_addr_set_or_get *rsp)
575 int pf = rvu_get_pf(req->hdr.pcifunc);
578 if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
581 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
583 cgx_lmac_addr_set(cgx_id, lmac_id, req->mac_addr);
588 int rvu_mbox_handler_cgx_mac_addr_add(struct rvu *rvu,
589 struct cgx_mac_addr_add_req *req,
590 struct cgx_mac_addr_add_rsp *rsp)
592 int pf = rvu_get_pf(req->hdr.pcifunc);
596 if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
599 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
600 rc = cgx_lmac_addr_add(cgx_id, lmac_id, req->mac_addr);
609 int rvu_mbox_handler_cgx_mac_addr_del(struct rvu *rvu,
610 struct cgx_mac_addr_del_req *req,
613 int pf = rvu_get_pf(req->hdr.pcifunc);
616 if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
619 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
620 return cgx_lmac_addr_del(cgx_id, lmac_id, req->index);
623 int rvu_mbox_handler_cgx_mac_max_entries_get(struct rvu *rvu,
625 struct cgx_max_dmac_entries_get_rsp
628 int pf = rvu_get_pf(req->hdr.pcifunc);
631 /* If msg is received from PFs(which are not mapped to CGX LMACs)
632 * or VF then no entries are allocated for DMAC filters at CGX level.
635 if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc)) {
636 rsp->max_dmac_filters = 0;
640 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
641 rsp->max_dmac_filters = cgx_lmac_addr_max_entries_get(cgx_id, lmac_id);
645 int rvu_mbox_handler_cgx_mac_addr_get(struct rvu *rvu,
646 struct cgx_mac_addr_set_or_get *req,
647 struct cgx_mac_addr_set_or_get *rsp)
649 int pf = rvu_get_pf(req->hdr.pcifunc);
654 if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
657 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
660 cfg = cgx_lmac_addr_get(cgx_id, lmac_id);
661 /* copy 48 bit mac address to req->mac_addr */
662 for (i = 0; i < ETH_ALEN; i++)
663 rsp->mac_addr[i] = cfg >> (ETH_ALEN - 1 - i) * 8;
667 int rvu_mbox_handler_cgx_promisc_enable(struct rvu *rvu, struct msg_req *req,
670 u16 pcifunc = req->hdr.pcifunc;
671 int pf = rvu_get_pf(pcifunc);
674 if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
677 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
679 cgx_lmac_promisc_config(cgx_id, lmac_id, true);
683 int rvu_mbox_handler_cgx_promisc_disable(struct rvu *rvu, struct msg_req *req,
686 int pf = rvu_get_pf(req->hdr.pcifunc);
689 if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
692 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
694 cgx_lmac_promisc_config(cgx_id, lmac_id, false);
698 static int rvu_cgx_ptp_rx_cfg(struct rvu *rvu, u16 pcifunc, bool enable)
700 int pf = rvu_get_pf(pcifunc);
704 if (!is_mac_feature_supported(rvu, pf, RVU_LMAC_FEAT_PTP))
707 /* This msg is expected only from PFs that are mapped to CGX LMACs,
708 * if received from other PF/VF simply ACK, nothing to do.
710 if ((pcifunc & RVU_PFVF_FUNC_MASK) ||
711 !is_pf_cgxmapped(rvu, pf))
714 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
715 cgxd = rvu_cgx_pdata(cgx_id, rvu);
717 cgx_lmac_ptp_config(cgxd, lmac_id, enable);
718 /* If PTP is enabled then inform NPC that packets to be
719 * parsed by this PF will have their data shifted by 8 bytes
720 * and if PTP is disabled then no shift is required
722 if (npc_config_ts_kpuaction(rvu, pf, pcifunc, enable))
728 int rvu_mbox_handler_cgx_ptp_rx_enable(struct rvu *rvu, struct msg_req *req,
731 return rvu_cgx_ptp_rx_cfg(rvu, req->hdr.pcifunc, true);
734 int rvu_mbox_handler_cgx_ptp_rx_disable(struct rvu *rvu, struct msg_req *req,
737 return rvu_cgx_ptp_rx_cfg(rvu, req->hdr.pcifunc, false);
740 static int rvu_cgx_config_linkevents(struct rvu *rvu, u16 pcifunc, bool en)
742 int pf = rvu_get_pf(pcifunc);
745 if (!is_cgx_config_permitted(rvu, pcifunc))
748 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
751 set_bit(pf, &rvu->pf_notify_bmap);
752 /* Send the current link status to PF */
753 rvu_cgx_send_link_info(cgx_id, lmac_id, rvu);
755 clear_bit(pf, &rvu->pf_notify_bmap);
761 int rvu_mbox_handler_cgx_start_linkevents(struct rvu *rvu, struct msg_req *req,
764 rvu_cgx_config_linkevents(rvu, req->hdr.pcifunc, true);
768 int rvu_mbox_handler_cgx_stop_linkevents(struct rvu *rvu, struct msg_req *req,
771 rvu_cgx_config_linkevents(rvu, req->hdr.pcifunc, false);
775 int rvu_mbox_handler_cgx_get_linkinfo(struct rvu *rvu, struct msg_req *req,
776 struct cgx_link_info_msg *rsp)
781 pf = rvu_get_pf(req->hdr.pcifunc);
783 if (!is_pf_cgxmapped(rvu, pf))
786 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
788 err = cgx_get_link_info(rvu_cgx_pdata(cgx_id, rvu), lmac_id,
793 int rvu_mbox_handler_cgx_features_get(struct rvu *rvu,
795 struct cgx_features_info_msg *rsp)
797 int pf = rvu_get_pf(req->hdr.pcifunc);
801 if (!is_pf_cgxmapped(rvu, pf))
804 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_idx, &lmac);
805 cgxd = rvu_cgx_pdata(cgx_idx, rvu);
806 rsp->lmac_features = cgx_features_get(cgxd);
811 u32 rvu_cgx_get_fifolen(struct rvu *rvu)
813 struct mac_ops *mac_ops;
816 mac_ops = get_mac_ops(rvu_first_cgx_pdata(rvu));
817 fifo_len = mac_ops ? mac_ops->fifo_len : 0;
822 static int rvu_cgx_config_intlbk(struct rvu *rvu, u16 pcifunc, bool en)
824 int pf = rvu_get_pf(pcifunc);
825 struct mac_ops *mac_ops;
828 if (!is_cgx_config_permitted(rvu, pcifunc))
831 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
832 mac_ops = get_mac_ops(rvu_cgx_pdata(cgx_id, rvu));
834 return mac_ops->mac_lmac_intl_lbk(rvu_cgx_pdata(cgx_id, rvu),
838 int rvu_mbox_handler_cgx_intlbk_enable(struct rvu *rvu, struct msg_req *req,
841 rvu_cgx_config_intlbk(rvu, req->hdr.pcifunc, true);
845 int rvu_mbox_handler_cgx_intlbk_disable(struct rvu *rvu, struct msg_req *req,
848 rvu_cgx_config_intlbk(rvu, req->hdr.pcifunc, false);
852 int rvu_mbox_handler_cgx_cfg_pause_frm(struct rvu *rvu,
853 struct cgx_pause_frm_cfg *req,
854 struct cgx_pause_frm_cfg *rsp)
856 int pf = rvu_get_pf(req->hdr.pcifunc);
857 struct mac_ops *mac_ops;
861 if (!is_mac_feature_supported(rvu, pf, RVU_LMAC_FEAT_FC))
864 /* This msg is expected only from PF/VFs that are mapped to CGX LMACs,
865 * if received from other PF/VF simply ACK, nothing to do.
867 if (!is_pf_cgxmapped(rvu, pf))
870 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
871 cgxd = rvu_cgx_pdata(cgx_id, rvu);
872 mac_ops = get_mac_ops(cgxd);
875 mac_ops->mac_enadis_pause_frm(cgxd, lmac_id,
876 req->tx_pause, req->rx_pause);
878 mac_ops->mac_get_pause_frm_status(cgxd, lmac_id,
884 int rvu_mbox_handler_cgx_get_phy_fec_stats(struct rvu *rvu, struct msg_req *req,
887 int pf = rvu_get_pf(req->hdr.pcifunc);
890 if (!is_pf_cgxmapped(rvu, pf))
893 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
894 return cgx_get_phy_fec_stats(rvu_cgx_pdata(cgx_id, rvu), lmac_id);
897 /* Finds cumulative status of NIX rx/tx counters from LF of a PF and those
898 * from its VFs as well. ie. NIX rx/tx counters at the CGX port level
900 int rvu_cgx_nix_cuml_stats(struct rvu *rvu, void *cgxd, int lmac_id,
901 int index, int rxtxflag, u64 *stat)
903 struct rvu_block *block;
913 pf = cgxlmac_to_pf(rvu, cgx_get_cgxid(cgxd), lmac_id);
917 /* Assumes LF of a PF and all of its VF belongs to the same
920 pcifunc = pf << RVU_PFVF_PF_SHIFT;
921 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc);
924 block = &rvu->hw->block[blkaddr];
926 for (lf = 0; lf < block->lf.max; lf++) {
927 /* Check if a lf is attached to this PF or one of its VFs */
928 if (!((block->fn_map[lf] & ~RVU_PFVF_FUNC_MASK) == (pcifunc &
929 ~RVU_PFVF_FUNC_MASK)))
931 if (rxtxflag == NIX_STATS_RX)
932 *stat += rvu_read64(rvu, blkaddr,
933 NIX_AF_LFX_RX_STATX(lf, index));
935 *stat += rvu_read64(rvu, blkaddr,
936 NIX_AF_LFX_TX_STATX(lf, index));
942 int rvu_cgx_start_stop_io(struct rvu *rvu, u16 pcifunc, bool start)
944 struct rvu_pfvf *parent_pf, *pfvf;
945 int cgx_users, err = 0;
947 if (!is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc)))
950 parent_pf = &rvu->pf[rvu_get_pf(pcifunc)];
951 pfvf = rvu_get_pfvf(rvu, pcifunc);
953 mutex_lock(&rvu->cgx_cfg_lock);
955 if (start && pfvf->cgx_in_use)
956 goto exit; /* CGX is already started hence nothing to do */
957 if (!start && !pfvf->cgx_in_use)
958 goto exit; /* CGX is already stopped hence nothing to do */
961 cgx_users = parent_pf->cgx_users;
962 parent_pf->cgx_users++;
964 parent_pf->cgx_users--;
965 cgx_users = parent_pf->cgx_users;
968 /* Start CGX when first of all NIXLFs is started.
969 * Stop CGX when last of all NIXLFs is stopped.
972 err = rvu_cgx_config_rxtx(rvu, pcifunc & ~RVU_PFVF_FUNC_MASK,
975 dev_err(rvu->dev, "Unable to %s CGX\n",
976 start ? "start" : "stop");
977 /* Revert the usage count in case of error */
978 parent_pf->cgx_users = start ? parent_pf->cgx_users - 1
979 : parent_pf->cgx_users + 1;
983 pfvf->cgx_in_use = start;
985 mutex_unlock(&rvu->cgx_cfg_lock);
989 int rvu_mbox_handler_cgx_set_fec_param(struct rvu *rvu,
990 struct fec_mode *req,
991 struct fec_mode *rsp)
993 int pf = rvu_get_pf(req->hdr.pcifunc);
996 if (!is_pf_cgxmapped(rvu, pf))
999 if (req->fec == OTX2_FEC_OFF)
1000 req->fec = OTX2_FEC_NONE;
1001 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
1002 rsp->fec = cgx_set_fec(req->fec, cgx_id, lmac_id);
1006 int rvu_mbox_handler_cgx_get_aux_link_info(struct rvu *rvu, struct msg_req *req,
1007 struct cgx_fw_data *rsp)
1009 int pf = rvu_get_pf(req->hdr.pcifunc);
1015 if (!is_pf_cgxmapped(rvu, pf))
1018 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
1020 memcpy(&rsp->fwdata, &rvu->fwdata->cgx_fw_data[cgx_id][lmac_id],
1021 sizeof(struct cgx_lmac_fwdata_s));
1025 int rvu_mbox_handler_cgx_set_link_mode(struct rvu *rvu,
1026 struct cgx_set_link_mode_req *req,
1027 struct cgx_set_link_mode_rsp *rsp)
1029 int pf = rvu_get_pf(req->hdr.pcifunc);
1033 if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
1036 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_idx, &lmac);
1037 cgxd = rvu_cgx_pdata(cgx_idx, rvu);
1038 rsp->status = cgx_set_link_mode(cgxd, req->args, cgx_idx, lmac);
1042 int rvu_mbox_handler_cgx_mac_addr_reset(struct rvu *rvu, struct msg_req *req,
1043 struct msg_rsp *rsp)
1045 int pf = rvu_get_pf(req->hdr.pcifunc);
1048 if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
1051 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
1052 return cgx_lmac_addr_reset(cgx_id, lmac_id);
1055 int rvu_mbox_handler_cgx_mac_addr_update(struct rvu *rvu,
1056 struct cgx_mac_addr_update_req *req,
1057 struct msg_rsp *rsp)
1059 int pf = rvu_get_pf(req->hdr.pcifunc);
1062 if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
1065 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
1066 return cgx_lmac_addr_update(cgx_id, lmac_id, req->mac_addr, req->index);