1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Marvell OcteonTx2 RVU Admin Function driver
4 * Copyright (C) 2018 Marvell International Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
14 #include <linux/pci.h>
15 #include "rvu_struct.h"
21 #define PCI_DEVID_OCTEONTX2_RVU_AF 0xA065
23 /* Subsystem Device ID */
24 #define PCI_SUBSYS_DEVID_96XX 0xB200
27 #define PCI_AF_REG_BAR_NUM 0
28 #define PCI_PF_REG_BAR_NUM 2
29 #define PCI_MBOX_BAR_NUM 4
32 #define MAX_NIX_BLKS 2
35 #define RVU_PFVF_PF_SHIFT 10
36 #define RVU_PFVF_PF_MASK 0x3F
37 #define RVU_PFVF_FUNC_SHIFT 0
38 #define RVU_PFVF_FUNC_MASK 0x3FF
40 #ifdef CONFIG_DEBUG_FS
49 struct dentry *cgx_root;
55 struct dump_ctx npa_aura_ctx;
56 struct dump_ctx npa_pool_ctx;
57 struct dump_ctx nix_cq_ctx;
58 struct dump_ctx nix_rq_ctx;
59 struct dump_ctx nix_sq_ctx;
66 struct work_struct work;
73 unsigned long *bmap; /* Pointer to resource bitmap */
74 u16 max; /* Max resource id or count */
79 struct admin_queue *aq; /* NIX/NPA AQ */
80 u16 *fn_map; /* LF to pcifunc mapping */
83 u8 addr; /* RVU_BLOCK_ADDR_E */
84 u8 type; /* RVU_BLOCK_TYPE_E */
92 unsigned char name[NAME_SIZE];
97 struct qmem *mcast_buf;
100 struct mutex mce_lock; /* Serialize MCE updates */
103 struct nix_mce_list {
104 struct hlist_head head;
109 /* layer metadata to uniquely identify a packet header field */
110 struct npc_layer_mdata {
118 /* Structure to represent a field present in the
119 * generated key. A key field may present anywhere and can
120 * be of any size in the generated key. Once this structure
121 * is populated for fields of interest then field's presence
122 * and location (if present) can be known.
124 struct npc_key_field {
125 /* Masks where all set bits indicate position
126 * of a field in the key
128 u64 kw_mask[NPC_MAX_KWS_IN_KEY];
129 /* Number of words in the key a field spans. If a field is
130 * of 16 bytes and key offset is 4 then the field will use
131 * 4 bytes in KW0, 8 bytes in KW1 and 4 bytes in KW2 and
132 * nr_kws will be 3(KW0, KW1 and KW2).
135 /* used by packet header fields */
136 struct npc_layer_mdata layer_mdata;
140 struct rsrc_bmap counters;
141 struct mutex lock; /* MCAM entries and counters update lock */
142 unsigned long *bmap; /* bitmap, 0 => bmap_entries */
143 unsigned long *bmap_reverse; /* Reverse bitmap, bmap_entries => 0 */
144 u16 bmap_entries; /* Number of unreserved MCAM entries */
145 u16 bmap_fcnt; /* MCAM entries free count */
150 u16 *entry2target_pffunc;
151 u8 keysize; /* MCAM keysize 112/224/448 bits */
152 u8 banks; /* Number of MCAM banks */
153 u8 banks_per_entry;/* Number of keywords in key */
154 u16 banksize; /* Number of MCAM entries in each bank */
155 u16 total_entries; /* Total number of MCAM entries */
156 u16 nixlf_offset; /* Offset of nixlf rsvd uncast entries */
157 u16 pf_offset; /* Offset of PF's rsvd bcast, promisc entries */
162 u16 rx_miss_act_cntr; /* Counter for RX MISS action */
163 /* fields present in the generated key */
164 struct npc_key_field tx_key_fields[NPC_KEY_FIELDS_MAX];
165 struct npc_key_field rx_key_fields[NPC_KEY_FIELDS_MAX];
168 struct list_head mcam_rules;
171 /* Structure for per RVU func info ie PF/VF */
173 bool npalf; /* Only one NPALF per RVU_FUNC */
174 bool nixlf; /* Only one NIXLF per RVU_FUNC */
182 /* Block LF's MSIX vector info */
183 struct rsrc_bmap msix; /* Bitmap for MSIX vector alloc */
184 #define MSIX_BLKLF(blkaddr, lf) (((blkaddr) << 8) | ((lf) & 0xFF))
185 u16 *msix_lfmap; /* Vector to block LF mapping */
188 struct qmem *aura_ctx;
189 struct qmem *pool_ctx;
190 struct qmem *npa_qints_ctx;
191 unsigned long *aura_bmap;
192 unsigned long *pool_bmap;
198 struct qmem *rss_ctx;
199 struct qmem *cq_ints_ctx;
200 struct qmem *nix_qints_ctx;
201 unsigned long *sq_bmap;
202 unsigned long *rq_bmap;
203 unsigned long *cq_bmap;
207 u8 rx_chan_cnt; /* total number of RX channels */
208 u8 tx_chan_cnt; /* total number of TX channels */
213 u8 mac_addr[ETH_ALEN]; /* MAC address of this PF/VF */
214 u8 default_mac[ETH_ALEN]; /* MAC address from FWdata */
216 /* Broadcast pkt replication info */
218 struct nix_mce_list bcast_mce_list;
221 struct mcam_entry entry;
225 struct rvu_npc_mcam_rule *def_ucast_rule;
227 bool cgx_in_use; /* this PF/VF using CGX? */
228 int cgx_users; /* number of cgx users - used only by PFs */
230 u8 nix_blkaddr; /* BLKADDR_NIX0/1 assigned to this PF */
231 u8 nix_rx_intf; /* NIX0_RX/NIX1_RX interface to NPC */
232 u8 nix_tx_intf; /* NIX0_TX/NIX1_TX interface to NPC */
236 struct rsrc_bmap schq;
238 #define NIX_TXSCHQ_FREE BIT_ULL(1)
239 #define NIX_TXSCHQ_CFG_DONE BIT_ULL(0)
240 #define TXSCH_MAP_FUNC(__pfvf_map) ((__pfvf_map) & 0xFFFF)
241 #define TXSCH_MAP_FLAGS(__pfvf_map) ((__pfvf_map) >> 16)
242 #define TXSCH_MAP(__func, __flags) (((__func) & 0xFFFF) | ((__flags) << 16))
243 #define TXSCH_SET_FLAG(__pfvf_map, flag) ((__pfvf_map) | ((flag) << 16))
247 struct nix_mark_format {
254 struct rsrc_bmap rsrc;
259 #define NIX_FLOW_KEY_ALG_MAX 32
260 u32 flowkey[NIX_FLOW_KEY_ALG_MAX];
270 #define NIX_TX_VTAG_DEF_MAX 0x400
271 struct rsrc_bmap rsrc;
273 struct mutex rsrc_lock; /* Serialize resource alloc/free */
279 struct nix_txsch txsch[NIX_TXSCH_LVL_CNT]; /* Tx schedulers */
280 struct nix_mcast mcast;
281 struct nix_flowkey flowkey;
282 struct nix_mark_format mark_format;
284 struct nix_txvlan txvlan;
287 /* RVU block's capabilities or functionality,
288 * which vary by silicon version/skew.
291 /* Transmit side supported functionality */
292 u8 nix_tx_aggr_lvl; /* Tx link's traffic aggregation level */
293 u16 nix_txsch_per_cgx_lmac; /* Max Q's transmitting to CGX LMAC */
294 u16 nix_txsch_per_lbk_lmac; /* Max Q's transmitting to LBK LMAC */
295 u16 nix_txsch_per_sdp_lmac; /* Max Q's transmitting to SDP LMAC */
296 bool nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */
297 bool nix_shaping; /* Is shaping and coloring supported */
298 bool nix_tx_link_bp; /* Can link backpressure TL queues ? */
299 bool nix_rx_multicast; /* Rx packet replication support */
303 u8 total_pfs; /* MAX RVU PFs HW supports */
304 u16 total_vfs; /* Max RVU VFs HW supports */
305 u16 max_vfs_per_pf; /* Max VFs that can be attached to a PF */
311 u8 npc_kpus; /* No of parser units */
312 u8 npc_pkinds; /* No of port kinds */
313 u8 npc_intfs; /* No of interfaces */
314 u8 npc_kpu_entries; /* No of KPU entries */
315 u16 npc_counters; /* No of match stats counters */
316 bool npc_ext_set; /* Extended register set */
319 struct rvu_block block[BLK_COUNT]; /* Block info */
322 struct npc_pkind pkind;
323 struct npc_mcam mcam;
326 struct mbox_wq_info {
327 struct otx2_mbox mbox;
328 struct rvu_work *mbox_wrk;
330 struct otx2_mbox mbox_up;
331 struct rvu_work *mbox_wrk_up;
333 struct workqueue_struct *mbox_wq;
337 #define RVU_FWDATA_HEADER_MAGIC 0xCFDA /* Custom Firmware Data*/
338 #define RVU_FWDATA_VERSION 0x0001
340 u32 version; /* version id */
343 #define PF_MACNUM_MAX 32
344 #define VF_MACNUM_MAX 256
345 u64 pf_macs[PF_MACNUM_MAX];
346 u64 vf_macs[VF_MACNUM_MAX];
352 #define FWDATA_RESERVED_MEM 1023
353 u64 reserved[FWDATA_RESERVED_MEM];
358 /* KPU profile adapter structure gathering all KPU configuration data and abstracting out the
359 * source where it came from.
361 struct npc_kpu_profile_adapter {
364 const struct npc_lt_def_cfg *lt_def;
365 const struct npc_kpu_profile_action *ikpu; /* array[pkinds] */
366 const struct npc_kpu_profile *kpu; /* array[kpus] */
367 struct npc_mcam_kex *mkex;
373 void __iomem *afreg_base;
374 void __iomem *pfreg_base;
375 struct pci_dev *pdev;
377 struct rvu_hwinfo *hw;
379 struct rvu_pfvf *hwvf;
380 struct mutex rsrc_lock; /* Serialize resource alloc/free */
381 int vfs; /* Number of VFs attached to RVU */
382 int nix_blkaddr[MAX_NIX_BLKS];
385 struct mbox_wq_info afpf_wq_info;
386 struct mbox_wq_info afvf_wq_info;
389 struct rvu_work *flr_wrk;
390 struct workqueue_struct *flr_wq;
391 struct mutex flr_lock; /* Serialize FLRs */
397 dma_addr_t msix_base_iova;
398 u64 msixtr_base_phy; /* Register reset value */
401 #define PF_CGXMAP_BASE 1 /* PF 0 is reserved for RVU PF */
403 u8 cgx_cnt_max; /* CGX port count max */
404 u8 *pf2cgxlmac_map; /* pf to cgx_lmac map */
405 u16 *cgxlmac2pf_map; /* bitmap of mapped pfs for
406 * every cgx lmac port
408 unsigned long pf_notify_bmap; /* Flags for PF notification */
409 void **cgx_idmap; /* cgx id to cgx data map table */
410 struct work_struct cgx_evh_work;
411 struct workqueue_struct *cgx_evh_wq;
412 spinlock_t cgx_evq_lock; /* cgx event queue lock */
413 struct list_head cgx_evq_head; /* cgx event queue head */
414 struct mutex cgx_cfg_lock; /* serialize cgx configuration */
416 char mkex_pfl_name[MKEX_NAME_LEN]; /* Configured MKEX profile name */
419 struct rvu_fwdata *fwdata;
422 struct npc_kpu_profile_adapter kpu;
426 #ifdef CONFIG_DEBUG_FS
427 struct rvu_debugfs rvu_dbg;
431 static inline void rvu_write64(struct rvu *rvu, u64 block, u64 offset, u64 val)
433 writeq(val, rvu->afreg_base + ((block << 28) | offset));
436 static inline u64 rvu_read64(struct rvu *rvu, u64 block, u64 offset)
438 return readq(rvu->afreg_base + ((block << 28) | offset));
441 static inline void rvupf_write64(struct rvu *rvu, u64 offset, u64 val)
443 writeq(val, rvu->pfreg_base + offset);
446 static inline u64 rvupf_read64(struct rvu *rvu, u64 offset)
448 return readq(rvu->pfreg_base + offset);
451 /* Silicon revisions */
452 static inline bool is_rvu_96xx_A0(struct rvu *rvu)
454 struct pci_dev *pdev = rvu->pdev;
456 return (pdev->revision == 0x00) &&
457 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX);
460 static inline bool is_rvu_96xx_B0(struct rvu *rvu)
462 struct pci_dev *pdev = rvu->pdev;
464 return ((pdev->revision == 0x00) || (pdev->revision == 0x01)) &&
465 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX);
468 /* Function Prototypes
471 static inline int is_afvf(u16 pcifunc)
473 return !(pcifunc & ~RVU_PFVF_FUNC_MASK);
476 static inline bool is_rvu_fwdata_valid(struct rvu *rvu)
478 return (rvu->fwdata->header_magic == RVU_FWDATA_HEADER_MAGIC) &&
479 (rvu->fwdata->version == RVU_FWDATA_VERSION);
482 int rvu_alloc_bitmap(struct rsrc_bmap *rsrc);
483 int rvu_alloc_rsrc(struct rsrc_bmap *rsrc);
484 void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id);
485 int rvu_rsrc_free_count(struct rsrc_bmap *rsrc);
486 int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc);
487 bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc);
488 u16 rvu_get_rsrc_mapcount(struct rvu_pfvf *pfvf, int blkaddr);
489 int rvu_get_pf(u16 pcifunc);
490 struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc);
491 void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf);
492 bool is_block_implemented(struct rvu_hwinfo *hw, int blkaddr);
493 bool is_pffunc_map_valid(struct rvu *rvu, u16 pcifunc, int blktype);
494 int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot);
495 int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block, int lf);
496 int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc);
497 int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero);
498 int rvu_get_num_lbk_chans(void);
500 /* RVU HW reg validation */
506 bool rvu_check_valid_reg(int regmap, int regblk, u64 reg);
508 /* NPA/NIX AQ APIs */
509 int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue,
510 int qsize, int inst_size, int res_size);
511 void rvu_aq_free(struct rvu *rvu, struct admin_queue *aq);
514 static inline bool is_pf_cgxmapped(struct rvu *rvu, u8 pf)
516 return (pf >= PF_CGXMAP_BASE && pf <= rvu->cgx_mapped_pfs);
519 static inline void rvu_get_cgx_lmac_id(u8 map, u8 *cgx_id, u8 *lmac_id)
521 *cgx_id = (map >> 4) & 0xF;
522 *lmac_id = (map & 0xF);
525 #define M(_name, _id, fn_name, req, rsp) \
526 int rvu_mbox_handler_ ## fn_name(struct rvu *, struct req *, struct rsp *);
530 int rvu_cgx_init(struct rvu *rvu);
531 int rvu_cgx_exit(struct rvu *rvu);
532 void *rvu_cgx_pdata(u8 cgx_id, struct rvu *rvu);
533 int rvu_cgx_config_rxtx(struct rvu *rvu, u16 pcifunc, bool start);
534 void rvu_cgx_enadis_rx_bp(struct rvu *rvu, int pf, bool enable);
535 int rvu_cgx_start_stop_io(struct rvu *rvu, u16 pcifunc, bool start);
536 int rvu_cgx_nix_cuml_stats(struct rvu *rvu, void *cgxd, int lmac_id, int index,
537 int rxtxflag, u64 *stat);
539 int rvu_npa_init(struct rvu *rvu);
540 void rvu_npa_freemem(struct rvu *rvu);
541 void rvu_npa_lf_teardown(struct rvu *rvu, u16 pcifunc, int npalf);
542 int rvu_npa_aq_enq_inst(struct rvu *rvu, struct npa_aq_enq_req *req,
543 struct npa_aq_enq_rsp *rsp);
546 bool is_nixlf_attached(struct rvu *rvu, u16 pcifunc);
547 int rvu_nix_init(struct rvu *rvu);
548 int rvu_nix_reserve_mark_format(struct rvu *rvu, struct nix_hw *nix_hw,
549 int blkaddr, u32 cfg);
550 void rvu_nix_freemem(struct rvu *rvu);
551 int rvu_get_nixlf_count(struct rvu *rvu);
552 void rvu_nix_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int npalf);
553 int nix_get_nixlf(struct rvu *rvu, u16 pcifunc, int *nixlf, int *nix_blkaddr);
554 int nix_update_bcast_mce_list(struct rvu *rvu, u16 pcifunc, bool add);
555 struct nix_hw *get_nix_hw(struct rvu_hwinfo *hw, int blkaddr);
556 int rvu_get_next_nix_blkaddr(struct rvu *rvu, int blkaddr);
557 void rvu_nix_reset_mac(struct rvu_pfvf *pfvf, int pcifunc);
560 int rvu_npc_init(struct rvu *rvu);
561 void rvu_npc_freemem(struct rvu *rvu);
562 int rvu_npc_get_pkind(struct rvu *rvu, u16 pf);
563 void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf);
564 int npc_config_ts_kpuaction(struct rvu *rvu, int pf, u16 pcifunc, bool en);
565 void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc,
566 int nixlf, u64 chan, u8 *mac_addr);
567 void rvu_npc_install_promisc_entry(struct rvu *rvu, u16 pcifunc,
568 int nixlf, u64 chan, bool allmulti);
569 void rvu_npc_disable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf);
570 void rvu_npc_enable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf);
571 void rvu_npc_install_bcast_match_entry(struct rvu *rvu, u16 pcifunc,
572 int nixlf, u64 chan);
573 void rvu_npc_enable_bcast_entry(struct rvu *rvu, u16 pcifunc, bool enable);
574 int rvu_npc_update_rxvlan(struct rvu *rvu, u16 pcifunc, int nixlf);
575 void rvu_npc_disable_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
576 void rvu_npc_free_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
577 void rvu_npc_disable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
578 void rvu_npc_enable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
579 void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu, u16 pcifunc, int nixlf,
580 int group, int alg_idx, int mcam_index);
581 void rvu_npc_get_mcam_entry_alloc_info(struct rvu *rvu, u16 pcifunc,
582 int blkaddr, int *alloc_cnt,
584 void rvu_npc_get_mcam_counter_alloc_info(struct rvu *rvu, u16 pcifunc,
585 int blkaddr, int *alloc_cnt,
587 bool is_npc_intf_tx(u8 intf);
588 bool is_npc_intf_rx(u8 intf);
589 bool is_npc_interface_valid(struct rvu *rvu, u8 intf);
590 int rvu_npc_get_tx_nibble_cfg(struct rvu *rvu, u64 nibble_ena);
591 int npc_mcam_verify_channel(struct rvu *rvu, u16 pcifunc, u8 intf, u16 channel);
592 int npc_flow_steering_init(struct rvu *rvu, int blkaddr);
593 const char *npc_get_field_name(u8 hdr);
594 bool rvu_npc_write_default_rule(struct rvu *rvu, int blkaddr, int nixlf,
595 u16 pcifunc, u8 intf, struct mcam_entry *entry,
597 int npc_get_bank(struct npc_mcam *mcam, int index);
598 void npc_mcam_enable_flows(struct rvu *rvu, u16 target);
599 void npc_mcam_disable_flows(struct rvu *rvu, u16 target);
600 void npc_enable_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
601 int blkaddr, int index, bool enable);
602 void npc_read_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
603 int blkaddr, u16 src, struct mcam_entry *entry,
606 #ifdef CONFIG_DEBUG_FS
607 void rvu_dbg_init(struct rvu *rvu);
608 void rvu_dbg_exit(struct rvu *rvu);
610 static inline void rvu_dbg_init(struct rvu *rvu) {}
611 static inline void rvu_dbg_exit(struct rvu *rvu) {}