1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Marvell OcteonTx2 RVU Admin Function driver
4 * Copyright (C) 2018 Marvell International Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
14 #include <linux/pci.h>
15 #include "rvu_struct.h"
20 #define PCI_DEVID_OCTEONTX2_RVU_AF 0xA065
22 /* Subsystem Device ID */
23 #define PCI_SUBSYS_DEVID_96XX 0xB200
26 #define PCI_AF_REG_BAR_NUM 0
27 #define PCI_PF_REG_BAR_NUM 2
28 #define PCI_MBOX_BAR_NUM 4
33 #define RVU_PFVF_PF_SHIFT 10
34 #define RVU_PFVF_PF_MASK 0x3F
35 #define RVU_PFVF_FUNC_SHIFT 0
36 #define RVU_PFVF_FUNC_MASK 0x3FF
38 #ifdef CONFIG_DEBUG_FS
47 struct dentry *cgx_root;
53 struct dump_ctx npa_aura_ctx;
54 struct dump_ctx npa_pool_ctx;
55 struct dump_ctx nix_cq_ctx;
56 struct dump_ctx nix_rq_ctx;
57 struct dump_ctx nix_sq_ctx;
64 struct work_struct work;
71 unsigned long *bmap; /* Pointer to resource bitmap */
72 u16 max; /* Max resource id or count */
77 struct admin_queue *aq; /* NIX/NPA AQ */
78 u16 *fn_map; /* LF to pcifunc mapping */
81 u8 addr; /* RVU_BLOCK_ADDR_E */
82 u8 type; /* RVU_BLOCK_TYPE_E */
90 unsigned char name[NAME_SIZE];
95 struct qmem *mcast_buf;
98 struct mutex mce_lock; /* Serialize MCE updates */
101 struct nix_mce_list {
102 struct hlist_head head;
108 struct rsrc_bmap counters;
109 struct mutex lock; /* MCAM entries and counters update lock */
110 unsigned long *bmap; /* bitmap, 0 => bmap_entries */
111 unsigned long *bmap_reverse; /* Reverse bitmap, bmap_entries => 0 */
112 u16 bmap_entries; /* Number of unreserved MCAM entries */
113 u16 bmap_fcnt; /* MCAM entries free count */
118 u8 keysize; /* MCAM keysize 112/224/448 bits */
119 u8 banks; /* Number of MCAM banks */
120 u8 banks_per_entry;/* Number of keywords in key */
121 u16 banksize; /* Number of MCAM entries in each bank */
122 u16 total_entries; /* Total number of MCAM entries */
123 u16 nixlf_offset; /* Offset of nixlf rsvd uncast entries */
124 u16 pf_offset; /* Offset of PF's rsvd bcast, promisc entries */
129 u16 rx_miss_act_cntr; /* Counter for RX MISS action */
132 /* Structure for per RVU func info ie PF/VF */
134 bool npalf; /* Only one NPALF per RVU_FUNC */
135 bool nixlf; /* Only one NIXLF per RVU_FUNC */
142 /* Block LF's MSIX vector info */
143 struct rsrc_bmap msix; /* Bitmap for MSIX vector alloc */
144 #define MSIX_BLKLF(blkaddr, lf) (((blkaddr) << 8) | ((lf) & 0xFF))
145 u16 *msix_lfmap; /* Vector to block LF mapping */
148 struct qmem *aura_ctx;
149 struct qmem *pool_ctx;
150 struct qmem *npa_qints_ctx;
151 unsigned long *aura_bmap;
152 unsigned long *pool_bmap;
158 struct qmem *rss_ctx;
159 struct qmem *cq_ints_ctx;
160 struct qmem *nix_qints_ctx;
161 unsigned long *sq_bmap;
162 unsigned long *rq_bmap;
163 unsigned long *cq_bmap;
167 u8 rx_chan_cnt; /* total number of RX channels */
168 u8 tx_chan_cnt; /* total number of TX channels */
172 u8 mac_addr[ETH_ALEN]; /* MAC address of this PF/VF */
174 /* Broadcast pkt replication info */
176 struct nix_mce_list bcast_mce_list;
179 struct mcam_entry entry;
183 bool cgx_in_use; /* this PF/VF using CGX? */
184 int cgx_users; /* number of cgx users - used only by PFs */
188 struct rsrc_bmap schq;
190 #define NIX_TXSCHQ_FREE BIT_ULL(1)
191 #define NIX_TXSCHQ_CFG_DONE BIT_ULL(0)
192 #define TXSCH_MAP_FUNC(__pfvf_map) ((__pfvf_map) & 0xFFFF)
193 #define TXSCH_MAP_FLAGS(__pfvf_map) ((__pfvf_map) >> 16)
194 #define TXSCH_MAP(__func, __flags) (((__func) & 0xFFFF) | ((__flags) << 16))
195 #define TXSCH_SET_FLAG(__pfvf_map, flag) ((__pfvf_map) | ((flag) << 16))
199 struct nix_mark_format {
206 struct rsrc_bmap rsrc;
211 #define NIX_FLOW_KEY_ALG_MAX 32
212 u32 flowkey[NIX_FLOW_KEY_ALG_MAX];
222 struct nix_txsch txsch[NIX_TXSCH_LVL_CNT]; /* Tx schedulers */
223 struct nix_mcast mcast;
224 struct nix_flowkey flowkey;
225 struct nix_mark_format mark_format;
229 /* RVU block's capabilities or functionality,
230 * which vary by silicon version/skew.
233 /* Transmit side supported functionality */
234 u8 nix_tx_aggr_lvl; /* Tx link's traffic aggregation level */
235 u16 nix_txsch_per_cgx_lmac; /* Max Q's transmitting to CGX LMAC */
236 u16 nix_txsch_per_lbk_lmac; /* Max Q's transmitting to LBK LMAC */
237 u16 nix_txsch_per_sdp_lmac; /* Max Q's transmitting to SDP LMAC */
238 bool nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */
239 bool nix_shaping; /* Is shaping and coloring supported */
240 bool nix_tx_link_bp; /* Can link backpressure TL queues ? */
241 bool nix_rx_multicast; /* Rx packet replication support */
245 u8 total_pfs; /* MAX RVU PFs HW supports */
246 u16 total_vfs; /* Max RVU VFs HW supports */
247 u16 max_vfs_per_pf; /* Max VFs that can be attached to a PF */
253 u8 npc_kpus; /* No of parser units */
256 struct rvu_block block[BLK_COUNT]; /* Block info */
258 struct npc_pkind pkind;
259 struct npc_mcam mcam;
262 struct mbox_wq_info {
263 struct otx2_mbox mbox;
264 struct rvu_work *mbox_wrk;
266 struct otx2_mbox mbox_up;
267 struct rvu_work *mbox_wrk_up;
269 struct workqueue_struct *mbox_wq;
273 #define RVU_FWDATA_HEADER_MAGIC 0xCFDA /* Custom Firmware Data*/
274 #define RVU_FWDATA_VERSION 0x0001
276 u32 version; /* version id */
279 #define PF_MACNUM_MAX 32
280 #define VF_MACNUM_MAX 256
281 u64 pf_macs[PF_MACNUM_MAX];
282 u64 vf_macs[VF_MACNUM_MAX];
288 #define FWDATA_RESERVED_MEM 1023
289 u64 reserved[FWDATA_RESERVED_MEM];
294 /* KPU profile adapter structure gathering all KPU configuration data and abstracting out the
295 * source where it came from.
297 struct npc_kpu_profile_adapter {
300 const struct npc_lt_def_cfg *lt_def;
301 const struct npc_kpu_profile_action *ikpu; /* array[pkinds] */
302 const struct npc_kpu_profile *kpu; /* array[kpus] */
303 const struct npc_mcam_kex *mkex;
309 void __iomem *afreg_base;
310 void __iomem *pfreg_base;
311 struct pci_dev *pdev;
313 struct rvu_hwinfo *hw;
315 struct rvu_pfvf *hwvf;
316 struct mutex rsrc_lock; /* Serialize resource alloc/free */
317 int vfs; /* Number of VFs attached to RVU */
320 struct mbox_wq_info afpf_wq_info;
321 struct mbox_wq_info afvf_wq_info;
324 struct rvu_work *flr_wrk;
325 struct workqueue_struct *flr_wq;
326 struct mutex flr_lock; /* Serialize FLRs */
332 dma_addr_t msix_base_iova;
333 u64 msixtr_base_phy; /* Register reset value */
336 #define PF_CGXMAP_BASE 1 /* PF 0 is reserved for RVU PF */
338 u8 cgx_cnt_max; /* CGX port count max */
339 u8 *pf2cgxlmac_map; /* pf to cgx_lmac map */
340 u16 *cgxlmac2pf_map; /* bitmap of mapped pfs for
341 * every cgx lmac port
343 unsigned long pf_notify_bmap; /* Flags for PF notification */
344 void **cgx_idmap; /* cgx id to cgx data map table */
345 struct work_struct cgx_evh_work;
346 struct workqueue_struct *cgx_evh_wq;
347 spinlock_t cgx_evq_lock; /* cgx event queue lock */
348 struct list_head cgx_evq_head; /* cgx event queue head */
349 struct mutex cgx_cfg_lock; /* serialize cgx configuration */
351 char mkex_pfl_name[MKEX_NAME_LEN]; /* Configured MKEX profile name */
354 struct rvu_fwdata *fwdata;
357 struct npc_kpu_profile_adapter kpu;
361 #ifdef CONFIG_DEBUG_FS
362 struct rvu_debugfs rvu_dbg;
366 static inline void rvu_write64(struct rvu *rvu, u64 block, u64 offset, u64 val)
368 writeq(val, rvu->afreg_base + ((block << 28) | offset));
371 static inline u64 rvu_read64(struct rvu *rvu, u64 block, u64 offset)
373 return readq(rvu->afreg_base + ((block << 28) | offset));
376 static inline void rvupf_write64(struct rvu *rvu, u64 offset, u64 val)
378 writeq(val, rvu->pfreg_base + offset);
381 static inline u64 rvupf_read64(struct rvu *rvu, u64 offset)
383 return readq(rvu->pfreg_base + offset);
386 /* Silicon revisions */
387 static inline bool is_rvu_96xx_A0(struct rvu *rvu)
389 struct pci_dev *pdev = rvu->pdev;
391 return (pdev->revision == 0x00) &&
392 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX);
395 static inline bool is_rvu_96xx_B0(struct rvu *rvu)
397 struct pci_dev *pdev = rvu->pdev;
399 return ((pdev->revision == 0x00) || (pdev->revision == 0x01)) &&
400 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX);
403 /* Function Prototypes
406 static inline int is_afvf(u16 pcifunc)
408 return !(pcifunc & ~RVU_PFVF_FUNC_MASK);
411 static inline bool is_rvu_fwdata_valid(struct rvu *rvu)
413 return (rvu->fwdata->header_magic == RVU_FWDATA_HEADER_MAGIC) &&
414 (rvu->fwdata->version == RVU_FWDATA_VERSION);
417 int rvu_alloc_bitmap(struct rsrc_bmap *rsrc);
418 int rvu_alloc_rsrc(struct rsrc_bmap *rsrc);
419 void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id);
420 int rvu_rsrc_free_count(struct rsrc_bmap *rsrc);
421 int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc);
422 bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc);
423 int rvu_get_pf(u16 pcifunc);
424 struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc);
425 void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf);
426 bool is_block_implemented(struct rvu_hwinfo *hw, int blkaddr);
427 bool is_pffunc_map_valid(struct rvu *rvu, u16 pcifunc, int blktype);
428 int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot);
429 int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block, int lf);
430 int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc);
431 int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero);
433 /* RVU HW reg validation */
439 bool rvu_check_valid_reg(int regmap, int regblk, u64 reg);
441 /* NPA/NIX AQ APIs */
442 int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue,
443 int qsize, int inst_size, int res_size);
444 void rvu_aq_free(struct rvu *rvu, struct admin_queue *aq);
447 static inline bool is_pf_cgxmapped(struct rvu *rvu, u8 pf)
449 return (pf >= PF_CGXMAP_BASE && pf <= rvu->cgx_mapped_pfs);
452 static inline void rvu_get_cgx_lmac_id(u8 map, u8 *cgx_id, u8 *lmac_id)
454 *cgx_id = (map >> 4) & 0xF;
455 *lmac_id = (map & 0xF);
458 #define M(_name, _id, fn_name, req, rsp) \
459 int rvu_mbox_handler_ ## fn_name(struct rvu *, struct req *, struct rsp *);
463 int rvu_cgx_init(struct rvu *rvu);
464 int rvu_cgx_exit(struct rvu *rvu);
465 void *rvu_cgx_pdata(u8 cgx_id, struct rvu *rvu);
466 int rvu_cgx_config_rxtx(struct rvu *rvu, u16 pcifunc, bool start);
467 void rvu_cgx_enadis_rx_bp(struct rvu *rvu, int pf, bool enable);
468 int rvu_cgx_start_stop_io(struct rvu *rvu, u16 pcifunc, bool start);
469 int rvu_cgx_nix_cuml_stats(struct rvu *rvu, void *cgxd, int lmac_id, int index,
470 int rxtxflag, u64 *stat);
472 int rvu_npa_init(struct rvu *rvu);
473 void rvu_npa_freemem(struct rvu *rvu);
474 void rvu_npa_lf_teardown(struct rvu *rvu, u16 pcifunc, int npalf);
475 int rvu_npa_aq_enq_inst(struct rvu *rvu, struct npa_aq_enq_req *req,
476 struct npa_aq_enq_rsp *rsp);
479 bool is_nixlf_attached(struct rvu *rvu, u16 pcifunc);
480 int rvu_nix_init(struct rvu *rvu);
481 int rvu_nix_reserve_mark_format(struct rvu *rvu, struct nix_hw *nix_hw,
482 int blkaddr, u32 cfg);
483 void rvu_nix_freemem(struct rvu *rvu);
484 int rvu_get_nixlf_count(struct rvu *rvu);
485 void rvu_nix_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int npalf);
486 int nix_get_nixlf(struct rvu *rvu, u16 pcifunc, int *nixlf, int *nix_blkaddr);
487 int nix_update_bcast_mce_list(struct rvu *rvu, u16 pcifunc, bool add);
490 int rvu_npc_init(struct rvu *rvu);
491 void rvu_npc_freemem(struct rvu *rvu);
492 int rvu_npc_get_pkind(struct rvu *rvu, u16 pf);
493 void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf);
494 int npc_config_ts_kpuaction(struct rvu *rvu, int pf, u16 pcifunc, bool en);
495 void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc,
496 int nixlf, u64 chan, u8 *mac_addr);
497 void rvu_npc_install_promisc_entry(struct rvu *rvu, u16 pcifunc,
498 int nixlf, u64 chan, bool allmulti);
499 void rvu_npc_disable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf);
500 void rvu_npc_enable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf);
501 void rvu_npc_install_bcast_match_entry(struct rvu *rvu, u16 pcifunc,
502 int nixlf, u64 chan);
503 void rvu_npc_enable_bcast_entry(struct rvu *rvu, u16 pcifunc, bool enable);
504 int rvu_npc_update_rxvlan(struct rvu *rvu, u16 pcifunc, int nixlf);
505 void rvu_npc_disable_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
506 void rvu_npc_disable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
507 void rvu_npc_enable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
508 void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu, u16 pcifunc, int nixlf,
509 int group, int alg_idx, int mcam_index);
510 void rvu_npc_get_mcam_entry_alloc_info(struct rvu *rvu, u16 pcifunc,
511 int blkaddr, int *alloc_cnt,
513 void rvu_npc_get_mcam_counter_alloc_info(struct rvu *rvu, u16 pcifunc,
514 int blkaddr, int *alloc_cnt,
517 #ifdef CONFIG_DEBUG_FS
518 void rvu_dbg_init(struct rvu *rvu);
519 void rvu_dbg_exit(struct rvu *rvu);
521 static inline void rvu_dbg_init(struct rvu *rvu) {}
522 static inline void rvu_dbg_exit(struct rvu *rvu) {}