drivers/net/ethernet/marvell/octeontx2/af/rvu.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Marvell RVU Admin Function driver
   3  *
   4  * Copyright (C) 2018 Marvell.
   5  *
   6  */
   7
   8 #include <linux/module.h>
   9 #include <linux/interrupt.h>
  10 #include <linux/delay.h>
  11 #include <linux/irq.h>
  12 #include <linux/pci.h>
  13 #include <linux/sysfs.h>
  14
  15 #include "cgx.h"
  16 #include "rvu.h"
  17 #include "rvu_reg.h"
  18 #include "ptp.h"
  19
  20 #include "rvu_trace.h"
  21
  22 #define DRV_NAME        "rvu_af"
  23 #define DRV_STRING      "Marvell OcteonTX2 RVU Admin Function Driver"
  24
  25 static int rvu_get_hwvf(struct rvu *rvu, int pcifunc);
  26
  27 static void rvu_set_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf,
  28                                 struct rvu_block *block, int lf);
  29 static void rvu_clear_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf,
  30                                   struct rvu_block *block, int lf);
  31 static void __rvu_flr_handler(struct rvu *rvu, u16 pcifunc);
  32
  33 static int rvu_mbox_init(struct rvu *rvu, struct mbox_wq_info *mw,
  34                          int type, int num,
  35                          void (mbox_handler)(struct work_struct *),
  36                          void (mbox_up_handler)(struct work_struct *));
  37 enum {
  38         TYPE_AFVF,
  39         TYPE_AFPF,
  40 };
  41
  42 /* Supported devices */
  43 static const struct pci_device_id rvu_id_table[] = {
  44         { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_AF) },
  45         { 0, }  /* end of table */
  46 };
  47
  48 MODULE_AUTHOR("Sunil Goutham <sgoutham@marvell.com>");
  49 MODULE_DESCRIPTION(DRV_STRING);
  50 MODULE_LICENSE("GPL v2");
  51 MODULE_DEVICE_TABLE(pci, rvu_id_table);
  52
  53 static char *mkex_profile; /* MKEX profile name */
  54 module_param(mkex_profile, charp, 0000);
  55 MODULE_PARM_DESC(mkex_profile, "MKEX profile name string");
  56
  57 static char *kpu_profile; /* KPU profile name */
  58 module_param(kpu_profile, charp, 0000);
  59 MODULE_PARM_DESC(kpu_profile, "KPU profile name string");
  60
  61 static void rvu_setup_hw_capabilities(struct rvu *rvu)
  62 {
  63         struct rvu_hwinfo *hw = rvu->hw;
  64
  65         hw->cap.nix_tx_aggr_lvl = NIX_TXSCH_LVL_TL1;
  66         hw->cap.nix_fixed_txschq_mapping = false;
  67         hw->cap.nix_shaping = true;
  68         hw->cap.nix_tx_link_bp = true;
  69         hw->cap.nix_rx_multicast = true;
  70         hw->cap.nix_shaper_toggle_wait = false;
  71         hw->rvu = rvu;
  72
  73         if (is_rvu_pre_96xx_C0(rvu)) {
  74                 hw->cap.nix_fixed_txschq_mapping = true;
  75                 hw->cap.nix_txsch_per_cgx_lmac = 4;
  76                 hw->cap.nix_txsch_per_lbk_lmac = 132;
  77                 hw->cap.nix_txsch_per_sdp_lmac = 76;
  78                 hw->cap.nix_shaping = false;
  79                 hw->cap.nix_tx_link_bp = false;
  80                 if (is_rvu_96xx_A0(rvu) || is_rvu_95xx_A0(rvu))
  81                         hw->cap.nix_rx_multicast = false;
  82         }
  83         if (!is_rvu_pre_96xx_C0(rvu))
  84                 hw->cap.nix_shaper_toggle_wait = true;
  85
  86         if (!is_rvu_otx2(rvu))
  87                 hw->cap.per_pf_mbox_regs = true;
  88 }
  89
  90 /* Poll a RVU block's register 'offset', for a 'zero'
  91  * or 'nonzero' at bits specified by 'mask'
  92  */
  93 int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero)
  94 {
  95         unsigned long timeout = jiffies + usecs_to_jiffies(20000);
  96         bool twice = false;
  97         void __iomem *reg;
  98         u64 reg_val;
  99
 100         reg = rvu->afreg_base + ((block << 28) | offset);
 101 again:
 102         reg_val = readq(reg);
 103         if (zero && !(reg_val & mask))
 104                 return 0;
 105         if (!zero && (reg_val & mask))
 106                 return 0;
 107         if (time_before(jiffies, timeout)) {
 108                 usleep_range(1, 5);
 109                 goto again;
 110         }
 111         /* In scenarios where CPU is scheduled out before checking
 112          * 'time_before' (above) and gets scheduled in such that
 113          * jiffies are beyond timeout value, then check again if HW is
 114          * done with the operation in the meantime.
 115          */
 116         if (!twice) {
 117                 twice = true;
 118                 goto again;
 119         }
 120         return -EBUSY;
 121 }
 122
 123 int rvu_alloc_rsrc(struct rsrc_bmap *rsrc)
 124 {
 125         int id;
 126
 127         if (!rsrc->bmap)
 128                 return -EINVAL;
 129
 130         id = find_first_zero_bit(rsrc->bmap, rsrc->max);
 131         if (id >= rsrc->max)
 132                 return -ENOSPC;
 133
 134         __set_bit(id, rsrc->bmap);
 135
 136         return id;
 137 }
 138
 139 int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc)
 140 {
 141         int start;
 142
 143         if (!rsrc->bmap)
 144                 return -EINVAL;
 145
 146         start = bitmap_find_next_zero_area(rsrc->bmap, rsrc->max, 0, nrsrc, 0);
 147         if (start >= rsrc->max)
 148                 return -ENOSPC;
 149
 150         bitmap_set(rsrc->bmap, start, nrsrc);
 151         return start;
 152 }
 153
 154 static void rvu_free_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc, int start)
 155 {
 156         if (!rsrc->bmap)
 157                 return;
 158         if (start >= rsrc->max)
 159                 return;
 160
 161         bitmap_clear(rsrc->bmap, start, nrsrc);
 162 }
 163
 164 bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc)
 165 {
 166         int start;
 167
 168         if (!rsrc->bmap)
 169                 return false;
 170
 171         start = bitmap_find_next_zero_area(rsrc->bmap, rsrc->max, 0, nrsrc, 0);
 172         if (start >= rsrc->max)
 173                 return false;
 174
 175         return true;
 176 }
 177
 178 void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id)
 179 {
 180         if (!rsrc->bmap)
 181                 return;
 182
 183         __clear_bit(id, rsrc->bmap);
 184 }
 185
 186 int rvu_rsrc_free_count(struct rsrc_bmap *rsrc)
 187 {
 188         int used;
 189
 190         if (!rsrc->bmap)
 191                 return 0;
 192
 193         used = bitmap_weight(rsrc->bmap, rsrc->max);
 194         return (rsrc->max - used);
 195 }
 196
 197 bool is_rsrc_free(struct rsrc_bmap *rsrc, int id)
 198 {
 199         if (!rsrc->bmap)
 200                 return false;
 201
 202         return !test_bit(id, rsrc->bmap);
 203 }
 204
 205 int rvu_alloc_bitmap(struct rsrc_bmap *rsrc)
 206 {
 207         rsrc->bmap = kcalloc(BITS_TO_LONGS(rsrc->max),
 208                              sizeof(long), GFP_KERNEL);
 209         if (!rsrc->bmap)
 210                 return -ENOMEM;
 211         return 0;
 212 }
 213
 214 void rvu_free_bitmap(struct rsrc_bmap *rsrc)
 215 {
 216         kfree(rsrc->bmap);
 217 }
 218
 219 /* Get block LF's HW index from a PF_FUNC's block slot number */
 220 int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot)
 221 {
 222         u16 match = 0;
 223         int lf;
 224
 225         mutex_lock(&rvu->rsrc_lock);
 226         for (lf = 0; lf < block->lf.max; lf++) {
 227                 if (block->fn_map[lf] == pcifunc) {
 228                         if (slot == match) {
 229                                 mutex_unlock(&rvu->rsrc_lock);
 230                                 return lf;
 231                         }
 232                         match++;
 233                 }
 234         }
 235         mutex_unlock(&rvu->rsrc_lock);
 236         return -ENODEV;
 237 }
 238
 239 /* Convert BLOCK_TYPE_E to a BLOCK_ADDR_E.
 240  * Some silicon variants of OcteonTX2 supports
 241  * multiple blocks of same type.
 242  *
 243  * @pcifunc has to be zero when no LF is yet attached.
 244  *
 245  * For a pcifunc if LFs are attached from multiple blocks of same type, then
 246  * return blkaddr of first encountered block.
 247  */
 248 int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc)
 249 {
 250         int devnum, blkaddr = -ENODEV;
 251         u64 cfg, reg;
 252         bool is_pf;
 253
 254         switch (blktype) {
 255         case BLKTYPE_NPC:
 256                 blkaddr = BLKADDR_NPC;
 257                 goto exit;
 258         case BLKTYPE_NPA:
 259                 blkaddr = BLKADDR_NPA;
 260                 goto exit;
 261         case BLKTYPE_NIX:
 262                 /* For now assume NIX0 */
 263                 if (!pcifunc) {
 264                         blkaddr = BLKADDR_NIX0;
 265                         goto exit;
 266                 }
 267                 break;
 268         case BLKTYPE_SSO:
 269                 blkaddr = BLKADDR_SSO;
 270                 goto exit;
 271         case BLKTYPE_SSOW:
 272                 blkaddr = BLKADDR_SSOW;
 273                 goto exit;
 274         case BLKTYPE_TIM:
 275                 blkaddr = BLKADDR_TIM;
 276                 goto exit;
 277         case BLKTYPE_CPT:
 278                 /* For now assume CPT0 */
 279                 if (!pcifunc) {
 280                         blkaddr = BLKADDR_CPT0;
 281                         goto exit;
 282                 }
 283                 break;
 284         }
 285
 286         /* Check if this is a RVU PF or VF */
 287         if (pcifunc & RVU_PFVF_FUNC_MASK) {
 288                 is_pf = false;
 289                 devnum = rvu_get_hwvf(rvu, pcifunc);
 290         } else {
 291                 is_pf = true;
 292                 devnum = rvu_get_pf(pcifunc);
 293         }
 294
 295         /* Check if the 'pcifunc' has a NIX LF from 'BLKADDR_NIX0' or
 296          * 'BLKADDR_NIX1'.
 297          */
 298         if (blktype == BLKTYPE_NIX) {
 299                 reg = is_pf ? RVU_PRIV_PFX_NIXX_CFG(0) :
 300                         RVU_PRIV_HWVFX_NIXX_CFG(0);
 301                 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16));
 302                 if (cfg) {
 303                         blkaddr = BLKADDR_NIX0;
 304                         goto exit;
 305                 }
 306
 307                 reg = is_pf ? RVU_PRIV_PFX_NIXX_CFG(1) :
 308                         RVU_PRIV_HWVFX_NIXX_CFG(1);
 309                 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16));
 310                 if (cfg)
 311                         blkaddr = BLKADDR_NIX1;
 312         }
 313
 314         if (blktype == BLKTYPE_CPT) {
 315                 reg = is_pf ? RVU_PRIV_PFX_CPTX_CFG(0) :
 316                         RVU_PRIV_HWVFX_CPTX_CFG(0);
 317                 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16));
 318                 if (cfg) {
 319                         blkaddr = BLKADDR_CPT0;
 320                         goto exit;
 321                 }
 322
 323                 reg = is_pf ? RVU_PRIV_PFX_CPTX_CFG(1) :
 324                         RVU_PRIV_HWVFX_CPTX_CFG(1);
 325                 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16));
 326                 if (cfg)
 327                         blkaddr = BLKADDR_CPT1;
 328         }
 329
 330 exit:
 331         if (is_block_implemented(rvu->hw, blkaddr))
 332                 return blkaddr;
 333         return -ENODEV;
 334 }
 335
 336 static void rvu_update_rsrc_map(struct rvu *rvu, struct rvu_pfvf *pfvf,
 337                                 struct rvu_block *block, u16 pcifunc,
 338                                 u16 lf, bool attach)
 339 {
 340         int devnum, num_lfs = 0;
 341         bool is_pf;
 342         u64 reg;
 343
 344         if (lf >= block->lf.max) {
 345                 dev_err(&rvu->pdev->dev,
 346                         "%s: FATAL: LF %d is >= %s's max lfs i.e %d\n",
 347                         __func__, lf, block->name, block->lf.max);
 348                 return;
 349         }
 350
 351         /* Check if this is for a RVU PF or VF */
 352         if (pcifunc & RVU_PFVF_FUNC_MASK) {
 353                 is_pf = false;
 354                 devnum = rvu_get_hwvf(rvu, pcifunc);
 355         } else {
 356                 is_pf = true;
 357                 devnum = rvu_get_pf(pcifunc);
 358         }
 359
 360         block->fn_map[lf] = attach ? pcifunc : 0;
 361
 362         switch (block->addr) {
 363         case BLKADDR_NPA:
 364                 pfvf->npalf = attach ? true : false;
 365                 num_lfs = pfvf->npalf;
 366                 break;
 367         case BLKADDR_NIX0:
 368         case BLKADDR_NIX1:
 369                 pfvf->nixlf = attach ? true : false;
 370                 num_lfs = pfvf->nixlf;
 371                 break;
 372         case BLKADDR_SSO:
 373                 attach ? pfvf->sso++ : pfvf->sso--;
 374                 num_lfs = pfvf->sso;
 375                 break;
 376         case BLKADDR_SSOW:
 377                 attach ? pfvf->ssow++ : pfvf->ssow--;
 378                 num_lfs = pfvf->ssow;
 379                 break;
 380         case BLKADDR_TIM:
 381                 attach ? pfvf->timlfs++ : pfvf->timlfs--;
 382                 num_lfs = pfvf->timlfs;
 383                 break;
 384         case BLKADDR_CPT0:
 385                 attach ? pfvf->cptlfs++ : pfvf->cptlfs--;
 386                 num_lfs = pfvf->cptlfs;
 387                 break;
 388         case BLKADDR_CPT1:
 389                 attach ? pfvf->cpt1_lfs++ : pfvf->cpt1_lfs--;
 390                 num_lfs = pfvf->cpt1_lfs;
 391                 break;
 392         }
 393
 394         reg = is_pf ? block->pf_lfcnt_reg : block->vf_lfcnt_reg;
 395         rvu_write64(rvu, BLKADDR_RVUM, reg | (devnum << 16), num_lfs);
 396 }
 397
 398 inline int rvu_get_pf(u16 pcifunc)
 399 {
 400         return (pcifunc >> RVU_PFVF_PF_SHIFT) & RVU_PFVF_PF_MASK;
 401 }
 402
 403 void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf)
 404 {
 405         u64 cfg;
 406
 407         /* Get numVFs attached to this PF and first HWVF */
 408         cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf));
 409         if (numvfs)
 410                 *numvfs = (cfg >> 12) & 0xFF;
 411         if (hwvf)
 412                 *hwvf = cfg & 0xFFF;
 413 }
 414
 415 static int rvu_get_hwvf(struct rvu *rvu, int pcifunc)
 416 {
 417         int pf, func;
 418         u64 cfg;
 419
 420         pf = rvu_get_pf(pcifunc);
 421         func = pcifunc & RVU_PFVF_FUNC_MASK;
 422
 423         /* Get first HWVF attached to this PF */
 424         cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf));
 425
 426         return ((cfg & 0xFFF) + func - 1);
 427 }
 428
 429 struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc)
 430 {
 431         /* Check if it is a PF or VF */
 432         if (pcifunc & RVU_PFVF_FUNC_MASK)
 433                 return &rvu->hwvf[rvu_get_hwvf(rvu, pcifunc)];
 434         else
 435                 return &rvu->pf[rvu_get_pf(pcifunc)];
 436 }
 437
 438 static bool is_pf_func_valid(struct rvu *rvu, u16 pcifunc)
 439 {
 440         int pf, vf, nvfs;
 441         u64 cfg;
 442
 443         pf = rvu_get_pf(pcifunc);
 444         if (pf >= rvu->hw->total_pfs)
 445                 return false;
 446
 447         if (!(pcifunc & RVU_PFVF_FUNC_MASK))
 448                 return true;
 449
 450         /* Check if VF is within number of VFs attached to this PF */
 451         vf = (pcifunc & RVU_PFVF_FUNC_MASK) - 1;
 452         cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf));
 453         nvfs = (cfg >> 12) & 0xFF;
 454         if (vf >= nvfs)
 455                 return false;
 456
 457         return true;
 458 }
 459
 460 bool is_block_implemented(struct rvu_hwinfo *hw, int blkaddr)
 461 {
 462         struct rvu_block *block;
 463
 464         if (blkaddr < BLKADDR_RVUM || blkaddr >= BLK_COUNT)
 465                 return false;
 466
 467         block = &hw->block[blkaddr];
 468         return block->implemented;
 469 }
 470
 471 static void rvu_check_block_implemented(struct rvu *rvu)
 472 {
 473         struct rvu_hwinfo *hw = rvu->hw;
 474         struct rvu_block *block;
 475         int blkid;
 476         u64 cfg;
 477
 478         /* For each block check if 'implemented' bit is set */
 479         for (blkid = 0; blkid < BLK_COUNT; blkid++) {
 480                 block = &hw->block[blkid];
 481                 cfg = rvupf_read64(rvu, RVU_PF_BLOCK_ADDRX_DISC(blkid));
 482                 if (cfg & BIT_ULL(11))
 483                         block->implemented = true;
 484         }
 485 }
 486
 487 static void rvu_setup_rvum_blk_revid(struct rvu *rvu)
 488 {
 489         rvu_write64(rvu, BLKADDR_RVUM,
 490                     RVU_PRIV_BLOCK_TYPEX_REV(BLKTYPE_RVUM),
 491                     RVU_BLK_RVUM_REVID);
 492 }
 493
 494 static void rvu_clear_rvum_blk_revid(struct rvu *rvu)
 495 {
 496         rvu_write64(rvu, BLKADDR_RVUM,
 497                     RVU_PRIV_BLOCK_TYPEX_REV(BLKTYPE_RVUM), 0x00);
 498 }
 499
 500 int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block, int lf)
 501 {
 502         int err;
 503
 504         if (!block->implemented)
 505                 return 0;
 506
 507         rvu_write64(rvu, block->addr, block->lfreset_reg, lf | BIT_ULL(12));
 508         err = rvu_poll_reg(rvu, block->addr, block->lfreset_reg, BIT_ULL(12),
 509                            true);
 510         return err;
 511 }
 512
 513 static void rvu_block_reset(struct rvu *rvu, int blkaddr, u64 rst_reg)
 514 {
 515         struct rvu_block *block = &rvu->hw->block[blkaddr];
 516         int err;
 517
 518         if (!block->implemented)
 519                 return;
 520
 521         rvu_write64(rvu, blkaddr, rst_reg, BIT_ULL(0));
 522         err = rvu_poll_reg(rvu, blkaddr, rst_reg, BIT_ULL(63), true);
 523         if (err)
 524                 dev_err(rvu->dev, "HW block:%d reset failed\n", blkaddr);
 525 }
 526
 527 static void rvu_reset_all_blocks(struct rvu *rvu)
 528 {
 529         /* Do a HW reset of all RVU blocks */
 530         rvu_block_reset(rvu, BLKADDR_NPA, NPA_AF_BLK_RST);
 531         rvu_block_reset(rvu, BLKADDR_NIX0, NIX_AF_BLK_RST);
 532         rvu_block_reset(rvu, BLKADDR_NIX1, NIX_AF_BLK_RST);
 533         rvu_block_reset(rvu, BLKADDR_NPC, NPC_AF_BLK_RST);
 534         rvu_block_reset(rvu, BLKADDR_SSO, SSO_AF_BLK_RST);
 535         rvu_block_reset(rvu, BLKADDR_TIM, TIM_AF_BLK_RST);
 536         rvu_block_reset(rvu, BLKADDR_CPT0, CPT_AF_BLK_RST);
 537         rvu_block_reset(rvu, BLKADDR_CPT1, CPT_AF_BLK_RST);
 538         rvu_block_reset(rvu, BLKADDR_NDC_NIX0_RX, NDC_AF_BLK_RST);
 539         rvu_block_reset(rvu, BLKADDR_NDC_NIX0_TX, NDC_AF_BLK_RST);
 540         rvu_block_reset(rvu, BLKADDR_NDC_NIX1_RX, NDC_AF_BLK_RST);
 541         rvu_block_reset(rvu, BLKADDR_NDC_NIX1_TX, NDC_AF_BLK_RST);
 542         rvu_block_reset(rvu, BLKADDR_NDC_NPA0, NDC_AF_BLK_RST);
 543 }
 544
 545 static void rvu_scan_block(struct rvu *rvu, struct rvu_block *block)
 546 {
 547         struct rvu_pfvf *pfvf;
 548         u64 cfg;
 549         int lf;
 550
 551         for (lf = 0; lf < block->lf.max; lf++) {
 552                 cfg = rvu_read64(rvu, block->addr,
 553                                  block->lfcfg_reg | (lf << block->lfshift));
 554                 if (!(cfg & BIT_ULL(63)))
 555                         continue;
 556
 557                 /* Set this resource as being used */
 558                 __set_bit(lf, block->lf.bmap);
 559
 560                 /* Get, to whom this LF is attached */
 561                 pfvf = rvu_get_pfvf(rvu, (cfg >> 8) & 0xFFFF);
 562                 rvu_update_rsrc_map(rvu, pfvf, block,
 563                                     (cfg >> 8) & 0xFFFF, lf, true);
 564
 565                 /* Set start MSIX vector for this LF within this PF/VF */
 566                 rvu_set_msix_offset(rvu, pfvf, block, lf);
 567         }
 568 }
 569
 570 static void rvu_check_min_msix_vec(struct rvu *rvu, int nvecs, int pf, int vf)
 571 {
 572         int min_vecs;
 573
 574         if (!vf)
 575                 goto check_pf;
 576
 577         if (!nvecs) {
 578                 dev_warn(rvu->dev,
 579                          "PF%d:VF%d is configured with zero msix vectors, %d\n",
 580                          pf, vf - 1, nvecs);
 581         }
 582         return;
 583
 584 check_pf:
 585         if (pf == 0)
 586                 min_vecs = RVU_AF_INT_VEC_CNT + RVU_PF_INT_VEC_CNT;
 587         else
 588                 min_vecs = RVU_PF_INT_VEC_CNT;
 589
 590         if (!(nvecs < min_vecs))
 591                 return;
 592         dev_warn(rvu->dev,
 593                  "PF%d is configured with too few vectors, %d, min is %d\n",
 594                  pf, nvecs, min_vecs);
 595 }
 596
 597 static int rvu_setup_msix_resources(struct rvu *rvu)
 598 {
 599         struct rvu_hwinfo *hw = rvu->hw;
 600         int pf, vf, numvfs, hwvf, err;
 601         int nvecs, offset, max_msix;
 602         struct rvu_pfvf *pfvf;
 603         u64 cfg, phy_addr;
 604         dma_addr_t iova;
 605
 606         for (pf = 0; pf < hw->total_pfs; pf++) {
 607                 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf));
 608                 /* If PF is not enabled, nothing to do */
 609                 if (!((cfg >> 20) & 0x01))
 610                         continue;
 611
 612                 rvu_get_pf_numvfs(rvu, pf, &numvfs, &hwvf);
 613
 614                 pfvf = &rvu->pf[pf];
 615                 /* Get num of MSIX vectors attached to this PF */
 616                 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_MSIX_CFG(pf));
 617                 pfvf->msix.max = ((cfg >> 32) & 0xFFF) + 1;
 618                 rvu_check_min_msix_vec(rvu, pfvf->msix.max, pf, 0);
 619
 620                 /* Alloc msix bitmap for this PF */
 621                 err = rvu_alloc_bitmap(&pfvf->msix);
 622                 if (err)
 623                         return err;
 624
 625                 /* Allocate memory for MSIX vector to RVU block LF mapping */
 626                 pfvf->msix_lfmap = devm_kcalloc(rvu->dev, pfvf->msix.max,
 627                                                 sizeof(u16), GFP_KERNEL);
 628                 if (!pfvf->msix_lfmap)
 629                         return -ENOMEM;
 630
 631                 /* For PF0 (AF) firmware will set msix vector offsets for
 632                  * AF, block AF and PF0_INT vectors, so jump to VFs.
 633                  */
 634                 if (!pf)
 635                         goto setup_vfmsix;
 636
 637                 /* Set MSIX offset for PF's 'RVU_PF_INT_VEC' vectors.
 638                  * These are allocated on driver init and never freed,
 639                  * so no need to set 'msix_lfmap' for these.
 640                  */
 641                 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_INT_CFG(pf));
 642                 nvecs = (cfg >> 12) & 0xFF;
 643                 cfg &= ~0x7FFULL;
 644                 offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs);
 645                 rvu_write64(rvu, BLKADDR_RVUM,
 646                             RVU_PRIV_PFX_INT_CFG(pf), cfg | offset);
 647 setup_vfmsix:
 648                 /* Alloc msix bitmap for VFs */
 649                 for (vf = 0; vf < numvfs; vf++) {
 650                         pfvf =  &rvu->hwvf[hwvf + vf];
 651                         /* Get num of MSIX vectors attached to this VF */
 652                         cfg = rvu_read64(rvu, BLKADDR_RVUM,
 653                                          RVU_PRIV_PFX_MSIX_CFG(pf));
 654                         pfvf->msix.max = (cfg & 0xFFF) + 1;
 655                         rvu_check_min_msix_vec(rvu, pfvf->msix.max, pf, vf + 1);
 656
 657                         /* Alloc msix bitmap for this VF */
 658                         err = rvu_alloc_bitmap(&pfvf->msix);
 659                         if (err)
 660                                 return err;
 661
 662                         pfvf->msix_lfmap =
 663                                 devm_kcalloc(rvu->dev, pfvf->msix.max,
 664                                              sizeof(u16), GFP_KERNEL);
 665                         if (!pfvf->msix_lfmap)
 666                                 return -ENOMEM;
 667
 668                         /* Set MSIX offset for HWVF's 'RVU_VF_INT_VEC' vectors.
 669                          * These are allocated on driver init and never freed,
 670                          * so no need to set 'msix_lfmap' for these.
 671                          */
 672                         cfg = rvu_read64(rvu, BLKADDR_RVUM,
 673                                          RVU_PRIV_HWVFX_INT_CFG(hwvf + vf));
 674                         nvecs = (cfg >> 12) & 0xFF;
 675                         cfg &= ~0x7FFULL;
 676                         offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs);
 677                         rvu_write64(rvu, BLKADDR_RVUM,
 678                                     RVU_PRIV_HWVFX_INT_CFG(hwvf + vf),
 679                                     cfg | offset);
 680                 }
 681         }
 682
 683         /* HW interprets RVU_AF_MSIXTR_BASE address as an IOVA, hence
 684          * create an IOMMU mapping for the physical address configured by
 685          * firmware and reconfig RVU_AF_MSIXTR_BASE with IOVA.
 686          */
 687         cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST);
 688         max_msix = cfg & 0xFFFFF;
 689         if (rvu->fwdata && rvu->fwdata->msixtr_base)
 690                 phy_addr = rvu->fwdata->msixtr_base;
 691         else
 692                 phy_addr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE);
 693
 694         iova = dma_map_resource(rvu->dev, phy_addr,
 695                                 max_msix * PCI_MSIX_ENTRY_SIZE,
 696                                 DMA_BIDIRECTIONAL, 0);
 697
 698         if (dma_mapping_error(rvu->dev, iova))
 699                 return -ENOMEM;
 700
 701         rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE, (u64)iova);
 702         rvu->msix_base_iova = iova;
 703         rvu->msixtr_base_phy = phy_addr;
 704
 705         return 0;
 706 }
 707
 708 static void rvu_reset_msix(struct rvu *rvu)
 709 {
 710         /* Restore msixtr base register */
 711         rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE,
 712                     rvu->msixtr_base_phy);
 713 }
 714
 715 static void rvu_free_hw_resources(struct rvu *rvu)
 716 {
 717         struct rvu_hwinfo *hw = rvu->hw;
 718         struct rvu_block *block;
 719         struct rvu_pfvf  *pfvf;
 720         int id, max_msix;
 721         u64 cfg;
 722
 723         rvu_npa_freemem(rvu);
 724         rvu_npc_freemem(rvu);
 725         rvu_nix_freemem(rvu);
 726
 727         /* Free block LF bitmaps */
 728         for (id = 0; id < BLK_COUNT; id++) {
 729                 block = &hw->block[id];
 730                 kfree(block->lf.bmap);
 731         }
 732
 733         /* Free MSIX bitmaps */
 734         for (id = 0; id < hw->total_pfs; id++) {
 735                 pfvf = &rvu->pf[id];
 736                 kfree(pfvf->msix.bmap);
 737         }
 738
 739         for (id = 0; id < hw->total_vfs; id++) {
 740                 pfvf = &rvu->hwvf[id];
 741                 kfree(pfvf->msix.bmap);
 742         }
 743
 744         /* Unmap MSIX vector base IOVA mapping */
 745         if (!rvu->msix_base_iova)
 746                 return;
 747         cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST);
 748         max_msix = cfg & 0xFFFFF;
 749         dma_unmap_resource(rvu->dev, rvu->msix_base_iova,
 750                            max_msix * PCI_MSIX_ENTRY_SIZE,
 751                            DMA_BIDIRECTIONAL, 0);
 752
 753         rvu_reset_msix(rvu);
 754         mutex_destroy(&rvu->rsrc_lock);
 755 }
 756
 757 static void rvu_setup_pfvf_macaddress(struct rvu *rvu)
 758 {
 759         struct rvu_hwinfo *hw = rvu->hw;
 760         int pf, vf, numvfs, hwvf;
 761         struct rvu_pfvf *pfvf;
 762         u64 *mac;
 763
 764         for (pf = 0; pf < hw->total_pfs; pf++) {
 765                 /* For PF0(AF), Assign MAC address to only VFs (LBKVFs) */
 766                 if (!pf)
 767                         goto lbkvf;
 768
 769                 if (!is_pf_cgxmapped(rvu, pf))
 770                         continue;
 771                 /* Assign MAC address to PF */
 772                 pfvf = &rvu->pf[pf];
 773                 if (rvu->fwdata && pf < PF_MACNUM_MAX) {
 774                         mac = &rvu->fwdata->pf_macs[pf];
 775                         if (*mac)
 776                                 u64_to_ether_addr(*mac, pfvf->mac_addr);
 777                         else
 778                                 eth_random_addr(pfvf->mac_addr);
 779                 } else {
 780                         eth_random_addr(pfvf->mac_addr);
 781                 }
 782                 ether_addr_copy(pfvf->default_mac, pfvf->mac_addr);
 783
 784 lbkvf:
 785                 /* Assign MAC address to VFs*/
 786                 rvu_get_pf_numvfs(rvu, pf, &numvfs, &hwvf);
 787                 for (vf = 0; vf < numvfs; vf++, hwvf++) {
 788                         pfvf = &rvu->hwvf[hwvf];
 789                         if (rvu->fwdata && hwvf < VF_MACNUM_MAX) {
 790                                 mac = &rvu->fwdata->vf_macs[hwvf];
 791                                 if (*mac)
 792                                         u64_to_ether_addr(*mac, pfvf->mac_addr);
 793                                 else
 794                                         eth_random_addr(pfvf->mac_addr);
 795                         } else {
 796                                 eth_random_addr(pfvf->mac_addr);
 797                         }
 798                         ether_addr_copy(pfvf->default_mac, pfvf->mac_addr);
 799                 }
 800         }
 801 }
 802
 803 static int rvu_fwdata_init(struct rvu *rvu)
 804 {
 805         u64 fwdbase;
 806         int err;
 807
 808         /* Get firmware data base address */
 809         err = cgx_get_fwdata_base(&fwdbase);
 810         if (err)
 811                 goto fail;
 812         rvu->fwdata = ioremap_wc(fwdbase, sizeof(struct rvu_fwdata));
 813         if (!rvu->fwdata)
 814                 goto fail;
 815         if (!is_rvu_fwdata_valid(rvu)) {
 816                 dev_err(rvu->dev,
 817                         "Mismatch in 'fwdata' struct btw kernel and firmware\n");
 818                 iounmap(rvu->fwdata);
 819                 rvu->fwdata = NULL;
 820                 return -EINVAL;
 821         }
 822         return 0;
 823 fail:
 824         dev_info(rvu->dev, "Unable to fetch 'fwdata' from firmware\n");
 825         return -EIO;
 826 }
 827
 828 static void rvu_fwdata_exit(struct rvu *rvu)
 829 {
 830         if (rvu->fwdata)
 831                 iounmap(rvu->fwdata);
 832 }
 833
 834 static int rvu_setup_nix_hw_resource(struct rvu *rvu, int blkaddr)
 835 {
 836         struct rvu_hwinfo *hw = rvu->hw;
 837         struct rvu_block *block;
 838         int blkid;
 839         u64 cfg;
 840
 841         /* Init NIX LF's bitmap */
 842         block = &hw->block[blkaddr];
 843         if (!block->implemented)
 844                 return 0;
 845         blkid = (blkaddr == BLKADDR_NIX0) ? 0 : 1;
 846         cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST2);
 847         block->lf.max = cfg & 0xFFF;
 848         block->addr = blkaddr;
 849         block->type = BLKTYPE_NIX;
 850         block->lfshift = 8;
 851         block->lookup_reg = NIX_AF_RVU_LF_CFG_DEBUG;
 852         block->pf_lfcnt_reg = RVU_PRIV_PFX_NIXX_CFG(blkid);
 853         block->vf_lfcnt_reg = RVU_PRIV_HWVFX_NIXX_CFG(blkid);
 854         block->lfcfg_reg = NIX_PRIV_LFX_CFG;
 855         block->msixcfg_reg = NIX_PRIV_LFX_INT_CFG;
 856         block->lfreset_reg = NIX_AF_LF_RST;
 857         block->rvu = rvu;
 858         sprintf(block->name, "NIX%d", blkid);
 859         rvu->nix_blkaddr[blkid] = blkaddr;
 860         return rvu_alloc_bitmap(&block->lf);
 861 }
 862
 863 static int rvu_setup_cpt_hw_resource(struct rvu *rvu, int blkaddr)
 864 {
 865         struct rvu_hwinfo *hw = rvu->hw;
 866         struct rvu_block *block;
 867         int blkid;
 868         u64 cfg;
 869
 870         /* Init CPT LF's bitmap */
 871         block = &hw->block[blkaddr];
 872         if (!block->implemented)
 873                 return 0;
 874         blkid = (blkaddr == BLKADDR_CPT0) ? 0 : 1;
 875         cfg = rvu_read64(rvu, blkaddr, CPT_AF_CONSTANTS0);
 876         block->lf.max = cfg & 0xFF;
 877         block->addr = blkaddr;
 878         block->type = BLKTYPE_CPT;
 879         block->multislot = true;
 880         block->lfshift = 3;
 881         block->lookup_reg = CPT_AF_RVU_LF_CFG_DEBUG;
 882         block->pf_lfcnt_reg = RVU_PRIV_PFX_CPTX_CFG(blkid);
 883         block->vf_lfcnt_reg = RVU_PRIV_HWVFX_CPTX_CFG(blkid);
 884         block->lfcfg_reg = CPT_PRIV_LFX_CFG;
 885         block->msixcfg_reg = CPT_PRIV_LFX_INT_CFG;
 886         block->lfreset_reg = CPT_AF_LF_RST;
 887         block->rvu = rvu;
 888         sprintf(block->name, "CPT%d", blkid);
 889         return rvu_alloc_bitmap(&block->lf);
 890 }
 891
 892 static void rvu_get_lbk_bufsize(struct rvu *rvu)
 893 {
 894         struct pci_dev *pdev = NULL;
 895         void __iomem *base;
 896         u64 lbk_const;
 897
 898         pdev = pci_get_device(PCI_VENDOR_ID_CAVIUM,
 899                               PCI_DEVID_OCTEONTX2_LBK, pdev);
 900         if (!pdev)
 901                 return;
 902
 903         base = pci_ioremap_bar(pdev, 0);
 904         if (!base)
 905                 goto err_put;
 906
 907         lbk_const = readq(base + LBK_CONST);
 908
 909         /* cache fifo size */
 910         rvu->hw->lbk_bufsize = FIELD_GET(LBK_CONST_BUF_SIZE, lbk_const);
 911
 912         iounmap(base);
 913 err_put:
 914         pci_dev_put(pdev);
 915 }
 916
 917 static int rvu_setup_hw_resources(struct rvu *rvu)
 918 {
 919         struct rvu_hwinfo *hw = rvu->hw;
 920         struct rvu_block *block;
 921         int blkid, err;
 922         u64 cfg;
 923
 924         /* Get HW supported max RVU PF & VF count */
 925         cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST);
 926         hw->total_pfs = (cfg >> 32) & 0xFF;
 927         hw->total_vfs = (cfg >> 20) & 0xFFF;
 928         hw->max_vfs_per_pf = (cfg >> 40) & 0xFF;
 929
 930         /* Init NPA LF's bitmap */
 931         block = &hw->block[BLKADDR_NPA];
 932         if (!block->implemented)
 933                 goto nix;
 934         cfg = rvu_read64(rvu, BLKADDR_NPA, NPA_AF_CONST);
 935         block->lf.max = (cfg >> 16) & 0xFFF;
 936         block->addr = BLKADDR_NPA;
 937         block->type = BLKTYPE_NPA;
 938         block->lfshift = 8;
 939         block->lookup_reg = NPA_AF_RVU_LF_CFG_DEBUG;
 940         block->pf_lfcnt_reg = RVU_PRIV_PFX_NPA_CFG;
 941         block->vf_lfcnt_reg = RVU_PRIV_HWVFX_NPA_CFG;
 942         block->lfcfg_reg = NPA_PRIV_LFX_CFG;
 943         block->msixcfg_reg = NPA_PRIV_LFX_INT_CFG;
 944         block->lfreset_reg = NPA_AF_LF_RST;
 945         block->rvu = rvu;
 946         sprintf(block->name, "NPA");
 947         err = rvu_alloc_bitmap(&block->lf);
 948         if (err) {
 949                 dev_err(rvu->dev,
 950                         "%s: Failed to allocate NPA LF bitmap\n", __func__);
 951                 return err;
 952         }
 953
 954 nix:
 955         err = rvu_setup_nix_hw_resource(rvu, BLKADDR_NIX0);
 956         if (err) {
 957                 dev_err(rvu->dev,
 958                         "%s: Failed to allocate NIX0 LFs bitmap\n", __func__);
 959                 return err;
 960         }
 961
 962         err = rvu_setup_nix_hw_resource(rvu, BLKADDR_NIX1);
 963         if (err) {
 964                 dev_err(rvu->dev,
 965                         "%s: Failed to allocate NIX1 LFs bitmap\n", __func__);
 966                 return err;
 967         }
 968
 969         /* Init SSO group's bitmap */
 970         block = &hw->block[BLKADDR_SSO];
 971         if (!block->implemented)
 972                 goto ssow;
 973         cfg = rvu_read64(rvu, BLKADDR_SSO, SSO_AF_CONST);
 974         block->lf.max = cfg & 0xFFFF;
 975         block->addr = BLKADDR_SSO;
 976         block->type = BLKTYPE_SSO;
 977         block->multislot = true;
 978         block->lfshift = 3;
 979         block->lookup_reg = SSO_AF_RVU_LF_CFG_DEBUG;
 980         block->pf_lfcnt_reg = RVU_PRIV_PFX_SSO_CFG;
 981         block->vf_lfcnt_reg = RVU_PRIV_HWVFX_SSO_CFG;
 982         block->lfcfg_reg = SSO_PRIV_LFX_HWGRP_CFG;
 983         block->msixcfg_reg = SSO_PRIV_LFX_HWGRP_INT_CFG;
 984         block->lfreset_reg = SSO_AF_LF_HWGRP_RST;
 985         block->rvu = rvu;
 986         sprintf(block->name, "SSO GROUP");
 987         err = rvu_alloc_bitmap(&block->lf);
 988         if (err) {
 989                 dev_err(rvu->dev,
 990                         "%s: Failed to allocate SSO LF bitmap\n", __func__);
 991                 return err;
 992         }
 993
 994 ssow:
 995         /* Init SSO workslot's bitmap */
 996         block = &hw->block[BLKADDR_SSOW];
 997         if (!block->implemented)
 998                 goto tim;
 999         block->lf.max = (cfg >> 56) & 0xFF;
1000         block->addr = BLKADDR_SSOW;
1001         block->type = BLKTYPE_SSOW;
1002         block->multislot = true;
1003         block->lfshift = 3;
1004         block->lookup_reg = SSOW_AF_RVU_LF_HWS_CFG_DEBUG;
1005         block->pf_lfcnt_reg = RVU_PRIV_PFX_SSOW_CFG;
1006         block->vf_lfcnt_reg = RVU_PRIV_HWVFX_SSOW_CFG;
1007         block->lfcfg_reg = SSOW_PRIV_LFX_HWS_CFG;
1008         block->msixcfg_reg = SSOW_PRIV_LFX_HWS_INT_CFG;
1009         block->lfreset_reg = SSOW_AF_LF_HWS_RST;
1010         block->rvu = rvu;
1011         sprintf(block->name, "SSOWS");
1012         err = rvu_alloc_bitmap(&block->lf);
1013         if (err) {
1014                 dev_err(rvu->dev,
1015                         "%s: Failed to allocate SSOW LF bitmap\n", __func__);
1016                 return err;
1017         }
1018
1019 tim:
1020         /* Init TIM LF's bitmap */
1021         block = &hw->block[BLKADDR_TIM];
1022         if (!block->implemented)
1023                 goto cpt;
1024         cfg = rvu_read64(rvu, BLKADDR_TIM, TIM_AF_CONST);
1025         block->lf.max = cfg & 0xFFFF;
1026         block->addr = BLKADDR_TIM;
1027         block->type = BLKTYPE_TIM;
1028         block->multislot = true;
1029         block->lfshift = 3;
1030         block->lookup_reg = TIM_AF_RVU_LF_CFG_DEBUG;
1031         block->pf_lfcnt_reg = RVU_PRIV_PFX_TIM_CFG;
1032         block->vf_lfcnt_reg = RVU_PRIV_HWVFX_TIM_CFG;
1033         block->lfcfg_reg = TIM_PRIV_LFX_CFG;
1034         block->msixcfg_reg = TIM_PRIV_LFX_INT_CFG;
1035         block->lfreset_reg = TIM_AF_LF_RST;
1036         block->rvu = rvu;
1037         sprintf(block->name, "TIM");
1038         err = rvu_alloc_bitmap(&block->lf);
1039         if (err) {
1040                 dev_err(rvu->dev,
1041                         "%s: Failed to allocate TIM LF bitmap\n", __func__);
1042                 return err;
1043         }
1044
1045 cpt:
1046         err = rvu_setup_cpt_hw_resource(rvu, BLKADDR_CPT0);
1047         if (err) {
1048                 dev_err(rvu->dev,
1049                         "%s: Failed to allocate CPT0 LF bitmap\n", __func__);
1050                 return err;
1051         }
1052         err = rvu_setup_cpt_hw_resource(rvu, BLKADDR_CPT1);
1053         if (err) {
1054                 dev_err(rvu->dev,
1055                         "%s: Failed to allocate CPT1 LF bitmap\n", __func__);
1056                 return err;
1057         }
1058
1059         /* Allocate memory for PFVF data */
1060         rvu->pf = devm_kcalloc(rvu->dev, hw->total_pfs,
1061                                sizeof(struct rvu_pfvf), GFP_KERNEL);
1062         if (!rvu->pf) {
1063                 dev_err(rvu->dev,
1064                         "%s: Failed to allocate memory for PF's rvu_pfvf struct\n", __func__);
1065                 return -ENOMEM;
1066         }
1067
1068         rvu->hwvf = devm_kcalloc(rvu->dev, hw->total_vfs,
1069                                  sizeof(struct rvu_pfvf), GFP_KERNEL);
1070         if (!rvu->hwvf) {
1071                 dev_err(rvu->dev,
1072                         "%s: Failed to allocate memory for VF's rvu_pfvf struct\n", __func__);
1073                 return -ENOMEM;
1074         }
1075
1076         mutex_init(&rvu->rsrc_lock);
1077
1078         rvu_fwdata_init(rvu);
1079
1080         err = rvu_setup_msix_resources(rvu);
1081         if (err) {
1082                 dev_err(rvu->dev,
1083                         "%s: Failed to setup MSIX resources\n", __func__);
1084                 return err;
1085         }
1086
1087         for (blkid = 0; blkid < BLK_COUNT; blkid++) {
1088                 block = &hw->block[blkid];
1089                 if (!block->lf.bmap)
1090                         continue;
1091
1092                 /* Allocate memory for block LF/slot to pcifunc mapping info */
1093                 block->fn_map = devm_kcalloc(rvu->dev, block->lf.max,
1094                                              sizeof(u16), GFP_KERNEL);
1095                 if (!block->fn_map) {
1096                         err = -ENOMEM;
1097                         goto msix_err;
1098                 }
1099
1100                 /* Scan all blocks to check if low level firmware has
1101                  * already provisioned any of the resources to a PF/VF.
1102                  */
1103                 rvu_scan_block(rvu, block);
1104         }
1105
1106         err = rvu_set_channels_base(rvu);
1107         if (err)
1108                 goto msix_err;
1109
1110         err = rvu_npc_init(rvu);
1111         if (err) {
1112                 dev_err(rvu->dev, "%s: Failed to initialize npc\n", __func__);
1113                 goto npc_err;
1114         }
1115
1116         err = rvu_cgx_init(rvu);
1117         if (err) {
1118                 dev_err(rvu->dev, "%s: Failed to initialize cgx\n", __func__);
1119                 goto cgx_err;
1120         }
1121
1122         /* Assign MACs for CGX mapped functions */
1123         rvu_setup_pfvf_macaddress(rvu);
1124
1125         err = rvu_npa_init(rvu);
1126         if (err) {
1127                 dev_err(rvu->dev, "%s: Failed to initialize npa\n", __func__);
1128                 goto npa_err;
1129         }
1130
1131         rvu_get_lbk_bufsize(rvu);
1132
1133         err = rvu_nix_init(rvu);
1134         if (err) {
1135                 dev_err(rvu->dev, "%s: Failed to initialize nix\n", __func__);
1136                 goto nix_err;
1137         }
1138
1139         err = rvu_sdp_init(rvu);
1140         if (err) {
1141                 dev_err(rvu->dev, "%s: Failed to initialize sdp\n", __func__);
1142                 goto nix_err;
1143         }
1144
1145         rvu_program_channels(rvu);
1146
1147         return 0;
1148
1149 nix_err:
1150         rvu_nix_freemem(rvu);
1151 npa_err:
1152         rvu_npa_freemem(rvu);
1153 cgx_err:
1154         rvu_cgx_exit(rvu);
1155 npc_err:
1156         rvu_npc_freemem(rvu);
1157         rvu_fwdata_exit(rvu);
1158 msix_err:
1159         rvu_reset_msix(rvu);
1160         return err;
1161 }
1162
1163 /* NPA and NIX admin queue APIs */
1164 void rvu_aq_free(struct rvu *rvu, struct admin_queue *aq)
1165 {
1166         if (!aq)
1167                 return;
1168
1169         qmem_free(rvu->dev, aq->inst);
1170         qmem_free(rvu->dev, aq->res);
1171         devm_kfree(rvu->dev, aq);
1172 }
1173
1174 int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue,
1175                  int qsize, int inst_size, int res_size)
1176 {
1177         struct admin_queue *aq;
1178         int err;
1179
1180         *ad_queue = devm_kzalloc(rvu->dev, sizeof(*aq), GFP_KERNEL);
1181         if (!*ad_queue)
1182                 return -ENOMEM;
1183         aq = *ad_queue;
1184
1185         /* Alloc memory for instructions i.e AQ */
1186         err = qmem_alloc(rvu->dev, &aq->inst, qsize, inst_size);
1187         if (err) {
1188                 devm_kfree(rvu->dev, aq);
1189                 return err;
1190         }
1191
1192         /* Alloc memory for results */
1193         err = qmem_alloc(rvu->dev, &aq->res, qsize, res_size);
1194         if (err) {
1195                 rvu_aq_free(rvu, aq);
1196                 return err;
1197         }
1198
1199         spin_lock_init(&aq->lock);
1200         return 0;
1201 }
1202
1203 int rvu_mbox_handler_ready(struct rvu *rvu, struct msg_req *req,
1204                            struct ready_msg_rsp *rsp)
1205 {
1206         if (rvu->fwdata) {
1207                 rsp->rclk_freq = rvu->fwdata->rclk;
1208                 rsp->sclk_freq = rvu->fwdata->sclk;
1209         }
1210         return 0;
1211 }
1212
1213 /* Get current count of a RVU block's LF/slots
1214  * provisioned to a given RVU func.
1215  */
1216 u16 rvu_get_rsrc_mapcount(struct rvu_pfvf *pfvf, int blkaddr)
1217 {
1218         switch (blkaddr) {
1219         case BLKADDR_NPA:
1220                 return pfvf->npalf ? 1 : 0;
1221         case BLKADDR_NIX0:
1222         case BLKADDR_NIX1:
1223                 return pfvf->nixlf ? 1 : 0;
1224         case BLKADDR_SSO:
1225                 return pfvf->sso;
1226         case BLKADDR_SSOW:
1227                 return pfvf->ssow;
1228         case BLKADDR_TIM:
1229                 return pfvf->timlfs;
1230         case BLKADDR_CPT0:
1231                 return pfvf->cptlfs;
1232         case BLKADDR_CPT1:
1233                 return pfvf->cpt1_lfs;
1234         }
1235         return 0;
1236 }
1237
1238 /* Return true if LFs of block type are attached to pcifunc */
1239 static bool is_blktype_attached(struct rvu_pfvf *pfvf, int blktype)
1240 {
1241         switch (blktype) {
1242         case BLKTYPE_NPA:
1243                 return pfvf->npalf ? 1 : 0;
1244         case BLKTYPE_NIX:
1245                 return pfvf->nixlf ? 1 : 0;
1246         case BLKTYPE_SSO:
1247                 return !!pfvf->sso;
1248         case BLKTYPE_SSOW:
1249                 return !!pfvf->ssow;
1250         case BLKTYPE_TIM:
1251                 return !!pfvf->timlfs;
1252         case BLKTYPE_CPT:
1253                 return pfvf->cptlfs || pfvf->cpt1_lfs;
1254         }
1255
1256         return false;
1257 }
1258
1259 bool is_pffunc_map_valid(struct rvu *rvu, u16 pcifunc, int blktype)
1260 {
1261         struct rvu_pfvf *pfvf;
1262
1263         if (!is_pf_func_valid(rvu, pcifunc))
1264                 return false;
1265
1266         pfvf = rvu_get_pfvf(rvu, pcifunc);
1267
1268         /* Check if this PFFUNC has a LF of type blktype attached */
1269         if (!is_blktype_attached(pfvf, blktype))
1270                 return false;
1271
1272         return true;
1273 }
1274
1275 static int rvu_lookup_rsrc(struct rvu *rvu, struct rvu_block *block,
1276                            int pcifunc, int slot)
1277 {
1278         u64 val;
1279
1280         val = ((u64)pcifunc << 24) | (slot << 16) | (1ULL << 13);
1281         rvu_write64(rvu, block->addr, block->lookup_reg, val);
1282         /* Wait for the lookup to finish */
1283         /* TODO: put some timeout here */
1284         while (rvu_read64(rvu, block->addr, block->lookup_reg) & (1ULL << 13))
1285                 ;
1286
1287         val = rvu_read64(rvu, block->addr, block->lookup_reg);
1288
1289         /* Check LF valid bit */
1290         if (!(val & (1ULL << 12)))
1291                 return -1;
1292
1293         return (val & 0xFFF);
1294 }
1295
1296 int rvu_get_blkaddr_from_slot(struct rvu *rvu, int blktype, u16 pcifunc,
1297                               u16 global_slot, u16 *slot_in_block)
1298 {
1299         struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
1300         int numlfs, total_lfs = 0, nr_blocks = 0;
1301         int i, num_blkaddr[BLK_COUNT] = { 0 };
1302         struct rvu_block *block;
1303         int blkaddr;
1304         u16 start_slot;
1305
1306         if (!is_blktype_attached(pfvf, blktype))
1307                 return -ENODEV;
1308
1309         /* Get all the block addresses from which LFs are attached to
1310          * the given pcifunc in num_blkaddr[].
1311          */
1312         for (blkaddr = BLKADDR_RVUM; blkaddr < BLK_COUNT; blkaddr++) {
1313                 block = &rvu->hw->block[blkaddr];
1314                 if (block->type != blktype)
1315                         continue;
1316                 if (!is_block_implemented(rvu->hw, blkaddr))
1317                         continue;
1318
1319                 numlfs = rvu_get_rsrc_mapcount(pfvf, blkaddr);
1320                 if (numlfs) {
1321                         total_lfs += numlfs;
1322                         num_blkaddr[nr_blocks] = blkaddr;
1323                         nr_blocks++;
1324                 }
1325         }
1326
1327         if (global_slot >= total_lfs)
1328                 return -ENODEV;
1329
1330         /* Based on the given global slot number retrieve the
1331          * correct block address out of all attached block
1332          * addresses and slot number in that block.
1333          */
1334         total_lfs = 0;
1335         blkaddr = -ENODEV;
1336         for (i = 0; i < nr_blocks; i++) {
1337                 numlfs = rvu_get_rsrc_mapcount(pfvf, num_blkaddr[i]);
1338                 total_lfs += numlfs;
1339                 if (global_slot < total_lfs) {
1340                         blkaddr = num_blkaddr[i];
1341                         start_slot = total_lfs - numlfs;
1342                         *slot_in_block = global_slot - start_slot;
1343                         break;
1344                 }
1345         }
1346
1347         return blkaddr;
1348 }
1349
1350 static void rvu_detach_block(struct rvu *rvu, int pcifunc, int blktype)
1351 {
1352         struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
1353         struct rvu_hwinfo *hw = rvu->hw;
1354         struct rvu_block *block;
1355         int slot, lf, num_lfs;
1356         int blkaddr;
1357
1358         blkaddr = rvu_get_blkaddr(rvu, blktype, pcifunc);
1359         if (blkaddr < 0)
1360                 return;
1361
1362         if (blktype == BLKTYPE_NIX)
1363                 rvu_nix_reset_mac(pfvf, pcifunc);
1364
1365         block = &hw->block[blkaddr];
1366
1367         num_lfs = rvu_get_rsrc_mapcount(pfvf, block->addr);
1368         if (!num_lfs)
1369                 return;
1370
1371         for (slot = 0; slot < num_lfs; slot++) {
1372                 lf = rvu_lookup_rsrc(rvu, block, pcifunc, slot);
1373                 if (lf < 0) /* This should never happen */
1374                         continue;
1375
1376                 /* Disable the LF */
1377                 rvu_write64(rvu, blkaddr, block->lfcfg_reg |
1378                             (lf << block->lfshift), 0x00ULL);
1379
1380                 /* Update SW maintained mapping info as well */
1381                 rvu_update_rsrc_map(rvu, pfvf, block,
1382                                     pcifunc, lf, false);
1383
1384                 /* Free the resource */
1385                 rvu_free_rsrc(&block->lf, lf);
1386
1387                 /* Clear MSIX vector offset for this LF */
1388                 rvu_clear_msix_offset(rvu, pfvf, block, lf);
1389         }
1390 }
1391
1392 static int rvu_detach_rsrcs(struct rvu *rvu, struct rsrc_detach *detach,
1393                             u16 pcifunc)
1394 {
1395         struct rvu_hwinfo *hw = rvu->hw;
1396         bool detach_all = true;
1397         struct rvu_block *block;
1398         int blkid;
1399
1400         mutex_lock(&rvu->rsrc_lock);
1401
1402         /* Check for partial resource detach */
1403         if (detach && detach->partial)
1404                 detach_all = false;
1405
1406         /* Check for RVU block's LFs attached to this func,
1407          * if so, detach them.
1408          */
1409         for (blkid = 0; blkid < BLK_COUNT; blkid++) {
1410                 block = &hw->block[blkid];
1411                 if (!block->lf.bmap)
1412                         continue;
1413                 if (!detach_all && detach) {
1414                         if (blkid == BLKADDR_NPA && !detach->npalf)
1415                                 continue;
1416                         else if ((blkid == BLKADDR_NIX0) && !detach->nixlf)
1417                                 continue;
1418                         else if ((blkid == BLKADDR_NIX1) && !detach->nixlf)
1419                                 continue;
1420                         else if ((blkid == BLKADDR_SSO) && !detach->sso)
1421                                 continue;
1422                         else if ((blkid == BLKADDR_SSOW) && !detach->ssow)
1423                                 continue;
1424                         else if ((blkid == BLKADDR_TIM) && !detach->timlfs)
1425                                 continue;
1426                         else if ((blkid == BLKADDR_CPT0) && !detach->cptlfs)
1427                                 continue;
1428                         else if ((blkid == BLKADDR_CPT1) && !detach->cptlfs)
1429                                 continue;
1430                 }
1431                 rvu_detach_block(rvu, pcifunc, block->type);
1432         }
1433
1434         mutex_unlock(&rvu->rsrc_lock);
1435         return 0;
1436 }
1437
1438 int rvu_mbox_handler_detach_resources(struct rvu *rvu,
1439                                       struct rsrc_detach *detach,
1440                                       struct msg_rsp *rsp)
1441 {
1442         return rvu_detach_rsrcs(rvu, detach, detach->hdr.pcifunc);
1443 }
1444
1445 int rvu_get_nix_blkaddr(struct rvu *rvu, u16 pcifunc)
1446 {
1447         struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
1448         int blkaddr = BLKADDR_NIX0, vf;
1449         struct rvu_pfvf *pf;
1450
1451         pf = rvu_get_pfvf(rvu, pcifunc & ~RVU_PFVF_FUNC_MASK);
1452
1453         /* All CGX mapped PFs are set with assigned NIX block during init */
1454         if (is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc))) {
1455                 blkaddr = pf->nix_blkaddr;
1456         } else if (is_afvf(pcifunc)) {
1457                 vf = pcifunc - 1;
1458                 /* Assign NIX based on VF number. All even numbered VFs get
1459                  * NIX0 and odd numbered gets NIX1
1460                  */
1461                 blkaddr = (vf & 1) ? BLKADDR_NIX1 : BLKADDR_NIX0;
1462                 /* NIX1 is not present on all silicons */
1463                 if (!is_block_implemented(rvu->hw, BLKADDR_NIX1))
1464                         blkaddr = BLKADDR_NIX0;
1465         }
1466
1467         /* if SDP1 then the blkaddr is NIX1 */
1468         if (is_sdp_pfvf(pcifunc) && pf->sdp_info->node_id == 1)
1469                 blkaddr = BLKADDR_NIX1;
1470
1471         switch (blkaddr) {
1472         case BLKADDR_NIX1:
1473                 pfvf->nix_blkaddr = BLKADDR_NIX1;
1474                 pfvf->nix_rx_intf = NIX_INTFX_RX(1);
1475                 pfvf->nix_tx_intf = NIX_INTFX_TX(1);
1476                 break;
1477         case BLKADDR_NIX0:
1478         default:
1479                 pfvf->nix_blkaddr = BLKADDR_NIX0;
1480                 pfvf->nix_rx_intf = NIX_INTFX_RX(0);
1481                 pfvf->nix_tx_intf = NIX_INTFX_TX(0);
1482                 break;
1483         }
1484
1485         return pfvf->nix_blkaddr;
1486 }
1487
1488 static int rvu_get_attach_blkaddr(struct rvu *rvu, int blktype,
1489                                   u16 pcifunc, struct rsrc_attach *attach)
1490 {
1491         int blkaddr;
1492
1493         switch (blktype) {
1494         case BLKTYPE_NIX:
1495                 blkaddr = rvu_get_nix_blkaddr(rvu, pcifunc);
1496                 break;
1497         case BLKTYPE_CPT:
1498                 if (attach->hdr.ver < RVU_MULTI_BLK_VER)
1499                         return rvu_get_blkaddr(rvu, blktype, 0);
1500                 blkaddr = attach->cpt_blkaddr ? attach->cpt_blkaddr :
1501                           BLKADDR_CPT0;
1502                 if (blkaddr != BLKADDR_CPT0 && blkaddr != BLKADDR_CPT1)
1503                         return -ENODEV;
1504                 break;
1505         default:
1506                 return rvu_get_blkaddr(rvu, blktype, 0);
1507         }
1508
1509         if (is_block_implemented(rvu->hw, blkaddr))
1510                 return blkaddr;
1511
1512         return -ENODEV;
1513 }
1514
1515 static void rvu_attach_block(struct rvu *rvu, int pcifunc, int blktype,
1516                              int num_lfs, struct rsrc_attach *attach)
1517 {
1518         struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
1519         struct rvu_hwinfo *hw = rvu->hw;
1520         struct rvu_block *block;
1521         int slot, lf;
1522         int blkaddr;
1523         u64 cfg;
1524
1525         if (!num_lfs)
1526                 return;
1527
1528         blkaddr = rvu_get_attach_blkaddr(rvu, blktype, pcifunc, attach);
1529         if (blkaddr < 0)
1530                 return;
1531
1532         block = &hw->block[blkaddr];
1533         if (!block->lf.bmap)
1534                 return;
1535
1536         for (slot = 0; slot < num_lfs; slot++) {
1537                 /* Allocate the resource */
1538                 lf = rvu_alloc_rsrc(&block->lf);
1539                 if (lf < 0)
1540                         return;
1541
1542                 cfg = (1ULL << 63) | (pcifunc << 8) | slot;
1543                 rvu_write64(rvu, blkaddr, block->lfcfg_reg |
1544                             (lf << block->lfshift), cfg);
1545                 rvu_update_rsrc_map(rvu, pfvf, block,
1546                                     pcifunc, lf, true);
1547
1548                 /* Set start MSIX vector for this LF within this PF/VF */
1549                 rvu_set_msix_offset(rvu, pfvf, block, lf);
1550         }
1551 }
1552
1553 static int rvu_check_rsrc_availability(struct rvu *rvu,
1554                                        struct rsrc_attach *req, u16 pcifunc)
1555 {
1556         struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
1557         int free_lfs, mappedlfs, blkaddr;
1558         struct rvu_hwinfo *hw = rvu->hw;
1559         struct rvu_block *block;
1560
1561         /* Only one NPA LF can be attached */
1562         if (req->npalf && !is_blktype_attached(pfvf, BLKTYPE_NPA)) {
1563                 block = &hw->block[BLKADDR_NPA];
1564                 free_lfs = rvu_rsrc_free_count(&block->lf);
1565                 if (!free_lfs)
1566                         goto fail;
1567         } else if (req->npalf) {
1568                 dev_err(&rvu->pdev->dev,
1569                         "Func 0x%x: Invalid req, already has NPA\n",
1570                          pcifunc);
1571                 return -EINVAL;
1572         }
1573
1574         /* Only one NIX LF can be attached */
1575         if (req->nixlf && !is_blktype_attached(pfvf, BLKTYPE_NIX)) {
1576                 blkaddr = rvu_get_attach_blkaddr(rvu, BLKTYPE_NIX,
1577                                                  pcifunc, req);
1578                 if (blkaddr < 0)
1579                         return blkaddr;
1580                 block = &hw->block[blkaddr];
1581                 free_lfs = rvu_rsrc_free_count(&block->lf);
1582                 if (!free_lfs)
1583                         goto fail;
1584         } else if (req->nixlf) {
1585                 dev_err(&rvu->pdev->dev,
1586                         "Func 0x%x: Invalid req, already has NIX\n",
1587                         pcifunc);
1588                 return -EINVAL;
1589         }
1590
1591         if (req->sso) {
1592                 block = &hw->block[BLKADDR_SSO];
1593                 /* Is request within limits ? */
1594                 if (req->sso > block->lf.max) {
1595                         dev_err(&rvu->pdev->dev,
1596                                 "Func 0x%x: Invalid SSO req, %d > max %d\n",
1597                                  pcifunc, req->sso, block->lf.max);
1598                         return -EINVAL;
1599                 }
1600                 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr);
1601                 free_lfs = rvu_rsrc_free_count(&block->lf);
1602                 /* Check if additional resources are available */
1603                 if (req->sso > mappedlfs &&
1604                     ((req->sso - mappedlfs) > free_lfs))
1605                         goto fail;
1606         }
1607
1608         if (req->ssow) {
1609                 block = &hw->block[BLKADDR_SSOW];
1610                 if (req->ssow > block->lf.max) {
1611                         dev_err(&rvu->pdev->dev,
1612                                 "Func 0x%x: Invalid SSOW req, %d > max %d\n",
1613                                  pcifunc, req->sso, block->lf.max);
1614                         return -EINVAL;
1615                 }
1616                 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr);
1617                 free_lfs = rvu_rsrc_free_count(&block->lf);
1618                 if (req->ssow > mappedlfs &&
1619                     ((req->ssow - mappedlfs) > free_lfs))
1620                         goto fail;
1621         }
1622
1623         if (req->timlfs) {
1624                 block = &hw->block[BLKADDR_TIM];
1625                 if (req->timlfs > block->lf.max) {
1626                         dev_err(&rvu->pdev->dev,
1627                                 "Func 0x%x: Invalid TIMLF req, %d > max %d\n",
1628                                  pcifunc, req->timlfs, block->lf.max);
1629                         return -EINVAL;
1630                 }
1631                 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr);
1632                 free_lfs = rvu_rsrc_free_count(&block->lf);
1633                 if (req->timlfs > mappedlfs &&
1634                     ((req->timlfs - mappedlfs) > free_lfs))
1635                         goto fail;
1636         }
1637
1638         if (req->cptlfs) {
1639                 blkaddr = rvu_get_attach_blkaddr(rvu, BLKTYPE_CPT,
1640                                                  pcifunc, req);
1641                 if (blkaddr < 0)
1642                         return blkaddr;
1643                 block = &hw->block[blkaddr];
1644                 if (req->cptlfs > block->lf.max) {
1645                         dev_err(&rvu->pdev->dev,
1646                                 "Func 0x%x: Invalid CPTLF req, %d > max %d\n",
1647                                  pcifunc, req->cptlfs, block->lf.max);
1648                         return -EINVAL;
1649                 }
1650                 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr);
1651                 free_lfs = rvu_rsrc_free_count(&block->lf);
1652                 if (req->cptlfs > mappedlfs &&
1653                     ((req->cptlfs - mappedlfs) > free_lfs))
1654                         goto fail;
1655         }
1656
1657         return 0;
1658
1659 fail:
1660         dev_info(rvu->dev, "Request for %s failed\n", block->name);
1661         return -ENOSPC;
1662 }
1663
1664 static bool rvu_attach_from_same_block(struct rvu *rvu, int blktype,
1665                                        struct rsrc_attach *attach)
1666 {
1667         int blkaddr, num_lfs;
1668
1669         blkaddr = rvu_get_attach_blkaddr(rvu, blktype,
1670                                          attach->hdr.pcifunc, attach);
1671         if (blkaddr < 0)
1672                 return false;
1673
1674         num_lfs = rvu_get_rsrc_mapcount(rvu_get_pfvf(rvu, attach->hdr.pcifunc),
1675                                         blkaddr);
1676         /* Requester already has LFs from given block ? */
1677         return !!num_lfs;
1678 }
1679
1680 int rvu_mbox_handler_attach_resources(struct rvu *rvu,
1681                                       struct rsrc_attach *attach,
1682                                       struct msg_rsp *rsp)
1683 {
1684         u16 pcifunc = attach->hdr.pcifunc;
1685         int err;
1686
1687         /* If first request, detach all existing attached resources */
1688         if (!attach->modify)
1689                 rvu_detach_rsrcs(rvu, NULL, pcifunc);
1690
1691         mutex_lock(&rvu->rsrc_lock);
1692
1693         /* Check if the request can be accommodated */
1694         err = rvu_check_rsrc_availability(rvu, attach, pcifunc);
1695         if (err)
1696                 goto exit;
1697
1698         /* Now attach the requested resources */
1699         if (attach->npalf)
1700                 rvu_attach_block(rvu, pcifunc, BLKTYPE_NPA, 1, attach);
1701
1702         if (attach->nixlf)
1703                 rvu_attach_block(rvu, pcifunc, BLKTYPE_NIX, 1, attach);
1704
1705         if (attach->sso) {
1706                 /* RVU func doesn't know which exact LF or slot is attached
1707                  * to it, it always sees as slot 0,1,2. So for a 'modify'
1708                  * request, simply detach all existing attached LFs/slots
1709                  * and attach a fresh.
1710                  */
1711                 if (attach->modify)
1712                         rvu_detach_block(rvu, pcifunc, BLKTYPE_SSO);
1713                 rvu_attach_block(rvu, pcifunc, BLKTYPE_SSO,
1714                                  attach->sso, attach);
1715         }
1716
1717         if (attach->ssow) {
1718                 if (attach->modify)
1719                         rvu_detach_block(rvu, pcifunc, BLKTYPE_SSOW);
1720                 rvu_attach_block(rvu, pcifunc, BLKTYPE_SSOW,
1721                                  attach->ssow, attach);
1722         }
1723
1724         if (attach->timlfs) {
1725                 if (attach->modify)
1726                         rvu_detach_block(rvu, pcifunc, BLKTYPE_TIM);
1727                 rvu_attach_block(rvu, pcifunc, BLKTYPE_TIM,
1728                                  attach->timlfs, attach);
1729         }
1730
1731         if (attach->cptlfs) {
1732                 if (attach->modify &&
1733                     rvu_attach_from_same_block(rvu, BLKTYPE_CPT, attach))
1734                         rvu_detach_block(rvu, pcifunc, BLKTYPE_CPT);
1735                 rvu_attach_block(rvu, pcifunc, BLKTYPE_CPT,
1736                                  attach->cptlfs, attach);
1737         }
1738
1739 exit:
1740         mutex_unlock(&rvu->rsrc_lock);
1741         return err;
1742 }
1743
1744 static u16 rvu_get_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf,
1745                                int blkaddr, int lf)
1746 {
1747         u16 vec;
1748
1749         if (lf < 0)
1750                 return MSIX_VECTOR_INVALID;
1751
1752         for (vec = 0; vec < pfvf->msix.max; vec++) {
1753                 if (pfvf->msix_lfmap[vec] == MSIX_BLKLF(blkaddr, lf))
1754                         return vec;
1755         }
1756         return MSIX_VECTOR_INVALID;
1757 }
1758
1759 static void rvu_set_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf,
1760                                 struct rvu_block *block, int lf)
1761 {
1762         u16 nvecs, vec, offset;
1763         u64 cfg;
1764
1765         cfg = rvu_read64(rvu, block->addr, block->msixcfg_reg |
1766                          (lf << block->lfshift));
1767         nvecs = (cfg >> 12) & 0xFF;
1768
1769         /* Check and alloc MSIX vectors, must be contiguous */
1770         if (!rvu_rsrc_check_contig(&pfvf->msix, nvecs))
1771                 return;
1772
1773         offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs);
1774
1775         /* Config MSIX offset in LF */
1776         rvu_write64(rvu, block->addr, block->msixcfg_reg |
1777                     (lf << block->lfshift), (cfg & ~0x7FFULL) | offset);
1778
1779         /* Update the bitmap as well */
1780         for (vec = 0; vec < nvecs; vec++)
1781                 pfvf->msix_lfmap[offset + vec] = MSIX_BLKLF(block->addr, lf);
1782 }
1783
1784 static void rvu_clear_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf,
1785                                   struct rvu_block *block, int lf)
1786 {
1787         u16 nvecs, vec, offset;
1788         u64 cfg;
1789
1790         cfg = rvu_read64(rvu, block->addr, block->msixcfg_reg |
1791                          (lf << block->lfshift));
1792         nvecs = (cfg >> 12) & 0xFF;
1793
1794         /* Clear MSIX offset in LF */
1795         rvu_write64(rvu, block->addr, block->msixcfg_reg |
1796                     (lf << block->lfshift), cfg & ~0x7FFULL);
1797
1798         offset = rvu_get_msix_offset(rvu, pfvf, block->addr, lf);
1799
1800         /* Update the mapping */
1801         for (vec = 0; vec < nvecs; vec++)
1802                 pfvf->msix_lfmap[offset + vec] = 0;
1803
1804         /* Free the same in MSIX bitmap */
1805         rvu_free_rsrc_contig(&pfvf->msix, nvecs, offset);
1806 }
1807
1808 int rvu_mbox_handler_msix_offset(struct rvu *rvu, struct msg_req *req,
1809                                  struct msix_offset_rsp *rsp)
1810 {
1811         struct rvu_hwinfo *hw = rvu->hw;
1812         u16 pcifunc = req->hdr.pcifunc;
1813         struct rvu_pfvf *pfvf;
1814         int lf, slot, blkaddr;
1815
1816         pfvf = rvu_get_pfvf(rvu, pcifunc);
1817         if (!pfvf->msix.bmap)
1818                 return 0;
1819
1820         /* Set MSIX offsets for each block's LFs attached to this PF/VF */
1821         lf = rvu_get_lf(rvu, &hw->block[BLKADDR_NPA], pcifunc, 0);
1822         rsp->npa_msixoff = rvu_get_msix_offset(rvu, pfvf, BLKADDR_NPA, lf);
1823
1824         /* Get BLKADDR from which LFs are attached to pcifunc */
1825         blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc);
1826         if (blkaddr < 0) {
1827                 rsp->nix_msixoff = MSIX_VECTOR_INVALID;
1828         } else {
1829                 lf = rvu_get_lf(rvu, &hw->block[blkaddr], pcifunc, 0);
1830                 rsp->nix_msixoff = rvu_get_msix_offset(rvu, pfvf, blkaddr, lf);
1831         }
1832
1833         rsp->sso = pfvf->sso;
1834         for (slot = 0; slot < rsp->sso; slot++) {
1835                 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_SSO], pcifunc, slot);
1836                 rsp->sso_msixoff[slot] =
1837                         rvu_get_msix_offset(rvu, pfvf, BLKADDR_SSO, lf);
1838         }
1839
1840         rsp->ssow = pfvf->ssow;
1841         for (slot = 0; slot < rsp->ssow; slot++) {
1842                 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_SSOW], pcifunc, slot);
1843                 rsp->ssow_msixoff[slot] =
1844                         rvu_get_msix_offset(rvu, pfvf, BLKADDR_SSOW, lf);
1845         }
1846
1847         rsp->timlfs = pfvf->timlfs;
1848         for (slot = 0; slot < rsp->timlfs; slot++) {
1849                 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_TIM], pcifunc, slot);
1850                 rsp->timlf_msixoff[slot] =
1851                         rvu_get_msix_offset(rvu, pfvf, BLKADDR_TIM, lf);
1852         }
1853
1854         rsp->cptlfs = pfvf->cptlfs;
1855         for (slot = 0; slot < rsp->cptlfs; slot++) {
1856                 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_CPT0], pcifunc, slot);
1857                 rsp->cptlf_msixoff[slot] =
1858                         rvu_get_msix_offset(rvu, pfvf, BLKADDR_CPT0, lf);
1859         }
1860
1861         rsp->cpt1_lfs = pfvf->cpt1_lfs;
1862         for (slot = 0; slot < rsp->cpt1_lfs; slot++) {
1863                 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_CPT1], pcifunc, slot);
1864                 rsp->cpt1_lf_msixoff[slot] =
1865                         rvu_get_msix_offset(rvu, pfvf, BLKADDR_CPT1, lf);
1866         }
1867
1868         return 0;
1869 }
1870
1871 int rvu_mbox_handler_free_rsrc_cnt(struct rvu *rvu, struct msg_req *req,
1872                                    struct free_rsrcs_rsp *rsp)
1873 {
1874         struct rvu_hwinfo *hw = rvu->hw;
1875         struct rvu_block *block;
1876         struct nix_txsch *txsch;
1877         struct nix_hw *nix_hw;
1878
1879         mutex_lock(&rvu->rsrc_lock);
1880
1881         block = &hw->block[BLKADDR_NPA];
1882         rsp->npa = rvu_rsrc_free_count(&block->lf);
1883
1884         block = &hw->block[BLKADDR_NIX0];
1885         rsp->nix = rvu_rsrc_free_count(&block->lf);
1886
1887         block = &hw->block[BLKADDR_NIX1];
1888         rsp->nix1 = rvu_rsrc_free_count(&block->lf);
1889
1890         block = &hw->block[BLKADDR_SSO];
1891         rsp->sso = rvu_rsrc_free_count(&block->lf);
1892
1893         block = &hw->block[BLKADDR_SSOW];
1894         rsp->ssow = rvu_rsrc_free_count(&block->lf);
1895
1896         block = &hw->block[BLKADDR_TIM];
1897         rsp->tim = rvu_rsrc_free_count(&block->lf);
1898
1899         block = &hw->block[BLKADDR_CPT0];
1900         rsp->cpt = rvu_rsrc_free_count(&block->lf);
1901
1902         block = &hw->block[BLKADDR_CPT1];
1903         rsp->cpt1 = rvu_rsrc_free_count(&block->lf);
1904
1905         if (rvu->hw->cap.nix_fixed_txschq_mapping) {
1906                 rsp->schq[NIX_TXSCH_LVL_SMQ] = 1;
1907                 rsp->schq[NIX_TXSCH_LVL_TL4] = 1;
1908                 rsp->schq[NIX_TXSCH_LVL_TL3] = 1;
1909                 rsp->schq[NIX_TXSCH_LVL_TL2] = 1;
1910                 /* NIX1 */
1911                 if (!is_block_implemented(rvu->hw, BLKADDR_NIX1))
1912                         goto out;
1913                 rsp->schq_nix1[NIX_TXSCH_LVL_SMQ] = 1;
1914                 rsp->schq_nix1[NIX_TXSCH_LVL_TL4] = 1;
1915                 rsp->schq_nix1[NIX_TXSCH_LVL_TL3] = 1;
1916                 rsp->schq_nix1[NIX_TXSCH_LVL_TL2] = 1;
1917         } else {
1918                 nix_hw = get_nix_hw(hw, BLKADDR_NIX0);
1919                 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_SMQ];
1920                 rsp->schq[NIX_TXSCH_LVL_SMQ] =
1921                                 rvu_rsrc_free_count(&txsch->schq);
1922
1923                 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL4];
1924                 rsp->schq[NIX_TXSCH_LVL_TL4] =
1925                                 rvu_rsrc_free_count(&txsch->schq);
1926
1927                 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL3];
1928                 rsp->schq[NIX_TXSCH_LVL_TL3] =
1929                                 rvu_rsrc_free_count(&txsch->schq);
1930
1931                 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL2];
1932                 rsp->schq[NIX_TXSCH_LVL_TL2] =
1933                                 rvu_rsrc_free_count(&txsch->schq);
1934
1935                 if (!is_block_implemented(rvu->hw, BLKADDR_NIX1))
1936                         goto out;
1937
1938                 nix_hw = get_nix_hw(hw, BLKADDR_NIX1);
1939                 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_SMQ];
1940                 rsp->schq_nix1[NIX_TXSCH_LVL_SMQ] =
1941                                 rvu_rsrc_free_count(&txsch->schq);
1942
1943                 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL4];
1944                 rsp->schq_nix1[NIX_TXSCH_LVL_TL4] =
1945                                 rvu_rsrc_free_count(&txsch->schq);
1946
1947                 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL3];
1948                 rsp->schq_nix1[NIX_TXSCH_LVL_TL3] =
1949                                 rvu_rsrc_free_count(&txsch->schq);
1950
1951                 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL2];
1952                 rsp->schq_nix1[NIX_TXSCH_LVL_TL2] =
1953                                 rvu_rsrc_free_count(&txsch->schq);
1954         }
1955
1956         rsp->schq_nix1[NIX_TXSCH_LVL_TL1] = 1;
1957 out:
1958         rsp->schq[NIX_TXSCH_LVL_TL1] = 1;
1959         mutex_unlock(&rvu->rsrc_lock);
1960
1961         return 0;
1962 }
1963
1964 int rvu_mbox_handler_vf_flr(struct rvu *rvu, struct msg_req *req,
1965                             struct msg_rsp *rsp)
1966 {
1967         u16 pcifunc = req->hdr.pcifunc;
1968         u16 vf, numvfs;
1969         u64 cfg;
1970
1971         vf = pcifunc & RVU_PFVF_FUNC_MASK;
1972         cfg = rvu_read64(rvu, BLKADDR_RVUM,
1973                          RVU_PRIV_PFX_CFG(rvu_get_pf(pcifunc)));
1974         numvfs = (cfg >> 12) & 0xFF;
1975
1976         if (vf && vf <= numvfs)
1977                 __rvu_flr_handler(rvu, pcifunc);
1978         else
1979                 return RVU_INVALID_VF_ID;
1980
1981         return 0;
1982 }
1983
1984 int rvu_mbox_handler_get_hw_cap(struct rvu *rvu, struct msg_req *req,
1985                                 struct get_hw_cap_rsp *rsp)
1986 {
1987         struct rvu_hwinfo *hw = rvu->hw;
1988
1989         rsp->nix_fixed_txschq_mapping = hw->cap.nix_fixed_txschq_mapping;
1990         rsp->nix_shaping = hw->cap.nix_shaping;
1991
1992         return 0;
1993 }
1994
1995 int rvu_mbox_handler_set_vf_perm(struct rvu *rvu, struct set_vf_perm *req,
1996                                  struct msg_rsp *rsp)
1997 {
1998         struct rvu_hwinfo *hw = rvu->hw;
1999         u16 pcifunc = req->hdr.pcifunc;
2000         struct rvu_pfvf *pfvf;
2001         int blkaddr, nixlf;
2002         u16 target;
2003
2004         /* Only PF can add VF permissions */
2005         if ((pcifunc & RVU_PFVF_FUNC_MASK) || is_afvf(pcifunc))
2006                 return -EOPNOTSUPP;
2007
2008         target = (pcifunc & ~RVU_PFVF_FUNC_MASK) | (req->vf + 1);
2009         pfvf = rvu_get_pfvf(rvu, target);
2010
2011         if (req->flags & RESET_VF_PERM) {
2012                 pfvf->flags &= RVU_CLEAR_VF_PERM;
2013         } else if (test_bit(PF_SET_VF_TRUSTED, &pfvf->flags) ^
2014                  (req->flags & VF_TRUSTED)) {
2015                 change_bit(PF_SET_VF_TRUSTED, &pfvf->flags);
2016                 /* disable multicast and promisc entries */
2017                 if (!test_bit(PF_SET_VF_TRUSTED, &pfvf->flags)) {
2018                         blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, target);
2019                         if (blkaddr < 0)
2020                                 return 0;
2021                         nixlf = rvu_get_lf(rvu, &hw->block[blkaddr],
2022                                            target, 0);
2023                         if (nixlf < 0)
2024                                 return 0;
2025                         npc_enadis_default_mce_entry(rvu, target, nixlf,
2026                                                      NIXLF_ALLMULTI_ENTRY,
2027                                                      false);
2028                         npc_enadis_default_mce_entry(rvu, target, nixlf,
2029                                                      NIXLF_PROMISC_ENTRY,
2030                                                      false);
2031                 }
2032         }
2033
2034         return 0;
2035 }
2036
2037 static int rvu_process_mbox_msg(struct otx2_mbox *mbox, int devid,
2038                                 struct mbox_msghdr *req)
2039 {
2040         struct rvu *rvu = pci_get_drvdata(mbox->pdev);
2041
2042         /* Check if valid, if not reply with a invalid msg */
2043         if (req->sig != OTX2_MBOX_REQ_SIG)
2044                 goto bad_message;
2045
2046         switch (req->id) {
2047 #define M(_name, _id, _fn_name, _req_type, _rsp_type)                   \
2048         case _id: {                                                     \
2049                 struct _rsp_type *rsp;                                  \
2050                 int err;                                                \
2051                                                                         \
2052                 rsp = (struct _rsp_type *)otx2_mbox_alloc_msg(          \
2053                         mbox, devid,                                    \
2054                         sizeof(struct _rsp_type));                      \
2055                 /* some handlers should complete even if reply */       \
2056                 /* could not be allocated */                            \
2057                 if (!rsp &&                                             \
2058                     _id != MBOX_MSG_DETACH_RESOURCES &&                 \
2059                     _id != MBOX_MSG_NIX_TXSCH_FREE &&                   \
2060                     _id != MBOX_MSG_VF_FLR)                             \
2061                         return -ENOMEM;                                 \
2062                 if (rsp) {                                              \
2063                         rsp->hdr.id = _id;                              \
2064                         rsp->hdr.sig = OTX2_MBOX_RSP_SIG;               \
2065                         rsp->hdr.pcifunc = req->pcifunc;                \
2066                         rsp->hdr.rc = 0;                                \
2067                 }                                                       \
2068                                                                         \
2069                 err = rvu_mbox_handler_ ## _fn_name(rvu,                \
2070                                                     (struct _req_type *)req, \
2071                                                     rsp);               \
2072                 if (rsp && err)                                         \
2073                         rsp->hdr.rc = err;                              \
2074                                                                         \
2075                 trace_otx2_msg_process(mbox->pdev, _id, err);           \
2076                 return rsp ? err : -ENOMEM;                             \
2077         }
2078 MBOX_MESSAGES
2079 #undef M
2080
2081 bad_message:
2082         default:
2083                 otx2_reply_invalid_msg(mbox, devid, req->pcifunc, req->id);
2084                 return -ENODEV;
2085         }
2086 }
2087
2088 static void __rvu_mbox_handler(struct rvu_work *mwork, int type)
2089 {
2090         struct rvu *rvu = mwork->rvu;
2091         int offset, err, id, devid;
2092         struct otx2_mbox_dev *mdev;
2093         struct mbox_hdr *req_hdr;
2094         struct mbox_msghdr *msg;
2095         struct mbox_wq_info *mw;
2096         struct otx2_mbox *mbox;
2097
2098         switch (type) {
2099         case TYPE_AFPF:
2100                 mw = &rvu->afpf_wq_info;
2101                 break;
2102         case TYPE_AFVF:
2103                 mw = &rvu->afvf_wq_info;
2104                 break;
2105         default:
2106                 return;
2107         }
2108
2109         devid = mwork - mw->mbox_wrk;
2110         mbox = &mw->mbox;
2111         mdev = &mbox->dev[devid];
2112
2113         /* Process received mbox messages */
2114         req_hdr = mdev->mbase + mbox->rx_start;
2115         if (mw->mbox_wrk[devid].num_msgs == 0)
2116                 return;
2117
2118         offset = mbox->rx_start + ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN);
2119
2120         for (id = 0; id < mw->mbox_wrk[devid].num_msgs; id++) {
2121                 msg = mdev->mbase + offset;
2122
2123                 /* Set which PF/VF sent this message based on mbox IRQ */
2124                 switch (type) {
2125                 case TYPE_AFPF:
2126                         msg->pcifunc &=
2127                                 ~(RVU_PFVF_PF_MASK << RVU_PFVF_PF_SHIFT);
2128                         msg->pcifunc |= (devid << RVU_PFVF_PF_SHIFT);
2129                         break;
2130                 case TYPE_AFVF:
2131                         msg->pcifunc &=
2132                                 ~(RVU_PFVF_FUNC_MASK << RVU_PFVF_FUNC_SHIFT);
2133                         msg->pcifunc |= (devid << RVU_PFVF_FUNC_SHIFT) + 1;
2134                         break;
2135                 }
2136
2137                 err = rvu_process_mbox_msg(mbox, devid, msg);
2138                 if (!err) {
2139                         offset = mbox->rx_start + msg->next_msgoff;
2140                         continue;
2141                 }
2142
2143                 if (msg->pcifunc & RVU_PFVF_FUNC_MASK)
2144                         dev_warn(rvu->dev, "Error %d when processing message %s (0x%x) from PF%d:VF%d\n",
2145                                  err, otx2_mbox_id2name(msg->id),
2146                                  msg->id, rvu_get_pf(msg->pcifunc),
2147                                  (msg->pcifunc & RVU_PFVF_FUNC_MASK) - 1);
2148                 else
2149                         dev_warn(rvu->dev, "Error %d when processing message %s (0x%x) from PF%d\n",
2150                                  err, otx2_mbox_id2name(msg->id),
2151                                  msg->id, devid);
2152         }
2153         mw->mbox_wrk[devid].num_msgs = 0;
2154
2155         /* Send mbox responses to VF/PF */
2156         otx2_mbox_msg_send(mbox, devid);
2157 }
2158
2159 static inline void rvu_afpf_mbox_handler(struct work_struct *work)
2160 {
2161         struct rvu_work *mwork = container_of(work, struct rvu_work, work);
2162
2163         __rvu_mbox_handler(mwork, TYPE_AFPF);
2164 }
2165
2166 static inline void rvu_afvf_mbox_handler(struct work_struct *work)
2167 {
2168         struct rvu_work *mwork = container_of(work, struct rvu_work, work);
2169
2170         __rvu_mbox_handler(mwork, TYPE_AFVF);
2171 }
2172
2173 static void __rvu_mbox_up_handler(struct rvu_work *mwork, int type)
2174 {
2175         struct rvu *rvu = mwork->rvu;
2176         struct otx2_mbox_dev *mdev;
2177         struct mbox_hdr *rsp_hdr;
2178         struct mbox_msghdr *msg;
2179         struct mbox_wq_info *mw;
2180         struct otx2_mbox *mbox;
2181         int offset, id, devid;
2182
2183         switch (type) {
2184         case TYPE_AFPF:
2185                 mw = &rvu->afpf_wq_info;
2186                 break;
2187         case TYPE_AFVF:
2188                 mw = &rvu->afvf_wq_info;
2189                 break;
2190         default:
2191                 return;
2192         }
2193
2194         devid = mwork - mw->mbox_wrk_up;
2195         mbox = &mw->mbox_up;
2196         mdev = &mbox->dev[devid];
2197
2198         rsp_hdr = mdev->mbase + mbox->rx_start;
2199         if (mw->mbox_wrk_up[devid].up_num_msgs == 0) {
2200                 dev_warn(rvu->dev, "mbox up handler: num_msgs = 0\n");
2201                 return;
2202         }
2203
2204         offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN);
2205
2206         for (id = 0; id < mw->mbox_wrk_up[devid].up_num_msgs; id++) {
2207                 msg = mdev->mbase + offset;
2208
2209                 if (msg->id >= MBOX_MSG_MAX) {
2210                         dev_err(rvu->dev,
2211                                 "Mbox msg with unknown ID 0x%x\n", msg->id);
2212                         goto end;
2213                 }
2214
2215                 if (msg->sig != OTX2_MBOX_RSP_SIG) {
2216                         dev_err(rvu->dev,
2217                                 "Mbox msg with wrong signature %x, ID 0x%x\n",
2218                                 msg->sig, msg->id);
2219                         goto end;
2220                 }
2221
2222                 switch (msg->id) {
2223                 case MBOX_MSG_CGX_LINK_EVENT:
2224                         break;
2225                 default:
2226                         if (msg->rc)
2227                                 dev_err(rvu->dev,
2228                                         "Mbox msg response has err %d, ID 0x%x\n",
2229                                         msg->rc, msg->id);
2230                         break;
2231                 }
2232 end:
2233                 offset = mbox->rx_start + msg->next_msgoff;
2234                 mdev->msgs_acked++;
2235         }
2236         mw->mbox_wrk_up[devid].up_num_msgs = 0;
2237
2238         otx2_mbox_reset(mbox, devid);
2239 }
2240
2241 static inline void rvu_afpf_mbox_up_handler(struct work_struct *work)
2242 {
2243         struct rvu_work *mwork = container_of(work, struct rvu_work, work);
2244
2245         __rvu_mbox_up_handler(mwork, TYPE_AFPF);
2246 }
2247
2248 static inline void rvu_afvf_mbox_up_handler(struct work_struct *work)
2249 {
2250         struct rvu_work *mwork = container_of(work, struct rvu_work, work);
2251
2252         __rvu_mbox_up_handler(mwork, TYPE_AFVF);
2253 }
2254
2255 static int rvu_get_mbox_regions(struct rvu *rvu, void **mbox_addr,
2256                                 int num, int type)
2257 {
2258         struct rvu_hwinfo *hw = rvu->hw;
2259         int region;
2260         u64 bar4;
2261
2262         /* For cn10k platform VF mailbox regions of a PF follows after the
2263          * PF <-> AF mailbox region. Whereas for Octeontx2 it is read from
2264          * RVU_PF_VF_BAR4_ADDR register.
2265          */
2266         if (type == TYPE_AFVF) {
2267                 for (region = 0; region < num; region++) {
2268                         if (hw->cap.per_pf_mbox_regs) {
2269                                 bar4 = rvu_read64(rvu, BLKADDR_RVUM,
2270                                                   RVU_AF_PFX_BAR4_ADDR(0)) +
2271                                                   MBOX_SIZE;
2272                                 bar4 += region * MBOX_SIZE;
2273                         } else {
2274                                 bar4 = rvupf_read64(rvu, RVU_PF_VF_BAR4_ADDR);
2275                                 bar4 += region * MBOX_SIZE;
2276                         }
2277                         mbox_addr[region] = (void *)ioremap_wc(bar4, MBOX_SIZE);
2278                         if (!mbox_addr[region])
2279                                 goto error;
2280                 }
2281                 return 0;
2282         }
2283
2284         /* For cn10k platform AF <-> PF mailbox region of a PF is read from per
2285          * PF registers. Whereas for Octeontx2 it is read from
2286          * RVU_AF_PF_BAR4_ADDR register.
2287          */
2288         for (region = 0; region < num; region++) {
2289                 if (hw->cap.per_pf_mbox_regs) {
2290                         bar4 = rvu_read64(rvu, BLKADDR_RVUM,
2291                                           RVU_AF_PFX_BAR4_ADDR(region));
2292                 } else {
2293                         bar4 = rvu_read64(rvu, BLKADDR_RVUM,
2294                                           RVU_AF_PF_BAR4_ADDR);
2295                         bar4 += region * MBOX_SIZE;
2296                 }
2297                 mbox_addr[region] = (void *)ioremap_wc(bar4, MBOX_SIZE);
2298                 if (!mbox_addr[region])
2299                         goto error;
2300         }
2301         return 0;
2302
2303 error:
2304         while (region--)
2305                 iounmap((void __iomem *)mbox_addr[region]);
2306         return -ENOMEM;
2307 }
2308
2309 static int rvu_mbox_init(struct rvu *rvu, struct mbox_wq_info *mw,
2310                          int type, int num,
2311                          void (mbox_handler)(struct work_struct *),
2312                          void (mbox_up_handler)(struct work_struct *))
2313 {
2314         int err = -EINVAL, i, dir, dir_up;
2315         void __iomem *reg_base;
2316         struct rvu_work *mwork;
2317         void **mbox_regions;
2318         const char *name;
2319
2320         mbox_regions = kcalloc(num, sizeof(void *), GFP_KERNEL);
2321         if (!mbox_regions)
2322                 return -ENOMEM;
2323
2324         switch (type) {
2325         case TYPE_AFPF:
2326                 name = "rvu_afpf_mailbox";
2327                 dir = MBOX_DIR_AFPF;
2328                 dir_up = MBOX_DIR_AFPF_UP;
2329                 reg_base = rvu->afreg_base;
2330                 err = rvu_get_mbox_regions(rvu, mbox_regions, num, TYPE_AFPF);
2331                 if (err)
2332                         goto free_regions;
2333                 break;
2334         case TYPE_AFVF:
2335                 name = "rvu_afvf_mailbox";
2336                 dir = MBOX_DIR_PFVF;
2337                 dir_up = MBOX_DIR_PFVF_UP;
2338                 reg_base = rvu->pfreg_base;
2339                 err = rvu_get_mbox_regions(rvu, mbox_regions, num, TYPE_AFVF);
2340                 if (err)
2341                         goto free_regions;
2342                 break;
2343         default:
2344                 return err;
2345         }
2346
2347         mw->mbox_wq = alloc_workqueue(name,
2348                                       WQ_UNBOUND | WQ_HIGHPRI | WQ_MEM_RECLAIM,
2349                                       num);
2350         if (!mw->mbox_wq) {
2351                 err = -ENOMEM;
2352                 goto unmap_regions;
2353         }
2354
2355         mw->mbox_wrk = devm_kcalloc(rvu->dev, num,
2356                                     sizeof(struct rvu_work), GFP_KERNEL);
2357         if (!mw->mbox_wrk) {
2358                 err = -ENOMEM;
2359                 goto exit;
2360         }
2361
2362         mw->mbox_wrk_up = devm_kcalloc(rvu->dev, num,
2363                                        sizeof(struct rvu_work), GFP_KERNEL);
2364         if (!mw->mbox_wrk_up) {
2365                 err = -ENOMEM;
2366                 goto exit;
2367         }
2368
2369         err = otx2_mbox_regions_init(&mw->mbox, mbox_regions, rvu->pdev,
2370                                      reg_base, dir, num);
2371         if (err)
2372                 goto exit;
2373
2374         err = otx2_mbox_regions_init(&mw->mbox_up, mbox_regions, rvu->pdev,
2375                                      reg_base, dir_up, num);
2376         if (err)
2377                 goto exit;
2378
2379         for (i = 0; i < num; i++) {
2380                 mwork = &mw->mbox_wrk[i];
2381                 mwork->rvu = rvu;
2382                 INIT_WORK(&mwork->work, mbox_handler);
2383
2384                 mwork = &mw->mbox_wrk_up[i];
2385                 mwork->rvu = rvu;
2386                 INIT_WORK(&mwork->work, mbox_up_handler);
2387         }
2388         kfree(mbox_regions);
2389         return 0;
2390
2391 exit:
2392         destroy_workqueue(mw->mbox_wq);
2393 unmap_regions:
2394         while (num--)
2395                 iounmap((void __iomem *)mbox_regions[num]);
2396 free_regions:
2397         kfree(mbox_regions);
2398         return err;
2399 }
2400
2401 static void rvu_mbox_destroy(struct mbox_wq_info *mw)
2402 {
2403         struct otx2_mbox *mbox = &mw->mbox;
2404         struct otx2_mbox_dev *mdev;
2405         int devid;
2406
2407         if (mw->mbox_wq) {
2408                 destroy_workqueue(mw->mbox_wq);
2409                 mw->mbox_wq = NULL;
2410         }
2411
2412         for (devid = 0; devid < mbox->ndevs; devid++) {
2413                 mdev = &mbox->dev[devid];
2414                 if (mdev->hwbase)
2415                         iounmap((void __iomem *)mdev->hwbase);
2416         }
2417
2418         otx2_mbox_destroy(&mw->mbox);
2419         otx2_mbox_destroy(&mw->mbox_up);
2420 }
2421
2422 static void rvu_queue_work(struct mbox_wq_info *mw, int first,
2423                            int mdevs, u64 intr)
2424 {
2425         struct otx2_mbox_dev *mdev;
2426         struct otx2_mbox *mbox;
2427         struct mbox_hdr *hdr;
2428         int i;
2429
2430         for (i = first; i < mdevs; i++) {
2431                 /* start from 0 */
2432                 if (!(intr & BIT_ULL(i - first)))
2433                         continue;
2434
2435                 mbox = &mw->mbox;
2436                 mdev = &mbox->dev[i];
2437                 hdr = mdev->mbase + mbox->rx_start;
2438
2439                 /*The hdr->num_msgs is set to zero immediately in the interrupt
2440                  * handler to  ensure that it holds a correct value next time
2441                  * when the interrupt handler is called.
2442                  * pf->mbox.num_msgs holds the data for use in pfaf_mbox_handler
2443                  * pf>mbox.up_num_msgs holds the data for use in
2444                  * pfaf_mbox_up_handler.
2445                  */
2446
2447                 if (hdr->num_msgs) {
2448                         mw->mbox_wrk[i].num_msgs = hdr->num_msgs;
2449                         hdr->num_msgs = 0;
2450                         queue_work(mw->mbox_wq, &mw->mbox_wrk[i].work);
2451                 }
2452                 mbox = &mw->mbox_up;
2453                 mdev = &mbox->dev[i];
2454                 hdr = mdev->mbase + mbox->rx_start;
2455                 if (hdr->num_msgs) {
2456                         mw->mbox_wrk_up[i].up_num_msgs = hdr->num_msgs;
2457                         hdr->num_msgs = 0;
2458                         queue_work(mw->mbox_wq, &mw->mbox_wrk_up[i].work);
2459                 }
2460         }
2461 }
2462
2463 static irqreturn_t rvu_mbox_intr_handler(int irq, void *rvu_irq)
2464 {
2465         struct rvu *rvu = (struct rvu *)rvu_irq;
2466         int vfs = rvu->vfs;
2467         u64 intr;
2468
2469         intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT);
2470         /* Clear interrupts */
2471         rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT, intr);
2472         if (intr)
2473                 trace_otx2_msg_interrupt(rvu->pdev, "PF(s) to AF", intr);
2474
2475         /* Sync with mbox memory region */
2476         rmb();
2477
2478         rvu_queue_work(&rvu->afpf_wq_info, 0, rvu->hw->total_pfs, intr);
2479
2480         /* Handle VF interrupts */
2481         if (vfs > 64) {
2482                 intr = rvupf_read64(rvu, RVU_PF_VFPF_MBOX_INTX(1));
2483                 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(1), intr);
2484
2485                 rvu_queue_work(&rvu->afvf_wq_info, 64, vfs, intr);
2486                 vfs -= 64;
2487         }
2488
2489         intr = rvupf_read64(rvu, RVU_PF_VFPF_MBOX_INTX(0));
2490         rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(0), intr);
2491         if (intr)
2492                 trace_otx2_msg_interrupt(rvu->pdev, "VF(s) to AF", intr);
2493
2494         rvu_queue_work(&rvu->afvf_wq_info, 0, vfs, intr);
2495
2496         return IRQ_HANDLED;
2497 }
2498
2499 static void rvu_enable_mbox_intr(struct rvu *rvu)
2500 {
2501         struct rvu_hwinfo *hw = rvu->hw;
2502
2503         /* Clear spurious irqs, if any */
2504         rvu_write64(rvu, BLKADDR_RVUM,
2505                     RVU_AF_PFAF_MBOX_INT, INTR_MASK(hw->total_pfs));
2506
2507         /* Enable mailbox interrupt for all PFs except PF0 i.e AF itself */
2508         rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT_ENA_W1S,
2509                     INTR_MASK(hw->total_pfs) & ~1ULL);
2510 }
2511
2512 static void rvu_blklf_teardown(struct rvu *rvu, u16 pcifunc, u8 blkaddr)
2513 {
2514         struct rvu_block *block;
2515         int slot, lf, num_lfs;
2516         int err;
2517
2518         block = &rvu->hw->block[blkaddr];
2519         num_lfs = rvu_get_rsrc_mapcount(rvu_get_pfvf(rvu, pcifunc),
2520                                         block->addr);
2521         if (!num_lfs)
2522                 return;
2523         for (slot = 0; slot < num_lfs; slot++) {
2524                 lf = rvu_get_lf(rvu, block, pcifunc, slot);
2525                 if (lf < 0)
2526                         continue;
2527
2528                 /* Cleanup LF and reset it */
2529                 if (block->addr == BLKADDR_NIX0 || block->addr == BLKADDR_NIX1)
2530                         rvu_nix_lf_teardown(rvu, pcifunc, block->addr, lf);
2531                 else if (block->addr == BLKADDR_NPA)
2532                         rvu_npa_lf_teardown(rvu, pcifunc, lf);
2533                 else if ((block->addr == BLKADDR_CPT0) ||
2534                          (block->addr == BLKADDR_CPT1))
2535                         rvu_cpt_lf_teardown(rvu, pcifunc, block->addr, lf,
2536                                             slot);
2537
2538                 err = rvu_lf_reset(rvu, block, lf);
2539                 if (err) {
2540                         dev_err(rvu->dev, "Failed to reset blkaddr %d LF%d\n",
2541                                 block->addr, lf);
2542                 }
2543         }
2544 }
2545
2546 static void __rvu_flr_handler(struct rvu *rvu, u16 pcifunc)
2547 {
2548         mutex_lock(&rvu->flr_lock);
2549         /* Reset order should reflect inter-block dependencies:
2550          * 1. Reset any packet/work sources (NIX, CPT, TIM)
2551          * 2. Flush and reset SSO/SSOW
2552          * 3. Cleanup pools (NPA)
2553          */
2554         rvu_blklf_teardown(rvu, pcifunc, BLKADDR_NIX0);
2555         rvu_blklf_teardown(rvu, pcifunc, BLKADDR_NIX1);
2556         rvu_blklf_teardown(rvu, pcifunc, BLKADDR_CPT0);
2557         rvu_blklf_teardown(rvu, pcifunc, BLKADDR_CPT1);
2558         rvu_blklf_teardown(rvu, pcifunc, BLKADDR_TIM);
2559         rvu_blklf_teardown(rvu, pcifunc, BLKADDR_SSOW);
2560         rvu_blklf_teardown(rvu, pcifunc, BLKADDR_SSO);
2561         rvu_blklf_teardown(rvu, pcifunc, BLKADDR_NPA);
2562         rvu_reset_lmt_map_tbl(rvu, pcifunc);
2563         rvu_detach_rsrcs(rvu, NULL, pcifunc);
2564         mutex_unlock(&rvu->flr_lock);
2565 }
2566
2567 static void rvu_afvf_flr_handler(struct rvu *rvu, int vf)
2568 {
2569         int reg = 0;
2570
2571         /* pcifunc = 0(PF0) | (vf + 1) */
2572         __rvu_flr_handler(rvu, vf + 1);
2573
2574         if (vf >= 64) {
2575                 reg = 1;
2576                 vf = vf - 64;
2577         }
2578
2579         /* Signal FLR finish and enable IRQ */
2580         rvupf_write64(rvu, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf));
2581         rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(reg), BIT_ULL(vf));
2582 }
2583
2584 static void rvu_flr_handler(struct work_struct *work)
2585 {
2586         struct rvu_work *flrwork = container_of(work, struct rvu_work, work);
2587         struct rvu *rvu = flrwork->rvu;
2588         u16 pcifunc, numvfs, vf;
2589         u64 cfg;
2590         int pf;
2591
2592         pf = flrwork - rvu->flr_wrk;
2593         if (pf >= rvu->hw->total_pfs) {
2594                 rvu_afvf_flr_handler(rvu, pf - rvu->hw->total_pfs);
2595                 return;
2596         }
2597
2598         cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf));
2599         numvfs = (cfg >> 12) & 0xFF;
2600         pcifunc  = pf << RVU_PFVF_PF_SHIFT;
2601
2602         for (vf = 0; vf < numvfs; vf++)
2603                 __rvu_flr_handler(rvu, (pcifunc | (vf + 1)));
2604
2605         __rvu_flr_handler(rvu, pcifunc);
2606
2607         /* Signal FLR finish */
2608         rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFTRPEND, BIT_ULL(pf));
2609
2610         /* Enable interrupt */
2611         rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1S,  BIT_ULL(pf));
2612 }
2613
2614 static void rvu_afvf_queue_flr_work(struct rvu *rvu, int start_vf, int numvfs)
2615 {
2616         int dev, vf, reg = 0;
2617         u64 intr;
2618
2619         if (start_vf >= 64)
2620                 reg = 1;
2621
2622         intr = rvupf_read64(rvu, RVU_PF_VFFLR_INTX(reg));
2623         if (!intr)
2624                 return;
2625
2626         for (vf = 0; vf < numvfs; vf++) {
2627                 if (!(intr & BIT_ULL(vf)))
2628                         continue;
2629                 /* Clear and disable the interrupt */
2630                 rvupf_write64(rvu, RVU_PF_VFFLR_INTX(reg), BIT_ULL(vf));
2631                 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(reg), BIT_ULL(vf));
2632
2633                 dev = vf + start_vf + rvu->hw->total_pfs;
2634                 queue_work(rvu->flr_wq, &rvu->flr_wrk[dev].work);
2635         }
2636 }
2637
2638 static irqreturn_t rvu_flr_intr_handler(int irq, void *rvu_irq)
2639 {
2640         struct rvu *rvu = (struct rvu *)rvu_irq;
2641         u64 intr;
2642         u8  pf;
2643
2644         intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT);
2645         if (!intr)
2646                 goto afvf_flr;
2647
2648         for (pf = 0; pf < rvu->hw->total_pfs; pf++) {
2649                 if (intr & (1ULL << pf)) {
2650                         /* clear interrupt */
2651                         rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT,
2652                                     BIT_ULL(pf));
2653                         /* Disable the interrupt */
2654                         rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1C,
2655                                     BIT_ULL(pf));
2656                         /* PF is already dead do only AF related operations */
2657                         queue_work(rvu->flr_wq, &rvu->flr_wrk[pf].work);
2658                 }
2659         }
2660
2661 afvf_flr:
2662         rvu_afvf_queue_flr_work(rvu, 0, 64);
2663         if (rvu->vfs > 64)
2664                 rvu_afvf_queue_flr_work(rvu, 64, rvu->vfs - 64);
2665
2666         return IRQ_HANDLED;
2667 }
2668
2669 static void rvu_me_handle_vfset(struct rvu *rvu, int idx, u64 intr)
2670 {
2671         int vf;
2672
2673         /* Nothing to be done here other than clearing the
2674          * TRPEND bit.
2675          */
2676         for (vf = 0; vf < 64; vf++) {
2677                 if (intr & (1ULL << vf)) {
2678                         /* clear the trpend due to ME(master enable) */
2679                         rvupf_write64(rvu, RVU_PF_VFTRPENDX(idx), BIT_ULL(vf));
2680                         /* clear interrupt */
2681                         rvupf_write64(rvu, RVU_PF_VFME_INTX(idx), BIT_ULL(vf));
2682                 }
2683         }
2684 }
2685
2686 /* Handles ME interrupts from VFs of AF */
2687 static irqreturn_t rvu_me_vf_intr_handler(int irq, void *rvu_irq)
2688 {
2689         struct rvu *rvu = (struct rvu *)rvu_irq;
2690         int vfset;
2691         u64 intr;
2692
2693         intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT);
2694
2695         for (vfset = 0; vfset <= 1; vfset++) {
2696                 intr = rvupf_read64(rvu, RVU_PF_VFME_INTX(vfset));
2697                 if (intr)
2698                         rvu_me_handle_vfset(rvu, vfset, intr);
2699         }
2700
2701         return IRQ_HANDLED;
2702 }
2703
2704 /* Handles ME interrupts from PFs */
2705 static irqreturn_t rvu_me_pf_intr_handler(int irq, void *rvu_irq)
2706 {
2707         struct rvu *rvu = (struct rvu *)rvu_irq;
2708         u64 intr;
2709         u8  pf;
2710
2711         intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT);
2712
2713         /* Nothing to be done here other than clearing the
2714          * TRPEND bit.
2715          */
2716         for (pf = 0; pf < rvu->hw->total_pfs; pf++) {
2717                 if (intr & (1ULL << pf)) {
2718                         /* clear the trpend due to ME(master enable) */
2719                         rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFTRPEND,
2720                                     BIT_ULL(pf));
2721                         /* clear interrupt */
2722                         rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT,
2723                                     BIT_ULL(pf));
2724                 }
2725         }
2726
2727         return IRQ_HANDLED;
2728 }
2729
2730 static void rvu_unregister_interrupts(struct rvu *rvu)
2731 {
2732         int irq;
2733
2734         rvu_cpt_unregister_interrupts(rvu);
2735
2736         /* Disable the Mbox interrupt */
2737         rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT_ENA_W1C,
2738                     INTR_MASK(rvu->hw->total_pfs) & ~1ULL);
2739
2740         /* Disable the PF FLR interrupt */
2741         rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1C,
2742                     INTR_MASK(rvu->hw->total_pfs) & ~1ULL);
2743
2744         /* Disable the PF ME interrupt */
2745         rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT_ENA_W1C,
2746                     INTR_MASK(rvu->hw->total_pfs) & ~1ULL);
2747
2748         for (irq = 0; irq < rvu->num_vec; irq++) {
2749                 if (rvu->irq_allocated[irq]) {
2750                         free_irq(pci_irq_vector(rvu->pdev, irq), rvu);
2751                         rvu->irq_allocated[irq] = false;
2752                 }
2753         }
2754
2755         pci_free_irq_vectors(rvu->pdev);
2756         rvu->num_vec = 0;
2757 }
2758
2759 static int rvu_afvf_msix_vectors_num_ok(struct rvu *rvu)
2760 {
2761         struct rvu_pfvf *pfvf = &rvu->pf[0];
2762         int offset;
2763
2764         pfvf = &rvu->pf[0];
2765         offset = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_INT_CFG(0)) & 0x3ff;
2766
2767         /* Make sure there are enough MSIX vectors configured so that
2768          * VF interrupts can be handled. Offset equal to zero means
2769          * that PF vectors are not configured and overlapping AF vectors.
2770          */
2771         return (pfvf->msix.max >= RVU_AF_INT_VEC_CNT + RVU_PF_INT_VEC_CNT) &&
2772                offset;
2773 }
2774
2775 static int rvu_register_interrupts(struct rvu *rvu)
2776 {
2777         int ret, offset, pf_vec_start;
2778
2779         rvu->num_vec = pci_msix_vec_count(rvu->pdev);
2780
2781         rvu->irq_name = devm_kmalloc_array(rvu->dev, rvu->num_vec,
2782                                            NAME_SIZE, GFP_KERNEL);
2783         if (!rvu->irq_name)
2784                 return -ENOMEM;
2785
2786         rvu->irq_allocated = devm_kcalloc(rvu->dev, rvu->num_vec,
2787                                           sizeof(bool), GFP_KERNEL);
2788         if (!rvu->irq_allocated)
2789                 return -ENOMEM;
2790
2791         /* Enable MSI-X */
2792         ret = pci_alloc_irq_vectors(rvu->pdev, rvu->num_vec,
2793                                     rvu->num_vec, PCI_IRQ_MSIX);
2794         if (ret < 0) {
2795                 dev_err(rvu->dev,
2796                         "RVUAF: Request for %d msix vectors failed, ret %d\n",
2797                         rvu->num_vec, ret);
2798                 return ret;
2799         }
2800
2801         /* Register mailbox interrupt handler */
2802         sprintf(&rvu->irq_name[RVU_AF_INT_VEC_MBOX * NAME_SIZE], "RVUAF Mbox");
2803         ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_MBOX),
2804                           rvu_mbox_intr_handler, 0,
2805                           &rvu->irq_name[RVU_AF_INT_VEC_MBOX * NAME_SIZE], rvu);
2806         if (ret) {
2807                 dev_err(rvu->dev,
2808                         "RVUAF: IRQ registration failed for mbox irq\n");
2809                 goto fail;
2810         }
2811
2812         rvu->irq_allocated[RVU_AF_INT_VEC_MBOX] = true;
2813
2814         /* Enable mailbox interrupts from all PFs */
2815         rvu_enable_mbox_intr(rvu);
2816
2817         /* Register FLR interrupt handler */
2818         sprintf(&rvu->irq_name[RVU_AF_INT_VEC_PFFLR * NAME_SIZE],
2819                 "RVUAF FLR");
2820         ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_PFFLR),
2821                           rvu_flr_intr_handler, 0,
2822                           &rvu->irq_name[RVU_AF_INT_VEC_PFFLR * NAME_SIZE],
2823                           rvu);
2824         if (ret) {
2825                 dev_err(rvu->dev,
2826                         "RVUAF: IRQ registration failed for FLR\n");
2827                 goto fail;
2828         }
2829         rvu->irq_allocated[RVU_AF_INT_VEC_PFFLR] = true;
2830
2831         /* Enable FLR interrupt for all PFs*/
2832         rvu_write64(rvu, BLKADDR_RVUM,
2833                     RVU_AF_PFFLR_INT, INTR_MASK(rvu->hw->total_pfs));
2834
2835         rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1S,
2836                     INTR_MASK(rvu->hw->total_pfs) & ~1ULL);
2837
2838         /* Register ME interrupt handler */
2839         sprintf(&rvu->irq_name[RVU_AF_INT_VEC_PFME * NAME_SIZE],
2840                 "RVUAF ME");
2841         ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_PFME),
2842                           rvu_me_pf_intr_handler, 0,
2843                           &rvu->irq_name[RVU_AF_INT_VEC_PFME * NAME_SIZE],
2844                           rvu);
2845         if (ret) {
2846                 dev_err(rvu->dev,
2847                         "RVUAF: IRQ registration failed for ME\n");
2848         }
2849         rvu->irq_allocated[RVU_AF_INT_VEC_PFME] = true;
2850
2851         /* Clear TRPEND bit for all PF */
2852         rvu_write64(rvu, BLKADDR_RVUM,
2853                     RVU_AF_PFTRPEND, INTR_MASK(rvu->hw->total_pfs));
2854         /* Enable ME interrupt for all PFs*/
2855         rvu_write64(rvu, BLKADDR_RVUM,
2856                     RVU_AF_PFME_INT, INTR_MASK(rvu->hw->total_pfs));
2857
2858         rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT_ENA_W1S,
2859                     INTR_MASK(rvu->hw->total_pfs) & ~1ULL);
2860
2861         if (!rvu_afvf_msix_vectors_num_ok(rvu))
2862                 return 0;
2863
2864         /* Get PF MSIX vectors offset. */
2865         pf_vec_start = rvu_read64(rvu, BLKADDR_RVUM,
2866                                   RVU_PRIV_PFX_INT_CFG(0)) & 0x3ff;
2867
2868         /* Register MBOX0 interrupt. */
2869         offset = pf_vec_start + RVU_PF_INT_VEC_VFPF_MBOX0;
2870         sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF Mbox0");
2871         ret = request_irq(pci_irq_vector(rvu->pdev, offset),
2872                           rvu_mbox_intr_handler, 0,
2873                           &rvu->irq_name[offset * NAME_SIZE],
2874                           rvu);
2875         if (ret)
2876                 dev_err(rvu->dev,
2877                         "RVUAF: IRQ registration failed for Mbox0\n");
2878
2879         rvu->irq_allocated[offset] = true;
2880
2881         /* Register MBOX1 interrupt. MBOX1 IRQ number follows MBOX0 so
2882          * simply increment current offset by 1.
2883          */
2884         offset = pf_vec_start + RVU_PF_INT_VEC_VFPF_MBOX1;
2885         sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF Mbox1");
2886         ret = request_irq(pci_irq_vector(rvu->pdev, offset),
2887                           rvu_mbox_intr_handler, 0,
2888                           &rvu->irq_name[offset * NAME_SIZE],
2889                           rvu);
2890         if (ret)
2891                 dev_err(rvu->dev,
2892                         "RVUAF: IRQ registration failed for Mbox1\n");
2893
2894         rvu->irq_allocated[offset] = true;
2895
2896         /* Register FLR interrupt handler for AF's VFs */
2897         offset = pf_vec_start + RVU_PF_INT_VEC_VFFLR0;
2898         sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF FLR0");
2899         ret = request_irq(pci_irq_vector(rvu->pdev, offset),
2900                           rvu_flr_intr_handler, 0,
2901                           &rvu->irq_name[offset * NAME_SIZE], rvu);
2902         if (ret) {
2903                 dev_err(rvu->dev,
2904                         "RVUAF: IRQ registration failed for RVUAFVF FLR0\n");
2905                 goto fail;
2906         }
2907         rvu->irq_allocated[offset] = true;
2908
2909         offset = pf_vec_start + RVU_PF_INT_VEC_VFFLR1;
2910         sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF FLR1");
2911         ret = request_irq(pci_irq_vector(rvu->pdev, offset),
2912                           rvu_flr_intr_handler, 0,
2913                           &rvu->irq_name[offset * NAME_SIZE], rvu);
2914         if (ret) {
2915                 dev_err(rvu->dev,
2916                         "RVUAF: IRQ registration failed for RVUAFVF FLR1\n");
2917                 goto fail;
2918         }
2919         rvu->irq_allocated[offset] = true;
2920
2921         /* Register ME interrupt handler for AF's VFs */
2922         offset = pf_vec_start + RVU_PF_INT_VEC_VFME0;
2923         sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF ME0");
2924         ret = request_irq(pci_irq_vector(rvu->pdev, offset),
2925                           rvu_me_vf_intr_handler, 0,
2926                           &rvu->irq_name[offset * NAME_SIZE], rvu);
2927         if (ret) {
2928                 dev_err(rvu->dev,
2929                         "RVUAF: IRQ registration failed for RVUAFVF ME0\n");
2930                 goto fail;
2931         }
2932         rvu->irq_allocated[offset] = true;
2933
2934         offset = pf_vec_start + RVU_PF_INT_VEC_VFME1;
2935         sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF ME1");
2936         ret = request_irq(pci_irq_vector(rvu->pdev, offset),
2937                           rvu_me_vf_intr_handler, 0,
2938                           &rvu->irq_name[offset * NAME_SIZE], rvu);
2939         if (ret) {
2940                 dev_err(rvu->dev,
2941                         "RVUAF: IRQ registration failed for RVUAFVF ME1\n");
2942                 goto fail;
2943         }
2944         rvu->irq_allocated[offset] = true;
2945
2946         ret = rvu_cpt_register_interrupts(rvu);
2947         if (ret)
2948                 goto fail;
2949
2950         return 0;
2951
2952 fail:
2953         rvu_unregister_interrupts(rvu);
2954         return ret;
2955 }
2956
2957 static void rvu_flr_wq_destroy(struct rvu *rvu)
2958 {
2959         if (rvu->flr_wq) {
2960                 destroy_workqueue(rvu->flr_wq);
2961                 rvu->flr_wq = NULL;
2962         }
2963 }
2964
2965 static int rvu_flr_init(struct rvu *rvu)
2966 {
2967         int dev, num_devs;
2968         u64 cfg;
2969         int pf;
2970
2971         /* Enable FLR for all PFs*/
2972         for (pf = 0; pf < rvu->hw->total_pfs; pf++) {
2973                 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf));
2974                 rvu_write64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf),
2975                             cfg | BIT_ULL(22));
2976         }
2977
2978         rvu->flr_wq = alloc_workqueue("rvu_afpf_flr",
2979                                       WQ_UNBOUND | WQ_HIGHPRI | WQ_MEM_RECLAIM,
2980                                        1);
2981         if (!rvu->flr_wq)
2982                 return -ENOMEM;
2983
2984         num_devs = rvu->hw->total_pfs + pci_sriov_get_totalvfs(rvu->pdev);
2985         rvu->flr_wrk = devm_kcalloc(rvu->dev, num_devs,
2986                                     sizeof(struct rvu_work), GFP_KERNEL);
2987         if (!rvu->flr_wrk) {
2988                 destroy_workqueue(rvu->flr_wq);
2989                 return -ENOMEM;
2990         }
2991
2992         for (dev = 0; dev < num_devs; dev++) {
2993                 rvu->flr_wrk[dev].rvu = rvu;
2994                 INIT_WORK(&rvu->flr_wrk[dev].work, rvu_flr_handler);
2995         }
2996
2997         mutex_init(&rvu->flr_lock);
2998
2999         return 0;
3000 }
3001
3002 static void rvu_disable_afvf_intr(struct rvu *rvu)
3003 {
3004         int vfs = rvu->vfs;
3005
3006         rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(0), INTR_MASK(vfs));
3007         rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(0), INTR_MASK(vfs));
3008         rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1CX(0), INTR_MASK(vfs));
3009         if (vfs <= 64)
3010                 return;
3011
3012         rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(1),
3013                       INTR_MASK(vfs - 64));
3014         rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(1), INTR_MASK(vfs - 64));
3015         rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1CX(1), INTR_MASK(vfs - 64));
3016 }
3017
3018 static void rvu_enable_afvf_intr(struct rvu *rvu)
3019 {
3020         int vfs = rvu->vfs;
3021
3022         /* Clear any pending interrupts and enable AF VF interrupts for
3023          * the first 64 VFs.
3024          */
3025         /* Mbox */
3026         rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(0), INTR_MASK(vfs));
3027         rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(0), INTR_MASK(vfs));
3028
3029         /* FLR */
3030         rvupf_write64(rvu, RVU_PF_VFFLR_INTX(0), INTR_MASK(vfs));
3031         rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(0), INTR_MASK(vfs));
3032         rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1SX(0), INTR_MASK(vfs));
3033
3034         /* Same for remaining VFs, if any. */
3035         if (vfs <= 64)
3036                 return;
3037
3038         rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(1), INTR_MASK(vfs - 64));
3039         rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(1),
3040                       INTR_MASK(vfs - 64));
3041
3042         rvupf_write64(rvu, RVU_PF_VFFLR_INTX(1), INTR_MASK(vfs - 64));
3043         rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(1), INTR_MASK(vfs - 64));
3044         rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1SX(1), INTR_MASK(vfs - 64));
3045 }
3046
3047 int rvu_get_num_lbk_chans(void)
3048 {
3049         struct pci_dev *pdev;
3050         void __iomem *base;
3051         int ret = -EIO;
3052
3053         pdev = pci_get_device(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_LBK,
3054                               NULL);
3055         if (!pdev)
3056                 goto err;
3057
3058         base = pci_ioremap_bar(pdev, 0);
3059         if (!base)
3060                 goto err_put;
3061
3062         /* Read number of available LBK channels from LBK(0)_CONST register. */
3063         ret = (readq(base + 0x10) >> 32) & 0xffff;
3064         iounmap(base);
3065 err_put:
3066         pci_dev_put(pdev);
3067 err:
3068         return ret;
3069 }
3070
3071 static int rvu_enable_sriov(struct rvu *rvu)
3072 {
3073         struct pci_dev *pdev = rvu->pdev;
3074         int err, chans, vfs;
3075
3076         if (!rvu_afvf_msix_vectors_num_ok(rvu)) {
3077                 dev_warn(&pdev->dev,
3078                          "Skipping SRIOV enablement since not enough IRQs are available\n");
3079                 return 0;
3080         }
3081
3082         chans = rvu_get_num_lbk_chans();
3083         if (chans < 0)
3084                 return chans;
3085
3086         vfs = pci_sriov_get_totalvfs(pdev);
3087
3088         /* Limit VFs in case we have more VFs than LBK channels available. */
3089         if (vfs > chans)
3090                 vfs = chans;
3091
3092         if (!vfs)
3093                 return 0;
3094
3095         /* LBK channel number 63 is used for switching packets between
3096          * CGX mapped VFs. Hence limit LBK pairs till 62 only.
3097          */
3098         if (vfs > 62)
3099                 vfs = 62;
3100
3101         /* Save VFs number for reference in VF interrupts handlers.
3102          * Since interrupts might start arriving during SRIOV enablement
3103          * ordinary API cannot be used to get number of enabled VFs.
3104          */
3105         rvu->vfs = vfs;
3106
3107         err = rvu_mbox_init(rvu, &rvu->afvf_wq_info, TYPE_AFVF, vfs,
3108                             rvu_afvf_mbox_handler, rvu_afvf_mbox_up_handler);
3109         if (err)
3110                 return err;
3111
3112         rvu_enable_afvf_intr(rvu);
3113         /* Make sure IRQs are enabled before SRIOV. */
3114         mb();
3115
3116         err = pci_enable_sriov(pdev, vfs);
3117         if (err) {
3118                 rvu_disable_afvf_intr(rvu);
3119                 rvu_mbox_destroy(&rvu->afvf_wq_info);
3120                 return err;
3121         }
3122
3123         return 0;
3124 }
3125
3126 static void rvu_disable_sriov(struct rvu *rvu)
3127 {
3128         rvu_disable_afvf_intr(rvu);
3129         rvu_mbox_destroy(&rvu->afvf_wq_info);
3130         pci_disable_sriov(rvu->pdev);
3131 }
3132
3133 static void rvu_update_module_params(struct rvu *rvu)
3134 {
3135         const char *default_pfl_name = "default";
3136
3137         strscpy(rvu->mkex_pfl_name,
3138                 mkex_profile ? mkex_profile : default_pfl_name, MKEX_NAME_LEN);
3139         strscpy(rvu->kpu_pfl_name,
3140                 kpu_profile ? kpu_profile : default_pfl_name, KPU_NAME_LEN);
3141 }
3142
3143 static int rvu_probe(struct pci_dev *pdev, const struct pci_device_id *id)
3144 {
3145         struct device *dev = &pdev->dev;
3146         struct rvu *rvu;
3147         int    err;
3148
3149         rvu = devm_kzalloc(dev, sizeof(*rvu), GFP_KERNEL);
3150         if (!rvu)
3151                 return -ENOMEM;
3152
3153         rvu->hw = devm_kzalloc(dev, sizeof(struct rvu_hwinfo), GFP_KERNEL);
3154         if (!rvu->hw) {
3155                 devm_kfree(dev, rvu);
3156                 return -ENOMEM;
3157         }
3158
3159         pci_set_drvdata(pdev, rvu);
3160         rvu->pdev = pdev;
3161         rvu->dev = &pdev->dev;
3162
3163         err = pci_enable_device(pdev);
3164         if (err) {
3165                 dev_err(dev, "Failed to enable PCI device\n");
3166                 goto err_freemem;
3167         }
3168
3169         err = pci_request_regions(pdev, DRV_NAME);
3170         if (err) {
3171                 dev_err(dev, "PCI request regions failed 0x%x\n", err);
3172                 goto err_disable_device;
3173         }
3174
3175         err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48));
3176         if (err) {
3177                 dev_err(dev, "DMA mask config failed, abort\n");
3178                 goto err_release_regions;
3179         }
3180
3181         pci_set_master(pdev);
3182
3183         rvu->ptp = ptp_get();
3184         if (IS_ERR(rvu->ptp)) {
3185                 err = PTR_ERR(rvu->ptp);
3186                 if (err == -EPROBE_DEFER)
3187                         goto err_release_regions;
3188                 rvu->ptp = NULL;
3189         }
3190
3191         /* Map Admin function CSRs */
3192         rvu->afreg_base = pcim_iomap(pdev, PCI_AF_REG_BAR_NUM, 0);
3193         rvu->pfreg_base = pcim_iomap(pdev, PCI_PF_REG_BAR_NUM, 0);
3194         if (!rvu->afreg_base || !rvu->pfreg_base) {
3195                 dev_err(dev, "Unable to map admin function CSRs, aborting\n");
3196                 err = -ENOMEM;
3197                 goto err_put_ptp;
3198         }
3199
3200         /* Store module params in rvu structure */
3201         rvu_update_module_params(rvu);
3202
3203         /* Check which blocks the HW supports */
3204         rvu_check_block_implemented(rvu);
3205
3206         rvu_reset_all_blocks(rvu);
3207
3208         rvu_setup_hw_capabilities(rvu);
3209
3210         err = rvu_setup_hw_resources(rvu);
3211         if (err)
3212                 goto err_put_ptp;
3213
3214         /* Init mailbox btw AF and PFs */
3215         err = rvu_mbox_init(rvu, &rvu->afpf_wq_info, TYPE_AFPF,
3216                             rvu->hw->total_pfs, rvu_afpf_mbox_handler,
3217                             rvu_afpf_mbox_up_handler);
3218         if (err) {
3219                 dev_err(dev, "%s: Failed to initialize mbox\n", __func__);
3220                 goto err_hwsetup;
3221         }
3222
3223         err = rvu_flr_init(rvu);
3224         if (err) {
3225                 dev_err(dev, "%s: Failed to initialize flr\n", __func__);
3226                 goto err_mbox;
3227         }
3228
3229         err = rvu_register_interrupts(rvu);
3230         if (err) {
3231                 dev_err(dev, "%s: Failed to register interrupts\n", __func__);
3232                 goto err_flr;
3233         }
3234
3235         err = rvu_register_dl(rvu);
3236         if (err) {
3237                 dev_err(dev, "%s: Failed to register devlink\n", __func__);
3238                 goto err_irq;
3239         }
3240
3241         rvu_setup_rvum_blk_revid(rvu);
3242
3243         /* Enable AF's VFs (if any) */
3244         err = rvu_enable_sriov(rvu);
3245         if (err) {
3246                 dev_err(dev, "%s: Failed to enable sriov\n", __func__);
3247                 goto err_dl;
3248         }
3249
3250         /* Initialize debugfs */
3251         rvu_dbg_init(rvu);
3252
3253         mutex_init(&rvu->rswitch.switch_lock);
3254
3255         if (rvu->fwdata)
3256                 ptp_start(rvu->ptp, rvu->fwdata->sclk, rvu->fwdata->ptp_ext_clk_rate,
3257                           rvu->fwdata->ptp_ext_tstamp);
3258
3259         return 0;
3260 err_dl:
3261         rvu_unregister_dl(rvu);
3262 err_irq:
3263         rvu_unregister_interrupts(rvu);
3264 err_flr:
3265         rvu_flr_wq_destroy(rvu);
3266 err_mbox:
3267         rvu_mbox_destroy(&rvu->afpf_wq_info);
3268 err_hwsetup:
3269         rvu_cgx_exit(rvu);
3270         rvu_fwdata_exit(rvu);
3271         rvu_reset_all_blocks(rvu);
3272         rvu_free_hw_resources(rvu);
3273         rvu_clear_rvum_blk_revid(rvu);
3274 err_put_ptp:
3275         ptp_put(rvu->ptp);
3276 err_release_regions:
3277         pci_release_regions(pdev);
3278 err_disable_device:
3279         pci_disable_device(pdev);
3280 err_freemem:
3281         pci_set_drvdata(pdev, NULL);
3282         devm_kfree(&pdev->dev, rvu->hw);
3283         devm_kfree(dev, rvu);
3284         return err;
3285 }
3286
3287 static void rvu_remove(struct pci_dev *pdev)
3288 {
3289         struct rvu *rvu = pci_get_drvdata(pdev);
3290
3291         rvu_dbg_exit(rvu);
3292         rvu_unregister_dl(rvu);
3293         rvu_unregister_interrupts(rvu);
3294         rvu_flr_wq_destroy(rvu);
3295         rvu_cgx_exit(rvu);
3296         rvu_fwdata_exit(rvu);
3297         rvu_mbox_destroy(&rvu->afpf_wq_info);
3298         rvu_disable_sriov(rvu);
3299         rvu_reset_all_blocks(rvu);
3300         rvu_free_hw_resources(rvu);
3301         rvu_clear_rvum_blk_revid(rvu);
3302         ptp_put(rvu->ptp);
3303         pci_release_regions(pdev);
3304         pci_disable_device(pdev);
3305         pci_set_drvdata(pdev, NULL);
3306
3307         devm_kfree(&pdev->dev, rvu->hw);
3308         devm_kfree(&pdev->dev, rvu);
3309 }
3310
3311 static struct pci_driver rvu_driver = {
3312         .name = DRV_NAME,
3313         .id_table = rvu_id_table,
3314         .probe = rvu_probe,
3315         .remove = rvu_remove,
3316 };
3317
3318 static int __init rvu_init_module(void)
3319 {
3320         int err;
3321
3322         pr_info("%s: %s\n", DRV_NAME, DRV_STRING);
3323
3324         err = pci_register_driver(&cgx_driver);
3325         if (err < 0)
3326                 return err;
3327
3328         err = pci_register_driver(&ptp_driver);
3329         if (err < 0)
3330                 goto ptp_err;
3331
3332         err =  pci_register_driver(&rvu_driver);
3333         if (err < 0)
3334                 goto rvu_err;
3335
3336         return 0;
3337 rvu_err:
3338         pci_unregister_driver(&ptp_driver);
3339 ptp_err:
3340         pci_unregister_driver(&cgx_driver);
3341
3342         return err;
3343 }
3344
3345 static void __exit rvu_cleanup_module(void)
3346 {
3347         pci_unregister_driver(&rvu_driver);
3348         pci_unregister_driver(&ptp_driver);
3349         pci_unregister_driver(&cgx_driver);
3350 }
3351
3352 module_init(rvu_init_module);
3353 module_exit(rvu_cleanup_module);