drivers/net/ethernet/marvell/octeontx2/af/rvu.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Marvell OcteonTx2 RVU Admin Function driver
   3  *
   4  * Copyright (C) 2018 Marvell International Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/delay.h>
  14 #include <linux/irq.h>
  15 #include <linux/pci.h>
  16 #include <linux/sysfs.h>
  17
  18 #include "cgx.h"
  19 #include "rvu.h"
  20 #include "rvu_reg.h"
  21 #include "ptp.h"
  22
  23 #include "rvu_trace.h"
  24
  25 #define DRV_NAME        "rvu_af"
  26 #define DRV_STRING      "Marvell OcteonTX2 RVU Admin Function Driver"
  27
  28 static int rvu_get_hwvf(struct rvu *rvu, int pcifunc);
  29
  30 static void rvu_set_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf,
  31                                 struct rvu_block *block, int lf);
  32 static void rvu_clear_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf,
  33                                   struct rvu_block *block, int lf);
  34 static void __rvu_flr_handler(struct rvu *rvu, u16 pcifunc);
  35
  36 static int rvu_mbox_init(struct rvu *rvu, struct mbox_wq_info *mw,
  37                          int type, int num,
  38                          void (mbox_handler)(struct work_struct *),
  39                          void (mbox_up_handler)(struct work_struct *));
  40 enum {
  41         TYPE_AFVF,
  42         TYPE_AFPF,
  43 };
  44
  45 /* Supported devices */
  46 static const struct pci_device_id rvu_id_table[] = {
  47         { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_AF) },
  48         { 0, }  /* end of table */
  49 };
  50
  51 MODULE_AUTHOR("Sunil Goutham <sgoutham@marvell.com>");
  52 MODULE_DESCRIPTION(DRV_STRING);
  53 MODULE_LICENSE("GPL v2");
  54 MODULE_DEVICE_TABLE(pci, rvu_id_table);
  55
  56 static char *mkex_profile; /* MKEX profile name */
  57 module_param(mkex_profile, charp, 0000);
  58 MODULE_PARM_DESC(mkex_profile, "MKEX profile name string");
  59
  60 static char *kpu_profile; /* KPU profile name */
  61 module_param(kpu_profile, charp, 0000);
  62 MODULE_PARM_DESC(kpu_profile, "KPU profile name string");
  63
  64 static void rvu_setup_hw_capabilities(struct rvu *rvu)
  65 {
  66         struct rvu_hwinfo *hw = rvu->hw;
  67
  68         hw->cap.nix_tx_aggr_lvl = NIX_TXSCH_LVL_TL1;
  69         hw->cap.nix_fixed_txschq_mapping = false;
  70         hw->cap.nix_shaping = true;
  71         hw->cap.nix_tx_link_bp = true;
  72         hw->cap.nix_rx_multicast = true;
  73         hw->rvu = rvu;
  74
  75         if (is_rvu_96xx_B0(rvu)) {
  76                 hw->cap.nix_fixed_txschq_mapping = true;
  77                 hw->cap.nix_txsch_per_cgx_lmac = 4;
  78                 hw->cap.nix_txsch_per_lbk_lmac = 132;
  79                 hw->cap.nix_txsch_per_sdp_lmac = 76;
  80                 hw->cap.nix_shaping = false;
  81                 hw->cap.nix_tx_link_bp = false;
  82                 if (is_rvu_96xx_A0(rvu))
  83                         hw->cap.nix_rx_multicast = false;
  84         }
  85
  86         if (!is_rvu_otx2(rvu))
  87                 hw->cap.per_pf_mbox_regs = true;
  88 }
  89
  90 /* Poll a RVU block's register 'offset', for a 'zero'
  91  * or 'nonzero' at bits specified by 'mask'
  92  */
  93 int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero)
  94 {
  95         unsigned long timeout = jiffies + usecs_to_jiffies(10000);
  96         void __iomem *reg;
  97         u64 reg_val;
  98
  99         reg = rvu->afreg_base + ((block << 28) | offset);
 100 again:
 101         reg_val = readq(reg);
 102         if (zero && !(reg_val & mask))
 103                 return 0;
 104         if (!zero && (reg_val & mask))
 105                 return 0;
 106         if (time_before(jiffies, timeout)) {
 107                 usleep_range(1, 5);
 108                 goto again;
 109         }
 110         return -EBUSY;
 111 }
 112
 113 int rvu_alloc_rsrc(struct rsrc_bmap *rsrc)
 114 {
 115         int id;
 116
 117         if (!rsrc->bmap)
 118                 return -EINVAL;
 119
 120         id = find_first_zero_bit(rsrc->bmap, rsrc->max);
 121         if (id >= rsrc->max)
 122                 return -ENOSPC;
 123
 124         __set_bit(id, rsrc->bmap);
 125
 126         return id;
 127 }
 128
 129 int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc)
 130 {
 131         int start;
 132
 133         if (!rsrc->bmap)
 134                 return -EINVAL;
 135
 136         start = bitmap_find_next_zero_area(rsrc->bmap, rsrc->max, 0, nrsrc, 0);
 137         if (start >= rsrc->max)
 138                 return -ENOSPC;
 139
 140         bitmap_set(rsrc->bmap, start, nrsrc);
 141         return start;
 142 }
 143
 144 static void rvu_free_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc, int start)
 145 {
 146         if (!rsrc->bmap)
 147                 return;
 148         if (start >= rsrc->max)
 149                 return;
 150
 151         bitmap_clear(rsrc->bmap, start, nrsrc);
 152 }
 153
 154 bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc)
 155 {
 156         int start;
 157
 158         if (!rsrc->bmap)
 159                 return false;
 160
 161         start = bitmap_find_next_zero_area(rsrc->bmap, rsrc->max, 0, nrsrc, 0);
 162         if (start >= rsrc->max)
 163                 return false;
 164
 165         return true;
 166 }
 167
 168 void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id)
 169 {
 170         if (!rsrc->bmap)
 171                 return;
 172
 173         __clear_bit(id, rsrc->bmap);
 174 }
 175
 176 int rvu_rsrc_free_count(struct rsrc_bmap *rsrc)
 177 {
 178         int used;
 179
 180         if (!rsrc->bmap)
 181                 return 0;
 182
 183         used = bitmap_weight(rsrc->bmap, rsrc->max);
 184         return (rsrc->max - used);
 185 }
 186
 187 bool is_rsrc_free(struct rsrc_bmap *rsrc, int id)
 188 {
 189         if (!rsrc->bmap)
 190                 return false;
 191
 192         return !test_bit(id, rsrc->bmap);
 193 }
 194
 195 int rvu_alloc_bitmap(struct rsrc_bmap *rsrc)
 196 {
 197         rsrc->bmap = kcalloc(BITS_TO_LONGS(rsrc->max),
 198                              sizeof(long), GFP_KERNEL);
 199         if (!rsrc->bmap)
 200                 return -ENOMEM;
 201         return 0;
 202 }
 203
 204 /* Get block LF's HW index from a PF_FUNC's block slot number */
 205 int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot)
 206 {
 207         u16 match = 0;
 208         int lf;
 209
 210         mutex_lock(&rvu->rsrc_lock);
 211         for (lf = 0; lf < block->lf.max; lf++) {
 212                 if (block->fn_map[lf] == pcifunc) {
 213                         if (slot == match) {
 214                                 mutex_unlock(&rvu->rsrc_lock);
 215                                 return lf;
 216                         }
 217                         match++;
 218                 }
 219         }
 220         mutex_unlock(&rvu->rsrc_lock);
 221         return -ENODEV;
 222 }
 223
 224 /* Convert BLOCK_TYPE_E to a BLOCK_ADDR_E.
 225  * Some silicon variants of OcteonTX2 supports
 226  * multiple blocks of same type.
 227  *
 228  * @pcifunc has to be zero when no LF is yet attached.
 229  *
 230  * For a pcifunc if LFs are attached from multiple blocks of same type, then
 231  * return blkaddr of first encountered block.
 232  */
 233 int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc)
 234 {
 235         int devnum, blkaddr = -ENODEV;
 236         u64 cfg, reg;
 237         bool is_pf;
 238
 239         switch (blktype) {
 240         case BLKTYPE_NPC:
 241                 blkaddr = BLKADDR_NPC;
 242                 goto exit;
 243         case BLKTYPE_NPA:
 244                 blkaddr = BLKADDR_NPA;
 245                 goto exit;
 246         case BLKTYPE_NIX:
 247                 /* For now assume NIX0 */
 248                 if (!pcifunc) {
 249                         blkaddr = BLKADDR_NIX0;
 250                         goto exit;
 251                 }
 252                 break;
 253         case BLKTYPE_SSO:
 254                 blkaddr = BLKADDR_SSO;
 255                 goto exit;
 256         case BLKTYPE_SSOW:
 257                 blkaddr = BLKADDR_SSOW;
 258                 goto exit;
 259         case BLKTYPE_TIM:
 260                 blkaddr = BLKADDR_TIM;
 261                 goto exit;
 262         case BLKTYPE_CPT:
 263                 /* For now assume CPT0 */
 264                 if (!pcifunc) {
 265                         blkaddr = BLKADDR_CPT0;
 266                         goto exit;
 267                 }
 268                 break;
 269         }
 270
 271         /* Check if this is a RVU PF or VF */
 272         if (pcifunc & RVU_PFVF_FUNC_MASK) {
 273                 is_pf = false;
 274                 devnum = rvu_get_hwvf(rvu, pcifunc);
 275         } else {
 276                 is_pf = true;
 277                 devnum = rvu_get_pf(pcifunc);
 278         }
 279
 280         /* Check if the 'pcifunc' has a NIX LF from 'BLKADDR_NIX0' or
 281          * 'BLKADDR_NIX1'.
 282          */
 283         if (blktype == BLKTYPE_NIX) {
 284                 reg = is_pf ? RVU_PRIV_PFX_NIXX_CFG(0) :
 285                         RVU_PRIV_HWVFX_NIXX_CFG(0);
 286                 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16));
 287                 if (cfg) {
 288                         blkaddr = BLKADDR_NIX0;
 289                         goto exit;
 290                 }
 291
 292                 reg = is_pf ? RVU_PRIV_PFX_NIXX_CFG(1) :
 293                         RVU_PRIV_HWVFX_NIXX_CFG(1);
 294                 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16));
 295                 if (cfg)
 296                         blkaddr = BLKADDR_NIX1;
 297         }
 298
 299         if (blktype == BLKTYPE_CPT) {
 300                 reg = is_pf ? RVU_PRIV_PFX_CPTX_CFG(0) :
 301                         RVU_PRIV_HWVFX_CPTX_CFG(0);
 302                 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16));
 303                 if (cfg) {
 304                         blkaddr = BLKADDR_CPT0;
 305                         goto exit;
 306                 }
 307
 308                 reg = is_pf ? RVU_PRIV_PFX_CPTX_CFG(1) :
 309                         RVU_PRIV_HWVFX_CPTX_CFG(1);
 310                 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16));
 311                 if (cfg)
 312                         blkaddr = BLKADDR_CPT1;
 313         }
 314
 315 exit:
 316         if (is_block_implemented(rvu->hw, blkaddr))
 317                 return blkaddr;
 318         return -ENODEV;
 319 }
 320
 321 static void rvu_update_rsrc_map(struct rvu *rvu, struct rvu_pfvf *pfvf,
 322                                 struct rvu_block *block, u16 pcifunc,
 323                                 u16 lf, bool attach)
 324 {
 325         int devnum, num_lfs = 0;
 326         bool is_pf;
 327         u64 reg;
 328
 329         if (lf >= block->lf.max) {
 330                 dev_err(&rvu->pdev->dev,
 331                         "%s: FATAL: LF %d is >= %s's max lfs i.e %d\n",
 332                         __func__, lf, block->name, block->lf.max);
 333                 return;
 334         }
 335
 336         /* Check if this is for a RVU PF or VF */
 337         if (pcifunc & RVU_PFVF_FUNC_MASK) {
 338                 is_pf = false;
 339                 devnum = rvu_get_hwvf(rvu, pcifunc);
 340         } else {
 341                 is_pf = true;
 342                 devnum = rvu_get_pf(pcifunc);
 343         }
 344
 345         block->fn_map[lf] = attach ? pcifunc : 0;
 346
 347         switch (block->addr) {
 348         case BLKADDR_NPA:
 349                 pfvf->npalf = attach ? true : false;
 350                 num_lfs = pfvf->npalf;
 351                 break;
 352         case BLKADDR_NIX0:
 353         case BLKADDR_NIX1:
 354                 pfvf->nixlf = attach ? true : false;
 355                 num_lfs = pfvf->nixlf;
 356                 break;
 357         case BLKADDR_SSO:
 358                 attach ? pfvf->sso++ : pfvf->sso--;
 359                 num_lfs = pfvf->sso;
 360                 break;
 361         case BLKADDR_SSOW:
 362                 attach ? pfvf->ssow++ : pfvf->ssow--;
 363                 num_lfs = pfvf->ssow;
 364                 break;
 365         case BLKADDR_TIM:
 366                 attach ? pfvf->timlfs++ : pfvf->timlfs--;
 367                 num_lfs = pfvf->timlfs;
 368                 break;
 369         case BLKADDR_CPT0:
 370                 attach ? pfvf->cptlfs++ : pfvf->cptlfs--;
 371                 num_lfs = pfvf->cptlfs;
 372                 break;
 373         case BLKADDR_CPT1:
 374                 attach ? pfvf->cpt1_lfs++ : pfvf->cpt1_lfs--;
 375                 num_lfs = pfvf->cpt1_lfs;
 376                 break;
 377         }
 378
 379         reg = is_pf ? block->pf_lfcnt_reg : block->vf_lfcnt_reg;
 380         rvu_write64(rvu, BLKADDR_RVUM, reg | (devnum << 16), num_lfs);
 381 }
 382
 383 inline int rvu_get_pf(u16 pcifunc)
 384 {
 385         return (pcifunc >> RVU_PFVF_PF_SHIFT) & RVU_PFVF_PF_MASK;
 386 }
 387
 388 void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf)
 389 {
 390         u64 cfg;
 391
 392         /* Get numVFs attached to this PF and first HWVF */
 393         cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf));
 394         if (numvfs)
 395                 *numvfs = (cfg >> 12) & 0xFF;
 396         if (hwvf)
 397                 *hwvf = cfg & 0xFFF;
 398 }
 399
 400 static int rvu_get_hwvf(struct rvu *rvu, int pcifunc)
 401 {
 402         int pf, func;
 403         u64 cfg;
 404
 405         pf = rvu_get_pf(pcifunc);
 406         func = pcifunc & RVU_PFVF_FUNC_MASK;
 407
 408         /* Get first HWVF attached to this PF */
 409         cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf));
 410
 411         return ((cfg & 0xFFF) + func - 1);
 412 }
 413
 414 struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc)
 415 {
 416         /* Check if it is a PF or VF */
 417         if (pcifunc & RVU_PFVF_FUNC_MASK)
 418                 return &rvu->hwvf[rvu_get_hwvf(rvu, pcifunc)];
 419         else
 420                 return &rvu->pf[rvu_get_pf(pcifunc)];
 421 }
 422
 423 static bool is_pf_func_valid(struct rvu *rvu, u16 pcifunc)
 424 {
 425         int pf, vf, nvfs;
 426         u64 cfg;
 427
 428         pf = rvu_get_pf(pcifunc);
 429         if (pf >= rvu->hw->total_pfs)
 430                 return false;
 431
 432         if (!(pcifunc & RVU_PFVF_FUNC_MASK))
 433                 return true;
 434
 435         /* Check if VF is within number of VFs attached to this PF */
 436         vf = (pcifunc & RVU_PFVF_FUNC_MASK) - 1;
 437         cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf));
 438         nvfs = (cfg >> 12) & 0xFF;
 439         if (vf >= nvfs)
 440                 return false;
 441
 442         return true;
 443 }
 444
 445 bool is_block_implemented(struct rvu_hwinfo *hw, int blkaddr)
 446 {
 447         struct rvu_block *block;
 448
 449         if (blkaddr < BLKADDR_RVUM || blkaddr >= BLK_COUNT)
 450                 return false;
 451
 452         block = &hw->block[blkaddr];
 453         return block->implemented;
 454 }
 455
 456 static void rvu_check_block_implemented(struct rvu *rvu)
 457 {
 458         struct rvu_hwinfo *hw = rvu->hw;
 459         struct rvu_block *block;
 460         int blkid;
 461         u64 cfg;
 462
 463         /* For each block check if 'implemented' bit is set */
 464         for (blkid = 0; blkid < BLK_COUNT; blkid++) {
 465                 block = &hw->block[blkid];
 466                 cfg = rvupf_read64(rvu, RVU_PF_BLOCK_ADDRX_DISC(blkid));
 467                 if (cfg & BIT_ULL(11))
 468                         block->implemented = true;
 469         }
 470 }
 471
 472 static void rvu_setup_rvum_blk_revid(struct rvu *rvu)
 473 {
 474         rvu_write64(rvu, BLKADDR_RVUM,
 475                     RVU_PRIV_BLOCK_TYPEX_REV(BLKTYPE_RVUM),
 476                     RVU_BLK_RVUM_REVID);
 477 }
 478
 479 static void rvu_clear_rvum_blk_revid(struct rvu *rvu)
 480 {
 481         rvu_write64(rvu, BLKADDR_RVUM,
 482                     RVU_PRIV_BLOCK_TYPEX_REV(BLKTYPE_RVUM), 0x00);
 483 }
 484
 485 int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block, int lf)
 486 {
 487         int err;
 488
 489         if (!block->implemented)
 490                 return 0;
 491
 492         rvu_write64(rvu, block->addr, block->lfreset_reg, lf | BIT_ULL(12));
 493         err = rvu_poll_reg(rvu, block->addr, block->lfreset_reg, BIT_ULL(12),
 494                            true);
 495         return err;
 496 }
 497
 498 static void rvu_block_reset(struct rvu *rvu, int blkaddr, u64 rst_reg)
 499 {
 500         struct rvu_block *block = &rvu->hw->block[blkaddr];
 501         int err;
 502
 503         if (!block->implemented)
 504                 return;
 505
 506         rvu_write64(rvu, blkaddr, rst_reg, BIT_ULL(0));
 507         err = rvu_poll_reg(rvu, blkaddr, rst_reg, BIT_ULL(63), true);
 508         if (err)
 509                 dev_err(rvu->dev, "HW block:%d reset failed\n", blkaddr);
 510 }
 511
 512 static void rvu_reset_all_blocks(struct rvu *rvu)
 513 {
 514         /* Do a HW reset of all RVU blocks */
 515         rvu_block_reset(rvu, BLKADDR_NPA, NPA_AF_BLK_RST);
 516         rvu_block_reset(rvu, BLKADDR_NIX0, NIX_AF_BLK_RST);
 517         rvu_block_reset(rvu, BLKADDR_NIX1, NIX_AF_BLK_RST);
 518         rvu_block_reset(rvu, BLKADDR_NPC, NPC_AF_BLK_RST);
 519         rvu_block_reset(rvu, BLKADDR_SSO, SSO_AF_BLK_RST);
 520         rvu_block_reset(rvu, BLKADDR_TIM, TIM_AF_BLK_RST);
 521         rvu_block_reset(rvu, BLKADDR_CPT0, CPT_AF_BLK_RST);
 522         rvu_block_reset(rvu, BLKADDR_CPT1, CPT_AF_BLK_RST);
 523         rvu_block_reset(rvu, BLKADDR_NDC_NIX0_RX, NDC_AF_BLK_RST);
 524         rvu_block_reset(rvu, BLKADDR_NDC_NIX0_TX, NDC_AF_BLK_RST);
 525         rvu_block_reset(rvu, BLKADDR_NDC_NIX1_RX, NDC_AF_BLK_RST);
 526         rvu_block_reset(rvu, BLKADDR_NDC_NIX1_TX, NDC_AF_BLK_RST);
 527         rvu_block_reset(rvu, BLKADDR_NDC_NPA0, NDC_AF_BLK_RST);
 528 }
 529
 530 static void rvu_scan_block(struct rvu *rvu, struct rvu_block *block)
 531 {
 532         struct rvu_pfvf *pfvf;
 533         u64 cfg;
 534         int lf;
 535
 536         for (lf = 0; lf < block->lf.max; lf++) {
 537                 cfg = rvu_read64(rvu, block->addr,
 538                                  block->lfcfg_reg | (lf << block->lfshift));
 539                 if (!(cfg & BIT_ULL(63)))
 540                         continue;
 541
 542                 /* Set this resource as being used */
 543                 __set_bit(lf, block->lf.bmap);
 544
 545                 /* Get, to whom this LF is attached */
 546                 pfvf = rvu_get_pfvf(rvu, (cfg >> 8) & 0xFFFF);
 547                 rvu_update_rsrc_map(rvu, pfvf, block,
 548                                     (cfg >> 8) & 0xFFFF, lf, true);
 549
 550                 /* Set start MSIX vector for this LF within this PF/VF */
 551                 rvu_set_msix_offset(rvu, pfvf, block, lf);
 552         }
 553 }
 554
 555 static void rvu_check_min_msix_vec(struct rvu *rvu, int nvecs, int pf, int vf)
 556 {
 557         int min_vecs;
 558
 559         if (!vf)
 560                 goto check_pf;
 561
 562         if (!nvecs) {
 563                 dev_warn(rvu->dev,
 564                          "PF%d:VF%d is configured with zero msix vectors, %d\n",
 565                          pf, vf - 1, nvecs);
 566         }
 567         return;
 568
 569 check_pf:
 570         if (pf == 0)
 571                 min_vecs = RVU_AF_INT_VEC_CNT + RVU_PF_INT_VEC_CNT;
 572         else
 573                 min_vecs = RVU_PF_INT_VEC_CNT;
 574
 575         if (!(nvecs < min_vecs))
 576                 return;
 577         dev_warn(rvu->dev,
 578                  "PF%d is configured with too few vectors, %d, min is %d\n",
 579                  pf, nvecs, min_vecs);
 580 }
 581
 582 static int rvu_setup_msix_resources(struct rvu *rvu)
 583 {
 584         struct rvu_hwinfo *hw = rvu->hw;
 585         int pf, vf, numvfs, hwvf, err;
 586         int nvecs, offset, max_msix;
 587         struct rvu_pfvf *pfvf;
 588         u64 cfg, phy_addr;
 589         dma_addr_t iova;
 590
 591         for (pf = 0; pf < hw->total_pfs; pf++) {
 592                 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf));
 593                 /* If PF is not enabled, nothing to do */
 594                 if (!((cfg >> 20) & 0x01))
 595                         continue;
 596
 597                 rvu_get_pf_numvfs(rvu, pf, &numvfs, &hwvf);
 598
 599                 pfvf = &rvu->pf[pf];
 600                 /* Get num of MSIX vectors attached to this PF */
 601                 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_MSIX_CFG(pf));
 602                 pfvf->msix.max = ((cfg >> 32) & 0xFFF) + 1;
 603                 rvu_check_min_msix_vec(rvu, pfvf->msix.max, pf, 0);
 604
 605                 /* Alloc msix bitmap for this PF */
 606                 err = rvu_alloc_bitmap(&pfvf->msix);
 607                 if (err)
 608                         return err;
 609
 610                 /* Allocate memory for MSIX vector to RVU block LF mapping */
 611                 pfvf->msix_lfmap = devm_kcalloc(rvu->dev, pfvf->msix.max,
 612                                                 sizeof(u16), GFP_KERNEL);
 613                 if (!pfvf->msix_lfmap)
 614                         return -ENOMEM;
 615
 616                 /* For PF0 (AF) firmware will set msix vector offsets for
 617                  * AF, block AF and PF0_INT vectors, so jump to VFs.
 618                  */
 619                 if (!pf)
 620                         goto setup_vfmsix;
 621
 622                 /* Set MSIX offset for PF's 'RVU_PF_INT_VEC' vectors.
 623                  * These are allocated on driver init and never freed,
 624                  * so no need to set 'msix_lfmap' for these.
 625                  */
 626                 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_INT_CFG(pf));
 627                 nvecs = (cfg >> 12) & 0xFF;
 628                 cfg &= ~0x7FFULL;
 629                 offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs);
 630                 rvu_write64(rvu, BLKADDR_RVUM,
 631                             RVU_PRIV_PFX_INT_CFG(pf), cfg | offset);
 632 setup_vfmsix:
 633                 /* Alloc msix bitmap for VFs */
 634                 for (vf = 0; vf < numvfs; vf++) {
 635                         pfvf =  &rvu->hwvf[hwvf + vf];
 636                         /* Get num of MSIX vectors attached to this VF */
 637                         cfg = rvu_read64(rvu, BLKADDR_RVUM,
 638                                          RVU_PRIV_PFX_MSIX_CFG(pf));
 639                         pfvf->msix.max = (cfg & 0xFFF) + 1;
 640                         rvu_check_min_msix_vec(rvu, pfvf->msix.max, pf, vf + 1);
 641
 642                         /* Alloc msix bitmap for this VF */
 643                         err = rvu_alloc_bitmap(&pfvf->msix);
 644                         if (err)
 645                                 return err;
 646
 647                         pfvf->msix_lfmap =
 648                                 devm_kcalloc(rvu->dev, pfvf->msix.max,
 649                                              sizeof(u16), GFP_KERNEL);
 650                         if (!pfvf->msix_lfmap)
 651                                 return -ENOMEM;
 652
 653                         /* Set MSIX offset for HWVF's 'RVU_VF_INT_VEC' vectors.
 654                          * These are allocated on driver init and never freed,
 655                          * so no need to set 'msix_lfmap' for these.
 656                          */
 657                         cfg = rvu_read64(rvu, BLKADDR_RVUM,
 658                                          RVU_PRIV_HWVFX_INT_CFG(hwvf + vf));
 659                         nvecs = (cfg >> 12) & 0xFF;
 660                         cfg &= ~0x7FFULL;
 661                         offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs);
 662                         rvu_write64(rvu, BLKADDR_RVUM,
 663                                     RVU_PRIV_HWVFX_INT_CFG(hwvf + vf),
 664                                     cfg | offset);
 665                 }
 666         }
 667
 668         /* HW interprets RVU_AF_MSIXTR_BASE address as an IOVA, hence
 669          * create an IOMMU mapping for the physical address configured by
 670          * firmware and reconfig RVU_AF_MSIXTR_BASE with IOVA.
 671          */
 672         cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST);
 673         max_msix = cfg & 0xFFFFF;
 674         if (rvu->fwdata && rvu->fwdata->msixtr_base)
 675                 phy_addr = rvu->fwdata->msixtr_base;
 676         else
 677                 phy_addr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE);
 678
 679         iova = dma_map_resource(rvu->dev, phy_addr,
 680                                 max_msix * PCI_MSIX_ENTRY_SIZE,
 681                                 DMA_BIDIRECTIONAL, 0);
 682
 683         if (dma_mapping_error(rvu->dev, iova))
 684                 return -ENOMEM;
 685
 686         rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE, (u64)iova);
 687         rvu->msix_base_iova = iova;
 688         rvu->msixtr_base_phy = phy_addr;
 689
 690         return 0;
 691 }
 692
 693 static void rvu_reset_msix(struct rvu *rvu)
 694 {
 695         /* Restore msixtr base register */
 696         rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE,
 697                     rvu->msixtr_base_phy);
 698 }
 699
 700 static void rvu_free_hw_resources(struct rvu *rvu)
 701 {
 702         struct rvu_hwinfo *hw = rvu->hw;
 703         struct rvu_block *block;
 704         struct rvu_pfvf  *pfvf;
 705         int id, max_msix;
 706         u64 cfg;
 707
 708         rvu_npa_freemem(rvu);
 709         rvu_npc_freemem(rvu);
 710         rvu_nix_freemem(rvu);
 711
 712         /* Free block LF bitmaps */
 713         for (id = 0; id < BLK_COUNT; id++) {
 714                 block = &hw->block[id];
 715                 kfree(block->lf.bmap);
 716         }
 717
 718         /* Free MSIX bitmaps */
 719         for (id = 0; id < hw->total_pfs; id++) {
 720                 pfvf = &rvu->pf[id];
 721                 kfree(pfvf->msix.bmap);
 722         }
 723
 724         for (id = 0; id < hw->total_vfs; id++) {
 725                 pfvf = &rvu->hwvf[id];
 726                 kfree(pfvf->msix.bmap);
 727         }
 728
 729         /* Unmap MSIX vector base IOVA mapping */
 730         if (!rvu->msix_base_iova)
 731                 return;
 732         cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST);
 733         max_msix = cfg & 0xFFFFF;
 734         dma_unmap_resource(rvu->dev, rvu->msix_base_iova,
 735                            max_msix * PCI_MSIX_ENTRY_SIZE,
 736                            DMA_BIDIRECTIONAL, 0);
 737
 738         rvu_reset_msix(rvu);
 739         mutex_destroy(&rvu->rsrc_lock);
 740 }
 741
 742 static void rvu_setup_pfvf_macaddress(struct rvu *rvu)
 743 {
 744         struct rvu_hwinfo *hw = rvu->hw;
 745         int pf, vf, numvfs, hwvf;
 746         struct rvu_pfvf *pfvf;
 747         u64 *mac;
 748
 749         for (pf = 0; pf < hw->total_pfs; pf++) {
 750                 /* For PF0(AF), Assign MAC address to only VFs (LBKVFs) */
 751                 if (!pf)
 752                         goto lbkvf;
 753
 754                 if (!is_pf_cgxmapped(rvu, pf))
 755                         continue;
 756                 /* Assign MAC address to PF */
 757                 pfvf = &rvu->pf[pf];
 758                 if (rvu->fwdata && pf < PF_MACNUM_MAX) {
 759                         mac = &rvu->fwdata->pf_macs[pf];
 760                         if (*mac)
 761                                 u64_to_ether_addr(*mac, pfvf->mac_addr);
 762                         else
 763                                 eth_random_addr(pfvf->mac_addr);
 764                 } else {
 765                         eth_random_addr(pfvf->mac_addr);
 766                 }
 767                 ether_addr_copy(pfvf->default_mac, pfvf->mac_addr);
 768
 769 lbkvf:
 770                 /* Assign MAC address to VFs*/
 771                 rvu_get_pf_numvfs(rvu, pf, &numvfs, &hwvf);
 772                 for (vf = 0; vf < numvfs; vf++, hwvf++) {
 773                         pfvf = &rvu->hwvf[hwvf];
 774                         if (rvu->fwdata && hwvf < VF_MACNUM_MAX) {
 775                                 mac = &rvu->fwdata->vf_macs[hwvf];
 776                                 if (*mac)
 777                                         u64_to_ether_addr(*mac, pfvf->mac_addr);
 778                                 else
 779                                         eth_random_addr(pfvf->mac_addr);
 780                         } else {
 781                                 eth_random_addr(pfvf->mac_addr);
 782                         }
 783                         ether_addr_copy(pfvf->default_mac, pfvf->mac_addr);
 784                 }
 785         }
 786 }
 787
 788 static int rvu_fwdata_init(struct rvu *rvu)
 789 {
 790         u64 fwdbase;
 791         int err;
 792
 793         /* Get firmware data base address */
 794         err = cgx_get_fwdata_base(&fwdbase);
 795         if (err)
 796                 goto fail;
 797         rvu->fwdata = ioremap_wc(fwdbase, sizeof(struct rvu_fwdata));
 798         if (!rvu->fwdata)
 799                 goto fail;
 800         if (!is_rvu_fwdata_valid(rvu)) {
 801                 dev_err(rvu->dev,
 802                         "Mismatch in 'fwdata' struct btw kernel and firmware\n");
 803                 iounmap(rvu->fwdata);
 804                 rvu->fwdata = NULL;
 805                 return -EINVAL;
 806         }
 807         return 0;
 808 fail:
 809         dev_info(rvu->dev, "Unable to fetch 'fwdata' from firmware\n");
 810         return -EIO;
 811 }
 812
 813 static void rvu_fwdata_exit(struct rvu *rvu)
 814 {
 815         if (rvu->fwdata)
 816                 iounmap(rvu->fwdata);
 817 }
 818
 819 static int rvu_setup_nix_hw_resource(struct rvu *rvu, int blkaddr)
 820 {
 821         struct rvu_hwinfo *hw = rvu->hw;
 822         struct rvu_block *block;
 823         int blkid;
 824         u64 cfg;
 825
 826         /* Init NIX LF's bitmap */
 827         block = &hw->block[blkaddr];
 828         if (!block->implemented)
 829                 return 0;
 830         blkid = (blkaddr == BLKADDR_NIX0) ? 0 : 1;
 831         cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST2);
 832         block->lf.max = cfg & 0xFFF;
 833         block->addr = blkaddr;
 834         block->type = BLKTYPE_NIX;
 835         block->lfshift = 8;
 836         block->lookup_reg = NIX_AF_RVU_LF_CFG_DEBUG;
 837         block->pf_lfcnt_reg = RVU_PRIV_PFX_NIXX_CFG(blkid);
 838         block->vf_lfcnt_reg = RVU_PRIV_HWVFX_NIXX_CFG(blkid);
 839         block->lfcfg_reg = NIX_PRIV_LFX_CFG;
 840         block->msixcfg_reg = NIX_PRIV_LFX_INT_CFG;
 841         block->lfreset_reg = NIX_AF_LF_RST;
 842         sprintf(block->name, "NIX%d", blkid);
 843         rvu->nix_blkaddr[blkid] = blkaddr;
 844         return rvu_alloc_bitmap(&block->lf);
 845 }
 846
 847 static int rvu_setup_cpt_hw_resource(struct rvu *rvu, int blkaddr)
 848 {
 849         struct rvu_hwinfo *hw = rvu->hw;
 850         struct rvu_block *block;
 851         int blkid;
 852         u64 cfg;
 853
 854         /* Init CPT LF's bitmap */
 855         block = &hw->block[blkaddr];
 856         if (!block->implemented)
 857                 return 0;
 858         blkid = (blkaddr == BLKADDR_CPT0) ? 0 : 1;
 859         cfg = rvu_read64(rvu, blkaddr, CPT_AF_CONSTANTS0);
 860         block->lf.max = cfg & 0xFF;
 861         block->addr = blkaddr;
 862         block->type = BLKTYPE_CPT;
 863         block->multislot = true;
 864         block->lfshift = 3;
 865         block->lookup_reg = CPT_AF_RVU_LF_CFG_DEBUG;
 866         block->pf_lfcnt_reg = RVU_PRIV_PFX_CPTX_CFG(blkid);
 867         block->vf_lfcnt_reg = RVU_PRIV_HWVFX_CPTX_CFG(blkid);
 868         block->lfcfg_reg = CPT_PRIV_LFX_CFG;
 869         block->msixcfg_reg = CPT_PRIV_LFX_INT_CFG;
 870         block->lfreset_reg = CPT_AF_LF_RST;
 871         sprintf(block->name, "CPT%d", blkid);
 872         return rvu_alloc_bitmap(&block->lf);
 873 }
 874
 875 static void rvu_get_lbk_bufsize(struct rvu *rvu)
 876 {
 877         struct pci_dev *pdev = NULL;
 878         void __iomem *base;
 879         u64 lbk_const;
 880
 881         pdev = pci_get_device(PCI_VENDOR_ID_CAVIUM,
 882                               PCI_DEVID_OCTEONTX2_LBK, pdev);
 883         if (!pdev)
 884                 return;
 885
 886         base = pci_ioremap_bar(pdev, 0);
 887         if (!base)
 888                 goto err_put;
 889
 890         lbk_const = readq(base + LBK_CONST);
 891
 892         /* cache fifo size */
 893         rvu->hw->lbk_bufsize = FIELD_GET(LBK_CONST_BUF_SIZE, lbk_const);
 894
 895         iounmap(base);
 896 err_put:
 897         pci_dev_put(pdev);
 898 }
 899
 900 static int rvu_setup_hw_resources(struct rvu *rvu)
 901 {
 902         struct rvu_hwinfo *hw = rvu->hw;
 903         struct rvu_block *block;
 904         int blkid, err;
 905         u64 cfg;
 906
 907         /* Get HW supported max RVU PF & VF count */
 908         cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST);
 909         hw->total_pfs = (cfg >> 32) & 0xFF;
 910         hw->total_vfs = (cfg >> 20) & 0xFFF;
 911         hw->max_vfs_per_pf = (cfg >> 40) & 0xFF;
 912
 913         /* Init NPA LF's bitmap */
 914         block = &hw->block[BLKADDR_NPA];
 915         if (!block->implemented)
 916                 goto nix;
 917         cfg = rvu_read64(rvu, BLKADDR_NPA, NPA_AF_CONST);
 918         block->lf.max = (cfg >> 16) & 0xFFF;
 919         block->addr = BLKADDR_NPA;
 920         block->type = BLKTYPE_NPA;
 921         block->lfshift = 8;
 922         block->lookup_reg = NPA_AF_RVU_LF_CFG_DEBUG;
 923         block->pf_lfcnt_reg = RVU_PRIV_PFX_NPA_CFG;
 924         block->vf_lfcnt_reg = RVU_PRIV_HWVFX_NPA_CFG;
 925         block->lfcfg_reg = NPA_PRIV_LFX_CFG;
 926         block->msixcfg_reg = NPA_PRIV_LFX_INT_CFG;
 927         block->lfreset_reg = NPA_AF_LF_RST;
 928         sprintf(block->name, "NPA");
 929         err = rvu_alloc_bitmap(&block->lf);
 930         if (err) {
 931                 dev_err(rvu->dev,
 932                         "%s: Failed to allocate NPA LF bitmap\n", __func__);
 933                 return err;
 934         }
 935
 936 nix:
 937         err = rvu_setup_nix_hw_resource(rvu, BLKADDR_NIX0);
 938         if (err) {
 939                 dev_err(rvu->dev,
 940                         "%s: Failed to allocate NIX0 LFs bitmap\n", __func__);
 941                 return err;
 942         }
 943
 944         err = rvu_setup_nix_hw_resource(rvu, BLKADDR_NIX1);
 945         if (err) {
 946                 dev_err(rvu->dev,
 947                         "%s: Failed to allocate NIX1 LFs bitmap\n", __func__);
 948                 return err;
 949         }
 950
 951         /* Init SSO group's bitmap */
 952         block = &hw->block[BLKADDR_SSO];
 953         if (!block->implemented)
 954                 goto ssow;
 955         cfg = rvu_read64(rvu, BLKADDR_SSO, SSO_AF_CONST);
 956         block->lf.max = cfg & 0xFFFF;
 957         block->addr = BLKADDR_SSO;
 958         block->type = BLKTYPE_SSO;
 959         block->multislot = true;
 960         block->lfshift = 3;
 961         block->lookup_reg = SSO_AF_RVU_LF_CFG_DEBUG;
 962         block->pf_lfcnt_reg = RVU_PRIV_PFX_SSO_CFG;
 963         block->vf_lfcnt_reg = RVU_PRIV_HWVFX_SSO_CFG;
 964         block->lfcfg_reg = SSO_PRIV_LFX_HWGRP_CFG;
 965         block->msixcfg_reg = SSO_PRIV_LFX_HWGRP_INT_CFG;
 966         block->lfreset_reg = SSO_AF_LF_HWGRP_RST;
 967         sprintf(block->name, "SSO GROUP");
 968         err = rvu_alloc_bitmap(&block->lf);
 969         if (err) {
 970                 dev_err(rvu->dev,
 971                         "%s: Failed to allocate SSO LF bitmap\n", __func__);
 972                 return err;
 973         }
 974
 975 ssow:
 976         /* Init SSO workslot's bitmap */
 977         block = &hw->block[BLKADDR_SSOW];
 978         if (!block->implemented)
 979                 goto tim;
 980         block->lf.max = (cfg >> 56) & 0xFF;
 981         block->addr = BLKADDR_SSOW;
 982         block->type = BLKTYPE_SSOW;
 983         block->multislot = true;
 984         block->lfshift = 3;
 985         block->lookup_reg = SSOW_AF_RVU_LF_HWS_CFG_DEBUG;
 986         block->pf_lfcnt_reg = RVU_PRIV_PFX_SSOW_CFG;
 987         block->vf_lfcnt_reg = RVU_PRIV_HWVFX_SSOW_CFG;
 988         block->lfcfg_reg = SSOW_PRIV_LFX_HWS_CFG;
 989         block->msixcfg_reg = SSOW_PRIV_LFX_HWS_INT_CFG;
 990         block->lfreset_reg = SSOW_AF_LF_HWS_RST;
 991         sprintf(block->name, "SSOWS");
 992         err = rvu_alloc_bitmap(&block->lf);
 993         if (err) {
 994                 dev_err(rvu->dev,
 995                         "%s: Failed to allocate SSOW LF bitmap\n", __func__);
 996                 return err;
 997         }
 998
 999 tim:
1000         /* Init TIM LF's bitmap */
1001         block = &hw->block[BLKADDR_TIM];
1002         if (!block->implemented)
1003                 goto cpt;
1004         cfg = rvu_read64(rvu, BLKADDR_TIM, TIM_AF_CONST);
1005         block->lf.max = cfg & 0xFFFF;
1006         block->addr = BLKADDR_TIM;
1007         block->type = BLKTYPE_TIM;
1008         block->multislot = true;
1009         block->lfshift = 3;
1010         block->lookup_reg = TIM_AF_RVU_LF_CFG_DEBUG;
1011         block->pf_lfcnt_reg = RVU_PRIV_PFX_TIM_CFG;
1012         block->vf_lfcnt_reg = RVU_PRIV_HWVFX_TIM_CFG;
1013         block->lfcfg_reg = TIM_PRIV_LFX_CFG;
1014         block->msixcfg_reg = TIM_PRIV_LFX_INT_CFG;
1015         block->lfreset_reg = TIM_AF_LF_RST;
1016         sprintf(block->name, "TIM");
1017         err = rvu_alloc_bitmap(&block->lf);
1018         if (err) {
1019                 dev_err(rvu->dev,
1020                         "%s: Failed to allocate TIM LF bitmap\n", __func__);
1021                 return err;
1022         }
1023
1024 cpt:
1025         err = rvu_setup_cpt_hw_resource(rvu, BLKADDR_CPT0);
1026         if (err) {
1027                 dev_err(rvu->dev,
1028                         "%s: Failed to allocate CPT0 LF bitmap\n", __func__);
1029                 return err;
1030         }
1031         err = rvu_setup_cpt_hw_resource(rvu, BLKADDR_CPT1);
1032         if (err) {
1033                 dev_err(rvu->dev,
1034                         "%s: Failed to allocate CPT1 LF bitmap\n", __func__);
1035                 return err;
1036         }
1037
1038         /* Allocate memory for PFVF data */
1039         rvu->pf = devm_kcalloc(rvu->dev, hw->total_pfs,
1040                                sizeof(struct rvu_pfvf), GFP_KERNEL);
1041         if (!rvu->pf) {
1042                 dev_err(rvu->dev,
1043                         "%s: Failed to allocate memory for PF's rvu_pfvf struct\n", __func__);
1044                 return -ENOMEM;
1045         }
1046
1047         rvu->hwvf = devm_kcalloc(rvu->dev, hw->total_vfs,
1048                                  sizeof(struct rvu_pfvf), GFP_KERNEL);
1049         if (!rvu->hwvf) {
1050                 dev_err(rvu->dev,
1051                         "%s: Failed to allocate memory for VF's rvu_pfvf struct\n", __func__);
1052                 return -ENOMEM;
1053         }
1054
1055         mutex_init(&rvu->rsrc_lock);
1056
1057         rvu_fwdata_init(rvu);
1058
1059         err = rvu_setup_msix_resources(rvu);
1060         if (err) {
1061                 dev_err(rvu->dev,
1062                         "%s: Failed to setup MSIX resources\n", __func__);
1063                 return err;
1064         }
1065
1066         for (blkid = 0; blkid < BLK_COUNT; blkid++) {
1067                 block = &hw->block[blkid];
1068                 if (!block->lf.bmap)
1069                         continue;
1070
1071                 /* Allocate memory for block LF/slot to pcifunc mapping info */
1072                 block->fn_map = devm_kcalloc(rvu->dev, block->lf.max,
1073                                              sizeof(u16), GFP_KERNEL);
1074                 if (!block->fn_map) {
1075                         err = -ENOMEM;
1076                         goto msix_err;
1077                 }
1078
1079                 /* Scan all blocks to check if low level firmware has
1080                  * already provisioned any of the resources to a PF/VF.
1081                  */
1082                 rvu_scan_block(rvu, block);
1083         }
1084
1085         err = rvu_set_channels_base(rvu);
1086         if (err)
1087                 goto msix_err;
1088
1089         err = rvu_npc_init(rvu);
1090         if (err) {
1091                 dev_err(rvu->dev, "%s: Failed to initialize npc\n", __func__);
1092                 goto npc_err;
1093         }
1094
1095         err = rvu_cgx_init(rvu);
1096         if (err) {
1097                 dev_err(rvu->dev, "%s: Failed to initialize cgx\n", __func__);
1098                 goto cgx_err;
1099         }
1100
1101         /* Assign MACs for CGX mapped functions */
1102         rvu_setup_pfvf_macaddress(rvu);
1103
1104         err = rvu_npa_init(rvu);
1105         if (err) {
1106                 dev_err(rvu->dev, "%s: Failed to initialize npa\n", __func__);
1107                 goto npa_err;
1108         }
1109
1110         rvu_get_lbk_bufsize(rvu);
1111
1112         err = rvu_nix_init(rvu);
1113         if (err) {
1114                 dev_err(rvu->dev, "%s: Failed to initialize nix\n", __func__);
1115                 goto nix_err;
1116         }
1117
1118         rvu_program_channels(rvu);
1119
1120         return 0;
1121
1122 nix_err:
1123         rvu_nix_freemem(rvu);
1124 npa_err:
1125         rvu_npa_freemem(rvu);
1126 cgx_err:
1127         rvu_cgx_exit(rvu);
1128 npc_err:
1129         rvu_npc_freemem(rvu);
1130         rvu_fwdata_exit(rvu);
1131 msix_err:
1132         rvu_reset_msix(rvu);
1133         return err;
1134 }
1135
1136 /* NPA and NIX admin queue APIs */
1137 void rvu_aq_free(struct rvu *rvu, struct admin_queue *aq)
1138 {
1139         if (!aq)
1140                 return;
1141
1142         qmem_free(rvu->dev, aq->inst);
1143         qmem_free(rvu->dev, aq->res);
1144         devm_kfree(rvu->dev, aq);
1145 }
1146
1147 int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue,
1148                  int qsize, int inst_size, int res_size)
1149 {
1150         struct admin_queue *aq;
1151         int err;
1152
1153         *ad_queue = devm_kzalloc(rvu->dev, sizeof(*aq), GFP_KERNEL);
1154         if (!*ad_queue)
1155                 return -ENOMEM;
1156         aq = *ad_queue;
1157
1158         /* Alloc memory for instructions i.e AQ */
1159         err = qmem_alloc(rvu->dev, &aq->inst, qsize, inst_size);
1160         if (err) {
1161                 devm_kfree(rvu->dev, aq);
1162                 return err;
1163         }
1164
1165         /* Alloc memory for results */
1166         err = qmem_alloc(rvu->dev, &aq->res, qsize, res_size);
1167         if (err) {
1168                 rvu_aq_free(rvu, aq);
1169                 return err;
1170         }
1171
1172         spin_lock_init(&aq->lock);
1173         return 0;
1174 }
1175
1176 int rvu_mbox_handler_ready(struct rvu *rvu, struct msg_req *req,
1177                            struct ready_msg_rsp *rsp)
1178 {
1179         if (rvu->fwdata) {
1180                 rsp->rclk_freq = rvu->fwdata->rclk;
1181                 rsp->sclk_freq = rvu->fwdata->sclk;
1182         }
1183         return 0;
1184 }
1185
1186 /* Get current count of a RVU block's LF/slots
1187  * provisioned to a given RVU func.
1188  */
1189 u16 rvu_get_rsrc_mapcount(struct rvu_pfvf *pfvf, int blkaddr)
1190 {
1191         switch (blkaddr) {
1192         case BLKADDR_NPA:
1193                 return pfvf->npalf ? 1 : 0;
1194         case BLKADDR_NIX0:
1195         case BLKADDR_NIX1:
1196                 return pfvf->nixlf ? 1 : 0;
1197         case BLKADDR_SSO:
1198                 return pfvf->sso;
1199         case BLKADDR_SSOW:
1200                 return pfvf->ssow;
1201         case BLKADDR_TIM:
1202                 return pfvf->timlfs;
1203         case BLKADDR_CPT0:
1204                 return pfvf->cptlfs;
1205         case BLKADDR_CPT1:
1206                 return pfvf->cpt1_lfs;
1207         }
1208         return 0;
1209 }
1210
1211 /* Return true if LFs of block type are attached to pcifunc */
1212 static bool is_blktype_attached(struct rvu_pfvf *pfvf, int blktype)
1213 {
1214         switch (blktype) {
1215         case BLKTYPE_NPA:
1216                 return pfvf->npalf ? 1 : 0;
1217         case BLKTYPE_NIX:
1218                 return pfvf->nixlf ? 1 : 0;
1219         case BLKTYPE_SSO:
1220                 return !!pfvf->sso;
1221         case BLKTYPE_SSOW:
1222                 return !!pfvf->ssow;
1223         case BLKTYPE_TIM:
1224                 return !!pfvf->timlfs;
1225         case BLKTYPE_CPT:
1226                 return pfvf->cptlfs || pfvf->cpt1_lfs;
1227         }
1228
1229         return false;
1230 }
1231
1232 bool is_pffunc_map_valid(struct rvu *rvu, u16 pcifunc, int blktype)
1233 {
1234         struct rvu_pfvf *pfvf;
1235
1236         if (!is_pf_func_valid(rvu, pcifunc))
1237                 return false;
1238
1239         pfvf = rvu_get_pfvf(rvu, pcifunc);
1240
1241         /* Check if this PFFUNC has a LF of type blktype attached */
1242         if (!is_blktype_attached(pfvf, blktype))
1243                 return false;
1244
1245         return true;
1246 }
1247
1248 static int rvu_lookup_rsrc(struct rvu *rvu, struct rvu_block *block,
1249                            int pcifunc, int slot)
1250 {
1251         u64 val;
1252
1253         val = ((u64)pcifunc << 24) | (slot << 16) | (1ULL << 13);
1254         rvu_write64(rvu, block->addr, block->lookup_reg, val);
1255         /* Wait for the lookup to finish */
1256         /* TODO: put some timeout here */
1257         while (rvu_read64(rvu, block->addr, block->lookup_reg) & (1ULL << 13))
1258                 ;
1259
1260         val = rvu_read64(rvu, block->addr, block->lookup_reg);
1261
1262         /* Check LF valid bit */
1263         if (!(val & (1ULL << 12)))
1264                 return -1;
1265
1266         return (val & 0xFFF);
1267 }
1268
1269 static void rvu_detach_block(struct rvu *rvu, int pcifunc, int blktype)
1270 {
1271         struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
1272         struct rvu_hwinfo *hw = rvu->hw;
1273         struct rvu_block *block;
1274         int slot, lf, num_lfs;
1275         int blkaddr;
1276
1277         blkaddr = rvu_get_blkaddr(rvu, blktype, pcifunc);
1278         if (blkaddr < 0)
1279                 return;
1280
1281         if (blktype == BLKTYPE_NIX)
1282                 rvu_nix_reset_mac(pfvf, pcifunc);
1283
1284         block = &hw->block[blkaddr];
1285
1286         num_lfs = rvu_get_rsrc_mapcount(pfvf, block->addr);
1287         if (!num_lfs)
1288                 return;
1289
1290         for (slot = 0; slot < num_lfs; slot++) {
1291                 lf = rvu_lookup_rsrc(rvu, block, pcifunc, slot);
1292                 if (lf < 0) /* This should never happen */
1293                         continue;
1294
1295                 /* Disable the LF */
1296                 rvu_write64(rvu, blkaddr, block->lfcfg_reg |
1297                             (lf << block->lfshift), 0x00ULL);
1298
1299                 /* Update SW maintained mapping info as well */
1300                 rvu_update_rsrc_map(rvu, pfvf, block,
1301                                     pcifunc, lf, false);
1302
1303                 /* Free the resource */
1304                 rvu_free_rsrc(&block->lf, lf);
1305
1306                 /* Clear MSIX vector offset for this LF */
1307                 rvu_clear_msix_offset(rvu, pfvf, block, lf);
1308         }
1309 }
1310
1311 static int rvu_detach_rsrcs(struct rvu *rvu, struct rsrc_detach *detach,
1312                             u16 pcifunc)
1313 {
1314         struct rvu_hwinfo *hw = rvu->hw;
1315         bool detach_all = true;
1316         struct rvu_block *block;
1317         int blkid;
1318
1319         mutex_lock(&rvu->rsrc_lock);
1320
1321         /* Check for partial resource detach */
1322         if (detach && detach->partial)
1323                 detach_all = false;
1324
1325         /* Check for RVU block's LFs attached to this func,
1326          * if so, detach them.
1327          */
1328         for (blkid = 0; blkid < BLK_COUNT; blkid++) {
1329                 block = &hw->block[blkid];
1330                 if (!block->lf.bmap)
1331                         continue;
1332                 if (!detach_all && detach) {
1333                         if (blkid == BLKADDR_NPA && !detach->npalf)
1334                                 continue;
1335                         else if ((blkid == BLKADDR_NIX0) && !detach->nixlf)
1336                                 continue;
1337                         else if ((blkid == BLKADDR_NIX1) && !detach->nixlf)
1338                                 continue;
1339                         else if ((blkid == BLKADDR_SSO) && !detach->sso)
1340                                 continue;
1341                         else if ((blkid == BLKADDR_SSOW) && !detach->ssow)
1342                                 continue;
1343                         else if ((blkid == BLKADDR_TIM) && !detach->timlfs)
1344                                 continue;
1345                         else if ((blkid == BLKADDR_CPT0) && !detach->cptlfs)
1346                                 continue;
1347                         else if ((blkid == BLKADDR_CPT1) && !detach->cptlfs)
1348                                 continue;
1349                 }
1350                 rvu_detach_block(rvu, pcifunc, block->type);
1351         }
1352
1353         mutex_unlock(&rvu->rsrc_lock);
1354         return 0;
1355 }
1356
1357 int rvu_mbox_handler_detach_resources(struct rvu *rvu,
1358                                       struct rsrc_detach *detach,
1359                                       struct msg_rsp *rsp)
1360 {
1361         return rvu_detach_rsrcs(rvu, detach, detach->hdr.pcifunc);
1362 }
1363
1364 int rvu_get_nix_blkaddr(struct rvu *rvu, u16 pcifunc)
1365 {
1366         struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
1367         int blkaddr = BLKADDR_NIX0, vf;
1368         struct rvu_pfvf *pf;
1369
1370         /* All CGX mapped PFs are set with assigned NIX block during init */
1371         if (is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc))) {
1372                 pf = rvu_get_pfvf(rvu, pcifunc & ~RVU_PFVF_FUNC_MASK);
1373                 blkaddr = pf->nix_blkaddr;
1374         } else if (is_afvf(pcifunc)) {
1375                 vf = pcifunc - 1;
1376                 /* Assign NIX based on VF number. All even numbered VFs get
1377                  * NIX0 and odd numbered gets NIX1
1378                  */
1379                 blkaddr = (vf & 1) ? BLKADDR_NIX1 : BLKADDR_NIX0;
1380                 /* NIX1 is not present on all silicons */
1381                 if (!is_block_implemented(rvu->hw, BLKADDR_NIX1))
1382                         blkaddr = BLKADDR_NIX0;
1383         }
1384
1385         switch (blkaddr) {
1386         case BLKADDR_NIX1:
1387                 pfvf->nix_blkaddr = BLKADDR_NIX1;
1388                 pfvf->nix_rx_intf = NIX_INTFX_RX(1);
1389                 pfvf->nix_tx_intf = NIX_INTFX_TX(1);
1390                 break;
1391         case BLKADDR_NIX0:
1392         default:
1393                 pfvf->nix_blkaddr = BLKADDR_NIX0;
1394                 pfvf->nix_rx_intf = NIX_INTFX_RX(0);
1395                 pfvf->nix_tx_intf = NIX_INTFX_TX(0);
1396                 break;
1397         }
1398
1399         return pfvf->nix_blkaddr;
1400 }
1401
1402 static int rvu_get_attach_blkaddr(struct rvu *rvu, int blktype,
1403                                   u16 pcifunc, struct rsrc_attach *attach)
1404 {
1405         int blkaddr;
1406
1407         switch (blktype) {
1408         case BLKTYPE_NIX:
1409                 blkaddr = rvu_get_nix_blkaddr(rvu, pcifunc);
1410                 break;
1411         case BLKTYPE_CPT:
1412                 if (attach->hdr.ver < RVU_MULTI_BLK_VER)
1413                         return rvu_get_blkaddr(rvu, blktype, 0);
1414                 blkaddr = attach->cpt_blkaddr ? attach->cpt_blkaddr :
1415                           BLKADDR_CPT0;
1416                 if (blkaddr != BLKADDR_CPT0 && blkaddr != BLKADDR_CPT1)
1417                         return -ENODEV;
1418                 break;
1419         default:
1420                 return rvu_get_blkaddr(rvu, blktype, 0);
1421         }
1422
1423         if (is_block_implemented(rvu->hw, blkaddr))
1424                 return blkaddr;
1425
1426         return -ENODEV;
1427 }
1428
1429 static void rvu_attach_block(struct rvu *rvu, int pcifunc, int blktype,
1430                              int num_lfs, struct rsrc_attach *attach)
1431 {
1432         struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
1433         struct rvu_hwinfo *hw = rvu->hw;
1434         struct rvu_block *block;
1435         int slot, lf;
1436         int blkaddr;
1437         u64 cfg;
1438
1439         if (!num_lfs)
1440                 return;
1441
1442         blkaddr = rvu_get_attach_blkaddr(rvu, blktype, pcifunc, attach);
1443         if (blkaddr < 0)
1444                 return;
1445
1446         block = &hw->block[blkaddr];
1447         if (!block->lf.bmap)
1448                 return;
1449
1450         for (slot = 0; slot < num_lfs; slot++) {
1451                 /* Allocate the resource */
1452                 lf = rvu_alloc_rsrc(&block->lf);
1453                 if (lf < 0)
1454                         return;
1455
1456                 cfg = (1ULL << 63) | (pcifunc << 8) | slot;
1457                 rvu_write64(rvu, blkaddr, block->lfcfg_reg |
1458                             (lf << block->lfshift), cfg);
1459                 rvu_update_rsrc_map(rvu, pfvf, block,
1460                                     pcifunc, lf, true);
1461
1462                 /* Set start MSIX vector for this LF within this PF/VF */
1463                 rvu_set_msix_offset(rvu, pfvf, block, lf);
1464         }
1465 }
1466
1467 static int rvu_check_rsrc_availability(struct rvu *rvu,
1468                                        struct rsrc_attach *req, u16 pcifunc)
1469 {
1470         struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
1471         int free_lfs, mappedlfs, blkaddr;
1472         struct rvu_hwinfo *hw = rvu->hw;
1473         struct rvu_block *block;
1474
1475         /* Only one NPA LF can be attached */
1476         if (req->npalf && !is_blktype_attached(pfvf, BLKTYPE_NPA)) {
1477                 block = &hw->block[BLKADDR_NPA];
1478                 free_lfs = rvu_rsrc_free_count(&block->lf);
1479                 if (!free_lfs)
1480                         goto fail;
1481         } else if (req->npalf) {
1482                 dev_err(&rvu->pdev->dev,
1483                         "Func 0x%x: Invalid req, already has NPA\n",
1484                          pcifunc);
1485                 return -EINVAL;
1486         }
1487
1488         /* Only one NIX LF can be attached */
1489         if (req->nixlf && !is_blktype_attached(pfvf, BLKTYPE_NIX)) {
1490                 blkaddr = rvu_get_attach_blkaddr(rvu, BLKTYPE_NIX,
1491                                                  pcifunc, req);
1492                 if (blkaddr < 0)
1493                         return blkaddr;
1494                 block = &hw->block[blkaddr];
1495                 free_lfs = rvu_rsrc_free_count(&block->lf);
1496                 if (!free_lfs)
1497                         goto fail;
1498         } else if (req->nixlf) {
1499                 dev_err(&rvu->pdev->dev,
1500                         "Func 0x%x: Invalid req, already has NIX\n",
1501                         pcifunc);
1502                 return -EINVAL;
1503         }
1504
1505         if (req->sso) {
1506                 block = &hw->block[BLKADDR_SSO];
1507                 /* Is request within limits ? */
1508                 if (req->sso > block->lf.max) {
1509                         dev_err(&rvu->pdev->dev,
1510                                 "Func 0x%x: Invalid SSO req, %d > max %d\n",
1511                                  pcifunc, req->sso, block->lf.max);
1512                         return -EINVAL;
1513                 }
1514                 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr);
1515                 free_lfs = rvu_rsrc_free_count(&block->lf);
1516                 /* Check if additional resources are available */
1517                 if (req->sso > mappedlfs &&
1518                     ((req->sso - mappedlfs) > free_lfs))
1519                         goto fail;
1520         }
1521
1522         if (req->ssow) {
1523                 block = &hw->block[BLKADDR_SSOW];
1524                 if (req->ssow > block->lf.max) {
1525                         dev_err(&rvu->pdev->dev,
1526                                 "Func 0x%x: Invalid SSOW req, %d > max %d\n",
1527                                  pcifunc, req->sso, block->lf.max);
1528                         return -EINVAL;
1529                 }
1530                 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr);
1531                 free_lfs = rvu_rsrc_free_count(&block->lf);
1532                 if (req->ssow > mappedlfs &&
1533                     ((req->ssow - mappedlfs) > free_lfs))
1534                         goto fail;
1535         }
1536
1537         if (req->timlfs) {
1538                 block = &hw->block[BLKADDR_TIM];
1539                 if (req->timlfs > block->lf.max) {
1540                         dev_err(&rvu->pdev->dev,
1541                                 "Func 0x%x: Invalid TIMLF req, %d > max %d\n",
1542                                  pcifunc, req->timlfs, block->lf.max);
1543                         return -EINVAL;
1544                 }
1545                 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr);
1546                 free_lfs = rvu_rsrc_free_count(&block->lf);
1547                 if (req->timlfs > mappedlfs &&
1548                     ((req->timlfs - mappedlfs) > free_lfs))
1549                         goto fail;
1550         }
1551
1552         if (req->cptlfs) {
1553                 blkaddr = rvu_get_attach_blkaddr(rvu, BLKTYPE_CPT,
1554                                                  pcifunc, req);
1555                 if (blkaddr < 0)
1556                         return blkaddr;
1557                 block = &hw->block[blkaddr];
1558                 if (req->cptlfs > block->lf.max) {
1559                         dev_err(&rvu->pdev->dev,
1560                                 "Func 0x%x: Invalid CPTLF req, %d > max %d\n",
1561                                  pcifunc, req->cptlfs, block->lf.max);
1562                         return -EINVAL;
1563                 }
1564                 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr);
1565                 free_lfs = rvu_rsrc_free_count(&block->lf);
1566                 if (req->cptlfs > mappedlfs &&
1567                     ((req->cptlfs - mappedlfs) > free_lfs))
1568                         goto fail;
1569         }
1570
1571         return 0;
1572
1573 fail:
1574         dev_info(rvu->dev, "Request for %s failed\n", block->name);
1575         return -ENOSPC;
1576 }
1577
1578 static bool rvu_attach_from_same_block(struct rvu *rvu, int blktype,
1579                                        struct rsrc_attach *attach)
1580 {
1581         int blkaddr, num_lfs;
1582
1583         blkaddr = rvu_get_attach_blkaddr(rvu, blktype,
1584                                          attach->hdr.pcifunc, attach);
1585         if (blkaddr < 0)
1586                 return false;
1587
1588         num_lfs = rvu_get_rsrc_mapcount(rvu_get_pfvf(rvu, attach->hdr.pcifunc),
1589                                         blkaddr);
1590         /* Requester already has LFs from given block ? */
1591         return !!num_lfs;
1592 }
1593
1594 int rvu_mbox_handler_attach_resources(struct rvu *rvu,
1595                                       struct rsrc_attach *attach,
1596                                       struct msg_rsp *rsp)
1597 {
1598         u16 pcifunc = attach->hdr.pcifunc;
1599         int err;
1600
1601         /* If first request, detach all existing attached resources */
1602         if (!attach->modify)
1603                 rvu_detach_rsrcs(rvu, NULL, pcifunc);
1604
1605         mutex_lock(&rvu->rsrc_lock);
1606
1607         /* Check if the request can be accommodated */
1608         err = rvu_check_rsrc_availability(rvu, attach, pcifunc);
1609         if (err)
1610                 goto exit;
1611
1612         /* Now attach the requested resources */
1613         if (attach->npalf)
1614                 rvu_attach_block(rvu, pcifunc, BLKTYPE_NPA, 1, attach);
1615
1616         if (attach->nixlf)
1617                 rvu_attach_block(rvu, pcifunc, BLKTYPE_NIX, 1, attach);
1618
1619         if (attach->sso) {
1620                 /* RVU func doesn't know which exact LF or slot is attached
1621                  * to it, it always sees as slot 0,1,2. So for a 'modify'
1622                  * request, simply detach all existing attached LFs/slots
1623                  * and attach a fresh.
1624                  */
1625                 if (attach->modify)
1626                         rvu_detach_block(rvu, pcifunc, BLKTYPE_SSO);
1627                 rvu_attach_block(rvu, pcifunc, BLKTYPE_SSO,
1628                                  attach->sso, attach);
1629         }
1630
1631         if (attach->ssow) {
1632                 if (attach->modify)
1633                         rvu_detach_block(rvu, pcifunc, BLKTYPE_SSOW);
1634                 rvu_attach_block(rvu, pcifunc, BLKTYPE_SSOW,
1635                                  attach->ssow, attach);
1636         }
1637
1638         if (attach->timlfs) {
1639                 if (attach->modify)
1640                         rvu_detach_block(rvu, pcifunc, BLKTYPE_TIM);
1641                 rvu_attach_block(rvu, pcifunc, BLKTYPE_TIM,
1642                                  attach->timlfs, attach);
1643         }
1644
1645         if (attach->cptlfs) {
1646                 if (attach->modify &&
1647                     rvu_attach_from_same_block(rvu, BLKTYPE_CPT, attach))
1648                         rvu_detach_block(rvu, pcifunc, BLKTYPE_CPT);
1649                 rvu_attach_block(rvu, pcifunc, BLKTYPE_CPT,
1650                                  attach->cptlfs, attach);
1651         }
1652
1653 exit:
1654         mutex_unlock(&rvu->rsrc_lock);
1655         return err;
1656 }
1657
1658 static u16 rvu_get_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf,
1659                                int blkaddr, int lf)
1660 {
1661         u16 vec;
1662
1663         if (lf < 0)
1664                 return MSIX_VECTOR_INVALID;
1665
1666         for (vec = 0; vec < pfvf->msix.max; vec++) {
1667                 if (pfvf->msix_lfmap[vec] == MSIX_BLKLF(blkaddr, lf))
1668                         return vec;
1669         }
1670         return MSIX_VECTOR_INVALID;
1671 }
1672
1673 static void rvu_set_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf,
1674                                 struct rvu_block *block, int lf)
1675 {
1676         u16 nvecs, vec, offset;
1677         u64 cfg;
1678
1679         cfg = rvu_read64(rvu, block->addr, block->msixcfg_reg |
1680                          (lf << block->lfshift));
1681         nvecs = (cfg >> 12) & 0xFF;
1682
1683         /* Check and alloc MSIX vectors, must be contiguous */
1684         if (!rvu_rsrc_check_contig(&pfvf->msix, nvecs))
1685                 return;
1686
1687         offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs);
1688
1689         /* Config MSIX offset in LF */
1690         rvu_write64(rvu, block->addr, block->msixcfg_reg |
1691                     (lf << block->lfshift), (cfg & ~0x7FFULL) | offset);
1692
1693         /* Update the bitmap as well */
1694         for (vec = 0; vec < nvecs; vec++)
1695                 pfvf->msix_lfmap[offset + vec] = MSIX_BLKLF(block->addr, lf);
1696 }
1697
1698 static void rvu_clear_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf,
1699                                   struct rvu_block *block, int lf)
1700 {
1701         u16 nvecs, vec, offset;
1702         u64 cfg;
1703
1704         cfg = rvu_read64(rvu, block->addr, block->msixcfg_reg |
1705                          (lf << block->lfshift));
1706         nvecs = (cfg >> 12) & 0xFF;
1707
1708         /* Clear MSIX offset in LF */
1709         rvu_write64(rvu, block->addr, block->msixcfg_reg |
1710                     (lf << block->lfshift), cfg & ~0x7FFULL);
1711
1712         offset = rvu_get_msix_offset(rvu, pfvf, block->addr, lf);
1713
1714         /* Update the mapping */
1715         for (vec = 0; vec < nvecs; vec++)
1716                 pfvf->msix_lfmap[offset + vec] = 0;
1717
1718         /* Free the same in MSIX bitmap */
1719         rvu_free_rsrc_contig(&pfvf->msix, nvecs, offset);
1720 }
1721
1722 int rvu_mbox_handler_msix_offset(struct rvu *rvu, struct msg_req *req,
1723                                  struct msix_offset_rsp *rsp)
1724 {
1725         struct rvu_hwinfo *hw = rvu->hw;
1726         u16 pcifunc = req->hdr.pcifunc;
1727         struct rvu_pfvf *pfvf;
1728         int lf, slot, blkaddr;
1729
1730         pfvf = rvu_get_pfvf(rvu, pcifunc);
1731         if (!pfvf->msix.bmap)
1732                 return 0;
1733
1734         /* Set MSIX offsets for each block's LFs attached to this PF/VF */
1735         lf = rvu_get_lf(rvu, &hw->block[BLKADDR_NPA], pcifunc, 0);
1736         rsp->npa_msixoff = rvu_get_msix_offset(rvu, pfvf, BLKADDR_NPA, lf);
1737
1738         /* Get BLKADDR from which LFs are attached to pcifunc */
1739         blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc);
1740         if (blkaddr < 0) {
1741                 rsp->nix_msixoff = MSIX_VECTOR_INVALID;
1742         } else {
1743                 lf = rvu_get_lf(rvu, &hw->block[blkaddr], pcifunc, 0);
1744                 rsp->nix_msixoff = rvu_get_msix_offset(rvu, pfvf, blkaddr, lf);
1745         }
1746
1747         rsp->sso = pfvf->sso;
1748         for (slot = 0; slot < rsp->sso; slot++) {
1749                 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_SSO], pcifunc, slot);
1750                 rsp->sso_msixoff[slot] =
1751                         rvu_get_msix_offset(rvu, pfvf, BLKADDR_SSO, lf);
1752         }
1753
1754         rsp->ssow = pfvf->ssow;
1755         for (slot = 0; slot < rsp->ssow; slot++) {
1756                 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_SSOW], pcifunc, slot);
1757                 rsp->ssow_msixoff[slot] =
1758                         rvu_get_msix_offset(rvu, pfvf, BLKADDR_SSOW, lf);
1759         }
1760
1761         rsp->timlfs = pfvf->timlfs;
1762         for (slot = 0; slot < rsp->timlfs; slot++) {
1763                 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_TIM], pcifunc, slot);
1764                 rsp->timlf_msixoff[slot] =
1765                         rvu_get_msix_offset(rvu, pfvf, BLKADDR_TIM, lf);
1766         }
1767
1768         rsp->cptlfs = pfvf->cptlfs;
1769         for (slot = 0; slot < rsp->cptlfs; slot++) {
1770                 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_CPT0], pcifunc, slot);
1771                 rsp->cptlf_msixoff[slot] =
1772                         rvu_get_msix_offset(rvu, pfvf, BLKADDR_CPT0, lf);
1773         }
1774
1775         rsp->cpt1_lfs = pfvf->cpt1_lfs;
1776         for (slot = 0; slot < rsp->cpt1_lfs; slot++) {
1777                 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_CPT1], pcifunc, slot);
1778                 rsp->cpt1_lf_msixoff[slot] =
1779                         rvu_get_msix_offset(rvu, pfvf, BLKADDR_CPT1, lf);
1780         }
1781
1782         return 0;
1783 }
1784
1785 int rvu_mbox_handler_vf_flr(struct rvu *rvu, struct msg_req *req,
1786                             struct msg_rsp *rsp)
1787 {
1788         u16 pcifunc = req->hdr.pcifunc;
1789         u16 vf, numvfs;
1790         u64 cfg;
1791
1792         vf = pcifunc & RVU_PFVF_FUNC_MASK;
1793         cfg = rvu_read64(rvu, BLKADDR_RVUM,
1794                          RVU_PRIV_PFX_CFG(rvu_get_pf(pcifunc)));
1795         numvfs = (cfg >> 12) & 0xFF;
1796
1797         if (vf && vf <= numvfs)
1798                 __rvu_flr_handler(rvu, pcifunc);
1799         else
1800                 return RVU_INVALID_VF_ID;
1801
1802         return 0;
1803 }
1804
1805 int rvu_mbox_handler_get_hw_cap(struct rvu *rvu, struct msg_req *req,
1806                                 struct get_hw_cap_rsp *rsp)
1807 {
1808         struct rvu_hwinfo *hw = rvu->hw;
1809
1810         rsp->nix_fixed_txschq_mapping = hw->cap.nix_fixed_txschq_mapping;
1811         rsp->nix_shaping = hw->cap.nix_shaping;
1812
1813         return 0;
1814 }
1815
1816 int rvu_mbox_handler_set_vf_perm(struct rvu *rvu, struct set_vf_perm *req,
1817                                  struct msg_rsp *rsp)
1818 {
1819         struct rvu_hwinfo *hw = rvu->hw;
1820         u16 pcifunc = req->hdr.pcifunc;
1821         struct rvu_pfvf *pfvf;
1822         int blkaddr, nixlf;
1823         u16 target;
1824
1825         /* Only PF can add VF permissions */
1826         if ((pcifunc & RVU_PFVF_FUNC_MASK) || is_afvf(pcifunc))
1827                 return -EOPNOTSUPP;
1828
1829         target = (pcifunc & ~RVU_PFVF_FUNC_MASK) | (req->vf + 1);
1830         pfvf = rvu_get_pfvf(rvu, target);
1831
1832         if (req->flags & RESET_VF_PERM) {
1833                 pfvf->flags &= RVU_CLEAR_VF_PERM;
1834         } else if (test_bit(PF_SET_VF_TRUSTED, &pfvf->flags) ^
1835                  (req->flags & VF_TRUSTED)) {
1836                 change_bit(PF_SET_VF_TRUSTED, &pfvf->flags);
1837                 /* disable multicast and promisc entries */
1838                 if (!test_bit(PF_SET_VF_TRUSTED, &pfvf->flags)) {
1839                         blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, target);
1840                         if (blkaddr < 0)
1841                                 return 0;
1842                         nixlf = rvu_get_lf(rvu, &hw->block[blkaddr],
1843                                            target, 0);
1844                         if (nixlf < 0)
1845                                 return 0;
1846                         npc_enadis_default_mce_entry(rvu, target, nixlf,
1847                                                      NIXLF_ALLMULTI_ENTRY,
1848                                                      false);
1849                         npc_enadis_default_mce_entry(rvu, target, nixlf,
1850                                                      NIXLF_PROMISC_ENTRY,
1851                                                      false);
1852                 }
1853         }
1854
1855         return 0;
1856 }
1857
1858 static int rvu_process_mbox_msg(struct otx2_mbox *mbox, int devid,
1859                                 struct mbox_msghdr *req)
1860 {
1861         struct rvu *rvu = pci_get_drvdata(mbox->pdev);
1862
1863         /* Check if valid, if not reply with a invalid msg */
1864         if (req->sig != OTX2_MBOX_REQ_SIG)
1865                 goto bad_message;
1866
1867         switch (req->id) {
1868 #define M(_name, _id, _fn_name, _req_type, _rsp_type)                   \
1869         case _id: {                                                     \
1870                 struct _rsp_type *rsp;                                  \
1871                 int err;                                                \
1872                                                                         \
1873                 rsp = (struct _rsp_type *)otx2_mbox_alloc_msg(          \
1874                         mbox, devid,                                    \
1875                         sizeof(struct _rsp_type));                      \
1876                 /* some handlers should complete even if reply */       \
1877                 /* could not be allocated */                            \
1878                 if (!rsp &&                                             \
1879                     _id != MBOX_MSG_DETACH_RESOURCES &&                 \
1880                     _id != MBOX_MSG_NIX_TXSCH_FREE &&                   \
1881                     _id != MBOX_MSG_VF_FLR)                             \
1882                         return -ENOMEM;                                 \
1883                 if (rsp) {                                              \
1884                         rsp->hdr.id = _id;                              \
1885                         rsp->hdr.sig = OTX2_MBOX_RSP_SIG;               \
1886                         rsp->hdr.pcifunc = req->pcifunc;                \
1887                         rsp->hdr.rc = 0;                                \
1888                 }                                                       \
1889                                                                         \
1890                 err = rvu_mbox_handler_ ## _fn_name(rvu,                \
1891                                                     (struct _req_type *)req, \
1892                                                     rsp);               \
1893                 if (rsp && err)                                         \
1894                         rsp->hdr.rc = err;                              \
1895                                                                         \
1896                 trace_otx2_msg_process(mbox->pdev, _id, err);           \
1897                 return rsp ? err : -ENOMEM;                             \
1898         }
1899 MBOX_MESSAGES
1900 #undef M
1901
1902 bad_message:
1903         default:
1904                 otx2_reply_invalid_msg(mbox, devid, req->pcifunc, req->id);
1905                 return -ENODEV;
1906         }
1907 }
1908
1909 static void __rvu_mbox_handler(struct rvu_work *mwork, int type)
1910 {
1911         struct rvu *rvu = mwork->rvu;
1912         int offset, err, id, devid;
1913         struct otx2_mbox_dev *mdev;
1914         struct mbox_hdr *req_hdr;
1915         struct mbox_msghdr *msg;
1916         struct mbox_wq_info *mw;
1917         struct otx2_mbox *mbox;
1918
1919         switch (type) {
1920         case TYPE_AFPF:
1921                 mw = &rvu->afpf_wq_info;
1922                 break;
1923         case TYPE_AFVF:
1924                 mw = &rvu->afvf_wq_info;
1925                 break;
1926         default:
1927                 return;
1928         }
1929
1930         devid = mwork - mw->mbox_wrk;
1931         mbox = &mw->mbox;
1932         mdev = &mbox->dev[devid];
1933
1934         /* Process received mbox messages */
1935         req_hdr = mdev->mbase + mbox->rx_start;
1936         if (mw->mbox_wrk[devid].num_msgs == 0)
1937                 return;
1938
1939         offset = mbox->rx_start + ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN);
1940
1941         for (id = 0; id < mw->mbox_wrk[devid].num_msgs; id++) {
1942                 msg = mdev->mbase + offset;
1943
1944                 /* Set which PF/VF sent this message based on mbox IRQ */
1945                 switch (type) {
1946                 case TYPE_AFPF:
1947                         msg->pcifunc &=
1948                                 ~(RVU_PFVF_PF_MASK << RVU_PFVF_PF_SHIFT);
1949                         msg->pcifunc |= (devid << RVU_PFVF_PF_SHIFT);
1950                         break;
1951                 case TYPE_AFVF:
1952                         msg->pcifunc &=
1953                                 ~(RVU_PFVF_FUNC_MASK << RVU_PFVF_FUNC_SHIFT);
1954                         msg->pcifunc |= (devid << RVU_PFVF_FUNC_SHIFT) + 1;
1955                         break;
1956                 }
1957
1958                 err = rvu_process_mbox_msg(mbox, devid, msg);
1959                 if (!err) {
1960                         offset = mbox->rx_start + msg->next_msgoff;
1961                         continue;
1962                 }
1963
1964                 if (msg->pcifunc & RVU_PFVF_FUNC_MASK)
1965                         dev_warn(rvu->dev, "Error %d when processing message %s (0x%x) from PF%d:VF%d\n",
1966                                  err, otx2_mbox_id2name(msg->id),
1967                                  msg->id, rvu_get_pf(msg->pcifunc),
1968                                  (msg->pcifunc & RVU_PFVF_FUNC_MASK) - 1);
1969                 else
1970                         dev_warn(rvu->dev, "Error %d when processing message %s (0x%x) from PF%d\n",
1971                                  err, otx2_mbox_id2name(msg->id),
1972                                  msg->id, devid);
1973         }
1974         mw->mbox_wrk[devid].num_msgs = 0;
1975
1976         /* Send mbox responses to VF/PF */
1977         otx2_mbox_msg_send(mbox, devid);
1978 }
1979
1980 static inline void rvu_afpf_mbox_handler(struct work_struct *work)
1981 {
1982         struct rvu_work *mwork = container_of(work, struct rvu_work, work);
1983
1984         __rvu_mbox_handler(mwork, TYPE_AFPF);
1985 }
1986
1987 static inline void rvu_afvf_mbox_handler(struct work_struct *work)
1988 {
1989         struct rvu_work *mwork = container_of(work, struct rvu_work, work);
1990
1991         __rvu_mbox_handler(mwork, TYPE_AFVF);
1992 }
1993
1994 static void __rvu_mbox_up_handler(struct rvu_work *mwork, int type)
1995 {
1996         struct rvu *rvu = mwork->rvu;
1997         struct otx2_mbox_dev *mdev;
1998         struct mbox_hdr *rsp_hdr;
1999         struct mbox_msghdr *msg;
2000         struct mbox_wq_info *mw;
2001         struct otx2_mbox *mbox;
2002         int offset, id, devid;
2003
2004         switch (type) {
2005         case TYPE_AFPF:
2006                 mw = &rvu->afpf_wq_info;
2007                 break;
2008         case TYPE_AFVF:
2009                 mw = &rvu->afvf_wq_info;
2010                 break;
2011         default:
2012                 return;
2013         }
2014
2015         devid = mwork - mw->mbox_wrk_up;
2016         mbox = &mw->mbox_up;
2017         mdev = &mbox->dev[devid];
2018
2019         rsp_hdr = mdev->mbase + mbox->rx_start;
2020         if (mw->mbox_wrk_up[devid].up_num_msgs == 0) {
2021                 dev_warn(rvu->dev, "mbox up handler: num_msgs = 0\n");
2022                 return;
2023         }
2024
2025         offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN);
2026
2027         for (id = 0; id < mw->mbox_wrk_up[devid].up_num_msgs; id++) {
2028                 msg = mdev->mbase + offset;
2029
2030                 if (msg->id >= MBOX_MSG_MAX) {
2031                         dev_err(rvu->dev,
2032                                 "Mbox msg with unknown ID 0x%x\n", msg->id);
2033                         goto end;
2034                 }
2035
2036                 if (msg->sig != OTX2_MBOX_RSP_SIG) {
2037                         dev_err(rvu->dev,
2038                                 "Mbox msg with wrong signature %x, ID 0x%x\n",
2039                                 msg->sig, msg->id);
2040                         goto end;
2041                 }
2042
2043                 switch (msg->id) {
2044                 case MBOX_MSG_CGX_LINK_EVENT:
2045                         break;
2046                 default:
2047                         if (msg->rc)
2048                                 dev_err(rvu->dev,
2049                                         "Mbox msg response has err %d, ID 0x%x\n",
2050                                         msg->rc, msg->id);
2051                         break;
2052                 }
2053 end:
2054                 offset = mbox->rx_start + msg->next_msgoff;
2055                 mdev->msgs_acked++;
2056         }
2057         mw->mbox_wrk_up[devid].up_num_msgs = 0;
2058
2059         otx2_mbox_reset(mbox, devid);
2060 }
2061
2062 static inline void rvu_afpf_mbox_up_handler(struct work_struct *work)
2063 {
2064         struct rvu_work *mwork = container_of(work, struct rvu_work, work);
2065
2066         __rvu_mbox_up_handler(mwork, TYPE_AFPF);
2067 }
2068
2069 static inline void rvu_afvf_mbox_up_handler(struct work_struct *work)
2070 {
2071         struct rvu_work *mwork = container_of(work, struct rvu_work, work);
2072
2073         __rvu_mbox_up_handler(mwork, TYPE_AFVF);
2074 }
2075
2076 static int rvu_get_mbox_regions(struct rvu *rvu, void **mbox_addr,
2077                                 int num, int type)
2078 {
2079         struct rvu_hwinfo *hw = rvu->hw;
2080         int region;
2081         u64 bar4;
2082
2083         /* For cn10k platform VF mailbox regions of a PF follows after the
2084          * PF <-> AF mailbox region. Whereas for Octeontx2 it is read from
2085          * RVU_PF_VF_BAR4_ADDR register.
2086          */
2087         if (type == TYPE_AFVF) {
2088                 for (region = 0; region < num; region++) {
2089                         if (hw->cap.per_pf_mbox_regs) {
2090                                 bar4 = rvu_read64(rvu, BLKADDR_RVUM,
2091                                                   RVU_AF_PFX_BAR4_ADDR(0)) +
2092                                                   MBOX_SIZE;
2093                                 bar4 += region * MBOX_SIZE;
2094                         } else {
2095                                 bar4 = rvupf_read64(rvu, RVU_PF_VF_BAR4_ADDR);
2096                                 bar4 += region * MBOX_SIZE;
2097                         }
2098                         mbox_addr[region] = (void *)ioremap_wc(bar4, MBOX_SIZE);
2099                         if (!mbox_addr[region])
2100                                 goto error;
2101                 }
2102                 return 0;
2103         }
2104
2105         /* For cn10k platform AF <-> PF mailbox region of a PF is read from per
2106          * PF registers. Whereas for Octeontx2 it is read from
2107          * RVU_AF_PF_BAR4_ADDR register.
2108          */
2109         for (region = 0; region < num; region++) {
2110                 if (hw->cap.per_pf_mbox_regs) {
2111                         bar4 = rvu_read64(rvu, BLKADDR_RVUM,
2112                                           RVU_AF_PFX_BAR4_ADDR(region));
2113                 } else {
2114                         bar4 = rvu_read64(rvu, BLKADDR_RVUM,
2115                                           RVU_AF_PF_BAR4_ADDR);
2116                         bar4 += region * MBOX_SIZE;
2117                 }
2118                 mbox_addr[region] = (void *)ioremap_wc(bar4, MBOX_SIZE);
2119                 if (!mbox_addr[region])
2120                         goto error;
2121         }
2122         return 0;
2123
2124 error:
2125         while (region--)
2126                 iounmap((void __iomem *)mbox_addr[region]);
2127         return -ENOMEM;
2128 }
2129
2130 static int rvu_mbox_init(struct rvu *rvu, struct mbox_wq_info *mw,
2131                          int type, int num,
2132                          void (mbox_handler)(struct work_struct *),
2133                          void (mbox_up_handler)(struct work_struct *))
2134 {
2135         int err = -EINVAL, i, dir, dir_up;
2136         void __iomem *reg_base;
2137         struct rvu_work *mwork;
2138         void **mbox_regions;
2139         const char *name;
2140
2141         mbox_regions = kcalloc(num, sizeof(void *), GFP_KERNEL);
2142         if (!mbox_regions)
2143                 return -ENOMEM;
2144
2145         switch (type) {
2146         case TYPE_AFPF:
2147                 name = "rvu_afpf_mailbox";
2148                 dir = MBOX_DIR_AFPF;
2149                 dir_up = MBOX_DIR_AFPF_UP;
2150                 reg_base = rvu->afreg_base;
2151                 err = rvu_get_mbox_regions(rvu, mbox_regions, num, TYPE_AFPF);
2152                 if (err)
2153                         goto free_regions;
2154                 break;
2155         case TYPE_AFVF:
2156                 name = "rvu_afvf_mailbox";
2157                 dir = MBOX_DIR_PFVF;
2158                 dir_up = MBOX_DIR_PFVF_UP;
2159                 reg_base = rvu->pfreg_base;
2160                 err = rvu_get_mbox_regions(rvu, mbox_regions, num, TYPE_AFVF);
2161                 if (err)
2162                         goto free_regions;
2163                 break;
2164         default:
2165                 return err;
2166         }
2167
2168         mw->mbox_wq = alloc_workqueue(name,
2169                                       WQ_UNBOUND | WQ_HIGHPRI | WQ_MEM_RECLAIM,
2170                                       num);
2171         if (!mw->mbox_wq) {
2172                 err = -ENOMEM;
2173                 goto unmap_regions;
2174         }
2175
2176         mw->mbox_wrk = devm_kcalloc(rvu->dev, num,
2177                                     sizeof(struct rvu_work), GFP_KERNEL);
2178         if (!mw->mbox_wrk) {
2179                 err = -ENOMEM;
2180                 goto exit;
2181         }
2182
2183         mw->mbox_wrk_up = devm_kcalloc(rvu->dev, num,
2184                                        sizeof(struct rvu_work), GFP_KERNEL);
2185         if (!mw->mbox_wrk_up) {
2186                 err = -ENOMEM;
2187                 goto exit;
2188         }
2189
2190         err = otx2_mbox_regions_init(&mw->mbox, mbox_regions, rvu->pdev,
2191                                      reg_base, dir, num);
2192         if (err)
2193                 goto exit;
2194
2195         err = otx2_mbox_regions_init(&mw->mbox_up, mbox_regions, rvu->pdev,
2196                                      reg_base, dir_up, num);
2197         if (err)
2198                 goto exit;
2199
2200         for (i = 0; i < num; i++) {
2201                 mwork = &mw->mbox_wrk[i];
2202                 mwork->rvu = rvu;
2203                 INIT_WORK(&mwork->work, mbox_handler);
2204
2205                 mwork = &mw->mbox_wrk_up[i];
2206                 mwork->rvu = rvu;
2207                 INIT_WORK(&mwork->work, mbox_up_handler);
2208         }
2209         kfree(mbox_regions);
2210         return 0;
2211
2212 exit:
2213         destroy_workqueue(mw->mbox_wq);
2214 unmap_regions:
2215         while (num--)
2216                 iounmap((void __iomem *)mbox_regions[num]);
2217 free_regions:
2218         kfree(mbox_regions);
2219         return err;
2220 }
2221
2222 static void rvu_mbox_destroy(struct mbox_wq_info *mw)
2223 {
2224         struct otx2_mbox *mbox = &mw->mbox;
2225         struct otx2_mbox_dev *mdev;
2226         int devid;
2227
2228         if (mw->mbox_wq) {
2229                 flush_workqueue(mw->mbox_wq);
2230                 destroy_workqueue(mw->mbox_wq);
2231                 mw->mbox_wq = NULL;
2232         }
2233
2234         for (devid = 0; devid < mbox->ndevs; devid++) {
2235                 mdev = &mbox->dev[devid];
2236                 if (mdev->hwbase)
2237                         iounmap((void __iomem *)mdev->hwbase);
2238         }
2239
2240         otx2_mbox_destroy(&mw->mbox);
2241         otx2_mbox_destroy(&mw->mbox_up);
2242 }
2243
2244 static void rvu_queue_work(struct mbox_wq_info *mw, int first,
2245                            int mdevs, u64 intr)
2246 {
2247         struct otx2_mbox_dev *mdev;
2248         struct otx2_mbox *mbox;
2249         struct mbox_hdr *hdr;
2250         int i;
2251
2252         for (i = first; i < mdevs; i++) {
2253                 /* start from 0 */
2254                 if (!(intr & BIT_ULL(i - first)))
2255                         continue;
2256
2257                 mbox = &mw->mbox;
2258                 mdev = &mbox->dev[i];
2259                 hdr = mdev->mbase + mbox->rx_start;
2260
2261                 /*The hdr->num_msgs is set to zero immediately in the interrupt
2262                  * handler to  ensure that it holds a correct value next time
2263                  * when the interrupt handler is called.
2264                  * pf->mbox.num_msgs holds the data for use in pfaf_mbox_handler
2265                  * pf>mbox.up_num_msgs holds the data for use in
2266                  * pfaf_mbox_up_handler.
2267                  */
2268
2269                 if (hdr->num_msgs) {
2270                         mw->mbox_wrk[i].num_msgs = hdr->num_msgs;
2271                         hdr->num_msgs = 0;
2272                         queue_work(mw->mbox_wq, &mw->mbox_wrk[i].work);
2273                 }
2274                 mbox = &mw->mbox_up;
2275                 mdev = &mbox->dev[i];
2276                 hdr = mdev->mbase + mbox->rx_start;
2277                 if (hdr->num_msgs) {
2278                         mw->mbox_wrk_up[i].up_num_msgs = hdr->num_msgs;
2279                         hdr->num_msgs = 0;
2280                         queue_work(mw->mbox_wq, &mw->mbox_wrk_up[i].work);
2281                 }
2282         }
2283 }
2284
2285 static irqreturn_t rvu_mbox_intr_handler(int irq, void *rvu_irq)
2286 {
2287         struct rvu *rvu = (struct rvu *)rvu_irq;
2288         int vfs = rvu->vfs;
2289         u64 intr;
2290
2291         intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT);
2292         /* Clear interrupts */
2293         rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT, intr);
2294         if (intr)
2295                 trace_otx2_msg_interrupt(rvu->pdev, "PF(s) to AF", intr);
2296
2297         /* Sync with mbox memory region */
2298         rmb();
2299
2300         rvu_queue_work(&rvu->afpf_wq_info, 0, rvu->hw->total_pfs, intr);
2301
2302         /* Handle VF interrupts */
2303         if (vfs > 64) {
2304                 intr = rvupf_read64(rvu, RVU_PF_VFPF_MBOX_INTX(1));
2305                 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(1), intr);
2306
2307                 rvu_queue_work(&rvu->afvf_wq_info, 64, vfs, intr);
2308                 vfs -= 64;
2309         }
2310
2311         intr = rvupf_read64(rvu, RVU_PF_VFPF_MBOX_INTX(0));
2312         rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(0), intr);
2313         if (intr)
2314                 trace_otx2_msg_interrupt(rvu->pdev, "VF(s) to AF", intr);
2315
2316         rvu_queue_work(&rvu->afvf_wq_info, 0, vfs, intr);
2317
2318         return IRQ_HANDLED;
2319 }
2320
2321 static void rvu_enable_mbox_intr(struct rvu *rvu)
2322 {
2323         struct rvu_hwinfo *hw = rvu->hw;
2324
2325         /* Clear spurious irqs, if any */
2326         rvu_write64(rvu, BLKADDR_RVUM,
2327                     RVU_AF_PFAF_MBOX_INT, INTR_MASK(hw->total_pfs));
2328
2329         /* Enable mailbox interrupt for all PFs except PF0 i.e AF itself */
2330         rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT_ENA_W1S,
2331                     INTR_MASK(hw->total_pfs) & ~1ULL);
2332 }
2333
2334 static void rvu_blklf_teardown(struct rvu *rvu, u16 pcifunc, u8 blkaddr)
2335 {
2336         struct rvu_block *block;
2337         int slot, lf, num_lfs;
2338         int err;
2339
2340         block = &rvu->hw->block[blkaddr];
2341         num_lfs = rvu_get_rsrc_mapcount(rvu_get_pfvf(rvu, pcifunc),
2342                                         block->addr);
2343         if (!num_lfs)
2344                 return;
2345         for (slot = 0; slot < num_lfs; slot++) {
2346                 lf = rvu_get_lf(rvu, block, pcifunc, slot);
2347                 if (lf < 0)
2348                         continue;
2349
2350                 /* Cleanup LF and reset it */
2351                 if (block->addr == BLKADDR_NIX0 || block->addr == BLKADDR_NIX1)
2352                         rvu_nix_lf_teardown(rvu, pcifunc, block->addr, lf);
2353                 else if (block->addr == BLKADDR_NPA)
2354                         rvu_npa_lf_teardown(rvu, pcifunc, lf);
2355                 else if ((block->addr == BLKADDR_CPT0) ||
2356                          (block->addr == BLKADDR_CPT1))
2357                         rvu_cpt_lf_teardown(rvu, pcifunc, lf, slot);
2358
2359                 err = rvu_lf_reset(rvu, block, lf);
2360                 if (err) {
2361                         dev_err(rvu->dev, "Failed to reset blkaddr %d LF%d\n",
2362                                 block->addr, lf);
2363                 }
2364         }
2365 }
2366
2367 static void __rvu_flr_handler(struct rvu *rvu, u16 pcifunc)
2368 {
2369         mutex_lock(&rvu->flr_lock);
2370         /* Reset order should reflect inter-block dependencies:
2371          * 1. Reset any packet/work sources (NIX, CPT, TIM)
2372          * 2. Flush and reset SSO/SSOW
2373          * 3. Cleanup pools (NPA)
2374          */
2375         rvu_blklf_teardown(rvu, pcifunc, BLKADDR_NIX0);
2376         rvu_blklf_teardown(rvu, pcifunc, BLKADDR_NIX1);
2377         rvu_blklf_teardown(rvu, pcifunc, BLKADDR_CPT0);
2378         rvu_blklf_teardown(rvu, pcifunc, BLKADDR_CPT1);
2379         rvu_blklf_teardown(rvu, pcifunc, BLKADDR_TIM);
2380         rvu_blklf_teardown(rvu, pcifunc, BLKADDR_SSOW);
2381         rvu_blklf_teardown(rvu, pcifunc, BLKADDR_SSO);
2382         rvu_blklf_teardown(rvu, pcifunc, BLKADDR_NPA);
2383         rvu_reset_lmt_map_tbl(rvu, pcifunc);
2384         rvu_detach_rsrcs(rvu, NULL, pcifunc);
2385         mutex_unlock(&rvu->flr_lock);
2386 }
2387
2388 static void rvu_afvf_flr_handler(struct rvu *rvu, int vf)
2389 {
2390         int reg = 0;
2391
2392         /* pcifunc = 0(PF0) | (vf + 1) */
2393         __rvu_flr_handler(rvu, vf + 1);
2394
2395         if (vf >= 64) {
2396                 reg = 1;
2397                 vf = vf - 64;
2398         }
2399
2400         /* Signal FLR finish and enable IRQ */
2401         rvupf_write64(rvu, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf));
2402         rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(reg), BIT_ULL(vf));
2403 }
2404
2405 static void rvu_flr_handler(struct work_struct *work)
2406 {
2407         struct rvu_work *flrwork = container_of(work, struct rvu_work, work);
2408         struct rvu *rvu = flrwork->rvu;
2409         u16 pcifunc, numvfs, vf;
2410         u64 cfg;
2411         int pf;
2412
2413         pf = flrwork - rvu->flr_wrk;
2414         if (pf >= rvu->hw->total_pfs) {
2415                 rvu_afvf_flr_handler(rvu, pf - rvu->hw->total_pfs);
2416                 return;
2417         }
2418
2419         cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf));
2420         numvfs = (cfg >> 12) & 0xFF;
2421         pcifunc  = pf << RVU_PFVF_PF_SHIFT;
2422
2423         for (vf = 0; vf < numvfs; vf++)
2424                 __rvu_flr_handler(rvu, (pcifunc | (vf + 1)));
2425
2426         __rvu_flr_handler(rvu, pcifunc);
2427
2428         /* Signal FLR finish */
2429         rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFTRPEND, BIT_ULL(pf));
2430
2431         /* Enable interrupt */
2432         rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1S,  BIT_ULL(pf));
2433 }
2434
2435 static void rvu_afvf_queue_flr_work(struct rvu *rvu, int start_vf, int numvfs)
2436 {
2437         int dev, vf, reg = 0;
2438         u64 intr;
2439
2440         if (start_vf >= 64)
2441                 reg = 1;
2442
2443         intr = rvupf_read64(rvu, RVU_PF_VFFLR_INTX(reg));
2444         if (!intr)
2445                 return;
2446
2447         for (vf = 0; vf < numvfs; vf++) {
2448                 if (!(intr & BIT_ULL(vf)))
2449                         continue;
2450                 /* Clear and disable the interrupt */
2451                 rvupf_write64(rvu, RVU_PF_VFFLR_INTX(reg), BIT_ULL(vf));
2452                 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(reg), BIT_ULL(vf));
2453
2454                 dev = vf + start_vf + rvu->hw->total_pfs;
2455                 queue_work(rvu->flr_wq, &rvu->flr_wrk[dev].work);
2456         }
2457 }
2458
2459 static irqreturn_t rvu_flr_intr_handler(int irq, void *rvu_irq)
2460 {
2461         struct rvu *rvu = (struct rvu *)rvu_irq;
2462         u64 intr;
2463         u8  pf;
2464
2465         intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT);
2466         if (!intr)
2467                 goto afvf_flr;
2468
2469         for (pf = 0; pf < rvu->hw->total_pfs; pf++) {
2470                 if (intr & (1ULL << pf)) {
2471                         /* clear interrupt */
2472                         rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT,
2473                                     BIT_ULL(pf));
2474                         /* Disable the interrupt */
2475                         rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1C,
2476                                     BIT_ULL(pf));
2477                         /* PF is already dead do only AF related operations */
2478                         queue_work(rvu->flr_wq, &rvu->flr_wrk[pf].work);
2479                 }
2480         }
2481
2482 afvf_flr:
2483         rvu_afvf_queue_flr_work(rvu, 0, 64);
2484         if (rvu->vfs > 64)
2485                 rvu_afvf_queue_flr_work(rvu, 64, rvu->vfs - 64);
2486
2487         return IRQ_HANDLED;
2488 }
2489
2490 static void rvu_me_handle_vfset(struct rvu *rvu, int idx, u64 intr)
2491 {
2492         int vf;
2493
2494         /* Nothing to be done here other than clearing the
2495          * TRPEND bit.
2496          */
2497         for (vf = 0; vf < 64; vf++) {
2498                 if (intr & (1ULL << vf)) {
2499                         /* clear the trpend due to ME(master enable) */
2500                         rvupf_write64(rvu, RVU_PF_VFTRPENDX(idx), BIT_ULL(vf));
2501                         /* clear interrupt */
2502                         rvupf_write64(rvu, RVU_PF_VFME_INTX(idx), BIT_ULL(vf));
2503                 }
2504         }
2505 }
2506
2507 /* Handles ME interrupts from VFs of AF */
2508 static irqreturn_t rvu_me_vf_intr_handler(int irq, void *rvu_irq)
2509 {
2510         struct rvu *rvu = (struct rvu *)rvu_irq;
2511         int vfset;
2512         u64 intr;
2513
2514         intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT);
2515
2516         for (vfset = 0; vfset <= 1; vfset++) {
2517                 intr = rvupf_read64(rvu, RVU_PF_VFME_INTX(vfset));
2518                 if (intr)
2519                         rvu_me_handle_vfset(rvu, vfset, intr);
2520         }
2521
2522         return IRQ_HANDLED;
2523 }
2524
2525 /* Handles ME interrupts from PFs */
2526 static irqreturn_t rvu_me_pf_intr_handler(int irq, void *rvu_irq)
2527 {
2528         struct rvu *rvu = (struct rvu *)rvu_irq;
2529         u64 intr;
2530         u8  pf;
2531
2532         intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT);
2533
2534         /* Nothing to be done here other than clearing the
2535          * TRPEND bit.
2536          */
2537         for (pf = 0; pf < rvu->hw->total_pfs; pf++) {
2538                 if (intr & (1ULL << pf)) {
2539                         /* clear the trpend due to ME(master enable) */
2540                         rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFTRPEND,
2541                                     BIT_ULL(pf));
2542                         /* clear interrupt */
2543                         rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT,
2544                                     BIT_ULL(pf));
2545                 }
2546         }
2547
2548         return IRQ_HANDLED;
2549 }
2550
2551 static void rvu_unregister_interrupts(struct rvu *rvu)
2552 {
2553         int irq;
2554
2555         /* Disable the Mbox interrupt */
2556         rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT_ENA_W1C,
2557                     INTR_MASK(rvu->hw->total_pfs) & ~1ULL);
2558
2559         /* Disable the PF FLR interrupt */
2560         rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1C,
2561                     INTR_MASK(rvu->hw->total_pfs) & ~1ULL);
2562
2563         /* Disable the PF ME interrupt */
2564         rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT_ENA_W1C,
2565                     INTR_MASK(rvu->hw->total_pfs) & ~1ULL);
2566
2567         for (irq = 0; irq < rvu->num_vec; irq++) {
2568                 if (rvu->irq_allocated[irq]) {
2569                         free_irq(pci_irq_vector(rvu->pdev, irq), rvu);
2570                         rvu->irq_allocated[irq] = false;
2571                 }
2572         }
2573
2574         pci_free_irq_vectors(rvu->pdev);
2575         rvu->num_vec = 0;
2576 }
2577
2578 static int rvu_afvf_msix_vectors_num_ok(struct rvu *rvu)
2579 {
2580         struct rvu_pfvf *pfvf = &rvu->pf[0];
2581         int offset;
2582
2583         pfvf = &rvu->pf[0];
2584         offset = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_INT_CFG(0)) & 0x3ff;
2585
2586         /* Make sure there are enough MSIX vectors configured so that
2587          * VF interrupts can be handled. Offset equal to zero means
2588          * that PF vectors are not configured and overlapping AF vectors.
2589          */
2590         return (pfvf->msix.max >= RVU_AF_INT_VEC_CNT + RVU_PF_INT_VEC_CNT) &&
2591                offset;
2592 }
2593
2594 static int rvu_register_interrupts(struct rvu *rvu)
2595 {
2596         int ret, offset, pf_vec_start;
2597
2598         rvu->num_vec = pci_msix_vec_count(rvu->pdev);
2599
2600         rvu->irq_name = devm_kmalloc_array(rvu->dev, rvu->num_vec,
2601                                            NAME_SIZE, GFP_KERNEL);
2602         if (!rvu->irq_name)
2603                 return -ENOMEM;
2604
2605         rvu->irq_allocated = devm_kcalloc(rvu->dev, rvu->num_vec,
2606                                           sizeof(bool), GFP_KERNEL);
2607         if (!rvu->irq_allocated)
2608                 return -ENOMEM;
2609
2610         /* Enable MSI-X */
2611         ret = pci_alloc_irq_vectors(rvu->pdev, rvu->num_vec,
2612                                     rvu->num_vec, PCI_IRQ_MSIX);
2613         if (ret < 0) {
2614                 dev_err(rvu->dev,
2615                         "RVUAF: Request for %d msix vectors failed, ret %d\n",
2616                         rvu->num_vec, ret);
2617                 return ret;
2618         }
2619
2620         /* Register mailbox interrupt handler */
2621         sprintf(&rvu->irq_name[RVU_AF_INT_VEC_MBOX * NAME_SIZE], "RVUAF Mbox");
2622         ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_MBOX),
2623                           rvu_mbox_intr_handler, 0,
2624                           &rvu->irq_name[RVU_AF_INT_VEC_MBOX * NAME_SIZE], rvu);
2625         if (ret) {
2626                 dev_err(rvu->dev,
2627                         "RVUAF: IRQ registration failed for mbox irq\n");
2628                 goto fail;
2629         }
2630
2631         rvu->irq_allocated[RVU_AF_INT_VEC_MBOX] = true;
2632
2633         /* Enable mailbox interrupts from all PFs */
2634         rvu_enable_mbox_intr(rvu);
2635
2636         /* Register FLR interrupt handler */
2637         sprintf(&rvu->irq_name[RVU_AF_INT_VEC_PFFLR * NAME_SIZE],
2638                 "RVUAF FLR");
2639         ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_PFFLR),
2640                           rvu_flr_intr_handler, 0,
2641                           &rvu->irq_name[RVU_AF_INT_VEC_PFFLR * NAME_SIZE],
2642                           rvu);
2643         if (ret) {
2644                 dev_err(rvu->dev,
2645                         "RVUAF: IRQ registration failed for FLR\n");
2646                 goto fail;
2647         }
2648         rvu->irq_allocated[RVU_AF_INT_VEC_PFFLR] = true;
2649
2650         /* Enable FLR interrupt for all PFs*/
2651         rvu_write64(rvu, BLKADDR_RVUM,
2652                     RVU_AF_PFFLR_INT, INTR_MASK(rvu->hw->total_pfs));
2653
2654         rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1S,
2655                     INTR_MASK(rvu->hw->total_pfs) & ~1ULL);
2656
2657         /* Register ME interrupt handler */
2658         sprintf(&rvu->irq_name[RVU_AF_INT_VEC_PFME * NAME_SIZE],
2659                 "RVUAF ME");
2660         ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_PFME),
2661                           rvu_me_pf_intr_handler, 0,
2662                           &rvu->irq_name[RVU_AF_INT_VEC_PFME * NAME_SIZE],
2663                           rvu);
2664         if (ret) {
2665                 dev_err(rvu->dev,
2666                         "RVUAF: IRQ registration failed for ME\n");
2667         }
2668         rvu->irq_allocated[RVU_AF_INT_VEC_PFME] = true;
2669
2670         /* Clear TRPEND bit for all PF */
2671         rvu_write64(rvu, BLKADDR_RVUM,
2672                     RVU_AF_PFTRPEND, INTR_MASK(rvu->hw->total_pfs));
2673         /* Enable ME interrupt for all PFs*/
2674         rvu_write64(rvu, BLKADDR_RVUM,
2675                     RVU_AF_PFME_INT, INTR_MASK(rvu->hw->total_pfs));
2676
2677         rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT_ENA_W1S,
2678                     INTR_MASK(rvu->hw->total_pfs) & ~1ULL);
2679
2680         if (!rvu_afvf_msix_vectors_num_ok(rvu))
2681                 return 0;
2682
2683         /* Get PF MSIX vectors offset. */
2684         pf_vec_start = rvu_read64(rvu, BLKADDR_RVUM,
2685                                   RVU_PRIV_PFX_INT_CFG(0)) & 0x3ff;
2686
2687         /* Register MBOX0 interrupt. */
2688         offset = pf_vec_start + RVU_PF_INT_VEC_VFPF_MBOX0;
2689         sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF Mbox0");
2690         ret = request_irq(pci_irq_vector(rvu->pdev, offset),
2691                           rvu_mbox_intr_handler, 0,
2692                           &rvu->irq_name[offset * NAME_SIZE],
2693                           rvu);
2694         if (ret)
2695                 dev_err(rvu->dev,
2696                         "RVUAF: IRQ registration failed for Mbox0\n");
2697
2698         rvu->irq_allocated[offset] = true;
2699
2700         /* Register MBOX1 interrupt. MBOX1 IRQ number follows MBOX0 so
2701          * simply increment current offset by 1.
2702          */
2703         offset = pf_vec_start + RVU_PF_INT_VEC_VFPF_MBOX1;
2704         sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF Mbox1");
2705         ret = request_irq(pci_irq_vector(rvu->pdev, offset),
2706                           rvu_mbox_intr_handler, 0,
2707                           &rvu->irq_name[offset * NAME_SIZE],
2708                           rvu);
2709         if (ret)
2710                 dev_err(rvu->dev,
2711                         "RVUAF: IRQ registration failed for Mbox1\n");
2712
2713         rvu->irq_allocated[offset] = true;
2714
2715         /* Register FLR interrupt handler for AF's VFs */
2716         offset = pf_vec_start + RVU_PF_INT_VEC_VFFLR0;
2717         sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF FLR0");
2718         ret = request_irq(pci_irq_vector(rvu->pdev, offset),
2719                           rvu_flr_intr_handler, 0,
2720                           &rvu->irq_name[offset * NAME_SIZE], rvu);
2721         if (ret) {
2722                 dev_err(rvu->dev,
2723                         "RVUAF: IRQ registration failed for RVUAFVF FLR0\n");
2724                 goto fail;
2725         }
2726         rvu->irq_allocated[offset] = true;
2727
2728         offset = pf_vec_start + RVU_PF_INT_VEC_VFFLR1;
2729         sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF FLR1");
2730         ret = request_irq(pci_irq_vector(rvu->pdev, offset),
2731                           rvu_flr_intr_handler, 0,
2732                           &rvu->irq_name[offset * NAME_SIZE], rvu);
2733         if (ret) {
2734                 dev_err(rvu->dev,
2735                         "RVUAF: IRQ registration failed for RVUAFVF FLR1\n");
2736                 goto fail;
2737         }
2738         rvu->irq_allocated[offset] = true;
2739
2740         /* Register ME interrupt handler for AF's VFs */
2741         offset = pf_vec_start + RVU_PF_INT_VEC_VFME0;
2742         sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF ME0");
2743         ret = request_irq(pci_irq_vector(rvu->pdev, offset),
2744                           rvu_me_vf_intr_handler, 0,
2745                           &rvu->irq_name[offset * NAME_SIZE], rvu);
2746         if (ret) {
2747                 dev_err(rvu->dev,
2748                         "RVUAF: IRQ registration failed for RVUAFVF ME0\n");
2749                 goto fail;
2750         }
2751         rvu->irq_allocated[offset] = true;
2752
2753         offset = pf_vec_start + RVU_PF_INT_VEC_VFME1;
2754         sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF ME1");
2755         ret = request_irq(pci_irq_vector(rvu->pdev, offset),
2756                           rvu_me_vf_intr_handler, 0,
2757                           &rvu->irq_name[offset * NAME_SIZE], rvu);
2758         if (ret) {
2759                 dev_err(rvu->dev,
2760                         "RVUAF: IRQ registration failed for RVUAFVF ME1\n");
2761                 goto fail;
2762         }
2763         rvu->irq_allocated[offset] = true;
2764         return 0;
2765
2766 fail:
2767         rvu_unregister_interrupts(rvu);
2768         return ret;
2769 }
2770
2771 static void rvu_flr_wq_destroy(struct rvu *rvu)
2772 {
2773         if (rvu->flr_wq) {
2774                 flush_workqueue(rvu->flr_wq);
2775                 destroy_workqueue(rvu->flr_wq);
2776                 rvu->flr_wq = NULL;
2777         }
2778 }
2779
2780 static int rvu_flr_init(struct rvu *rvu)
2781 {
2782         int dev, num_devs;
2783         u64 cfg;
2784         int pf;
2785
2786         /* Enable FLR for all PFs*/
2787         for (pf = 0; pf < rvu->hw->total_pfs; pf++) {
2788                 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf));
2789                 rvu_write64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf),
2790                             cfg | BIT_ULL(22));
2791         }
2792
2793         rvu->flr_wq = alloc_workqueue("rvu_afpf_flr",
2794                                       WQ_UNBOUND | WQ_HIGHPRI | WQ_MEM_RECLAIM,
2795                                        1);
2796         if (!rvu->flr_wq)
2797                 return -ENOMEM;
2798
2799         num_devs = rvu->hw->total_pfs + pci_sriov_get_totalvfs(rvu->pdev);
2800         rvu->flr_wrk = devm_kcalloc(rvu->dev, num_devs,
2801                                     sizeof(struct rvu_work), GFP_KERNEL);
2802         if (!rvu->flr_wrk) {
2803                 destroy_workqueue(rvu->flr_wq);
2804                 return -ENOMEM;
2805         }
2806
2807         for (dev = 0; dev < num_devs; dev++) {
2808                 rvu->flr_wrk[dev].rvu = rvu;
2809                 INIT_WORK(&rvu->flr_wrk[dev].work, rvu_flr_handler);
2810         }
2811
2812         mutex_init(&rvu->flr_lock);
2813
2814         return 0;
2815 }
2816
2817 static void rvu_disable_afvf_intr(struct rvu *rvu)
2818 {
2819         int vfs = rvu->vfs;
2820
2821         rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(0), INTR_MASK(vfs));
2822         rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(0), INTR_MASK(vfs));
2823         rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1CX(0), INTR_MASK(vfs));
2824         if (vfs <= 64)
2825                 return;
2826
2827         rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(1),
2828                       INTR_MASK(vfs - 64));
2829         rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(1), INTR_MASK(vfs - 64));
2830         rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1CX(1), INTR_MASK(vfs - 64));
2831 }
2832
2833 static void rvu_enable_afvf_intr(struct rvu *rvu)
2834 {
2835         int vfs = rvu->vfs;
2836
2837         /* Clear any pending interrupts and enable AF VF interrupts for
2838          * the first 64 VFs.
2839          */
2840         /* Mbox */
2841         rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(0), INTR_MASK(vfs));
2842         rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(0), INTR_MASK(vfs));
2843
2844         /* FLR */
2845         rvupf_write64(rvu, RVU_PF_VFFLR_INTX(0), INTR_MASK(vfs));
2846         rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(0), INTR_MASK(vfs));
2847         rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1SX(0), INTR_MASK(vfs));
2848
2849         /* Same for remaining VFs, if any. */
2850         if (vfs <= 64)
2851                 return;
2852
2853         rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(1), INTR_MASK(vfs - 64));
2854         rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(1),
2855                       INTR_MASK(vfs - 64));
2856
2857         rvupf_write64(rvu, RVU_PF_VFFLR_INTX(1), INTR_MASK(vfs - 64));
2858         rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(1), INTR_MASK(vfs - 64));
2859         rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1SX(1), INTR_MASK(vfs - 64));
2860 }
2861
2862 int rvu_get_num_lbk_chans(void)
2863 {
2864         struct pci_dev *pdev;
2865         void __iomem *base;
2866         int ret = -EIO;
2867
2868         pdev = pci_get_device(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_LBK,
2869                               NULL);
2870         if (!pdev)
2871                 goto err;
2872
2873         base = pci_ioremap_bar(pdev, 0);
2874         if (!base)
2875                 goto err_put;
2876
2877         /* Read number of available LBK channels from LBK(0)_CONST register. */
2878         ret = (readq(base + 0x10) >> 32) & 0xffff;
2879         iounmap(base);
2880 err_put:
2881         pci_dev_put(pdev);
2882 err:
2883         return ret;
2884 }
2885
2886 static int rvu_enable_sriov(struct rvu *rvu)
2887 {
2888         struct pci_dev *pdev = rvu->pdev;
2889         int err, chans, vfs;
2890
2891         if (!rvu_afvf_msix_vectors_num_ok(rvu)) {
2892                 dev_warn(&pdev->dev,
2893                          "Skipping SRIOV enablement since not enough IRQs are available\n");
2894                 return 0;
2895         }
2896
2897         chans = rvu_get_num_lbk_chans();
2898         if (chans < 0)
2899                 return chans;
2900
2901         vfs = pci_sriov_get_totalvfs(pdev);
2902
2903         /* Limit VFs in case we have more VFs than LBK channels available. */
2904         if (vfs > chans)
2905                 vfs = chans;
2906
2907         if (!vfs)
2908                 return 0;
2909
2910         /* LBK channel number 63 is used for switching packets between
2911          * CGX mapped VFs. Hence limit LBK pairs till 62 only.
2912          */
2913         if (vfs > 62)
2914                 vfs = 62;
2915
2916         /* Save VFs number for reference in VF interrupts handlers.
2917          * Since interrupts might start arriving during SRIOV enablement
2918          * ordinary API cannot be used to get number of enabled VFs.
2919          */
2920         rvu->vfs = vfs;
2921
2922         err = rvu_mbox_init(rvu, &rvu->afvf_wq_info, TYPE_AFVF, vfs,
2923                             rvu_afvf_mbox_handler, rvu_afvf_mbox_up_handler);
2924         if (err)
2925                 return err;
2926
2927         rvu_enable_afvf_intr(rvu);
2928         /* Make sure IRQs are enabled before SRIOV. */
2929         mb();
2930
2931         err = pci_enable_sriov(pdev, vfs);
2932         if (err) {
2933                 rvu_disable_afvf_intr(rvu);
2934                 rvu_mbox_destroy(&rvu->afvf_wq_info);
2935                 return err;
2936         }
2937
2938         return 0;
2939 }
2940
2941 static void rvu_disable_sriov(struct rvu *rvu)
2942 {
2943         rvu_disable_afvf_intr(rvu);
2944         rvu_mbox_destroy(&rvu->afvf_wq_info);
2945         pci_disable_sriov(rvu->pdev);
2946 }
2947
2948 static void rvu_update_module_params(struct rvu *rvu)
2949 {
2950         const char *default_pfl_name = "default";
2951
2952         strscpy(rvu->mkex_pfl_name,
2953                 mkex_profile ? mkex_profile : default_pfl_name, MKEX_NAME_LEN);
2954         strscpy(rvu->kpu_pfl_name,
2955                 kpu_profile ? kpu_profile : default_pfl_name, KPU_NAME_LEN);
2956 }
2957
2958 static int rvu_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2959 {
2960         struct device *dev = &pdev->dev;
2961         struct rvu *rvu;
2962         int    err;
2963
2964         rvu = devm_kzalloc(dev, sizeof(*rvu), GFP_KERNEL);
2965         if (!rvu)
2966                 return -ENOMEM;
2967
2968         rvu->hw = devm_kzalloc(dev, sizeof(struct rvu_hwinfo), GFP_KERNEL);
2969         if (!rvu->hw) {
2970                 devm_kfree(dev, rvu);
2971                 return -ENOMEM;
2972         }
2973
2974         pci_set_drvdata(pdev, rvu);
2975         rvu->pdev = pdev;
2976         rvu->dev = &pdev->dev;
2977
2978         err = pci_enable_device(pdev);
2979         if (err) {
2980                 dev_err(dev, "Failed to enable PCI device\n");
2981                 goto err_freemem;
2982         }
2983
2984         err = pci_request_regions(pdev, DRV_NAME);
2985         if (err) {
2986                 dev_err(dev, "PCI request regions failed 0x%x\n", err);
2987                 goto err_disable_device;
2988         }
2989
2990         err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48));
2991         if (err) {
2992                 dev_err(dev, "DMA mask config failed, abort\n");
2993                 goto err_release_regions;
2994         }
2995
2996         pci_set_master(pdev);
2997
2998         rvu->ptp = ptp_get();
2999         if (IS_ERR(rvu->ptp)) {
3000                 err = PTR_ERR(rvu->ptp);
3001                 if (err == -EPROBE_DEFER)
3002                         goto err_release_regions;
3003                 rvu->ptp = NULL;
3004         }
3005
3006         /* Map Admin function CSRs */
3007         rvu->afreg_base = pcim_iomap(pdev, PCI_AF_REG_BAR_NUM, 0);
3008         rvu->pfreg_base = pcim_iomap(pdev, PCI_PF_REG_BAR_NUM, 0);
3009         if (!rvu->afreg_base || !rvu->pfreg_base) {
3010                 dev_err(dev, "Unable to map admin function CSRs, aborting\n");
3011                 err = -ENOMEM;
3012                 goto err_put_ptp;
3013         }
3014
3015         /* Store module params in rvu structure */
3016         rvu_update_module_params(rvu);
3017
3018         /* Check which blocks the HW supports */
3019         rvu_check_block_implemented(rvu);
3020
3021         rvu_reset_all_blocks(rvu);
3022
3023         rvu_setup_hw_capabilities(rvu);
3024
3025         err = rvu_setup_hw_resources(rvu);
3026         if (err)
3027                 goto err_put_ptp;
3028
3029         /* Init mailbox btw AF and PFs */
3030         err = rvu_mbox_init(rvu, &rvu->afpf_wq_info, TYPE_AFPF,
3031                             rvu->hw->total_pfs, rvu_afpf_mbox_handler,
3032                             rvu_afpf_mbox_up_handler);
3033         if (err) {
3034                 dev_err(dev, "%s: Failed to initialize mbox\n", __func__);
3035                 goto err_hwsetup;
3036         }
3037
3038         err = rvu_flr_init(rvu);
3039         if (err) {
3040                 dev_err(dev, "%s: Failed to initialize flr\n", __func__);
3041                 goto err_mbox;
3042         }
3043
3044         err = rvu_register_interrupts(rvu);
3045         if (err) {
3046                 dev_err(dev, "%s: Failed to register interrupts\n", __func__);
3047                 goto err_flr;
3048         }
3049
3050         err = rvu_register_dl(rvu);
3051         if (err) {
3052                 dev_err(dev, "%s: Failed to register devlink\n", __func__);
3053                 goto err_irq;
3054         }
3055
3056         rvu_setup_rvum_blk_revid(rvu);
3057
3058         /* Enable AF's VFs (if any) */
3059         err = rvu_enable_sriov(rvu);
3060         if (err) {
3061                 dev_err(dev, "%s: Failed to enable sriov\n", __func__);
3062                 goto err_dl;
3063         }
3064
3065         /* Initialize debugfs */
3066         rvu_dbg_init(rvu);
3067
3068         mutex_init(&rvu->rswitch.switch_lock);
3069
3070         return 0;
3071 err_dl:
3072         rvu_unregister_dl(rvu);
3073 err_irq:
3074         rvu_unregister_interrupts(rvu);
3075 err_flr:
3076         rvu_flr_wq_destroy(rvu);
3077 err_mbox:
3078         rvu_mbox_destroy(&rvu->afpf_wq_info);
3079 err_hwsetup:
3080         rvu_cgx_exit(rvu);
3081         rvu_fwdata_exit(rvu);
3082         rvu_reset_all_blocks(rvu);
3083         rvu_free_hw_resources(rvu);
3084         rvu_clear_rvum_blk_revid(rvu);
3085 err_put_ptp:
3086         ptp_put(rvu->ptp);
3087 err_release_regions:
3088         pci_release_regions(pdev);
3089 err_disable_device:
3090         pci_disable_device(pdev);
3091 err_freemem:
3092         pci_set_drvdata(pdev, NULL);
3093         devm_kfree(&pdev->dev, rvu->hw);
3094         devm_kfree(dev, rvu);
3095         return err;
3096 }
3097
3098 static void rvu_remove(struct pci_dev *pdev)
3099 {
3100         struct rvu *rvu = pci_get_drvdata(pdev);
3101
3102         rvu_dbg_exit(rvu);
3103         rvu_unregister_dl(rvu);
3104         rvu_unregister_interrupts(rvu);
3105         rvu_flr_wq_destroy(rvu);
3106         rvu_cgx_exit(rvu);
3107         rvu_fwdata_exit(rvu);
3108         rvu_mbox_destroy(&rvu->afpf_wq_info);
3109         rvu_disable_sriov(rvu);
3110         rvu_reset_all_blocks(rvu);
3111         rvu_free_hw_resources(rvu);
3112         rvu_clear_rvum_blk_revid(rvu);
3113         ptp_put(rvu->ptp);
3114         pci_release_regions(pdev);
3115         pci_disable_device(pdev);
3116         pci_set_drvdata(pdev, NULL);
3117
3118         devm_kfree(&pdev->dev, rvu->hw);
3119         devm_kfree(&pdev->dev, rvu);
3120 }
3121
3122 static struct pci_driver rvu_driver = {
3123         .name = DRV_NAME,
3124         .id_table = rvu_id_table,
3125         .probe = rvu_probe,
3126         .remove = rvu_remove,
3127 };
3128
3129 static int __init rvu_init_module(void)
3130 {
3131         int err;
3132
3133         pr_info("%s: %s\n", DRV_NAME, DRV_STRING);
3134
3135         err = pci_register_driver(&cgx_driver);
3136         if (err < 0)
3137                 return err;
3138
3139         err = pci_register_driver(&ptp_driver);
3140         if (err < 0)
3141                 goto ptp_err;
3142
3143         err =  pci_register_driver(&rvu_driver);
3144         if (err < 0)
3145                 goto rvu_err;
3146
3147         return 0;
3148 rvu_err:
3149         pci_unregister_driver(&ptp_driver);
3150 ptp_err:
3151         pci_unregister_driver(&cgx_driver);
3152
3153         return err;
3154 }
3155
3156 static void __exit rvu_cleanup_module(void)
3157 {
3158         pci_unregister_driver(&rvu_driver);
3159         pci_unregister_driver(&ptp_driver);
3160         pci_unregister_driver(&cgx_driver);
3161 }
3162
3163 module_init(rvu_init_module);
3164 module_exit(rvu_cleanup_module);