1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Marvell OcteonTx2 RVU Admin Function driver
4 * Copyright (C) 2018 Marvell International Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
14 #include <linux/etherdevice.h>
15 #include <linux/sizes.h>
17 #include "rvu_struct.h"
20 #define MBOX_SIZE SZ_64K
22 /* AF/PF: PF initiated, PF/VF VF initiated */
23 #define MBOX_DOWN_RX_START 0
24 #define MBOX_DOWN_RX_SIZE (46 * SZ_1K)
25 #define MBOX_DOWN_TX_START (MBOX_DOWN_RX_START + MBOX_DOWN_RX_SIZE)
26 #define MBOX_DOWN_TX_SIZE (16 * SZ_1K)
27 /* AF/PF: AF initiated, PF/VF PF initiated */
28 #define MBOX_UP_RX_START (MBOX_DOWN_TX_START + MBOX_DOWN_TX_SIZE)
29 #define MBOX_UP_RX_SIZE SZ_1K
30 #define MBOX_UP_TX_START (MBOX_UP_RX_START + MBOX_UP_RX_SIZE)
31 #define MBOX_UP_TX_SIZE SZ_1K
33 #if MBOX_UP_TX_SIZE + MBOX_UP_TX_START != MBOX_SIZE
34 # error "incorrect mailbox area sizes"
37 #define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull))
39 #define MBOX_RSP_TIMEOUT 2000 /* Time(ms) to wait for mbox response */
41 #define MBOX_MSG_ALIGN 16 /* Align mbox msg start to 16bytes */
43 /* Mailbox directions */
44 #define MBOX_DIR_AFPF 0 /* AF replies to PF */
45 #define MBOX_DIR_PFAF 1 /* PF sends messages to AF */
46 #define MBOX_DIR_PFVF 2 /* PF replies to VF */
47 #define MBOX_DIR_VFPF 3 /* VF sends messages to PF */
48 #define MBOX_DIR_AFPF_UP 4 /* AF sends messages to PF */
49 #define MBOX_DIR_PFAF_UP 5 /* PF replies to AF */
50 #define MBOX_DIR_PFVF_UP 6 /* PF sends messages to VF */
51 #define MBOX_DIR_VFPF_UP 7 /* VF replies to PF */
53 struct otx2_mbox_dev {
54 void *mbase; /* This dev's mbox region */
56 u16 msg_size; /* Total msg size to be sent */
57 u16 rsp_size; /* Total rsp size to be sure the reply is ok */
58 u16 num_msgs; /* No of msgs sent or waiting for response */
59 u16 msgs_acked; /* No of msgs for which response is received */
64 void *hwbase; /* Mbox region advertised by HW */
65 void *reg_base;/* CSR base for this dev */
66 u64 trigger; /* Trigger mbox notification */
67 u16 tr_shift; /* Mbox trigger shift */
68 u64 rx_start; /* Offset of Rx region in mbox memory */
69 u64 tx_start; /* Offset of Tx region in mbox memory */
70 u16 rx_size; /* Size of Rx region */
71 u16 tx_size; /* Size of Tx region */
72 u16 ndevs; /* The number of peers */
73 struct otx2_mbox_dev *dev;
76 /* Header which preceeds all mbox messages */
78 u64 msg_size; /* Total msgs size embedded */
79 u16 num_msgs; /* No of msgs embedded */
82 /* Header which preceeds every msg and is also part of it */
84 u16 pcifunc; /* Who's sending this msg */
85 u16 id; /* Mbox message ID */
86 #define OTX2_MBOX_REQ_SIG (0xdead)
87 #define OTX2_MBOX_RSP_SIG (0xbeef)
88 u16 sig; /* Signature, for validating corrupted msgs */
89 #define OTX2_MBOX_VERSION (0x0007)
90 u16 ver; /* Version of msg's structure for this ID */
91 u16 next_msgoff; /* Offset of next msg within mailbox region */
92 int rc; /* Msg process'ed response code */
95 void otx2_mbox_reset(struct otx2_mbox *mbox, int devid);
96 void __otx2_mbox_reset(struct otx2_mbox *mbox, int devid);
97 void otx2_mbox_destroy(struct otx2_mbox *mbox);
98 int otx2_mbox_init(struct otx2_mbox *mbox, void __force *hwbase,
99 struct pci_dev *pdev, void __force *reg_base,
100 int direction, int ndevs);
101 void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid);
102 int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid);
103 int otx2_mbox_busy_poll_for_rsp(struct otx2_mbox *mbox, int devid);
104 struct mbox_msghdr *otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid,
105 int size, int size_rsp);
106 struct mbox_msghdr *otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid,
107 struct mbox_msghdr *msg);
108 int otx2_mbox_check_rsp_msgs(struct otx2_mbox *mbox, int devid);
109 int otx2_reply_invalid_msg(struct otx2_mbox *mbox, int devid,
110 u16 pcifunc, u16 id);
111 bool otx2_mbox_nonempty(struct otx2_mbox *mbox, int devid);
112 const char *otx2_mbox_id2name(u16 id);
113 static inline struct mbox_msghdr *otx2_mbox_alloc_msg(struct otx2_mbox *mbox,
116 return otx2_mbox_alloc_msg_rsp(mbox, devid, size, 0);
119 /* Mailbox message types */
120 #define MBOX_MSG_MASK 0xFFFF
121 #define MBOX_MSG_INVALID 0xFFFE
122 #define MBOX_MSG_MAX 0xFFFF
124 #define MBOX_MESSAGES \
125 /* Generic mbox IDs (range 0x000 - 0x1FF) */ \
126 M(READY, 0x001, ready, msg_req, ready_msg_rsp) \
127 M(ATTACH_RESOURCES, 0x002, attach_resources, rsrc_attach, msg_rsp) \
128 M(DETACH_RESOURCES, 0x003, detach_resources, rsrc_detach, msg_rsp) \
129 M(MSIX_OFFSET, 0x005, msix_offset, msg_req, msix_offset_rsp) \
130 M(VF_FLR, 0x006, vf_flr, msg_req, msg_rsp) \
131 M(PTP_OP, 0x007, ptp_op, ptp_req, ptp_rsp) \
132 M(GET_HW_CAP, 0x008, get_hw_cap, msg_req, get_hw_cap_rsp) \
133 /* CGX mbox IDs (range 0x200 - 0x3FF) */ \
134 M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \
135 M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \
136 M(CGX_STATS, 0x202, cgx_stats, msg_req, cgx_stats_rsp) \
137 M(CGX_MAC_ADDR_SET, 0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get, \
138 cgx_mac_addr_set_or_get) \
139 M(CGX_MAC_ADDR_GET, 0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get, \
140 cgx_mac_addr_set_or_get) \
141 M(CGX_PROMISC_ENABLE, 0x205, cgx_promisc_enable, msg_req, msg_rsp) \
142 M(CGX_PROMISC_DISABLE, 0x206, cgx_promisc_disable, msg_req, msg_rsp) \
143 M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp) \
144 M(CGX_STOP_LINKEVENTS, 0x208, cgx_stop_linkevents, msg_req, msg_rsp) \
145 M(CGX_GET_LINKINFO, 0x209, cgx_get_linkinfo, msg_req, cgx_link_info_msg) \
146 M(CGX_INTLBK_ENABLE, 0x20A, cgx_intlbk_enable, msg_req, msg_rsp) \
147 M(CGX_INTLBK_DISABLE, 0x20B, cgx_intlbk_disable, msg_req, msg_rsp) \
148 M(CGX_PTP_RX_ENABLE, 0x20C, cgx_ptp_rx_enable, msg_req, msg_rsp) \
149 M(CGX_PTP_RX_DISABLE, 0x20D, cgx_ptp_rx_disable, msg_req, msg_rsp) \
150 M(CGX_CFG_PAUSE_FRM, 0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg, \
152 /* NPA mbox IDs (range 0x400 - 0x5FF) */ \
153 M(NPA_LF_ALLOC, 0x400, npa_lf_alloc, \
154 npa_lf_alloc_req, npa_lf_alloc_rsp) \
155 M(NPA_LF_FREE, 0x401, npa_lf_free, msg_req, msg_rsp) \
156 M(NPA_AQ_ENQ, 0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp) \
157 M(NPA_HWCTX_DISABLE, 0x403, npa_hwctx_disable, hwctx_disable_req, msg_rsp)\
158 /* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */ \
159 /* TIM mbox IDs (range 0x800 - 0x9FF) */ \
160 /* CPT mbox IDs (range 0xA00 - 0xBFF) */ \
161 /* NPC mbox IDs (range 0x6000 - 0x7FFF) */ \
162 M(NPC_MCAM_ALLOC_ENTRY, 0x6000, npc_mcam_alloc_entry, npc_mcam_alloc_entry_req,\
163 npc_mcam_alloc_entry_rsp) \
164 M(NPC_MCAM_FREE_ENTRY, 0x6001, npc_mcam_free_entry, \
165 npc_mcam_free_entry_req, msg_rsp) \
166 M(NPC_MCAM_WRITE_ENTRY, 0x6002, npc_mcam_write_entry, \
167 npc_mcam_write_entry_req, msg_rsp) \
168 M(NPC_MCAM_ENA_ENTRY, 0x6003, npc_mcam_ena_entry, \
169 npc_mcam_ena_dis_entry_req, msg_rsp) \
170 M(NPC_MCAM_DIS_ENTRY, 0x6004, npc_mcam_dis_entry, \
171 npc_mcam_ena_dis_entry_req, msg_rsp) \
172 M(NPC_MCAM_SHIFT_ENTRY, 0x6005, npc_mcam_shift_entry, npc_mcam_shift_entry_req,\
173 npc_mcam_shift_entry_rsp) \
174 M(NPC_MCAM_ALLOC_COUNTER, 0x6006, npc_mcam_alloc_counter, \
175 npc_mcam_alloc_counter_req, \
176 npc_mcam_alloc_counter_rsp) \
177 M(NPC_MCAM_FREE_COUNTER, 0x6007, npc_mcam_free_counter, \
178 npc_mcam_oper_counter_req, msg_rsp) \
179 M(NPC_MCAM_UNMAP_COUNTER, 0x6008, npc_mcam_unmap_counter, \
180 npc_mcam_unmap_counter_req, msg_rsp) \
181 M(NPC_MCAM_CLEAR_COUNTER, 0x6009, npc_mcam_clear_counter, \
182 npc_mcam_oper_counter_req, msg_rsp) \
183 M(NPC_MCAM_COUNTER_STATS, 0x600a, npc_mcam_counter_stats, \
184 npc_mcam_oper_counter_req, \
185 npc_mcam_oper_counter_rsp) \
186 M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, npc_mcam_alloc_and_write_entry, \
187 npc_mcam_alloc_and_write_entry_req, \
188 npc_mcam_alloc_and_write_entry_rsp) \
189 M(NPC_GET_KEX_CFG, 0x600c, npc_get_kex_cfg, \
190 msg_req, npc_get_kex_cfg_rsp) \
191 M(NPC_INSTALL_FLOW, 0x600d, npc_install_flow, \
192 npc_install_flow_req, npc_install_flow_rsp) \
193 M(NPC_DELETE_FLOW, 0x600e, npc_delete_flow, \
194 npc_delete_flow_req, msg_rsp) \
195 M(NPC_MCAM_READ_ENTRY, 0x600f, npc_mcam_read_entry, \
196 npc_mcam_read_entry_req, \
197 npc_mcam_read_entry_rsp) \
198 M(NPC_MCAM_READ_BASE_RULE, 0x6011, npc_read_base_steer_rule, \
199 msg_req, npc_mcam_read_base_rule_rsp) \
200 /* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \
201 M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, \
202 nix_lf_alloc_req, nix_lf_alloc_rsp) \
203 M(NIX_LF_FREE, 0x8001, nix_lf_free, nix_lf_free_req, msg_rsp) \
204 M(NIX_AQ_ENQ, 0x8002, nix_aq_enq, nix_aq_enq_req, nix_aq_enq_rsp) \
205 M(NIX_HWCTX_DISABLE, 0x8003, nix_hwctx_disable, \
206 hwctx_disable_req, msg_rsp) \
207 M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc, \
208 nix_txsch_alloc_req, nix_txsch_alloc_rsp) \
209 M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free, nix_txsch_free_req, msg_rsp) \
210 M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_cfg, nix_txschq_config, msg_rsp) \
211 M(NIX_STATS_RST, 0x8007, nix_stats_rst, msg_req, msg_rsp) \
212 M(NIX_VTAG_CFG, 0x8008, nix_vtag_cfg, nix_vtag_config, \
213 nix_vtag_config_rsp) \
214 M(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, \
215 nix_rss_flowkey_cfg, \
216 nix_rss_flowkey_cfg_rsp) \
217 M(NIX_SET_MAC_ADDR, 0x800a, nix_set_mac_addr, nix_set_mac_addr, msg_rsp) \
218 M(NIX_SET_RX_MODE, 0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp) \
219 M(NIX_SET_HW_FRS, 0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp) \
220 M(NIX_LF_START_RX, 0x800d, nix_lf_start_rx, msg_req, msg_rsp) \
221 M(NIX_LF_STOP_RX, 0x800e, nix_lf_stop_rx, msg_req, msg_rsp) \
222 M(NIX_MARK_FORMAT_CFG, 0x800f, nix_mark_format_cfg, \
223 nix_mark_format_cfg, \
224 nix_mark_format_cfg_rsp) \
225 M(NIX_SET_RX_CFG, 0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp) \
226 M(NIX_LSO_FORMAT_CFG, 0x8011, nix_lso_format_cfg, \
227 nix_lso_format_cfg, \
228 nix_lso_format_cfg_rsp) \
229 M(NIX_LF_PTP_TX_ENABLE, 0x8013, nix_lf_ptp_tx_enable, msg_req, msg_rsp) \
230 M(NIX_LF_PTP_TX_DISABLE, 0x8014, nix_lf_ptp_tx_disable, msg_req, msg_rsp) \
231 M(NIX_BP_ENABLE, 0x8016, nix_bp_enable, nix_bp_cfg_req, \
233 M(NIX_BP_DISABLE, 0x8017, nix_bp_disable, nix_bp_cfg_req, msg_rsp) \
234 M(NIX_GET_MAC_ADDR, 0x8018, nix_get_mac_addr, msg_req, nix_get_mac_addr_rsp) \
236 /* Messages initiated by AF (range 0xC00 - 0xDFF) */
237 #define MBOX_UP_CGX_MESSAGES \
238 M(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, msg_rsp)
241 #define M(_name, _id, _1, _2, _3) MBOX_MSG_ ## _name = _id,
247 /* Mailbox message formats */
249 #define RVU_DEFAULT_PF_FUNC 0xFFFF
251 /* Generic request msg used for those mbox messages which
252 * don't send any data in the request.
255 struct mbox_msghdr hdr;
258 /* Generic rsponse msg used a ack or response for those mbox
259 * messages which doesn't have a specific rsp msg format.
262 struct mbox_msghdr hdr;
265 /* RVU mailbox error codes
269 RVU_INVALID_VF_ID = -256,
272 struct ready_msg_rsp {
273 struct mbox_msghdr hdr;
274 u16 sclk_freq; /* SCLK frequency (in MHz) */
275 u16 rclk_freq; /* RCLK frequency (in MHz) */
278 /* Structure for requesting resource provisioning.
279 * 'modify' flag to be used when either requesting more
280 * or to detach partial of a cetain resource type.
281 * Rest of the fields specify how many of what type to
283 * To request LFs from two blocks of same type this mailbox
284 * can be sent twice as below:
285 * struct rsrc_attach *attach;
286 * .. Allocate memory for message ..
287 * attach->cptlfs = 3; <3 LFs from CPT0>
289 * .. Allocate memory for message ..
290 * attach->modify = 1;
291 * attach->cpt_blkaddr = BLKADDR_CPT1;
292 * attach->cptlfs = 2; <2 LFs from CPT1>
296 struct mbox_msghdr hdr;
304 int cpt_blkaddr; /* BLKADDR_CPT0/BLKADDR_CPT1 or 0 for BLKADDR_CPT0 */
307 /* Structure for relinquishing resources.
308 * 'partial' flag to be used when relinquishing all resources
309 * but only of a certain type. If not set, all resources of all
310 * types provisioned to the RVU function will be detached.
313 struct mbox_msghdr hdr;
323 #define MSIX_VECTOR_INVALID 0xFFFF
324 #define MAX_RVU_BLKLF_CNT 256
326 struct msix_offset_rsp {
327 struct mbox_msghdr hdr;
334 u16 sso_msixoff[MAX_RVU_BLKLF_CNT];
335 u16 ssow_msixoff[MAX_RVU_BLKLF_CNT];
336 u16 timlf_msixoff[MAX_RVU_BLKLF_CNT];
337 u16 cptlf_msixoff[MAX_RVU_BLKLF_CNT];
339 u16 cpt1_lf_msixoff[MAX_RVU_BLKLF_CNT];
342 struct get_hw_cap_rsp {
343 struct mbox_msghdr hdr;
344 u8 nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */
345 u8 nix_shaping; /* Is shaping and coloring supported */
348 /* CGX mbox message formats */
350 struct cgx_stats_rsp {
351 struct mbox_msghdr hdr;
352 #define CGX_RX_STATS_COUNT 13
353 #define CGX_TX_STATS_COUNT 18
354 u64 rx_stats[CGX_RX_STATS_COUNT];
355 u64 tx_stats[CGX_TX_STATS_COUNT];
358 /* Structure for requesting the operation for
359 * setting/getting mac address in the CGX interface
361 struct cgx_mac_addr_set_or_get {
362 struct mbox_msghdr hdr;
363 u8 mac_addr[ETH_ALEN];
366 struct cgx_link_user_info {
368 uint64_t full_duplex:1;
369 uint64_t lmac_type_id:4;
370 uint64_t speed:20; /* speed in Mbps */
371 #define LMACTYPE_STR_LEN 16
372 char lmac_type[LMACTYPE_STR_LEN];
375 struct cgx_link_info_msg {
376 struct mbox_msghdr hdr;
377 struct cgx_link_user_info link_info;
380 struct cgx_pause_frm_cfg {
381 struct mbox_msghdr hdr;
383 /* set = 1 if the request is to config pause frames */
384 /* set = 0 if the request is to fetch pause frames config */
389 /* NPA mbox message formats */
391 /* NPA mailbox error codes
395 NPA_AF_ERR_PARAM = -301,
396 NPA_AF_ERR_AQ_FULL = -302,
397 NPA_AF_ERR_AQ_ENQUEUE = -303,
398 NPA_AF_ERR_AF_LF_INVALID = -304,
399 NPA_AF_ERR_AF_LF_ALLOC = -305,
400 NPA_AF_ERR_LF_RESET = -306,
403 /* For NPA LF context alloc and init */
404 struct npa_lf_alloc_req {
405 struct mbox_msghdr hdr;
407 int aura_sz; /* No of auras */
408 u32 nr_pools; /* No of pools */
412 struct npa_lf_alloc_rsp {
413 struct mbox_msghdr hdr;
414 u32 stack_pg_ptrs; /* No of ptrs per stack page */
415 u32 stack_pg_bytes; /* Size of stack page */
416 u16 qints; /* NPA_AF_CONST::QINTS */
419 /* NPA AQ enqueue msg */
420 struct npa_aq_enq_req {
421 struct mbox_msghdr hdr;
426 /* Valid when op == WRITE/INIT and ctype == AURA.
427 * LF fills the pool_id in aura.pool_addr. AF will translate
428 * the pool_id to pool context pointer.
430 struct npa_aura_s aura;
431 /* Valid when op == WRITE/INIT and ctype == POOL */
432 struct npa_pool_s pool;
434 /* Mask data when op == WRITE (1=write, 0=don't write) */
436 /* Valid when op == WRITE and ctype == AURA */
437 struct npa_aura_s aura_mask;
438 /* Valid when op == WRITE and ctype == POOL */
439 struct npa_pool_s pool_mask;
443 struct npa_aq_enq_rsp {
444 struct mbox_msghdr hdr;
446 /* Valid when op == READ and ctype == AURA */
447 struct npa_aura_s aura;
448 /* Valid when op == READ and ctype == POOL */
449 struct npa_pool_s pool;
453 /* Disable all contexts of type 'ctype' */
454 struct hwctx_disable_req {
455 struct mbox_msghdr hdr;
459 /* NIX mbox message formats */
461 /* NIX mailbox error codes
465 NIX_AF_ERR_PARAM = -401,
466 NIX_AF_ERR_AQ_FULL = -402,
467 NIX_AF_ERR_AQ_ENQUEUE = -403,
468 NIX_AF_ERR_AF_LF_INVALID = -404,
469 NIX_AF_ERR_AF_LF_ALLOC = -405,
470 NIX_AF_ERR_TLX_ALLOC_FAIL = -406,
471 NIX_AF_ERR_TLX_INVALID = -407,
472 NIX_AF_ERR_RSS_SIZE_INVALID = -408,
473 NIX_AF_ERR_RSS_GRPS_INVALID = -409,
474 NIX_AF_ERR_FRS_INVALID = -410,
475 NIX_AF_ERR_RX_LINK_INVALID = -411,
476 NIX_AF_INVAL_TXSCHQ_CFG = -412,
477 NIX_AF_SMQ_FLUSH_FAILED = -413,
478 NIX_AF_ERR_LF_RESET = -414,
479 NIX_AF_ERR_RSS_NOSPC_FIELD = -415,
480 NIX_AF_ERR_RSS_NOSPC_ALGO = -416,
481 NIX_AF_ERR_MARK_CFG_FAIL = -417,
482 NIX_AF_ERR_LSO_CFG_FAIL = -418,
483 NIX_AF_INVAL_NPA_PF_FUNC = -419,
484 NIX_AF_INVAL_SSO_PF_FUNC = -420,
485 NIX_AF_ERR_TX_VTAG_NOSPC = -421,
486 NIX_AF_ERR_RX_VTAG_INUSE = -422,
489 /* For NIX RX vtag action */
490 enum nix_rx_vtag0_type {
491 NIX_AF_LFX_RX_VTAG_TYPE0, /* reserved for rx vlan offload */
492 NIX_AF_LFX_RX_VTAG_TYPE1,
493 NIX_AF_LFX_RX_VTAG_TYPE2,
494 NIX_AF_LFX_RX_VTAG_TYPE3,
495 NIX_AF_LFX_RX_VTAG_TYPE4,
496 NIX_AF_LFX_RX_VTAG_TYPE5,
497 NIX_AF_LFX_RX_VTAG_TYPE6,
498 NIX_AF_LFX_RX_VTAG_TYPE7,
501 /* For NIX LF context alloc and init */
502 struct nix_lf_alloc_req {
503 struct mbox_msghdr hdr;
505 u32 rq_cnt; /* No of receive queues */
506 u32 sq_cnt; /* No of send queues */
507 u32 cq_cnt; /* No of completion queues */
513 u64 rx_cfg; /* See NIX_AF_LF(0..127)_RX_CFG */
517 struct nix_lf_alloc_rsp {
518 struct mbox_msghdr hdr;
522 u8 rx_chan_cnt; /* total number of RX channels */
523 u8 tx_chan_cnt; /* total number of TX channels */
526 u8 mac_addr[ETH_ALEN];
527 u8 lf_rx_stats; /* NIX_AF_CONST1::LF_RX_STATS */
528 u8 lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */
529 u16 cints; /* NIX_AF_CONST2::CINTS */
530 u16 qints; /* NIX_AF_CONST2::QINTS */
531 u8 cgx_links; /* No. of CGX links present in HW */
532 u8 lbk_links; /* No. of LBK links present in HW */
533 u8 sdp_links; /* No. of SDP links present in HW */
536 struct nix_lf_free_req {
537 struct mbox_msghdr hdr;
538 #define NIX_LF_DISABLE_FLOWS BIT_ULL(0)
539 #define NIX_LF_DONT_FREE_TX_VTAG BIT_ULL(1)
543 /* NIX AQ enqueue msg */
544 struct nix_aq_enq_req {
545 struct mbox_msghdr hdr;
550 struct nix_rq_ctx_s rq;
551 struct nix_sq_ctx_s sq;
552 struct nix_cq_ctx_s cq;
553 struct nix_rsse_s rss;
554 struct nix_rx_mce_s mce;
557 struct nix_rq_ctx_s rq_mask;
558 struct nix_sq_ctx_s sq_mask;
559 struct nix_cq_ctx_s cq_mask;
560 struct nix_rsse_s rss_mask;
561 struct nix_rx_mce_s mce_mask;
565 struct nix_aq_enq_rsp {
566 struct mbox_msghdr hdr;
568 struct nix_rq_ctx_s rq;
569 struct nix_sq_ctx_s sq;
570 struct nix_cq_ctx_s cq;
571 struct nix_rsse_s rss;
572 struct nix_rx_mce_s mce;
576 /* Tx scheduler/shaper mailbox messages */
578 #define MAX_TXSCHQ_PER_FUNC 128
580 struct nix_txsch_alloc_req {
581 struct mbox_msghdr hdr;
582 /* Scheduler queue count request at each level */
583 u16 schq_contig[NIX_TXSCH_LVL_CNT]; /* No of contiguous queues */
584 u16 schq[NIX_TXSCH_LVL_CNT]; /* No of non-contiguous queues */
587 struct nix_txsch_alloc_rsp {
588 struct mbox_msghdr hdr;
589 /* Scheduler queue count allocated at each level */
590 u16 schq_contig[NIX_TXSCH_LVL_CNT];
591 u16 schq[NIX_TXSCH_LVL_CNT];
592 /* Scheduler queue list allocated at each level */
593 u16 schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
594 u16 schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
595 u8 aggr_level; /* Traffic aggregation scheduler level */
596 u8 aggr_lvl_rr_prio; /* Aggregation lvl's RR_PRIO config */
597 u8 link_cfg_lvl; /* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */
600 struct nix_txsch_free_req {
601 struct mbox_msghdr hdr;
602 #define TXSCHQ_FREE_ALL BIT_ULL(0)
604 /* Scheduler queue level to be freed */
606 /* List of scheduler queues to be freed */
610 struct nix_txschq_config {
611 struct mbox_msghdr hdr;
612 u8 lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */
613 #define TXSCHQ_IDX_SHIFT 16
614 #define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1)
615 #define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK)
617 #define MAX_REGS_PER_MBOX_MSG 20
618 u64 reg[MAX_REGS_PER_MBOX_MSG];
619 u64 regval[MAX_REGS_PER_MBOX_MSG];
622 struct nix_vtag_config {
623 struct mbox_msghdr hdr;
624 /* '0' for 4 octet VTAG, '1' for 8 octet VTAG */
626 /* cfg_type is '0' for tx vlan cfg
627 * cfg_type is '1' for rx vlan cfg
631 /* valid when cfg_type is '0' */
636 /* cfg_vtag0 & cfg_vtag1 fields are valid
637 * when free_vtag0 & free_vtag1 are '0's.
639 /* cfg_vtag0 = 1 to configure vtag0 */
641 /* cfg_vtag1 = 1 to configure vtag1 */
644 /* vtag0_idx & vtag1_idx are only valid when
645 * both cfg_vtag0 & cfg_vtag1 are '0's,
646 * these fields are used along with free_vtag0
647 * & free_vtag1 to free the nix lf's tx_vlan
650 * Denotes the indices of tx_vtag def registers
651 * that needs to be cleared and freed.
656 /* free_vtag0 & free_vtag1 fields are valid
657 * when cfg_vtag0 & cfg_vtag1 are '0's.
659 /* free_vtag0 = 1 clears vtag0 configuration
660 * vtag0_idx denotes the index to be cleared.
663 /* free_vtag1 = 1 clears vtag1 configuration
664 * vtag1_idx denotes the index to be cleared.
669 /* valid when cfg_type is '1' */
671 /* rx vtag type index, valid values are in 0..7 range */
675 /* rx vtag capture */
681 struct nix_vtag_config_rsp {
682 struct mbox_msghdr hdr;
685 /* Indices of tx_vtag def registers used to configure
686 * tx vtag0 & vtag1 headers, these indices are valid
687 * when nix_vtag_config mbox requested for vtag0 and/
688 * or vtag1 configuration.
692 struct nix_rss_flowkey_cfg {
693 struct mbox_msghdr hdr;
694 int mcam_index; /* MCAM entry index to modify */
695 #define NIX_FLOW_KEY_TYPE_PORT BIT(0)
696 #define NIX_FLOW_KEY_TYPE_IPV4 BIT(1)
697 #define NIX_FLOW_KEY_TYPE_IPV6 BIT(2)
698 #define NIX_FLOW_KEY_TYPE_TCP BIT(3)
699 #define NIX_FLOW_KEY_TYPE_UDP BIT(4)
700 #define NIX_FLOW_KEY_TYPE_SCTP BIT(5)
701 #define NIX_FLOW_KEY_TYPE_NVGRE BIT(6)
702 #define NIX_FLOW_KEY_TYPE_VXLAN BIT(7)
703 #define NIX_FLOW_KEY_TYPE_GENEVE BIT(8)
704 #define NIX_FLOW_KEY_TYPE_ETH_DMAC BIT(9)
705 #define NIX_FLOW_KEY_TYPE_IPV6_EXT BIT(10)
706 #define NIX_FLOW_KEY_TYPE_GTPU BIT(11)
707 #define NIX_FLOW_KEY_TYPE_INNR_IPV4 BIT(12)
708 #define NIX_FLOW_KEY_TYPE_INNR_IPV6 BIT(13)
709 #define NIX_FLOW_KEY_TYPE_INNR_TCP BIT(14)
710 #define NIX_FLOW_KEY_TYPE_INNR_UDP BIT(15)
711 #define NIX_FLOW_KEY_TYPE_INNR_SCTP BIT(16)
712 #define NIX_FLOW_KEY_TYPE_INNR_ETH_DMAC BIT(17)
713 #define NIX_FLOW_KEY_TYPE_VLAN BIT(20)
714 u32 flowkey_cfg; /* Flowkey types selected */
715 u8 group; /* RSS context or group */
718 struct nix_rss_flowkey_cfg_rsp {
719 struct mbox_msghdr hdr;
720 u8 alg_idx; /* Selected algo index */
723 struct nix_set_mac_addr {
724 struct mbox_msghdr hdr;
725 u8 mac_addr[ETH_ALEN]; /* MAC address to be set for this pcifunc */
728 struct nix_get_mac_addr_rsp {
729 struct mbox_msghdr hdr;
730 u8 mac_addr[ETH_ALEN];
733 struct nix_mark_format_cfg {
734 struct mbox_msghdr hdr;
742 struct nix_mark_format_cfg_rsp {
743 struct mbox_msghdr hdr;
748 struct mbox_msghdr hdr;
749 #define NIX_RX_MODE_UCAST BIT(0)
750 #define NIX_RX_MODE_PROMISC BIT(1)
751 #define NIX_RX_MODE_ALLMULTI BIT(2)
756 struct mbox_msghdr hdr;
757 #define NIX_RX_OL3_VERIFY BIT(0)
758 #define NIX_RX_OL4_VERIFY BIT(1)
759 u8 len_verify; /* Outer L3/L4 len check */
760 #define NIX_RX_CSUM_OL4_VERIFY BIT(0)
761 u8 csum_verify; /* Outer L4 checksum verification */
765 struct mbox_msghdr hdr;
766 u8 update_smq; /* Update SMQ's min/max lens */
767 u8 update_minlen; /* Set minlen also */
768 u8 sdp_link; /* Set SDP RX link */
773 struct nix_lso_format_cfg {
774 struct mbox_msghdr hdr;
776 #define NIX_LSO_FIELD_MAX 8
777 u64 fields[NIX_LSO_FIELD_MAX];
780 struct nix_lso_format_cfg_rsp {
781 struct mbox_msghdr hdr;
785 struct nix_bp_cfg_req {
786 struct mbox_msghdr hdr;
787 u16 chan_base; /* Starting channel number */
788 u8 chan_cnt; /* Number of channels */
790 /* bpid_per_chan = 0 assigns single bp id for range of channels */
791 /* bpid_per_chan = 1 assigns separate bp id for each channel */
794 /* PF can be mapped to either CGX or LBK interface,
795 * so maximum 64 channels are possible.
797 #define NIX_MAX_BPID_CHAN 64
798 struct nix_bp_cfg_rsp {
799 struct mbox_msghdr hdr;
800 u16 chan_bpid[NIX_MAX_BPID_CHAN]; /* Channel and bpid mapping */
801 u8 chan_cnt; /* Number of channel for which bpids are assigned */
804 /* NPC mbox message structs */
806 #define NPC_MCAM_ENTRY_INVALID 0xFFFF
807 #define NPC_MCAM_INVALID_MAP 0xFFFF
809 /* NPC mailbox error codes
813 NPC_MCAM_INVALID_REQ = -701,
814 NPC_MCAM_ALLOC_DENIED = -702,
815 NPC_MCAM_ALLOC_FAILED = -703,
816 NPC_MCAM_PERM_DENIED = -704,
819 struct npc_mcam_alloc_entry_req {
820 struct mbox_msghdr hdr;
821 #define NPC_MAX_NONCONTIG_ENTRIES 256
822 u8 contig; /* Contiguous entries ? */
823 #define NPC_MCAM_ANY_PRIO 0
824 #define NPC_MCAM_LOWER_PRIO 1
825 #define NPC_MCAM_HIGHER_PRIO 2
826 u8 priority; /* Lower or higher w.r.t ref_entry */
828 u16 count; /* Number of entries requested */
831 struct npc_mcam_alloc_entry_rsp {
832 struct mbox_msghdr hdr;
833 u16 entry; /* Entry allocated or start index if contiguous.
834 * Invalid incase of non-contiguous.
836 u16 count; /* Number of entries allocated */
837 u16 free_count; /* Number of entries available */
838 u16 entry_list[NPC_MAX_NONCONTIG_ENTRIES];
841 struct npc_mcam_free_entry_req {
842 struct mbox_msghdr hdr;
843 u16 entry; /* Entry index to be freed */
844 u8 all; /* If all entries allocated to this PFVF to be freed */
848 #define NPC_MAX_KWS_IN_KEY 7 /* Number of keywords in max keywidth */
849 u64 kw[NPC_MAX_KWS_IN_KEY];
850 u64 kw_mask[NPC_MAX_KWS_IN_KEY];
855 struct npc_mcam_write_entry_req {
856 struct mbox_msghdr hdr;
857 struct mcam_entry entry_data;
858 u16 entry; /* MCAM entry to write this match key */
859 u16 cntr; /* Counter for this MCAM entry */
860 u8 intf; /* Rx or Tx interface */
861 u8 enable_entry;/* Enable this MCAM entry ? */
862 u8 set_cntr; /* Set counter for this entry ? */
865 /* Enable/Disable a given entry */
866 struct npc_mcam_ena_dis_entry_req {
867 struct mbox_msghdr hdr;
871 struct npc_mcam_shift_entry_req {
872 struct mbox_msghdr hdr;
873 #define NPC_MCAM_MAX_SHIFTS 64
874 u16 curr_entry[NPC_MCAM_MAX_SHIFTS];
875 u16 new_entry[NPC_MCAM_MAX_SHIFTS];
876 u16 shift_count; /* Number of entries to shift */
879 struct npc_mcam_shift_entry_rsp {
880 struct mbox_msghdr hdr;
881 u16 failed_entry_idx; /* Index in 'curr_entry', not entry itself */
884 struct npc_mcam_alloc_counter_req {
885 struct mbox_msghdr hdr;
886 u8 contig; /* Contiguous counters ? */
887 #define NPC_MAX_NONCONTIG_COUNTERS 64
888 u16 count; /* Number of counters requested */
891 struct npc_mcam_alloc_counter_rsp {
892 struct mbox_msghdr hdr;
893 u16 cntr; /* Counter allocated or start index if contiguous.
894 * Invalid incase of non-contiguous.
896 u16 count; /* Number of counters allocated */
897 u16 cntr_list[NPC_MAX_NONCONTIG_COUNTERS];
900 struct npc_mcam_oper_counter_req {
901 struct mbox_msghdr hdr;
902 u16 cntr; /* Free a counter or clear/fetch it's stats */
905 struct npc_mcam_oper_counter_rsp {
906 struct mbox_msghdr hdr;
907 u64 stat; /* valid only while fetching counter's stats */
910 struct npc_mcam_unmap_counter_req {
911 struct mbox_msghdr hdr;
913 u16 entry; /* Entry and counter to be unmapped */
914 u8 all; /* Unmap all entries using this counter ? */
917 struct npc_mcam_alloc_and_write_entry_req {
918 struct mbox_msghdr hdr;
919 struct mcam_entry entry_data;
921 u8 priority; /* Lower or higher w.r.t ref_entry */
922 u8 intf; /* Rx or Tx interface */
923 u8 enable_entry;/* Enable this MCAM entry ? */
924 u8 alloc_cntr; /* Allocate counter and map ? */
927 struct npc_mcam_alloc_and_write_entry_rsp {
928 struct mbox_msghdr hdr;
933 struct npc_get_kex_cfg_rsp {
934 struct mbox_msghdr hdr;
935 u64 rx_keyx_cfg; /* NPC_AF_INTF(0)_KEX_CFG */
936 u64 tx_keyx_cfg; /* NPC_AF_INTF(1)_KEX_CFG */
937 #define NPC_MAX_INTF 2
938 #define NPC_MAX_LID 8
939 #define NPC_MAX_LT 16
941 #define NPC_MAX_LFL 16
942 /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */
943 u64 kex_ld_flags[NPC_MAX_LD];
944 /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */
945 u64 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD];
946 /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */
947 u64 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL];
948 #define MKEX_NAME_LEN 128
949 u8 mkex_pfl_name[MKEX_NAME_LEN];
953 unsigned char dmac[6];
954 unsigned char smac[6];
974 struct npc_install_flow_req {
975 struct mbox_msghdr hdr;
976 struct flow_msg packet;
977 struct flow_msg mask;
982 u8 set_cntr; /* If counter is available set counter for this entry ? */
984 u8 append; /* overwrite(0) or append(1) flow to default rule? */
1003 struct npc_install_flow_rsp {
1004 struct mbox_msghdr hdr;
1005 int counter; /* negative if no counter else counter number */
1008 struct npc_delete_flow_req {
1009 struct mbox_msghdr hdr;
1011 u16 start;/*Disable range of entries */
1013 u8 all; /* PF + VFs */
1016 struct npc_mcam_read_entry_req {
1017 struct mbox_msghdr hdr;
1018 u16 entry; /* MCAM entry to read */
1021 struct npc_mcam_read_entry_rsp {
1022 struct mbox_msghdr hdr;
1023 struct mcam_entry entry_data;
1028 struct npc_mcam_read_base_rule_rsp {
1029 struct mbox_msghdr hdr;
1030 struct mcam_entry entry;
1035 PTP_OP_GET_CLOCK = 1,
1039 struct mbox_msghdr hdr;
1045 struct mbox_msghdr hdr;