1 /* SPDX-License-Identifier: GPL-2.0
2 * Marvell OcteonTx2 RVU Admin Function driver
4 * Copyright (C) 2018 Marvell International Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
14 #include <linux/etherdevice.h>
15 #include <linux/sizes.h>
17 #include "rvu_struct.h"
20 #define MBOX_SIZE SZ_64K
22 /* AF/PF: PF initiated, PF/VF VF initiated */
23 #define MBOX_DOWN_RX_START 0
24 #define MBOX_DOWN_RX_SIZE (46 * SZ_1K)
25 #define MBOX_DOWN_TX_START (MBOX_DOWN_RX_START + MBOX_DOWN_RX_SIZE)
26 #define MBOX_DOWN_TX_SIZE (16 * SZ_1K)
27 /* AF/PF: AF initiated, PF/VF PF initiated */
28 #define MBOX_UP_RX_START (MBOX_DOWN_TX_START + MBOX_DOWN_TX_SIZE)
29 #define MBOX_UP_RX_SIZE SZ_1K
30 #define MBOX_UP_TX_START (MBOX_UP_RX_START + MBOX_UP_RX_SIZE)
31 #define MBOX_UP_TX_SIZE SZ_1K
33 #if MBOX_UP_TX_SIZE + MBOX_UP_TX_START != MBOX_SIZE
34 # error "incorrect mailbox area sizes"
37 #define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull))
39 #define MBOX_RSP_TIMEOUT 1000 /* in ms, Time to wait for mbox response */
41 #define MBOX_MSG_ALIGN 16 /* Align mbox msg start to 16bytes */
43 /* Mailbox directions */
44 #define MBOX_DIR_AFPF 0 /* AF replies to PF */
45 #define MBOX_DIR_PFAF 1 /* PF sends messages to AF */
46 #define MBOX_DIR_PFVF 2 /* PF replies to VF */
47 #define MBOX_DIR_VFPF 3 /* VF sends messages to PF */
48 #define MBOX_DIR_AFPF_UP 4 /* AF sends messages to PF */
49 #define MBOX_DIR_PFAF_UP 5 /* PF replies to AF */
50 #define MBOX_DIR_PFVF_UP 6 /* PF sends messages to VF */
51 #define MBOX_DIR_VFPF_UP 7 /* VF replies to PF */
53 struct otx2_mbox_dev {
54 void *mbase; /* This dev's mbox region */
56 u16 msg_size; /* Total msg size to be sent */
57 u16 rsp_size; /* Total rsp size to be sure the reply is ok */
58 u16 num_msgs; /* No of msgs sent or waiting for response */
59 u16 msgs_acked; /* No of msgs for which response is received */
64 void *hwbase; /* Mbox region advertised by HW */
65 void *reg_base;/* CSR base for this dev */
66 u64 trigger; /* Trigger mbox notification */
67 u16 tr_shift; /* Mbox trigger shift */
68 u64 rx_start; /* Offset of Rx region in mbox memory */
69 u64 tx_start; /* Offset of Tx region in mbox memory */
70 u16 rx_size; /* Size of Rx region */
71 u16 tx_size; /* Size of Tx region */
72 u16 ndevs; /* The number of peers */
73 struct otx2_mbox_dev *dev;
76 /* Header which preceeds all mbox messages */
78 u16 num_msgs; /* No of msgs embedded */
81 /* Header which preceeds every msg and is also part of it */
83 u16 pcifunc; /* Who's sending this msg */
84 u16 id; /* Mbox message ID */
85 #define OTX2_MBOX_REQ_SIG (0xdead)
86 #define OTX2_MBOX_RSP_SIG (0xbeef)
87 u16 sig; /* Signature, for validating corrupted msgs */
88 #define OTX2_MBOX_VERSION (0x0001)
89 u16 ver; /* Version of msg's structure for this ID */
90 u16 next_msgoff; /* Offset of next msg within mailbox region */
91 int rc; /* Msg process'ed response code */
94 void otx2_mbox_reset(struct otx2_mbox *mbox, int devid);
95 void otx2_mbox_destroy(struct otx2_mbox *mbox);
96 int otx2_mbox_init(struct otx2_mbox *mbox, void __force *hwbase,
97 struct pci_dev *pdev, void __force *reg_base,
98 int direction, int ndevs);
99 void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid);
100 int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid);
101 int otx2_mbox_busy_poll_for_rsp(struct otx2_mbox *mbox, int devid);
102 struct mbox_msghdr *otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid,
103 int size, int size_rsp);
104 struct mbox_msghdr *otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid,
105 struct mbox_msghdr *msg);
106 int otx2_mbox_check_rsp_msgs(struct otx2_mbox *mbox, int devid);
107 int otx2_reply_invalid_msg(struct otx2_mbox *mbox, int devid,
108 u16 pcifunc, u16 id);
109 bool otx2_mbox_nonempty(struct otx2_mbox *mbox, int devid);
110 const char *otx2_mbox_id2name(u16 id);
111 static inline struct mbox_msghdr *otx2_mbox_alloc_msg(struct otx2_mbox *mbox,
114 return otx2_mbox_alloc_msg_rsp(mbox, devid, size, 0);
117 /* Mailbox message types */
118 #define MBOX_MSG_MASK 0xFFFF
119 #define MBOX_MSG_INVALID 0xFFFE
120 #define MBOX_MSG_MAX 0xFFFF
122 #define MBOX_MESSAGES \
123 /* Generic mbox IDs (range 0x000 - 0x1FF) */ \
124 M(READY, 0x001, ready, msg_req, ready_msg_rsp) \
125 M(ATTACH_RESOURCES, 0x002, attach_resources, rsrc_attach, msg_rsp) \
126 M(DETACH_RESOURCES, 0x003, detach_resources, rsrc_detach, msg_rsp) \
127 M(MSIX_OFFSET, 0x004, msix_offset, msg_req, msix_offset_rsp) \
128 M(VF_FLR, 0x006, vf_flr, msg_req, msg_rsp) \
129 /* CGX mbox IDs (range 0x200 - 0x3FF) */ \
130 M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \
131 M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \
132 M(CGX_STATS, 0x202, cgx_stats, msg_req, cgx_stats_rsp) \
133 M(CGX_MAC_ADDR_SET, 0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get, \
134 cgx_mac_addr_set_or_get) \
135 M(CGX_MAC_ADDR_GET, 0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get, \
136 cgx_mac_addr_set_or_get) \
137 M(CGX_PROMISC_ENABLE, 0x205, cgx_promisc_enable, msg_req, msg_rsp) \
138 M(CGX_PROMISC_DISABLE, 0x206, cgx_promisc_disable, msg_req, msg_rsp) \
139 M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp) \
140 M(CGX_STOP_LINKEVENTS, 0x208, cgx_stop_linkevents, msg_req, msg_rsp) \
141 M(CGX_GET_LINKINFO, 0x209, cgx_get_linkinfo, msg_req, cgx_link_info_msg) \
142 M(CGX_INTLBK_ENABLE, 0x20A, cgx_intlbk_enable, msg_req, msg_rsp) \
143 M(CGX_INTLBK_DISABLE, 0x20B, cgx_intlbk_disable, msg_req, msg_rsp) \
144 /* NPA mbox IDs (range 0x400 - 0x5FF) */ \
145 M(NPA_LF_ALLOC, 0x400, npa_lf_alloc, \
146 npa_lf_alloc_req, npa_lf_alloc_rsp) \
147 M(NPA_LF_FREE, 0x401, npa_lf_free, msg_req, msg_rsp) \
148 M(NPA_AQ_ENQ, 0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp) \
149 M(NPA_HWCTX_DISABLE, 0x403, npa_hwctx_disable, hwctx_disable_req, msg_rsp)\
150 /* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */ \
151 /* TIM mbox IDs (range 0x800 - 0x9FF) */ \
152 /* CPT mbox IDs (range 0xA00 - 0xBFF) */ \
153 /* NPC mbox IDs (range 0x6000 - 0x7FFF) */ \
154 M(NPC_MCAM_ALLOC_ENTRY, 0x6000, npc_mcam_alloc_entry, npc_mcam_alloc_entry_req,\
155 npc_mcam_alloc_entry_rsp) \
156 M(NPC_MCAM_FREE_ENTRY, 0x6001, npc_mcam_free_entry, \
157 npc_mcam_free_entry_req, msg_rsp) \
158 M(NPC_MCAM_WRITE_ENTRY, 0x6002, npc_mcam_write_entry, \
159 npc_mcam_write_entry_req, msg_rsp) \
160 M(NPC_MCAM_ENA_ENTRY, 0x6003, npc_mcam_ena_entry, \
161 npc_mcam_ena_dis_entry_req, msg_rsp) \
162 M(NPC_MCAM_DIS_ENTRY, 0x6004, npc_mcam_dis_entry, \
163 npc_mcam_ena_dis_entry_req, msg_rsp) \
164 M(NPC_MCAM_SHIFT_ENTRY, 0x6005, npc_mcam_shift_entry, npc_mcam_shift_entry_req,\
165 npc_mcam_shift_entry_rsp) \
166 M(NPC_MCAM_ALLOC_COUNTER, 0x6006, npc_mcam_alloc_counter, \
167 npc_mcam_alloc_counter_req, \
168 npc_mcam_alloc_counter_rsp) \
169 M(NPC_MCAM_FREE_COUNTER, 0x6007, npc_mcam_free_counter, \
170 npc_mcam_oper_counter_req, msg_rsp) \
171 M(NPC_MCAM_UNMAP_COUNTER, 0x6008, npc_mcam_unmap_counter, \
172 npc_mcam_unmap_counter_req, msg_rsp) \
173 M(NPC_MCAM_CLEAR_COUNTER, 0x6009, npc_mcam_clear_counter, \
174 npc_mcam_oper_counter_req, msg_rsp) \
175 M(NPC_MCAM_COUNTER_STATS, 0x600a, npc_mcam_counter_stats, \
176 npc_mcam_oper_counter_req, \
177 npc_mcam_oper_counter_rsp) \
178 M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, npc_mcam_alloc_and_write_entry, \
179 npc_mcam_alloc_and_write_entry_req, \
180 npc_mcam_alloc_and_write_entry_rsp) \
181 M(NPC_GET_KEX_CFG, 0x600c, npc_get_kex_cfg, \
182 msg_req, npc_get_kex_cfg_rsp) \
183 /* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \
184 M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, \
185 nix_lf_alloc_req, nix_lf_alloc_rsp) \
186 M(NIX_LF_FREE, 0x8001, nix_lf_free, msg_req, msg_rsp) \
187 M(NIX_AQ_ENQ, 0x8002, nix_aq_enq, nix_aq_enq_req, nix_aq_enq_rsp) \
188 M(NIX_HWCTX_DISABLE, 0x8003, nix_hwctx_disable, \
189 hwctx_disable_req, msg_rsp) \
190 M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc, \
191 nix_txsch_alloc_req, nix_txsch_alloc_rsp) \
192 M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free, nix_txsch_free_req, msg_rsp) \
193 M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_cfg, nix_txschq_config, msg_rsp) \
194 M(NIX_STATS_RST, 0x8007, nix_stats_rst, msg_req, msg_rsp) \
195 M(NIX_VTAG_CFG, 0x8008, nix_vtag_cfg, nix_vtag_config, msg_rsp) \
196 M(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, \
197 nix_rss_flowkey_cfg, \
198 nix_rss_flowkey_cfg_rsp) \
199 M(NIX_SET_MAC_ADDR, 0x800a, nix_set_mac_addr, nix_set_mac_addr, msg_rsp) \
200 M(NIX_SET_RX_MODE, 0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp) \
201 M(NIX_SET_HW_FRS, 0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp) \
202 M(NIX_LF_START_RX, 0x800d, nix_lf_start_rx, msg_req, msg_rsp) \
203 M(NIX_LF_STOP_RX, 0x800e, nix_lf_stop_rx, msg_req, msg_rsp) \
204 M(NIX_MARK_FORMAT_CFG, 0x800f, nix_mark_format_cfg, \
205 nix_mark_format_cfg, \
206 nix_mark_format_cfg_rsp) \
207 M(NIX_SET_RX_CFG, 0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp) \
208 M(NIX_LSO_FORMAT_CFG, 0x8011, nix_lso_format_cfg, \
209 nix_lso_format_cfg, \
210 nix_lso_format_cfg_rsp) \
211 M(NIX_RXVLAN_ALLOC, 0x8012, nix_rxvlan_alloc, msg_req, msg_rsp)
213 /* Messages initiated by AF (range 0xC00 - 0xDFF) */
214 #define MBOX_UP_CGX_MESSAGES \
215 M(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, msg_rsp)
218 #define M(_name, _id, _1, _2, _3) MBOX_MSG_ ## _name = _id,
224 /* Mailbox message formats */
226 #define RVU_DEFAULT_PF_FUNC 0xFFFF
228 /* Generic request msg used for those mbox messages which
229 * don't send any data in the request.
232 struct mbox_msghdr hdr;
235 /* Generic rsponse msg used a ack or response for those mbox
236 * messages which doesn't have a specific rsp msg format.
239 struct mbox_msghdr hdr;
242 /* RVU mailbox error codes
246 RVU_INVALID_VF_ID = -256,
249 struct ready_msg_rsp {
250 struct mbox_msghdr hdr;
251 u16 sclk_feq; /* SCLK frequency */
254 /* Structure for requesting resource provisioning.
255 * 'modify' flag to be used when either requesting more
256 * or to detach partial of a cetain resource type.
257 * Rest of the fields specify how many of what type to
261 struct mbox_msghdr hdr;
271 /* Structure for relinquishing resources.
272 * 'partial' flag to be used when relinquishing all resources
273 * but only of a certain type. If not set, all resources of all
274 * types provisioned to the RVU function will be detached.
277 struct mbox_msghdr hdr;
287 #define MSIX_VECTOR_INVALID 0xFFFF
288 #define MAX_RVU_BLKLF_CNT 256
290 struct msix_offset_rsp {
291 struct mbox_msghdr hdr;
298 u16 sso_msixoff[MAX_RVU_BLKLF_CNT];
299 u16 ssow_msixoff[MAX_RVU_BLKLF_CNT];
300 u16 timlf_msixoff[MAX_RVU_BLKLF_CNT];
301 u16 cptlf_msixoff[MAX_RVU_BLKLF_CNT];
304 /* CGX mbox message formats */
306 struct cgx_stats_rsp {
307 struct mbox_msghdr hdr;
308 #define CGX_RX_STATS_COUNT 13
309 #define CGX_TX_STATS_COUNT 18
310 u64 rx_stats[CGX_RX_STATS_COUNT];
311 u64 tx_stats[CGX_TX_STATS_COUNT];
314 /* Structure for requesting the operation for
315 * setting/getting mac address in the CGX interface
317 struct cgx_mac_addr_set_or_get {
318 struct mbox_msghdr hdr;
319 u8 mac_addr[ETH_ALEN];
322 struct cgx_link_user_info {
324 uint64_t full_duplex:1;
325 uint64_t lmac_type_id:4;
326 uint64_t speed:20; /* speed in Mbps */
327 #define LMACTYPE_STR_LEN 16
328 char lmac_type[LMACTYPE_STR_LEN];
331 struct cgx_link_info_msg {
332 struct mbox_msghdr hdr;
333 struct cgx_link_user_info link_info;
336 /* NPA mbox message formats */
338 /* NPA mailbox error codes
342 NPA_AF_ERR_PARAM = -301,
343 NPA_AF_ERR_AQ_FULL = -302,
344 NPA_AF_ERR_AQ_ENQUEUE = -303,
345 NPA_AF_ERR_AF_LF_INVALID = -304,
346 NPA_AF_ERR_AF_LF_ALLOC = -305,
347 NPA_AF_ERR_LF_RESET = -306,
350 /* For NPA LF context alloc and init */
351 struct npa_lf_alloc_req {
352 struct mbox_msghdr hdr;
354 int aura_sz; /* No of auras */
355 u32 nr_pools; /* No of pools */
358 struct npa_lf_alloc_rsp {
359 struct mbox_msghdr hdr;
360 u32 stack_pg_ptrs; /* No of ptrs per stack page */
361 u32 stack_pg_bytes; /* Size of stack page */
362 u16 qints; /* NPA_AF_CONST::QINTS */
365 /* NPA AQ enqueue msg */
366 struct npa_aq_enq_req {
367 struct mbox_msghdr hdr;
372 /* Valid when op == WRITE/INIT and ctype == AURA.
373 * LF fills the pool_id in aura.pool_addr. AF will translate
374 * the pool_id to pool context pointer.
376 struct npa_aura_s aura;
377 /* Valid when op == WRITE/INIT and ctype == POOL */
378 struct npa_pool_s pool;
380 /* Mask data when op == WRITE (1=write, 0=don't write) */
382 /* Valid when op == WRITE and ctype == AURA */
383 struct npa_aura_s aura_mask;
384 /* Valid when op == WRITE and ctype == POOL */
385 struct npa_pool_s pool_mask;
389 struct npa_aq_enq_rsp {
390 struct mbox_msghdr hdr;
392 /* Valid when op == READ and ctype == AURA */
393 struct npa_aura_s aura;
394 /* Valid when op == READ and ctype == POOL */
395 struct npa_pool_s pool;
399 /* Disable all contexts of type 'ctype' */
400 struct hwctx_disable_req {
401 struct mbox_msghdr hdr;
405 /* NIX mbox message formats */
407 /* NIX mailbox error codes
411 NIX_AF_ERR_PARAM = -401,
412 NIX_AF_ERR_AQ_FULL = -402,
413 NIX_AF_ERR_AQ_ENQUEUE = -403,
414 NIX_AF_ERR_AF_LF_INVALID = -404,
415 NIX_AF_ERR_AF_LF_ALLOC = -405,
416 NIX_AF_ERR_TLX_ALLOC_FAIL = -406,
417 NIX_AF_ERR_TLX_INVALID = -407,
418 NIX_AF_ERR_RSS_SIZE_INVALID = -408,
419 NIX_AF_ERR_RSS_GRPS_INVALID = -409,
420 NIX_AF_ERR_FRS_INVALID = -410,
421 NIX_AF_ERR_RX_LINK_INVALID = -411,
422 NIX_AF_INVAL_TXSCHQ_CFG = -412,
423 NIX_AF_SMQ_FLUSH_FAILED = -413,
424 NIX_AF_ERR_LF_RESET = -414,
425 NIX_AF_ERR_RSS_NOSPC_FIELD = -415,
426 NIX_AF_ERR_RSS_NOSPC_ALGO = -416,
427 NIX_AF_ERR_MARK_CFG_FAIL = -417,
428 NIX_AF_ERR_LSO_CFG_FAIL = -418,
429 NIX_AF_INVAL_NPA_PF_FUNC = -419,
430 NIX_AF_INVAL_SSO_PF_FUNC = -420,
433 /* For NIX LF context alloc and init */
434 struct nix_lf_alloc_req {
435 struct mbox_msghdr hdr;
437 u32 rq_cnt; /* No of receive queues */
438 u32 sq_cnt; /* No of send queues */
439 u32 cq_cnt; /* No of completion queues */
445 u64 rx_cfg; /* See NIX_AF_LF(0..127)_RX_CFG */
448 struct nix_lf_alloc_rsp {
449 struct mbox_msghdr hdr;
453 u8 rx_chan_cnt; /* total number of RX channels */
454 u8 tx_chan_cnt; /* total number of TX channels */
457 u8 mac_addr[ETH_ALEN];
458 u8 lf_rx_stats; /* NIX_AF_CONST1::LF_RX_STATS */
459 u8 lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */
460 u16 cints; /* NIX_AF_CONST2::CINTS */
461 u16 qints; /* NIX_AF_CONST2::QINTS */
464 /* NIX AQ enqueue msg */
465 struct nix_aq_enq_req {
466 struct mbox_msghdr hdr;
471 struct nix_rq_ctx_s rq;
472 struct nix_sq_ctx_s sq;
473 struct nix_cq_ctx_s cq;
474 struct nix_rsse_s rss;
475 struct nix_rx_mce_s mce;
478 struct nix_rq_ctx_s rq_mask;
479 struct nix_sq_ctx_s sq_mask;
480 struct nix_cq_ctx_s cq_mask;
481 struct nix_rsse_s rss_mask;
482 struct nix_rx_mce_s mce_mask;
486 struct nix_aq_enq_rsp {
487 struct mbox_msghdr hdr;
489 struct nix_rq_ctx_s rq;
490 struct nix_sq_ctx_s sq;
491 struct nix_cq_ctx_s cq;
492 struct nix_rsse_s rss;
493 struct nix_rx_mce_s mce;
497 /* Tx scheduler/shaper mailbox messages */
499 #define MAX_TXSCHQ_PER_FUNC 128
501 struct nix_txsch_alloc_req {
502 struct mbox_msghdr hdr;
503 /* Scheduler queue count request at each level */
504 u16 schq_contig[NIX_TXSCH_LVL_CNT]; /* No of contiguous queues */
505 u16 schq[NIX_TXSCH_LVL_CNT]; /* No of non-contiguous queues */
508 struct nix_txsch_alloc_rsp {
509 struct mbox_msghdr hdr;
510 /* Scheduler queue count allocated at each level */
511 u16 schq_contig[NIX_TXSCH_LVL_CNT];
512 u16 schq[NIX_TXSCH_LVL_CNT];
513 /* Scheduler queue list allocated at each level */
514 u16 schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
515 u16 schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
518 struct nix_txsch_free_req {
519 struct mbox_msghdr hdr;
520 #define TXSCHQ_FREE_ALL BIT_ULL(0)
522 /* Scheduler queue level to be freed */
524 /* List of scheduler queues to be freed */
528 struct nix_txschq_config {
529 struct mbox_msghdr hdr;
530 u8 lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */
531 #define TXSCHQ_IDX_SHIFT 16
532 #define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1)
533 #define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK)
535 #define MAX_REGS_PER_MBOX_MSG 20
536 u64 reg[MAX_REGS_PER_MBOX_MSG];
537 u64 regval[MAX_REGS_PER_MBOX_MSG];
540 struct nix_vtag_config {
541 struct mbox_msghdr hdr;
542 /* '0' for 4 octet VTAG, '1' for 8 octet VTAG */
544 /* cfg_type is '0' for tx vlan cfg
545 * cfg_type is '1' for rx vlan cfg
549 /* valid when cfg_type is '0' */
551 /* tx vlan0 tag(C-VLAN) */
553 /* tx vlan1 tag(S-VLAN) */
555 /* insert tx vlan tag */
557 /* insert tx double vlan tag */
561 /* valid when cfg_type is '1' */
563 /* rx vtag type index, valid values are in 0..7 range */
567 /* rx vtag capture */
573 struct nix_rss_flowkey_cfg {
574 struct mbox_msghdr hdr;
575 int mcam_index; /* MCAM entry index to modify */
576 #define NIX_FLOW_KEY_TYPE_PORT BIT(0)
577 #define NIX_FLOW_KEY_TYPE_IPV4 BIT(1)
578 #define NIX_FLOW_KEY_TYPE_IPV6 BIT(2)
579 #define NIX_FLOW_KEY_TYPE_TCP BIT(3)
580 #define NIX_FLOW_KEY_TYPE_UDP BIT(4)
581 #define NIX_FLOW_KEY_TYPE_SCTP BIT(5)
582 u32 flowkey_cfg; /* Flowkey types selected */
583 u8 group; /* RSS context or group */
586 struct nix_rss_flowkey_cfg_rsp {
587 struct mbox_msghdr hdr;
588 u8 alg_idx; /* Selected algo index */
591 struct nix_set_mac_addr {
592 struct mbox_msghdr hdr;
593 u8 mac_addr[ETH_ALEN]; /* MAC address to be set for this pcifunc */
596 struct nix_mark_format_cfg {
597 struct mbox_msghdr hdr;
605 struct nix_mark_format_cfg_rsp {
606 struct mbox_msghdr hdr;
611 struct mbox_msghdr hdr;
612 #define NIX_RX_MODE_UCAST BIT(0)
613 #define NIX_RX_MODE_PROMISC BIT(1)
614 #define NIX_RX_MODE_ALLMULTI BIT(2)
619 struct mbox_msghdr hdr;
620 #define NIX_RX_OL3_VERIFY BIT(0)
621 #define NIX_RX_OL4_VERIFY BIT(1)
622 u8 len_verify; /* Outer L3/L4 len check */
623 #define NIX_RX_CSUM_OL4_VERIFY BIT(0)
624 u8 csum_verify; /* Outer L4 checksum verification */
628 struct mbox_msghdr hdr;
629 u8 update_smq; /* Update SMQ's min/max lens */
630 u8 update_minlen; /* Set minlen also */
631 u8 sdp_link; /* Set SDP RX link */
636 struct nix_lso_format_cfg {
637 struct mbox_msghdr hdr;
639 #define NIX_LSO_FIELD_MAX 8
640 u64 fields[NIX_LSO_FIELD_MAX];
643 struct nix_lso_format_cfg_rsp {
644 struct mbox_msghdr hdr;
648 /* NPC mbox message structs */
650 #define NPC_MCAM_ENTRY_INVALID 0xFFFF
651 #define NPC_MCAM_INVALID_MAP 0xFFFF
653 /* NPC mailbox error codes
657 NPC_MCAM_INVALID_REQ = -701,
658 NPC_MCAM_ALLOC_DENIED = -702,
659 NPC_MCAM_ALLOC_FAILED = -703,
660 NPC_MCAM_PERM_DENIED = -704,
663 struct npc_mcam_alloc_entry_req {
664 struct mbox_msghdr hdr;
665 #define NPC_MAX_NONCONTIG_ENTRIES 256
666 u8 contig; /* Contiguous entries ? */
667 #define NPC_MCAM_ANY_PRIO 0
668 #define NPC_MCAM_LOWER_PRIO 1
669 #define NPC_MCAM_HIGHER_PRIO 2
670 u8 priority; /* Lower or higher w.r.t ref_entry */
672 u16 count; /* Number of entries requested */
675 struct npc_mcam_alloc_entry_rsp {
676 struct mbox_msghdr hdr;
677 u16 entry; /* Entry allocated or start index if contiguous.
678 * Invalid incase of non-contiguous.
680 u16 count; /* Number of entries allocated */
681 u16 free_count; /* Number of entries available */
682 u16 entry_list[NPC_MAX_NONCONTIG_ENTRIES];
685 struct npc_mcam_free_entry_req {
686 struct mbox_msghdr hdr;
687 u16 entry; /* Entry index to be freed */
688 u8 all; /* If all entries allocated to this PFVF to be freed */
692 #define NPC_MAX_KWS_IN_KEY 7 /* Number of keywords in max keywidth */
693 u64 kw[NPC_MAX_KWS_IN_KEY];
694 u64 kw_mask[NPC_MAX_KWS_IN_KEY];
699 struct npc_mcam_write_entry_req {
700 struct mbox_msghdr hdr;
701 struct mcam_entry entry_data;
702 u16 entry; /* MCAM entry to write this match key */
703 u16 cntr; /* Counter for this MCAM entry */
704 u8 intf; /* Rx or Tx interface */
705 u8 enable_entry;/* Enable this MCAM entry ? */
706 u8 set_cntr; /* Set counter for this entry ? */
709 /* Enable/Disable a given entry */
710 struct npc_mcam_ena_dis_entry_req {
711 struct mbox_msghdr hdr;
715 struct npc_mcam_shift_entry_req {
716 struct mbox_msghdr hdr;
717 #define NPC_MCAM_MAX_SHIFTS 64
718 u16 curr_entry[NPC_MCAM_MAX_SHIFTS];
719 u16 new_entry[NPC_MCAM_MAX_SHIFTS];
720 u16 shift_count; /* Number of entries to shift */
723 struct npc_mcam_shift_entry_rsp {
724 struct mbox_msghdr hdr;
725 u16 failed_entry_idx; /* Index in 'curr_entry', not entry itself */
728 struct npc_mcam_alloc_counter_req {
729 struct mbox_msghdr hdr;
730 u8 contig; /* Contiguous counters ? */
731 #define NPC_MAX_NONCONTIG_COUNTERS 64
732 u16 count; /* Number of counters requested */
735 struct npc_mcam_alloc_counter_rsp {
736 struct mbox_msghdr hdr;
737 u16 cntr; /* Counter allocated or start index if contiguous.
738 * Invalid incase of non-contiguous.
740 u16 count; /* Number of counters allocated */
741 u16 cntr_list[NPC_MAX_NONCONTIG_COUNTERS];
744 struct npc_mcam_oper_counter_req {
745 struct mbox_msghdr hdr;
746 u16 cntr; /* Free a counter or clear/fetch it's stats */
749 struct npc_mcam_oper_counter_rsp {
750 struct mbox_msghdr hdr;
751 u64 stat; /* valid only while fetching counter's stats */
754 struct npc_mcam_unmap_counter_req {
755 struct mbox_msghdr hdr;
757 u16 entry; /* Entry and counter to be unmapped */
758 u8 all; /* Unmap all entries using this counter ? */
761 struct npc_mcam_alloc_and_write_entry_req {
762 struct mbox_msghdr hdr;
763 struct mcam_entry entry_data;
765 u8 priority; /* Lower or higher w.r.t ref_entry */
766 u8 intf; /* Rx or Tx interface */
767 u8 enable_entry;/* Enable this MCAM entry ? */
768 u8 alloc_cntr; /* Allocate counter and map ? */
771 struct npc_mcam_alloc_and_write_entry_rsp {
772 struct mbox_msghdr hdr;
777 struct npc_get_kex_cfg_rsp {
778 struct mbox_msghdr hdr;
779 u64 rx_keyx_cfg; /* NPC_AF_INTF(0)_KEX_CFG */
780 u64 tx_keyx_cfg; /* NPC_AF_INTF(1)_KEX_CFG */
781 #define NPC_MAX_INTF 2
782 #define NPC_MAX_LID 8
783 #define NPC_MAX_LT 16
785 #define NPC_MAX_LFL 16
786 /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */
787 u64 kex_ld_flags[NPC_MAX_LD];
788 /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */
789 u64 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD];
790 /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */
791 u64 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL];
792 #define MKEX_NAME_LEN 128
793 u8 mkex_pfl_name[MKEX_NAME_LEN];