Merge tag 'for-linus' of git://github.com/openrisc/linux
[linux-2.6-microblaze.git] / drivers / net / ethernet / marvell / octeontx2 / af / lmac_common.h
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*  Marvell OcteonTx2 RPM driver
3  *
4  * Copyright (C) 2020 Marvell.
5  */
6
7 #ifndef LMAC_COMMON_H
8 #define LMAC_COMMON_H
9
10 #include "rvu.h"
11 #include "cgx.h"
12 /**
13  * struct lmac
14  * @wq_cmd_cmplt:       waitq to keep the process blocked until cmd completion
15  * @cmd_lock:           Lock to serialize the command interface
16  * @resp:               command response
17  * @link_info:          link related information
18  * @event_cb:           callback for linkchange events
19  * @event_cb_lock:      lock for serializing callback with unregister
20  * @cmd_pend:           flag set before new command is started
21  *                      flag cleared after command response is received
22  * @cgx:                parent cgx port
23  * @lmac_id:            lmac port id
24  * @name:               lmac port name
25  */
26 struct lmac {
27         wait_queue_head_t wq_cmd_cmplt;
28         /* Lock to serialize the command interface */
29         struct mutex cmd_lock;
30         u64 resp;
31         struct cgx_link_user_info link_info;
32         struct cgx_event_cb event_cb;
33         /* lock for serializing callback with unregister */
34         spinlock_t event_cb_lock;
35         bool cmd_pend;
36         struct cgx *cgx;
37         u8 lmac_id;
38         char *name;
39 };
40
41 /* CGX & RPM has different feature set
42  * update the structure fields with different one
43  */
44 struct mac_ops {
45         char                   *name;
46         /* Features like RXSTAT, TXSTAT, DMAC FILTER csrs differs by fixed
47          * bar offset for example
48          * CGX DMAC_CTL0  0x1f8
49          * RPM DMAC_CTL0  0x4ff8
50          */
51         u64                     csr_offset;
52         /* For ATF to send events to kernel, there is no dedicated interrupt
53          * defined hence CGX uses OVERFLOW bit in CMR_INT. RPM block supports
54          * SW_INT so that ATF triggers this interrupt after processing of
55          * requested command
56          */
57         u64                     int_register;
58         u64                     int_set_reg;
59         /* lmac offset is different is RPM */
60         u8                      lmac_offset;
61         u8                      irq_offset;
62         u8                      int_ena_bit;
63         u8                      lmac_fwi;
64         u32                     fifo_len;
65         bool                    non_contiguous_serdes_lane;
66         /* RPM & CGX differs in number of Receive/transmit stats */
67         u8                      rx_stats_cnt;
68         u8                      tx_stats_cnt;
69         /* Incase of RPM get number of lmacs from RPMX_CMR_RX_LMACS[LMAC_EXIST]
70          * number of setbits in lmac_exist tells number of lmacs
71          */
72         int                     (*get_nr_lmacs)(void *cgx);
73         u8                      (*get_lmac_type)(void *cgx, int lmac_id);
74         int                     (*mac_lmac_intl_lbk)(void *cgx, int lmac_id,
75                                                      bool enable);
76         /* Register Stats related functions */
77         int                     (*mac_get_rx_stats)(void *cgx, int lmac_id,
78                                                     int idx, u64 *rx_stat);
79         int                     (*mac_get_tx_stats)(void *cgx, int lmac_id,
80                                                     int idx, u64 *tx_stat);
81
82         /* Enable LMAC Pause Frame Configuration */
83         void                    (*mac_enadis_rx_pause_fwding)(void *cgxd,
84                                                               int lmac_id,
85                                                               bool enable);
86
87         int                     (*mac_get_pause_frm_status)(void *cgxd,
88                                                             int lmac_id,
89                                                             u8 *tx_pause,
90                                                             u8 *rx_pause);
91
92         int                     (*mac_enadis_pause_frm)(void *cgxd,
93                                                         int lmac_id,
94                                                         u8 tx_pause,
95                                                         u8 rx_pause);
96
97         void                    (*mac_pause_frm_config)(void  *cgxd,
98                                                         int lmac_id,
99                                                         bool enable);
100 };
101
102 struct cgx {
103         void __iomem            *reg_base;
104         struct pci_dev          *pdev;
105         u8                      cgx_id;
106         u8                      lmac_count;
107         struct lmac             *lmac_idmap[MAX_LMAC_PER_CGX];
108         struct                  work_struct cgx_cmd_work;
109         struct                  workqueue_struct *cgx_cmd_workq;
110         struct list_head        cgx_list;
111         u64                     hw_features;
112         struct mac_ops          *mac_ops;
113         unsigned long           lmac_bmap; /* bitmap of enabled lmacs */
114         /* Lock to serialize read/write of global csrs like
115          * RPMX_MTI_STAT_DATA_HI_CDC etc
116          */
117         struct mutex            lock;
118 };
119
120 typedef struct cgx rpm_t;
121
122 /* Function Declarations */
123 void cgx_write(struct cgx *cgx, u64 lmac, u64 offset, u64 val);
124 u64 cgx_read(struct cgx *cgx, u64 lmac, u64 offset);
125 struct lmac *lmac_pdata(u8 lmac_id, struct cgx *cgx);
126 int cgx_fwi_cmd_send(u64 req, u64 *resp, struct lmac *lmac);
127 int cgx_fwi_cmd_generic(u64 req, u64 *resp, struct cgx *cgx, int lmac_id);
128 bool is_lmac_valid(struct cgx *cgx, int lmac_id);
129 struct mac_ops *rpm_get_mac_ops(void);
130
131 #endif /* LMAC_COMMON_H */