2 * Driver for Marvell PPv2 network controller for Armada 375 SoC.
4 * Copyright (C) 2014 Marvell
6 * Marcin Wojtas <mw@semihalf.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
13 #include <linux/kernel.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/platform_device.h>
17 #include <linux/skbuff.h>
18 #include <linux/inetdevice.h>
19 #include <linux/mbus.h>
20 #include <linux/module.h>
21 #include <linux/interrupt.h>
22 #include <linux/cpumask.h>
24 #include <linux/of_irq.h>
25 #include <linux/of_mdio.h>
26 #include <linux/of_net.h>
27 #include <linux/of_address.h>
28 #include <linux/of_device.h>
29 #include <linux/phy.h>
30 #include <linux/clk.h>
31 #include <linux/hrtimer.h>
32 #include <linux/ktime.h>
33 #include <uapi/linux/ppp_defs.h>
37 /* RX Fifo Registers */
38 #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port))
39 #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port))
40 #define MVPP2_RX_MIN_PKT_SIZE_REG 0x60
41 #define MVPP2_RX_FIFO_INIT_REG 0x64
43 /* RX DMA Top Registers */
44 #define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port))
45 #define MVPP2_RX_LOW_LATENCY_PKT_SIZE(s) (((s) & 0xfff) << 16)
46 #define MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK BIT(31)
47 #define MVPP2_POOL_BUF_SIZE_REG(pool) (0x180 + 4 * (pool))
48 #define MVPP2_POOL_BUF_SIZE_OFFSET 5
49 #define MVPP2_RXQ_CONFIG_REG(rxq) (0x800 + 4 * (rxq))
50 #define MVPP2_SNOOP_PKT_SIZE_MASK 0x1ff
51 #define MVPP2_SNOOP_BUF_HDR_MASK BIT(9)
52 #define MVPP2_RXQ_POOL_SHORT_OFFS 20
53 #define MVPP21_RXQ_POOL_SHORT_MASK 0x700000
54 #define MVPP22_RXQ_POOL_SHORT_MASK 0xf00000
55 #define MVPP2_RXQ_POOL_LONG_OFFS 24
56 #define MVPP21_RXQ_POOL_LONG_MASK 0x7000000
57 #define MVPP22_RXQ_POOL_LONG_MASK 0xf000000
58 #define MVPP2_RXQ_PACKET_OFFSET_OFFS 28
59 #define MVPP2_RXQ_PACKET_OFFSET_MASK 0x70000000
60 #define MVPP2_RXQ_DISABLE_MASK BIT(31)
62 /* Parser Registers */
63 #define MVPP2_PRS_INIT_LOOKUP_REG 0x1000
64 #define MVPP2_PRS_PORT_LU_MAX 0xf
65 #define MVPP2_PRS_PORT_LU_MASK(port) (0xff << ((port) * 4))
66 #define MVPP2_PRS_PORT_LU_VAL(port, val) ((val) << ((port) * 4))
67 #define MVPP2_PRS_INIT_OFFS_REG(port) (0x1004 + ((port) & 4))
68 #define MVPP2_PRS_INIT_OFF_MASK(port) (0x3f << (((port) % 4) * 8))
69 #define MVPP2_PRS_INIT_OFF_VAL(port, val) ((val) << (((port) % 4) * 8))
70 #define MVPP2_PRS_MAX_LOOP_REG(port) (0x100c + ((port) & 4))
71 #define MVPP2_PRS_MAX_LOOP_MASK(port) (0xff << (((port) % 4) * 8))
72 #define MVPP2_PRS_MAX_LOOP_VAL(port, val) ((val) << (((port) % 4) * 8))
73 #define MVPP2_PRS_TCAM_IDX_REG 0x1100
74 #define MVPP2_PRS_TCAM_DATA_REG(idx) (0x1104 + (idx) * 4)
75 #define MVPP2_PRS_TCAM_INV_MASK BIT(31)
76 #define MVPP2_PRS_SRAM_IDX_REG 0x1200
77 #define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4)
78 #define MVPP2_PRS_TCAM_CTRL_REG 0x1230
79 #define MVPP2_PRS_TCAM_EN_MASK BIT(0)
81 /* Classifier Registers */
82 #define MVPP2_CLS_MODE_REG 0x1800
83 #define MVPP2_CLS_MODE_ACTIVE_MASK BIT(0)
84 #define MVPP2_CLS_PORT_WAY_REG 0x1810
85 #define MVPP2_CLS_PORT_WAY_MASK(port) (1 << (port))
86 #define MVPP2_CLS_LKP_INDEX_REG 0x1814
87 #define MVPP2_CLS_LKP_INDEX_WAY_OFFS 6
88 #define MVPP2_CLS_LKP_TBL_REG 0x1818
89 #define MVPP2_CLS_LKP_TBL_RXQ_MASK 0xff
90 #define MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK BIT(25)
91 #define MVPP2_CLS_FLOW_INDEX_REG 0x1820
92 #define MVPP2_CLS_FLOW_TBL0_REG 0x1824
93 #define MVPP2_CLS_FLOW_TBL1_REG 0x1828
94 #define MVPP2_CLS_FLOW_TBL2_REG 0x182c
95 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port) (0x1980 + ((port) * 4))
96 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS 3
97 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK 0x7
98 #define MVPP2_CLS_SWFWD_P2HQ_REG(port) (0x19b0 + ((port) * 4))
99 #define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0
100 #define MVPP2_CLS_SWFWD_PCTRL_MASK(port) (1 << (port))
102 /* Descriptor Manager Top Registers */
103 #define MVPP2_RXQ_NUM_REG 0x2040
104 #define MVPP2_RXQ_DESC_ADDR_REG 0x2044
105 #define MVPP22_DESC_ADDR_OFFS 8
106 #define MVPP2_RXQ_DESC_SIZE_REG 0x2048
107 #define MVPP2_RXQ_DESC_SIZE_MASK 0x3ff0
108 #define MVPP2_RXQ_STATUS_UPDATE_REG(rxq) (0x3000 + 4 * (rxq))
109 #define MVPP2_RXQ_NUM_PROCESSED_OFFSET 0
110 #define MVPP2_RXQ_NUM_NEW_OFFSET 16
111 #define MVPP2_RXQ_STATUS_REG(rxq) (0x3400 + 4 * (rxq))
112 #define MVPP2_RXQ_OCCUPIED_MASK 0x3fff
113 #define MVPP2_RXQ_NON_OCCUPIED_OFFSET 16
114 #define MVPP2_RXQ_NON_OCCUPIED_MASK 0x3fff0000
115 #define MVPP2_RXQ_THRESH_REG 0x204c
116 #define MVPP2_OCCUPIED_THRESH_OFFSET 0
117 #define MVPP2_OCCUPIED_THRESH_MASK 0x3fff
118 #define MVPP2_RXQ_INDEX_REG 0x2050
119 #define MVPP2_TXQ_NUM_REG 0x2080
120 #define MVPP2_TXQ_DESC_ADDR_REG 0x2084
121 #define MVPP2_TXQ_DESC_SIZE_REG 0x2088
122 #define MVPP2_TXQ_DESC_SIZE_MASK 0x3ff0
123 #define MVPP2_AGGR_TXQ_UPDATE_REG 0x2090
124 #define MVPP2_TXQ_INDEX_REG 0x2098
125 #define MVPP2_TXQ_PREF_BUF_REG 0x209c
126 #define MVPP2_PREF_BUF_PTR(desc) ((desc) & 0xfff)
127 #define MVPP2_PREF_BUF_SIZE_4 (BIT(12) | BIT(13))
128 #define MVPP2_PREF_BUF_SIZE_16 (BIT(12) | BIT(14))
129 #define MVPP2_PREF_BUF_THRESH(val) ((val) << 17)
130 #define MVPP2_TXQ_DRAIN_EN_MASK BIT(31)
131 #define MVPP2_TXQ_PENDING_REG 0x20a0
132 #define MVPP2_TXQ_PENDING_MASK 0x3fff
133 #define MVPP2_TXQ_INT_STATUS_REG 0x20a4
134 #define MVPP2_TXQ_SENT_REG(txq) (0x3c00 + 4 * (txq))
135 #define MVPP2_TRANSMITTED_COUNT_OFFSET 16
136 #define MVPP2_TRANSMITTED_COUNT_MASK 0x3fff0000
137 #define MVPP2_TXQ_RSVD_REQ_REG 0x20b0
138 #define MVPP2_TXQ_RSVD_REQ_Q_OFFSET 16
139 #define MVPP2_TXQ_RSVD_RSLT_REG 0x20b4
140 #define MVPP2_TXQ_RSVD_RSLT_MASK 0x3fff
141 #define MVPP2_TXQ_RSVD_CLR_REG 0x20b8
142 #define MVPP2_TXQ_RSVD_CLR_OFFSET 16
143 #define MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu) (0x2100 + 4 * (cpu))
144 #define MVPP22_AGGR_TXQ_DESC_ADDR_OFFS 8
145 #define MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu) (0x2140 + 4 * (cpu))
146 #define MVPP2_AGGR_TXQ_DESC_SIZE_MASK 0x3ff0
147 #define MVPP2_AGGR_TXQ_STATUS_REG(cpu) (0x2180 + 4 * (cpu))
148 #define MVPP2_AGGR_TXQ_PENDING_MASK 0x3fff
149 #define MVPP2_AGGR_TXQ_INDEX_REG(cpu) (0x21c0 + 4 * (cpu))
151 /* MBUS bridge registers */
152 #define MVPP2_WIN_BASE(w) (0x4000 + ((w) << 2))
153 #define MVPP2_WIN_SIZE(w) (0x4020 + ((w) << 2))
154 #define MVPP2_WIN_REMAP(w) (0x4040 + ((w) << 2))
155 #define MVPP2_BASE_ADDR_ENABLE 0x4060
157 /* Interrupt Cause and Mask registers */
158 #define MVPP2_ISR_RX_THRESHOLD_REG(rxq) (0x5200 + 4 * (rxq))
159 #define MVPP2_MAX_ISR_RX_THRESHOLD 0xfffff0
160 #define MVPP2_ISR_RXQ_GROUP_REG(rxq) (0x5400 + 4 * (rxq))
161 #define MVPP2_ISR_ENABLE_REG(port) (0x5420 + 4 * (port))
162 #define MVPP2_ISR_ENABLE_INTERRUPT(mask) ((mask) & 0xffff)
163 #define MVPP2_ISR_DISABLE_INTERRUPT(mask) (((mask) << 16) & 0xffff0000)
164 #define MVPP2_ISR_RX_TX_CAUSE_REG(port) (0x5480 + 4 * (port))
165 #define MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff
166 #define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK 0xff0000
167 #define MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK BIT(24)
168 #define MVPP2_CAUSE_FCS_ERR_MASK BIT(25)
169 #define MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK BIT(26)
170 #define MVPP2_CAUSE_TX_EXCEPTION_SUM_MASK BIT(29)
171 #define MVPP2_CAUSE_RX_EXCEPTION_SUM_MASK BIT(30)
172 #define MVPP2_CAUSE_MISC_SUM_MASK BIT(31)
173 #define MVPP2_ISR_RX_TX_MASK_REG(port) (0x54a0 + 4 * (port))
174 #define MVPP2_ISR_PON_RX_TX_MASK_REG 0x54bc
175 #define MVPP2_PON_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff
176 #define MVPP2_PON_CAUSE_TXP_OCCUP_DESC_ALL_MASK 0x3fc00000
177 #define MVPP2_PON_CAUSE_MISC_SUM_MASK BIT(31)
178 #define MVPP2_ISR_MISC_CAUSE_REG 0x55b0
180 /* Buffer Manager registers */
181 #define MVPP2_BM_POOL_BASE_REG(pool) (0x6000 + ((pool) * 4))
182 #define MVPP2_BM_POOL_BASE_ADDR_MASK 0xfffff80
183 #define MVPP2_BM_POOL_SIZE_REG(pool) (0x6040 + ((pool) * 4))
184 #define MVPP2_BM_POOL_SIZE_MASK 0xfff0
185 #define MVPP2_BM_POOL_READ_PTR_REG(pool) (0x6080 + ((pool) * 4))
186 #define MVPP2_BM_POOL_GET_READ_PTR_MASK 0xfff0
187 #define MVPP2_BM_POOL_PTRS_NUM_REG(pool) (0x60c0 + ((pool) * 4))
188 #define MVPP2_BM_POOL_PTRS_NUM_MASK 0xfff0
189 #define MVPP2_BM_BPPI_READ_PTR_REG(pool) (0x6100 + ((pool) * 4))
190 #define MVPP2_BM_BPPI_PTRS_NUM_REG(pool) (0x6140 + ((pool) * 4))
191 #define MVPP2_BM_BPPI_PTR_NUM_MASK 0x7ff
192 #define MVPP2_BM_BPPI_PREFETCH_FULL_MASK BIT(16)
193 #define MVPP2_BM_POOL_CTRL_REG(pool) (0x6200 + ((pool) * 4))
194 #define MVPP2_BM_START_MASK BIT(0)
195 #define MVPP2_BM_STOP_MASK BIT(1)
196 #define MVPP2_BM_STATE_MASK BIT(4)
197 #define MVPP2_BM_LOW_THRESH_OFFS 8
198 #define MVPP2_BM_LOW_THRESH_MASK 0x7f00
199 #define MVPP2_BM_LOW_THRESH_VALUE(val) ((val) << \
200 MVPP2_BM_LOW_THRESH_OFFS)
201 #define MVPP2_BM_HIGH_THRESH_OFFS 16
202 #define MVPP2_BM_HIGH_THRESH_MASK 0x7f0000
203 #define MVPP2_BM_HIGH_THRESH_VALUE(val) ((val) << \
204 MVPP2_BM_HIGH_THRESH_OFFS)
205 #define MVPP2_BM_INTR_CAUSE_REG(pool) (0x6240 + ((pool) * 4))
206 #define MVPP2_BM_RELEASED_DELAY_MASK BIT(0)
207 #define MVPP2_BM_ALLOC_FAILED_MASK BIT(1)
208 #define MVPP2_BM_BPPE_EMPTY_MASK BIT(2)
209 #define MVPP2_BM_BPPE_FULL_MASK BIT(3)
210 #define MVPP2_BM_AVAILABLE_BP_LOW_MASK BIT(4)
211 #define MVPP2_BM_INTR_MASK_REG(pool) (0x6280 + ((pool) * 4))
212 #define MVPP2_BM_PHY_ALLOC_REG(pool) (0x6400 + ((pool) * 4))
213 #define MVPP2_BM_PHY_ALLOC_GRNTD_MASK BIT(0)
214 #define MVPP2_BM_VIRT_ALLOC_REG 0x6440
215 #define MVPP22_BM_ADDR_HIGH_ALLOC 0x6444
216 #define MVPP22_BM_ADDR_HIGH_PHYS_MASK 0xff
217 #define MVPP22_BM_ADDR_HIGH_VIRT_MASK 0xff00
218 #define MVPP22_BM_ADDR_HIGH_VIRT_SHIFT 8
219 #define MVPP2_BM_PHY_RLS_REG(pool) (0x6480 + ((pool) * 4))
220 #define MVPP2_BM_PHY_RLS_MC_BUFF_MASK BIT(0)
221 #define MVPP2_BM_PHY_RLS_PRIO_EN_MASK BIT(1)
222 #define MVPP2_BM_PHY_RLS_GRNTD_MASK BIT(2)
223 #define MVPP2_BM_VIRT_RLS_REG 0x64c0
224 #define MVPP22_BM_ADDR_HIGH_RLS_REG 0x64c4
225 #define MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK 0xff
226 #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK 0xff00
227 #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT 8
229 /* TX Scheduler registers */
230 #define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000
231 #define MVPP2_TXP_SCHED_Q_CMD_REG 0x8004
232 #define MVPP2_TXP_SCHED_ENQ_MASK 0xff
233 #define MVPP2_TXP_SCHED_DISQ_OFFSET 8
234 #define MVPP2_TXP_SCHED_CMD_1_REG 0x8010
235 #define MVPP2_TXP_SCHED_PERIOD_REG 0x8018
236 #define MVPP2_TXP_SCHED_MTU_REG 0x801c
237 #define MVPP2_TXP_MTU_MAX 0x7FFFF
238 #define MVPP2_TXP_SCHED_REFILL_REG 0x8020
239 #define MVPP2_TXP_REFILL_TOKENS_ALL_MASK 0x7ffff
240 #define MVPP2_TXP_REFILL_PERIOD_ALL_MASK 0x3ff00000
241 #define MVPP2_TXP_REFILL_PERIOD_MASK(v) ((v) << 20)
242 #define MVPP2_TXP_SCHED_TOKEN_SIZE_REG 0x8024
243 #define MVPP2_TXP_TOKEN_SIZE_MAX 0xffffffff
244 #define MVPP2_TXQ_SCHED_REFILL_REG(q) (0x8040 + ((q) << 2))
245 #define MVPP2_TXQ_REFILL_TOKENS_ALL_MASK 0x7ffff
246 #define MVPP2_TXQ_REFILL_PERIOD_ALL_MASK 0x3ff00000
247 #define MVPP2_TXQ_REFILL_PERIOD_MASK(v) ((v) << 20)
248 #define MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(q) (0x8060 + ((q) << 2))
249 #define MVPP2_TXQ_TOKEN_SIZE_MAX 0x7fffffff
250 #define MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(q) (0x8080 + ((q) << 2))
251 #define MVPP2_TXQ_TOKEN_CNTR_MAX 0xffffffff
253 /* TX general registers */
254 #define MVPP2_TX_SNOOP_REG 0x8800
255 #define MVPP2_TX_PORT_FLUSH_REG 0x8810
256 #define MVPP2_TX_PORT_FLUSH_MASK(port) (1 << (port))
259 #define MVPP2_SRC_ADDR_MIDDLE 0x24
260 #define MVPP2_SRC_ADDR_HIGH 0x28
261 #define MVPP2_PHY_AN_CFG0_REG 0x34
262 #define MVPP2_PHY_AN_STOP_SMI0_MASK BIT(7)
263 #define MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG 0x305c
264 #define MVPP2_EXT_GLOBAL_CTRL_DEFAULT 0x27
266 /* Per-port registers */
267 #define MVPP2_GMAC_CTRL_0_REG 0x0
268 #define MVPP2_GMAC_PORT_EN_MASK BIT(0)
269 #define MVPP2_GMAC_MAX_RX_SIZE_OFFS 2
270 #define MVPP2_GMAC_MAX_RX_SIZE_MASK 0x7ffc
271 #define MVPP2_GMAC_MIB_CNTR_EN_MASK BIT(15)
272 #define MVPP2_GMAC_CTRL_1_REG 0x4
273 #define MVPP2_GMAC_PERIODIC_XON_EN_MASK BIT(1)
274 #define MVPP2_GMAC_GMII_LB_EN_MASK BIT(5)
275 #define MVPP2_GMAC_PCS_LB_EN_BIT 6
276 #define MVPP2_GMAC_PCS_LB_EN_MASK BIT(6)
277 #define MVPP2_GMAC_SA_LOW_OFFS 7
278 #define MVPP2_GMAC_CTRL_2_REG 0x8
279 #define MVPP2_GMAC_INBAND_AN_MASK BIT(0)
280 #define MVPP2_GMAC_PCS_ENABLE_MASK BIT(3)
281 #define MVPP2_GMAC_PORT_RGMII_MASK BIT(4)
282 #define MVPP2_GMAC_PORT_RESET_MASK BIT(6)
283 #define MVPP2_GMAC_AUTONEG_CONFIG 0xc
284 #define MVPP2_GMAC_FORCE_LINK_DOWN BIT(0)
285 #define MVPP2_GMAC_FORCE_LINK_PASS BIT(1)
286 #define MVPP2_GMAC_CONFIG_MII_SPEED BIT(5)
287 #define MVPP2_GMAC_CONFIG_GMII_SPEED BIT(6)
288 #define MVPP2_GMAC_AN_SPEED_EN BIT(7)
289 #define MVPP2_GMAC_FC_ADV_EN BIT(9)
290 #define MVPP2_GMAC_CONFIG_FULL_DUPLEX BIT(12)
291 #define MVPP2_GMAC_AN_DUPLEX_EN BIT(13)
292 #define MVPP2_GMAC_PORT_FIFO_CFG_1_REG 0x1c
293 #define MVPP2_GMAC_TX_FIFO_MIN_TH_OFFS 6
294 #define MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK 0x1fc0
295 #define MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v) (((v) << 6) & \
296 MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK)
298 #define MVPP2_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
300 /* Descriptor ring Macros */
301 #define MVPP2_QUEUE_NEXT_DESC(q, index) \
302 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
304 /* Various constants */
307 #define MVPP2_TXDONE_COAL_PKTS_THRESH 15
308 #define MVPP2_TXDONE_HRTIMER_PERIOD_NS 1000000UL
309 #define MVPP2_RX_COAL_PKTS 32
310 #define MVPP2_RX_COAL_USEC 100
312 /* The two bytes Marvell header. Either contains a special value used
313 * by Marvell switches when a specific hardware mode is enabled (not
314 * supported by this driver) or is filled automatically by zeroes on
315 * the RX side. Those two bytes being at the front of the Ethernet
316 * header, they allow to have the IP header aligned on a 4 bytes
317 * boundary automatically: the hardware skips those two bytes on its
320 #define MVPP2_MH_SIZE 2
321 #define MVPP2_ETH_TYPE_LEN 2
322 #define MVPP2_PPPOE_HDR_SIZE 8
323 #define MVPP2_VLAN_TAG_LEN 4
325 /* Lbtd 802.3 type */
326 #define MVPP2_IP_LBDT_TYPE 0xfffa
328 #define MVPP2_TX_CSUM_MAX_SIZE 9800
330 /* Timeout constants */
331 #define MVPP2_TX_DISABLE_TIMEOUT_MSEC 1000
332 #define MVPP2_TX_PENDING_TIMEOUT_MSEC 1000
334 #define MVPP2_TX_MTU_MAX 0x7ffff
336 /* Maximum number of T-CONTs of PON port */
337 #define MVPP2_MAX_TCONT 16
339 /* Maximum number of supported ports */
340 #define MVPP2_MAX_PORTS 4
342 /* Maximum number of TXQs used by single port */
343 #define MVPP2_MAX_TXQ 8
345 /* Maximum number of RXQs used by single port */
346 #define MVPP2_MAX_RXQ 8
348 /* Dfault number of RXQs in use */
349 #define MVPP2_DEFAULT_RXQ 4
351 /* Total number of RXQs available to all ports */
352 #define MVPP2_RXQ_TOTAL_NUM (MVPP2_MAX_PORTS * MVPP2_MAX_RXQ)
354 /* Max number of Rx descriptors */
355 #define MVPP2_MAX_RXD 128
357 /* Max number of Tx descriptors */
358 #define MVPP2_MAX_TXD 1024
360 /* Amount of Tx descriptors that can be reserved at once by CPU */
361 #define MVPP2_CPU_DESC_CHUNK 64
363 /* Max number of Tx descriptors in each aggregated queue */
364 #define MVPP2_AGGR_TXQ_SIZE 256
366 /* Descriptor aligned size */
367 #define MVPP2_DESC_ALIGNED_SIZE 32
369 /* Descriptor alignment mask */
370 #define MVPP2_TX_DESC_ALIGN (MVPP2_DESC_ALIGNED_SIZE - 1)
372 /* RX FIFO constants */
373 #define MVPP2_RX_FIFO_PORT_DATA_SIZE 0x2000
374 #define MVPP2_RX_FIFO_PORT_ATTR_SIZE 0x80
375 #define MVPP2_RX_FIFO_PORT_MIN_PKT 0x80
377 /* RX buffer constants */
378 #define MVPP2_SKB_SHINFO_SIZE \
379 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))
381 #define MVPP2_RX_PKT_SIZE(mtu) \
382 ALIGN((mtu) + MVPP2_MH_SIZE + MVPP2_VLAN_TAG_LEN + \
383 ETH_HLEN + ETH_FCS_LEN, cache_line_size())
385 #define MVPP2_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD)
386 #define MVPP2_RX_TOTAL_SIZE(buf_size) ((buf_size) + MVPP2_SKB_SHINFO_SIZE)
387 #define MVPP2_RX_MAX_PKT_SIZE(total_size) \
388 ((total_size) - NET_SKB_PAD - MVPP2_SKB_SHINFO_SIZE)
390 #define MVPP2_BIT_TO_BYTE(bit) ((bit) / 8)
392 /* IPv6 max L3 address size */
393 #define MVPP2_MAX_L3_ADDR_SIZE 16
396 #define MVPP2_F_LOOPBACK BIT(0)
398 /* Marvell tag types */
399 enum mvpp2_tag_type {
400 MVPP2_TAG_TYPE_NONE = 0,
401 MVPP2_TAG_TYPE_MH = 1,
402 MVPP2_TAG_TYPE_DSA = 2,
403 MVPP2_TAG_TYPE_EDSA = 3,
404 MVPP2_TAG_TYPE_VLAN = 4,
405 MVPP2_TAG_TYPE_LAST = 5
408 /* Parser constants */
409 #define MVPP2_PRS_TCAM_SRAM_SIZE 256
410 #define MVPP2_PRS_TCAM_WORDS 6
411 #define MVPP2_PRS_SRAM_WORDS 4
412 #define MVPP2_PRS_FLOW_ID_SIZE 64
413 #define MVPP2_PRS_FLOW_ID_MASK 0x3f
414 #define MVPP2_PRS_TCAM_ENTRY_INVALID 1
415 #define MVPP2_PRS_TCAM_DSA_TAGGED_BIT BIT(5)
416 #define MVPP2_PRS_IPV4_HEAD 0x40
417 #define MVPP2_PRS_IPV4_HEAD_MASK 0xf0
418 #define MVPP2_PRS_IPV4_MC 0xe0
419 #define MVPP2_PRS_IPV4_MC_MASK 0xf0
420 #define MVPP2_PRS_IPV4_BC_MASK 0xff
421 #define MVPP2_PRS_IPV4_IHL 0x5
422 #define MVPP2_PRS_IPV4_IHL_MASK 0xf
423 #define MVPP2_PRS_IPV6_MC 0xff
424 #define MVPP2_PRS_IPV6_MC_MASK 0xff
425 #define MVPP2_PRS_IPV6_HOP_MASK 0xff
426 #define MVPP2_PRS_TCAM_PROTO_MASK 0xff
427 #define MVPP2_PRS_TCAM_PROTO_MASK_L 0x3f
428 #define MVPP2_PRS_DBL_VLANS_MAX 100
431 * - lookup ID - 4 bits
433 * - additional information - 1 byte
434 * - header data - 8 bytes
435 * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(5)->(0).
437 #define MVPP2_PRS_AI_BITS 8
438 #define MVPP2_PRS_PORT_MASK 0xff
439 #define MVPP2_PRS_LU_MASK 0xf
440 #define MVPP2_PRS_TCAM_DATA_BYTE(offs) \
441 (((offs) - ((offs) % 2)) * 2 + ((offs) % 2))
442 #define MVPP2_PRS_TCAM_DATA_BYTE_EN(offs) \
443 (((offs) * 2) - ((offs) % 2) + 2)
444 #define MVPP2_PRS_TCAM_AI_BYTE 16
445 #define MVPP2_PRS_TCAM_PORT_BYTE 17
446 #define MVPP2_PRS_TCAM_LU_BYTE 20
447 #define MVPP2_PRS_TCAM_EN_OFFS(offs) ((offs) + 2)
448 #define MVPP2_PRS_TCAM_INV_WORD 5
449 /* Tcam entries ID */
450 #define MVPP2_PE_DROP_ALL 0
451 #define MVPP2_PE_FIRST_FREE_TID 1
452 #define MVPP2_PE_LAST_FREE_TID (MVPP2_PRS_TCAM_SRAM_SIZE - 31)
453 #define MVPP2_PE_IP6_EXT_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 30)
454 #define MVPP2_PE_MAC_MC_IP6 (MVPP2_PRS_TCAM_SRAM_SIZE - 29)
455 #define MVPP2_PE_IP6_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 28)
456 #define MVPP2_PE_IP4_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 27)
457 #define MVPP2_PE_LAST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 26)
458 #define MVPP2_PE_FIRST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 19)
459 #define MVPP2_PE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 18)
460 #define MVPP2_PE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 17)
461 #define MVPP2_PE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 16)
462 #define MVPP2_PE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 15)
463 #define MVPP2_PE_ETYPE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 14)
464 #define MVPP2_PE_ETYPE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 13)
465 #define MVPP2_PE_ETYPE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 12)
466 #define MVPP2_PE_ETYPE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 11)
467 #define MVPP2_PE_MH_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 10)
468 #define MVPP2_PE_DSA_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 9)
469 #define MVPP2_PE_IP6_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 8)
470 #define MVPP2_PE_IP4_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 7)
471 #define MVPP2_PE_ETH_TYPE_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 6)
472 #define MVPP2_PE_VLAN_DBL (MVPP2_PRS_TCAM_SRAM_SIZE - 5)
473 #define MVPP2_PE_VLAN_NONE (MVPP2_PRS_TCAM_SRAM_SIZE - 4)
474 #define MVPP2_PE_MAC_MC_ALL (MVPP2_PRS_TCAM_SRAM_SIZE - 3)
475 #define MVPP2_PE_MAC_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 2)
476 #define MVPP2_PE_MAC_NON_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 1)
479 * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(3)->(0).
481 #define MVPP2_PRS_SRAM_RI_OFFS 0
482 #define MVPP2_PRS_SRAM_RI_WORD 0
483 #define MVPP2_PRS_SRAM_RI_CTRL_OFFS 32
484 #define MVPP2_PRS_SRAM_RI_CTRL_WORD 1
485 #define MVPP2_PRS_SRAM_RI_CTRL_BITS 32
486 #define MVPP2_PRS_SRAM_SHIFT_OFFS 64
487 #define MVPP2_PRS_SRAM_SHIFT_SIGN_BIT 72
488 #define MVPP2_PRS_SRAM_UDF_OFFS 73
489 #define MVPP2_PRS_SRAM_UDF_BITS 8
490 #define MVPP2_PRS_SRAM_UDF_MASK 0xff
491 #define MVPP2_PRS_SRAM_UDF_SIGN_BIT 81
492 #define MVPP2_PRS_SRAM_UDF_TYPE_OFFS 82
493 #define MVPP2_PRS_SRAM_UDF_TYPE_MASK 0x7
494 #define MVPP2_PRS_SRAM_UDF_TYPE_L3 1
495 #define MVPP2_PRS_SRAM_UDF_TYPE_L4 4
496 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS 85
497 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK 0x3
498 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD 1
499 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP4_ADD 2
500 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP6_ADD 3
501 #define MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS 87
502 #define MVPP2_PRS_SRAM_OP_SEL_UDF_BITS 2
503 #define MVPP2_PRS_SRAM_OP_SEL_UDF_MASK 0x3
504 #define MVPP2_PRS_SRAM_OP_SEL_UDF_ADD 0
505 #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP4_ADD 2
506 #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP6_ADD 3
507 #define MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS 89
508 #define MVPP2_PRS_SRAM_AI_OFFS 90
509 #define MVPP2_PRS_SRAM_AI_CTRL_OFFS 98
510 #define MVPP2_PRS_SRAM_AI_CTRL_BITS 8
511 #define MVPP2_PRS_SRAM_AI_MASK 0xff
512 #define MVPP2_PRS_SRAM_NEXT_LU_OFFS 106
513 #define MVPP2_PRS_SRAM_NEXT_LU_MASK 0xf
514 #define MVPP2_PRS_SRAM_LU_DONE_BIT 110
515 #define MVPP2_PRS_SRAM_LU_GEN_BIT 111
517 /* Sram result info bits assignment */
518 #define MVPP2_PRS_RI_MAC_ME_MASK 0x1
519 #define MVPP2_PRS_RI_DSA_MASK 0x2
520 #define MVPP2_PRS_RI_VLAN_MASK (BIT(2) | BIT(3))
521 #define MVPP2_PRS_RI_VLAN_NONE 0x0
522 #define MVPP2_PRS_RI_VLAN_SINGLE BIT(2)
523 #define MVPP2_PRS_RI_VLAN_DOUBLE BIT(3)
524 #define MVPP2_PRS_RI_VLAN_TRIPLE (BIT(2) | BIT(3))
525 #define MVPP2_PRS_RI_CPU_CODE_MASK 0x70
526 #define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4)
527 #define MVPP2_PRS_RI_L2_CAST_MASK (BIT(9) | BIT(10))
528 #define MVPP2_PRS_RI_L2_UCAST 0x0
529 #define MVPP2_PRS_RI_L2_MCAST BIT(9)
530 #define MVPP2_PRS_RI_L2_BCAST BIT(10)
531 #define MVPP2_PRS_RI_PPPOE_MASK 0x800
532 #define MVPP2_PRS_RI_L3_PROTO_MASK (BIT(12) | BIT(13) | BIT(14))
533 #define MVPP2_PRS_RI_L3_UN 0x0
534 #define MVPP2_PRS_RI_L3_IP4 BIT(12)
535 #define MVPP2_PRS_RI_L3_IP4_OPT BIT(13)
536 #define MVPP2_PRS_RI_L3_IP4_OTHER (BIT(12) | BIT(13))
537 #define MVPP2_PRS_RI_L3_IP6 BIT(14)
538 #define MVPP2_PRS_RI_L3_IP6_EXT (BIT(12) | BIT(14))
539 #define MVPP2_PRS_RI_L3_ARP (BIT(13) | BIT(14))
540 #define MVPP2_PRS_RI_L3_ADDR_MASK (BIT(15) | BIT(16))
541 #define MVPP2_PRS_RI_L3_UCAST 0x0
542 #define MVPP2_PRS_RI_L3_MCAST BIT(15)
543 #define MVPP2_PRS_RI_L3_BCAST (BIT(15) | BIT(16))
544 #define MVPP2_PRS_RI_IP_FRAG_MASK 0x20000
545 #define MVPP2_PRS_RI_UDF3_MASK 0x300000
546 #define MVPP2_PRS_RI_UDF3_RX_SPECIAL BIT(21)
547 #define MVPP2_PRS_RI_L4_PROTO_MASK 0x1c00000
548 #define MVPP2_PRS_RI_L4_TCP BIT(22)
549 #define MVPP2_PRS_RI_L4_UDP BIT(23)
550 #define MVPP2_PRS_RI_L4_OTHER (BIT(22) | BIT(23))
551 #define MVPP2_PRS_RI_UDF7_MASK 0x60000000
552 #define MVPP2_PRS_RI_UDF7_IP6_LITE BIT(29)
553 #define MVPP2_PRS_RI_DROP_MASK 0x80000000
555 /* Sram additional info bits assignment */
556 #define MVPP2_PRS_IPV4_DIP_AI_BIT BIT(0)
557 #define MVPP2_PRS_IPV6_NO_EXT_AI_BIT BIT(0)
558 #define MVPP2_PRS_IPV6_EXT_AI_BIT BIT(1)
559 #define MVPP2_PRS_IPV6_EXT_AH_AI_BIT BIT(2)
560 #define MVPP2_PRS_IPV6_EXT_AH_LEN_AI_BIT BIT(3)
561 #define MVPP2_PRS_IPV6_EXT_AH_L4_AI_BIT BIT(4)
562 #define MVPP2_PRS_SINGLE_VLAN_AI 0
563 #define MVPP2_PRS_DBL_VLAN_AI_BIT BIT(7)
566 #define MVPP2_PRS_TAGGED true
567 #define MVPP2_PRS_UNTAGGED false
568 #define MVPP2_PRS_EDSA true
569 #define MVPP2_PRS_DSA false
571 /* MAC entries, shadow udf */
573 MVPP2_PRS_UDF_MAC_DEF,
574 MVPP2_PRS_UDF_MAC_RANGE,
575 MVPP2_PRS_UDF_L2_DEF,
576 MVPP2_PRS_UDF_L2_DEF_COPY,
577 MVPP2_PRS_UDF_L2_USER,
581 enum mvpp2_prs_lookup {
595 enum mvpp2_prs_l3_cast {
596 MVPP2_PRS_L3_UNI_CAST,
597 MVPP2_PRS_L3_MULTI_CAST,
598 MVPP2_PRS_L3_BROAD_CAST
601 /* Classifier constants */
602 #define MVPP2_CLS_FLOWS_TBL_SIZE 512
603 #define MVPP2_CLS_FLOWS_TBL_DATA_WORDS 3
604 #define MVPP2_CLS_LKP_TBL_SIZE 64
607 #define MVPP2_BM_POOLS_NUM 8
608 #define MVPP2_BM_LONG_BUF_NUM 1024
609 #define MVPP2_BM_SHORT_BUF_NUM 2048
610 #define MVPP2_BM_POOL_SIZE_MAX (16*1024 - MVPP2_BM_POOL_PTR_ALIGN/4)
611 #define MVPP2_BM_POOL_PTR_ALIGN 128
612 #define MVPP2_BM_SWF_LONG_POOL(port) ((port > 2) ? 2 : port)
613 #define MVPP2_BM_SWF_SHORT_POOL 3
615 /* BM cookie (32 bits) definition */
616 #define MVPP2_BM_COOKIE_POOL_OFFS 8
617 #define MVPP2_BM_COOKIE_CPU_OFFS 24
619 /* BM short pool packet size
620 * These value assure that for SWF the total number
621 * of bytes allocated for each buffer will be 512
623 #define MVPP2_BM_SHORT_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(512)
633 /* Shared Packet Processor resources */
635 /* Shared registers' base addresses */
637 void __iomem *lms_base;
643 /* List of pointers to port structures */
644 struct mvpp2_port **port_list;
646 /* Aggregated TXQs */
647 struct mvpp2_tx_queue *aggr_txqs;
650 struct mvpp2_bm_pool *bm_pools;
652 /* PRS shadow table */
653 struct mvpp2_prs_shadow *prs_shadow;
654 /* PRS auxiliary table for double vlan entries control */
655 bool *prs_double_vlans;
661 enum { MVPP21, MVPP22 } hw_version;
664 struct mvpp2_pcpu_stats {
665 struct u64_stats_sync syncp;
672 /* Per-CPU port control */
673 struct mvpp2_port_pcpu {
674 struct hrtimer tx_done_timer;
675 bool timer_scheduled;
676 /* Tasklet for egress finalization */
677 struct tasklet_struct tx_done_tasklet;
687 /* Per-port registers' base address */
690 struct mvpp2_rx_queue **rxqs;
691 struct mvpp2_tx_queue **txqs;
692 struct net_device *dev;
696 u32 pending_cause_rx;
697 struct napi_struct napi;
699 /* Per-CPU port control */
700 struct mvpp2_port_pcpu __percpu *pcpu;
707 struct mvpp2_pcpu_stats __percpu *stats;
709 phy_interface_t phy_interface;
710 struct device_node *phy_node;
715 struct mvpp2_bm_pool *pool_long;
716 struct mvpp2_bm_pool *pool_short;
718 /* Index of first port's physical RXQ */
722 /* The mvpp2_tx_desc and mvpp2_rx_desc structures describe the
723 * layout of the transmit and reception DMA descriptors, and their
724 * layout is therefore defined by the hardware design
727 #define MVPP2_TXD_L3_OFF_SHIFT 0
728 #define MVPP2_TXD_IP_HLEN_SHIFT 8
729 #define MVPP2_TXD_L4_CSUM_FRAG BIT(13)
730 #define MVPP2_TXD_L4_CSUM_NOT BIT(14)
731 #define MVPP2_TXD_IP_CSUM_DISABLE BIT(15)
732 #define MVPP2_TXD_PADDING_DISABLE BIT(23)
733 #define MVPP2_TXD_L4_UDP BIT(24)
734 #define MVPP2_TXD_L3_IP6 BIT(26)
735 #define MVPP2_TXD_L_DESC BIT(28)
736 #define MVPP2_TXD_F_DESC BIT(29)
738 #define MVPP2_RXD_ERR_SUMMARY BIT(15)
739 #define MVPP2_RXD_ERR_CODE_MASK (BIT(13) | BIT(14))
740 #define MVPP2_RXD_ERR_CRC 0x0
741 #define MVPP2_RXD_ERR_OVERRUN BIT(13)
742 #define MVPP2_RXD_ERR_RESOURCE (BIT(13) | BIT(14))
743 #define MVPP2_RXD_BM_POOL_ID_OFFS 16
744 #define MVPP2_RXD_BM_POOL_ID_MASK (BIT(16) | BIT(17) | BIT(18))
745 #define MVPP2_RXD_HWF_SYNC BIT(21)
746 #define MVPP2_RXD_L4_CSUM_OK BIT(22)
747 #define MVPP2_RXD_IP4_HEADER_ERR BIT(24)
748 #define MVPP2_RXD_L4_TCP BIT(25)
749 #define MVPP2_RXD_L4_UDP BIT(26)
750 #define MVPP2_RXD_L3_IP4 BIT(28)
751 #define MVPP2_RXD_L3_IP6 BIT(30)
752 #define MVPP2_RXD_BUF_HDR BIT(31)
754 /* HW TX descriptor for PPv2.1 */
755 struct mvpp21_tx_desc {
756 u32 command; /* Options used by HW for packet transmitting.*/
757 u8 packet_offset; /* the offset from the buffer beginning */
758 u8 phys_txq; /* destination queue ID */
759 u16 data_size; /* data size of transmitted packet in bytes */
760 u32 buf_dma_addr; /* physical addr of transmitted buffer */
761 u32 buf_cookie; /* cookie for access to TX buffer in tx path */
762 u32 reserved1[3]; /* hw_cmd (for future use, BM, PON, PNC) */
763 u32 reserved2; /* reserved (for future use) */
766 /* HW RX descriptor for PPv2.1 */
767 struct mvpp21_rx_desc {
768 u32 status; /* info about received packet */
769 u16 reserved1; /* parser_info (for future use, PnC) */
770 u16 data_size; /* size of received packet in bytes */
771 u32 buf_dma_addr; /* physical address of the buffer */
772 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
773 u16 reserved2; /* gem_port_id (for future use, PON) */
774 u16 reserved3; /* csum_l4 (for future use, PnC) */
775 u8 reserved4; /* bm_qset (for future use, BM) */
777 u16 reserved6; /* classify_info (for future use, PnC) */
778 u32 reserved7; /* flow_id (for future use, PnC) */
782 /* HW TX descriptor for PPv2.2 */
783 struct mvpp22_tx_desc {
789 u64 buf_dma_addr_ptp;
793 /* HW RX descriptor for PPv2.2 */
794 struct mvpp22_rx_desc {
800 u64 buf_dma_addr_key_hash;
804 /* Opaque type used by the driver to manipulate the HW TX and RX
807 struct mvpp2_tx_desc {
809 struct mvpp21_tx_desc pp21;
810 struct mvpp22_tx_desc pp22;
814 struct mvpp2_rx_desc {
816 struct mvpp21_rx_desc pp21;
817 struct mvpp22_rx_desc pp22;
821 struct mvpp2_txq_pcpu_buf {
822 /* Transmitted SKB */
825 /* Physical address of transmitted buffer */
828 /* Size transmitted */
832 /* Per-CPU Tx queue control */
833 struct mvpp2_txq_pcpu {
836 /* Number of Tx DMA descriptors in the descriptor ring */
839 /* Number of currently used Tx DMA descriptor in the
844 /* Number of Tx DMA descriptors reserved for each CPU */
847 /* Infos about transmitted buffers */
848 struct mvpp2_txq_pcpu_buf *buffs;
850 /* Index of last TX DMA descriptor that was inserted */
853 /* Index of the TX DMA descriptor to be cleaned up */
857 struct mvpp2_tx_queue {
858 /* Physical number of this Tx queue */
861 /* Logical number of this Tx queue */
864 /* Number of Tx DMA descriptors in the descriptor ring */
867 /* Number of currently used Tx DMA descriptor in the descriptor ring */
870 /* Per-CPU control of physical Tx queues */
871 struct mvpp2_txq_pcpu __percpu *pcpu;
875 /* Virtual address of thex Tx DMA descriptors array */
876 struct mvpp2_tx_desc *descs;
878 /* DMA address of the Tx DMA descriptors array */
879 dma_addr_t descs_dma;
881 /* Index of the last Tx DMA descriptor */
884 /* Index of the next Tx DMA descriptor to process */
885 int next_desc_to_proc;
888 struct mvpp2_rx_queue {
889 /* RX queue number, in the range 0-31 for physical RXQs */
892 /* Num of rx descriptors in the rx descriptor ring */
898 /* Virtual address of the RX DMA descriptors array */
899 struct mvpp2_rx_desc *descs;
901 /* DMA address of the RX DMA descriptors array */
902 dma_addr_t descs_dma;
904 /* Index of the last RX DMA descriptor */
907 /* Index of the next RX DMA descriptor to process */
908 int next_desc_to_proc;
910 /* ID of port to which physical RXQ is mapped */
913 /* Port's logic RXQ number to which physical RXQ is mapped */
917 union mvpp2_prs_tcam_entry {
918 u32 word[MVPP2_PRS_TCAM_WORDS];
919 u8 byte[MVPP2_PRS_TCAM_WORDS * 4];
922 union mvpp2_prs_sram_entry {
923 u32 word[MVPP2_PRS_SRAM_WORDS];
924 u8 byte[MVPP2_PRS_SRAM_WORDS * 4];
927 struct mvpp2_prs_entry {
929 union mvpp2_prs_tcam_entry tcam;
930 union mvpp2_prs_sram_entry sram;
933 struct mvpp2_prs_shadow {
940 /* User defined offset */
948 struct mvpp2_cls_flow_entry {
950 u32 data[MVPP2_CLS_FLOWS_TBL_DATA_WORDS];
953 struct mvpp2_cls_lookup_entry {
959 struct mvpp2_bm_pool {
960 /* Pool number in the range 0-7 */
962 enum mvpp2_bm_type type;
964 /* Buffer Pointers Pool External (BPPE) size */
966 /* BPPE size in bytes */
968 /* Number of buffers for this pool */
970 /* Pool buffer size */
976 /* BPPE virtual base address */
978 /* BPPE DMA base address */
981 /* Ports using BM pool */
985 /* Static declaractions */
987 /* Number of RXQs used by single port */
988 static int rxq_number = MVPP2_DEFAULT_RXQ;
989 /* Number of TXQs used by single port */
990 static int txq_number = MVPP2_MAX_TXQ;
992 #define MVPP2_DRIVER_NAME "mvpp2"
993 #define MVPP2_DRIVER_VERSION "1.0"
995 /* Utility/helper methods */
997 static void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data)
999 writel(data, priv->base + offset);
1002 static u32 mvpp2_read(struct mvpp2 *priv, u32 offset)
1004 return readl(priv->base + offset);
1007 static dma_addr_t mvpp2_txdesc_dma_addr_get(struct mvpp2_port *port,
1008 struct mvpp2_tx_desc *tx_desc)
1010 if (port->priv->hw_version == MVPP21)
1011 return tx_desc->pp21.buf_dma_addr;
1013 return tx_desc->pp22.buf_dma_addr_ptp & GENMASK_ULL(40, 0);
1016 static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port,
1017 struct mvpp2_tx_desc *tx_desc,
1018 dma_addr_t dma_addr)
1020 if (port->priv->hw_version == MVPP21) {
1021 tx_desc->pp21.buf_dma_addr = dma_addr;
1023 u64 val = (u64)dma_addr;
1025 tx_desc->pp22.buf_dma_addr_ptp &= ~GENMASK_ULL(40, 0);
1026 tx_desc->pp22.buf_dma_addr_ptp |= val;
1030 static size_t mvpp2_txdesc_size_get(struct mvpp2_port *port,
1031 struct mvpp2_tx_desc *tx_desc)
1033 if (port->priv->hw_version == MVPP21)
1034 return tx_desc->pp21.data_size;
1036 return tx_desc->pp22.data_size;
1039 static void mvpp2_txdesc_size_set(struct mvpp2_port *port,
1040 struct mvpp2_tx_desc *tx_desc,
1043 if (port->priv->hw_version == MVPP21)
1044 tx_desc->pp21.data_size = size;
1046 tx_desc->pp22.data_size = size;
1049 static void mvpp2_txdesc_txq_set(struct mvpp2_port *port,
1050 struct mvpp2_tx_desc *tx_desc,
1053 if (port->priv->hw_version == MVPP21)
1054 tx_desc->pp21.phys_txq = txq;
1056 tx_desc->pp22.phys_txq = txq;
1059 static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port,
1060 struct mvpp2_tx_desc *tx_desc,
1061 unsigned int command)
1063 if (port->priv->hw_version == MVPP21)
1064 tx_desc->pp21.command = command;
1066 tx_desc->pp22.command = command;
1069 static void mvpp2_txdesc_offset_set(struct mvpp2_port *port,
1070 struct mvpp2_tx_desc *tx_desc,
1071 unsigned int offset)
1073 if (port->priv->hw_version == MVPP21)
1074 tx_desc->pp21.packet_offset = offset;
1076 tx_desc->pp22.packet_offset = offset;
1079 static unsigned int mvpp2_txdesc_offset_get(struct mvpp2_port *port,
1080 struct mvpp2_tx_desc *tx_desc)
1082 if (port->priv->hw_version == MVPP21)
1083 return tx_desc->pp21.packet_offset;
1085 return tx_desc->pp22.packet_offset;
1088 static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port,
1089 struct mvpp2_rx_desc *rx_desc)
1091 if (port->priv->hw_version == MVPP21)
1092 return rx_desc->pp21.buf_dma_addr;
1094 return rx_desc->pp22.buf_dma_addr_key_hash & GENMASK_ULL(40, 0);
1097 static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port,
1098 struct mvpp2_rx_desc *rx_desc)
1100 if (port->priv->hw_version == MVPP21)
1101 return rx_desc->pp21.buf_cookie;
1103 return rx_desc->pp22.buf_cookie_misc & GENMASK_ULL(40, 0);
1106 static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port,
1107 struct mvpp2_rx_desc *rx_desc)
1109 if (port->priv->hw_version == MVPP21)
1110 return rx_desc->pp21.data_size;
1112 return rx_desc->pp22.data_size;
1115 static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port,
1116 struct mvpp2_rx_desc *rx_desc)
1118 if (port->priv->hw_version == MVPP21)
1119 return rx_desc->pp21.status;
1121 return rx_desc->pp22.status;
1124 static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu)
1126 txq_pcpu->txq_get_index++;
1127 if (txq_pcpu->txq_get_index == txq_pcpu->size)
1128 txq_pcpu->txq_get_index = 0;
1131 static void mvpp2_txq_inc_put(struct mvpp2_port *port,
1132 struct mvpp2_txq_pcpu *txq_pcpu,
1133 struct sk_buff *skb,
1134 struct mvpp2_tx_desc *tx_desc)
1136 struct mvpp2_txq_pcpu_buf *tx_buf =
1137 txq_pcpu->buffs + txq_pcpu->txq_put_index;
1139 tx_buf->size = mvpp2_txdesc_size_get(port, tx_desc);
1140 tx_buf->dma = mvpp2_txdesc_dma_addr_get(port, tx_desc) +
1141 mvpp2_txdesc_offset_get(port, tx_desc);
1142 txq_pcpu->txq_put_index++;
1143 if (txq_pcpu->txq_put_index == txq_pcpu->size)
1144 txq_pcpu->txq_put_index = 0;
1147 /* Get number of physical egress port */
1148 static inline int mvpp2_egress_port(struct mvpp2_port *port)
1150 return MVPP2_MAX_TCONT + port->id;
1153 /* Get number of physical TXQ */
1154 static inline int mvpp2_txq_phys(int port, int txq)
1156 return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq;
1159 /* Parser configuration routines */
1161 /* Update parser tcam and sram hw entries */
1162 static int mvpp2_prs_hw_write(struct mvpp2 *priv, struct mvpp2_prs_entry *pe)
1166 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1)
1169 /* Clear entry invalidation bit */
1170 pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] &= ~MVPP2_PRS_TCAM_INV_MASK;
1172 /* Write tcam index - indirect access */
1173 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index);
1174 for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
1175 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), pe->tcam.word[i]);
1177 /* Write sram index - indirect access */
1178 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index);
1179 for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
1180 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]);
1185 /* Read tcam entry from hw */
1186 static int mvpp2_prs_hw_read(struct mvpp2 *priv, struct mvpp2_prs_entry *pe)
1190 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1)
1193 /* Write tcam index - indirect access */
1194 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index);
1196 pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] = mvpp2_read(priv,
1197 MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD));
1198 if (pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] & MVPP2_PRS_TCAM_INV_MASK)
1199 return MVPP2_PRS_TCAM_ENTRY_INVALID;
1201 for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
1202 pe->tcam.word[i] = mvpp2_read(priv, MVPP2_PRS_TCAM_DATA_REG(i));
1204 /* Write sram index - indirect access */
1205 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index);
1206 for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
1207 pe->sram.word[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i));
1212 /* Invalidate tcam hw entry */
1213 static void mvpp2_prs_hw_inv(struct mvpp2 *priv, int index)
1215 /* Write index - indirect access */
1216 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index);
1217 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD),
1218 MVPP2_PRS_TCAM_INV_MASK);
1221 /* Enable shadow table entry and set its lookup ID */
1222 static void mvpp2_prs_shadow_set(struct mvpp2 *priv, int index, int lu)
1224 priv->prs_shadow[index].valid = true;
1225 priv->prs_shadow[index].lu = lu;
1228 /* Update ri fields in shadow table entry */
1229 static void mvpp2_prs_shadow_ri_set(struct mvpp2 *priv, int index,
1230 unsigned int ri, unsigned int ri_mask)
1232 priv->prs_shadow[index].ri_mask = ri_mask;
1233 priv->prs_shadow[index].ri = ri;
1236 /* Update lookup field in tcam sw entry */
1237 static void mvpp2_prs_tcam_lu_set(struct mvpp2_prs_entry *pe, unsigned int lu)
1239 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_LU_BYTE);
1241 pe->tcam.byte[MVPP2_PRS_TCAM_LU_BYTE] = lu;
1242 pe->tcam.byte[enable_off] = MVPP2_PRS_LU_MASK;
1245 /* Update mask for single port in tcam sw entry */
1246 static void mvpp2_prs_tcam_port_set(struct mvpp2_prs_entry *pe,
1247 unsigned int port, bool add)
1249 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
1252 pe->tcam.byte[enable_off] &= ~(1 << port);
1254 pe->tcam.byte[enable_off] |= 1 << port;
1257 /* Update port map in tcam sw entry */
1258 static void mvpp2_prs_tcam_port_map_set(struct mvpp2_prs_entry *pe,
1261 unsigned char port_mask = MVPP2_PRS_PORT_MASK;
1262 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
1264 pe->tcam.byte[MVPP2_PRS_TCAM_PORT_BYTE] = 0;
1265 pe->tcam.byte[enable_off] &= ~port_mask;
1266 pe->tcam.byte[enable_off] |= ~ports & MVPP2_PRS_PORT_MASK;
1269 /* Obtain port map from tcam sw entry */
1270 static unsigned int mvpp2_prs_tcam_port_map_get(struct mvpp2_prs_entry *pe)
1272 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
1274 return ~(pe->tcam.byte[enable_off]) & MVPP2_PRS_PORT_MASK;
1277 /* Set byte of data and its enable bits in tcam sw entry */
1278 static void mvpp2_prs_tcam_data_byte_set(struct mvpp2_prs_entry *pe,
1279 unsigned int offs, unsigned char byte,
1280 unsigned char enable)
1282 pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)] = byte;
1283 pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)] = enable;
1286 /* Get byte of data and its enable bits from tcam sw entry */
1287 static void mvpp2_prs_tcam_data_byte_get(struct mvpp2_prs_entry *pe,
1288 unsigned int offs, unsigned char *byte,
1289 unsigned char *enable)
1291 *byte = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)];
1292 *enable = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)];
1295 /* Compare tcam data bytes with a pattern */
1296 static bool mvpp2_prs_tcam_data_cmp(struct mvpp2_prs_entry *pe, int offs,
1299 int off = MVPP2_PRS_TCAM_DATA_BYTE(offs);
1302 tcam_data = (8 << pe->tcam.byte[off + 1]) | pe->tcam.byte[off];
1303 if (tcam_data != data)
1308 /* Update ai bits in tcam sw entry */
1309 static void mvpp2_prs_tcam_ai_update(struct mvpp2_prs_entry *pe,
1310 unsigned int bits, unsigned int enable)
1312 int i, ai_idx = MVPP2_PRS_TCAM_AI_BYTE;
1314 for (i = 0; i < MVPP2_PRS_AI_BITS; i++) {
1316 if (!(enable & BIT(i)))
1320 pe->tcam.byte[ai_idx] |= 1 << i;
1322 pe->tcam.byte[ai_idx] &= ~(1 << i);
1325 pe->tcam.byte[MVPP2_PRS_TCAM_EN_OFFS(ai_idx)] |= enable;
1328 /* Get ai bits from tcam sw entry */
1329 static int mvpp2_prs_tcam_ai_get(struct mvpp2_prs_entry *pe)
1331 return pe->tcam.byte[MVPP2_PRS_TCAM_AI_BYTE];
1334 /* Set ethertype in tcam sw entry */
1335 static void mvpp2_prs_match_etype(struct mvpp2_prs_entry *pe, int offset,
1336 unsigned short ethertype)
1338 mvpp2_prs_tcam_data_byte_set(pe, offset + 0, ethertype >> 8, 0xff);
1339 mvpp2_prs_tcam_data_byte_set(pe, offset + 1, ethertype & 0xff, 0xff);
1342 /* Set bits in sram sw entry */
1343 static void mvpp2_prs_sram_bits_set(struct mvpp2_prs_entry *pe, int bit_num,
1346 pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] |= (val << (bit_num % 8));
1349 /* Clear bits in sram sw entry */
1350 static void mvpp2_prs_sram_bits_clear(struct mvpp2_prs_entry *pe, int bit_num,
1353 pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] &= ~(val << (bit_num % 8));
1356 /* Update ri bits in sram sw entry */
1357 static void mvpp2_prs_sram_ri_update(struct mvpp2_prs_entry *pe,
1358 unsigned int bits, unsigned int mask)
1362 for (i = 0; i < MVPP2_PRS_SRAM_RI_CTRL_BITS; i++) {
1363 int ri_off = MVPP2_PRS_SRAM_RI_OFFS;
1365 if (!(mask & BIT(i)))
1369 mvpp2_prs_sram_bits_set(pe, ri_off + i, 1);
1371 mvpp2_prs_sram_bits_clear(pe, ri_off + i, 1);
1373 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_RI_CTRL_OFFS + i, 1);
1377 /* Obtain ri bits from sram sw entry */
1378 static int mvpp2_prs_sram_ri_get(struct mvpp2_prs_entry *pe)
1380 return pe->sram.word[MVPP2_PRS_SRAM_RI_WORD];
1383 /* Update ai bits in sram sw entry */
1384 static void mvpp2_prs_sram_ai_update(struct mvpp2_prs_entry *pe,
1385 unsigned int bits, unsigned int mask)
1388 int ai_off = MVPP2_PRS_SRAM_AI_OFFS;
1390 for (i = 0; i < MVPP2_PRS_SRAM_AI_CTRL_BITS; i++) {
1392 if (!(mask & BIT(i)))
1396 mvpp2_prs_sram_bits_set(pe, ai_off + i, 1);
1398 mvpp2_prs_sram_bits_clear(pe, ai_off + i, 1);
1400 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_AI_CTRL_OFFS + i, 1);
1404 /* Read ai bits from sram sw entry */
1405 static int mvpp2_prs_sram_ai_get(struct mvpp2_prs_entry *pe)
1408 int ai_off = MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_AI_OFFS);
1409 int ai_en_off = ai_off + 1;
1410 int ai_shift = MVPP2_PRS_SRAM_AI_OFFS % 8;
1412 bits = (pe->sram.byte[ai_off] >> ai_shift) |
1413 (pe->sram.byte[ai_en_off] << (8 - ai_shift));
1418 /* In sram sw entry set lookup ID field of the tcam key to be used in the next
1421 static void mvpp2_prs_sram_next_lu_set(struct mvpp2_prs_entry *pe,
1424 int sram_next_off = MVPP2_PRS_SRAM_NEXT_LU_OFFS;
1426 mvpp2_prs_sram_bits_clear(pe, sram_next_off,
1427 MVPP2_PRS_SRAM_NEXT_LU_MASK);
1428 mvpp2_prs_sram_bits_set(pe, sram_next_off, lu);
1431 /* In the sram sw entry set sign and value of the next lookup offset
1432 * and the offset value generated to the classifier
1434 static void mvpp2_prs_sram_shift_set(struct mvpp2_prs_entry *pe, int shift,
1439 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1);
1442 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1);
1446 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_SHIFT_OFFS)] =
1447 (unsigned char)shift;
1449 /* Reset and set operation */
1450 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS,
1451 MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK);
1452 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS, op);
1454 /* Set base offset as current */
1455 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1);
1458 /* In the sram sw entry set sign and value of the user defined offset
1459 * generated to the classifier
1461 static void mvpp2_prs_sram_offset_set(struct mvpp2_prs_entry *pe,
1462 unsigned int type, int offset,
1467 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1);
1468 offset = 0 - offset;
1470 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1);
1474 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_OFFS,
1475 MVPP2_PRS_SRAM_UDF_MASK);
1476 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_OFFS, offset);
1477 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS +
1478 MVPP2_PRS_SRAM_UDF_BITS)] &=
1479 ~(MVPP2_PRS_SRAM_UDF_MASK >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8)));
1480 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS +
1481 MVPP2_PRS_SRAM_UDF_BITS)] |=
1482 (offset >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8)));
1484 /* Set offset type */
1485 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS,
1486 MVPP2_PRS_SRAM_UDF_TYPE_MASK);
1487 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS, type);
1489 /* Set offset operation */
1490 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS,
1491 MVPP2_PRS_SRAM_OP_SEL_UDF_MASK);
1492 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS, op);
1494 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS +
1495 MVPP2_PRS_SRAM_OP_SEL_UDF_BITS)] &=
1496 ~(MVPP2_PRS_SRAM_OP_SEL_UDF_MASK >>
1497 (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8)));
1499 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS +
1500 MVPP2_PRS_SRAM_OP_SEL_UDF_BITS)] |=
1501 (op >> (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8)));
1503 /* Set base offset as current */
1504 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1);
1507 /* Find parser flow entry */
1508 static struct mvpp2_prs_entry *mvpp2_prs_flow_find(struct mvpp2 *priv, int flow)
1510 struct mvpp2_prs_entry *pe;
1513 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
1516 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS);
1518 /* Go through the all entires with MVPP2_PRS_LU_FLOWS */
1519 for (tid = MVPP2_PRS_TCAM_SRAM_SIZE - 1; tid >= 0; tid--) {
1522 if (!priv->prs_shadow[tid].valid ||
1523 priv->prs_shadow[tid].lu != MVPP2_PRS_LU_FLOWS)
1527 mvpp2_prs_hw_read(priv, pe);
1528 bits = mvpp2_prs_sram_ai_get(pe);
1530 /* Sram store classification lookup ID in AI bits [5:0] */
1531 if ((bits & MVPP2_PRS_FLOW_ID_MASK) == flow)
1539 /* Return first free tcam index, seeking from start to end */
1540 static int mvpp2_prs_tcam_first_free(struct mvpp2 *priv, unsigned char start,
1548 if (end >= MVPP2_PRS_TCAM_SRAM_SIZE)
1549 end = MVPP2_PRS_TCAM_SRAM_SIZE - 1;
1551 for (tid = start; tid <= end; tid++) {
1552 if (!priv->prs_shadow[tid].valid)
1559 /* Enable/disable dropping all mac da's */
1560 static void mvpp2_prs_mac_drop_all_set(struct mvpp2 *priv, int port, bool add)
1562 struct mvpp2_prs_entry pe;
1564 if (priv->prs_shadow[MVPP2_PE_DROP_ALL].valid) {
1565 /* Entry exist - update port only */
1566 pe.index = MVPP2_PE_DROP_ALL;
1567 mvpp2_prs_hw_read(priv, &pe);
1569 /* Entry doesn't exist - create new */
1570 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1571 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1572 pe.index = MVPP2_PE_DROP_ALL;
1574 /* Non-promiscuous mode for all ports - DROP unknown packets */
1575 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,
1576 MVPP2_PRS_RI_DROP_MASK);
1578 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1579 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1581 /* Update shadow table */
1582 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1584 /* Mask all ports */
1585 mvpp2_prs_tcam_port_map_set(&pe, 0);
1588 /* Update port mask */
1589 mvpp2_prs_tcam_port_set(&pe, port, add);
1591 mvpp2_prs_hw_write(priv, &pe);
1594 /* Set port to promiscuous mode */
1595 static void mvpp2_prs_mac_promisc_set(struct mvpp2 *priv, int port, bool add)
1597 struct mvpp2_prs_entry pe;
1599 /* Promiscuous mode - Accept unknown packets */
1601 if (priv->prs_shadow[MVPP2_PE_MAC_PROMISCUOUS].valid) {
1602 /* Entry exist - update port only */
1603 pe.index = MVPP2_PE_MAC_PROMISCUOUS;
1604 mvpp2_prs_hw_read(priv, &pe);
1606 /* Entry doesn't exist - create new */
1607 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1608 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1609 pe.index = MVPP2_PE_MAC_PROMISCUOUS;
1611 /* Continue - set next lookup */
1612 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA);
1614 /* Set result info bits */
1615 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_UCAST,
1616 MVPP2_PRS_RI_L2_CAST_MASK);
1618 /* Shift to ethertype */
1619 mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN,
1620 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1622 /* Mask all ports */
1623 mvpp2_prs_tcam_port_map_set(&pe, 0);
1625 /* Update shadow table */
1626 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1629 /* Update port mask */
1630 mvpp2_prs_tcam_port_set(&pe, port, add);
1632 mvpp2_prs_hw_write(priv, &pe);
1635 /* Accept multicast */
1636 static void mvpp2_prs_mac_multi_set(struct mvpp2 *priv, int port, int index,
1639 struct mvpp2_prs_entry pe;
1640 unsigned char da_mc;
1642 /* Ethernet multicast address first byte is
1643 * 0x01 for IPv4 and 0x33 for IPv6
1645 da_mc = (index == MVPP2_PE_MAC_MC_ALL) ? 0x01 : 0x33;
1647 if (priv->prs_shadow[index].valid) {
1648 /* Entry exist - update port only */
1650 mvpp2_prs_hw_read(priv, &pe);
1652 /* Entry doesn't exist - create new */
1653 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1654 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1657 /* Continue - set next lookup */
1658 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA);
1660 /* Set result info bits */
1661 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_MCAST,
1662 MVPP2_PRS_RI_L2_CAST_MASK);
1664 /* Update tcam entry data first byte */
1665 mvpp2_prs_tcam_data_byte_set(&pe, 0, da_mc, 0xff);
1667 /* Shift to ethertype */
1668 mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN,
1669 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1671 /* Mask all ports */
1672 mvpp2_prs_tcam_port_map_set(&pe, 0);
1674 /* Update shadow table */
1675 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1678 /* Update port mask */
1679 mvpp2_prs_tcam_port_set(&pe, port, add);
1681 mvpp2_prs_hw_write(priv, &pe);
1684 /* Set entry for dsa packets */
1685 static void mvpp2_prs_dsa_tag_set(struct mvpp2 *priv, int port, bool add,
1686 bool tagged, bool extend)
1688 struct mvpp2_prs_entry pe;
1692 tid = tagged ? MVPP2_PE_EDSA_TAGGED : MVPP2_PE_EDSA_UNTAGGED;
1695 tid = tagged ? MVPP2_PE_DSA_TAGGED : MVPP2_PE_DSA_UNTAGGED;
1699 if (priv->prs_shadow[tid].valid) {
1700 /* Entry exist - update port only */
1702 mvpp2_prs_hw_read(priv, &pe);
1704 /* Entry doesn't exist - create new */
1705 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1706 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_DSA);
1709 /* Shift 4 bytes if DSA tag or 8 bytes in case of EDSA tag*/
1710 mvpp2_prs_sram_shift_set(&pe, shift,
1711 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1713 /* Update shadow table */
1714 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_DSA);
1717 /* Set tagged bit in DSA tag */
1718 mvpp2_prs_tcam_data_byte_set(&pe, 0,
1719 MVPP2_PRS_TCAM_DSA_TAGGED_BIT,
1720 MVPP2_PRS_TCAM_DSA_TAGGED_BIT);
1721 /* Clear all ai bits for next iteration */
1722 mvpp2_prs_sram_ai_update(&pe, 0,
1723 MVPP2_PRS_SRAM_AI_MASK);
1724 /* If packet is tagged continue check vlans */
1725 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VLAN);
1727 /* Set result info bits to 'no vlans' */
1728 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_NONE,
1729 MVPP2_PRS_RI_VLAN_MASK);
1730 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2);
1733 /* Mask all ports */
1734 mvpp2_prs_tcam_port_map_set(&pe, 0);
1737 /* Update port mask */
1738 mvpp2_prs_tcam_port_set(&pe, port, add);
1740 mvpp2_prs_hw_write(priv, &pe);
1743 /* Set entry for dsa ethertype */
1744 static void mvpp2_prs_dsa_tag_ethertype_set(struct mvpp2 *priv, int port,
1745 bool add, bool tagged, bool extend)
1747 struct mvpp2_prs_entry pe;
1748 int tid, shift, port_mask;
1751 tid = tagged ? MVPP2_PE_ETYPE_EDSA_TAGGED :
1752 MVPP2_PE_ETYPE_EDSA_UNTAGGED;
1756 tid = tagged ? MVPP2_PE_ETYPE_DSA_TAGGED :
1757 MVPP2_PE_ETYPE_DSA_UNTAGGED;
1758 port_mask = MVPP2_PRS_PORT_MASK;
1762 if (priv->prs_shadow[tid].valid) {
1763 /* Entry exist - update port only */
1765 mvpp2_prs_hw_read(priv, &pe);
1767 /* Entry doesn't exist - create new */
1768 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1769 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_DSA);
1773 mvpp2_prs_match_etype(&pe, 0, ETH_P_EDSA);
1774 mvpp2_prs_match_etype(&pe, 2, 0);
1776 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DSA_MASK,
1777 MVPP2_PRS_RI_DSA_MASK);
1778 /* Shift ethertype + 2 byte reserved + tag*/
1779 mvpp2_prs_sram_shift_set(&pe, 2 + MVPP2_ETH_TYPE_LEN + shift,
1780 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1782 /* Update shadow table */
1783 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_DSA);
1786 /* Set tagged bit in DSA tag */
1787 mvpp2_prs_tcam_data_byte_set(&pe,
1788 MVPP2_ETH_TYPE_LEN + 2 + 3,
1789 MVPP2_PRS_TCAM_DSA_TAGGED_BIT,
1790 MVPP2_PRS_TCAM_DSA_TAGGED_BIT);
1791 /* Clear all ai bits for next iteration */
1792 mvpp2_prs_sram_ai_update(&pe, 0,
1793 MVPP2_PRS_SRAM_AI_MASK);
1794 /* If packet is tagged continue check vlans */
1795 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VLAN);
1797 /* Set result info bits to 'no vlans' */
1798 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_NONE,
1799 MVPP2_PRS_RI_VLAN_MASK);
1800 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2);
1802 /* Mask/unmask all ports, depending on dsa type */
1803 mvpp2_prs_tcam_port_map_set(&pe, port_mask);
1806 /* Update port mask */
1807 mvpp2_prs_tcam_port_set(&pe, port, add);
1809 mvpp2_prs_hw_write(priv, &pe);
1812 /* Search for existing single/triple vlan entry */
1813 static struct mvpp2_prs_entry *mvpp2_prs_vlan_find(struct mvpp2 *priv,
1814 unsigned short tpid, int ai)
1816 struct mvpp2_prs_entry *pe;
1819 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
1822 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_VLAN);
1824 /* Go through the all entries with MVPP2_PRS_LU_VLAN */
1825 for (tid = MVPP2_PE_FIRST_FREE_TID;
1826 tid <= MVPP2_PE_LAST_FREE_TID; tid++) {
1827 unsigned int ri_bits, ai_bits;
1830 if (!priv->prs_shadow[tid].valid ||
1831 priv->prs_shadow[tid].lu != MVPP2_PRS_LU_VLAN)
1836 mvpp2_prs_hw_read(priv, pe);
1837 match = mvpp2_prs_tcam_data_cmp(pe, 0, swab16(tpid));
1842 ri_bits = mvpp2_prs_sram_ri_get(pe);
1843 ri_bits &= MVPP2_PRS_RI_VLAN_MASK;
1845 /* Get current ai value from tcam */
1846 ai_bits = mvpp2_prs_tcam_ai_get(pe);
1847 /* Clear double vlan bit */
1848 ai_bits &= ~MVPP2_PRS_DBL_VLAN_AI_BIT;
1853 if (ri_bits == MVPP2_PRS_RI_VLAN_SINGLE ||
1854 ri_bits == MVPP2_PRS_RI_VLAN_TRIPLE)
1862 /* Add/update single/triple vlan entry */
1863 static int mvpp2_prs_vlan_add(struct mvpp2 *priv, unsigned short tpid, int ai,
1864 unsigned int port_map)
1866 struct mvpp2_prs_entry *pe;
1870 pe = mvpp2_prs_vlan_find(priv, tpid, ai);
1873 /* Create new tcam entry */
1874 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_LAST_FREE_TID,
1875 MVPP2_PE_FIRST_FREE_TID);
1879 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
1883 /* Get last double vlan tid */
1884 for (tid_aux = MVPP2_PE_LAST_FREE_TID;
1885 tid_aux >= MVPP2_PE_FIRST_FREE_TID; tid_aux--) {
1886 unsigned int ri_bits;
1888 if (!priv->prs_shadow[tid_aux].valid ||
1889 priv->prs_shadow[tid_aux].lu != MVPP2_PRS_LU_VLAN)
1892 pe->index = tid_aux;
1893 mvpp2_prs_hw_read(priv, pe);
1894 ri_bits = mvpp2_prs_sram_ri_get(pe);
1895 if ((ri_bits & MVPP2_PRS_RI_VLAN_MASK) ==
1896 MVPP2_PRS_RI_VLAN_DOUBLE)
1900 if (tid <= tid_aux) {
1905 memset(pe, 0 , sizeof(struct mvpp2_prs_entry));
1906 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_VLAN);
1909 mvpp2_prs_match_etype(pe, 0, tpid);
1911 mvpp2_prs_sram_next_lu_set(pe, MVPP2_PRS_LU_L2);
1912 /* Shift 4 bytes - skip 1 vlan tag */
1913 mvpp2_prs_sram_shift_set(pe, MVPP2_VLAN_TAG_LEN,
1914 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1915 /* Clear all ai bits for next iteration */
1916 mvpp2_prs_sram_ai_update(pe, 0, MVPP2_PRS_SRAM_AI_MASK);
1918 if (ai == MVPP2_PRS_SINGLE_VLAN_AI) {
1919 mvpp2_prs_sram_ri_update(pe, MVPP2_PRS_RI_VLAN_SINGLE,
1920 MVPP2_PRS_RI_VLAN_MASK);
1922 ai |= MVPP2_PRS_DBL_VLAN_AI_BIT;
1923 mvpp2_prs_sram_ri_update(pe, MVPP2_PRS_RI_VLAN_TRIPLE,
1924 MVPP2_PRS_RI_VLAN_MASK);
1926 mvpp2_prs_tcam_ai_update(pe, ai, MVPP2_PRS_SRAM_AI_MASK);
1928 mvpp2_prs_shadow_set(priv, pe->index, MVPP2_PRS_LU_VLAN);
1930 /* Update ports' mask */
1931 mvpp2_prs_tcam_port_map_set(pe, port_map);
1933 mvpp2_prs_hw_write(priv, pe);
1941 /* Get first free double vlan ai number */
1942 static int mvpp2_prs_double_vlan_ai_free_get(struct mvpp2 *priv)
1946 for (i = 1; i < MVPP2_PRS_DBL_VLANS_MAX; i++) {
1947 if (!priv->prs_double_vlans[i])
1954 /* Search for existing double vlan entry */
1955 static struct mvpp2_prs_entry *mvpp2_prs_double_vlan_find(struct mvpp2 *priv,
1956 unsigned short tpid1,
1957 unsigned short tpid2)
1959 struct mvpp2_prs_entry *pe;
1962 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
1965 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_VLAN);
1967 /* Go through the all entries with MVPP2_PRS_LU_VLAN */
1968 for (tid = MVPP2_PE_FIRST_FREE_TID;
1969 tid <= MVPP2_PE_LAST_FREE_TID; tid++) {
1970 unsigned int ri_mask;
1973 if (!priv->prs_shadow[tid].valid ||
1974 priv->prs_shadow[tid].lu != MVPP2_PRS_LU_VLAN)
1978 mvpp2_prs_hw_read(priv, pe);
1980 match = mvpp2_prs_tcam_data_cmp(pe, 0, swab16(tpid1))
1981 && mvpp2_prs_tcam_data_cmp(pe, 4, swab16(tpid2));
1986 ri_mask = mvpp2_prs_sram_ri_get(pe) & MVPP2_PRS_RI_VLAN_MASK;
1987 if (ri_mask == MVPP2_PRS_RI_VLAN_DOUBLE)
1995 /* Add or update double vlan entry */
1996 static int mvpp2_prs_double_vlan_add(struct mvpp2 *priv, unsigned short tpid1,
1997 unsigned short tpid2,
1998 unsigned int port_map)
2000 struct mvpp2_prs_entry *pe;
2001 int tid_aux, tid, ai, ret = 0;
2003 pe = mvpp2_prs_double_vlan_find(priv, tpid1, tpid2);
2006 /* Create new tcam entry */
2007 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2008 MVPP2_PE_LAST_FREE_TID);
2012 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
2016 /* Set ai value for new double vlan entry */
2017 ai = mvpp2_prs_double_vlan_ai_free_get(priv);
2023 /* Get first single/triple vlan tid */
2024 for (tid_aux = MVPP2_PE_FIRST_FREE_TID;
2025 tid_aux <= MVPP2_PE_LAST_FREE_TID; tid_aux++) {
2026 unsigned int ri_bits;
2028 if (!priv->prs_shadow[tid_aux].valid ||
2029 priv->prs_shadow[tid_aux].lu != MVPP2_PRS_LU_VLAN)
2032 pe->index = tid_aux;
2033 mvpp2_prs_hw_read(priv, pe);
2034 ri_bits = mvpp2_prs_sram_ri_get(pe);
2035 ri_bits &= MVPP2_PRS_RI_VLAN_MASK;
2036 if (ri_bits == MVPP2_PRS_RI_VLAN_SINGLE ||
2037 ri_bits == MVPP2_PRS_RI_VLAN_TRIPLE)
2041 if (tid >= tid_aux) {
2046 memset(pe, 0, sizeof(struct mvpp2_prs_entry));
2047 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_VLAN);
2050 priv->prs_double_vlans[ai] = true;
2052 mvpp2_prs_match_etype(pe, 0, tpid1);
2053 mvpp2_prs_match_etype(pe, 4, tpid2);
2055 mvpp2_prs_sram_next_lu_set(pe, MVPP2_PRS_LU_VLAN);
2056 /* Shift 8 bytes - skip 2 vlan tags */
2057 mvpp2_prs_sram_shift_set(pe, 2 * MVPP2_VLAN_TAG_LEN,
2058 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2059 mvpp2_prs_sram_ri_update(pe, MVPP2_PRS_RI_VLAN_DOUBLE,
2060 MVPP2_PRS_RI_VLAN_MASK);
2061 mvpp2_prs_sram_ai_update(pe, ai | MVPP2_PRS_DBL_VLAN_AI_BIT,
2062 MVPP2_PRS_SRAM_AI_MASK);
2064 mvpp2_prs_shadow_set(priv, pe->index, MVPP2_PRS_LU_VLAN);
2067 /* Update ports' mask */
2068 mvpp2_prs_tcam_port_map_set(pe, port_map);
2069 mvpp2_prs_hw_write(priv, pe);
2076 /* IPv4 header parsing for fragmentation and L4 offset */
2077 static int mvpp2_prs_ip4_proto(struct mvpp2 *priv, unsigned short proto,
2078 unsigned int ri, unsigned int ri_mask)
2080 struct mvpp2_prs_entry pe;
2083 if ((proto != IPPROTO_TCP) && (proto != IPPROTO_UDP) &&
2084 (proto != IPPROTO_IGMP))
2087 /* Fragmented packet */
2088 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2089 MVPP2_PE_LAST_FREE_TID);
2093 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2094 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4);
2097 /* Set next lu to IPv4 */
2098 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4);
2099 mvpp2_prs_sram_shift_set(&pe, 12, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2101 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4,
2102 sizeof(struct iphdr) - 4,
2103 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2104 mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT,
2105 MVPP2_PRS_IPV4_DIP_AI_BIT);
2106 mvpp2_prs_sram_ri_update(&pe, ri | MVPP2_PRS_RI_IP_FRAG_MASK,
2107 ri_mask | MVPP2_PRS_RI_IP_FRAG_MASK);
2109 mvpp2_prs_tcam_data_byte_set(&pe, 5, proto, MVPP2_PRS_TCAM_PROTO_MASK);
2110 mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV4_DIP_AI_BIT);
2111 /* Unmask all ports */
2112 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
2114 /* Update shadow table and hw entry */
2115 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4);
2116 mvpp2_prs_hw_write(priv, &pe);
2118 /* Not fragmented packet */
2119 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2120 MVPP2_PE_LAST_FREE_TID);
2125 /* Clear ri before updating */
2126 pe.sram.word[MVPP2_PRS_SRAM_RI_WORD] = 0x0;
2127 pe.sram.word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0;
2128 mvpp2_prs_sram_ri_update(&pe, ri, ri_mask);
2130 mvpp2_prs_tcam_data_byte_set(&pe, 2, 0x00, MVPP2_PRS_TCAM_PROTO_MASK_L);
2131 mvpp2_prs_tcam_data_byte_set(&pe, 3, 0x00, MVPP2_PRS_TCAM_PROTO_MASK);
2133 /* Update shadow table and hw entry */
2134 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4);
2135 mvpp2_prs_hw_write(priv, &pe);
2140 /* IPv4 L3 multicast or broadcast */
2141 static int mvpp2_prs_ip4_cast(struct mvpp2 *priv, unsigned short l3_cast)
2143 struct mvpp2_prs_entry pe;
2146 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2147 MVPP2_PE_LAST_FREE_TID);
2151 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2152 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4);
2156 case MVPP2_PRS_L3_MULTI_CAST:
2157 mvpp2_prs_tcam_data_byte_set(&pe, 0, MVPP2_PRS_IPV4_MC,
2158 MVPP2_PRS_IPV4_MC_MASK);
2159 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_MCAST,
2160 MVPP2_PRS_RI_L3_ADDR_MASK);
2162 case MVPP2_PRS_L3_BROAD_CAST:
2163 mask = MVPP2_PRS_IPV4_BC_MASK;
2164 mvpp2_prs_tcam_data_byte_set(&pe, 0, mask, mask);
2165 mvpp2_prs_tcam_data_byte_set(&pe, 1, mask, mask);
2166 mvpp2_prs_tcam_data_byte_set(&pe, 2, mask, mask);
2167 mvpp2_prs_tcam_data_byte_set(&pe, 3, mask, mask);
2168 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_BCAST,
2169 MVPP2_PRS_RI_L3_ADDR_MASK);
2175 /* Finished: go to flowid generation */
2176 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2177 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
2179 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT,
2180 MVPP2_PRS_IPV4_DIP_AI_BIT);
2181 /* Unmask all ports */
2182 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
2184 /* Update shadow table and hw entry */
2185 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4);
2186 mvpp2_prs_hw_write(priv, &pe);
2191 /* Set entries for protocols over IPv6 */
2192 static int mvpp2_prs_ip6_proto(struct mvpp2 *priv, unsigned short proto,
2193 unsigned int ri, unsigned int ri_mask)
2195 struct mvpp2_prs_entry pe;
2198 if ((proto != IPPROTO_TCP) && (proto != IPPROTO_UDP) &&
2199 (proto != IPPROTO_ICMPV6) && (proto != IPPROTO_IPIP))
2202 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2203 MVPP2_PE_LAST_FREE_TID);
2207 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2208 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6);
2211 /* Finished: go to flowid generation */
2212 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2213 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
2214 mvpp2_prs_sram_ri_update(&pe, ri, ri_mask);
2215 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4,
2216 sizeof(struct ipv6hdr) - 6,
2217 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2219 mvpp2_prs_tcam_data_byte_set(&pe, 0, proto, MVPP2_PRS_TCAM_PROTO_MASK);
2220 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT,
2221 MVPP2_PRS_IPV6_NO_EXT_AI_BIT);
2222 /* Unmask all ports */
2223 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
2226 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP6);
2227 mvpp2_prs_hw_write(priv, &pe);
2232 /* IPv6 L3 multicast entry */
2233 static int mvpp2_prs_ip6_cast(struct mvpp2 *priv, unsigned short l3_cast)
2235 struct mvpp2_prs_entry pe;
2238 if (l3_cast != MVPP2_PRS_L3_MULTI_CAST)
2241 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2242 MVPP2_PE_LAST_FREE_TID);
2246 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2247 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6);
2250 /* Finished: go to flowid generation */
2251 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6);
2252 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_MCAST,
2253 MVPP2_PRS_RI_L3_ADDR_MASK);
2254 mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT,
2255 MVPP2_PRS_IPV6_NO_EXT_AI_BIT);
2256 /* Shift back to IPv6 NH */
2257 mvpp2_prs_sram_shift_set(&pe, -18, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2259 mvpp2_prs_tcam_data_byte_set(&pe, 0, MVPP2_PRS_IPV6_MC,
2260 MVPP2_PRS_IPV6_MC_MASK);
2261 mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV6_NO_EXT_AI_BIT);
2262 /* Unmask all ports */
2263 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
2265 /* Update shadow table and hw entry */
2266 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP6);
2267 mvpp2_prs_hw_write(priv, &pe);
2272 /* Parser per-port initialization */
2273 static void mvpp2_prs_hw_port_init(struct mvpp2 *priv, int port, int lu_first,
2274 int lu_max, int offset)
2279 val = mvpp2_read(priv, MVPP2_PRS_INIT_LOOKUP_REG);
2280 val &= ~MVPP2_PRS_PORT_LU_MASK(port);
2281 val |= MVPP2_PRS_PORT_LU_VAL(port, lu_first);
2282 mvpp2_write(priv, MVPP2_PRS_INIT_LOOKUP_REG, val);
2284 /* Set maximum number of loops for packet received from port */
2285 val = mvpp2_read(priv, MVPP2_PRS_MAX_LOOP_REG(port));
2286 val &= ~MVPP2_PRS_MAX_LOOP_MASK(port);
2287 val |= MVPP2_PRS_MAX_LOOP_VAL(port, lu_max);
2288 mvpp2_write(priv, MVPP2_PRS_MAX_LOOP_REG(port), val);
2290 /* Set initial offset for packet header extraction for the first
2293 val = mvpp2_read(priv, MVPP2_PRS_INIT_OFFS_REG(port));
2294 val &= ~MVPP2_PRS_INIT_OFF_MASK(port);
2295 val |= MVPP2_PRS_INIT_OFF_VAL(port, offset);
2296 mvpp2_write(priv, MVPP2_PRS_INIT_OFFS_REG(port), val);
2299 /* Default flow entries initialization for all ports */
2300 static void mvpp2_prs_def_flow_init(struct mvpp2 *priv)
2302 struct mvpp2_prs_entry pe;
2305 for (port = 0; port < MVPP2_MAX_PORTS; port++) {
2306 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2307 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2308 pe.index = MVPP2_PE_FIRST_DEFAULT_FLOW - port;
2310 /* Mask all ports */
2311 mvpp2_prs_tcam_port_map_set(&pe, 0);
2314 mvpp2_prs_sram_ai_update(&pe, port, MVPP2_PRS_FLOW_ID_MASK);
2315 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);
2317 /* Update shadow table and hw entry */
2318 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_FLOWS);
2319 mvpp2_prs_hw_write(priv, &pe);
2323 /* Set default entry for Marvell Header field */
2324 static void mvpp2_prs_mh_init(struct mvpp2 *priv)
2326 struct mvpp2_prs_entry pe;
2328 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2330 pe.index = MVPP2_PE_MH_DEFAULT;
2331 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MH);
2332 mvpp2_prs_sram_shift_set(&pe, MVPP2_MH_SIZE,
2333 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2334 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_MAC);
2336 /* Unmask all ports */
2337 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
2339 /* Update shadow table and hw entry */
2340 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MH);
2341 mvpp2_prs_hw_write(priv, &pe);
2344 /* Set default entires (place holder) for promiscuous, non-promiscuous and
2345 * multicast MAC addresses
2347 static void mvpp2_prs_mac_init(struct mvpp2 *priv)
2349 struct mvpp2_prs_entry pe;
2351 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2353 /* Non-promiscuous mode for all ports - DROP unknown packets */
2354 pe.index = MVPP2_PE_MAC_NON_PROMISCUOUS;
2355 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
2357 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,
2358 MVPP2_PRS_RI_DROP_MASK);
2359 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
2360 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2362 /* Unmask all ports */
2363 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
2365 /* Update shadow table and hw entry */
2366 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
2367 mvpp2_prs_hw_write(priv, &pe);
2369 /* place holders only - no ports */
2370 mvpp2_prs_mac_drop_all_set(priv, 0, false);
2371 mvpp2_prs_mac_promisc_set(priv, 0, false);
2372 mvpp2_prs_mac_multi_set(priv, MVPP2_PE_MAC_MC_ALL, 0, false);
2373 mvpp2_prs_mac_multi_set(priv, MVPP2_PE_MAC_MC_IP6, 0, false);
2376 /* Set default entries for various types of dsa packets */
2377 static void mvpp2_prs_dsa_init(struct mvpp2 *priv)
2379 struct mvpp2_prs_entry pe;
2381 /* None tagged EDSA entry - place holder */
2382 mvpp2_prs_dsa_tag_set(priv, 0, false, MVPP2_PRS_UNTAGGED,
2385 /* Tagged EDSA entry - place holder */
2386 mvpp2_prs_dsa_tag_set(priv, 0, false, MVPP2_PRS_TAGGED, MVPP2_PRS_EDSA);
2388 /* None tagged DSA entry - place holder */
2389 mvpp2_prs_dsa_tag_set(priv, 0, false, MVPP2_PRS_UNTAGGED,
2392 /* Tagged DSA entry - place holder */
2393 mvpp2_prs_dsa_tag_set(priv, 0, false, MVPP2_PRS_TAGGED, MVPP2_PRS_DSA);
2395 /* None tagged EDSA ethertype entry - place holder*/
2396 mvpp2_prs_dsa_tag_ethertype_set(priv, 0, false,
2397 MVPP2_PRS_UNTAGGED, MVPP2_PRS_EDSA);
2399 /* Tagged EDSA ethertype entry - place holder*/
2400 mvpp2_prs_dsa_tag_ethertype_set(priv, 0, false,
2401 MVPP2_PRS_TAGGED, MVPP2_PRS_EDSA);
2403 /* None tagged DSA ethertype entry */
2404 mvpp2_prs_dsa_tag_ethertype_set(priv, 0, true,
2405 MVPP2_PRS_UNTAGGED, MVPP2_PRS_DSA);
2407 /* Tagged DSA ethertype entry */
2408 mvpp2_prs_dsa_tag_ethertype_set(priv, 0, true,
2409 MVPP2_PRS_TAGGED, MVPP2_PRS_DSA);
2411 /* Set default entry, in case DSA or EDSA tag not found */
2412 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2413 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_DSA);
2414 pe.index = MVPP2_PE_DSA_DEFAULT;
2415 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VLAN);
2418 mvpp2_prs_sram_shift_set(&pe, 0, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2419 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
2421 /* Clear all sram ai bits for next iteration */
2422 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK);
2424 /* Unmask all ports */
2425 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
2427 mvpp2_prs_hw_write(priv, &pe);
2430 /* Match basic ethertypes */
2431 static int mvpp2_prs_etype_init(struct mvpp2 *priv)
2433 struct mvpp2_prs_entry pe;
2436 /* Ethertype: PPPoE */
2437 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2438 MVPP2_PE_LAST_FREE_TID);
2442 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2443 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2446 mvpp2_prs_match_etype(&pe, 0, ETH_P_PPP_SES);
2448 mvpp2_prs_sram_shift_set(&pe, MVPP2_PPPOE_HDR_SIZE,
2449 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2450 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_PPPOE);
2451 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_PPPOE_MASK,
2452 MVPP2_PRS_RI_PPPOE_MASK);
2454 /* Update shadow table and hw entry */
2455 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2456 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2457 priv->prs_shadow[pe.index].finish = false;
2458 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_PPPOE_MASK,
2459 MVPP2_PRS_RI_PPPOE_MASK);
2460 mvpp2_prs_hw_write(priv, &pe);
2462 /* Ethertype: ARP */
2463 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2464 MVPP2_PE_LAST_FREE_TID);
2468 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2469 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2472 mvpp2_prs_match_etype(&pe, 0, ETH_P_ARP);
2474 /* Generate flow in the next iteration*/
2475 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2476 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
2477 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_ARP,
2478 MVPP2_PRS_RI_L3_PROTO_MASK);
2480 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2482 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2484 /* Update shadow table and hw entry */
2485 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2486 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2487 priv->prs_shadow[pe.index].finish = true;
2488 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_ARP,
2489 MVPP2_PRS_RI_L3_PROTO_MASK);
2490 mvpp2_prs_hw_write(priv, &pe);
2492 /* Ethertype: LBTD */
2493 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2494 MVPP2_PE_LAST_FREE_TID);
2498 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2499 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2502 mvpp2_prs_match_etype(&pe, 0, MVPP2_IP_LBDT_TYPE);
2504 /* Generate flow in the next iteration*/
2505 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2506 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
2507 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC |
2508 MVPP2_PRS_RI_UDF3_RX_SPECIAL,
2509 MVPP2_PRS_RI_CPU_CODE_MASK |
2510 MVPP2_PRS_RI_UDF3_MASK);
2512 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2514 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2516 /* Update shadow table and hw entry */
2517 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2518 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2519 priv->prs_shadow[pe.index].finish = true;
2520 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC |
2521 MVPP2_PRS_RI_UDF3_RX_SPECIAL,
2522 MVPP2_PRS_RI_CPU_CODE_MASK |
2523 MVPP2_PRS_RI_UDF3_MASK);
2524 mvpp2_prs_hw_write(priv, &pe);
2526 /* Ethertype: IPv4 without options */
2527 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2528 MVPP2_PE_LAST_FREE_TID);
2532 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2533 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2536 mvpp2_prs_match_etype(&pe, 0, ETH_P_IP);
2537 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,
2538 MVPP2_PRS_IPV4_HEAD | MVPP2_PRS_IPV4_IHL,
2539 MVPP2_PRS_IPV4_HEAD_MASK |
2540 MVPP2_PRS_IPV4_IHL_MASK);
2542 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4);
2543 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4,
2544 MVPP2_PRS_RI_L3_PROTO_MASK);
2545 /* Skip eth_type + 4 bytes of IP header */
2546 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4,
2547 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2549 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2551 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2553 /* Update shadow table and hw entry */
2554 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2555 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2556 priv->prs_shadow[pe.index].finish = false;
2557 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4,
2558 MVPP2_PRS_RI_L3_PROTO_MASK);
2559 mvpp2_prs_hw_write(priv, &pe);
2561 /* Ethertype: IPv4 with options */
2562 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2563 MVPP2_PE_LAST_FREE_TID);
2569 /* Clear tcam data before updating */
2570 pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(MVPP2_ETH_TYPE_LEN)] = 0x0;
2571 pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(MVPP2_ETH_TYPE_LEN)] = 0x0;
2573 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,
2574 MVPP2_PRS_IPV4_HEAD,
2575 MVPP2_PRS_IPV4_HEAD_MASK);
2577 /* Clear ri before updating */
2578 pe.sram.word[MVPP2_PRS_SRAM_RI_WORD] = 0x0;
2579 pe.sram.word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0;
2580 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4_OPT,
2581 MVPP2_PRS_RI_L3_PROTO_MASK);
2583 /* Update shadow table and hw entry */
2584 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2585 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2586 priv->prs_shadow[pe.index].finish = false;
2587 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4_OPT,
2588 MVPP2_PRS_RI_L3_PROTO_MASK);
2589 mvpp2_prs_hw_write(priv, &pe);
2591 /* Ethertype: IPv6 without options */
2592 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2593 MVPP2_PE_LAST_FREE_TID);
2597 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2598 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2601 mvpp2_prs_match_etype(&pe, 0, ETH_P_IPV6);
2603 /* Skip DIP of IPV6 header */
2604 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 8 +
2605 MVPP2_MAX_L3_ADDR_SIZE,
2606 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2607 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6);
2608 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6,
2609 MVPP2_PRS_RI_L3_PROTO_MASK);
2611 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2613 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2615 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2616 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2617 priv->prs_shadow[pe.index].finish = false;
2618 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP6,
2619 MVPP2_PRS_RI_L3_PROTO_MASK);
2620 mvpp2_prs_hw_write(priv, &pe);
2622 /* Default entry for MVPP2_PRS_LU_L2 - Unknown ethtype */
2623 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2624 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2625 pe.index = MVPP2_PE_ETH_TYPE_UN;
2627 /* Unmask all ports */
2628 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
2630 /* Generate flow in the next iteration*/
2631 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
2632 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2633 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN,
2634 MVPP2_PRS_RI_L3_PROTO_MASK);
2635 /* Set L3 offset even it's unknown L3 */
2636 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2638 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2640 /* Update shadow table and hw entry */
2641 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2642 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2643 priv->prs_shadow[pe.index].finish = true;
2644 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_UN,
2645 MVPP2_PRS_RI_L3_PROTO_MASK);
2646 mvpp2_prs_hw_write(priv, &pe);
2651 /* Configure vlan entries and detect up to 2 successive VLAN tags.
2658 static int mvpp2_prs_vlan_init(struct platform_device *pdev, struct mvpp2 *priv)
2660 struct mvpp2_prs_entry pe;
2663 priv->prs_double_vlans = devm_kcalloc(&pdev->dev, sizeof(bool),
2664 MVPP2_PRS_DBL_VLANS_MAX,
2666 if (!priv->prs_double_vlans)
2669 /* Double VLAN: 0x8100, 0x88A8 */
2670 err = mvpp2_prs_double_vlan_add(priv, ETH_P_8021Q, ETH_P_8021AD,
2671 MVPP2_PRS_PORT_MASK);
2675 /* Double VLAN: 0x8100, 0x8100 */
2676 err = mvpp2_prs_double_vlan_add(priv, ETH_P_8021Q, ETH_P_8021Q,
2677 MVPP2_PRS_PORT_MASK);
2681 /* Single VLAN: 0x88a8 */
2682 err = mvpp2_prs_vlan_add(priv, ETH_P_8021AD, MVPP2_PRS_SINGLE_VLAN_AI,
2683 MVPP2_PRS_PORT_MASK);
2687 /* Single VLAN: 0x8100 */
2688 err = mvpp2_prs_vlan_add(priv, ETH_P_8021Q, MVPP2_PRS_SINGLE_VLAN_AI,
2689 MVPP2_PRS_PORT_MASK);
2693 /* Set default double vlan entry */
2694 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2695 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VLAN);
2696 pe.index = MVPP2_PE_VLAN_DBL;
2698 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2);
2699 /* Clear ai for next iterations */
2700 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK);
2701 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_DOUBLE,
2702 MVPP2_PRS_RI_VLAN_MASK);
2704 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_DBL_VLAN_AI_BIT,
2705 MVPP2_PRS_DBL_VLAN_AI_BIT);
2706 /* Unmask all ports */
2707 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
2709 /* Update shadow table and hw entry */
2710 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VLAN);
2711 mvpp2_prs_hw_write(priv, &pe);
2713 /* Set default vlan none entry */
2714 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2715 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VLAN);
2716 pe.index = MVPP2_PE_VLAN_NONE;
2718 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2);
2719 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_NONE,
2720 MVPP2_PRS_RI_VLAN_MASK);
2722 /* Unmask all ports */
2723 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
2725 /* Update shadow table and hw entry */
2726 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VLAN);
2727 mvpp2_prs_hw_write(priv, &pe);
2732 /* Set entries for PPPoE ethertype */
2733 static int mvpp2_prs_pppoe_init(struct mvpp2 *priv)
2735 struct mvpp2_prs_entry pe;
2738 /* IPv4 over PPPoE with options */
2739 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2740 MVPP2_PE_LAST_FREE_TID);
2744 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2745 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_PPPOE);
2748 mvpp2_prs_match_etype(&pe, 0, PPP_IP);
2750 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4);
2751 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4_OPT,
2752 MVPP2_PRS_RI_L3_PROTO_MASK);
2753 /* Skip eth_type + 4 bytes of IP header */
2754 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4,
2755 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2757 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2759 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2761 /* Update shadow table and hw entry */
2762 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE);
2763 mvpp2_prs_hw_write(priv, &pe);
2765 /* IPv4 over PPPoE without options */
2766 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2767 MVPP2_PE_LAST_FREE_TID);
2773 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,
2774 MVPP2_PRS_IPV4_HEAD | MVPP2_PRS_IPV4_IHL,
2775 MVPP2_PRS_IPV4_HEAD_MASK |
2776 MVPP2_PRS_IPV4_IHL_MASK);
2778 /* Clear ri before updating */
2779 pe.sram.word[MVPP2_PRS_SRAM_RI_WORD] = 0x0;
2780 pe.sram.word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0;
2781 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4,
2782 MVPP2_PRS_RI_L3_PROTO_MASK);
2784 /* Update shadow table and hw entry */
2785 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE);
2786 mvpp2_prs_hw_write(priv, &pe);
2788 /* IPv6 over PPPoE */
2789 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2790 MVPP2_PE_LAST_FREE_TID);
2794 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2795 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_PPPOE);
2798 mvpp2_prs_match_etype(&pe, 0, PPP_IPV6);
2800 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6);
2801 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6,
2802 MVPP2_PRS_RI_L3_PROTO_MASK);
2803 /* Skip eth_type + 4 bytes of IPv6 header */
2804 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4,
2805 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2807 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2809 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2811 /* Update shadow table and hw entry */
2812 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE);
2813 mvpp2_prs_hw_write(priv, &pe);
2815 /* Non-IP over PPPoE */
2816 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2817 MVPP2_PE_LAST_FREE_TID);
2821 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2822 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_PPPOE);
2825 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN,
2826 MVPP2_PRS_RI_L3_PROTO_MASK);
2828 /* Finished: go to flowid generation */
2829 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2830 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
2831 /* Set L3 offset even if it's unknown L3 */
2832 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2834 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2836 /* Update shadow table and hw entry */
2837 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE);
2838 mvpp2_prs_hw_write(priv, &pe);
2843 /* Initialize entries for IPv4 */
2844 static int mvpp2_prs_ip4_init(struct mvpp2 *priv)
2846 struct mvpp2_prs_entry pe;
2849 /* Set entries for TCP, UDP and IGMP over IPv4 */
2850 err = mvpp2_prs_ip4_proto(priv, IPPROTO_TCP, MVPP2_PRS_RI_L4_TCP,
2851 MVPP2_PRS_RI_L4_PROTO_MASK);
2855 err = mvpp2_prs_ip4_proto(priv, IPPROTO_UDP, MVPP2_PRS_RI_L4_UDP,
2856 MVPP2_PRS_RI_L4_PROTO_MASK);
2860 err = mvpp2_prs_ip4_proto(priv, IPPROTO_IGMP,
2861 MVPP2_PRS_RI_CPU_CODE_RX_SPEC |
2862 MVPP2_PRS_RI_UDF3_RX_SPECIAL,
2863 MVPP2_PRS_RI_CPU_CODE_MASK |
2864 MVPP2_PRS_RI_UDF3_MASK);
2868 /* IPv4 Broadcast */
2869 err = mvpp2_prs_ip4_cast(priv, MVPP2_PRS_L3_BROAD_CAST);
2873 /* IPv4 Multicast */
2874 err = mvpp2_prs_ip4_cast(priv, MVPP2_PRS_L3_MULTI_CAST);
2878 /* Default IPv4 entry for unknown protocols */
2879 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2880 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4);
2881 pe.index = MVPP2_PE_IP4_PROTO_UN;
2883 /* Set next lu to IPv4 */
2884 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4);
2885 mvpp2_prs_sram_shift_set(&pe, 12, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2887 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4,
2888 sizeof(struct iphdr) - 4,
2889 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2890 mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT,
2891 MVPP2_PRS_IPV4_DIP_AI_BIT);
2892 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L4_OTHER,
2893 MVPP2_PRS_RI_L4_PROTO_MASK);
2895 mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV4_DIP_AI_BIT);
2896 /* Unmask all ports */
2897 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
2899 /* Update shadow table and hw entry */
2900 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4);
2901 mvpp2_prs_hw_write(priv, &pe);
2903 /* Default IPv4 entry for unicast address */
2904 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2905 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4);
2906 pe.index = MVPP2_PE_IP4_ADDR_UN;
2908 /* Finished: go to flowid generation */
2909 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2910 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
2911 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UCAST,
2912 MVPP2_PRS_RI_L3_ADDR_MASK);
2914 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT,
2915 MVPP2_PRS_IPV4_DIP_AI_BIT);
2916 /* Unmask all ports */
2917 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
2919 /* Update shadow table and hw entry */
2920 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4);
2921 mvpp2_prs_hw_write(priv, &pe);
2926 /* Initialize entries for IPv6 */
2927 static int mvpp2_prs_ip6_init(struct mvpp2 *priv)
2929 struct mvpp2_prs_entry pe;
2932 /* Set entries for TCP, UDP and ICMP over IPv6 */
2933 err = mvpp2_prs_ip6_proto(priv, IPPROTO_TCP,
2934 MVPP2_PRS_RI_L4_TCP,
2935 MVPP2_PRS_RI_L4_PROTO_MASK);
2939 err = mvpp2_prs_ip6_proto(priv, IPPROTO_UDP,
2940 MVPP2_PRS_RI_L4_UDP,
2941 MVPP2_PRS_RI_L4_PROTO_MASK);
2945 err = mvpp2_prs_ip6_proto(priv, IPPROTO_ICMPV6,
2946 MVPP2_PRS_RI_CPU_CODE_RX_SPEC |
2947 MVPP2_PRS_RI_UDF3_RX_SPECIAL,
2948 MVPP2_PRS_RI_CPU_CODE_MASK |
2949 MVPP2_PRS_RI_UDF3_MASK);
2953 /* IPv4 is the last header. This is similar case as 6-TCP or 17-UDP */
2954 /* Result Info: UDF7=1, DS lite */
2955 err = mvpp2_prs_ip6_proto(priv, IPPROTO_IPIP,
2956 MVPP2_PRS_RI_UDF7_IP6_LITE,
2957 MVPP2_PRS_RI_UDF7_MASK);
2961 /* IPv6 multicast */
2962 err = mvpp2_prs_ip6_cast(priv, MVPP2_PRS_L3_MULTI_CAST);
2966 /* Entry for checking hop limit */
2967 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2968 MVPP2_PE_LAST_FREE_TID);
2972 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2973 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6);
2976 /* Finished: go to flowid generation */
2977 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2978 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
2979 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN |
2980 MVPP2_PRS_RI_DROP_MASK,
2981 MVPP2_PRS_RI_L3_PROTO_MASK |
2982 MVPP2_PRS_RI_DROP_MASK);
2984 mvpp2_prs_tcam_data_byte_set(&pe, 1, 0x00, MVPP2_PRS_IPV6_HOP_MASK);
2985 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT,
2986 MVPP2_PRS_IPV6_NO_EXT_AI_BIT);
2988 /* Update shadow table and hw entry */
2989 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4);
2990 mvpp2_prs_hw_write(priv, &pe);
2992 /* Default IPv6 entry for unknown protocols */
2993 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2994 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6);
2995 pe.index = MVPP2_PE_IP6_PROTO_UN;
2997 /* Finished: go to flowid generation */
2998 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2999 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
3000 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L4_OTHER,
3001 MVPP2_PRS_RI_L4_PROTO_MASK);
3002 /* Set L4 offset relatively to our current place */
3003 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4,
3004 sizeof(struct ipv6hdr) - 4,
3005 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
3007 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT,
3008 MVPP2_PRS_IPV6_NO_EXT_AI_BIT);
3009 /* Unmask all ports */
3010 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
3012 /* Update shadow table and hw entry */
3013 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4);
3014 mvpp2_prs_hw_write(priv, &pe);
3016 /* Default IPv6 entry for unknown ext protocols */
3017 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
3018 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6);
3019 pe.index = MVPP2_PE_IP6_EXT_PROTO_UN;
3021 /* Finished: go to flowid generation */
3022 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
3023 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
3024 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L4_OTHER,
3025 MVPP2_PRS_RI_L4_PROTO_MASK);
3027 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_EXT_AI_BIT,
3028 MVPP2_PRS_IPV6_EXT_AI_BIT);
3029 /* Unmask all ports */
3030 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
3032 /* Update shadow table and hw entry */
3033 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4);
3034 mvpp2_prs_hw_write(priv, &pe);
3036 /* Default IPv6 entry for unicast address */
3037 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
3038 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6);
3039 pe.index = MVPP2_PE_IP6_ADDR_UN;
3041 /* Finished: go to IPv6 again */
3042 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6);
3043 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UCAST,
3044 MVPP2_PRS_RI_L3_ADDR_MASK);
3045 mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT,
3046 MVPP2_PRS_IPV6_NO_EXT_AI_BIT);
3047 /* Shift back to IPV6 NH */
3048 mvpp2_prs_sram_shift_set(&pe, -18, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
3050 mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV6_NO_EXT_AI_BIT);
3051 /* Unmask all ports */
3052 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
3054 /* Update shadow table and hw entry */
3055 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP6);
3056 mvpp2_prs_hw_write(priv, &pe);
3061 /* Parser default initialization */
3062 static int mvpp2_prs_default_init(struct platform_device *pdev,
3067 /* Enable tcam table */
3068 mvpp2_write(priv, MVPP2_PRS_TCAM_CTRL_REG, MVPP2_PRS_TCAM_EN_MASK);
3070 /* Clear all tcam and sram entries */
3071 for (index = 0; index < MVPP2_PRS_TCAM_SRAM_SIZE; index++) {
3072 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index);
3073 for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
3074 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), 0);
3076 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, index);
3077 for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
3078 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), 0);
3081 /* Invalidate all tcam entries */
3082 for (index = 0; index < MVPP2_PRS_TCAM_SRAM_SIZE; index++)
3083 mvpp2_prs_hw_inv(priv, index);
3085 priv->prs_shadow = devm_kcalloc(&pdev->dev, MVPP2_PRS_TCAM_SRAM_SIZE,
3086 sizeof(struct mvpp2_prs_shadow),
3088 if (!priv->prs_shadow)
3091 /* Always start from lookup = 0 */
3092 for (index = 0; index < MVPP2_MAX_PORTS; index++)
3093 mvpp2_prs_hw_port_init(priv, index, MVPP2_PRS_LU_MH,
3094 MVPP2_PRS_PORT_LU_MAX, 0);
3096 mvpp2_prs_def_flow_init(priv);
3098 mvpp2_prs_mh_init(priv);
3100 mvpp2_prs_mac_init(priv);
3102 mvpp2_prs_dsa_init(priv);
3104 err = mvpp2_prs_etype_init(priv);
3108 err = mvpp2_prs_vlan_init(pdev, priv);
3112 err = mvpp2_prs_pppoe_init(priv);
3116 err = mvpp2_prs_ip6_init(priv);
3120 err = mvpp2_prs_ip4_init(priv);
3127 /* Compare MAC DA with tcam entry data */
3128 static bool mvpp2_prs_mac_range_equals(struct mvpp2_prs_entry *pe,
3129 const u8 *da, unsigned char *mask)
3131 unsigned char tcam_byte, tcam_mask;
3134 for (index = 0; index < ETH_ALEN; index++) {
3135 mvpp2_prs_tcam_data_byte_get(pe, index, &tcam_byte, &tcam_mask);
3136 if (tcam_mask != mask[index])
3139 if ((tcam_mask & tcam_byte) != (da[index] & mask[index]))
3146 /* Find tcam entry with matched pair <MAC DA, port> */
3147 static struct mvpp2_prs_entry *
3148 mvpp2_prs_mac_da_range_find(struct mvpp2 *priv, int pmap, const u8 *da,
3149 unsigned char *mask, int udf_type)
3151 struct mvpp2_prs_entry *pe;
3154 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
3157 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC);
3159 /* Go through the all entires with MVPP2_PRS_LU_MAC */
3160 for (tid = MVPP2_PE_FIRST_FREE_TID;
3161 tid <= MVPP2_PE_LAST_FREE_TID; tid++) {
3162 unsigned int entry_pmap;
3164 if (!priv->prs_shadow[tid].valid ||
3165 (priv->prs_shadow[tid].lu != MVPP2_PRS_LU_MAC) ||
3166 (priv->prs_shadow[tid].udf != udf_type))
3170 mvpp2_prs_hw_read(priv, pe);
3171 entry_pmap = mvpp2_prs_tcam_port_map_get(pe);
3173 if (mvpp2_prs_mac_range_equals(pe, da, mask) &&
3182 /* Update parser's mac da entry */
3183 static int mvpp2_prs_mac_da_accept(struct mvpp2 *priv, int port,
3184 const u8 *da, bool add)
3186 struct mvpp2_prs_entry *pe;
3187 unsigned int pmap, len, ri;
3188 unsigned char mask[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
3191 /* Scan TCAM and see if entry with this <MAC DA, port> already exist */
3192 pe = mvpp2_prs_mac_da_range_find(priv, (1 << port), da, mask,
3193 MVPP2_PRS_UDF_MAC_DEF);
3200 /* Create new TCAM entry */
3201 /* Find first range mac entry*/
3202 for (tid = MVPP2_PE_FIRST_FREE_TID;
3203 tid <= MVPP2_PE_LAST_FREE_TID; tid++)
3204 if (priv->prs_shadow[tid].valid &&
3205 (priv->prs_shadow[tid].lu == MVPP2_PRS_LU_MAC) &&
3206 (priv->prs_shadow[tid].udf ==
3207 MVPP2_PRS_UDF_MAC_RANGE))
3210 /* Go through the all entries from first to last */
3211 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
3216 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
3219 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC);
3222 /* Mask all ports */
3223 mvpp2_prs_tcam_port_map_set(pe, 0);
3226 /* Update port mask */
3227 mvpp2_prs_tcam_port_set(pe, port, add);
3229 /* Invalidate the entry if no ports are left enabled */
3230 pmap = mvpp2_prs_tcam_port_map_get(pe);
3236 mvpp2_prs_hw_inv(priv, pe->index);
3237 priv->prs_shadow[pe->index].valid = false;
3242 /* Continue - set next lookup */
3243 mvpp2_prs_sram_next_lu_set(pe, MVPP2_PRS_LU_DSA);
3245 /* Set match on DA */
3248 mvpp2_prs_tcam_data_byte_set(pe, len, da[len], 0xff);
3250 /* Set result info bits */
3251 if (is_broadcast_ether_addr(da))
3252 ri = MVPP2_PRS_RI_L2_BCAST;
3253 else if (is_multicast_ether_addr(da))
3254 ri = MVPP2_PRS_RI_L2_MCAST;
3256 ri = MVPP2_PRS_RI_L2_UCAST | MVPP2_PRS_RI_MAC_ME_MASK;
3258 mvpp2_prs_sram_ri_update(pe, ri, MVPP2_PRS_RI_L2_CAST_MASK |
3259 MVPP2_PRS_RI_MAC_ME_MASK);
3260 mvpp2_prs_shadow_ri_set(priv, pe->index, ri, MVPP2_PRS_RI_L2_CAST_MASK |
3261 MVPP2_PRS_RI_MAC_ME_MASK);
3263 /* Shift to ethertype */
3264 mvpp2_prs_sram_shift_set(pe, 2 * ETH_ALEN,
3265 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
3267 /* Update shadow table and hw entry */
3268 priv->prs_shadow[pe->index].udf = MVPP2_PRS_UDF_MAC_DEF;
3269 mvpp2_prs_shadow_set(priv, pe->index, MVPP2_PRS_LU_MAC);
3270 mvpp2_prs_hw_write(priv, pe);
3277 static int mvpp2_prs_update_mac_da(struct net_device *dev, const u8 *da)
3279 struct mvpp2_port *port = netdev_priv(dev);
3282 /* Remove old parser entry */
3283 err = mvpp2_prs_mac_da_accept(port->priv, port->id, dev->dev_addr,
3288 /* Add new parser entry */
3289 err = mvpp2_prs_mac_da_accept(port->priv, port->id, da, true);
3293 /* Set addr in the device */
3294 ether_addr_copy(dev->dev_addr, da);
3299 /* Delete all port's multicast simple (not range) entries */
3300 static void mvpp2_prs_mcast_del_all(struct mvpp2 *priv, int port)
3302 struct mvpp2_prs_entry pe;
3305 for (tid = MVPP2_PE_FIRST_FREE_TID;
3306 tid <= MVPP2_PE_LAST_FREE_TID; tid++) {
3307 unsigned char da[ETH_ALEN], da_mask[ETH_ALEN];
3309 if (!priv->prs_shadow[tid].valid ||
3310 (priv->prs_shadow[tid].lu != MVPP2_PRS_LU_MAC) ||
3311 (priv->prs_shadow[tid].udf != MVPP2_PRS_UDF_MAC_DEF))
3314 /* Only simple mac entries */
3316 mvpp2_prs_hw_read(priv, &pe);
3318 /* Read mac addr from entry */
3319 for (index = 0; index < ETH_ALEN; index++)
3320 mvpp2_prs_tcam_data_byte_get(&pe, index, &da[index],
3323 if (is_multicast_ether_addr(da) && !is_broadcast_ether_addr(da))
3324 /* Delete this entry */
3325 mvpp2_prs_mac_da_accept(priv, port, da, false);
3329 static int mvpp2_prs_tag_mode_set(struct mvpp2 *priv, int port, int type)
3332 case MVPP2_TAG_TYPE_EDSA:
3333 /* Add port to EDSA entries */
3334 mvpp2_prs_dsa_tag_set(priv, port, true,
3335 MVPP2_PRS_TAGGED, MVPP2_PRS_EDSA);
3336 mvpp2_prs_dsa_tag_set(priv, port, true,
3337 MVPP2_PRS_UNTAGGED, MVPP2_PRS_EDSA);
3338 /* Remove port from DSA entries */
3339 mvpp2_prs_dsa_tag_set(priv, port, false,
3340 MVPP2_PRS_TAGGED, MVPP2_PRS_DSA);
3341 mvpp2_prs_dsa_tag_set(priv, port, false,
3342 MVPP2_PRS_UNTAGGED, MVPP2_PRS_DSA);
3345 case MVPP2_TAG_TYPE_DSA:
3346 /* Add port to DSA entries */
3347 mvpp2_prs_dsa_tag_set(priv, port, true,
3348 MVPP2_PRS_TAGGED, MVPP2_PRS_DSA);
3349 mvpp2_prs_dsa_tag_set(priv, port, true,
3350 MVPP2_PRS_UNTAGGED, MVPP2_PRS_DSA);
3351 /* Remove port from EDSA entries */
3352 mvpp2_prs_dsa_tag_set(priv, port, false,
3353 MVPP2_PRS_TAGGED, MVPP2_PRS_EDSA);
3354 mvpp2_prs_dsa_tag_set(priv, port, false,
3355 MVPP2_PRS_UNTAGGED, MVPP2_PRS_EDSA);
3358 case MVPP2_TAG_TYPE_MH:
3359 case MVPP2_TAG_TYPE_NONE:
3360 /* Remove port form EDSA and DSA entries */
3361 mvpp2_prs_dsa_tag_set(priv, port, false,
3362 MVPP2_PRS_TAGGED, MVPP2_PRS_DSA);
3363 mvpp2_prs_dsa_tag_set(priv, port, false,
3364 MVPP2_PRS_UNTAGGED, MVPP2_PRS_DSA);
3365 mvpp2_prs_dsa_tag_set(priv, port, false,
3366 MVPP2_PRS_TAGGED, MVPP2_PRS_EDSA);
3367 mvpp2_prs_dsa_tag_set(priv, port, false,
3368 MVPP2_PRS_UNTAGGED, MVPP2_PRS_EDSA);
3372 if ((type < 0) || (type > MVPP2_TAG_TYPE_EDSA))
3379 /* Set prs flow for the port */
3380 static int mvpp2_prs_def_flow(struct mvpp2_port *port)
3382 struct mvpp2_prs_entry *pe;
3385 pe = mvpp2_prs_flow_find(port->priv, port->id);
3387 /* Such entry not exist */
3389 /* Go through the all entires from last to first */
3390 tid = mvpp2_prs_tcam_first_free(port->priv,
3391 MVPP2_PE_LAST_FREE_TID,
3392 MVPP2_PE_FIRST_FREE_TID);
3396 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
3400 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS);
3404 mvpp2_prs_sram_ai_update(pe, port->id, MVPP2_PRS_FLOW_ID_MASK);
3405 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);
3407 /* Update shadow table */
3408 mvpp2_prs_shadow_set(port->priv, pe->index, MVPP2_PRS_LU_FLOWS);
3411 mvpp2_prs_tcam_port_map_set(pe, (1 << port->id));
3412 mvpp2_prs_hw_write(port->priv, pe);
3418 /* Classifier configuration routines */
3420 /* Update classification flow table registers */
3421 static void mvpp2_cls_flow_write(struct mvpp2 *priv,
3422 struct mvpp2_cls_flow_entry *fe)
3424 mvpp2_write(priv, MVPP2_CLS_FLOW_INDEX_REG, fe->index);
3425 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL0_REG, fe->data[0]);
3426 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL1_REG, fe->data[1]);
3427 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL2_REG, fe->data[2]);
3430 /* Update classification lookup table register */
3431 static void mvpp2_cls_lookup_write(struct mvpp2 *priv,
3432 struct mvpp2_cls_lookup_entry *le)
3436 val = (le->way << MVPP2_CLS_LKP_INDEX_WAY_OFFS) | le->lkpid;
3437 mvpp2_write(priv, MVPP2_CLS_LKP_INDEX_REG, val);
3438 mvpp2_write(priv, MVPP2_CLS_LKP_TBL_REG, le->data);
3441 /* Classifier default initialization */
3442 static void mvpp2_cls_init(struct mvpp2 *priv)
3444 struct mvpp2_cls_lookup_entry le;
3445 struct mvpp2_cls_flow_entry fe;
3448 /* Enable classifier */
3449 mvpp2_write(priv, MVPP2_CLS_MODE_REG, MVPP2_CLS_MODE_ACTIVE_MASK);
3451 /* Clear classifier flow table */
3452 memset(&fe.data, 0, sizeof(fe.data));
3453 for (index = 0; index < MVPP2_CLS_FLOWS_TBL_SIZE; index++) {
3455 mvpp2_cls_flow_write(priv, &fe);
3458 /* Clear classifier lookup table */
3460 for (index = 0; index < MVPP2_CLS_LKP_TBL_SIZE; index++) {
3463 mvpp2_cls_lookup_write(priv, &le);
3466 mvpp2_cls_lookup_write(priv, &le);
3470 static void mvpp2_cls_port_config(struct mvpp2_port *port)
3472 struct mvpp2_cls_lookup_entry le;
3475 /* Set way for the port */
3476 val = mvpp2_read(port->priv, MVPP2_CLS_PORT_WAY_REG);
3477 val &= ~MVPP2_CLS_PORT_WAY_MASK(port->id);
3478 mvpp2_write(port->priv, MVPP2_CLS_PORT_WAY_REG, val);
3480 /* Pick the entry to be accessed in lookup ID decoding table
3481 * according to the way and lkpid.
3483 le.lkpid = port->id;
3487 /* Set initial CPU queue for receiving packets */
3488 le.data &= ~MVPP2_CLS_LKP_TBL_RXQ_MASK;
3489 le.data |= port->first_rxq;
3491 /* Disable classification engines */
3492 le.data &= ~MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK;
3494 /* Update lookup ID table entry */
3495 mvpp2_cls_lookup_write(port->priv, &le);
3498 /* Set CPU queue number for oversize packets */
3499 static void mvpp2_cls_oversize_rxq_set(struct mvpp2_port *port)
3503 mvpp2_write(port->priv, MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port->id),
3504 port->first_rxq & MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK);
3506 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_P2HQ_REG(port->id),
3507 (port->first_rxq >> MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS));
3509 val = mvpp2_read(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG);
3510 val |= MVPP2_CLS_SWFWD_PCTRL_MASK(port->id);
3511 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG, val);
3514 static void *mvpp2_frag_alloc(const struct mvpp2_bm_pool *pool)
3516 if (likely(pool->frag_size <= PAGE_SIZE))
3517 return netdev_alloc_frag(pool->frag_size);
3519 return kmalloc(pool->frag_size, GFP_ATOMIC);
3522 static void mvpp2_frag_free(const struct mvpp2_bm_pool *pool, void *data)
3524 if (likely(pool->frag_size <= PAGE_SIZE))
3525 skb_free_frag(data);
3530 /* Buffer Manager configuration routines */
3533 static int mvpp2_bm_pool_create(struct platform_device *pdev,
3535 struct mvpp2_bm_pool *bm_pool, int size)
3539 /* Number of buffer pointers must be a multiple of 16, as per
3540 * hardware constraints
3542 if (!IS_ALIGNED(size, 16))
3545 /* PPv2.1 needs 8 bytes per buffer pointer, PPv2.2 needs 16
3546 * bytes per buffer pointer
3548 if (priv->hw_version == MVPP21)
3549 bm_pool->size_bytes = 2 * sizeof(u32) * size;
3551 bm_pool->size_bytes = 2 * sizeof(u64) * size;
3553 bm_pool->virt_addr = dma_alloc_coherent(&pdev->dev, bm_pool->size_bytes,
3556 if (!bm_pool->virt_addr)
3559 if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr,
3560 MVPP2_BM_POOL_PTR_ALIGN)) {
3561 dma_free_coherent(&pdev->dev, bm_pool->size_bytes,
3562 bm_pool->virt_addr, bm_pool->dma_addr);
3563 dev_err(&pdev->dev, "BM pool %d is not %d bytes aligned\n",
3564 bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN);
3568 mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id),
3569 lower_32_bits(bm_pool->dma_addr));
3570 mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size);
3572 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
3573 val |= MVPP2_BM_START_MASK;
3574 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
3576 bm_pool->type = MVPP2_BM_FREE;
3577 bm_pool->size = size;
3578 bm_pool->pkt_size = 0;
3579 bm_pool->buf_num = 0;
3584 /* Set pool buffer size */
3585 static void mvpp2_bm_pool_bufsize_set(struct mvpp2 *priv,
3586 struct mvpp2_bm_pool *bm_pool,
3591 bm_pool->buf_size = buf_size;
3593 val = ALIGN(buf_size, 1 << MVPP2_POOL_BUF_SIZE_OFFSET);
3594 mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val);
3597 static void mvpp2_bm_bufs_get_addrs(struct device *dev, struct mvpp2 *priv,
3598 struct mvpp2_bm_pool *bm_pool,
3599 dma_addr_t *dma_addr,
3600 phys_addr_t *phys_addr)
3602 *dma_addr = mvpp2_read(priv, MVPP2_BM_PHY_ALLOC_REG(bm_pool->id));
3603 *phys_addr = mvpp2_read(priv, MVPP2_BM_VIRT_ALLOC_REG);
3605 if (priv->hw_version == MVPP22) {
3607 u32 dma_addr_highbits, phys_addr_highbits;
3609 val = mvpp2_read(priv, MVPP22_BM_ADDR_HIGH_ALLOC);
3610 dma_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_PHYS_MASK);
3611 phys_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_VIRT_MASK) >>
3612 MVPP22_BM_ADDR_HIGH_VIRT_SHIFT;
3614 if (sizeof(dma_addr_t) == 8)
3615 *dma_addr |= (u64)dma_addr_highbits << 32;
3617 if (sizeof(phys_addr_t) == 8)
3618 *phys_addr |= (u64)phys_addr_highbits << 32;
3622 /* Free all buffers from the pool */
3623 static void mvpp2_bm_bufs_free(struct device *dev, struct mvpp2 *priv,
3624 struct mvpp2_bm_pool *bm_pool)
3628 for (i = 0; i < bm_pool->buf_num; i++) {
3629 dma_addr_t buf_dma_addr;
3630 phys_addr_t buf_phys_addr;
3633 mvpp2_bm_bufs_get_addrs(dev, priv, bm_pool,
3634 &buf_dma_addr, &buf_phys_addr);
3636 dma_unmap_single(dev, buf_dma_addr,
3637 bm_pool->buf_size, DMA_FROM_DEVICE);
3639 data = (void *)phys_to_virt(buf_phys_addr);
3643 mvpp2_frag_free(bm_pool, data);
3646 /* Update BM driver with number of buffers removed from pool */
3647 bm_pool->buf_num -= i;
3651 static int mvpp2_bm_pool_destroy(struct platform_device *pdev,
3653 struct mvpp2_bm_pool *bm_pool)
3657 mvpp2_bm_bufs_free(&pdev->dev, priv, bm_pool);
3658 if (bm_pool->buf_num) {
3659 WARN(1, "cannot free all buffers in pool %d\n", bm_pool->id);
3663 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
3664 val |= MVPP2_BM_STOP_MASK;
3665 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
3667 dma_free_coherent(&pdev->dev, bm_pool->size_bytes,
3673 static int mvpp2_bm_pools_init(struct platform_device *pdev,
3677 struct mvpp2_bm_pool *bm_pool;
3679 /* Create all pools with maximum size */
3680 size = MVPP2_BM_POOL_SIZE_MAX;
3681 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
3682 bm_pool = &priv->bm_pools[i];
3684 err = mvpp2_bm_pool_create(pdev, priv, bm_pool, size);
3686 goto err_unroll_pools;
3687 mvpp2_bm_pool_bufsize_set(priv, bm_pool, 0);
3692 dev_err(&pdev->dev, "failed to create BM pool %d, size %d\n", i, size);
3693 for (i = i - 1; i >= 0; i--)
3694 mvpp2_bm_pool_destroy(pdev, priv, &priv->bm_pools[i]);
3698 static int mvpp2_bm_init(struct platform_device *pdev, struct mvpp2 *priv)
3702 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
3703 /* Mask BM all interrupts */
3704 mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0);
3705 /* Clear BM cause register */
3706 mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0);
3709 /* Allocate and initialize BM pools */
3710 priv->bm_pools = devm_kcalloc(&pdev->dev, MVPP2_BM_POOLS_NUM,
3711 sizeof(struct mvpp2_bm_pool), GFP_KERNEL);
3712 if (!priv->bm_pools)
3715 err = mvpp2_bm_pools_init(pdev, priv);
3721 /* Attach long pool to rxq */
3722 static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port,
3723 int lrxq, int long_pool)
3728 /* Get queue physical ID */
3729 prxq = port->rxqs[lrxq]->id;
3731 if (port->priv->hw_version == MVPP21)
3732 mask = MVPP21_RXQ_POOL_LONG_MASK;
3734 mask = MVPP22_RXQ_POOL_LONG_MASK;
3736 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
3738 val |= (long_pool << MVPP2_RXQ_POOL_LONG_OFFS) & mask;
3739 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
3742 /* Attach short pool to rxq */
3743 static void mvpp2_rxq_short_pool_set(struct mvpp2_port *port,
3744 int lrxq, int short_pool)
3749 /* Get queue physical ID */
3750 prxq = port->rxqs[lrxq]->id;
3752 if (port->priv->hw_version == MVPP21)
3753 mask = MVPP21_RXQ_POOL_SHORT_MASK;
3755 mask = MVPP22_RXQ_POOL_SHORT_MASK;
3757 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
3759 val |= (short_pool << MVPP2_RXQ_POOL_SHORT_OFFS) & mask;
3760 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
3763 static void *mvpp2_buf_alloc(struct mvpp2_port *port,
3764 struct mvpp2_bm_pool *bm_pool,
3765 dma_addr_t *buf_dma_addr,
3766 phys_addr_t *buf_phys_addr,
3769 dma_addr_t dma_addr;
3772 data = mvpp2_frag_alloc(bm_pool);
3776 dma_addr = dma_map_single(port->dev->dev.parent, data,
3777 MVPP2_RX_BUF_SIZE(bm_pool->pkt_size),
3779 if (unlikely(dma_mapping_error(port->dev->dev.parent, dma_addr))) {
3780 mvpp2_frag_free(bm_pool, data);
3783 *buf_dma_addr = dma_addr;
3784 *buf_phys_addr = virt_to_phys(data);
3789 /* Set pool number in a BM cookie */
3790 static inline u32 mvpp2_bm_cookie_pool_set(u32 cookie, int pool)
3794 bm = cookie & ~(0xFF << MVPP2_BM_COOKIE_POOL_OFFS);
3795 bm |= ((pool & 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS);
3800 /* Get pool number from a BM cookie */
3801 static inline int mvpp2_bm_cookie_pool_get(unsigned long cookie)
3803 return (cookie >> MVPP2_BM_COOKIE_POOL_OFFS) & 0xFF;
3806 /* Release buffer to BM */
3807 static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
3808 dma_addr_t buf_dma_addr,
3809 phys_addr_t buf_phys_addr)
3811 if (port->priv->hw_version == MVPP22) {
3814 if (sizeof(dma_addr_t) == 8)
3815 val |= upper_32_bits(buf_dma_addr) &
3816 MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK;
3818 if (sizeof(phys_addr_t) == 8)
3819 val |= (upper_32_bits(buf_phys_addr)
3820 << MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT) &
3821 MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK;
3823 mvpp2_write(port->priv, MVPP22_BM_ADDR_HIGH_RLS_REG, val);
3826 /* MVPP2_BM_VIRT_RLS_REG is not interpreted by HW, and simply
3827 * returned in the "cookie" field of the RX
3828 * descriptor. Instead of storing the virtual address, we
3829 * store the physical address
3831 mvpp2_write(port->priv, MVPP2_BM_VIRT_RLS_REG, buf_phys_addr);
3832 mvpp2_write(port->priv, MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr);
3835 /* Refill BM pool */
3836 static void mvpp2_pool_refill(struct mvpp2_port *port, u32 bm,
3837 dma_addr_t dma_addr,
3838 phys_addr_t phys_addr)
3840 int pool = mvpp2_bm_cookie_pool_get(bm);
3842 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr);
3845 /* Allocate buffers for the pool */
3846 static int mvpp2_bm_bufs_add(struct mvpp2_port *port,
3847 struct mvpp2_bm_pool *bm_pool, int buf_num)
3849 int i, buf_size, total_size;
3850 dma_addr_t dma_addr;
3851 phys_addr_t phys_addr;
3854 buf_size = MVPP2_RX_BUF_SIZE(bm_pool->pkt_size);
3855 total_size = MVPP2_RX_TOTAL_SIZE(buf_size);
3858 (buf_num + bm_pool->buf_num > bm_pool->size)) {
3859 netdev_err(port->dev,
3860 "cannot allocate %d buffers for pool %d\n",
3861 buf_num, bm_pool->id);
3865 for (i = 0; i < buf_num; i++) {
3866 buf = mvpp2_buf_alloc(port, bm_pool, &dma_addr,
3867 &phys_addr, GFP_KERNEL);
3871 mvpp2_bm_pool_put(port, bm_pool->id, dma_addr,
3875 /* Update BM driver with number of buffers added to pool */
3876 bm_pool->buf_num += i;
3878 netdev_dbg(port->dev,
3879 "%s pool %d: pkt_size=%4d, buf_size=%4d, total_size=%4d\n",
3880 bm_pool->type == MVPP2_BM_SWF_SHORT ? "short" : " long",
3881 bm_pool->id, bm_pool->pkt_size, buf_size, total_size);
3883 netdev_dbg(port->dev,
3884 "%s pool %d: %d of %d buffers added\n",
3885 bm_pool->type == MVPP2_BM_SWF_SHORT ? "short" : " long",
3886 bm_pool->id, i, buf_num);
3890 /* Notify the driver that BM pool is being used as specific type and return the
3891 * pool pointer on success
3893 static struct mvpp2_bm_pool *
3894 mvpp2_bm_pool_use(struct mvpp2_port *port, int pool, enum mvpp2_bm_type type,
3897 struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool];
3900 if (new_pool->type != MVPP2_BM_FREE && new_pool->type != type) {
3901 netdev_err(port->dev, "mixing pool types is forbidden\n");
3905 if (new_pool->type == MVPP2_BM_FREE)
3906 new_pool->type = type;
3908 /* Allocate buffers in case BM pool is used as long pool, but packet
3909 * size doesn't match MTU or BM pool hasn't being used yet
3911 if (((type == MVPP2_BM_SWF_LONG) && (pkt_size > new_pool->pkt_size)) ||
3912 (new_pool->pkt_size == 0)) {
3915 /* Set default buffer number or free all the buffers in case
3916 * the pool is not empty
3918 pkts_num = new_pool->buf_num;
3920 pkts_num = type == MVPP2_BM_SWF_LONG ?
3921 MVPP2_BM_LONG_BUF_NUM :
3922 MVPP2_BM_SHORT_BUF_NUM;
3924 mvpp2_bm_bufs_free(port->dev->dev.parent,
3925 port->priv, new_pool);
3927 new_pool->pkt_size = pkt_size;
3928 new_pool->frag_size =
3929 SKB_DATA_ALIGN(MVPP2_RX_BUF_SIZE(pkt_size)) +
3930 MVPP2_SKB_SHINFO_SIZE;
3932 /* Allocate buffers for this pool */
3933 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num);
3934 if (num != pkts_num) {
3935 WARN(1, "pool %d: %d of %d allocated\n",
3936 new_pool->id, num, pkts_num);
3941 mvpp2_bm_pool_bufsize_set(port->priv, new_pool,
3942 MVPP2_RX_BUF_SIZE(new_pool->pkt_size));
3947 /* Initialize pools for swf */
3948 static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port)
3952 if (!port->pool_long) {
3954 mvpp2_bm_pool_use(port, MVPP2_BM_SWF_LONG_POOL(port->id),
3957 if (!port->pool_long)
3960 port->pool_long->port_map |= (1 << port->id);
3962 for (rxq = 0; rxq < rxq_number; rxq++)
3963 mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id);
3966 if (!port->pool_short) {
3968 mvpp2_bm_pool_use(port, MVPP2_BM_SWF_SHORT_POOL,
3970 MVPP2_BM_SHORT_PKT_SIZE);
3971 if (!port->pool_short)
3974 port->pool_short->port_map |= (1 << port->id);
3976 for (rxq = 0; rxq < rxq_number; rxq++)
3977 mvpp2_rxq_short_pool_set(port, rxq,
3978 port->pool_short->id);
3984 static int mvpp2_bm_update_mtu(struct net_device *dev, int mtu)
3986 struct mvpp2_port *port = netdev_priv(dev);
3987 struct mvpp2_bm_pool *port_pool = port->pool_long;
3988 int num, pkts_num = port_pool->buf_num;
3989 int pkt_size = MVPP2_RX_PKT_SIZE(mtu);
3991 /* Update BM pool with new buffer size */
3992 mvpp2_bm_bufs_free(dev->dev.parent, port->priv, port_pool);
3993 if (port_pool->buf_num) {
3994 WARN(1, "cannot free all buffers in pool %d\n", port_pool->id);
3998 port_pool->pkt_size = pkt_size;
3999 port_pool->frag_size = SKB_DATA_ALIGN(MVPP2_RX_BUF_SIZE(pkt_size)) +
4000 MVPP2_SKB_SHINFO_SIZE;
4001 num = mvpp2_bm_bufs_add(port, port_pool, pkts_num);
4002 if (num != pkts_num) {
4003 WARN(1, "pool %d: %d of %d allocated\n",
4004 port_pool->id, num, pkts_num);
4008 mvpp2_bm_pool_bufsize_set(port->priv, port_pool,
4009 MVPP2_RX_BUF_SIZE(port_pool->pkt_size));
4011 netdev_update_features(dev);
4015 static inline void mvpp2_interrupts_enable(struct mvpp2_port *port)
4017 int cpu, cpu_mask = 0;
4019 for_each_present_cpu(cpu)
4020 cpu_mask |= 1 << cpu;
4021 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
4022 MVPP2_ISR_ENABLE_INTERRUPT(cpu_mask));
4025 static inline void mvpp2_interrupts_disable(struct mvpp2_port *port)
4027 int cpu, cpu_mask = 0;
4029 for_each_present_cpu(cpu)
4030 cpu_mask |= 1 << cpu;
4031 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
4032 MVPP2_ISR_DISABLE_INTERRUPT(cpu_mask));
4035 /* Mask the current CPU's Rx/Tx interrupts */
4036 static void mvpp2_interrupts_mask(void *arg)
4038 struct mvpp2_port *port = arg;
4040 mvpp2_write(port->priv, MVPP2_ISR_RX_TX_MASK_REG(port->id), 0);
4043 /* Unmask the current CPU's Rx/Tx interrupts */
4044 static void mvpp2_interrupts_unmask(void *arg)
4046 struct mvpp2_port *port = arg;
4048 mvpp2_write(port->priv, MVPP2_ISR_RX_TX_MASK_REG(port->id),
4049 (MVPP2_CAUSE_MISC_SUM_MASK |
4050 MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK));
4053 /* Port configuration routines */
4055 static void mvpp2_port_mii_set(struct mvpp2_port *port)
4059 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
4061 switch (port->phy_interface) {
4062 case PHY_INTERFACE_MODE_SGMII:
4063 val |= MVPP2_GMAC_INBAND_AN_MASK;
4065 case PHY_INTERFACE_MODE_RGMII:
4066 val |= MVPP2_GMAC_PORT_RGMII_MASK;
4068 val &= ~MVPP2_GMAC_PCS_ENABLE_MASK;
4071 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
4074 static void mvpp2_port_fc_adv_enable(struct mvpp2_port *port)
4078 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4079 val |= MVPP2_GMAC_FC_ADV_EN;
4080 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4083 static void mvpp2_port_enable(struct mvpp2_port *port)
4087 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
4088 val |= MVPP2_GMAC_PORT_EN_MASK;
4089 val |= MVPP2_GMAC_MIB_CNTR_EN_MASK;
4090 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
4093 static void mvpp2_port_disable(struct mvpp2_port *port)
4097 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
4098 val &= ~(MVPP2_GMAC_PORT_EN_MASK);
4099 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
4102 /* Set IEEE 802.3x Flow Control Xon Packet Transmission Mode */
4103 static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port)
4107 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) &
4108 ~MVPP2_GMAC_PERIODIC_XON_EN_MASK;
4109 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
4112 /* Configure loopback port */
4113 static void mvpp2_port_loopback_set(struct mvpp2_port *port)
4117 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
4119 if (port->speed == 1000)
4120 val |= MVPP2_GMAC_GMII_LB_EN_MASK;
4122 val &= ~MVPP2_GMAC_GMII_LB_EN_MASK;
4124 if (port->phy_interface == PHY_INTERFACE_MODE_SGMII)
4125 val |= MVPP2_GMAC_PCS_LB_EN_MASK;
4127 val &= ~MVPP2_GMAC_PCS_LB_EN_MASK;
4129 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
4132 static void mvpp2_port_reset(struct mvpp2_port *port)
4136 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
4137 ~MVPP2_GMAC_PORT_RESET_MASK;
4138 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
4140 while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
4141 MVPP2_GMAC_PORT_RESET_MASK)
4145 /* Change maximum receive size of the port */
4146 static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port)
4150 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
4151 val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK;
4152 val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) <<
4153 MVPP2_GMAC_MAX_RX_SIZE_OFFS);
4154 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
4157 /* Set defaults to the MVPP2 port */
4158 static void mvpp2_defaults_set(struct mvpp2_port *port)
4160 int tx_port_num, val, queue, ptxq, lrxq;
4162 if (port->priv->hw_version == MVPP21) {
4163 /* Configure port to loopback if needed */
4164 if (port->flags & MVPP2_F_LOOPBACK)
4165 mvpp2_port_loopback_set(port);
4167 /* Update TX FIFO MIN Threshold */
4168 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
4169 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
4170 /* Min. TX threshold must be less than minimal packet length */
4171 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2);
4172 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
4175 /* Disable Legacy WRR, Disable EJP, Release from reset */
4176 tx_port_num = mvpp2_egress_port(port);
4177 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG,
4179 mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0);
4181 /* Close bandwidth for all queues */
4182 for (queue = 0; queue < MVPP2_MAX_TXQ; queue++) {
4183 ptxq = mvpp2_txq_phys(port->id, queue);
4184 mvpp2_write(port->priv,
4185 MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(ptxq), 0);
4188 /* Set refill period to 1 usec, refill tokens
4189 * and bucket size to maximum
4191 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG,
4192 port->priv->tclk / USEC_PER_SEC);
4193 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG);
4194 val &= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK;
4195 val |= MVPP2_TXP_REFILL_PERIOD_MASK(1);
4196 val |= MVPP2_TXP_REFILL_TOKENS_ALL_MASK;
4197 mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val);
4198 val = MVPP2_TXP_TOKEN_SIZE_MAX;
4199 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
4201 /* Set MaximumLowLatencyPacketSize value to 256 */
4202 mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id),
4203 MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK |
4204 MVPP2_RX_LOW_LATENCY_PKT_SIZE(256));
4206 /* Enable Rx cache snoop */
4207 for (lrxq = 0; lrxq < rxq_number; lrxq++) {
4208 queue = port->rxqs[lrxq]->id;
4209 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
4210 val |= MVPP2_SNOOP_PKT_SIZE_MASK |
4211 MVPP2_SNOOP_BUF_HDR_MASK;
4212 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
4215 /* At default, mask all interrupts to all present cpus */
4216 mvpp2_interrupts_disable(port);
4219 /* Enable/disable receiving packets */
4220 static void mvpp2_ingress_enable(struct mvpp2_port *port)
4225 for (lrxq = 0; lrxq < rxq_number; lrxq++) {
4226 queue = port->rxqs[lrxq]->id;
4227 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
4228 val &= ~MVPP2_RXQ_DISABLE_MASK;
4229 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
4233 static void mvpp2_ingress_disable(struct mvpp2_port *port)
4238 for (lrxq = 0; lrxq < rxq_number; lrxq++) {
4239 queue = port->rxqs[lrxq]->id;
4240 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
4241 val |= MVPP2_RXQ_DISABLE_MASK;
4242 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
4246 /* Enable transmit via physical egress queue
4247 * - HW starts take descriptors from DRAM
4249 static void mvpp2_egress_enable(struct mvpp2_port *port)
4253 int tx_port_num = mvpp2_egress_port(port);
4255 /* Enable all initialized TXs. */
4257 for (queue = 0; queue < txq_number; queue++) {
4258 struct mvpp2_tx_queue *txq = port->txqs[queue];
4260 if (txq->descs != NULL)
4261 qmap |= (1 << queue);
4264 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
4265 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap);
4268 /* Disable transmit via physical egress queue
4269 * - HW doesn't take descriptors from DRAM
4271 static void mvpp2_egress_disable(struct mvpp2_port *port)
4275 int tx_port_num = mvpp2_egress_port(port);
4277 /* Issue stop command for active channels only */
4278 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
4279 reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) &
4280 MVPP2_TXP_SCHED_ENQ_MASK;
4282 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG,
4283 (reg_data << MVPP2_TXP_SCHED_DISQ_OFFSET));
4285 /* Wait for all Tx activity to terminate. */
4288 if (delay >= MVPP2_TX_DISABLE_TIMEOUT_MSEC) {
4289 netdev_warn(port->dev,
4290 "Tx stop timed out, status=0x%08x\n",
4297 /* Check port TX Command register that all
4298 * Tx queues are stopped
4300 reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG);
4301 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK);
4304 /* Rx descriptors helper methods */
4306 /* Get number of Rx descriptors occupied by received packets */
4308 mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id)
4310 u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id));
4312 return val & MVPP2_RXQ_OCCUPIED_MASK;
4315 /* Update Rx queue status with the number of occupied and available
4316 * Rx descriptor slots.
4319 mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id,
4320 int used_count, int free_count)
4322 /* Decrement the number of used descriptors and increment count
4323 * increment the number of free descriptors.
4325 u32 val = used_count | (free_count << MVPP2_RXQ_NUM_NEW_OFFSET);
4327 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val);
4330 /* Get pointer to next RX descriptor to be processed by SW */
4331 static inline struct mvpp2_rx_desc *
4332 mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue *rxq)
4334 int rx_desc = rxq->next_desc_to_proc;
4336 rxq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(rxq, rx_desc);
4337 prefetch(rxq->descs + rxq->next_desc_to_proc);
4338 return rxq->descs + rx_desc;
4341 /* Set rx queue offset */
4342 static void mvpp2_rxq_offset_set(struct mvpp2_port *port,
4343 int prxq, int offset)
4347 /* Convert offset from bytes to units of 32 bytes */
4348 offset = offset >> 5;
4350 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
4351 val &= ~MVPP2_RXQ_PACKET_OFFSET_MASK;
4354 val |= ((offset << MVPP2_RXQ_PACKET_OFFSET_OFFS) &
4355 MVPP2_RXQ_PACKET_OFFSET_MASK);
4357 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
4360 /* Obtain BM cookie information from descriptor */
4361 static u32 mvpp2_bm_cookie_build(struct mvpp2_port *port,
4362 struct mvpp2_rx_desc *rx_desc)
4364 int cpu = smp_processor_id();
4367 pool = (mvpp2_rxdesc_status_get(port, rx_desc) &
4368 MVPP2_RXD_BM_POOL_ID_MASK) >>
4369 MVPP2_RXD_BM_POOL_ID_OFFS;
4371 return ((pool & 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS) |
4372 ((cpu & 0xFF) << MVPP2_BM_COOKIE_CPU_OFFS);
4375 /* Tx descriptors helper methods */
4377 /* Get pointer to next Tx descriptor to be processed (send) by HW */
4378 static struct mvpp2_tx_desc *
4379 mvpp2_txq_next_desc_get(struct mvpp2_tx_queue *txq)
4381 int tx_desc = txq->next_desc_to_proc;
4383 txq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(txq, tx_desc);
4384 return txq->descs + tx_desc;
4387 /* Update HW with number of aggregated Tx descriptors to be sent */
4388 static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending)
4390 /* aggregated access - relevant TXQ number is written in TX desc */
4391 mvpp2_write(port->priv, MVPP2_AGGR_TXQ_UPDATE_REG, pending);
4395 /* Check if there are enough free descriptors in aggregated txq.
4396 * If not, update the number of occupied descriptors and repeat the check.
4398 static int mvpp2_aggr_desc_num_check(struct mvpp2 *priv,
4399 struct mvpp2_tx_queue *aggr_txq, int num)
4401 if ((aggr_txq->count + num) > aggr_txq->size) {
4402 /* Update number of occupied aggregated Tx descriptors */
4403 int cpu = smp_processor_id();
4404 u32 val = mvpp2_read(priv, MVPP2_AGGR_TXQ_STATUS_REG(cpu));
4406 aggr_txq->count = val & MVPP2_AGGR_TXQ_PENDING_MASK;
4409 if ((aggr_txq->count + num) > aggr_txq->size)
4415 /* Reserved Tx descriptors allocation request */
4416 static int mvpp2_txq_alloc_reserved_desc(struct mvpp2 *priv,
4417 struct mvpp2_tx_queue *txq, int num)
4421 val = (txq->id << MVPP2_TXQ_RSVD_REQ_Q_OFFSET) | num;
4422 mvpp2_write(priv, MVPP2_TXQ_RSVD_REQ_REG, val);
4424 val = mvpp2_read(priv, MVPP2_TXQ_RSVD_RSLT_REG);
4426 return val & MVPP2_TXQ_RSVD_RSLT_MASK;
4429 /* Check if there are enough reserved descriptors for transmission.
4430 * If not, request chunk of reserved descriptors and check again.
4432 static int mvpp2_txq_reserved_desc_num_proc(struct mvpp2 *priv,
4433 struct mvpp2_tx_queue *txq,
4434 struct mvpp2_txq_pcpu *txq_pcpu,
4437 int req, cpu, desc_count;
4439 if (txq_pcpu->reserved_num >= num)
4442 /* Not enough descriptors reserved! Update the reserved descriptor
4443 * count and check again.
4447 /* Compute total of used descriptors */
4448 for_each_present_cpu(cpu) {
4449 struct mvpp2_txq_pcpu *txq_pcpu_aux;
4451 txq_pcpu_aux = per_cpu_ptr(txq->pcpu, cpu);
4452 desc_count += txq_pcpu_aux->count;
4453 desc_count += txq_pcpu_aux->reserved_num;
4456 req = max(MVPP2_CPU_DESC_CHUNK, num - txq_pcpu->reserved_num);
4460 (txq->size - (num_present_cpus() * MVPP2_CPU_DESC_CHUNK)))
4463 txq_pcpu->reserved_num += mvpp2_txq_alloc_reserved_desc(priv, txq, req);
4465 /* OK, the descriptor cound has been updated: check again. */
4466 if (txq_pcpu->reserved_num < num)
4471 /* Release the last allocated Tx descriptor. Useful to handle DMA
4472 * mapping failures in the Tx path.
4474 static void mvpp2_txq_desc_put(struct mvpp2_tx_queue *txq)
4476 if (txq->next_desc_to_proc == 0)
4477 txq->next_desc_to_proc = txq->last_desc - 1;
4479 txq->next_desc_to_proc--;
4482 /* Set Tx descriptors fields relevant for CSUM calculation */
4483 static u32 mvpp2_txq_desc_csum(int l3_offs, int l3_proto,
4484 int ip_hdr_len, int l4_proto)
4488 /* fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk,
4489 * G_L4_chk, L4_type required only for checksum calculation
4491 command = (l3_offs << MVPP2_TXD_L3_OFF_SHIFT);
4492 command |= (ip_hdr_len << MVPP2_TXD_IP_HLEN_SHIFT);
4493 command |= MVPP2_TXD_IP_CSUM_DISABLE;
4495 if (l3_proto == swab16(ETH_P_IP)) {
4496 command &= ~MVPP2_TXD_IP_CSUM_DISABLE; /* enable IPv4 csum */
4497 command &= ~MVPP2_TXD_L3_IP6; /* enable IPv4 */
4499 command |= MVPP2_TXD_L3_IP6; /* enable IPv6 */
4502 if (l4_proto == IPPROTO_TCP) {
4503 command &= ~MVPP2_TXD_L4_UDP; /* enable TCP */
4504 command &= ~MVPP2_TXD_L4_CSUM_FRAG; /* generate L4 csum */
4505 } else if (l4_proto == IPPROTO_UDP) {
4506 command |= MVPP2_TXD_L4_UDP; /* enable UDP */
4507 command &= ~MVPP2_TXD_L4_CSUM_FRAG; /* generate L4 csum */
4509 command |= MVPP2_TXD_L4_CSUM_NOT;
4515 /* Get number of sent descriptors and decrement counter.
4516 * The number of sent descriptors is returned.
4519 static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port,
4520 struct mvpp2_tx_queue *txq)
4524 /* Reading status reg resets transmitted descriptor counter */
4525 val = mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(txq->id));
4527 return (val & MVPP2_TRANSMITTED_COUNT_MASK) >>
4528 MVPP2_TRANSMITTED_COUNT_OFFSET;
4531 static void mvpp2_txq_sent_counter_clear(void *arg)
4533 struct mvpp2_port *port = arg;
4536 for (queue = 0; queue < txq_number; queue++) {
4537 int id = port->txqs[queue]->id;
4539 mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(id));
4543 /* Set max sizes for Tx queues */
4544 static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port)
4547 int txq, tx_port_num;
4549 mtu = port->pkt_size * 8;
4550 if (mtu > MVPP2_TXP_MTU_MAX)
4551 mtu = MVPP2_TXP_MTU_MAX;
4553 /* WA for wrong Token bucket update: Set MTU value = 3*real MTU value */
4556 /* Indirect access to registers */
4557 tx_port_num = mvpp2_egress_port(port);
4558 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
4561 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG);
4562 val &= ~MVPP2_TXP_MTU_MAX;
4564 mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val);
4566 /* TXP token size and all TXQs token size must be larger that MTU */
4567 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG);
4568 size = val & MVPP2_TXP_TOKEN_SIZE_MAX;
4571 val &= ~MVPP2_TXP_TOKEN_SIZE_MAX;
4573 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
4576 for (txq = 0; txq < txq_number; txq++) {
4577 val = mvpp2_read(port->priv,
4578 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq));
4579 size = val & MVPP2_TXQ_TOKEN_SIZE_MAX;
4583 val &= ~MVPP2_TXQ_TOKEN_SIZE_MAX;
4585 mvpp2_write(port->priv,
4586 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq),
4592 /* Set the number of packets that will be received before Rx interrupt
4593 * will be generated by HW.
4595 static void mvpp2_rx_pkts_coal_set(struct mvpp2_port *port,
4596 struct mvpp2_rx_queue *rxq)
4598 if (rxq->pkts_coal > MVPP2_OCCUPIED_THRESH_MASK)
4599 rxq->pkts_coal = MVPP2_OCCUPIED_THRESH_MASK;
4601 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
4602 mvpp2_write(port->priv, MVPP2_RXQ_THRESH_REG,
4606 static u32 mvpp2_usec_to_cycles(u32 usec, unsigned long clk_hz)
4608 u64 tmp = (u64)clk_hz * usec;
4610 do_div(tmp, USEC_PER_SEC);
4612 return tmp > U32_MAX ? U32_MAX : tmp;
4615 static u32 mvpp2_cycles_to_usec(u32 cycles, unsigned long clk_hz)
4617 u64 tmp = (u64)cycles * USEC_PER_SEC;
4619 do_div(tmp, clk_hz);
4621 return tmp > U32_MAX ? U32_MAX : tmp;
4624 /* Set the time delay in usec before Rx interrupt */
4625 static void mvpp2_rx_time_coal_set(struct mvpp2_port *port,
4626 struct mvpp2_rx_queue *rxq)
4628 unsigned long freq = port->priv->tclk;
4629 u32 val = mvpp2_usec_to_cycles(rxq->time_coal, freq);
4631 if (val > MVPP2_MAX_ISR_RX_THRESHOLD) {
4633 mvpp2_cycles_to_usec(MVPP2_MAX_ISR_RX_THRESHOLD, freq);
4635 /* re-evaluate to get actual register value */
4636 val = mvpp2_usec_to_cycles(rxq->time_coal, freq);
4639 mvpp2_write(port->priv, MVPP2_ISR_RX_THRESHOLD_REG(rxq->id), val);
4642 /* Free Tx queue skbuffs */
4643 static void mvpp2_txq_bufs_free(struct mvpp2_port *port,
4644 struct mvpp2_tx_queue *txq,
4645 struct mvpp2_txq_pcpu *txq_pcpu, int num)
4649 for (i = 0; i < num; i++) {
4650 struct mvpp2_txq_pcpu_buf *tx_buf =
4651 txq_pcpu->buffs + txq_pcpu->txq_get_index;
4653 dma_unmap_single(port->dev->dev.parent, tx_buf->dma,
4654 tx_buf->size, DMA_TO_DEVICE);
4656 dev_kfree_skb_any(tx_buf->skb);
4658 mvpp2_txq_inc_get(txq_pcpu);
4662 static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port,
4665 int queue = fls(cause) - 1;
4667 return port->rxqs[queue];
4670 static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port,
4673 int queue = fls(cause) - 1;
4675 return port->txqs[queue];
4678 /* Handle end of transmission */
4679 static void mvpp2_txq_done(struct mvpp2_port *port, struct mvpp2_tx_queue *txq,
4680 struct mvpp2_txq_pcpu *txq_pcpu)
4682 struct netdev_queue *nq = netdev_get_tx_queue(port->dev, txq->log_id);
4685 if (txq_pcpu->cpu != smp_processor_id())
4686 netdev_err(port->dev, "wrong cpu on the end of Tx processing\n");
4688 tx_done = mvpp2_txq_sent_desc_proc(port, txq);
4691 mvpp2_txq_bufs_free(port, txq, txq_pcpu, tx_done);
4693 txq_pcpu->count -= tx_done;
4695 if (netif_tx_queue_stopped(nq))
4696 if (txq_pcpu->size - txq_pcpu->count >= MAX_SKB_FRAGS + 1)
4697 netif_tx_wake_queue(nq);
4700 static unsigned int mvpp2_tx_done(struct mvpp2_port *port, u32 cause)
4702 struct mvpp2_tx_queue *txq;
4703 struct mvpp2_txq_pcpu *txq_pcpu;
4704 unsigned int tx_todo = 0;
4707 txq = mvpp2_get_tx_queue(port, cause);
4711 txq_pcpu = this_cpu_ptr(txq->pcpu);
4713 if (txq_pcpu->count) {
4714 mvpp2_txq_done(port, txq, txq_pcpu);
4715 tx_todo += txq_pcpu->count;
4718 cause &= ~(1 << txq->log_id);
4723 /* Rx/Tx queue initialization/cleanup methods */
4725 /* Allocate and initialize descriptors for aggr TXQ */
4726 static int mvpp2_aggr_txq_init(struct platform_device *pdev,
4727 struct mvpp2_tx_queue *aggr_txq,
4728 int desc_num, int cpu,
4733 /* Allocate memory for TX descriptors */
4734 aggr_txq->descs = dma_alloc_coherent(&pdev->dev,
4735 desc_num * MVPP2_DESC_ALIGNED_SIZE,
4736 &aggr_txq->descs_dma, GFP_KERNEL);
4737 if (!aggr_txq->descs)
4740 aggr_txq->last_desc = aggr_txq->size - 1;
4742 /* Aggr TXQ no reset WA */
4743 aggr_txq->next_desc_to_proc = mvpp2_read(priv,
4744 MVPP2_AGGR_TXQ_INDEX_REG(cpu));
4746 /* Set Tx descriptors queue starting address indirect
4749 if (priv->hw_version == MVPP21)
4750 txq_dma = aggr_txq->descs_dma;
4752 txq_dma = aggr_txq->descs_dma >>
4753 MVPP22_AGGR_TXQ_DESC_ADDR_OFFS;
4755 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu), txq_dma);
4756 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu), desc_num);
4761 /* Create a specified Rx queue */
4762 static int mvpp2_rxq_init(struct mvpp2_port *port,
4763 struct mvpp2_rx_queue *rxq)
4768 rxq->size = port->rx_ring_size;
4770 /* Allocate memory for RX descriptors */
4771 rxq->descs = dma_alloc_coherent(port->dev->dev.parent,
4772 rxq->size * MVPP2_DESC_ALIGNED_SIZE,
4773 &rxq->descs_dma, GFP_KERNEL);
4777 rxq->last_desc = rxq->size - 1;
4779 /* Zero occupied and non-occupied counters - direct access */
4780 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
4782 /* Set Rx descriptors queue starting address - indirect access */
4783 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
4784 if (port->priv->hw_version == MVPP21)
4785 rxq_dma = rxq->descs_dma;
4787 rxq_dma = rxq->descs_dma >> MVPP22_DESC_ADDR_OFFS;
4788 mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma);
4789 mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, rxq->size);
4790 mvpp2_write(port->priv, MVPP2_RXQ_INDEX_REG, 0);
4793 mvpp2_rxq_offset_set(port, rxq->id, NET_SKB_PAD);
4795 /* Set coalescing pkts and time */
4796 mvpp2_rx_pkts_coal_set(port, rxq);
4797 mvpp2_rx_time_coal_set(port, rxq);
4799 /* Add number of descriptors ready for receiving packets */
4800 mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size);
4805 /* Push packets received by the RXQ to BM pool */
4806 static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port,
4807 struct mvpp2_rx_queue *rxq)
4811 rx_received = mvpp2_rxq_received(port, rxq->id);
4815 for (i = 0; i < rx_received; i++) {
4816 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
4817 u32 bm = mvpp2_bm_cookie_build(port, rx_desc);
4819 mvpp2_pool_refill(port, bm,
4820 mvpp2_rxdesc_dma_addr_get(port, rx_desc),
4821 mvpp2_rxdesc_cookie_get(port, rx_desc));
4823 mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received);
4826 /* Cleanup Rx queue */
4827 static void mvpp2_rxq_deinit(struct mvpp2_port *port,
4828 struct mvpp2_rx_queue *rxq)
4830 mvpp2_rxq_drop_pkts(port, rxq);
4833 dma_free_coherent(port->dev->dev.parent,
4834 rxq->size * MVPP2_DESC_ALIGNED_SIZE,
4840 rxq->next_desc_to_proc = 0;
4843 /* Clear Rx descriptors queue starting address and size;
4844 * free descriptor number
4846 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
4847 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
4848 mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, 0);
4849 mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, 0);
4852 /* Create and initialize a Tx queue */
4853 static int mvpp2_txq_init(struct mvpp2_port *port,
4854 struct mvpp2_tx_queue *txq)
4857 int cpu, desc, desc_per_txq, tx_port_num;
4858 struct mvpp2_txq_pcpu *txq_pcpu;
4860 txq->size = port->tx_ring_size;
4862 /* Allocate memory for Tx descriptors */
4863 txq->descs = dma_alloc_coherent(port->dev->dev.parent,
4864 txq->size * MVPP2_DESC_ALIGNED_SIZE,
4865 &txq->descs_dma, GFP_KERNEL);
4869 txq->last_desc = txq->size - 1;
4871 /* Set Tx descriptors queue starting address - indirect access */
4872 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
4873 mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, txq->descs_dma);
4874 mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, txq->size &
4875 MVPP2_TXQ_DESC_SIZE_MASK);
4876 mvpp2_write(port->priv, MVPP2_TXQ_INDEX_REG, 0);
4877 mvpp2_write(port->priv, MVPP2_TXQ_RSVD_CLR_REG,
4878 txq->id << MVPP2_TXQ_RSVD_CLR_OFFSET);
4879 val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG);
4880 val &= ~MVPP2_TXQ_PENDING_MASK;
4881 mvpp2_write(port->priv, MVPP2_TXQ_PENDING_REG, val);
4883 /* Calculate base address in prefetch buffer. We reserve 16 descriptors
4884 * for each existing TXQ.
4885 * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT
4886 * GBE ports assumed to be continious from 0 to MVPP2_MAX_PORTS
4889 desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) +
4890 (txq->log_id * desc_per_txq);
4892 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG,
4893 MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 |
4894 MVPP2_PREF_BUF_THRESH(desc_per_txq/2));
4896 /* WRR / EJP configuration - indirect access */
4897 tx_port_num = mvpp2_egress_port(port);
4898 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
4900 val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id));
4901 val &= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK;
4902 val |= MVPP2_TXQ_REFILL_PERIOD_MASK(1);
4903 val |= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK;
4904 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val);
4906 val = MVPP2_TXQ_TOKEN_SIZE_MAX;
4907 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id),
4910 for_each_present_cpu(cpu) {
4911 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
4912 txq_pcpu->size = txq->size;
4913 txq_pcpu->buffs = kmalloc(txq_pcpu->size *
4914 sizeof(struct mvpp2_txq_pcpu_buf),
4916 if (!txq_pcpu->buffs)
4919 txq_pcpu->count = 0;
4920 txq_pcpu->reserved_num = 0;
4921 txq_pcpu->txq_put_index = 0;
4922 txq_pcpu->txq_get_index = 0;
4928 for_each_present_cpu(cpu) {
4929 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
4930 kfree(txq_pcpu->buffs);
4933 dma_free_coherent(port->dev->dev.parent,
4934 txq->size * MVPP2_DESC_ALIGNED_SIZE,
4935 txq->descs, txq->descs_dma);
4940 /* Free allocated TXQ resources */
4941 static void mvpp2_txq_deinit(struct mvpp2_port *port,
4942 struct mvpp2_tx_queue *txq)
4944 struct mvpp2_txq_pcpu *txq_pcpu;
4947 for_each_present_cpu(cpu) {
4948 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
4949 kfree(txq_pcpu->buffs);
4953 dma_free_coherent(port->dev->dev.parent,
4954 txq->size * MVPP2_DESC_ALIGNED_SIZE,
4955 txq->descs, txq->descs_dma);
4959 txq->next_desc_to_proc = 0;
4962 /* Set minimum bandwidth for disabled TXQs */
4963 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->id), 0);
4965 /* Set Tx descriptors queue starting address and size */
4966 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
4967 mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, 0);
4968 mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, 0);
4971 /* Cleanup Tx ports */
4972 static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq)
4974 struct mvpp2_txq_pcpu *txq_pcpu;
4975 int delay, pending, cpu;
4978 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
4979 val = mvpp2_read(port->priv, MVPP2_TXQ_PREF_BUF_REG);
4980 val |= MVPP2_TXQ_DRAIN_EN_MASK;
4981 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
4983 /* The napi queue has been stopped so wait for all packets
4984 * to be transmitted.
4988 if (delay >= MVPP2_TX_PENDING_TIMEOUT_MSEC) {
4989 netdev_warn(port->dev,
4990 "port %d: cleaning queue %d timed out\n",
4991 port->id, txq->log_id);
4997 pending = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG) &
4998 MVPP2_TXQ_PENDING_MASK;
5001 val &= ~MVPP2_TXQ_DRAIN_EN_MASK;
5002 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
5004 for_each_present_cpu(cpu) {
5005 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
5007 /* Release all packets */
5008 mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count);
5011 txq_pcpu->count = 0;
5012 txq_pcpu->txq_put_index = 0;
5013 txq_pcpu->txq_get_index = 0;
5017 /* Cleanup all Tx queues */
5018 static void mvpp2_cleanup_txqs(struct mvpp2_port *port)
5020 struct mvpp2_tx_queue *txq;
5024 val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG);
5026 /* Reset Tx ports and delete Tx queues */
5027 val |= MVPP2_TX_PORT_FLUSH_MASK(port->id);
5028 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
5030 for (queue = 0; queue < txq_number; queue++) {
5031 txq = port->txqs[queue];
5032 mvpp2_txq_clean(port, txq);
5033 mvpp2_txq_deinit(port, txq);
5036 on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1);
5038 val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id);
5039 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
5042 /* Cleanup all Rx queues */
5043 static void mvpp2_cleanup_rxqs(struct mvpp2_port *port)
5047 for (queue = 0; queue < rxq_number; queue++)
5048 mvpp2_rxq_deinit(port, port->rxqs[queue]);
5051 /* Init all Rx queues for port */
5052 static int mvpp2_setup_rxqs(struct mvpp2_port *port)
5056 for (queue = 0; queue < rxq_number; queue++) {
5057 err = mvpp2_rxq_init(port, port->rxqs[queue]);
5064 mvpp2_cleanup_rxqs(port);
5068 /* Init all tx queues for port */
5069 static int mvpp2_setup_txqs(struct mvpp2_port *port)
5071 struct mvpp2_tx_queue *txq;
5074 for (queue = 0; queue < txq_number; queue++) {
5075 txq = port->txqs[queue];
5076 err = mvpp2_txq_init(port, txq);
5081 on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1);
5085 mvpp2_cleanup_txqs(port);
5089 /* The callback for per-port interrupt */
5090 static irqreturn_t mvpp2_isr(int irq, void *dev_id)
5092 struct mvpp2_port *port = (struct mvpp2_port *)dev_id;
5094 mvpp2_interrupts_disable(port);
5096 napi_schedule(&port->napi);
5102 static void mvpp2_link_event(struct net_device *dev)
5104 struct mvpp2_port *port = netdev_priv(dev);
5105 struct phy_device *phydev = dev->phydev;
5106 int status_change = 0;
5110 if ((port->speed != phydev->speed) ||
5111 (port->duplex != phydev->duplex)) {
5114 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
5115 val &= ~(MVPP2_GMAC_CONFIG_MII_SPEED |
5116 MVPP2_GMAC_CONFIG_GMII_SPEED |
5117 MVPP2_GMAC_CONFIG_FULL_DUPLEX |
5118 MVPP2_GMAC_AN_SPEED_EN |
5119 MVPP2_GMAC_AN_DUPLEX_EN);
5122 val |= MVPP2_GMAC_CONFIG_FULL_DUPLEX;
5124 if (phydev->speed == SPEED_1000)
5125 val |= MVPP2_GMAC_CONFIG_GMII_SPEED;
5126 else if (phydev->speed == SPEED_100)
5127 val |= MVPP2_GMAC_CONFIG_MII_SPEED;
5129 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
5131 port->duplex = phydev->duplex;
5132 port->speed = phydev->speed;
5136 if (phydev->link != port->link) {
5137 if (!phydev->link) {
5142 port->link = phydev->link;
5146 if (status_change) {
5148 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
5149 val |= (MVPP2_GMAC_FORCE_LINK_PASS |
5150 MVPP2_GMAC_FORCE_LINK_DOWN);
5151 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
5152 mvpp2_egress_enable(port);
5153 mvpp2_ingress_enable(port);
5155 mvpp2_ingress_disable(port);
5156 mvpp2_egress_disable(port);
5158 phy_print_status(phydev);
5162 static void mvpp2_timer_set(struct mvpp2_port_pcpu *port_pcpu)
5166 if (!port_pcpu->timer_scheduled) {
5167 port_pcpu->timer_scheduled = true;
5168 interval = MVPP2_TXDONE_HRTIMER_PERIOD_NS;
5169 hrtimer_start(&port_pcpu->tx_done_timer, interval,
5170 HRTIMER_MODE_REL_PINNED);
5174 static void mvpp2_tx_proc_cb(unsigned long data)
5176 struct net_device *dev = (struct net_device *)data;
5177 struct mvpp2_port *port = netdev_priv(dev);
5178 struct mvpp2_port_pcpu *port_pcpu = this_cpu_ptr(port->pcpu);
5179 unsigned int tx_todo, cause;
5181 if (!netif_running(dev))
5183 port_pcpu->timer_scheduled = false;
5185 /* Process all the Tx queues */
5186 cause = (1 << txq_number) - 1;
5187 tx_todo = mvpp2_tx_done(port, cause);
5189 /* Set the timer in case not all the packets were processed */
5191 mvpp2_timer_set(port_pcpu);
5194 static enum hrtimer_restart mvpp2_hr_timer_cb(struct hrtimer *timer)
5196 struct mvpp2_port_pcpu *port_pcpu = container_of(timer,
5197 struct mvpp2_port_pcpu,
5200 tasklet_schedule(&port_pcpu->tx_done_tasklet);
5202 return HRTIMER_NORESTART;
5205 /* Main RX/TX processing routines */
5207 /* Display more error info */
5208 static void mvpp2_rx_error(struct mvpp2_port *port,
5209 struct mvpp2_rx_desc *rx_desc)
5211 u32 status = mvpp2_rxdesc_status_get(port, rx_desc);
5212 size_t sz = mvpp2_rxdesc_size_get(port, rx_desc);
5214 switch (status & MVPP2_RXD_ERR_CODE_MASK) {
5215 case MVPP2_RXD_ERR_CRC:
5216 netdev_err(port->dev, "bad rx status %08x (crc error), size=%zu\n",
5219 case MVPP2_RXD_ERR_OVERRUN:
5220 netdev_err(port->dev, "bad rx status %08x (overrun error), size=%zu\n",
5223 case MVPP2_RXD_ERR_RESOURCE:
5224 netdev_err(port->dev, "bad rx status %08x (resource error), size=%zu\n",
5230 /* Handle RX checksum offload */
5231 static void mvpp2_rx_csum(struct mvpp2_port *port, u32 status,
5232 struct sk_buff *skb)
5234 if (((status & MVPP2_RXD_L3_IP4) &&
5235 !(status & MVPP2_RXD_IP4_HEADER_ERR)) ||
5236 (status & MVPP2_RXD_L3_IP6))
5237 if (((status & MVPP2_RXD_L4_UDP) ||
5238 (status & MVPP2_RXD_L4_TCP)) &&
5239 (status & MVPP2_RXD_L4_CSUM_OK)) {
5241 skb->ip_summed = CHECKSUM_UNNECESSARY;
5245 skb->ip_summed = CHECKSUM_NONE;
5248 /* Reuse skb if possible, or allocate a new skb and add it to BM pool */
5249 static int mvpp2_rx_refill(struct mvpp2_port *port,
5250 struct mvpp2_bm_pool *bm_pool, u32 bm)
5252 dma_addr_t dma_addr;
5253 phys_addr_t phys_addr;
5256 /* No recycle or too many buffers are in use, so allocate a new skb */
5257 buf = mvpp2_buf_alloc(port, bm_pool, &dma_addr, &phys_addr,
5262 mvpp2_pool_refill(port, bm, dma_addr, phys_addr);
5267 /* Handle tx checksum */
5268 static u32 mvpp2_skb_tx_csum(struct mvpp2_port *port, struct sk_buff *skb)
5270 if (skb->ip_summed == CHECKSUM_PARTIAL) {
5274 if (skb->protocol == htons(ETH_P_IP)) {
5275 struct iphdr *ip4h = ip_hdr(skb);
5277 /* Calculate IPv4 checksum and L4 checksum */
5278 ip_hdr_len = ip4h->ihl;
5279 l4_proto = ip4h->protocol;
5280 } else if (skb->protocol == htons(ETH_P_IPV6)) {
5281 struct ipv6hdr *ip6h = ipv6_hdr(skb);
5283 /* Read l4_protocol from one of IPv6 extra headers */
5284 if (skb_network_header_len(skb) > 0)
5285 ip_hdr_len = (skb_network_header_len(skb) >> 2);
5286 l4_proto = ip6h->nexthdr;
5288 return MVPP2_TXD_L4_CSUM_NOT;
5291 return mvpp2_txq_desc_csum(skb_network_offset(skb),
5292 skb->protocol, ip_hdr_len, l4_proto);
5295 return MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE;
5298 /* Main rx processing */
5299 static int mvpp2_rx(struct mvpp2_port *port, int rx_todo,
5300 struct mvpp2_rx_queue *rxq)
5302 struct net_device *dev = port->dev;
5308 /* Get number of received packets and clamp the to-do */
5309 rx_received = mvpp2_rxq_received(port, rxq->id);
5310 if (rx_todo > rx_received)
5311 rx_todo = rx_received;
5313 while (rx_done < rx_todo) {
5314 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
5315 struct mvpp2_bm_pool *bm_pool;
5316 struct sk_buff *skb;
5317 unsigned int frag_size;
5318 dma_addr_t dma_addr;
5319 phys_addr_t phys_addr;
5321 int pool, rx_bytes, err;
5325 rx_status = mvpp2_rxdesc_status_get(port, rx_desc);
5326 rx_bytes = mvpp2_rxdesc_size_get(port, rx_desc);
5327 rx_bytes -= MVPP2_MH_SIZE;
5328 dma_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc);
5329 phys_addr = mvpp2_rxdesc_cookie_get(port, rx_desc);
5330 data = (void *)phys_to_virt(phys_addr);
5332 bm = mvpp2_bm_cookie_build(port, rx_desc);
5333 pool = mvpp2_bm_cookie_pool_get(bm);
5334 bm_pool = &port->priv->bm_pools[pool];
5336 /* In case of an error, release the requested buffer pointer
5337 * to the Buffer Manager. This request process is controlled
5338 * by the hardware, and the information about the buffer is
5339 * comprised by the RX descriptor.
5341 if (rx_status & MVPP2_RXD_ERR_SUMMARY) {
5343 dev->stats.rx_errors++;
5344 mvpp2_rx_error(port, rx_desc);
5345 /* Return the buffer to the pool */
5346 mvpp2_pool_refill(port, bm, dma_addr, phys_addr);
5350 if (bm_pool->frag_size > PAGE_SIZE)
5353 frag_size = bm_pool->frag_size;
5355 skb = build_skb(data, frag_size);
5357 netdev_warn(port->dev, "skb build failed\n");
5358 goto err_drop_frame;
5361 err = mvpp2_rx_refill(port, bm_pool, bm);
5363 netdev_err(port->dev, "failed to refill BM pools\n");
5364 goto err_drop_frame;
5367 dma_unmap_single(dev->dev.parent, dma_addr,
5368 bm_pool->buf_size, DMA_FROM_DEVICE);
5371 rcvd_bytes += rx_bytes;
5373 skb_reserve(skb, MVPP2_MH_SIZE + NET_SKB_PAD);
5374 skb_put(skb, rx_bytes);
5375 skb->protocol = eth_type_trans(skb, dev);
5376 mvpp2_rx_csum(port, rx_status, skb);
5378 napi_gro_receive(&port->napi, skb);
5382 struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats);
5384 u64_stats_update_begin(&stats->syncp);
5385 stats->rx_packets += rcvd_pkts;
5386 stats->rx_bytes += rcvd_bytes;
5387 u64_stats_update_end(&stats->syncp);
5390 /* Update Rx queue management counters */
5392 mvpp2_rxq_status_update(port, rxq->id, rx_done, rx_done);
5398 tx_desc_unmap_put(struct mvpp2_port *port, struct mvpp2_tx_queue *txq,
5399 struct mvpp2_tx_desc *desc)
5401 dma_addr_t buf_dma_addr =
5402 mvpp2_txdesc_dma_addr_get(port, desc);
5404 mvpp2_txdesc_size_get(port, desc);
5405 dma_unmap_single(port->dev->dev.parent, buf_dma_addr,
5406 buf_sz, DMA_TO_DEVICE);
5407 mvpp2_txq_desc_put(txq);
5410 /* Handle tx fragmentation processing */
5411 static int mvpp2_tx_frag_process(struct mvpp2_port *port, struct sk_buff *skb,
5412 struct mvpp2_tx_queue *aggr_txq,
5413 struct mvpp2_tx_queue *txq)
5415 struct mvpp2_txq_pcpu *txq_pcpu = this_cpu_ptr(txq->pcpu);
5416 struct mvpp2_tx_desc *tx_desc;
5418 dma_addr_t buf_dma_addr;
5420 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
5421 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5422 void *addr = page_address(frag->page.p) + frag->page_offset;
5424 tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
5425 mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
5426 mvpp2_txdesc_size_set(port, tx_desc, frag->size);
5428 buf_dma_addr = dma_map_single(port->dev->dev.parent, addr,
5431 if (dma_mapping_error(port->dev->dev.parent, buf_dma_addr)) {
5432 mvpp2_txq_desc_put(txq);
5436 mvpp2_txdesc_offset_set(port, tx_desc,
5437 buf_dma_addr & MVPP2_TX_DESC_ALIGN);
5438 mvpp2_txdesc_dma_addr_set(port, tx_desc,
5439 buf_dma_addr & ~MVPP2_TX_DESC_ALIGN);
5441 if (i == (skb_shinfo(skb)->nr_frags - 1)) {
5442 /* Last descriptor */
5443 mvpp2_txdesc_cmd_set(port, tx_desc,
5445 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc);
5447 /* Descriptor in the middle: Not First, Not Last */
5448 mvpp2_txdesc_cmd_set(port, tx_desc, 0);
5449 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc);
5456 /* Release all descriptors that were used to map fragments of
5457 * this packet, as well as the corresponding DMA mappings
5459 for (i = i - 1; i >= 0; i--) {
5460 tx_desc = txq->descs + i;
5461 tx_desc_unmap_put(port, txq, tx_desc);
5467 /* Main tx processing */
5468 static int mvpp2_tx(struct sk_buff *skb, struct net_device *dev)
5470 struct mvpp2_port *port = netdev_priv(dev);
5471 struct mvpp2_tx_queue *txq, *aggr_txq;
5472 struct mvpp2_txq_pcpu *txq_pcpu;
5473 struct mvpp2_tx_desc *tx_desc;
5474 dma_addr_t buf_dma_addr;
5479 txq_id = skb_get_queue_mapping(skb);
5480 txq = port->txqs[txq_id];
5481 txq_pcpu = this_cpu_ptr(txq->pcpu);
5482 aggr_txq = &port->priv->aggr_txqs[smp_processor_id()];
5484 frags = skb_shinfo(skb)->nr_frags + 1;
5486 /* Check number of available descriptors */
5487 if (mvpp2_aggr_desc_num_check(port->priv, aggr_txq, frags) ||
5488 mvpp2_txq_reserved_desc_num_proc(port->priv, txq,
5494 /* Get a descriptor for the first part of the packet */
5495 tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
5496 mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
5497 mvpp2_txdesc_size_set(port, tx_desc, skb_headlen(skb));
5499 buf_dma_addr = dma_map_single(dev->dev.parent, skb->data,
5500 skb_headlen(skb), DMA_TO_DEVICE);
5501 if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) {
5502 mvpp2_txq_desc_put(txq);
5507 mvpp2_txdesc_offset_set(port, tx_desc,
5508 buf_dma_addr & MVPP2_TX_DESC_ALIGN);
5509 mvpp2_txdesc_dma_addr_set(port, tx_desc,
5510 buf_dma_addr & ~MVPP2_TX_DESC_ALIGN);
5512 tx_cmd = mvpp2_skb_tx_csum(port, skb);
5515 /* First and Last descriptor */
5516 tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC;
5517 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd);
5518 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc);
5520 /* First but not Last */
5521 tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_PADDING_DISABLE;
5522 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd);
5523 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc);
5525 /* Continue with other skb fragments */
5526 if (mvpp2_tx_frag_process(port, skb, aggr_txq, txq)) {
5527 tx_desc_unmap_put(port, txq, tx_desc);
5533 txq_pcpu->reserved_num -= frags;
5534 txq_pcpu->count += frags;
5535 aggr_txq->count += frags;
5537 /* Enable transmit */
5539 mvpp2_aggr_txq_pend_desc_add(port, frags);
5541 if (txq_pcpu->size - txq_pcpu->count < MAX_SKB_FRAGS + 1) {
5542 struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id);
5544 netif_tx_stop_queue(nq);
5548 struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats);
5550 u64_stats_update_begin(&stats->syncp);
5551 stats->tx_packets++;
5552 stats->tx_bytes += skb->len;
5553 u64_stats_update_end(&stats->syncp);
5555 dev->stats.tx_dropped++;
5556 dev_kfree_skb_any(skb);
5559 /* Finalize TX processing */
5560 if (txq_pcpu->count >= txq->done_pkts_coal)
5561 mvpp2_txq_done(port, txq, txq_pcpu);
5563 /* Set the timer in case not all frags were processed */
5564 if (txq_pcpu->count <= frags && txq_pcpu->count > 0) {
5565 struct mvpp2_port_pcpu *port_pcpu = this_cpu_ptr(port->pcpu);
5567 mvpp2_timer_set(port_pcpu);
5570 return NETDEV_TX_OK;
5573 static inline void mvpp2_cause_error(struct net_device *dev, int cause)
5575 if (cause & MVPP2_CAUSE_FCS_ERR_MASK)
5576 netdev_err(dev, "FCS error\n");
5577 if (cause & MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK)
5578 netdev_err(dev, "rx fifo overrun error\n");
5579 if (cause & MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK)
5580 netdev_err(dev, "tx fifo underrun error\n");
5583 static int mvpp2_poll(struct napi_struct *napi, int budget)
5585 u32 cause_rx_tx, cause_rx, cause_misc;
5587 struct mvpp2_port *port = netdev_priv(napi->dev);
5589 /* Rx/Tx cause register
5591 * Bits 0-15: each bit indicates received packets on the Rx queue
5592 * (bit 0 is for Rx queue 0).
5594 * Bits 16-23: each bit indicates transmitted packets on the Tx queue
5595 * (bit 16 is for Tx queue 0).
5597 * Each CPU has its own Rx/Tx cause register
5599 cause_rx_tx = mvpp2_read(port->priv,
5600 MVPP2_ISR_RX_TX_CAUSE_REG(port->id));
5601 cause_rx_tx &= ~MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK;
5602 cause_misc = cause_rx_tx & MVPP2_CAUSE_MISC_SUM_MASK;
5605 mvpp2_cause_error(port->dev, cause_misc);
5607 /* Clear the cause register */
5608 mvpp2_write(port->priv, MVPP2_ISR_MISC_CAUSE_REG, 0);
5609 mvpp2_write(port->priv, MVPP2_ISR_RX_TX_CAUSE_REG(port->id),
5610 cause_rx_tx & ~MVPP2_CAUSE_MISC_SUM_MASK);
5613 cause_rx = cause_rx_tx & MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK;
5615 /* Process RX packets */
5616 cause_rx |= port->pending_cause_rx;
5617 while (cause_rx && budget > 0) {
5619 struct mvpp2_rx_queue *rxq;
5621 rxq = mvpp2_get_rx_queue(port, cause_rx);
5625 count = mvpp2_rx(port, budget, rxq);
5629 /* Clear the bit associated to this Rx queue
5630 * so that next iteration will continue from
5631 * the next Rx queue.
5633 cause_rx &= ~(1 << rxq->logic_rxq);
5639 napi_complete_done(napi, rx_done);
5641 mvpp2_interrupts_enable(port);
5643 port->pending_cause_rx = cause_rx;
5647 /* Set hw internals when starting port */
5648 static void mvpp2_start_dev(struct mvpp2_port *port)
5650 struct net_device *ndev = port->dev;
5652 mvpp2_gmac_max_rx_size_set(port);
5653 mvpp2_txp_max_tx_size_set(port);
5655 napi_enable(&port->napi);
5657 /* Enable interrupts on all CPUs */
5658 mvpp2_interrupts_enable(port);
5660 mvpp2_port_enable(port);
5661 phy_start(ndev->phydev);
5662 netif_tx_start_all_queues(port->dev);
5665 /* Set hw internals when stopping port */
5666 static void mvpp2_stop_dev(struct mvpp2_port *port)
5668 struct net_device *ndev = port->dev;
5670 /* Stop new packets from arriving to RXQs */
5671 mvpp2_ingress_disable(port);
5675 /* Disable interrupts on all CPUs */
5676 mvpp2_interrupts_disable(port);
5678 napi_disable(&port->napi);
5680 netif_carrier_off(port->dev);
5681 netif_tx_stop_all_queues(port->dev);
5683 mvpp2_egress_disable(port);
5684 mvpp2_port_disable(port);
5685 phy_stop(ndev->phydev);
5688 static int mvpp2_check_ringparam_valid(struct net_device *dev,
5689 struct ethtool_ringparam *ring)
5691 u16 new_rx_pending = ring->rx_pending;
5692 u16 new_tx_pending = ring->tx_pending;
5694 if (ring->rx_pending == 0 || ring->tx_pending == 0)
5697 if (ring->rx_pending > MVPP2_MAX_RXD)
5698 new_rx_pending = MVPP2_MAX_RXD;
5699 else if (!IS_ALIGNED(ring->rx_pending, 16))
5700 new_rx_pending = ALIGN(ring->rx_pending, 16);
5702 if (ring->tx_pending > MVPP2_MAX_TXD)
5703 new_tx_pending = MVPP2_MAX_TXD;
5704 else if (!IS_ALIGNED(ring->tx_pending, 32))
5705 new_tx_pending = ALIGN(ring->tx_pending, 32);
5707 if (ring->rx_pending != new_rx_pending) {
5708 netdev_info(dev, "illegal Rx ring size value %d, round to %d\n",
5709 ring->rx_pending, new_rx_pending);
5710 ring->rx_pending = new_rx_pending;
5713 if (ring->tx_pending != new_tx_pending) {
5714 netdev_info(dev, "illegal Tx ring size value %d, round to %d\n",
5715 ring->tx_pending, new_tx_pending);
5716 ring->tx_pending = new_tx_pending;
5722 static void mvpp2_get_mac_address(struct mvpp2_port *port, unsigned char *addr)
5724 u32 mac_addr_l, mac_addr_m, mac_addr_h;
5726 mac_addr_l = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
5727 mac_addr_m = readl(port->priv->lms_base + MVPP2_SRC_ADDR_MIDDLE);
5728 mac_addr_h = readl(port->priv->lms_base + MVPP2_SRC_ADDR_HIGH);
5729 addr[0] = (mac_addr_h >> 24) & 0xFF;
5730 addr[1] = (mac_addr_h >> 16) & 0xFF;
5731 addr[2] = (mac_addr_h >> 8) & 0xFF;
5732 addr[3] = mac_addr_h & 0xFF;
5733 addr[4] = mac_addr_m & 0xFF;
5734 addr[5] = (mac_addr_l >> MVPP2_GMAC_SA_LOW_OFFS) & 0xFF;
5737 static int mvpp2_phy_connect(struct mvpp2_port *port)
5739 struct phy_device *phy_dev;
5741 phy_dev = of_phy_connect(port->dev, port->phy_node, mvpp2_link_event, 0,
5742 port->phy_interface);
5744 netdev_err(port->dev, "cannot connect to phy\n");
5747 phy_dev->supported &= PHY_GBIT_FEATURES;
5748 phy_dev->advertising = phy_dev->supported;
5757 static void mvpp2_phy_disconnect(struct mvpp2_port *port)
5759 struct net_device *ndev = port->dev;
5761 phy_disconnect(ndev->phydev);
5764 static int mvpp2_open(struct net_device *dev)
5766 struct mvpp2_port *port = netdev_priv(dev);
5767 unsigned char mac_bcast[ETH_ALEN] = {
5768 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
5771 err = mvpp2_prs_mac_da_accept(port->priv, port->id, mac_bcast, true);
5773 netdev_err(dev, "mvpp2_prs_mac_da_accept BC failed\n");
5776 err = mvpp2_prs_mac_da_accept(port->priv, port->id,
5777 dev->dev_addr, true);
5779 netdev_err(dev, "mvpp2_prs_mac_da_accept MC failed\n");
5782 err = mvpp2_prs_tag_mode_set(port->priv, port->id, MVPP2_TAG_TYPE_MH);
5784 netdev_err(dev, "mvpp2_prs_tag_mode_set failed\n");
5787 err = mvpp2_prs_def_flow(port);
5789 netdev_err(dev, "mvpp2_prs_def_flow failed\n");
5793 /* Allocate the Rx/Tx queues */
5794 err = mvpp2_setup_rxqs(port);
5796 netdev_err(port->dev, "cannot allocate Rx queues\n");
5800 err = mvpp2_setup_txqs(port);
5802 netdev_err(port->dev, "cannot allocate Tx queues\n");
5803 goto err_cleanup_rxqs;
5806 err = request_irq(port->irq, mvpp2_isr, 0, dev->name, port);
5808 netdev_err(port->dev, "cannot request IRQ %d\n", port->irq);
5809 goto err_cleanup_txqs;
5812 /* In default link is down */
5813 netif_carrier_off(port->dev);
5815 err = mvpp2_phy_connect(port);
5819 /* Unmask interrupts on all CPUs */
5820 on_each_cpu(mvpp2_interrupts_unmask, port, 1);
5822 mvpp2_start_dev(port);
5827 free_irq(port->irq, port);
5829 mvpp2_cleanup_txqs(port);
5831 mvpp2_cleanup_rxqs(port);
5835 static int mvpp2_stop(struct net_device *dev)
5837 struct mvpp2_port *port = netdev_priv(dev);
5838 struct mvpp2_port_pcpu *port_pcpu;
5841 mvpp2_stop_dev(port);
5842 mvpp2_phy_disconnect(port);
5844 /* Mask interrupts on all CPUs */
5845 on_each_cpu(mvpp2_interrupts_mask, port, 1);
5847 free_irq(port->irq, port);
5848 for_each_present_cpu(cpu) {
5849 port_pcpu = per_cpu_ptr(port->pcpu, cpu);
5851 hrtimer_cancel(&port_pcpu->tx_done_timer);
5852 port_pcpu->timer_scheduled = false;
5853 tasklet_kill(&port_pcpu->tx_done_tasklet);
5855 mvpp2_cleanup_rxqs(port);
5856 mvpp2_cleanup_txqs(port);
5861 static void mvpp2_set_rx_mode(struct net_device *dev)
5863 struct mvpp2_port *port = netdev_priv(dev);
5864 struct mvpp2 *priv = port->priv;
5865 struct netdev_hw_addr *ha;
5867 bool allmulti = dev->flags & IFF_ALLMULTI;
5869 mvpp2_prs_mac_promisc_set(priv, id, dev->flags & IFF_PROMISC);
5870 mvpp2_prs_mac_multi_set(priv, id, MVPP2_PE_MAC_MC_ALL, allmulti);
5871 mvpp2_prs_mac_multi_set(priv, id, MVPP2_PE_MAC_MC_IP6, allmulti);
5873 /* Remove all port->id's mcast enries */
5874 mvpp2_prs_mcast_del_all(priv, id);
5876 if (allmulti && !netdev_mc_empty(dev)) {
5877 netdev_for_each_mc_addr(ha, dev)
5878 mvpp2_prs_mac_da_accept(priv, id, ha->addr, true);
5882 static int mvpp2_set_mac_address(struct net_device *dev, void *p)
5884 struct mvpp2_port *port = netdev_priv(dev);
5885 const struct sockaddr *addr = p;
5888 if (!is_valid_ether_addr(addr->sa_data)) {
5889 err = -EADDRNOTAVAIL;
5893 if (!netif_running(dev)) {
5894 err = mvpp2_prs_update_mac_da(dev, addr->sa_data);
5897 /* Reconfigure parser to accept the original MAC address */
5898 err = mvpp2_prs_update_mac_da(dev, dev->dev_addr);
5903 mvpp2_stop_dev(port);
5905 err = mvpp2_prs_update_mac_da(dev, addr->sa_data);
5909 /* Reconfigure parser accept the original MAC address */
5910 err = mvpp2_prs_update_mac_da(dev, dev->dev_addr);
5914 mvpp2_start_dev(port);
5915 mvpp2_egress_enable(port);
5916 mvpp2_ingress_enable(port);
5920 netdev_err(dev, "fail to change MAC address\n");
5924 static int mvpp2_change_mtu(struct net_device *dev, int mtu)
5926 struct mvpp2_port *port = netdev_priv(dev);
5929 if (!IS_ALIGNED(MVPP2_RX_PKT_SIZE(mtu), 8)) {
5930 netdev_info(dev, "illegal MTU value %d, round to %d\n", mtu,
5931 ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8));
5932 mtu = ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8);
5935 if (!netif_running(dev)) {
5936 err = mvpp2_bm_update_mtu(dev, mtu);
5938 port->pkt_size = MVPP2_RX_PKT_SIZE(mtu);
5942 /* Reconfigure BM to the original MTU */
5943 err = mvpp2_bm_update_mtu(dev, dev->mtu);
5948 mvpp2_stop_dev(port);
5950 err = mvpp2_bm_update_mtu(dev, mtu);
5952 port->pkt_size = MVPP2_RX_PKT_SIZE(mtu);
5956 /* Reconfigure BM to the original MTU */
5957 err = mvpp2_bm_update_mtu(dev, dev->mtu);
5962 mvpp2_start_dev(port);
5963 mvpp2_egress_enable(port);
5964 mvpp2_ingress_enable(port);
5969 netdev_err(dev, "fail to change MTU\n");
5974 mvpp2_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
5976 struct mvpp2_port *port = netdev_priv(dev);
5980 for_each_possible_cpu(cpu) {
5981 struct mvpp2_pcpu_stats *cpu_stats;
5987 cpu_stats = per_cpu_ptr(port->stats, cpu);
5989 start = u64_stats_fetch_begin_irq(&cpu_stats->syncp);
5990 rx_packets = cpu_stats->rx_packets;
5991 rx_bytes = cpu_stats->rx_bytes;
5992 tx_packets = cpu_stats->tx_packets;
5993 tx_bytes = cpu_stats->tx_bytes;
5994 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start));
5996 stats->rx_packets += rx_packets;
5997 stats->rx_bytes += rx_bytes;
5998 stats->tx_packets += tx_packets;
5999 stats->tx_bytes += tx_bytes;
6002 stats->rx_errors = dev->stats.rx_errors;
6003 stats->rx_dropped = dev->stats.rx_dropped;
6004 stats->tx_dropped = dev->stats.tx_dropped;
6007 static int mvpp2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
6014 ret = phy_mii_ioctl(dev->phydev, ifr, cmd);
6016 mvpp2_link_event(dev);
6021 /* Ethtool methods */
6023 /* Set interrupt coalescing for ethtools */
6024 static int mvpp2_ethtool_set_coalesce(struct net_device *dev,
6025 struct ethtool_coalesce *c)
6027 struct mvpp2_port *port = netdev_priv(dev);
6030 for (queue = 0; queue < rxq_number; queue++) {
6031 struct mvpp2_rx_queue *rxq = port->rxqs[queue];
6033 rxq->time_coal = c->rx_coalesce_usecs;
6034 rxq->pkts_coal = c->rx_max_coalesced_frames;
6035 mvpp2_rx_pkts_coal_set(port, rxq);
6036 mvpp2_rx_time_coal_set(port, rxq);
6039 for (queue = 0; queue < txq_number; queue++) {
6040 struct mvpp2_tx_queue *txq = port->txqs[queue];
6042 txq->done_pkts_coal = c->tx_max_coalesced_frames;
6048 /* get coalescing for ethtools */
6049 static int mvpp2_ethtool_get_coalesce(struct net_device *dev,
6050 struct ethtool_coalesce *c)
6052 struct mvpp2_port *port = netdev_priv(dev);
6054 c->rx_coalesce_usecs = port->rxqs[0]->time_coal;
6055 c->rx_max_coalesced_frames = port->rxqs[0]->pkts_coal;
6056 c->tx_max_coalesced_frames = port->txqs[0]->done_pkts_coal;
6060 static void mvpp2_ethtool_get_drvinfo(struct net_device *dev,
6061 struct ethtool_drvinfo *drvinfo)
6063 strlcpy(drvinfo->driver, MVPP2_DRIVER_NAME,
6064 sizeof(drvinfo->driver));
6065 strlcpy(drvinfo->version, MVPP2_DRIVER_VERSION,
6066 sizeof(drvinfo->version));
6067 strlcpy(drvinfo->bus_info, dev_name(&dev->dev),
6068 sizeof(drvinfo->bus_info));
6071 static void mvpp2_ethtool_get_ringparam(struct net_device *dev,
6072 struct ethtool_ringparam *ring)
6074 struct mvpp2_port *port = netdev_priv(dev);
6076 ring->rx_max_pending = MVPP2_MAX_RXD;
6077 ring->tx_max_pending = MVPP2_MAX_TXD;
6078 ring->rx_pending = port->rx_ring_size;
6079 ring->tx_pending = port->tx_ring_size;
6082 static int mvpp2_ethtool_set_ringparam(struct net_device *dev,
6083 struct ethtool_ringparam *ring)
6085 struct mvpp2_port *port = netdev_priv(dev);
6086 u16 prev_rx_ring_size = port->rx_ring_size;
6087 u16 prev_tx_ring_size = port->tx_ring_size;
6090 err = mvpp2_check_ringparam_valid(dev, ring);
6094 if (!netif_running(dev)) {
6095 port->rx_ring_size = ring->rx_pending;
6096 port->tx_ring_size = ring->tx_pending;
6100 /* The interface is running, so we have to force a
6101 * reallocation of the queues
6103 mvpp2_stop_dev(port);
6104 mvpp2_cleanup_rxqs(port);
6105 mvpp2_cleanup_txqs(port);
6107 port->rx_ring_size = ring->rx_pending;
6108 port->tx_ring_size = ring->tx_pending;
6110 err = mvpp2_setup_rxqs(port);
6112 /* Reallocate Rx queues with the original ring size */
6113 port->rx_ring_size = prev_rx_ring_size;
6114 ring->rx_pending = prev_rx_ring_size;
6115 err = mvpp2_setup_rxqs(port);
6119 err = mvpp2_setup_txqs(port);
6121 /* Reallocate Tx queues with the original ring size */
6122 port->tx_ring_size = prev_tx_ring_size;
6123 ring->tx_pending = prev_tx_ring_size;
6124 err = mvpp2_setup_txqs(port);
6126 goto err_clean_rxqs;
6129 mvpp2_start_dev(port);
6130 mvpp2_egress_enable(port);
6131 mvpp2_ingress_enable(port);
6136 mvpp2_cleanup_rxqs(port);
6138 netdev_err(dev, "fail to change ring parameters");
6144 static const struct net_device_ops mvpp2_netdev_ops = {
6145 .ndo_open = mvpp2_open,
6146 .ndo_stop = mvpp2_stop,
6147 .ndo_start_xmit = mvpp2_tx,
6148 .ndo_set_rx_mode = mvpp2_set_rx_mode,
6149 .ndo_set_mac_address = mvpp2_set_mac_address,
6150 .ndo_change_mtu = mvpp2_change_mtu,
6151 .ndo_get_stats64 = mvpp2_get_stats64,
6152 .ndo_do_ioctl = mvpp2_ioctl,
6155 static const struct ethtool_ops mvpp2_eth_tool_ops = {
6156 .nway_reset = phy_ethtool_nway_reset,
6157 .get_link = ethtool_op_get_link,
6158 .set_coalesce = mvpp2_ethtool_set_coalesce,
6159 .get_coalesce = mvpp2_ethtool_get_coalesce,
6160 .get_drvinfo = mvpp2_ethtool_get_drvinfo,
6161 .get_ringparam = mvpp2_ethtool_get_ringparam,
6162 .set_ringparam = mvpp2_ethtool_set_ringparam,
6163 .get_link_ksettings = phy_ethtool_get_link_ksettings,
6164 .set_link_ksettings = phy_ethtool_set_link_ksettings,
6167 /* Driver initialization */
6169 static void mvpp2_port_power_up(struct mvpp2_port *port)
6171 mvpp2_port_mii_set(port);
6172 mvpp2_port_periodic_xon_disable(port);
6173 mvpp2_port_fc_adv_enable(port);
6174 mvpp2_port_reset(port);
6177 /* Initialize port HW */
6178 static int mvpp2_port_init(struct mvpp2_port *port)
6180 struct device *dev = port->dev->dev.parent;
6181 struct mvpp2 *priv = port->priv;
6182 struct mvpp2_txq_pcpu *txq_pcpu;
6183 int queue, cpu, err;
6185 if (port->first_rxq + rxq_number > MVPP2_RXQ_TOTAL_NUM)
6189 mvpp2_egress_disable(port);
6190 mvpp2_port_disable(port);
6192 port->txqs = devm_kcalloc(dev, txq_number, sizeof(*port->txqs),
6197 /* Associate physical Tx queues to this port and initialize.
6198 * The mapping is predefined.
6200 for (queue = 0; queue < txq_number; queue++) {
6201 int queue_phy_id = mvpp2_txq_phys(port->id, queue);
6202 struct mvpp2_tx_queue *txq;
6204 txq = devm_kzalloc(dev, sizeof(*txq), GFP_KERNEL);
6207 goto err_free_percpu;
6210 txq->pcpu = alloc_percpu(struct mvpp2_txq_pcpu);
6213 goto err_free_percpu;
6216 txq->id = queue_phy_id;
6217 txq->log_id = queue;
6218 txq->done_pkts_coal = MVPP2_TXDONE_COAL_PKTS_THRESH;
6219 for_each_present_cpu(cpu) {
6220 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
6221 txq_pcpu->cpu = cpu;
6224 port->txqs[queue] = txq;
6227 port->rxqs = devm_kcalloc(dev, rxq_number, sizeof(*port->rxqs),
6231 goto err_free_percpu;
6234 /* Allocate and initialize Rx queue for this port */
6235 for (queue = 0; queue < rxq_number; queue++) {
6236 struct mvpp2_rx_queue *rxq;
6238 /* Map physical Rx queue to port's logical Rx queue */
6239 rxq = devm_kzalloc(dev, sizeof(*rxq), GFP_KERNEL);
6242 goto err_free_percpu;
6244 /* Map this Rx queue to a physical queue */
6245 rxq->id = port->first_rxq + queue;
6246 rxq->port = port->id;
6247 rxq->logic_rxq = queue;
6249 port->rxqs[queue] = rxq;
6252 /* Configure Rx queue group interrupt for this port */
6253 mvpp2_write(priv, MVPP2_ISR_RXQ_GROUP_REG(port->id), rxq_number);
6255 /* Create Rx descriptor rings */
6256 for (queue = 0; queue < rxq_number; queue++) {
6257 struct mvpp2_rx_queue *rxq = port->rxqs[queue];
6259 rxq->size = port->rx_ring_size;
6260 rxq->pkts_coal = MVPP2_RX_COAL_PKTS;
6261 rxq->time_coal = MVPP2_RX_COAL_USEC;
6264 mvpp2_ingress_disable(port);
6266 /* Port default configuration */
6267 mvpp2_defaults_set(port);
6269 /* Port's classifier configuration */
6270 mvpp2_cls_oversize_rxq_set(port);
6271 mvpp2_cls_port_config(port);
6273 /* Provide an initial Rx packet size */
6274 port->pkt_size = MVPP2_RX_PKT_SIZE(port->dev->mtu);
6276 /* Initialize pools for swf */
6277 err = mvpp2_swf_bm_pool_init(port);
6279 goto err_free_percpu;
6284 for (queue = 0; queue < txq_number; queue++) {
6285 if (!port->txqs[queue])
6287 free_percpu(port->txqs[queue]->pcpu);
6292 /* Ports initialization */
6293 static int mvpp2_port_probe(struct platform_device *pdev,
6294 struct device_node *port_node,
6296 int *next_first_rxq)
6298 struct device_node *phy_node;
6299 struct mvpp2_port *port;
6300 struct mvpp2_port_pcpu *port_pcpu;
6301 struct net_device *dev;
6302 struct resource *res;
6303 const char *dt_mac_addr;
6304 const char *mac_from;
6305 char hw_mac_addr[ETH_ALEN];
6309 int priv_common_regs_num = 2;
6312 dev = alloc_etherdev_mqs(sizeof(struct mvpp2_port), txq_number,
6317 phy_node = of_parse_phandle(port_node, "phy", 0);
6319 dev_err(&pdev->dev, "missing phy\n");
6321 goto err_free_netdev;
6324 phy_mode = of_get_phy_mode(port_node);
6326 dev_err(&pdev->dev, "incorrect phy mode\n");
6328 goto err_free_netdev;
6331 if (of_property_read_u32(port_node, "port-id", &id)) {
6333 dev_err(&pdev->dev, "missing port-id value\n");
6334 goto err_free_netdev;
6337 dev->tx_queue_len = MVPP2_MAX_TXD;
6338 dev->watchdog_timeo = 5 * HZ;
6339 dev->netdev_ops = &mvpp2_netdev_ops;
6340 dev->ethtool_ops = &mvpp2_eth_tool_ops;
6342 port = netdev_priv(dev);
6344 port->irq = irq_of_parse_and_map(port_node, 0);
6345 if (port->irq <= 0) {
6347 goto err_free_netdev;
6350 if (of_property_read_bool(port_node, "marvell,loopback"))
6351 port->flags |= MVPP2_F_LOOPBACK;
6355 port->first_rxq = *next_first_rxq;
6356 port->phy_node = phy_node;
6357 port->phy_interface = phy_mode;
6359 res = platform_get_resource(pdev, IORESOURCE_MEM,
6360 priv_common_regs_num + id);
6361 port->base = devm_ioremap_resource(&pdev->dev, res);
6362 if (IS_ERR(port->base)) {
6363 err = PTR_ERR(port->base);
6367 /* Alloc per-cpu stats */
6368 port->stats = netdev_alloc_pcpu_stats(struct mvpp2_pcpu_stats);
6374 dt_mac_addr = of_get_mac_address(port_node);
6375 if (dt_mac_addr && is_valid_ether_addr(dt_mac_addr)) {
6376 mac_from = "device tree";
6377 ether_addr_copy(dev->dev_addr, dt_mac_addr);
6379 mvpp2_get_mac_address(port, hw_mac_addr);
6380 if (is_valid_ether_addr(hw_mac_addr)) {
6381 mac_from = "hardware";
6382 ether_addr_copy(dev->dev_addr, hw_mac_addr);
6384 mac_from = "random";
6385 eth_hw_addr_random(dev);
6389 port->tx_ring_size = MVPP2_MAX_TXD;
6390 port->rx_ring_size = MVPP2_MAX_RXD;
6392 SET_NETDEV_DEV(dev, &pdev->dev);
6394 err = mvpp2_port_init(port);
6396 dev_err(&pdev->dev, "failed to init port %d\n", id);
6397 goto err_free_stats;
6399 mvpp2_port_power_up(port);
6401 port->pcpu = alloc_percpu(struct mvpp2_port_pcpu);
6404 goto err_free_txq_pcpu;
6407 for_each_present_cpu(cpu) {
6408 port_pcpu = per_cpu_ptr(port->pcpu, cpu);
6410 hrtimer_init(&port_pcpu->tx_done_timer, CLOCK_MONOTONIC,
6411 HRTIMER_MODE_REL_PINNED);
6412 port_pcpu->tx_done_timer.function = mvpp2_hr_timer_cb;
6413 port_pcpu->timer_scheduled = false;
6415 tasklet_init(&port_pcpu->tx_done_tasklet, mvpp2_tx_proc_cb,
6416 (unsigned long)dev);
6419 netif_napi_add(dev, &port->napi, mvpp2_poll, NAPI_POLL_WEIGHT);
6420 features = NETIF_F_SG | NETIF_F_IP_CSUM;
6421 dev->features = features | NETIF_F_RXCSUM;
6422 dev->hw_features |= features | NETIF_F_RXCSUM | NETIF_F_GRO;
6423 dev->vlan_features |= features;
6425 /* MTU range: 68 - 9676 */
6426 dev->min_mtu = ETH_MIN_MTU;
6427 /* 9676 == 9700 - 20 and rounding to 8 */
6428 dev->max_mtu = 9676;
6430 err = register_netdev(dev);
6432 dev_err(&pdev->dev, "failed to register netdev\n");
6433 goto err_free_port_pcpu;
6435 netdev_info(dev, "Using %s mac address %pM\n", mac_from, dev->dev_addr);
6437 /* Increment the first Rx queue number to be used by the next port */
6438 *next_first_rxq += rxq_number;
6439 priv->port_list[id] = port;
6443 free_percpu(port->pcpu);
6445 for (i = 0; i < txq_number; i++)
6446 free_percpu(port->txqs[i]->pcpu);
6448 free_percpu(port->stats);
6450 irq_dispose_mapping(port->irq);
6452 of_node_put(phy_node);
6457 /* Ports removal routine */
6458 static void mvpp2_port_remove(struct mvpp2_port *port)
6462 unregister_netdev(port->dev);
6463 of_node_put(port->phy_node);
6464 free_percpu(port->pcpu);
6465 free_percpu(port->stats);
6466 for (i = 0; i < txq_number; i++)
6467 free_percpu(port->txqs[i]->pcpu);
6468 irq_dispose_mapping(port->irq);
6469 free_netdev(port->dev);
6472 /* Initialize decoding windows */
6473 static void mvpp2_conf_mbus_windows(const struct mbus_dram_target_info *dram,
6479 for (i = 0; i < 6; i++) {
6480 mvpp2_write(priv, MVPP2_WIN_BASE(i), 0);
6481 mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0);
6484 mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0);
6489 for (i = 0; i < dram->num_cs; i++) {
6490 const struct mbus_dram_window *cs = dram->cs + i;
6492 mvpp2_write(priv, MVPP2_WIN_BASE(i),
6493 (cs->base & 0xffff0000) | (cs->mbus_attr << 8) |
6494 dram->mbus_dram_target_id);
6496 mvpp2_write(priv, MVPP2_WIN_SIZE(i),
6497 (cs->size - 1) & 0xffff0000);
6499 win_enable |= (1 << i);
6502 mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable);
6505 /* Initialize Rx FIFO's */
6506 static void mvpp2_rx_fifo_init(struct mvpp2 *priv)
6510 for (port = 0; port < MVPP2_MAX_PORTS; port++) {
6511 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
6512 MVPP2_RX_FIFO_PORT_DATA_SIZE);
6513 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
6514 MVPP2_RX_FIFO_PORT_ATTR_SIZE);
6517 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
6518 MVPP2_RX_FIFO_PORT_MIN_PKT);
6519 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
6522 /* Initialize network controller common part HW */
6523 static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv)
6525 const struct mbus_dram_target_info *dram_target_info;
6529 /* Checks for hardware constraints */
6530 if (rxq_number % 4 || (rxq_number > MVPP2_MAX_RXQ) ||
6531 (txq_number > MVPP2_MAX_TXQ)) {
6532 dev_err(&pdev->dev, "invalid queue size parameter\n");
6536 /* MBUS windows configuration */
6537 dram_target_info = mv_mbus_dram_info();
6538 if (dram_target_info)
6539 mvpp2_conf_mbus_windows(dram_target_info, priv);
6541 /* Disable HW PHY polling */
6542 val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
6543 val |= MVPP2_PHY_AN_STOP_SMI0_MASK;
6544 writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
6546 /* Allocate and initialize aggregated TXQs */
6547 priv->aggr_txqs = devm_kcalloc(&pdev->dev, num_present_cpus(),
6548 sizeof(struct mvpp2_tx_queue),
6550 if (!priv->aggr_txqs)
6553 for_each_present_cpu(i) {
6554 priv->aggr_txqs[i].id = i;
6555 priv->aggr_txqs[i].size = MVPP2_AGGR_TXQ_SIZE;
6556 err = mvpp2_aggr_txq_init(pdev, &priv->aggr_txqs[i],
6557 MVPP2_AGGR_TXQ_SIZE, i, priv);
6563 mvpp2_rx_fifo_init(priv);
6565 /* Reset Rx queue group interrupt configuration */
6566 for (i = 0; i < MVPP2_MAX_PORTS; i++)
6567 mvpp2_write(priv, MVPP2_ISR_RXQ_GROUP_REG(i), rxq_number);
6569 writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT,
6570 priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG);
6572 /* Allow cache snoop when transmiting packets */
6573 mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1);
6575 /* Buffer Manager initialization */
6576 err = mvpp2_bm_init(pdev, priv);
6580 /* Parser default initialization */
6581 err = mvpp2_prs_default_init(pdev, priv);
6585 /* Classifier default initialization */
6586 mvpp2_cls_init(priv);
6591 static int mvpp2_probe(struct platform_device *pdev)
6593 struct device_node *dn = pdev->dev.of_node;
6594 struct device_node *port_node;
6596 struct resource *res;
6597 int port_count, first_rxq;
6600 priv = devm_kzalloc(&pdev->dev, sizeof(struct mvpp2), GFP_KERNEL);
6605 (unsigned long)of_device_get_match_data(&pdev->dev);
6607 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
6608 priv->base = devm_ioremap_resource(&pdev->dev, res);
6609 if (IS_ERR(priv->base))
6610 return PTR_ERR(priv->base);
6612 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
6613 priv->lms_base = devm_ioremap_resource(&pdev->dev, res);
6614 if (IS_ERR(priv->lms_base))
6615 return PTR_ERR(priv->lms_base);
6617 priv->pp_clk = devm_clk_get(&pdev->dev, "pp_clk");
6618 if (IS_ERR(priv->pp_clk))
6619 return PTR_ERR(priv->pp_clk);
6620 err = clk_prepare_enable(priv->pp_clk);
6624 priv->gop_clk = devm_clk_get(&pdev->dev, "gop_clk");
6625 if (IS_ERR(priv->gop_clk)) {
6626 err = PTR_ERR(priv->gop_clk);
6629 err = clk_prepare_enable(priv->gop_clk);
6633 /* Get system's tclk rate */
6634 priv->tclk = clk_get_rate(priv->pp_clk);
6636 /* Initialize network controller */
6637 err = mvpp2_init(pdev, priv);
6639 dev_err(&pdev->dev, "failed to initialize controller\n");
6643 port_count = of_get_available_child_count(dn);
6644 if (port_count == 0) {
6645 dev_err(&pdev->dev, "no ports enabled\n");
6650 priv->port_list = devm_kcalloc(&pdev->dev, port_count,
6651 sizeof(struct mvpp2_port *),
6653 if (!priv->port_list) {
6658 /* Initialize ports */
6660 for_each_available_child_of_node(dn, port_node) {
6661 err = mvpp2_port_probe(pdev, port_node, priv, &first_rxq);
6666 platform_set_drvdata(pdev, priv);
6670 clk_disable_unprepare(priv->gop_clk);
6672 clk_disable_unprepare(priv->pp_clk);
6676 static int mvpp2_remove(struct platform_device *pdev)
6678 struct mvpp2 *priv = platform_get_drvdata(pdev);
6679 struct device_node *dn = pdev->dev.of_node;
6680 struct device_node *port_node;
6683 for_each_available_child_of_node(dn, port_node) {
6684 if (priv->port_list[i])
6685 mvpp2_port_remove(priv->port_list[i]);
6689 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
6690 struct mvpp2_bm_pool *bm_pool = &priv->bm_pools[i];
6692 mvpp2_bm_pool_destroy(pdev, priv, bm_pool);
6695 for_each_present_cpu(i) {
6696 struct mvpp2_tx_queue *aggr_txq = &priv->aggr_txqs[i];
6698 dma_free_coherent(&pdev->dev,
6699 MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE,
6701 aggr_txq->descs_dma);
6704 clk_disable_unprepare(priv->pp_clk);
6705 clk_disable_unprepare(priv->gop_clk);
6710 static const struct of_device_id mvpp2_match[] = {
6712 .compatible = "marvell,armada-375-pp2",
6713 .data = (void *)MVPP21,
6717 MODULE_DEVICE_TABLE(of, mvpp2_match);
6719 static struct platform_driver mvpp2_driver = {
6720 .probe = mvpp2_probe,
6721 .remove = mvpp2_remove,
6723 .name = MVPP2_DRIVER_NAME,
6724 .of_match_table = mvpp2_match,
6728 module_platform_driver(mvpp2_driver);
6730 MODULE_DESCRIPTION("Marvell PPv2 Ethernet Driver - www.marvell.com");
6731 MODULE_AUTHOR("Marcin Wojtas <mw@semihalf.com>");
6732 MODULE_LICENSE("GPL v2");