drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Driver for Marvell PPv2 network controller for Armada 375 SoC.
   4  *
   5  * Copyright (C) 2014 Marvell
   6  *
   7  * Marcin Wojtas <mw@semihalf.com>
   8  */
   9
  10 #include <linux/acpi.h>
  11 #include <linux/kernel.h>
  12 #include <linux/netdevice.h>
  13 #include <linux/etherdevice.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/skbuff.h>
  16 #include <linux/inetdevice.h>
  17 #include <linux/mbus.h>
  18 #include <linux/module.h>
  19 #include <linux/mfd/syscon.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/cpumask.h>
  22 #include <linux/of.h>
  23 #include <linux/of_irq.h>
  24 #include <linux/of_mdio.h>
  25 #include <linux/of_net.h>
  26 #include <linux/of_address.h>
  27 #include <linux/of_device.h>
  28 #include <linux/phy.h>
  29 #include <linux/phylink.h>
  30 #include <linux/phy/phy.h>
  31 #include <linux/ptp_classify.h>
  32 #include <linux/clk.h>
  33 #include <linux/hrtimer.h>
  34 #include <linux/ktime.h>
  35 #include <linux/regmap.h>
  36 #include <uapi/linux/ppp_defs.h>
  37 #include <net/ip.h>
  38 #include <net/ipv6.h>
  39 #include <net/tso.h>
  40 #include <linux/bpf_trace.h>
  41
  42 #include "mvpp2.h"
  43 #include "mvpp2_prs.h"
  44 #include "mvpp2_cls.h"
  45
  46 enum mvpp2_bm_pool_log_num {
  47         MVPP2_BM_SHORT,
  48         MVPP2_BM_LONG,
  49         MVPP2_BM_JUMBO,
  50         MVPP2_BM_POOLS_NUM
  51 };
  52
  53 static struct {
  54         int pkt_size;
  55         int buf_num;
  56 } mvpp2_pools[MVPP2_BM_POOLS_NUM];
  57
  58 /* The prototype is added here to be used in start_dev when using ACPI. This
  59  * will be removed once phylink is used for all modes (dt+ACPI).
  60  */
  61 static void mvpp2_acpi_start(struct mvpp2_port *port);
  62
  63 /* Queue modes */
  64 #define MVPP2_QDIST_SINGLE_MODE 0
  65 #define MVPP2_QDIST_MULTI_MODE  1
  66
  67 static int queue_mode = MVPP2_QDIST_MULTI_MODE;
  68
  69 module_param(queue_mode, int, 0444);
  70 MODULE_PARM_DESC(queue_mode, "Set queue_mode (single=0, multi=1)");
  71
  72 /* Utility/helper methods */
  73
  74 void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data)
  75 {
  76         writel(data, priv->swth_base[0] + offset);
  77 }
  78
  79 u32 mvpp2_read(struct mvpp2 *priv, u32 offset)
  80 {
  81         return readl(priv->swth_base[0] + offset);
  82 }
  83
  84 static u32 mvpp2_read_relaxed(struct mvpp2 *priv, u32 offset)
  85 {
  86         return readl_relaxed(priv->swth_base[0] + offset);
  87 }
  88
  89 static inline u32 mvpp2_cpu_to_thread(struct mvpp2 *priv, int cpu)
  90 {
  91         return cpu % priv->nthreads;
  92 }
  93
  94 static void mvpp2_cm3_write(struct mvpp2 *priv, u32 offset, u32 data)
  95 {
  96         writel(data, priv->cm3_base + offset);
  97 }
  98
  99 static u32 mvpp2_cm3_read(struct mvpp2 *priv, u32 offset)
 100 {
 101         return readl(priv->cm3_base + offset);
 102 }
 103
 104 static struct page_pool *
 105 mvpp2_create_page_pool(struct device *dev, int num, int len,
 106                        enum dma_data_direction dma_dir)
 107 {
 108         struct page_pool_params pp_params = {
 109                 /* internal DMA mapping in page_pool */
 110                 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV,
 111                 .pool_size = num,
 112                 .nid = NUMA_NO_NODE,
 113                 .dev = dev,
 114                 .dma_dir = dma_dir,
 115                 .offset = MVPP2_SKB_HEADROOM,
 116                 .max_len = len,
 117         };
 118
 119         return page_pool_create(&pp_params);
 120 }
 121
 122 /* These accessors should be used to access:
 123  *
 124  * - per-thread registers, where each thread has its own copy of the
 125  *   register.
 126  *
 127  *   MVPP2_BM_VIRT_ALLOC_REG
 128  *   MVPP2_BM_ADDR_HIGH_ALLOC
 129  *   MVPP22_BM_ADDR_HIGH_RLS_REG
 130  *   MVPP2_BM_VIRT_RLS_REG
 131  *   MVPP2_ISR_RX_TX_CAUSE_REG
 132  *   MVPP2_ISR_RX_TX_MASK_REG
 133  *   MVPP2_TXQ_NUM_REG
 134  *   MVPP2_AGGR_TXQ_UPDATE_REG
 135  *   MVPP2_TXQ_RSVD_REQ_REG
 136  *   MVPP2_TXQ_RSVD_RSLT_REG
 137  *   MVPP2_TXQ_SENT_REG
 138  *   MVPP2_RXQ_NUM_REG
 139  *
 140  * - global registers that must be accessed through a specific thread
 141  *   window, because they are related to an access to a per-thread
 142  *   register
 143  *
 144  *   MVPP2_BM_PHY_ALLOC_REG    (related to MVPP2_BM_VIRT_ALLOC_REG)
 145  *   MVPP2_BM_PHY_RLS_REG      (related to MVPP2_BM_VIRT_RLS_REG)
 146  *   MVPP2_RXQ_THRESH_REG      (related to MVPP2_RXQ_NUM_REG)
 147  *   MVPP2_RXQ_DESC_ADDR_REG   (related to MVPP2_RXQ_NUM_REG)
 148  *   MVPP2_RXQ_DESC_SIZE_REG   (related to MVPP2_RXQ_NUM_REG)
 149  *   MVPP2_RXQ_INDEX_REG       (related to MVPP2_RXQ_NUM_REG)
 150  *   MVPP2_TXQ_PENDING_REG     (related to MVPP2_TXQ_NUM_REG)
 151  *   MVPP2_TXQ_DESC_ADDR_REG   (related to MVPP2_TXQ_NUM_REG)
 152  *   MVPP2_TXQ_DESC_SIZE_REG   (related to MVPP2_TXQ_NUM_REG)
 153  *   MVPP2_TXQ_INDEX_REG       (related to MVPP2_TXQ_NUM_REG)
 154  *   MVPP2_TXQ_PENDING_REG     (related to MVPP2_TXQ_NUM_REG)
 155  *   MVPP2_TXQ_PREF_BUF_REG    (related to MVPP2_TXQ_NUM_REG)
 156  *   MVPP2_TXQ_PREF_BUF_REG    (related to MVPP2_TXQ_NUM_REG)
 157  */
 158 static void mvpp2_thread_write(struct mvpp2 *priv, unsigned int thread,
 159                                u32 offset, u32 data)
 160 {
 161         writel(data, priv->swth_base[thread] + offset);
 162 }
 163
 164 static u32 mvpp2_thread_read(struct mvpp2 *priv, unsigned int thread,
 165                              u32 offset)
 166 {
 167         return readl(priv->swth_base[thread] + offset);
 168 }
 169
 170 static void mvpp2_thread_write_relaxed(struct mvpp2 *priv, unsigned int thread,
 171                                        u32 offset, u32 data)
 172 {
 173         writel_relaxed(data, priv->swth_base[thread] + offset);
 174 }
 175
 176 static u32 mvpp2_thread_read_relaxed(struct mvpp2 *priv, unsigned int thread,
 177                                      u32 offset)
 178 {
 179         return readl_relaxed(priv->swth_base[thread] + offset);
 180 }
 181
 182 static dma_addr_t mvpp2_txdesc_dma_addr_get(struct mvpp2_port *port,
 183                                             struct mvpp2_tx_desc *tx_desc)
 184 {
 185         if (port->priv->hw_version == MVPP21)
 186                 return le32_to_cpu(tx_desc->pp21.buf_dma_addr);
 187         else
 188                 return le64_to_cpu(tx_desc->pp22.buf_dma_addr_ptp) &
 189                        MVPP2_DESC_DMA_MASK;
 190 }
 191
 192 static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port,
 193                                       struct mvpp2_tx_desc *tx_desc,
 194                                       dma_addr_t dma_addr)
 195 {
 196         dma_addr_t addr, offset;
 197
 198         addr = dma_addr & ~MVPP2_TX_DESC_ALIGN;
 199         offset = dma_addr & MVPP2_TX_DESC_ALIGN;
 200
 201         if (port->priv->hw_version == MVPP21) {
 202                 tx_desc->pp21.buf_dma_addr = cpu_to_le32(addr);
 203                 tx_desc->pp21.packet_offset = offset;
 204         } else {
 205                 __le64 val = cpu_to_le64(addr);
 206
 207                 tx_desc->pp22.buf_dma_addr_ptp &= ~cpu_to_le64(MVPP2_DESC_DMA_MASK);
 208                 tx_desc->pp22.buf_dma_addr_ptp |= val;
 209                 tx_desc->pp22.packet_offset = offset;
 210         }
 211 }
 212
 213 static size_t mvpp2_txdesc_size_get(struct mvpp2_port *port,
 214                                     struct mvpp2_tx_desc *tx_desc)
 215 {
 216         if (port->priv->hw_version == MVPP21)
 217                 return le16_to_cpu(tx_desc->pp21.data_size);
 218         else
 219                 return le16_to_cpu(tx_desc->pp22.data_size);
 220 }
 221
 222 static void mvpp2_txdesc_size_set(struct mvpp2_port *port,
 223                                   struct mvpp2_tx_desc *tx_desc,
 224                                   size_t size)
 225 {
 226         if (port->priv->hw_version == MVPP21)
 227                 tx_desc->pp21.data_size = cpu_to_le16(size);
 228         else
 229                 tx_desc->pp22.data_size = cpu_to_le16(size);
 230 }
 231
 232 static void mvpp2_txdesc_txq_set(struct mvpp2_port *port,
 233                                  struct mvpp2_tx_desc *tx_desc,
 234                                  unsigned int txq)
 235 {
 236         if (port->priv->hw_version == MVPP21)
 237                 tx_desc->pp21.phys_txq = txq;
 238         else
 239                 tx_desc->pp22.phys_txq = txq;
 240 }
 241
 242 static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port,
 243                                  struct mvpp2_tx_desc *tx_desc,
 244                                  unsigned int command)
 245 {
 246         if (port->priv->hw_version == MVPP21)
 247                 tx_desc->pp21.command = cpu_to_le32(command);
 248         else
 249                 tx_desc->pp22.command = cpu_to_le32(command);
 250 }
 251
 252 static unsigned int mvpp2_txdesc_offset_get(struct mvpp2_port *port,
 253                                             struct mvpp2_tx_desc *tx_desc)
 254 {
 255         if (port->priv->hw_version == MVPP21)
 256                 return tx_desc->pp21.packet_offset;
 257         else
 258                 return tx_desc->pp22.packet_offset;
 259 }
 260
 261 static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port,
 262                                             struct mvpp2_rx_desc *rx_desc)
 263 {
 264         if (port->priv->hw_version == MVPP21)
 265                 return le32_to_cpu(rx_desc->pp21.buf_dma_addr);
 266         else
 267                 return le64_to_cpu(rx_desc->pp22.buf_dma_addr_key_hash) &
 268                        MVPP2_DESC_DMA_MASK;
 269 }
 270
 271 static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port,
 272                                              struct mvpp2_rx_desc *rx_desc)
 273 {
 274         if (port->priv->hw_version == MVPP21)
 275                 return le32_to_cpu(rx_desc->pp21.buf_cookie);
 276         else
 277                 return le64_to_cpu(rx_desc->pp22.buf_cookie_misc) &
 278                        MVPP2_DESC_DMA_MASK;
 279 }
 280
 281 static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port,
 282                                     struct mvpp2_rx_desc *rx_desc)
 283 {
 284         if (port->priv->hw_version == MVPP21)
 285                 return le16_to_cpu(rx_desc->pp21.data_size);
 286         else
 287                 return le16_to_cpu(rx_desc->pp22.data_size);
 288 }
 289
 290 static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port,
 291                                    struct mvpp2_rx_desc *rx_desc)
 292 {
 293         if (port->priv->hw_version == MVPP21)
 294                 return le32_to_cpu(rx_desc->pp21.status);
 295         else
 296                 return le32_to_cpu(rx_desc->pp22.status);
 297 }
 298
 299 static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu)
 300 {
 301         txq_pcpu->txq_get_index++;
 302         if (txq_pcpu->txq_get_index == txq_pcpu->size)
 303                 txq_pcpu->txq_get_index = 0;
 304 }
 305
 306 static void mvpp2_txq_inc_put(struct mvpp2_port *port,
 307                               struct mvpp2_txq_pcpu *txq_pcpu,
 308                               void *data,
 309                               struct mvpp2_tx_desc *tx_desc,
 310                               enum mvpp2_tx_buf_type buf_type)
 311 {
 312         struct mvpp2_txq_pcpu_buf *tx_buf =
 313                 txq_pcpu->buffs + txq_pcpu->txq_put_index;
 314         tx_buf->type = buf_type;
 315         if (buf_type == MVPP2_TYPE_SKB)
 316                 tx_buf->skb = data;
 317         else
 318                 tx_buf->xdpf = data;
 319         tx_buf->size = mvpp2_txdesc_size_get(port, tx_desc);
 320         tx_buf->dma = mvpp2_txdesc_dma_addr_get(port, tx_desc) +
 321                 mvpp2_txdesc_offset_get(port, tx_desc);
 322         txq_pcpu->txq_put_index++;
 323         if (txq_pcpu->txq_put_index == txq_pcpu->size)
 324                 txq_pcpu->txq_put_index = 0;
 325 }
 326
 327 /* Get number of maximum RXQ */
 328 static int mvpp2_get_nrxqs(struct mvpp2 *priv)
 329 {
 330         unsigned int nrxqs;
 331
 332         if (priv->hw_version >= MVPP22 && queue_mode == MVPP2_QDIST_SINGLE_MODE)
 333                 return 1;
 334
 335         /* According to the PPv2.2 datasheet and our experiments on
 336          * PPv2.1, RX queues have an allocation granularity of 4 (when
 337          * more than a single one on PPv2.2).
 338          * Round up to nearest multiple of 4.
 339          */
 340         nrxqs = (num_possible_cpus() + 3) & ~0x3;
 341         if (nrxqs > MVPP2_PORT_MAX_RXQ)
 342                 nrxqs = MVPP2_PORT_MAX_RXQ;
 343
 344         return nrxqs;
 345 }
 346
 347 /* Get number of physical egress port */
 348 static inline int mvpp2_egress_port(struct mvpp2_port *port)
 349 {
 350         return MVPP2_MAX_TCONT + port->id;
 351 }
 352
 353 /* Get number of physical TXQ */
 354 static inline int mvpp2_txq_phys(int port, int txq)
 355 {
 356         return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq;
 357 }
 358
 359 /* Returns a struct page if page_pool is set, otherwise a buffer */
 360 static void *mvpp2_frag_alloc(const struct mvpp2_bm_pool *pool,
 361                               struct page_pool *page_pool)
 362 {
 363         if (page_pool)
 364                 return page_pool_dev_alloc_pages(page_pool);
 365
 366         if (likely(pool->frag_size <= PAGE_SIZE))
 367                 return netdev_alloc_frag(pool->frag_size);
 368
 369         return kmalloc(pool->frag_size, GFP_ATOMIC);
 370 }
 371
 372 static void mvpp2_frag_free(const struct mvpp2_bm_pool *pool,
 373                             struct page_pool *page_pool, void *data)
 374 {
 375         if (page_pool)
 376                 page_pool_put_full_page(page_pool, virt_to_head_page(data), false);
 377         else if (likely(pool->frag_size <= PAGE_SIZE))
 378                 skb_free_frag(data);
 379         else
 380                 kfree(data);
 381 }
 382
 383 /* Buffer Manager configuration routines */
 384
 385 /* Create pool */
 386 static int mvpp2_bm_pool_create(struct device *dev, struct mvpp2 *priv,
 387                                 struct mvpp2_bm_pool *bm_pool, int size)
 388 {
 389         u32 val;
 390
 391         /* Number of buffer pointers must be a multiple of 16, as per
 392          * hardware constraints
 393          */
 394         if (!IS_ALIGNED(size, 16))
 395                 return -EINVAL;
 396
 397         /* PPv2.1 needs 8 bytes per buffer pointer, PPv2.2 and PPv2.3 needs 16
 398          * bytes per buffer pointer
 399          */
 400         if (priv->hw_version == MVPP21)
 401                 bm_pool->size_bytes = 2 * sizeof(u32) * size;
 402         else
 403                 bm_pool->size_bytes = 2 * sizeof(u64) * size;
 404
 405         bm_pool->virt_addr = dma_alloc_coherent(dev, bm_pool->size_bytes,
 406                                                 &bm_pool->dma_addr,
 407                                                 GFP_KERNEL);
 408         if (!bm_pool->virt_addr)
 409                 return -ENOMEM;
 410
 411         if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr,
 412                         MVPP2_BM_POOL_PTR_ALIGN)) {
 413                 dma_free_coherent(dev, bm_pool->size_bytes,
 414                                   bm_pool->virt_addr, bm_pool->dma_addr);
 415                 dev_err(dev, "BM pool %d is not %d bytes aligned\n",
 416                         bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN);
 417                 return -ENOMEM;
 418         }
 419
 420         mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id),
 421                     lower_32_bits(bm_pool->dma_addr));
 422         mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size);
 423
 424         val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
 425         val |= MVPP2_BM_START_MASK;
 426
 427         val &= ~MVPP2_BM_LOW_THRESH_MASK;
 428         val &= ~MVPP2_BM_HIGH_THRESH_MASK;
 429
 430         /* Set 8 Pools BPPI threshold for MVPP23 */
 431         if (priv->hw_version == MVPP23) {
 432                 val |= MVPP2_BM_LOW_THRESH_VALUE(MVPP23_BM_BPPI_LOW_THRESH);
 433                 val |= MVPP2_BM_HIGH_THRESH_VALUE(MVPP23_BM_BPPI_HIGH_THRESH);
 434         } else {
 435                 val |= MVPP2_BM_LOW_THRESH_VALUE(MVPP2_BM_BPPI_LOW_THRESH);
 436                 val |= MVPP2_BM_HIGH_THRESH_VALUE(MVPP2_BM_BPPI_HIGH_THRESH);
 437         }
 438
 439         mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
 440
 441         bm_pool->size = size;
 442         bm_pool->pkt_size = 0;
 443         bm_pool->buf_num = 0;
 444
 445         return 0;
 446 }
 447
 448 /* Set pool buffer size */
 449 static void mvpp2_bm_pool_bufsize_set(struct mvpp2 *priv,
 450                                       struct mvpp2_bm_pool *bm_pool,
 451                                       int buf_size)
 452 {
 453         u32 val;
 454
 455         bm_pool->buf_size = buf_size;
 456
 457         val = ALIGN(buf_size, 1 << MVPP2_POOL_BUF_SIZE_OFFSET);
 458         mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val);
 459 }
 460
 461 static void mvpp2_bm_bufs_get_addrs(struct device *dev, struct mvpp2 *priv,
 462                                     struct mvpp2_bm_pool *bm_pool,
 463                                     dma_addr_t *dma_addr,
 464                                     phys_addr_t *phys_addr)
 465 {
 466         unsigned int thread = mvpp2_cpu_to_thread(priv, get_cpu());
 467
 468         *dma_addr = mvpp2_thread_read(priv, thread,
 469                                       MVPP2_BM_PHY_ALLOC_REG(bm_pool->id));
 470         *phys_addr = mvpp2_thread_read(priv, thread, MVPP2_BM_VIRT_ALLOC_REG);
 471
 472         if (priv->hw_version >= MVPP22) {
 473                 u32 val;
 474                 u32 dma_addr_highbits, phys_addr_highbits;
 475
 476                 val = mvpp2_thread_read(priv, thread, MVPP22_BM_ADDR_HIGH_ALLOC);
 477                 dma_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_PHYS_MASK);
 478                 phys_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_VIRT_MASK) >>
 479                         MVPP22_BM_ADDR_HIGH_VIRT_SHIFT;
 480
 481                 if (sizeof(dma_addr_t) == 8)
 482                         *dma_addr |= (u64)dma_addr_highbits << 32;
 483
 484                 if (sizeof(phys_addr_t) == 8)
 485                         *phys_addr |= (u64)phys_addr_highbits << 32;
 486         }
 487
 488         put_cpu();
 489 }
 490
 491 /* Free all buffers from the pool */
 492 static void mvpp2_bm_bufs_free(struct device *dev, struct mvpp2 *priv,
 493                                struct mvpp2_bm_pool *bm_pool, int buf_num)
 494 {
 495         struct page_pool *pp = NULL;
 496         int i;
 497
 498         if (buf_num > bm_pool->buf_num) {
 499                 WARN(1, "Pool does not have so many bufs pool(%d) bufs(%d)\n",
 500                      bm_pool->id, buf_num);
 501                 buf_num = bm_pool->buf_num;
 502         }
 503
 504         if (priv->percpu_pools)
 505                 pp = priv->page_pool[bm_pool->id];
 506
 507         for (i = 0; i < buf_num; i++) {
 508                 dma_addr_t buf_dma_addr;
 509                 phys_addr_t buf_phys_addr;
 510                 void *data;
 511
 512                 mvpp2_bm_bufs_get_addrs(dev, priv, bm_pool,
 513                                         &buf_dma_addr, &buf_phys_addr);
 514
 515                 if (!pp)
 516                         dma_unmap_single(dev, buf_dma_addr,
 517                                          bm_pool->buf_size, DMA_FROM_DEVICE);
 518
 519                 data = (void *)phys_to_virt(buf_phys_addr);
 520                 if (!data)
 521                         break;
 522
 523                 mvpp2_frag_free(bm_pool, pp, data);
 524         }
 525
 526         /* Update BM driver with number of buffers removed from pool */
 527         bm_pool->buf_num -= i;
 528 }
 529
 530 /* Check number of buffers in BM pool */
 531 static int mvpp2_check_hw_buf_num(struct mvpp2 *priv, struct mvpp2_bm_pool *bm_pool)
 532 {
 533         int buf_num = 0;
 534
 535         buf_num += mvpp2_read(priv, MVPP2_BM_POOL_PTRS_NUM_REG(bm_pool->id)) &
 536                                     MVPP22_BM_POOL_PTRS_NUM_MASK;
 537         buf_num += mvpp2_read(priv, MVPP2_BM_BPPI_PTRS_NUM_REG(bm_pool->id)) &
 538                                     MVPP2_BM_BPPI_PTR_NUM_MASK;
 539
 540         /* HW has one buffer ready which is not reflected in the counters */
 541         if (buf_num)
 542                 buf_num += 1;
 543
 544         return buf_num;
 545 }
 546
 547 /* Cleanup pool */
 548 static int mvpp2_bm_pool_destroy(struct device *dev, struct mvpp2 *priv,
 549                                  struct mvpp2_bm_pool *bm_pool)
 550 {
 551         int buf_num;
 552         u32 val;
 553
 554         buf_num = mvpp2_check_hw_buf_num(priv, bm_pool);
 555         mvpp2_bm_bufs_free(dev, priv, bm_pool, buf_num);
 556
 557         /* Check buffer counters after free */
 558         buf_num = mvpp2_check_hw_buf_num(priv, bm_pool);
 559         if (buf_num) {
 560                 WARN(1, "cannot free all buffers in pool %d, buf_num left %d\n",
 561                      bm_pool->id, bm_pool->buf_num);
 562                 return 0;
 563         }
 564
 565         val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
 566         val |= MVPP2_BM_STOP_MASK;
 567         mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
 568
 569         if (priv->percpu_pools) {
 570                 page_pool_destroy(priv->page_pool[bm_pool->id]);
 571                 priv->page_pool[bm_pool->id] = NULL;
 572         }
 573
 574         dma_free_coherent(dev, bm_pool->size_bytes,
 575                           bm_pool->virt_addr,
 576                           bm_pool->dma_addr);
 577         return 0;
 578 }
 579
 580 static int mvpp2_bm_pools_init(struct device *dev, struct mvpp2 *priv)
 581 {
 582         int i, err, size, poolnum = MVPP2_BM_POOLS_NUM;
 583         struct mvpp2_bm_pool *bm_pool;
 584
 585         if (priv->percpu_pools)
 586                 poolnum = mvpp2_get_nrxqs(priv) * 2;
 587
 588         /* Create all pools with maximum size */
 589         size = MVPP2_BM_POOL_SIZE_MAX;
 590         for (i = 0; i < poolnum; i++) {
 591                 bm_pool = &priv->bm_pools[i];
 592                 bm_pool->id = i;
 593                 err = mvpp2_bm_pool_create(dev, priv, bm_pool, size);
 594                 if (err)
 595                         goto err_unroll_pools;
 596                 mvpp2_bm_pool_bufsize_set(priv, bm_pool, 0);
 597         }
 598         return 0;
 599
 600 err_unroll_pools:
 601         dev_err(dev, "failed to create BM pool %d, size %d\n", i, size);
 602         for (i = i - 1; i >= 0; i--)
 603                 mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]);
 604         return err;
 605 }
 606
 607 /* Routine enable PPv23 8 pool mode */
 608 static void mvpp23_bm_set_8pool_mode(struct mvpp2 *priv)
 609 {
 610         int val;
 611
 612         val = mvpp2_read(priv, MVPP22_BM_POOL_BASE_ADDR_HIGH_REG);
 613         val |= MVPP23_BM_8POOL_MODE;
 614         mvpp2_write(priv, MVPP22_BM_POOL_BASE_ADDR_HIGH_REG, val);
 615 }
 616
 617 static int mvpp2_bm_init(struct device *dev, struct mvpp2 *priv)
 618 {
 619         enum dma_data_direction dma_dir = DMA_FROM_DEVICE;
 620         int i, err, poolnum = MVPP2_BM_POOLS_NUM;
 621         struct mvpp2_port *port;
 622
 623         if (priv->percpu_pools) {
 624                 for (i = 0; i < priv->port_count; i++) {
 625                         port = priv->port_list[i];
 626                         if (port->xdp_prog) {
 627                                 dma_dir = DMA_BIDIRECTIONAL;
 628                                 break;
 629                         }
 630                 }
 631
 632                 poolnum = mvpp2_get_nrxqs(priv) * 2;
 633                 for (i = 0; i < poolnum; i++) {
 634                         /* the pool in use */
 635                         int pn = i / (poolnum / 2);
 636
 637                         priv->page_pool[i] =
 638                                 mvpp2_create_page_pool(dev,
 639                                                        mvpp2_pools[pn].buf_num,
 640                                                        mvpp2_pools[pn].pkt_size,
 641                                                        dma_dir);
 642                         if (IS_ERR(priv->page_pool[i])) {
 643                                 int j;
 644
 645                                 for (j = 0; j < i; j++) {
 646                                         page_pool_destroy(priv->page_pool[j]);
 647                                         priv->page_pool[j] = NULL;
 648                                 }
 649                                 return PTR_ERR(priv->page_pool[i]);
 650                         }
 651                 }
 652         }
 653
 654         dev_info(dev, "using %d %s buffers\n", poolnum,
 655                  priv->percpu_pools ? "per-cpu" : "shared");
 656
 657         for (i = 0; i < poolnum; i++) {
 658                 /* Mask BM all interrupts */
 659                 mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0);
 660                 /* Clear BM cause register */
 661                 mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0);
 662         }
 663
 664         /* Allocate and initialize BM pools */
 665         priv->bm_pools = devm_kcalloc(dev, poolnum,
 666                                       sizeof(*priv->bm_pools), GFP_KERNEL);
 667         if (!priv->bm_pools)
 668                 return -ENOMEM;
 669
 670         if (priv->hw_version == MVPP23)
 671                 mvpp23_bm_set_8pool_mode(priv);
 672
 673         err = mvpp2_bm_pools_init(dev, priv);
 674         if (err < 0)
 675                 return err;
 676         return 0;
 677 }
 678
 679 static void mvpp2_setup_bm_pool(void)
 680 {
 681         /* Short pool */
 682         mvpp2_pools[MVPP2_BM_SHORT].buf_num  = MVPP2_BM_SHORT_BUF_NUM;
 683         mvpp2_pools[MVPP2_BM_SHORT].pkt_size = MVPP2_BM_SHORT_PKT_SIZE;
 684
 685         /* Long pool */
 686         mvpp2_pools[MVPP2_BM_LONG].buf_num  = MVPP2_BM_LONG_BUF_NUM;
 687         mvpp2_pools[MVPP2_BM_LONG].pkt_size = MVPP2_BM_LONG_PKT_SIZE;
 688
 689         /* Jumbo pool */
 690         mvpp2_pools[MVPP2_BM_JUMBO].buf_num  = MVPP2_BM_JUMBO_BUF_NUM;
 691         mvpp2_pools[MVPP2_BM_JUMBO].pkt_size = MVPP2_BM_JUMBO_PKT_SIZE;
 692 }
 693
 694 /* Attach long pool to rxq */
 695 static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port,
 696                                     int lrxq, int long_pool)
 697 {
 698         u32 val, mask;
 699         int prxq;
 700
 701         /* Get queue physical ID */
 702         prxq = port->rxqs[lrxq]->id;
 703
 704         if (port->priv->hw_version == MVPP21)
 705                 mask = MVPP21_RXQ_POOL_LONG_MASK;
 706         else
 707                 mask = MVPP22_RXQ_POOL_LONG_MASK;
 708
 709         val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
 710         val &= ~mask;
 711         val |= (long_pool << MVPP2_RXQ_POOL_LONG_OFFS) & mask;
 712         mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
 713 }
 714
 715 /* Attach short pool to rxq */
 716 static void mvpp2_rxq_short_pool_set(struct mvpp2_port *port,
 717                                      int lrxq, int short_pool)
 718 {
 719         u32 val, mask;
 720         int prxq;
 721
 722         /* Get queue physical ID */
 723         prxq = port->rxqs[lrxq]->id;
 724
 725         if (port->priv->hw_version == MVPP21)
 726                 mask = MVPP21_RXQ_POOL_SHORT_MASK;
 727         else
 728                 mask = MVPP22_RXQ_POOL_SHORT_MASK;
 729
 730         val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
 731         val &= ~mask;
 732         val |= (short_pool << MVPP2_RXQ_POOL_SHORT_OFFS) & mask;
 733         mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
 734 }
 735
 736 static void *mvpp2_buf_alloc(struct mvpp2_port *port,
 737                              struct mvpp2_bm_pool *bm_pool,
 738                              struct page_pool *page_pool,
 739                              dma_addr_t *buf_dma_addr,
 740                              phys_addr_t *buf_phys_addr,
 741                              gfp_t gfp_mask)
 742 {
 743         dma_addr_t dma_addr;
 744         struct page *page;
 745         void *data;
 746
 747         data = mvpp2_frag_alloc(bm_pool, page_pool);
 748         if (!data)
 749                 return NULL;
 750
 751         if (page_pool) {
 752                 page = (struct page *)data;
 753                 dma_addr = page_pool_get_dma_addr(page);
 754                 data = page_to_virt(page);
 755         } else {
 756                 dma_addr = dma_map_single(port->dev->dev.parent, data,
 757                                           MVPP2_RX_BUF_SIZE(bm_pool->pkt_size),
 758                                           DMA_FROM_DEVICE);
 759                 if (unlikely(dma_mapping_error(port->dev->dev.parent, dma_addr))) {
 760                         mvpp2_frag_free(bm_pool, NULL, data);
 761                         return NULL;
 762                 }
 763         }
 764         *buf_dma_addr = dma_addr;
 765         *buf_phys_addr = virt_to_phys(data);
 766
 767         return data;
 768 }
 769
 770 /* Routine enable flow control for RXQs condition */
 771 static void mvpp2_rxq_enable_fc(struct mvpp2_port *port)
 772 {
 773         int val, cm3_state, host_id, q;
 774         int fq = port->first_rxq;
 775         unsigned long flags;
 776
 777         spin_lock_irqsave(&port->priv->mss_spinlock, flags);
 778
 779         /* Remove Flow control enable bit to prevent race between FW and Kernel
 780          * If Flow control was enabled, it would be re-enabled.
 781          */
 782         val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG);
 783         cm3_state = (val & FLOW_CONTROL_ENABLE_BIT);
 784         val &= ~FLOW_CONTROL_ENABLE_BIT;
 785         mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val);
 786
 787         /* Set same Flow control for all RXQs */
 788         for (q = 0; q < port->nrxqs; q++) {
 789                 /* Set stop and start Flow control RXQ thresholds */
 790                 val = MSS_THRESHOLD_START;
 791                 val |= (MSS_THRESHOLD_STOP << MSS_RXQ_TRESH_STOP_OFFS);
 792                 mvpp2_cm3_write(port->priv, MSS_RXQ_TRESH_REG(q, fq), val);
 793
 794                 val = mvpp2_cm3_read(port->priv, MSS_RXQ_ASS_REG(q, fq));
 795                 /* Set RXQ port ID */
 796                 val &= ~(MSS_RXQ_ASS_PORTID_MASK << MSS_RXQ_ASS_Q_BASE(q, fq));
 797                 val |= (port->id << MSS_RXQ_ASS_Q_BASE(q, fq));
 798                 val &= ~(MSS_RXQ_ASS_HOSTID_MASK << (MSS_RXQ_ASS_Q_BASE(q, fq)
 799                         + MSS_RXQ_ASS_HOSTID_OFFS));
 800
 801                 /* Calculate RXQ host ID:
 802                  * In Single queue mode: Host ID equal to Host ID used for
 803                  *                       shared RX interrupt
 804                  * In Multi queue mode: Host ID equal to number of
 805                  *                      RXQ ID / number of CoS queues
 806                  * In Single resource mode: Host ID always equal to 0
 807                  */
 808                 if (queue_mode == MVPP2_QDIST_SINGLE_MODE)
 809                         host_id = port->nqvecs;
 810                 else if (queue_mode == MVPP2_QDIST_MULTI_MODE)
 811                         host_id = q;
 812                 else
 813                         host_id = 0;
 814
 815                 /* Set RXQ host ID */
 816                 val |= (host_id << (MSS_RXQ_ASS_Q_BASE(q, fq)
 817                         + MSS_RXQ_ASS_HOSTID_OFFS));
 818
 819                 mvpp2_cm3_write(port->priv, MSS_RXQ_ASS_REG(q, fq), val);
 820         }
 821
 822         /* Notify Firmware that Flow control config space ready for update */
 823         val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG);
 824         val |= FLOW_CONTROL_UPDATE_COMMAND_BIT;
 825         val |= cm3_state;
 826         mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val);
 827
 828         spin_unlock_irqrestore(&port->priv->mss_spinlock, flags);
 829 }
 830
 831 /* Routine disable flow control for RXQs condition */
 832 static void mvpp2_rxq_disable_fc(struct mvpp2_port *port)
 833 {
 834         int val, cm3_state, q;
 835         unsigned long flags;
 836         int fq = port->first_rxq;
 837
 838         spin_lock_irqsave(&port->priv->mss_spinlock, flags);
 839
 840         /* Remove Flow control enable bit to prevent race between FW and Kernel
 841          * If Flow control was enabled, it would be re-enabled.
 842          */
 843         val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG);
 844         cm3_state = (val & FLOW_CONTROL_ENABLE_BIT);
 845         val &= ~FLOW_CONTROL_ENABLE_BIT;
 846         mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val);
 847
 848         /* Disable Flow control for all RXQs */
 849         for (q = 0; q < port->nrxqs; q++) {
 850                 /* Set threshold 0 to disable Flow control */
 851                 val = 0;
 852                 val |= (0 << MSS_RXQ_TRESH_STOP_OFFS);
 853                 mvpp2_cm3_write(port->priv, MSS_RXQ_TRESH_REG(q, fq), val);
 854
 855                 val = mvpp2_cm3_read(port->priv, MSS_RXQ_ASS_REG(q, fq));
 856
 857                 val &= ~(MSS_RXQ_ASS_PORTID_MASK << MSS_RXQ_ASS_Q_BASE(q, fq));
 858
 859                 val &= ~(MSS_RXQ_ASS_HOSTID_MASK << (MSS_RXQ_ASS_Q_BASE(q, fq)
 860                         + MSS_RXQ_ASS_HOSTID_OFFS));
 861
 862                 mvpp2_cm3_write(port->priv, MSS_RXQ_ASS_REG(q, fq), val);
 863         }
 864
 865         /* Notify Firmware that Flow control config space ready for update */
 866         val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG);
 867         val |= FLOW_CONTROL_UPDATE_COMMAND_BIT;
 868         val |= cm3_state;
 869         mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val);
 870
 871         spin_unlock_irqrestore(&port->priv->mss_spinlock, flags);
 872 }
 873
 874 /* Routine disable/enable flow control for BM pool condition */
 875 static void mvpp2_bm_pool_update_fc(struct mvpp2_port *port,
 876                                     struct mvpp2_bm_pool *pool,
 877                                     bool en)
 878 {
 879         int val, cm3_state;
 880         unsigned long flags;
 881
 882         spin_lock_irqsave(&port->priv->mss_spinlock, flags);
 883
 884         /* Remove Flow control enable bit to prevent race between FW and Kernel
 885          * If Flow control were enabled, it would be re-enabled.
 886          */
 887         val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG);
 888         cm3_state = (val & FLOW_CONTROL_ENABLE_BIT);
 889         val &= ~FLOW_CONTROL_ENABLE_BIT;
 890         mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val);
 891
 892         /* Check if BM pool should be enabled/disable */
 893         if (en) {
 894                 /* Set BM pool start and stop thresholds per port */
 895                 val = mvpp2_cm3_read(port->priv, MSS_BUF_POOL_REG(pool->id));
 896                 val |= MSS_BUF_POOL_PORT_OFFS(port->id);
 897                 val &= ~MSS_BUF_POOL_START_MASK;
 898                 val |= (MSS_THRESHOLD_START << MSS_BUF_POOL_START_OFFS);
 899                 val &= ~MSS_BUF_POOL_STOP_MASK;
 900                 val |= MSS_THRESHOLD_STOP;
 901                 mvpp2_cm3_write(port->priv, MSS_BUF_POOL_REG(pool->id), val);
 902         } else {
 903                 /* Remove BM pool from the port */
 904                 val = mvpp2_cm3_read(port->priv, MSS_BUF_POOL_REG(pool->id));
 905                 val &= ~MSS_BUF_POOL_PORT_OFFS(port->id);
 906
 907                 /* Zero BM pool start and stop thresholds to disable pool
 908                  * flow control if pool empty (not used by any port)
 909                  */
 910                 if (!pool->buf_num) {
 911                         val &= ~MSS_BUF_POOL_START_MASK;
 912                         val &= ~MSS_BUF_POOL_STOP_MASK;
 913                 }
 914
 915                 mvpp2_cm3_write(port->priv, MSS_BUF_POOL_REG(pool->id), val);
 916         }
 917
 918         /* Notify Firmware that Flow control config space ready for update */
 919         val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG);
 920         val |= FLOW_CONTROL_UPDATE_COMMAND_BIT;
 921         val |= cm3_state;
 922         mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val);
 923
 924         spin_unlock_irqrestore(&port->priv->mss_spinlock, flags);
 925 }
 926
 927 /* disable/enable flow control for BM pool on all ports */
 928 static void mvpp2_bm_pool_update_priv_fc(struct mvpp2 *priv, bool en)
 929 {
 930         struct mvpp2_port *port;
 931         int i;
 932
 933         for (i = 0; i < priv->port_count; i++) {
 934                 port = priv->port_list[i];
 935                 if (port->priv->percpu_pools) {
 936                         for (i = 0; i < port->nrxqs; i++)
 937                                 mvpp2_bm_pool_update_fc(port, &port->priv->bm_pools[i],
 938                                                         port->tx_fc & en);
 939                 } else {
 940                         mvpp2_bm_pool_update_fc(port, port->pool_long, port->tx_fc & en);
 941                         mvpp2_bm_pool_update_fc(port, port->pool_short, port->tx_fc & en);
 942                 }
 943         }
 944 }
 945
 946 static int mvpp2_enable_global_fc(struct mvpp2 *priv)
 947 {
 948         int val, timeout = 0;
 949
 950         /* Enable global flow control. In this stage global
 951          * flow control enabled, but still disabled per port.
 952          */
 953         val = mvpp2_cm3_read(priv, MSS_FC_COM_REG);
 954         val |= FLOW_CONTROL_ENABLE_BIT;
 955         mvpp2_cm3_write(priv, MSS_FC_COM_REG, val);
 956
 957         /* Check if Firmware running and disable FC if not*/
 958         val |= FLOW_CONTROL_UPDATE_COMMAND_BIT;
 959         mvpp2_cm3_write(priv, MSS_FC_COM_REG, val);
 960
 961         while (timeout < MSS_FC_MAX_TIMEOUT) {
 962                 val = mvpp2_cm3_read(priv, MSS_FC_COM_REG);
 963
 964                 if (!(val & FLOW_CONTROL_UPDATE_COMMAND_BIT))
 965                         return 0;
 966                 usleep_range(10, 20);
 967                 timeout++;
 968         }
 969
 970         priv->global_tx_fc = false;
 971         return -EOPNOTSUPP;
 972 }
 973
 974 /* Release buffer to BM */
 975 static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
 976                                      dma_addr_t buf_dma_addr,
 977                                      phys_addr_t buf_phys_addr)
 978 {
 979         unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
 980         unsigned long flags = 0;
 981
 982         if (test_bit(thread, &port->priv->lock_map))
 983                 spin_lock_irqsave(&port->bm_lock[thread], flags);
 984
 985         if (port->priv->hw_version >= MVPP22) {
 986                 u32 val = 0;
 987
 988                 if (sizeof(dma_addr_t) == 8)
 989                         val |= upper_32_bits(buf_dma_addr) &
 990                                 MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK;
 991
 992                 if (sizeof(phys_addr_t) == 8)
 993                         val |= (upper_32_bits(buf_phys_addr)
 994                                 << MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT) &
 995                                 MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK;
 996
 997                 mvpp2_thread_write_relaxed(port->priv, thread,
 998                                            MVPP22_BM_ADDR_HIGH_RLS_REG, val);
 999         }
1000
1001         /* MVPP2_BM_VIRT_RLS_REG is not interpreted by HW, and simply
1002          * returned in the "cookie" field of the RX
1003          * descriptor. Instead of storing the virtual address, we
1004          * store the physical address
1005          */
1006         mvpp2_thread_write_relaxed(port->priv, thread,
1007                                    MVPP2_BM_VIRT_RLS_REG, buf_phys_addr);
1008         mvpp2_thread_write_relaxed(port->priv, thread,
1009                                    MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr);
1010
1011         if (test_bit(thread, &port->priv->lock_map))
1012                 spin_unlock_irqrestore(&port->bm_lock[thread], flags);
1013
1014         put_cpu();
1015 }
1016
1017 /* Allocate buffers for the pool */
1018 static int mvpp2_bm_bufs_add(struct mvpp2_port *port,
1019                              struct mvpp2_bm_pool *bm_pool, int buf_num)
1020 {
1021         int i, buf_size, total_size;
1022         dma_addr_t dma_addr;
1023         phys_addr_t phys_addr;
1024         struct page_pool *pp = NULL;
1025         void *buf;
1026
1027         if (port->priv->percpu_pools &&
1028             bm_pool->pkt_size > MVPP2_BM_LONG_PKT_SIZE) {
1029                 netdev_err(port->dev,
1030                            "attempted to use jumbo frames with per-cpu pools");
1031                 return 0;
1032         }
1033
1034         buf_size = MVPP2_RX_BUF_SIZE(bm_pool->pkt_size);
1035         total_size = MVPP2_RX_TOTAL_SIZE(buf_size);
1036
1037         if (buf_num < 0 ||
1038             (buf_num + bm_pool->buf_num > bm_pool->size)) {
1039                 netdev_err(port->dev,
1040                            "cannot allocate %d buffers for pool %d\n",
1041                            buf_num, bm_pool->id);
1042                 return 0;
1043         }
1044
1045         if (port->priv->percpu_pools)
1046                 pp = port->priv->page_pool[bm_pool->id];
1047         for (i = 0; i < buf_num; i++) {
1048                 buf = mvpp2_buf_alloc(port, bm_pool, pp, &dma_addr,
1049                                       &phys_addr, GFP_KERNEL);
1050                 if (!buf)
1051                         break;
1052
1053                 mvpp2_bm_pool_put(port, bm_pool->id, dma_addr,
1054                                   phys_addr);
1055         }
1056
1057         /* Update BM driver with number of buffers added to pool */
1058         bm_pool->buf_num += i;
1059
1060         netdev_dbg(port->dev,
1061                    "pool %d: pkt_size=%4d, buf_size=%4d, total_size=%4d\n",
1062                    bm_pool->id, bm_pool->pkt_size, buf_size, total_size);
1063
1064         netdev_dbg(port->dev,
1065                    "pool %d: %d of %d buffers added\n",
1066                    bm_pool->id, i, buf_num);
1067         return i;
1068 }
1069
1070 /* Notify the driver that BM pool is being used as specific type and return the
1071  * pool pointer on success
1072  */
1073 static struct mvpp2_bm_pool *
1074 mvpp2_bm_pool_use(struct mvpp2_port *port, unsigned pool, int pkt_size)
1075 {
1076         struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool];
1077         int num;
1078
1079         if ((port->priv->percpu_pools && pool > mvpp2_get_nrxqs(port->priv) * 2) ||
1080             (!port->priv->percpu_pools && pool >= MVPP2_BM_POOLS_NUM)) {
1081                 netdev_err(port->dev, "Invalid pool %d\n", pool);
1082                 return NULL;
1083         }
1084
1085         /* Allocate buffers in case BM pool is used as long pool, but packet
1086          * size doesn't match MTU or BM pool hasn't being used yet
1087          */
1088         if (new_pool->pkt_size == 0) {
1089                 int pkts_num;
1090
1091                 /* Set default buffer number or free all the buffers in case
1092                  * the pool is not empty
1093                  */
1094                 pkts_num = new_pool->buf_num;
1095                 if (pkts_num == 0) {
1096                         if (port->priv->percpu_pools) {
1097                                 if (pool < port->nrxqs)
1098                                         pkts_num = mvpp2_pools[MVPP2_BM_SHORT].buf_num;
1099                                 else
1100                                         pkts_num = mvpp2_pools[MVPP2_BM_LONG].buf_num;
1101                         } else {
1102                                 pkts_num = mvpp2_pools[pool].buf_num;
1103                         }
1104                 } else {
1105                         mvpp2_bm_bufs_free(port->dev->dev.parent,
1106                                            port->priv, new_pool, pkts_num);
1107                 }
1108
1109                 new_pool->pkt_size = pkt_size;
1110                 new_pool->frag_size =
1111                         SKB_DATA_ALIGN(MVPP2_RX_BUF_SIZE(pkt_size)) +
1112                         MVPP2_SKB_SHINFO_SIZE;
1113
1114                 /* Allocate buffers for this pool */
1115                 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num);
1116                 if (num != pkts_num) {
1117                         WARN(1, "pool %d: %d of %d allocated\n",
1118                              new_pool->id, num, pkts_num);
1119                         return NULL;
1120                 }
1121         }
1122
1123         mvpp2_bm_pool_bufsize_set(port->priv, new_pool,
1124                                   MVPP2_RX_BUF_SIZE(new_pool->pkt_size));
1125
1126         return new_pool;
1127 }
1128
1129 static struct mvpp2_bm_pool *
1130 mvpp2_bm_pool_use_percpu(struct mvpp2_port *port, int type,
1131                          unsigned int pool, int pkt_size)
1132 {
1133         struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool];
1134         int num;
1135
1136         if (pool > port->nrxqs * 2) {
1137                 netdev_err(port->dev, "Invalid pool %d\n", pool);
1138                 return NULL;
1139         }
1140
1141         /* Allocate buffers in case BM pool is used as long pool, but packet
1142          * size doesn't match MTU or BM pool hasn't being used yet
1143          */
1144         if (new_pool->pkt_size == 0) {
1145                 int pkts_num;
1146
1147                 /* Set default buffer number or free all the buffers in case
1148                  * the pool is not empty
1149                  */
1150                 pkts_num = new_pool->buf_num;
1151                 if (pkts_num == 0)
1152                         pkts_num = mvpp2_pools[type].buf_num;
1153                 else
1154                         mvpp2_bm_bufs_free(port->dev->dev.parent,
1155                                            port->priv, new_pool, pkts_num);
1156
1157                 new_pool->pkt_size = pkt_size;
1158                 new_pool->frag_size =
1159                         SKB_DATA_ALIGN(MVPP2_RX_BUF_SIZE(pkt_size)) +
1160                         MVPP2_SKB_SHINFO_SIZE;
1161
1162                 /* Allocate buffers for this pool */
1163                 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num);
1164                 if (num != pkts_num) {
1165                         WARN(1, "pool %d: %d of %d allocated\n",
1166                              new_pool->id, num, pkts_num);
1167                         return NULL;
1168                 }
1169         }
1170
1171         mvpp2_bm_pool_bufsize_set(port->priv, new_pool,
1172                                   MVPP2_RX_BUF_SIZE(new_pool->pkt_size));
1173
1174         return new_pool;
1175 }
1176
1177 /* Initialize pools for swf, shared buffers variant */
1178 static int mvpp2_swf_bm_pool_init_shared(struct mvpp2_port *port)
1179 {
1180         enum mvpp2_bm_pool_log_num long_log_pool, short_log_pool;
1181         int rxq;
1182
1183         /* If port pkt_size is higher than 1518B:
1184          * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool
1185          * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool
1186          */
1187         if (port->pkt_size > MVPP2_BM_LONG_PKT_SIZE) {
1188                 long_log_pool = MVPP2_BM_JUMBO;
1189                 short_log_pool = MVPP2_BM_LONG;
1190         } else {
1191                 long_log_pool = MVPP2_BM_LONG;
1192                 short_log_pool = MVPP2_BM_SHORT;
1193         }
1194
1195         if (!port->pool_long) {
1196                 port->pool_long =
1197                         mvpp2_bm_pool_use(port, long_log_pool,
1198                                           mvpp2_pools[long_log_pool].pkt_size);
1199                 if (!port->pool_long)
1200                         return -ENOMEM;
1201
1202                 port->pool_long->port_map |= BIT(port->id);
1203
1204                 for (rxq = 0; rxq < port->nrxqs; rxq++)
1205                         mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id);
1206         }
1207
1208         if (!port->pool_short) {
1209                 port->pool_short =
1210                         mvpp2_bm_pool_use(port, short_log_pool,
1211                                           mvpp2_pools[short_log_pool].pkt_size);
1212                 if (!port->pool_short)
1213                         return -ENOMEM;
1214
1215                 port->pool_short->port_map |= BIT(port->id);
1216
1217                 for (rxq = 0; rxq < port->nrxqs; rxq++)
1218                         mvpp2_rxq_short_pool_set(port, rxq,
1219                                                  port->pool_short->id);
1220         }
1221
1222         return 0;
1223 }
1224
1225 /* Initialize pools for swf, percpu buffers variant */
1226 static int mvpp2_swf_bm_pool_init_percpu(struct mvpp2_port *port)
1227 {
1228         struct mvpp2_bm_pool *bm_pool;
1229         int i;
1230
1231         for (i = 0; i < port->nrxqs; i++) {
1232                 bm_pool = mvpp2_bm_pool_use_percpu(port, MVPP2_BM_SHORT, i,
1233                                                    mvpp2_pools[MVPP2_BM_SHORT].pkt_size);
1234                 if (!bm_pool)
1235                         return -ENOMEM;
1236
1237                 bm_pool->port_map |= BIT(port->id);
1238                 mvpp2_rxq_short_pool_set(port, i, bm_pool->id);
1239         }
1240
1241         for (i = 0; i < port->nrxqs; i++) {
1242                 bm_pool = mvpp2_bm_pool_use_percpu(port, MVPP2_BM_LONG, i + port->nrxqs,
1243                                                    mvpp2_pools[MVPP2_BM_LONG].pkt_size);
1244                 if (!bm_pool)
1245                         return -ENOMEM;
1246
1247                 bm_pool->port_map |= BIT(port->id);
1248                 mvpp2_rxq_long_pool_set(port, i, bm_pool->id);
1249         }
1250
1251         port->pool_long = NULL;
1252         port->pool_short = NULL;
1253
1254         return 0;
1255 }
1256
1257 static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port)
1258 {
1259         if (port->priv->percpu_pools)
1260                 return mvpp2_swf_bm_pool_init_percpu(port);
1261         else
1262                 return mvpp2_swf_bm_pool_init_shared(port);
1263 }
1264
1265 static void mvpp2_set_hw_csum(struct mvpp2_port *port,
1266                               enum mvpp2_bm_pool_log_num new_long_pool)
1267 {
1268         const netdev_features_t csums = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1269
1270         /* Update L4 checksum when jumbo enable/disable on port.
1271          * Only port 0 supports hardware checksum offload due to
1272          * the Tx FIFO size limitation.
1273          * Also, don't set NETIF_F_HW_CSUM because L3_offset in TX descriptor
1274          * has 7 bits, so the maximum L3 offset is 128.
1275          */
1276         if (new_long_pool == MVPP2_BM_JUMBO && port->id != 0) {
1277                 port->dev->features &= ~csums;
1278                 port->dev->hw_features &= ~csums;
1279         } else {
1280                 port->dev->features |= csums;
1281                 port->dev->hw_features |= csums;
1282         }
1283 }
1284
1285 static int mvpp2_bm_update_mtu(struct net_device *dev, int mtu)
1286 {
1287         struct mvpp2_port *port = netdev_priv(dev);
1288         enum mvpp2_bm_pool_log_num new_long_pool;
1289         int pkt_size = MVPP2_RX_PKT_SIZE(mtu);
1290
1291         if (port->priv->percpu_pools)
1292                 goto out_set;
1293
1294         /* If port MTU is higher than 1518B:
1295          * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool
1296          * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool
1297          */
1298         if (pkt_size > MVPP2_BM_LONG_PKT_SIZE)
1299                 new_long_pool = MVPP2_BM_JUMBO;
1300         else
1301                 new_long_pool = MVPP2_BM_LONG;
1302
1303         if (new_long_pool != port->pool_long->id) {
1304                 if (port->tx_fc) {
1305                         if (pkt_size > MVPP2_BM_LONG_PKT_SIZE)
1306                                 mvpp2_bm_pool_update_fc(port,
1307                                                         port->pool_short,
1308                                                         false);
1309                         else
1310                                 mvpp2_bm_pool_update_fc(port, port->pool_long,
1311                                                         false);
1312                 }
1313
1314                 /* Remove port from old short & long pool */
1315                 port->pool_long = mvpp2_bm_pool_use(port, port->pool_long->id,
1316                                                     port->pool_long->pkt_size);
1317                 port->pool_long->port_map &= ~BIT(port->id);
1318                 port->pool_long = NULL;
1319
1320                 port->pool_short = mvpp2_bm_pool_use(port, port->pool_short->id,
1321                                                      port->pool_short->pkt_size);
1322                 port->pool_short->port_map &= ~BIT(port->id);
1323                 port->pool_short = NULL;
1324
1325                 port->pkt_size =  pkt_size;
1326
1327                 /* Add port to new short & long pool */
1328                 mvpp2_swf_bm_pool_init(port);
1329
1330                 mvpp2_set_hw_csum(port, new_long_pool);
1331
1332                 if (port->tx_fc) {
1333                         if (pkt_size > MVPP2_BM_LONG_PKT_SIZE)
1334                                 mvpp2_bm_pool_update_fc(port, port->pool_long,
1335                                                         true);
1336                         else
1337                                 mvpp2_bm_pool_update_fc(port, port->pool_short,
1338                                                         true);
1339                 }
1340
1341                 /* Update L4 checksum when jumbo enable/disable on port */
1342                 if (new_long_pool == MVPP2_BM_JUMBO && port->id != 0) {
1343                         dev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
1344                         dev->hw_features &= ~(NETIF_F_IP_CSUM |
1345                                               NETIF_F_IPV6_CSUM);
1346                 } else {
1347                         dev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1348                         dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1349                 }
1350         }
1351
1352 out_set:
1353         dev->mtu = mtu;
1354         dev->wanted_features = dev->features;
1355
1356         netdev_update_features(dev);
1357         return 0;
1358 }
1359
1360 static inline void mvpp2_interrupts_enable(struct mvpp2_port *port)
1361 {
1362         int i, sw_thread_mask = 0;
1363
1364         for (i = 0; i < port->nqvecs; i++)
1365                 sw_thread_mask |= port->qvecs[i].sw_thread_mask;
1366
1367         mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
1368                     MVPP2_ISR_ENABLE_INTERRUPT(sw_thread_mask));
1369 }
1370
1371 static inline void mvpp2_interrupts_disable(struct mvpp2_port *port)
1372 {
1373         int i, sw_thread_mask = 0;
1374
1375         for (i = 0; i < port->nqvecs; i++)
1376                 sw_thread_mask |= port->qvecs[i].sw_thread_mask;
1377
1378         mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
1379                     MVPP2_ISR_DISABLE_INTERRUPT(sw_thread_mask));
1380 }
1381
1382 static inline void mvpp2_qvec_interrupt_enable(struct mvpp2_queue_vector *qvec)
1383 {
1384         struct mvpp2_port *port = qvec->port;
1385
1386         mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
1387                     MVPP2_ISR_ENABLE_INTERRUPT(qvec->sw_thread_mask));
1388 }
1389
1390 static inline void mvpp2_qvec_interrupt_disable(struct mvpp2_queue_vector *qvec)
1391 {
1392         struct mvpp2_port *port = qvec->port;
1393
1394         mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
1395                     MVPP2_ISR_DISABLE_INTERRUPT(qvec->sw_thread_mask));
1396 }
1397
1398 /* Mask the current thread's Rx/Tx interrupts
1399  * Called by on_each_cpu(), guaranteed to run with migration disabled,
1400  * using smp_processor_id() is OK.
1401  */
1402 static void mvpp2_interrupts_mask(void *arg)
1403 {
1404         struct mvpp2_port *port = arg;
1405         int cpu = smp_processor_id();
1406         u32 thread;
1407
1408         /* If the thread isn't used, don't do anything */
1409         if (cpu > port->priv->nthreads)
1410                 return;
1411
1412         thread = mvpp2_cpu_to_thread(port->priv, cpu);
1413
1414         mvpp2_thread_write(port->priv, thread,
1415                            MVPP2_ISR_RX_TX_MASK_REG(port->id), 0);
1416         mvpp2_thread_write(port->priv, thread,
1417                            MVPP2_ISR_RX_ERR_CAUSE_REG(port->id), 0);
1418 }
1419
1420 /* Unmask the current thread's Rx/Tx interrupts.
1421  * Called by on_each_cpu(), guaranteed to run with migration disabled,
1422  * using smp_processor_id() is OK.
1423  */
1424 static void mvpp2_interrupts_unmask(void *arg)
1425 {
1426         struct mvpp2_port *port = arg;
1427         int cpu = smp_processor_id();
1428         u32 val, thread;
1429
1430         /* If the thread isn't used, don't do anything */
1431         if (cpu >= port->priv->nthreads)
1432                 return;
1433
1434         thread = mvpp2_cpu_to_thread(port->priv, cpu);
1435
1436         val = MVPP2_CAUSE_MISC_SUM_MASK |
1437                 MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version);
1438         if (port->has_tx_irqs)
1439                 val |= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK;
1440
1441         mvpp2_thread_write(port->priv, thread,
1442                            MVPP2_ISR_RX_TX_MASK_REG(port->id), val);
1443         mvpp2_thread_write(port->priv, thread,
1444                            MVPP2_ISR_RX_ERR_CAUSE_REG(port->id),
1445                            MVPP2_ISR_RX_ERR_CAUSE_NONOCC_MASK);
1446 }
1447
1448 static void
1449 mvpp2_shared_interrupt_mask_unmask(struct mvpp2_port *port, bool mask)
1450 {
1451         u32 val;
1452         int i;
1453
1454         if (port->priv->hw_version == MVPP21)
1455                 return;
1456
1457         if (mask)
1458                 val = 0;
1459         else
1460                 val = MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(MVPP22);
1461
1462         for (i = 0; i < port->nqvecs; i++) {
1463                 struct mvpp2_queue_vector *v = port->qvecs + i;
1464
1465                 if (v->type != MVPP2_QUEUE_VECTOR_SHARED)
1466                         continue;
1467
1468                 mvpp2_thread_write(port->priv, v->sw_thread_id,
1469                                    MVPP2_ISR_RX_TX_MASK_REG(port->id), val);
1470                 mvpp2_thread_write(port->priv, v->sw_thread_id,
1471                                    MVPP2_ISR_RX_ERR_CAUSE_REG(port->id),
1472                                    MVPP2_ISR_RX_ERR_CAUSE_NONOCC_MASK);
1473         }
1474 }
1475
1476 /* Only GOP port 0 has an XLG MAC */
1477 static bool mvpp2_port_supports_xlg(struct mvpp2_port *port)
1478 {
1479         return port->gop_id == 0;
1480 }
1481
1482 static bool mvpp2_port_supports_rgmii(struct mvpp2_port *port)
1483 {
1484         return !(port->priv->hw_version >= MVPP22 && port->gop_id == 0);
1485 }
1486
1487 /* Port configuration routines */
1488 static bool mvpp2_is_xlg(phy_interface_t interface)
1489 {
1490         return interface == PHY_INTERFACE_MODE_10GBASER ||
1491                interface == PHY_INTERFACE_MODE_XAUI;
1492 }
1493
1494 static void mvpp2_modify(void __iomem *ptr, u32 mask, u32 set)
1495 {
1496         u32 old, val;
1497
1498         old = val = readl(ptr);
1499         val &= ~mask;
1500         val |= set;
1501         if (old != val)
1502                 writel(val, ptr);
1503 }
1504
1505 static void mvpp22_gop_init_rgmii(struct mvpp2_port *port)
1506 {
1507         struct mvpp2 *priv = port->priv;
1508         u32 val;
1509
1510         regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val);
1511         val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT;
1512         regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val);
1513
1514         regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val);
1515         if (port->gop_id == 2)
1516                 val |= GENCONF_CTRL0_PORT2_RGMII;
1517         else if (port->gop_id == 3)
1518                 val |= GENCONF_CTRL0_PORT3_RGMII_MII;
1519         regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val);
1520 }
1521
1522 static void mvpp22_gop_init_sgmii(struct mvpp2_port *port)
1523 {
1524         struct mvpp2 *priv = port->priv;
1525         u32 val;
1526
1527         regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val);
1528         val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT |
1529                GENCONF_PORT_CTRL0_RX_DATA_SAMPLE;
1530         regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val);
1531
1532         if (port->gop_id > 1) {
1533                 regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val);
1534                 if (port->gop_id == 2)
1535                         val &= ~GENCONF_CTRL0_PORT2_RGMII;
1536                 else if (port->gop_id == 3)
1537                         val &= ~GENCONF_CTRL0_PORT3_RGMII_MII;
1538                 regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val);
1539         }
1540 }
1541
1542 static void mvpp22_gop_init_10gkr(struct mvpp2_port *port)
1543 {
1544         struct mvpp2 *priv = port->priv;
1545         void __iomem *mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id);
1546         void __iomem *xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id);
1547         u32 val;
1548
1549         val = readl(xpcs + MVPP22_XPCS_CFG0);
1550         val &= ~(MVPP22_XPCS_CFG0_PCS_MODE(0x3) |
1551                  MVPP22_XPCS_CFG0_ACTIVE_LANE(0x3));
1552         val |= MVPP22_XPCS_CFG0_ACTIVE_LANE(2);
1553         writel(val, xpcs + MVPP22_XPCS_CFG0);
1554
1555         val = readl(mpcs + MVPP22_MPCS_CTRL);
1556         val &= ~MVPP22_MPCS_CTRL_FWD_ERR_CONN;
1557         writel(val, mpcs + MVPP22_MPCS_CTRL);
1558
1559         val = readl(mpcs + MVPP22_MPCS_CLK_RESET);
1560         val &= ~MVPP22_MPCS_CLK_RESET_DIV_RATIO(0x7);
1561         val |= MVPP22_MPCS_CLK_RESET_DIV_RATIO(1);
1562         writel(val, mpcs + MVPP22_MPCS_CLK_RESET);
1563 }
1564
1565 static void mvpp22_gop_fca_enable_periodic(struct mvpp2_port *port, bool en)
1566 {
1567         struct mvpp2 *priv = port->priv;
1568         void __iomem *fca = priv->iface_base + MVPP22_FCA_BASE(port->gop_id);
1569         u32 val;
1570
1571         val = readl(fca + MVPP22_FCA_CONTROL_REG);
1572         val &= ~MVPP22_FCA_ENABLE_PERIODIC;
1573         if (en)
1574                 val |= MVPP22_FCA_ENABLE_PERIODIC;
1575         writel(val, fca + MVPP22_FCA_CONTROL_REG);
1576 }
1577
1578 static void mvpp22_gop_fca_set_timer(struct mvpp2_port *port, u32 timer)
1579 {
1580         struct mvpp2 *priv = port->priv;
1581         void __iomem *fca = priv->iface_base + MVPP22_FCA_BASE(port->gop_id);
1582         u32 lsb, msb;
1583
1584         lsb = timer & MVPP22_FCA_REG_MASK;
1585         msb = timer >> MVPP22_FCA_REG_SIZE;
1586
1587         writel(lsb, fca + MVPP22_PERIODIC_COUNTER_LSB_REG);
1588         writel(msb, fca + MVPP22_PERIODIC_COUNTER_MSB_REG);
1589 }
1590
1591 /* Set Flow Control timer x100 faster than pause quanta to ensure that link
1592  * partner won't send traffic if port is in XOFF mode.
1593  */
1594 static void mvpp22_gop_fca_set_periodic_timer(struct mvpp2_port *port)
1595 {
1596         u32 timer;
1597
1598         timer = (port->priv->tclk / (USEC_PER_SEC * FC_CLK_DIVIDER))
1599                 * FC_QUANTA;
1600
1601         mvpp22_gop_fca_enable_periodic(port, false);
1602
1603         mvpp22_gop_fca_set_timer(port, timer);
1604
1605         mvpp22_gop_fca_enable_periodic(port, true);
1606 }
1607
1608 static int mvpp22_gop_init(struct mvpp2_port *port)
1609 {
1610         struct mvpp2 *priv = port->priv;
1611         u32 val;
1612
1613         if (!priv->sysctrl_base)
1614                 return 0;
1615
1616         switch (port->phy_interface) {
1617         case PHY_INTERFACE_MODE_RGMII:
1618         case PHY_INTERFACE_MODE_RGMII_ID:
1619         case PHY_INTERFACE_MODE_RGMII_RXID:
1620         case PHY_INTERFACE_MODE_RGMII_TXID:
1621                 if (!mvpp2_port_supports_rgmii(port))
1622                         goto invalid_conf;
1623                 mvpp22_gop_init_rgmii(port);
1624                 break;
1625         case PHY_INTERFACE_MODE_SGMII:
1626         case PHY_INTERFACE_MODE_1000BASEX:
1627         case PHY_INTERFACE_MODE_2500BASEX:
1628                 mvpp22_gop_init_sgmii(port);
1629                 break;
1630         case PHY_INTERFACE_MODE_10GBASER:
1631                 if (!mvpp2_port_supports_xlg(port))
1632                         goto invalid_conf;
1633                 mvpp22_gop_init_10gkr(port);
1634                 break;
1635         default:
1636                 goto unsupported_conf;
1637         }
1638
1639         regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL1, &val);
1640         val |= GENCONF_PORT_CTRL1_RESET(port->gop_id) |
1641                GENCONF_PORT_CTRL1_EN(port->gop_id);
1642         regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL1, val);
1643
1644         regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val);
1645         val |= GENCONF_PORT_CTRL0_CLK_DIV_PHASE_CLR;
1646         regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val);
1647
1648         regmap_read(priv->sysctrl_base, GENCONF_SOFT_RESET1, &val);
1649         val |= GENCONF_SOFT_RESET1_GOP;
1650         regmap_write(priv->sysctrl_base, GENCONF_SOFT_RESET1, val);
1651
1652         mvpp22_gop_fca_set_periodic_timer(port);
1653
1654 unsupported_conf:
1655         return 0;
1656
1657 invalid_conf:
1658         netdev_err(port->dev, "Invalid port configuration\n");
1659         return -EINVAL;
1660 }
1661
1662 static void mvpp22_gop_unmask_irq(struct mvpp2_port *port)
1663 {
1664         u32 val;
1665
1666         if (phy_interface_mode_is_rgmii(port->phy_interface) ||
1667             phy_interface_mode_is_8023z(port->phy_interface) ||
1668             port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
1669                 /* Enable the GMAC link status irq for this port */
1670                 val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK);
1671                 val |= MVPP22_GMAC_INT_SUM_MASK_LINK_STAT;
1672                 writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK);
1673         }
1674
1675         if (mvpp2_port_supports_xlg(port)) {
1676                 /* Enable the XLG/GIG irqs for this port */
1677                 val = readl(port->base + MVPP22_XLG_EXT_INT_MASK);
1678                 if (mvpp2_is_xlg(port->phy_interface))
1679                         val |= MVPP22_XLG_EXT_INT_MASK_XLG;
1680                 else
1681                         val |= MVPP22_XLG_EXT_INT_MASK_GIG;
1682                 writel(val, port->base + MVPP22_XLG_EXT_INT_MASK);
1683         }
1684 }
1685
1686 static void mvpp22_gop_mask_irq(struct mvpp2_port *port)
1687 {
1688         u32 val;
1689
1690         if (mvpp2_port_supports_xlg(port)) {
1691                 val = readl(port->base + MVPP22_XLG_EXT_INT_MASK);
1692                 val &= ~(MVPP22_XLG_EXT_INT_MASK_XLG |
1693                          MVPP22_XLG_EXT_INT_MASK_GIG);
1694                 writel(val, port->base + MVPP22_XLG_EXT_INT_MASK);
1695         }
1696
1697         if (phy_interface_mode_is_rgmii(port->phy_interface) ||
1698             phy_interface_mode_is_8023z(port->phy_interface) ||
1699             port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
1700                 val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK);
1701                 val &= ~MVPP22_GMAC_INT_SUM_MASK_LINK_STAT;
1702                 writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK);
1703         }
1704 }
1705
1706 static void mvpp22_gop_setup_irq(struct mvpp2_port *port)
1707 {
1708         u32 val;
1709
1710         mvpp2_modify(port->base + MVPP22_GMAC_INT_SUM_MASK,
1711                      MVPP22_GMAC_INT_SUM_MASK_PTP,
1712                      MVPP22_GMAC_INT_SUM_MASK_PTP);
1713
1714         if (port->phylink ||
1715             phy_interface_mode_is_rgmii(port->phy_interface) ||
1716             phy_interface_mode_is_8023z(port->phy_interface) ||
1717             port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
1718                 val = readl(port->base + MVPP22_GMAC_INT_MASK);
1719                 val |= MVPP22_GMAC_INT_MASK_LINK_STAT;
1720                 writel(val, port->base + MVPP22_GMAC_INT_MASK);
1721         }
1722
1723         if (mvpp2_port_supports_xlg(port)) {
1724                 val = readl(port->base + MVPP22_XLG_INT_MASK);
1725                 val |= MVPP22_XLG_INT_MASK_LINK;
1726                 writel(val, port->base + MVPP22_XLG_INT_MASK);
1727
1728                 mvpp2_modify(port->base + MVPP22_XLG_EXT_INT_MASK,
1729                              MVPP22_XLG_EXT_INT_MASK_PTP,
1730                              MVPP22_XLG_EXT_INT_MASK_PTP);
1731         }
1732
1733         mvpp22_gop_unmask_irq(port);
1734 }
1735
1736 /* Sets the PHY mode of the COMPHY (which configures the serdes lanes).
1737  *
1738  * The PHY mode used by the PPv2 driver comes from the network subsystem, while
1739  * the one given to the COMPHY comes from the generic PHY subsystem. Hence they
1740  * differ.
1741  *
1742  * The COMPHY configures the serdes lanes regardless of the actual use of the
1743  * lanes by the physical layer. This is why configurations like
1744  * "PPv2 (2500BaseX) - COMPHY (2500SGMII)" are valid.
1745  */
1746 static int mvpp22_comphy_init(struct mvpp2_port *port)
1747 {
1748         int ret;
1749
1750         if (!port->comphy)
1751                 return 0;
1752
1753         ret = phy_set_mode_ext(port->comphy, PHY_MODE_ETHERNET,
1754                                port->phy_interface);
1755         if (ret)
1756                 return ret;
1757
1758         return phy_power_on(port->comphy);
1759 }
1760
1761 static void mvpp2_port_enable(struct mvpp2_port *port)
1762 {
1763         u32 val;
1764
1765         if (mvpp2_port_supports_xlg(port) &&
1766             mvpp2_is_xlg(port->phy_interface)) {
1767                 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
1768                 val |= MVPP22_XLG_CTRL0_PORT_EN;
1769                 val &= ~MVPP22_XLG_CTRL0_MIB_CNT_DIS;
1770                 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
1771         } else {
1772                 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
1773                 val |= MVPP2_GMAC_PORT_EN_MASK;
1774                 val |= MVPP2_GMAC_MIB_CNTR_EN_MASK;
1775                 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
1776         }
1777 }
1778
1779 static void mvpp2_port_disable(struct mvpp2_port *port)
1780 {
1781         u32 val;
1782
1783         if (mvpp2_port_supports_xlg(port) &&
1784             mvpp2_is_xlg(port->phy_interface)) {
1785                 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
1786                 val &= ~MVPP22_XLG_CTRL0_PORT_EN;
1787                 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
1788         }
1789
1790         val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
1791         val &= ~(MVPP2_GMAC_PORT_EN_MASK);
1792         writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
1793 }
1794
1795 /* Set IEEE 802.3x Flow Control Xon Packet Transmission Mode */
1796 static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port)
1797 {
1798         u32 val;
1799
1800         val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) &
1801                     ~MVPP2_GMAC_PERIODIC_XON_EN_MASK;
1802         writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
1803 }
1804
1805 /* Configure loopback port */
1806 static void mvpp2_port_loopback_set(struct mvpp2_port *port,
1807                                     const struct phylink_link_state *state)
1808 {
1809         u32 val;
1810
1811         val = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
1812
1813         if (state->speed == 1000)
1814                 val |= MVPP2_GMAC_GMII_LB_EN_MASK;
1815         else
1816                 val &= ~MVPP2_GMAC_GMII_LB_EN_MASK;
1817
1818         if (phy_interface_mode_is_8023z(state->interface) ||
1819             state->interface == PHY_INTERFACE_MODE_SGMII)
1820                 val |= MVPP2_GMAC_PCS_LB_EN_MASK;
1821         else
1822                 val &= ~MVPP2_GMAC_PCS_LB_EN_MASK;
1823
1824         writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
1825 }
1826
1827 enum {
1828         ETHTOOL_XDP_REDIRECT,
1829         ETHTOOL_XDP_PASS,
1830         ETHTOOL_XDP_DROP,
1831         ETHTOOL_XDP_TX,
1832         ETHTOOL_XDP_TX_ERR,
1833         ETHTOOL_XDP_XMIT,
1834         ETHTOOL_XDP_XMIT_ERR,
1835 };
1836
1837 struct mvpp2_ethtool_counter {
1838         unsigned int offset;
1839         const char string[ETH_GSTRING_LEN];
1840         bool reg_is_64b;
1841 };
1842
1843 static u64 mvpp2_read_count(struct mvpp2_port *port,
1844                             const struct mvpp2_ethtool_counter *counter)
1845 {
1846         u64 val;
1847
1848         val = readl(port->stats_base + counter->offset);
1849         if (counter->reg_is_64b)
1850                 val += (u64)readl(port->stats_base + counter->offset + 4) << 32;
1851
1852         return val;
1853 }
1854
1855 /* Some counters are accessed indirectly by first writing an index to
1856  * MVPP2_CTRS_IDX. The index can represent various resources depending on the
1857  * register we access, it can be a hit counter for some classification tables,
1858  * a counter specific to a rxq, a txq or a buffer pool.
1859  */
1860 static u32 mvpp2_read_index(struct mvpp2 *priv, u32 index, u32 reg)
1861 {
1862         mvpp2_write(priv, MVPP2_CTRS_IDX, index);
1863         return mvpp2_read(priv, reg);
1864 }
1865
1866 /* Due to the fact that software statistics and hardware statistics are, by
1867  * design, incremented at different moments in the chain of packet processing,
1868  * it is very likely that incoming packets could have been dropped after being
1869  * counted by hardware but before reaching software statistics (most probably
1870  * multicast packets), and in the oppposite way, during transmission, FCS bytes
1871  * are added in between as well as TSO skb will be split and header bytes added.
1872  * Hence, statistics gathered from userspace with ifconfig (software) and
1873  * ethtool (hardware) cannot be compared.
1874  */
1875 static const struct mvpp2_ethtool_counter mvpp2_ethtool_mib_regs[] = {
1876         { MVPP2_MIB_GOOD_OCTETS_RCVD, "good_octets_received", true },
1877         { MVPP2_MIB_BAD_OCTETS_RCVD, "bad_octets_received" },
1878         { MVPP2_MIB_CRC_ERRORS_SENT, "crc_errors_sent" },
1879         { MVPP2_MIB_UNICAST_FRAMES_RCVD, "unicast_frames_received" },
1880         { MVPP2_MIB_BROADCAST_FRAMES_RCVD, "broadcast_frames_received" },
1881         { MVPP2_MIB_MULTICAST_FRAMES_RCVD, "multicast_frames_received" },
1882         { MVPP2_MIB_FRAMES_64_OCTETS, "frames_64_octets" },
1883         { MVPP2_MIB_FRAMES_65_TO_127_OCTETS, "frames_65_to_127_octet" },
1884         { MVPP2_MIB_FRAMES_128_TO_255_OCTETS, "frames_128_to_255_octet" },
1885         { MVPP2_MIB_FRAMES_256_TO_511_OCTETS, "frames_256_to_511_octet" },
1886         { MVPP2_MIB_FRAMES_512_TO_1023_OCTETS, "frames_512_to_1023_octet" },
1887         { MVPP2_MIB_FRAMES_1024_TO_MAX_OCTETS, "frames_1024_to_max_octet" },
1888         { MVPP2_MIB_GOOD_OCTETS_SENT, "good_octets_sent", true },
1889         { MVPP2_MIB_UNICAST_FRAMES_SENT, "unicast_frames_sent" },
1890         { MVPP2_MIB_MULTICAST_FRAMES_SENT, "multicast_frames_sent" },
1891         { MVPP2_MIB_BROADCAST_FRAMES_SENT, "broadcast_frames_sent" },
1892         { MVPP2_MIB_FC_SENT, "fc_sent" },
1893         { MVPP2_MIB_FC_RCVD, "fc_received" },
1894         { MVPP2_MIB_RX_FIFO_OVERRUN, "rx_fifo_overrun" },
1895         { MVPP2_MIB_UNDERSIZE_RCVD, "undersize_received" },
1896         { MVPP2_MIB_FRAGMENTS_RCVD, "fragments_received" },
1897         { MVPP2_MIB_OVERSIZE_RCVD, "oversize_received" },
1898         { MVPP2_MIB_JABBER_RCVD, "jabber_received" },
1899         { MVPP2_MIB_MAC_RCV_ERROR, "mac_receive_error" },
1900         { MVPP2_MIB_BAD_CRC_EVENT, "bad_crc_event" },
1901         { MVPP2_MIB_COLLISION, "collision" },
1902         { MVPP2_MIB_LATE_COLLISION, "late_collision" },
1903 };
1904
1905 static const struct mvpp2_ethtool_counter mvpp2_ethtool_port_regs[] = {
1906         { MVPP2_OVERRUN_ETH_DROP, "rx_fifo_or_parser_overrun_drops" },
1907         { MVPP2_CLS_ETH_DROP, "rx_classifier_drops" },
1908 };
1909
1910 static const struct mvpp2_ethtool_counter mvpp2_ethtool_txq_regs[] = {
1911         { MVPP2_TX_DESC_ENQ_CTR, "txq_%d_desc_enqueue" },
1912         { MVPP2_TX_DESC_ENQ_TO_DDR_CTR, "txq_%d_desc_enqueue_to_ddr" },
1913         { MVPP2_TX_BUFF_ENQ_TO_DDR_CTR, "txq_%d_buff_euqueue_to_ddr" },
1914         { MVPP2_TX_DESC_ENQ_HW_FWD_CTR, "txq_%d_desc_hardware_forwarded" },
1915         { MVPP2_TX_PKTS_DEQ_CTR, "txq_%d_packets_dequeued" },
1916         { MVPP2_TX_PKTS_FULL_QUEUE_DROP_CTR, "txq_%d_queue_full_drops" },
1917         { MVPP2_TX_PKTS_EARLY_DROP_CTR, "txq_%d_packets_early_drops" },
1918         { MVPP2_TX_PKTS_BM_DROP_CTR, "txq_%d_packets_bm_drops" },
1919         { MVPP2_TX_PKTS_BM_MC_DROP_CTR, "txq_%d_packets_rep_bm_drops" },
1920 };
1921
1922 static const struct mvpp2_ethtool_counter mvpp2_ethtool_rxq_regs[] = {
1923         { MVPP2_RX_DESC_ENQ_CTR, "rxq_%d_desc_enqueue" },
1924         { MVPP2_RX_PKTS_FULL_QUEUE_DROP_CTR, "rxq_%d_queue_full_drops" },
1925         { MVPP2_RX_PKTS_EARLY_DROP_CTR, "rxq_%d_packets_early_drops" },
1926         { MVPP2_RX_PKTS_BM_DROP_CTR, "rxq_%d_packets_bm_drops" },
1927 };
1928
1929 static const struct mvpp2_ethtool_counter mvpp2_ethtool_xdp[] = {
1930         { ETHTOOL_XDP_REDIRECT, "rx_xdp_redirect", },
1931         { ETHTOOL_XDP_PASS, "rx_xdp_pass", },
1932         { ETHTOOL_XDP_DROP, "rx_xdp_drop", },
1933         { ETHTOOL_XDP_TX, "rx_xdp_tx", },
1934         { ETHTOOL_XDP_TX_ERR, "rx_xdp_tx_errors", },
1935         { ETHTOOL_XDP_XMIT, "tx_xdp_xmit", },
1936         { ETHTOOL_XDP_XMIT_ERR, "tx_xdp_xmit_errors", },
1937 };
1938
1939 #define MVPP2_N_ETHTOOL_STATS(ntxqs, nrxqs)     (ARRAY_SIZE(mvpp2_ethtool_mib_regs) + \
1940                                                  ARRAY_SIZE(mvpp2_ethtool_port_regs) + \
1941                                                  (ARRAY_SIZE(mvpp2_ethtool_txq_regs) * (ntxqs)) + \
1942                                                  (ARRAY_SIZE(mvpp2_ethtool_rxq_regs) * (nrxqs)) + \
1943                                                  ARRAY_SIZE(mvpp2_ethtool_xdp))
1944
1945 static void mvpp2_ethtool_get_strings(struct net_device *netdev, u32 sset,
1946                                       u8 *data)
1947 {
1948         struct mvpp2_port *port = netdev_priv(netdev);
1949         int i, q;
1950
1951         if (sset != ETH_SS_STATS)
1952                 return;
1953
1954         for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_mib_regs); i++) {
1955                 strscpy(data, mvpp2_ethtool_mib_regs[i].string,
1956                         ETH_GSTRING_LEN);
1957                 data += ETH_GSTRING_LEN;
1958         }
1959
1960         for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_port_regs); i++) {
1961                 strscpy(data, mvpp2_ethtool_port_regs[i].string,
1962                         ETH_GSTRING_LEN);
1963                 data += ETH_GSTRING_LEN;
1964         }
1965
1966         for (q = 0; q < port->ntxqs; q++) {
1967                 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_txq_regs); i++) {
1968                         snprintf(data, ETH_GSTRING_LEN,
1969                                  mvpp2_ethtool_txq_regs[i].string, q);
1970                         data += ETH_GSTRING_LEN;
1971                 }
1972         }
1973
1974         for (q = 0; q < port->nrxqs; q++) {
1975                 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_rxq_regs); i++) {
1976                         snprintf(data, ETH_GSTRING_LEN,
1977                                  mvpp2_ethtool_rxq_regs[i].string,
1978                                  q);
1979                         data += ETH_GSTRING_LEN;
1980                 }
1981         }
1982
1983         for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_xdp); i++) {
1984                 strscpy(data, mvpp2_ethtool_xdp[i].string,
1985                         ETH_GSTRING_LEN);
1986                 data += ETH_GSTRING_LEN;
1987         }
1988 }
1989
1990 static void
1991 mvpp2_get_xdp_stats(struct mvpp2_port *port, struct mvpp2_pcpu_stats *xdp_stats)
1992 {
1993         unsigned int start;
1994         unsigned int cpu;
1995
1996         /* Gather XDP Statistics */
1997         for_each_possible_cpu(cpu) {
1998                 struct mvpp2_pcpu_stats *cpu_stats;
1999                 u64     xdp_redirect;
2000                 u64     xdp_pass;
2001                 u64     xdp_drop;
2002                 u64     xdp_xmit;
2003                 u64     xdp_xmit_err;
2004                 u64     xdp_tx;
2005                 u64     xdp_tx_err;
2006
2007                 cpu_stats = per_cpu_ptr(port->stats, cpu);
2008                 do {
2009                         start = u64_stats_fetch_begin_irq(&cpu_stats->syncp);
2010                         xdp_redirect = cpu_stats->xdp_redirect;
2011                         xdp_pass   = cpu_stats->xdp_pass;
2012                         xdp_drop = cpu_stats->xdp_drop;
2013                         xdp_xmit   = cpu_stats->xdp_xmit;
2014                         xdp_xmit_err   = cpu_stats->xdp_xmit_err;
2015                         xdp_tx   = cpu_stats->xdp_tx;
2016                         xdp_tx_err   = cpu_stats->xdp_tx_err;
2017                 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start));
2018
2019                 xdp_stats->xdp_redirect += xdp_redirect;
2020                 xdp_stats->xdp_pass   += xdp_pass;
2021                 xdp_stats->xdp_drop += xdp_drop;
2022                 xdp_stats->xdp_xmit   += xdp_xmit;
2023                 xdp_stats->xdp_xmit_err   += xdp_xmit_err;
2024                 xdp_stats->xdp_tx   += xdp_tx;
2025                 xdp_stats->xdp_tx_err   += xdp_tx_err;
2026         }
2027 }
2028
2029 static void mvpp2_read_stats(struct mvpp2_port *port)
2030 {
2031         struct mvpp2_pcpu_stats xdp_stats = {};
2032         const struct mvpp2_ethtool_counter *s;
2033         u64 *pstats;
2034         int i, q;
2035
2036         pstats = port->ethtool_stats;
2037
2038         for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_mib_regs); i++)
2039                 *pstats++ += mvpp2_read_count(port, &mvpp2_ethtool_mib_regs[i]);
2040
2041         for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_port_regs); i++)
2042                 *pstats++ += mvpp2_read(port->priv,
2043                                         mvpp2_ethtool_port_regs[i].offset +
2044                                         4 * port->id);
2045
2046         for (q = 0; q < port->ntxqs; q++)
2047                 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_txq_regs); i++)
2048                         *pstats++ += mvpp2_read_index(port->priv,
2049                                                       MVPP22_CTRS_TX_CTR(port->id, q),
2050                                                       mvpp2_ethtool_txq_regs[i].offset);
2051
2052         /* Rxqs are numbered from 0 from the user standpoint, but not from the
2053          * driver's. We need to add the  port->first_rxq offset.
2054          */
2055         for (q = 0; q < port->nrxqs; q++)
2056                 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_rxq_regs); i++)
2057                         *pstats++ += mvpp2_read_index(port->priv,
2058                                                       port->first_rxq + q,
2059                                                       mvpp2_ethtool_rxq_regs[i].offset);
2060
2061         /* Gather XDP Statistics */
2062         mvpp2_get_xdp_stats(port, &xdp_stats);
2063
2064         for (i = 0, s = mvpp2_ethtool_xdp;
2065                  s < mvpp2_ethtool_xdp + ARRAY_SIZE(mvpp2_ethtool_xdp);
2066              s++, i++) {
2067                 switch (s->offset) {
2068                 case ETHTOOL_XDP_REDIRECT:
2069                         *pstats++ = xdp_stats.xdp_redirect;
2070                         break;
2071                 case ETHTOOL_XDP_PASS:
2072                         *pstats++ = xdp_stats.xdp_pass;
2073                         break;
2074                 case ETHTOOL_XDP_DROP:
2075                         *pstats++ = xdp_stats.xdp_drop;
2076                         break;
2077                 case ETHTOOL_XDP_TX:
2078                         *pstats++ = xdp_stats.xdp_tx;
2079                         break;
2080                 case ETHTOOL_XDP_TX_ERR:
2081                         *pstats++ = xdp_stats.xdp_tx_err;
2082                         break;
2083                 case ETHTOOL_XDP_XMIT:
2084                         *pstats++ = xdp_stats.xdp_xmit;
2085                         break;
2086                 case ETHTOOL_XDP_XMIT_ERR:
2087                         *pstats++ = xdp_stats.xdp_xmit_err;
2088                         break;
2089                 }
2090         }
2091 }
2092
2093 static void mvpp2_gather_hw_statistics(struct work_struct *work)
2094 {
2095         struct delayed_work *del_work = to_delayed_work(work);
2096         struct mvpp2_port *port = container_of(del_work, struct mvpp2_port,
2097                                                stats_work);
2098
2099         mutex_lock(&port->gather_stats_lock);
2100
2101         mvpp2_read_stats(port);
2102
2103         /* No need to read again the counters right after this function if it
2104          * was called asynchronously by the user (ie. use of ethtool).
2105          */
2106         cancel_delayed_work(&port->stats_work);
2107         queue_delayed_work(port->priv->stats_queue, &port->stats_work,
2108                            MVPP2_MIB_COUNTERS_STATS_DELAY);
2109
2110         mutex_unlock(&port->gather_stats_lock);
2111 }
2112
2113 static void mvpp2_ethtool_get_stats(struct net_device *dev,
2114                                     struct ethtool_stats *stats, u64 *data)
2115 {
2116         struct mvpp2_port *port = netdev_priv(dev);
2117
2118         /* Update statistics for the given port, then take the lock to avoid
2119          * concurrent accesses on the ethtool_stats structure during its copy.
2120          */
2121         mvpp2_gather_hw_statistics(&port->stats_work.work);
2122
2123         mutex_lock(&port->gather_stats_lock);
2124         memcpy(data, port->ethtool_stats,
2125                sizeof(u64) * MVPP2_N_ETHTOOL_STATS(port->ntxqs, port->nrxqs));
2126         mutex_unlock(&port->gather_stats_lock);
2127 }
2128
2129 static int mvpp2_ethtool_get_sset_count(struct net_device *dev, int sset)
2130 {
2131         struct mvpp2_port *port = netdev_priv(dev);
2132
2133         if (sset == ETH_SS_STATS)
2134                 return MVPP2_N_ETHTOOL_STATS(port->ntxqs, port->nrxqs);
2135
2136         return -EOPNOTSUPP;
2137 }
2138
2139 static void mvpp2_mac_reset_assert(struct mvpp2_port *port)
2140 {
2141         u32 val;
2142
2143         val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) |
2144               MVPP2_GMAC_PORT_RESET_MASK;
2145         writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
2146
2147         if (port->priv->hw_version >= MVPP22 && port->gop_id == 0) {
2148                 val = readl(port->base + MVPP22_XLG_CTRL0_REG) &
2149                       ~MVPP22_XLG_CTRL0_MAC_RESET_DIS;
2150                 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
2151         }
2152 }
2153
2154 static void mvpp22_pcs_reset_assert(struct mvpp2_port *port)
2155 {
2156         struct mvpp2 *priv = port->priv;
2157         void __iomem *mpcs, *xpcs;
2158         u32 val;
2159
2160         if (port->priv->hw_version == MVPP21 || port->gop_id != 0)
2161                 return;
2162
2163         mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id);
2164         xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id);
2165
2166         val = readl(mpcs + MVPP22_MPCS_CLK_RESET);
2167         val &= ~(MAC_CLK_RESET_MAC | MAC_CLK_RESET_SD_RX | MAC_CLK_RESET_SD_TX);
2168         val |= MVPP22_MPCS_CLK_RESET_DIV_SET;
2169         writel(val, mpcs + MVPP22_MPCS_CLK_RESET);
2170
2171         val = readl(xpcs + MVPP22_XPCS_CFG0);
2172         writel(val & ~MVPP22_XPCS_CFG0_RESET_DIS, xpcs + MVPP22_XPCS_CFG0);
2173 }
2174
2175 static void mvpp22_pcs_reset_deassert(struct mvpp2_port *port)
2176 {
2177         struct mvpp2 *priv = port->priv;
2178         void __iomem *mpcs, *xpcs;
2179         u32 val;
2180
2181         if (port->priv->hw_version == MVPP21 || port->gop_id != 0)
2182                 return;
2183
2184         mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id);
2185         xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id);
2186
2187         switch (port->phy_interface) {
2188         case PHY_INTERFACE_MODE_10GBASER:
2189                 val = readl(mpcs + MVPP22_MPCS_CLK_RESET);
2190                 val |= MAC_CLK_RESET_MAC | MAC_CLK_RESET_SD_RX |
2191                        MAC_CLK_RESET_SD_TX;
2192                 val &= ~MVPP22_MPCS_CLK_RESET_DIV_SET;
2193                 writel(val, mpcs + MVPP22_MPCS_CLK_RESET);
2194                 break;
2195         case PHY_INTERFACE_MODE_XAUI:
2196         case PHY_INTERFACE_MODE_RXAUI:
2197                 val = readl(xpcs + MVPP22_XPCS_CFG0);
2198                 writel(val | MVPP22_XPCS_CFG0_RESET_DIS, xpcs + MVPP22_XPCS_CFG0);
2199                 break;
2200         default:
2201                 break;
2202         }
2203 }
2204
2205 /* Change maximum receive size of the port */
2206 static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port)
2207 {
2208         u32 val;
2209
2210         val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
2211         val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK;
2212         val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) <<
2213                     MVPP2_GMAC_MAX_RX_SIZE_OFFS);
2214         writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
2215 }
2216
2217 /* Change maximum receive size of the port */
2218 static inline void mvpp2_xlg_max_rx_size_set(struct mvpp2_port *port)
2219 {
2220         u32 val;
2221
2222         val =  readl(port->base + MVPP22_XLG_CTRL1_REG);
2223         val &= ~MVPP22_XLG_CTRL1_FRAMESIZELIMIT_MASK;
2224         val |= ((port->pkt_size - MVPP2_MH_SIZE) / 2) <<
2225                MVPP22_XLG_CTRL1_FRAMESIZELIMIT_OFFS;
2226         writel(val, port->base + MVPP22_XLG_CTRL1_REG);
2227 }
2228
2229 /* Set defaults to the MVPP2 port */
2230 static void mvpp2_defaults_set(struct mvpp2_port *port)
2231 {
2232         int tx_port_num, val, queue, lrxq;
2233
2234         if (port->priv->hw_version == MVPP21) {
2235                 /* Update TX FIFO MIN Threshold */
2236                 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
2237                 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
2238                 /* Min. TX threshold must be less than minimal packet length */
2239                 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2);
2240                 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
2241         }
2242
2243         /* Disable Legacy WRR, Disable EJP, Release from reset */
2244         tx_port_num = mvpp2_egress_port(port);
2245         mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG,
2246                     tx_port_num);
2247         mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0);
2248
2249         /* Set TXQ scheduling to Round-Robin */
2250         mvpp2_write(port->priv, MVPP2_TXP_SCHED_FIXED_PRIO_REG, 0);
2251
2252         /* Close bandwidth for all queues */
2253         for (queue = 0; queue < MVPP2_MAX_TXQ; queue++)
2254                 mvpp2_write(port->priv,
2255                             MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(queue), 0);
2256
2257         /* Set refill period to 1 usec, refill tokens
2258          * and bucket size to maximum
2259          */
2260         mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG,
2261                     port->priv->tclk / USEC_PER_SEC);
2262         val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG);
2263         val &= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK;
2264         val |= MVPP2_TXP_REFILL_PERIOD_MASK(1);
2265         val |= MVPP2_TXP_REFILL_TOKENS_ALL_MASK;
2266         mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val);
2267         val = MVPP2_TXP_TOKEN_SIZE_MAX;
2268         mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
2269
2270         /* Set MaximumLowLatencyPacketSize value to 256 */
2271         mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id),
2272                     MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK |
2273                     MVPP2_RX_LOW_LATENCY_PKT_SIZE(256));
2274
2275         /* Enable Rx cache snoop */
2276         for (lrxq = 0; lrxq < port->nrxqs; lrxq++) {
2277                 queue = port->rxqs[lrxq]->id;
2278                 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
2279                 val |= MVPP2_SNOOP_PKT_SIZE_MASK |
2280                            MVPP2_SNOOP_BUF_HDR_MASK;
2281                 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
2282         }
2283
2284         /* At default, mask all interrupts to all present cpus */
2285         mvpp2_interrupts_disable(port);
2286 }
2287
2288 /* Enable/disable receiving packets */
2289 static void mvpp2_ingress_enable(struct mvpp2_port *port)
2290 {
2291         u32 val;
2292         int lrxq, queue;
2293
2294         for (lrxq = 0; lrxq < port->nrxqs; lrxq++) {
2295                 queue = port->rxqs[lrxq]->id;
2296                 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
2297                 val &= ~MVPP2_RXQ_DISABLE_MASK;
2298                 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
2299         }
2300 }
2301
2302 static void mvpp2_ingress_disable(struct mvpp2_port *port)
2303 {
2304         u32 val;
2305         int lrxq, queue;
2306
2307         for (lrxq = 0; lrxq < port->nrxqs; lrxq++) {
2308                 queue = port->rxqs[lrxq]->id;
2309                 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
2310                 val |= MVPP2_RXQ_DISABLE_MASK;
2311                 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
2312         }
2313 }
2314
2315 /* Enable transmit via physical egress queue
2316  * - HW starts take descriptors from DRAM
2317  */
2318 static void mvpp2_egress_enable(struct mvpp2_port *port)
2319 {
2320         u32 qmap;
2321         int queue;
2322         int tx_port_num = mvpp2_egress_port(port);
2323
2324         /* Enable all initialized TXs. */
2325         qmap = 0;
2326         for (queue = 0; queue < port->ntxqs; queue++) {
2327                 struct mvpp2_tx_queue *txq = port->txqs[queue];
2328
2329                 if (txq->descs)
2330                         qmap |= (1 << queue);
2331         }
2332
2333         mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
2334         mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap);
2335 }
2336
2337 /* Disable transmit via physical egress queue
2338  * - HW doesn't take descriptors from DRAM
2339  */
2340 static void mvpp2_egress_disable(struct mvpp2_port *port)
2341 {
2342         u32 reg_data;
2343         int delay;
2344         int tx_port_num = mvpp2_egress_port(port);
2345
2346         /* Issue stop command for active channels only */
2347         mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
2348         reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) &
2349                     MVPP2_TXP_SCHED_ENQ_MASK;
2350         if (reg_data != 0)
2351                 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG,
2352                             (reg_data << MVPP2_TXP_SCHED_DISQ_OFFSET));
2353
2354         /* Wait for all Tx activity to terminate. */
2355         delay = 0;
2356         do {
2357                 if (delay >= MVPP2_TX_DISABLE_TIMEOUT_MSEC) {
2358                         netdev_warn(port->dev,
2359                                     "Tx stop timed out, status=0x%08x\n",
2360                                     reg_data);
2361                         break;
2362                 }
2363                 mdelay(1);
2364                 delay++;
2365
2366                 /* Check port TX Command register that all
2367                  * Tx queues are stopped
2368                  */
2369                 reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG);
2370         } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK);
2371 }
2372
2373 /* Rx descriptors helper methods */
2374
2375 /* Get number of Rx descriptors occupied by received packets */
2376 static inline int
2377 mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id)
2378 {
2379         u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id));
2380
2381         return val & MVPP2_RXQ_OCCUPIED_MASK;
2382 }
2383
2384 /* Update Rx queue status with the number of occupied and available
2385  * Rx descriptor slots.
2386  */
2387 static inline void
2388 mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id,
2389                         int used_count, int free_count)
2390 {
2391         /* Decrement the number of used descriptors and increment count
2392          * increment the number of free descriptors.
2393          */
2394         u32 val = used_count | (free_count << MVPP2_RXQ_NUM_NEW_OFFSET);
2395
2396         mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val);
2397 }
2398
2399 /* Get pointer to next RX descriptor to be processed by SW */
2400 static inline struct mvpp2_rx_desc *
2401 mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue *rxq)
2402 {
2403         int rx_desc = rxq->next_desc_to_proc;
2404
2405         rxq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(rxq, rx_desc);
2406         prefetch(rxq->descs + rxq->next_desc_to_proc);
2407         return rxq->descs + rx_desc;
2408 }
2409
2410 /* Set rx queue offset */
2411 static void mvpp2_rxq_offset_set(struct mvpp2_port *port,
2412                                  int prxq, int offset)
2413 {
2414         u32 val;
2415
2416         /* Convert offset from bytes to units of 32 bytes */
2417         offset = offset >> 5;
2418
2419         val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
2420         val &= ~MVPP2_RXQ_PACKET_OFFSET_MASK;
2421
2422         /* Offset is in */
2423         val |= ((offset << MVPP2_RXQ_PACKET_OFFSET_OFFS) &
2424                     MVPP2_RXQ_PACKET_OFFSET_MASK);
2425
2426         mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
2427 }
2428
2429 /* Tx descriptors helper methods */
2430
2431 /* Get pointer to next Tx descriptor to be processed (send) by HW */
2432 static struct mvpp2_tx_desc *
2433 mvpp2_txq_next_desc_get(struct mvpp2_tx_queue *txq)
2434 {
2435         int tx_desc = txq->next_desc_to_proc;
2436
2437         txq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(txq, tx_desc);
2438         return txq->descs + tx_desc;
2439 }
2440
2441 /* Update HW with number of aggregated Tx descriptors to be sent
2442  *
2443  * Called only from mvpp2_tx(), so migration is disabled, using
2444  * smp_processor_id() is OK.
2445  */
2446 static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending)
2447 {
2448         /* aggregated access - relevant TXQ number is written in TX desc */
2449         mvpp2_thread_write(port->priv,
2450                            mvpp2_cpu_to_thread(port->priv, smp_processor_id()),
2451                            MVPP2_AGGR_TXQ_UPDATE_REG, pending);
2452 }
2453
2454 /* Check if there are enough free descriptors in aggregated txq.
2455  * If not, update the number of occupied descriptors and repeat the check.
2456  *
2457  * Called only from mvpp2_tx(), so migration is disabled, using
2458  * smp_processor_id() is OK.
2459  */
2460 static int mvpp2_aggr_desc_num_check(struct mvpp2_port *port,
2461                                      struct mvpp2_tx_queue *aggr_txq, int num)
2462 {
2463         if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE) {
2464                 /* Update number of occupied aggregated Tx descriptors */
2465                 unsigned int thread =
2466                         mvpp2_cpu_to_thread(port->priv, smp_processor_id());
2467                 u32 val = mvpp2_read_relaxed(port->priv,
2468                                              MVPP2_AGGR_TXQ_STATUS_REG(thread));
2469
2470                 aggr_txq->count = val & MVPP2_AGGR_TXQ_PENDING_MASK;
2471
2472                 if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE)
2473                         return -ENOMEM;
2474         }
2475         return 0;
2476 }
2477
2478 /* Reserved Tx descriptors allocation request
2479  *
2480  * Called only from mvpp2_txq_reserved_desc_num_proc(), itself called
2481  * only by mvpp2_tx(), so migration is disabled, using
2482  * smp_processor_id() is OK.
2483  */
2484 static int mvpp2_txq_alloc_reserved_desc(struct mvpp2_port *port,
2485                                          struct mvpp2_tx_queue *txq, int num)
2486 {
2487         unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
2488         struct mvpp2 *priv = port->priv;
2489         u32 val;
2490
2491         val = (txq->id << MVPP2_TXQ_RSVD_REQ_Q_OFFSET) | num;
2492         mvpp2_thread_write_relaxed(priv, thread, MVPP2_TXQ_RSVD_REQ_REG, val);
2493
2494         val = mvpp2_thread_read_relaxed(priv, thread, MVPP2_TXQ_RSVD_RSLT_REG);
2495
2496         return val & MVPP2_TXQ_RSVD_RSLT_MASK;
2497 }
2498
2499 /* Check if there are enough reserved descriptors for transmission.
2500  * If not, request chunk of reserved descriptors and check again.
2501  */
2502 static int mvpp2_txq_reserved_desc_num_proc(struct mvpp2_port *port,
2503                                             struct mvpp2_tx_queue *txq,
2504                                             struct mvpp2_txq_pcpu *txq_pcpu,
2505                                             int num)
2506 {
2507         int req, desc_count;
2508         unsigned int thread;
2509
2510         if (txq_pcpu->reserved_num >= num)
2511                 return 0;
2512
2513         /* Not enough descriptors reserved! Update the reserved descriptor
2514          * count and check again.
2515          */
2516
2517         desc_count = 0;
2518         /* Compute total of used descriptors */
2519         for (thread = 0; thread < port->priv->nthreads; thread++) {
2520                 struct mvpp2_txq_pcpu *txq_pcpu_aux;
2521
2522                 txq_pcpu_aux = per_cpu_ptr(txq->pcpu, thread);
2523                 desc_count += txq_pcpu_aux->count;
2524                 desc_count += txq_pcpu_aux->reserved_num;
2525         }
2526
2527         req = max(MVPP2_CPU_DESC_CHUNK, num - txq_pcpu->reserved_num);
2528         desc_count += req;
2529
2530         if (desc_count >
2531            (txq->size - (MVPP2_MAX_THREADS * MVPP2_CPU_DESC_CHUNK)))
2532                 return -ENOMEM;
2533
2534         txq_pcpu->reserved_num += mvpp2_txq_alloc_reserved_desc(port, txq, req);
2535
2536         /* OK, the descriptor could have been updated: check again. */
2537         if (txq_pcpu->reserved_num < num)
2538                 return -ENOMEM;
2539         return 0;
2540 }
2541
2542 /* Release the last allocated Tx descriptor. Useful to handle DMA
2543  * mapping failures in the Tx path.
2544  */
2545 static void mvpp2_txq_desc_put(struct mvpp2_tx_queue *txq)
2546 {
2547         if (txq->next_desc_to_proc == 0)
2548                 txq->next_desc_to_proc = txq->last_desc - 1;
2549         else
2550                 txq->next_desc_to_proc--;
2551 }
2552
2553 /* Set Tx descriptors fields relevant for CSUM calculation */
2554 static u32 mvpp2_txq_desc_csum(int l3_offs, __be16 l3_proto,
2555                                int ip_hdr_len, int l4_proto)
2556 {
2557         u32 command;
2558
2559         /* fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk,
2560          * G_L4_chk, L4_type required only for checksum calculation
2561          */
2562         command = (l3_offs << MVPP2_TXD_L3_OFF_SHIFT);
2563         command |= (ip_hdr_len << MVPP2_TXD_IP_HLEN_SHIFT);
2564         command |= MVPP2_TXD_IP_CSUM_DISABLE;
2565
2566         if (l3_proto == htons(ETH_P_IP)) {
2567                 command &= ~MVPP2_TXD_IP_CSUM_DISABLE;  /* enable IPv4 csum */
2568                 command &= ~MVPP2_TXD_L3_IP6;           /* enable IPv4 */
2569         } else {
2570                 command |= MVPP2_TXD_L3_IP6;            /* enable IPv6 */
2571         }
2572
2573         if (l4_proto == IPPROTO_TCP) {
2574                 command &= ~MVPP2_TXD_L4_UDP;           /* enable TCP */
2575                 command &= ~MVPP2_TXD_L4_CSUM_FRAG;     /* generate L4 csum */
2576         } else if (l4_proto == IPPROTO_UDP) {
2577                 command |= MVPP2_TXD_L4_UDP;            /* enable UDP */
2578                 command &= ~MVPP2_TXD_L4_CSUM_FRAG;     /* generate L4 csum */
2579         } else {
2580                 command |= MVPP2_TXD_L4_CSUM_NOT;
2581         }
2582
2583         return command;
2584 }
2585
2586 /* Get number of sent descriptors and decrement counter.
2587  * The number of sent descriptors is returned.
2588  * Per-thread access
2589  *
2590  * Called only from mvpp2_txq_done(), called from mvpp2_tx()
2591  * (migration disabled) and from the TX completion tasklet (migration
2592  * disabled) so using smp_processor_id() is OK.
2593  */
2594 static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port,
2595                                            struct mvpp2_tx_queue *txq)
2596 {
2597         u32 val;
2598
2599         /* Reading status reg resets transmitted descriptor counter */
2600         val = mvpp2_thread_read_relaxed(port->priv,
2601                                         mvpp2_cpu_to_thread(port->priv, smp_processor_id()),
2602                                         MVPP2_TXQ_SENT_REG(txq->id));
2603
2604         return (val & MVPP2_TRANSMITTED_COUNT_MASK) >>
2605                 MVPP2_TRANSMITTED_COUNT_OFFSET;
2606 }
2607
2608 /* Called through on_each_cpu(), so runs on all CPUs, with migration
2609  * disabled, therefore using smp_processor_id() is OK.
2610  */
2611 static void mvpp2_txq_sent_counter_clear(void *arg)
2612 {
2613         struct mvpp2_port *port = arg;
2614         int queue;
2615
2616         /* If the thread isn't used, don't do anything */
2617         if (smp_processor_id() >= port->priv->nthreads)
2618                 return;
2619
2620         for (queue = 0; queue < port->ntxqs; queue++) {
2621                 int id = port->txqs[queue]->id;
2622
2623                 mvpp2_thread_read(port->priv,
2624                                   mvpp2_cpu_to_thread(port->priv, smp_processor_id()),
2625                                   MVPP2_TXQ_SENT_REG(id));
2626         }
2627 }
2628
2629 /* Set max sizes for Tx queues */
2630 static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port)
2631 {
2632         u32     val, size, mtu;
2633         int     txq, tx_port_num;
2634
2635         mtu = port->pkt_size * 8;
2636         if (mtu > MVPP2_TXP_MTU_MAX)
2637                 mtu = MVPP2_TXP_MTU_MAX;
2638
2639         /* WA for wrong Token bucket update: Set MTU value = 3*real MTU value */
2640         mtu = 3 * mtu;
2641
2642         /* Indirect access to registers */
2643         tx_port_num = mvpp2_egress_port(port);
2644         mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
2645
2646         /* Set MTU */
2647         val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG);
2648         val &= ~MVPP2_TXP_MTU_MAX;
2649         val |= mtu;
2650         mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val);
2651
2652         /* TXP token size and all TXQs token size must be larger that MTU */
2653         val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG);
2654         size = val & MVPP2_TXP_TOKEN_SIZE_MAX;
2655         if (size < mtu) {
2656                 size = mtu;
2657                 val &= ~MVPP2_TXP_TOKEN_SIZE_MAX;
2658                 val |= size;
2659                 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
2660         }
2661
2662         for (txq = 0; txq < port->ntxqs; txq++) {
2663                 val = mvpp2_read(port->priv,
2664                                  MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq));
2665                 size = val & MVPP2_TXQ_TOKEN_SIZE_MAX;
2666
2667                 if (size < mtu) {
2668                         size = mtu;
2669                         val &= ~MVPP2_TXQ_TOKEN_SIZE_MAX;
2670                         val |= size;
2671                         mvpp2_write(port->priv,
2672                                     MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq),
2673                                     val);
2674                 }
2675         }
2676 }
2677
2678 /* Set the number of non-occupied descriptors threshold */
2679 static void mvpp2_set_rxq_free_tresh(struct mvpp2_port *port,
2680                                      struct mvpp2_rx_queue *rxq)
2681 {
2682         u32 val;
2683
2684         mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
2685
2686         val = mvpp2_read(port->priv, MVPP2_RXQ_THRESH_REG);
2687         val &= ~MVPP2_RXQ_NON_OCCUPIED_MASK;
2688         val |= MSS_THRESHOLD_STOP << MVPP2_RXQ_NON_OCCUPIED_OFFSET;
2689         mvpp2_write(port->priv, MVPP2_RXQ_THRESH_REG, val);
2690 }
2691
2692 /* Set the number of packets that will be received before Rx interrupt
2693  * will be generated by HW.
2694  */
2695 static void mvpp2_rx_pkts_coal_set(struct mvpp2_port *port,
2696                                    struct mvpp2_rx_queue *rxq)
2697 {
2698         unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
2699
2700         if (rxq->pkts_coal > MVPP2_OCCUPIED_THRESH_MASK)
2701                 rxq->pkts_coal = MVPP2_OCCUPIED_THRESH_MASK;
2702
2703         mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id);
2704         mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_THRESH_REG,
2705                            rxq->pkts_coal);
2706
2707         put_cpu();
2708 }
2709
2710 /* For some reason in the LSP this is done on each CPU. Why ? */
2711 static void mvpp2_tx_pkts_coal_set(struct mvpp2_port *port,
2712                                    struct mvpp2_tx_queue *txq)
2713 {
2714         unsigned int thread;
2715         u32 val;
2716
2717         if (txq->done_pkts_coal > MVPP2_TXQ_THRESH_MASK)
2718                 txq->done_pkts_coal = MVPP2_TXQ_THRESH_MASK;
2719
2720         val = (txq->done_pkts_coal << MVPP2_TXQ_THRESH_OFFSET);
2721         /* PKT-coalescing registers are per-queue + per-thread */
2722         for (thread = 0; thread < MVPP2_MAX_THREADS; thread++) {
2723                 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id);
2724                 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_THRESH_REG, val);
2725         }
2726 }
2727
2728 static u32 mvpp2_usec_to_cycles(u32 usec, unsigned long clk_hz)
2729 {
2730         u64 tmp = (u64)clk_hz * usec;
2731
2732         do_div(tmp, USEC_PER_SEC);
2733
2734         return tmp > U32_MAX ? U32_MAX : tmp;
2735 }
2736
2737 static u32 mvpp2_cycles_to_usec(u32 cycles, unsigned long clk_hz)
2738 {
2739         u64 tmp = (u64)cycles * USEC_PER_SEC;
2740
2741         do_div(tmp, clk_hz);
2742
2743         return tmp > U32_MAX ? U32_MAX : tmp;
2744 }
2745
2746 /* Set the time delay in usec before Rx interrupt */
2747 static void mvpp2_rx_time_coal_set(struct mvpp2_port *port,
2748                                    struct mvpp2_rx_queue *rxq)
2749 {
2750         unsigned long freq = port->priv->tclk;
2751         u32 val = mvpp2_usec_to_cycles(rxq->time_coal, freq);
2752
2753         if (val > MVPP2_MAX_ISR_RX_THRESHOLD) {
2754                 rxq->time_coal =
2755                         mvpp2_cycles_to_usec(MVPP2_MAX_ISR_RX_THRESHOLD, freq);
2756
2757                 /* re-evaluate to get actual register value */
2758                 val = mvpp2_usec_to_cycles(rxq->time_coal, freq);
2759         }
2760
2761         mvpp2_write(port->priv, MVPP2_ISR_RX_THRESHOLD_REG(rxq->id), val);
2762 }
2763
2764 static void mvpp2_tx_time_coal_set(struct mvpp2_port *port)
2765 {
2766         unsigned long freq = port->priv->tclk;
2767         u32 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq);
2768
2769         if (val > MVPP2_MAX_ISR_TX_THRESHOLD) {
2770                 port->tx_time_coal =
2771                         mvpp2_cycles_to_usec(MVPP2_MAX_ISR_TX_THRESHOLD, freq);
2772
2773                 /* re-evaluate to get actual register value */
2774                 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq);
2775         }
2776
2777         mvpp2_write(port->priv, MVPP2_ISR_TX_THRESHOLD_REG(port->id), val);
2778 }
2779
2780 /* Free Tx queue skbuffs */
2781 static void mvpp2_txq_bufs_free(struct mvpp2_port *port,
2782                                 struct mvpp2_tx_queue *txq,
2783                                 struct mvpp2_txq_pcpu *txq_pcpu, int num)
2784 {
2785         struct xdp_frame_bulk bq;
2786         int i;
2787
2788         xdp_frame_bulk_init(&bq);
2789
2790         rcu_read_lock(); /* need for xdp_return_frame_bulk */
2791
2792         for (i = 0; i < num; i++) {
2793                 struct mvpp2_txq_pcpu_buf *tx_buf =
2794                         txq_pcpu->buffs + txq_pcpu->txq_get_index;
2795
2796                 if (!IS_TSO_HEADER(txq_pcpu, tx_buf->dma) &&
2797                     tx_buf->type != MVPP2_TYPE_XDP_TX)
2798                         dma_unmap_single(port->dev->dev.parent, tx_buf->dma,
2799                                          tx_buf->size, DMA_TO_DEVICE);
2800                 if (tx_buf->type == MVPP2_TYPE_SKB && tx_buf->skb)
2801                         dev_kfree_skb_any(tx_buf->skb);
2802                 else if (tx_buf->type == MVPP2_TYPE_XDP_TX ||
2803                          tx_buf->type == MVPP2_TYPE_XDP_NDO)
2804                         xdp_return_frame_bulk(tx_buf->xdpf, &bq);
2805
2806                 mvpp2_txq_inc_get(txq_pcpu);
2807         }
2808         xdp_flush_frame_bulk(&bq);
2809
2810         rcu_read_unlock();
2811 }
2812
2813 static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port,
2814                                                         u32 cause)
2815 {
2816         int queue = fls(cause) - 1;
2817
2818         return port->rxqs[queue];
2819 }
2820
2821 static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port,
2822                                                         u32 cause)
2823 {
2824         int queue = fls(cause) - 1;
2825
2826         return port->txqs[queue];
2827 }
2828
2829 /* Handle end of transmission */
2830 static void mvpp2_txq_done(struct mvpp2_port *port, struct mvpp2_tx_queue *txq,
2831                            struct mvpp2_txq_pcpu *txq_pcpu)
2832 {
2833         struct netdev_queue *nq = netdev_get_tx_queue(port->dev, txq->log_id);
2834         int tx_done;
2835
2836         if (txq_pcpu->thread != mvpp2_cpu_to_thread(port->priv, smp_processor_id()))
2837                 netdev_err(port->dev, "wrong cpu on the end of Tx processing\n");
2838
2839         tx_done = mvpp2_txq_sent_desc_proc(port, txq);
2840         if (!tx_done)
2841                 return;
2842         mvpp2_txq_bufs_free(port, txq, txq_pcpu, tx_done);
2843
2844         txq_pcpu->count -= tx_done;
2845
2846         if (netif_tx_queue_stopped(nq))
2847                 if (txq_pcpu->count <= txq_pcpu->wake_threshold)
2848                         netif_tx_wake_queue(nq);
2849 }
2850
2851 static unsigned int mvpp2_tx_done(struct mvpp2_port *port, u32 cause,
2852                                   unsigned int thread)
2853 {
2854         struct mvpp2_tx_queue *txq;
2855         struct mvpp2_txq_pcpu *txq_pcpu;
2856         unsigned int tx_todo = 0;
2857
2858         while (cause) {
2859                 txq = mvpp2_get_tx_queue(port, cause);
2860                 if (!txq)
2861                         break;
2862
2863                 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
2864
2865                 if (txq_pcpu->count) {
2866                         mvpp2_txq_done(port, txq, txq_pcpu);
2867                         tx_todo += txq_pcpu->count;
2868                 }
2869
2870                 cause &= ~(1 << txq->log_id);
2871         }
2872         return tx_todo;
2873 }
2874
2875 /* Rx/Tx queue initialization/cleanup methods */
2876
2877 /* Allocate and initialize descriptors for aggr TXQ */
2878 static int mvpp2_aggr_txq_init(struct platform_device *pdev,
2879                                struct mvpp2_tx_queue *aggr_txq,
2880                                unsigned int thread, struct mvpp2 *priv)
2881 {
2882         u32 txq_dma;
2883
2884         /* Allocate memory for TX descriptors */
2885         aggr_txq->descs = dma_alloc_coherent(&pdev->dev,
2886                                              MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE,
2887                                              &aggr_txq->descs_dma, GFP_KERNEL);
2888         if (!aggr_txq->descs)
2889                 return -ENOMEM;
2890
2891         aggr_txq->last_desc = MVPP2_AGGR_TXQ_SIZE - 1;
2892
2893         /* Aggr TXQ no reset WA */
2894         aggr_txq->next_desc_to_proc = mvpp2_read(priv,
2895                                                  MVPP2_AGGR_TXQ_INDEX_REG(thread));
2896
2897         /* Set Tx descriptors queue starting address indirect
2898          * access
2899          */
2900         if (priv->hw_version == MVPP21)
2901                 txq_dma = aggr_txq->descs_dma;
2902         else
2903                 txq_dma = aggr_txq->descs_dma >>
2904                         MVPP22_AGGR_TXQ_DESC_ADDR_OFFS;
2905
2906         mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(thread), txq_dma);
2907         mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(thread),
2908                     MVPP2_AGGR_TXQ_SIZE);
2909
2910         return 0;
2911 }
2912
2913 /* Create a specified Rx queue */
2914 static int mvpp2_rxq_init(struct mvpp2_port *port,
2915                           struct mvpp2_rx_queue *rxq)
2916 {
2917         struct mvpp2 *priv = port->priv;
2918         unsigned int thread;
2919         u32 rxq_dma;
2920         int err;
2921
2922         rxq->size = port->rx_ring_size;
2923
2924         /* Allocate memory for RX descriptors */
2925         rxq->descs = dma_alloc_coherent(port->dev->dev.parent,
2926                                         rxq->size * MVPP2_DESC_ALIGNED_SIZE,
2927                                         &rxq->descs_dma, GFP_KERNEL);
2928         if (!rxq->descs)
2929                 return -ENOMEM;
2930
2931         rxq->last_desc = rxq->size - 1;
2932
2933         /* Zero occupied and non-occupied counters - direct access */
2934         mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
2935
2936         /* Set Rx descriptors queue starting address - indirect access */
2937         thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
2938         mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id);
2939         if (port->priv->hw_version == MVPP21)
2940                 rxq_dma = rxq->descs_dma;
2941         else
2942                 rxq_dma = rxq->descs_dma >> MVPP22_DESC_ADDR_OFFS;
2943         mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma);
2944         mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_SIZE_REG, rxq->size);
2945         mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_INDEX_REG, 0);
2946         put_cpu();
2947
2948         /* Set Offset */
2949         mvpp2_rxq_offset_set(port, rxq->id, MVPP2_SKB_HEADROOM);
2950
2951         /* Set coalescing pkts and time */
2952         mvpp2_rx_pkts_coal_set(port, rxq);
2953         mvpp2_rx_time_coal_set(port, rxq);
2954
2955         /* Set the number of non occupied descriptors threshold */
2956         mvpp2_set_rxq_free_tresh(port, rxq);
2957
2958         /* Add number of descriptors ready for receiving packets */
2959         mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size);
2960
2961         if (priv->percpu_pools) {
2962                 err = xdp_rxq_info_reg(&rxq->xdp_rxq_short, port->dev, rxq->id, 0);
2963                 if (err < 0)
2964                         goto err_free_dma;
2965
2966                 err = xdp_rxq_info_reg(&rxq->xdp_rxq_long, port->dev, rxq->id, 0);
2967                 if (err < 0)
2968                         goto err_unregister_rxq_short;
2969
2970                 /* Every RXQ has a pool for short and another for long packets */
2971                 err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq_short,
2972                                                  MEM_TYPE_PAGE_POOL,
2973                                                  priv->page_pool[rxq->logic_rxq]);
2974                 if (err < 0)
2975                         goto err_unregister_rxq_long;
2976
2977                 err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq_long,
2978                                                  MEM_TYPE_PAGE_POOL,
2979                                                  priv->page_pool[rxq->logic_rxq +
2980                                                                  port->nrxqs]);
2981                 if (err < 0)
2982                         goto err_unregister_mem_rxq_short;
2983         }
2984
2985         return 0;
2986
2987 err_unregister_mem_rxq_short:
2988         xdp_rxq_info_unreg_mem_model(&rxq->xdp_rxq_short);
2989 err_unregister_rxq_long:
2990         xdp_rxq_info_unreg(&rxq->xdp_rxq_long);
2991 err_unregister_rxq_short:
2992         xdp_rxq_info_unreg(&rxq->xdp_rxq_short);
2993 err_free_dma:
2994         dma_free_coherent(port->dev->dev.parent,
2995                           rxq->size * MVPP2_DESC_ALIGNED_SIZE,
2996                           rxq->descs, rxq->descs_dma);
2997         return err;
2998 }
2999
3000 /* Push packets received by the RXQ to BM pool */
3001 static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port,
3002                                 struct mvpp2_rx_queue *rxq)
3003 {
3004         int rx_received, i;
3005
3006         rx_received = mvpp2_rxq_received(port, rxq->id);
3007         if (!rx_received)
3008                 return;
3009
3010         for (i = 0; i < rx_received; i++) {
3011                 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
3012                 u32 status = mvpp2_rxdesc_status_get(port, rx_desc);
3013                 int pool;
3014
3015                 pool = (status & MVPP2_RXD_BM_POOL_ID_MASK) >>
3016                         MVPP2_RXD_BM_POOL_ID_OFFS;
3017
3018                 mvpp2_bm_pool_put(port, pool,
3019                                   mvpp2_rxdesc_dma_addr_get(port, rx_desc),
3020                                   mvpp2_rxdesc_cookie_get(port, rx_desc));
3021         }
3022         mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received);
3023 }
3024
3025 /* Cleanup Rx queue */
3026 static void mvpp2_rxq_deinit(struct mvpp2_port *port,
3027                              struct mvpp2_rx_queue *rxq)
3028 {
3029         unsigned int thread;
3030
3031         if (xdp_rxq_info_is_reg(&rxq->xdp_rxq_short))
3032                 xdp_rxq_info_unreg(&rxq->xdp_rxq_short);
3033
3034         if (xdp_rxq_info_is_reg(&rxq->xdp_rxq_long))
3035                 xdp_rxq_info_unreg(&rxq->xdp_rxq_long);
3036
3037         mvpp2_rxq_drop_pkts(port, rxq);
3038
3039         if (rxq->descs)
3040                 dma_free_coherent(port->dev->dev.parent,
3041                                   rxq->size * MVPP2_DESC_ALIGNED_SIZE,
3042                                   rxq->descs,
3043                                   rxq->descs_dma);
3044
3045         rxq->descs             = NULL;
3046         rxq->last_desc         = 0;
3047         rxq->next_desc_to_proc = 0;
3048         rxq->descs_dma         = 0;
3049
3050         /* Clear Rx descriptors queue starting address and size;
3051          * free descriptor number
3052          */
3053         mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
3054         thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
3055         mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id);
3056         mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_ADDR_REG, 0);
3057         mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_SIZE_REG, 0);
3058         put_cpu();
3059 }
3060
3061 /* Create and initialize a Tx queue */
3062 static int mvpp2_txq_init(struct mvpp2_port *port,
3063                           struct mvpp2_tx_queue *txq)
3064 {
3065         u32 val;
3066         unsigned int thread;
3067         int desc, desc_per_txq, tx_port_num;
3068         struct mvpp2_txq_pcpu *txq_pcpu;
3069
3070         txq->size = port->tx_ring_size;
3071
3072         /* Allocate memory for Tx descriptors */
3073         txq->descs = dma_alloc_coherent(port->dev->dev.parent,
3074                                 txq->size * MVPP2_DESC_ALIGNED_SIZE,
3075                                 &txq->descs_dma, GFP_KERNEL);
3076         if (!txq->descs)
3077                 return -ENOMEM;
3078
3079         txq->last_desc = txq->size - 1;
3080
3081         /* Set Tx descriptors queue starting address - indirect access */
3082         thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
3083         mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id);
3084         mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_ADDR_REG,
3085                            txq->descs_dma);
3086         mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_SIZE_REG,
3087                            txq->size & MVPP2_TXQ_DESC_SIZE_MASK);
3088         mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_INDEX_REG, 0);
3089         mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_RSVD_CLR_REG,
3090                            txq->id << MVPP2_TXQ_RSVD_CLR_OFFSET);
3091         val = mvpp2_thread_read(port->priv, thread, MVPP2_TXQ_PENDING_REG);
3092         val &= ~MVPP2_TXQ_PENDING_MASK;
3093         mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PENDING_REG, val);
3094
3095         /* Calculate base address in prefetch buffer. We reserve 16 descriptors
3096          * for each existing TXQ.
3097          * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT
3098          * GBE ports assumed to be continuous from 0 to MVPP2_MAX_PORTS
3099          */
3100         desc_per_txq = 16;
3101         desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) +
3102                (txq->log_id * desc_per_txq);
3103
3104         mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG,
3105                            MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 |
3106                            MVPP2_PREF_BUF_THRESH(desc_per_txq / 2));
3107         put_cpu();
3108
3109         /* WRR / EJP configuration - indirect access */
3110         tx_port_num = mvpp2_egress_port(port);
3111         mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
3112
3113         val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id));
3114         val &= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK;
3115         val |= MVPP2_TXQ_REFILL_PERIOD_MASK(1);
3116         val |= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK;
3117         mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val);
3118
3119         val = MVPP2_TXQ_TOKEN_SIZE_MAX;
3120         mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id),
3121                     val);
3122
3123         for (thread = 0; thread < port->priv->nthreads; thread++) {
3124                 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
3125                 txq_pcpu->size = txq->size;
3126                 txq_pcpu->buffs = kmalloc_array(txq_pcpu->size,
3127                                                 sizeof(*txq_pcpu->buffs),
3128                                                 GFP_KERNEL);
3129                 if (!txq_pcpu->buffs)
3130                         return -ENOMEM;
3131
3132                 txq_pcpu->count = 0;
3133                 txq_pcpu->reserved_num = 0;
3134                 txq_pcpu->txq_put_index = 0;
3135                 txq_pcpu->txq_get_index = 0;
3136                 txq_pcpu->tso_headers = NULL;
3137
3138                 txq_pcpu->stop_threshold = txq->size - MVPP2_MAX_SKB_DESCS;
3139                 txq_pcpu->wake_threshold = txq_pcpu->stop_threshold / 2;
3140
3141                 txq_pcpu->tso_headers =
3142                         dma_alloc_coherent(port->dev->dev.parent,
3143                                            txq_pcpu->size * TSO_HEADER_SIZE,
3144                                            &txq_pcpu->tso_headers_dma,
3145                                            GFP_KERNEL);
3146                 if (!txq_pcpu->tso_headers)
3147                         return -ENOMEM;
3148         }
3149
3150         return 0;
3151 }
3152
3153 /* Free allocated TXQ resources */
3154 static void mvpp2_txq_deinit(struct mvpp2_port *port,
3155                              struct mvpp2_tx_queue *txq)
3156 {
3157         struct mvpp2_txq_pcpu *txq_pcpu;
3158         unsigned int thread;
3159
3160         for (thread = 0; thread < port->priv->nthreads; thread++) {
3161                 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
3162                 kfree(txq_pcpu->buffs);
3163
3164                 if (txq_pcpu->tso_headers)
3165                         dma_free_coherent(port->dev->dev.parent,
3166                                           txq_pcpu->size * TSO_HEADER_SIZE,
3167                                           txq_pcpu->tso_headers,
3168                                           txq_pcpu->tso_headers_dma);
3169
3170                 txq_pcpu->tso_headers = NULL;
3171         }
3172
3173         if (txq->descs)
3174                 dma_free_coherent(port->dev->dev.parent,
3175                                   txq->size * MVPP2_DESC_ALIGNED_SIZE,
3176                                   txq->descs, txq->descs_dma);
3177
3178         txq->descs             = NULL;
3179         txq->last_desc         = 0;
3180         txq->next_desc_to_proc = 0;
3181         txq->descs_dma         = 0;
3182
3183         /* Set minimum bandwidth for disabled TXQs */
3184         mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->log_id), 0);
3185
3186         /* Set Tx descriptors queue starting address and size */
3187         thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
3188         mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id);
3189         mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_ADDR_REG, 0);
3190         mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_SIZE_REG, 0);
3191         put_cpu();
3192 }
3193
3194 /* Cleanup Tx ports */
3195 static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq)
3196 {
3197         struct mvpp2_txq_pcpu *txq_pcpu;
3198         int delay, pending;
3199         unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
3200         u32 val;
3201
3202         mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id);
3203         val = mvpp2_thread_read(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG);
3204         val |= MVPP2_TXQ_DRAIN_EN_MASK;
3205         mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, val);
3206
3207         /* The napi queue has been stopped so wait for all packets
3208          * to be transmitted.
3209          */
3210         delay = 0;
3211         do {
3212                 if (delay >= MVPP2_TX_PENDING_TIMEOUT_MSEC) {
3213                         netdev_warn(port->dev,
3214                                     "port %d: cleaning queue %d timed out\n",
3215                                     port->id, txq->log_id);
3216                         break;
3217                 }
3218                 mdelay(1);
3219                 delay++;
3220
3221                 pending = mvpp2_thread_read(port->priv, thread,
3222                                             MVPP2_TXQ_PENDING_REG);
3223                 pending &= MVPP2_TXQ_PENDING_MASK;
3224         } while (pending);
3225
3226         val &= ~MVPP2_TXQ_DRAIN_EN_MASK;
3227         mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, val);
3228         put_cpu();
3229
3230         for (thread = 0; thread < port->priv->nthreads; thread++) {
3231                 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
3232
3233                 /* Release all packets */
3234                 mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count);
3235
3236                 /* Reset queue */
3237                 txq_pcpu->count = 0;
3238                 txq_pcpu->txq_put_index = 0;
3239                 txq_pcpu->txq_get_index = 0;
3240         }
3241 }
3242
3243 /* Cleanup all Tx queues */
3244 static void mvpp2_cleanup_txqs(struct mvpp2_port *port)
3245 {
3246         struct mvpp2_tx_queue *txq;
3247         int queue;
3248         u32 val;
3249
3250         val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG);
3251
3252         /* Reset Tx ports and delete Tx queues */
3253         val |= MVPP2_TX_PORT_FLUSH_MASK(port->id);
3254         mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
3255
3256         for (queue = 0; queue < port->ntxqs; queue++) {
3257                 txq = port->txqs[queue];
3258                 mvpp2_txq_clean(port, txq);
3259                 mvpp2_txq_deinit(port, txq);
3260         }
3261
3262         on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1);
3263
3264         val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id);
3265         mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
3266 }
3267
3268 /* Cleanup all Rx queues */
3269 static void mvpp2_cleanup_rxqs(struct mvpp2_port *port)
3270 {
3271         int queue;
3272
3273         for (queue = 0; queue < port->nrxqs; queue++)
3274                 mvpp2_rxq_deinit(port, port->rxqs[queue]);
3275
3276         if (port->tx_fc)
3277                 mvpp2_rxq_disable_fc(port);
3278 }
3279
3280 /* Init all Rx queues for port */
3281 static int mvpp2_setup_rxqs(struct mvpp2_port *port)
3282 {
3283         int queue, err;
3284
3285         for (queue = 0; queue < port->nrxqs; queue++) {
3286                 err = mvpp2_rxq_init(port, port->rxqs[queue]);
3287                 if (err)
3288                         goto err_cleanup;
3289         }
3290
3291         if (port->tx_fc)
3292                 mvpp2_rxq_enable_fc(port);
3293
3294         return 0;
3295
3296 err_cleanup:
3297         mvpp2_cleanup_rxqs(port);
3298         return err;
3299 }
3300
3301 /* Init all tx queues for port */
3302 static int mvpp2_setup_txqs(struct mvpp2_port *port)
3303 {
3304         struct mvpp2_tx_queue *txq;
3305         int queue, err;
3306
3307         for (queue = 0; queue < port->ntxqs; queue++) {
3308                 txq = port->txqs[queue];
3309                 err = mvpp2_txq_init(port, txq);
3310                 if (err)
3311                         goto err_cleanup;
3312
3313                 /* Assign this queue to a CPU */
3314                 if (queue < num_possible_cpus())
3315                         netif_set_xps_queue(port->dev, cpumask_of(queue), queue);
3316         }
3317
3318         if (port->has_tx_irqs) {
3319                 mvpp2_tx_time_coal_set(port);
3320                 for (queue = 0; queue < port->ntxqs; queue++) {
3321                         txq = port->txqs[queue];
3322                         mvpp2_tx_pkts_coal_set(port, txq);
3323                 }
3324         }
3325
3326         on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1);
3327         return 0;
3328
3329 err_cleanup:
3330         mvpp2_cleanup_txqs(port);
3331         return err;
3332 }
3333
3334 /* The callback for per-port interrupt */
3335 static irqreturn_t mvpp2_isr(int irq, void *dev_id)
3336 {
3337         struct mvpp2_queue_vector *qv = dev_id;
3338
3339         mvpp2_qvec_interrupt_disable(qv);
3340
3341         napi_schedule(&qv->napi);
3342
3343         return IRQ_HANDLED;
3344 }
3345
3346 static void mvpp2_isr_handle_ptp_queue(struct mvpp2_port *port, int nq)
3347 {
3348         struct skb_shared_hwtstamps shhwtstamps;
3349         struct mvpp2_hwtstamp_queue *queue;
3350         struct sk_buff *skb;
3351         void __iomem *ptp_q;
3352         unsigned int id;
3353         u32 r0, r1, r2;
3354
3355         ptp_q = port->priv->iface_base + MVPP22_PTP_BASE(port->gop_id);
3356         if (nq)
3357                 ptp_q += MVPP22_PTP_TX_Q1_R0 - MVPP22_PTP_TX_Q0_R0;
3358
3359         queue = &port->tx_hwtstamp_queue[nq];
3360
3361         while (1) {
3362                 r0 = readl_relaxed(ptp_q + MVPP22_PTP_TX_Q0_R0) & 0xffff;
3363                 if (!r0)
3364                         break;
3365
3366                 r1 = readl_relaxed(ptp_q + MVPP22_PTP_TX_Q0_R1) & 0xffff;
3367                 r2 = readl_relaxed(ptp_q + MVPP22_PTP_TX_Q0_R2) & 0xffff;
3368
3369                 id = (r0 >> 1) & 31;
3370
3371                 skb = queue->skb[id];
3372                 queue->skb[id] = NULL;
3373                 if (skb) {
3374                         u32 ts = r2 << 19 | r1 << 3 | r0 >> 13;
3375
3376                         mvpp22_tai_tstamp(port->priv->tai, ts, &shhwtstamps);
3377                         skb_tstamp_tx(skb, &shhwtstamps);
3378                         dev_kfree_skb_any(skb);
3379                 }
3380         }
3381 }
3382
3383 static void mvpp2_isr_handle_ptp(struct mvpp2_port *port)
3384 {
3385         void __iomem *ptp;
3386         u32 val;
3387
3388         ptp = port->priv->iface_base + MVPP22_PTP_BASE(port->gop_id);
3389         val = readl(ptp + MVPP22_PTP_INT_CAUSE);
3390         if (val & MVPP22_PTP_INT_CAUSE_QUEUE0)
3391                 mvpp2_isr_handle_ptp_queue(port, 0);
3392         if (val & MVPP22_PTP_INT_CAUSE_QUEUE1)
3393                 mvpp2_isr_handle_ptp_queue(port, 1);
3394 }
3395
3396 static void mvpp2_isr_handle_link(struct mvpp2_port *port, bool link)
3397 {
3398         struct net_device *dev = port->dev;
3399
3400         if (port->phylink) {
3401                 phylink_mac_change(port->phylink, link);
3402                 return;
3403         }
3404
3405         if (!netif_running(dev))
3406                 return;
3407
3408         if (link) {
3409                 mvpp2_interrupts_enable(port);
3410
3411                 mvpp2_egress_enable(port);
3412                 mvpp2_ingress_enable(port);
3413                 netif_carrier_on(dev);
3414                 netif_tx_wake_all_queues(dev);
3415         } else {
3416                 netif_tx_stop_all_queues(dev);
3417                 netif_carrier_off(dev);
3418                 mvpp2_ingress_disable(port);
3419                 mvpp2_egress_disable(port);
3420
3421                 mvpp2_interrupts_disable(port);
3422         }
3423 }
3424
3425 static void mvpp2_isr_handle_xlg(struct mvpp2_port *port)
3426 {
3427         bool link;
3428         u32 val;
3429
3430         val = readl(port->base + MVPP22_XLG_INT_STAT);
3431         if (val & MVPP22_XLG_INT_STAT_LINK) {
3432                 val = readl(port->base + MVPP22_XLG_STATUS);
3433                 link = (val & MVPP22_XLG_STATUS_LINK_UP);
3434                 mvpp2_isr_handle_link(port, link);
3435         }
3436 }
3437
3438 static void mvpp2_isr_handle_gmac_internal(struct mvpp2_port *port)
3439 {
3440         bool link;
3441         u32 val;
3442
3443         if (phy_interface_mode_is_rgmii(port->phy_interface) ||
3444             phy_interface_mode_is_8023z(port->phy_interface) ||
3445             port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
3446                 val = readl(port->base + MVPP22_GMAC_INT_STAT);
3447                 if (val & MVPP22_GMAC_INT_STAT_LINK) {
3448                         val = readl(port->base + MVPP2_GMAC_STATUS0);
3449                         link = (val & MVPP2_GMAC_STATUS0_LINK_UP);
3450                         mvpp2_isr_handle_link(port, link);
3451                 }
3452         }
3453 }
3454
3455 /* Per-port interrupt for link status changes */
3456 static irqreturn_t mvpp2_port_isr(int irq, void *dev_id)
3457 {
3458         struct mvpp2_port *port = (struct mvpp2_port *)dev_id;
3459         u32 val;
3460
3461         mvpp22_gop_mask_irq(port);
3462
3463         if (mvpp2_port_supports_xlg(port) &&
3464             mvpp2_is_xlg(port->phy_interface)) {
3465                 /* Check the external status register */
3466                 val = readl(port->base + MVPP22_XLG_EXT_INT_STAT);
3467                 if (val & MVPP22_XLG_EXT_INT_STAT_XLG)
3468                         mvpp2_isr_handle_xlg(port);
3469                 if (val & MVPP22_XLG_EXT_INT_STAT_PTP)
3470                         mvpp2_isr_handle_ptp(port);
3471         } else {
3472                 /* If it's not the XLG, we must be using the GMAC.
3473                  * Check the summary status.
3474                  */
3475                 val = readl(port->base + MVPP22_GMAC_INT_SUM_STAT);
3476                 if (val & MVPP22_GMAC_INT_SUM_STAT_INTERNAL)
3477                         mvpp2_isr_handle_gmac_internal(port);
3478                 if (val & MVPP22_GMAC_INT_SUM_STAT_PTP)
3479                         mvpp2_isr_handle_ptp(port);
3480         }
3481
3482         mvpp22_gop_unmask_irq(port);
3483         return IRQ_HANDLED;
3484 }
3485
3486 static enum hrtimer_restart mvpp2_hr_timer_cb(struct hrtimer *timer)
3487 {
3488         struct net_device *dev;
3489         struct mvpp2_port *port;
3490         struct mvpp2_port_pcpu *port_pcpu;
3491         unsigned int tx_todo, cause;
3492
3493         port_pcpu = container_of(timer, struct mvpp2_port_pcpu, tx_done_timer);
3494         dev = port_pcpu->dev;
3495
3496         if (!netif_running(dev))
3497                 return HRTIMER_NORESTART;
3498
3499         port_pcpu->timer_scheduled = false;
3500         port = netdev_priv(dev);
3501
3502         /* Process all the Tx queues */
3503         cause = (1 << port->ntxqs) - 1;
3504         tx_todo = mvpp2_tx_done(port, cause,
3505                                 mvpp2_cpu_to_thread(port->priv, smp_processor_id()));
3506
3507         /* Set the timer in case not all the packets were processed */
3508         if (tx_todo && !port_pcpu->timer_scheduled) {
3509                 port_pcpu->timer_scheduled = true;
3510                 hrtimer_forward_now(&port_pcpu->tx_done_timer,
3511                                     MVPP2_TXDONE_HRTIMER_PERIOD_NS);
3512
3513                 return HRTIMER_RESTART;
3514         }
3515         return HRTIMER_NORESTART;
3516 }
3517
3518 /* Main RX/TX processing routines */
3519
3520 /* Display more error info */
3521 static void mvpp2_rx_error(struct mvpp2_port *port,
3522                            struct mvpp2_rx_desc *rx_desc)
3523 {
3524         u32 status = mvpp2_rxdesc_status_get(port, rx_desc);
3525         size_t sz = mvpp2_rxdesc_size_get(port, rx_desc);
3526         char *err_str = NULL;
3527
3528         switch (status & MVPP2_RXD_ERR_CODE_MASK) {
3529         case MVPP2_RXD_ERR_CRC:
3530                 err_str = "crc";
3531                 break;
3532         case MVPP2_RXD_ERR_OVERRUN:
3533                 err_str = "overrun";
3534                 break;
3535         case MVPP2_RXD_ERR_RESOURCE:
3536                 err_str = "resource";
3537                 break;
3538         }
3539         if (err_str && net_ratelimit())
3540                 netdev_err(port->dev,
3541                            "bad rx status %08x (%s error), size=%zu\n",
3542                            status, err_str, sz);
3543 }
3544
3545 /* Handle RX checksum offload */
3546 static void mvpp2_rx_csum(struct mvpp2_port *port, u32 status,
3547                           struct sk_buff *skb)
3548 {
3549         if (((status & MVPP2_RXD_L3_IP4) &&
3550              !(status & MVPP2_RXD_IP4_HEADER_ERR)) ||
3551             (status & MVPP2_RXD_L3_IP6))
3552                 if (((status & MVPP2_RXD_L4_UDP) ||
3553                      (status & MVPP2_RXD_L4_TCP)) &&
3554                      (status & MVPP2_RXD_L4_CSUM_OK)) {
3555                         skb->csum = 0;
3556                         skb->ip_summed = CHECKSUM_UNNECESSARY;
3557                         return;
3558                 }
3559
3560         skb->ip_summed = CHECKSUM_NONE;
3561 }
3562
3563 /* Allocate a new skb and add it to BM pool */
3564 static int mvpp2_rx_refill(struct mvpp2_port *port,
3565                            struct mvpp2_bm_pool *bm_pool,
3566                            struct page_pool *page_pool, int pool)
3567 {
3568         dma_addr_t dma_addr;
3569         phys_addr_t phys_addr;
3570         void *buf;
3571
3572         buf = mvpp2_buf_alloc(port, bm_pool, page_pool,
3573                               &dma_addr, &phys_addr, GFP_ATOMIC);
3574         if (!buf)
3575                 return -ENOMEM;
3576
3577         mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr);
3578
3579         return 0;
3580 }
3581
3582 /* Handle tx checksum */
3583 static u32 mvpp2_skb_tx_csum(struct mvpp2_port *port, struct sk_buff *skb)
3584 {
3585         if (skb->ip_summed == CHECKSUM_PARTIAL) {
3586                 int ip_hdr_len = 0;
3587                 u8 l4_proto;
3588                 __be16 l3_proto = vlan_get_protocol(skb);
3589
3590                 if (l3_proto == htons(ETH_P_IP)) {
3591                         struct iphdr *ip4h = ip_hdr(skb);
3592
3593                         /* Calculate IPv4 checksum and L4 checksum */
3594                         ip_hdr_len = ip4h->ihl;
3595                         l4_proto = ip4h->protocol;
3596                 } else if (l3_proto == htons(ETH_P_IPV6)) {
3597                         struct ipv6hdr *ip6h = ipv6_hdr(skb);
3598
3599                         /* Read l4_protocol from one of IPv6 extra headers */
3600                         if (skb_network_header_len(skb) > 0)
3601                                 ip_hdr_len = (skb_network_header_len(skb) >> 2);
3602                         l4_proto = ip6h->nexthdr;
3603                 } else {
3604                         return MVPP2_TXD_L4_CSUM_NOT;
3605                 }
3606
3607                 return mvpp2_txq_desc_csum(skb_network_offset(skb),
3608                                            l3_proto, ip_hdr_len, l4_proto);
3609         }
3610
3611         return MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE;
3612 }
3613
3614 static void mvpp2_xdp_finish_tx(struct mvpp2_port *port, u16 txq_id, int nxmit, int nxmit_byte)
3615 {
3616         unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
3617         struct mvpp2_tx_queue *aggr_txq;
3618         struct mvpp2_txq_pcpu *txq_pcpu;
3619         struct mvpp2_tx_queue *txq;
3620         struct netdev_queue *nq;
3621
3622         txq = port->txqs[txq_id];
3623         txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
3624         nq = netdev_get_tx_queue(port->dev, txq_id);
3625         aggr_txq = &port->priv->aggr_txqs[thread];
3626
3627         txq_pcpu->reserved_num -= nxmit;
3628         txq_pcpu->count += nxmit;
3629         aggr_txq->count += nxmit;
3630
3631         /* Enable transmit */
3632         wmb();
3633         mvpp2_aggr_txq_pend_desc_add(port, nxmit);
3634
3635         if (txq_pcpu->count >= txq_pcpu->stop_threshold)
3636                 netif_tx_stop_queue(nq);
3637
3638         /* Finalize TX processing */
3639         if (!port->has_tx_irqs && txq_pcpu->count >= txq->done_pkts_coal)
3640                 mvpp2_txq_done(port, txq, txq_pcpu);
3641 }
3642
3643 static int
3644 mvpp2_xdp_submit_frame(struct mvpp2_port *port, u16 txq_id,
3645                        struct xdp_frame *xdpf, bool dma_map)
3646 {
3647         unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
3648         u32 tx_cmd = MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE |
3649                      MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC;
3650         enum mvpp2_tx_buf_type buf_type;
3651         struct mvpp2_txq_pcpu *txq_pcpu;
3652         struct mvpp2_tx_queue *aggr_txq;
3653         struct mvpp2_tx_desc *tx_desc;
3654         struct mvpp2_tx_queue *txq;
3655         int ret = MVPP2_XDP_TX;
3656         dma_addr_t dma_addr;
3657
3658         txq = port->txqs[txq_id];
3659         txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
3660         aggr_txq = &port->priv->aggr_txqs[thread];
3661
3662         /* Check number of available descriptors */
3663         if (mvpp2_aggr_desc_num_check(port, aggr_txq, 1) ||
3664             mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu, 1)) {
3665                 ret = MVPP2_XDP_DROPPED;
3666                 goto out;
3667         }
3668
3669         /* Get a descriptor for the first part of the packet */
3670         tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
3671         mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
3672         mvpp2_txdesc_size_set(port, tx_desc, xdpf->len);
3673
3674         if (dma_map) {
3675                 /* XDP_REDIRECT or AF_XDP */
3676                 dma_addr = dma_map_single(port->dev->dev.parent, xdpf->data,
3677                                           xdpf->len, DMA_TO_DEVICE);
3678
3679                 if (unlikely(dma_mapping_error(port->dev->dev.parent, dma_addr))) {
3680                         mvpp2_txq_desc_put(txq);
3681                         ret = MVPP2_XDP_DROPPED;
3682                         goto out;
3683                 }
3684
3685                 buf_type = MVPP2_TYPE_XDP_NDO;
3686         } else {
3687                 /* XDP_TX */
3688                 struct page *page = virt_to_page(xdpf->data);
3689
3690                 dma_addr = page_pool_get_dma_addr(page) +
3691                            sizeof(*xdpf) + xdpf->headroom;
3692                 dma_sync_single_for_device(port->dev->dev.parent, dma_addr,
3693                                            xdpf->len, DMA_BIDIRECTIONAL);
3694
3695                 buf_type = MVPP2_TYPE_XDP_TX;
3696         }
3697
3698         mvpp2_txdesc_dma_addr_set(port, tx_desc, dma_addr);
3699
3700         mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd);
3701         mvpp2_txq_inc_put(port, txq_pcpu, xdpf, tx_desc, buf_type);
3702
3703 out:
3704         return ret;
3705 }
3706
3707 static int
3708 mvpp2_xdp_xmit_back(struct mvpp2_port *port, struct xdp_buff *xdp)
3709 {
3710         struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats);
3711         struct xdp_frame *xdpf;
3712         u16 txq_id;
3713         int ret;
3714
3715         xdpf = xdp_convert_buff_to_frame(xdp);
3716         if (unlikely(!xdpf))
3717                 return MVPP2_XDP_DROPPED;
3718
3719         /* The first of the TX queues are used for XPS,
3720          * the second half for XDP_TX
3721          */
3722         txq_id = mvpp2_cpu_to_thread(port->priv, smp_processor_id()) + (port->ntxqs / 2);
3723
3724         ret = mvpp2_xdp_submit_frame(port, txq_id, xdpf, false);
3725         if (ret == MVPP2_XDP_TX) {
3726                 u64_stats_update_begin(&stats->syncp);
3727                 stats->tx_bytes += xdpf->len;
3728                 stats->tx_packets++;
3729                 stats->xdp_tx++;
3730                 u64_stats_update_end(&stats->syncp);
3731
3732                 mvpp2_xdp_finish_tx(port, txq_id, 1, xdpf->len);
3733         } else {
3734                 u64_stats_update_begin(&stats->syncp);
3735                 stats->xdp_tx_err++;
3736                 u64_stats_update_end(&stats->syncp);
3737         }
3738
3739         return ret;
3740 }
3741
3742 static int
3743 mvpp2_xdp_xmit(struct net_device *dev, int num_frame,
3744                struct xdp_frame **frames, u32 flags)
3745 {
3746         struct mvpp2_port *port = netdev_priv(dev);
3747         int i, nxmit_byte = 0, nxmit = 0;
3748         struct mvpp2_pcpu_stats *stats;
3749         u16 txq_id;
3750         u32 ret;
3751
3752         if (unlikely(test_bit(0, &port->state)))
3753                 return -ENETDOWN;
3754
3755         if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
3756                 return -EINVAL;
3757
3758         /* The first of the TX queues are used for XPS,
3759          * the second half for XDP_TX
3760          */
3761         txq_id = mvpp2_cpu_to_thread(port->priv, smp_processor_id()) + (port->ntxqs / 2);
3762
3763         for (i = 0; i < num_frame; i++) {
3764                 ret = mvpp2_xdp_submit_frame(port, txq_id, frames[i], true);
3765                 if (ret != MVPP2_XDP_TX)
3766                         break;
3767
3768                 nxmit_byte += frames[i]->len;
3769                 nxmit++;
3770         }
3771
3772         if (likely(nxmit > 0))
3773                 mvpp2_xdp_finish_tx(port, txq_id, nxmit, nxmit_byte);
3774
3775         stats = this_cpu_ptr(port->stats);
3776         u64_stats_update_begin(&stats->syncp);
3777         stats->tx_bytes += nxmit_byte;
3778         stats->tx_packets += nxmit;
3779         stats->xdp_xmit += nxmit;
3780         stats->xdp_xmit_err += num_frame - nxmit;
3781         u64_stats_update_end(&stats->syncp);
3782
3783         return nxmit;
3784 }
3785
3786 static int
3787 mvpp2_run_xdp(struct mvpp2_port *port, struct mvpp2_rx_queue *rxq,
3788               struct bpf_prog *prog, struct xdp_buff *xdp,
3789               struct page_pool *pp, struct mvpp2_pcpu_stats *stats)
3790 {
3791         unsigned int len, sync, err;
3792         struct page *page;
3793         u32 ret, act;
3794
3795         len = xdp->data_end - xdp->data_hard_start - MVPP2_SKB_HEADROOM;
3796         act = bpf_prog_run_xdp(prog, xdp);
3797
3798         /* Due xdp_adjust_tail: DMA sync for_device cover max len CPU touch */
3799         sync = xdp->data_end - xdp->data_hard_start - MVPP2_SKB_HEADROOM;
3800         sync = max(sync, len);
3801
3802         switch (act) {
3803         case XDP_PASS:
3804                 stats->xdp_pass++;
3805                 ret = MVPP2_XDP_PASS;
3806                 break;
3807         case XDP_REDIRECT:
3808                 err = xdp_do_redirect(port->dev, xdp, prog);
3809                 if (unlikely(err)) {
3810                         ret = MVPP2_XDP_DROPPED;
3811                         page = virt_to_head_page(xdp->data);
3812                         page_pool_put_page(pp, page, sync, true);
3813                 } else {
3814                         ret = MVPP2_XDP_REDIR;
3815                         stats->xdp_redirect++;
3816                 }
3817                 break;
3818         case XDP_TX:
3819                 ret = mvpp2_xdp_xmit_back(port, xdp);
3820                 if (ret != MVPP2_XDP_TX) {
3821                         page = virt_to_head_page(xdp->data);
3822                         page_pool_put_page(pp, page, sync, true);
3823                 }
3824                 break;
3825         default:
3826                 bpf_warn_invalid_xdp_action(act);
3827                 fallthrough;
3828         case XDP_ABORTED:
3829                 trace_xdp_exception(port->dev, prog, act);
3830                 fallthrough;
3831         case XDP_DROP:
3832                 page = virt_to_head_page(xdp->data);
3833                 page_pool_put_page(pp, page, sync, true);
3834                 ret = MVPP2_XDP_DROPPED;
3835                 stats->xdp_drop++;
3836                 break;
3837         }
3838
3839         return ret;
3840 }
3841
3842 static void mvpp2_buff_hdr_pool_put(struct mvpp2_port *port, struct mvpp2_rx_desc *rx_desc,
3843                                     int pool, u32 rx_status)
3844 {
3845         phys_addr_t phys_addr, phys_addr_next;
3846         dma_addr_t dma_addr, dma_addr_next;
3847         struct mvpp2_buff_hdr *buff_hdr;
3848
3849         phys_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc);
3850         dma_addr = mvpp2_rxdesc_cookie_get(port, rx_desc);
3851
3852         do {
3853                 buff_hdr = (struct mvpp2_buff_hdr *)phys_to_virt(phys_addr);
3854
3855                 phys_addr_next = le32_to_cpu(buff_hdr->next_phys_addr);
3856                 dma_addr_next = le32_to_cpu(buff_hdr->next_dma_addr);
3857
3858                 if (port->priv->hw_version >= MVPP22) {
3859                         phys_addr_next |= ((u64)buff_hdr->next_phys_addr_high << 32);
3860                         dma_addr_next |= ((u64)buff_hdr->next_dma_addr_high << 32);
3861                 }
3862
3863                 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr);
3864
3865                 phys_addr = phys_addr_next;
3866                 dma_addr = dma_addr_next;
3867
3868         } while (!MVPP2_B_HDR_INFO_IS_LAST(le16_to_cpu(buff_hdr->info)));
3869 }
3870
3871 /* Main rx processing */
3872 static int mvpp2_rx(struct mvpp2_port *port, struct napi_struct *napi,
3873                     int rx_todo, struct mvpp2_rx_queue *rxq)
3874 {
3875         struct net_device *dev = port->dev;
3876         struct mvpp2_pcpu_stats ps = {};
3877         enum dma_data_direction dma_dir;
3878         struct bpf_prog *xdp_prog;
3879         struct xdp_buff xdp;
3880         int rx_received;
3881         int rx_done = 0;
3882         u32 xdp_ret = 0;
3883
3884         rcu_read_lock();
3885
3886         xdp_prog = READ_ONCE(port->xdp_prog);
3887
3888         /* Get number of received packets and clamp the to-do */
3889         rx_received = mvpp2_rxq_received(port, rxq->id);
3890         if (rx_todo > rx_received)
3891                 rx_todo = rx_received;
3892
3893         while (rx_done < rx_todo) {
3894                 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
3895                 struct mvpp2_bm_pool *bm_pool;
3896                 struct page_pool *pp = NULL;
3897                 struct sk_buff *skb;
3898                 unsigned int frag_size;
3899                 dma_addr_t dma_addr;
3900                 phys_addr_t phys_addr;
3901                 u32 rx_status, timestamp;
3902                 int pool, rx_bytes, err, ret;
3903                 void *data;
3904
3905                 rx_done++;
3906                 rx_status = mvpp2_rxdesc_status_get(port, rx_desc);
3907                 rx_bytes = mvpp2_rxdesc_size_get(port, rx_desc);
3908                 rx_bytes -= MVPP2_MH_SIZE;
3909                 dma_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc);
3910                 phys_addr = mvpp2_rxdesc_cookie_get(port, rx_desc);
3911                 data = (void *)phys_to_virt(phys_addr);
3912
3913                 pool = (rx_status & MVPP2_RXD_BM_POOL_ID_MASK) >>
3914                         MVPP2_RXD_BM_POOL_ID_OFFS;
3915                 bm_pool = &port->priv->bm_pools[pool];
3916
3917                 if (port->priv->percpu_pools) {
3918                         pp = port->priv->page_pool[pool];
3919                         dma_dir = page_pool_get_dma_dir(pp);
3920                 } else {
3921                         dma_dir = DMA_FROM_DEVICE;
3922                 }
3923
3924                 dma_sync_single_for_cpu(dev->dev.parent, dma_addr,
3925                                         rx_bytes + MVPP2_MH_SIZE,
3926                                         dma_dir);
3927
3928                 /* Buffer header not supported */
3929                 if (rx_status & MVPP2_RXD_BUF_HDR)
3930                         goto err_drop_frame;
3931
3932                 /* In case of an error, release the requested buffer pointer
3933                  * to the Buffer Manager. This request process is controlled
3934                  * by the hardware, and the information about the buffer is
3935                  * comprised by the RX descriptor.
3936                  */
3937                 if (rx_status & MVPP2_RXD_ERR_SUMMARY)
3938                         goto err_drop_frame;
3939
3940                 /* Prefetch header */
3941                 prefetch(data);
3942
3943                 if (bm_pool->frag_size > PAGE_SIZE)
3944                         frag_size = 0;
3945                 else
3946                         frag_size = bm_pool->frag_size;
3947
3948                 if (xdp_prog) {
3949                         struct xdp_rxq_info *xdp_rxq;
3950
3951                         if (bm_pool->pkt_size == MVPP2_BM_SHORT_PKT_SIZE)
3952                                 xdp_rxq = &rxq->xdp_rxq_short;
3953                         else
3954                                 xdp_rxq = &rxq->xdp_rxq_long;
3955
3956                         xdp_init_buff(&xdp, PAGE_SIZE, xdp_rxq);
3957                         xdp_prepare_buff(&xdp, data,
3958                                          MVPP2_MH_SIZE + MVPP2_SKB_HEADROOM,
3959                                          rx_bytes, false);
3960
3961                         ret = mvpp2_run_xdp(port, rxq, xdp_prog, &xdp, pp, &ps);
3962
3963                         if (ret) {
3964                                 xdp_ret |= ret;
3965                                 err = mvpp2_rx_refill(port, bm_pool, pp, pool);
3966                                 if (err) {
3967                                         netdev_err(port->dev, "failed to refill BM pools\n");
3968                                         goto err_drop_frame;
3969                                 }
3970
3971                                 ps.rx_packets++;
3972                                 ps.rx_bytes += rx_bytes;
3973                                 continue;
3974                         }
3975                 }
3976
3977                 skb = build_skb(data, frag_size);
3978                 if (!skb) {
3979                         netdev_warn(port->dev, "skb build failed\n");
3980                         goto err_drop_frame;
3981                 }
3982
3983                 /* If we have RX hardware timestamping enabled, grab the
3984                  * timestamp from the queue and convert.
3985                  */
3986                 if (mvpp22_rx_hwtstamping(port)) {
3987                         timestamp = le32_to_cpu(rx_desc->pp22.timestamp);
3988                         mvpp22_tai_tstamp(port->priv->tai, timestamp,
3989                                          skb_hwtstamps(skb));
3990                 }
3991
3992                 err = mvpp2_rx_refill(port, bm_pool, pp, pool);
3993                 if (err) {
3994                         netdev_err(port->dev, "failed to refill BM pools\n");
3995                         dev_kfree_skb_any(skb);
3996                         goto err_drop_frame;
3997                 }
3998
3999                 if (pp)
4000                         page_pool_release_page(pp, virt_to_page(data));
4001                 else
4002                         dma_unmap_single_attrs(dev->dev.parent, dma_addr,
4003                                                bm_pool->buf_size, DMA_FROM_DEVICE,
4004                                                DMA_ATTR_SKIP_CPU_SYNC);
4005
4006                 ps.rx_packets++;
4007                 ps.rx_bytes += rx_bytes;
4008
4009                 skb_reserve(skb, MVPP2_MH_SIZE + MVPP2_SKB_HEADROOM);
4010                 skb_put(skb, rx_bytes);
4011                 skb->protocol = eth_type_trans(skb, dev);
4012                 mvpp2_rx_csum(port, rx_status, skb);
4013
4014                 napi_gro_receive(napi, skb);
4015                 continue;
4016
4017 err_drop_frame:
4018                 dev->stats.rx_errors++;
4019                 mvpp2_rx_error(port, rx_desc);
4020                 /* Return the buffer to the pool */
4021                 if (rx_status & MVPP2_RXD_BUF_HDR)
4022                         mvpp2_buff_hdr_pool_put(port, rx_desc, pool, rx_status);
4023                 else
4024                         mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr);
4025         }
4026
4027         rcu_read_unlock();
4028
4029         if (xdp_ret & MVPP2_XDP_REDIR)
4030                 xdp_do_flush_map();
4031
4032         if (ps.rx_packets) {
4033                 struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats);
4034
4035                 u64_stats_update_begin(&stats->syncp);
4036                 stats->rx_packets += ps.rx_packets;
4037                 stats->rx_bytes   += ps.rx_bytes;
4038                 /* xdp */
4039                 stats->xdp_redirect += ps.xdp_redirect;
4040                 stats->xdp_pass += ps.xdp_pass;
4041                 stats->xdp_drop += ps.xdp_drop;
4042                 u64_stats_update_end(&stats->syncp);
4043         }
4044
4045         /* Update Rx queue management counters */
4046         wmb();
4047         mvpp2_rxq_status_update(port, rxq->id, rx_done, rx_done);
4048
4049         return rx_todo;
4050 }
4051
4052 static inline void
4053 tx_desc_unmap_put(struct mvpp2_port *port, struct mvpp2_tx_queue *txq,
4054                   struct mvpp2_tx_desc *desc)
4055 {
4056         unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
4057         struct mvpp2_txq_pcpu *txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
4058
4059         dma_addr_t buf_dma_addr =
4060                 mvpp2_txdesc_dma_addr_get(port, desc);
4061         size_t buf_sz =
4062                 mvpp2_txdesc_size_get(port, desc);
4063         if (!IS_TSO_HEADER(txq_pcpu, buf_dma_addr))
4064                 dma_unmap_single(port->dev->dev.parent, buf_dma_addr,
4065                                  buf_sz, DMA_TO_DEVICE);
4066         mvpp2_txq_desc_put(txq);
4067 }
4068
4069 static void mvpp2_txdesc_clear_ptp(struct mvpp2_port *port,
4070                                    struct mvpp2_tx_desc *desc)
4071 {
4072         /* We only need to clear the low bits */
4073         if (port->priv->hw_version >= MVPP22)
4074                 desc->pp22.ptp_descriptor &=
4075                         cpu_to_le32(~MVPP22_PTP_DESC_MASK_LOW);
4076 }
4077
4078 static bool mvpp2_tx_hw_tstamp(struct mvpp2_port *port,
4079                                struct mvpp2_tx_desc *tx_desc,
4080                                struct sk_buff *skb)
4081 {
4082         struct mvpp2_hwtstamp_queue *queue;
4083         unsigned int mtype, type, i;
4084         struct ptp_header *hdr;
4085         u64 ptpdesc;
4086
4087         if (port->priv->hw_version == MVPP21 ||
4088             port->tx_hwtstamp_type == HWTSTAMP_TX_OFF)
4089                 return false;
4090
4091         type = ptp_classify_raw(skb);
4092         if (!type)
4093                 return false;
4094
4095         hdr = ptp_parse_header(skb, type);
4096         if (!hdr)
4097                 return false;
4098
4099         skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4100
4101         ptpdesc = MVPP22_PTP_MACTIMESTAMPINGEN |
4102                   MVPP22_PTP_ACTION_CAPTURE;
4103         queue = &port->tx_hwtstamp_queue[0];
4104
4105         switch (type & PTP_CLASS_VMASK) {
4106         case PTP_CLASS_V1:
4107                 ptpdesc |= MVPP22_PTP_PACKETFORMAT(MVPP22_PTP_PKT_FMT_PTPV1);
4108                 break;
4109
4110         case PTP_CLASS_V2:
4111                 ptpdesc |= MVPP22_PTP_PACKETFORMAT(MVPP22_PTP_PKT_FMT_PTPV2);
4112                 mtype = hdr->tsmt & 15;
4113                 /* Direct PTP Sync messages to queue 1 */
4114                 if (mtype == 0) {
4115                         ptpdesc |= MVPP22_PTP_TIMESTAMPQUEUESELECT;
4116                         queue = &port->tx_hwtstamp_queue[1];
4117                 }
4118                 break;
4119         }
4120
4121         /* Take a reference on the skb and insert into our queue */
4122         i = queue->next;
4123         queue->next = (i + 1) & 31;
4124         if (queue->skb[i])
4125                 dev_kfree_skb_any(queue->skb[i]);
4126         queue->skb[i] = skb_get(skb);
4127
4128         ptpdesc |= MVPP22_PTP_TIMESTAMPENTRYID(i);
4129
4130         /*
4131          * 3:0          - PTPAction
4132          * 6:4          - PTPPacketFormat
4133          * 7            - PTP_CF_WraparoundCheckEn
4134          * 9:8          - IngressTimestampSeconds[1:0]
4135          * 10           - Reserved
4136          * 11           - MACTimestampingEn
4137          * 17:12        - PTP_TimestampQueueEntryID[5:0]
4138          * 18           - PTPTimestampQueueSelect
4139          * 19           - UDPChecksumUpdateEn
4140          * 27:20        - TimestampOffset
4141          *                      PTP, NTPTransmit, OWAMP/TWAMP - L3 to PTP header
4142          *                      NTPTs, Y.1731 - L3 to timestamp entry
4143          * 35:28        - UDP Checksum Offset
4144          *
4145          * stored in tx descriptor bits 75:64 (11:0) and 191:168 (35:12)
4146          */
4147         tx_desc->pp22.ptp_descriptor &=
4148                 cpu_to_le32(~MVPP22_PTP_DESC_MASK_LOW);
4149         tx_desc->pp22.ptp_descriptor |=
4150                 cpu_to_le32(ptpdesc & MVPP22_PTP_DESC_MASK_LOW);
4151         tx_desc->pp22.buf_dma_addr_ptp &= cpu_to_le64(~0xffffff0000000000ULL);
4152         tx_desc->pp22.buf_dma_addr_ptp |= cpu_to_le64((ptpdesc >> 12) << 40);
4153
4154         return true;
4155 }
4156
4157 /* Handle tx fragmentation processing */
4158 static int mvpp2_tx_frag_process(struct mvpp2_port *port, struct sk_buff *skb,
4159                                  struct mvpp2_tx_queue *aggr_txq,
4160                                  struct mvpp2_tx_queue *txq)
4161 {
4162         unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
4163         struct mvpp2_txq_pcpu *txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
4164         struct mvpp2_tx_desc *tx_desc;
4165         int i;
4166         dma_addr_t buf_dma_addr;
4167
4168         for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4169                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4170                 void *addr = skb_frag_address(frag);
4171
4172                 tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
4173                 mvpp2_txdesc_clear_ptp(port, tx_desc);
4174                 mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
4175                 mvpp2_txdesc_size_set(port, tx_desc, skb_frag_size(frag));
4176
4177                 buf_dma_addr = dma_map_single(port->dev->dev.parent, addr,
4178                                               skb_frag_size(frag),
4179                                               DMA_TO_DEVICE);
4180                 if (dma_mapping_error(port->dev->dev.parent, buf_dma_addr)) {
4181                         mvpp2_txq_desc_put(txq);
4182                         goto cleanup;
4183                 }
4184
4185                 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr);
4186
4187                 if (i == (skb_shinfo(skb)->nr_frags - 1)) {
4188                         /* Last descriptor */
4189                         mvpp2_txdesc_cmd_set(port, tx_desc,
4190                                              MVPP2_TXD_L_DESC);
4191                         mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc, MVPP2_TYPE_SKB);
4192                 } else {
4193                         /* Descriptor in the middle: Not First, Not Last */
4194                         mvpp2_txdesc_cmd_set(port, tx_desc, 0);
4195                         mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB);
4196                 }
4197         }
4198
4199         return 0;
4200 cleanup:
4201         /* Release all descriptors that were used to map fragments of
4202          * this packet, as well as the corresponding DMA mappings
4203          */
4204         for (i = i - 1; i >= 0; i--) {
4205                 tx_desc = txq->descs + i;
4206                 tx_desc_unmap_put(port, txq, tx_desc);
4207         }
4208
4209         return -ENOMEM;
4210 }
4211
4212 static inline void mvpp2_tso_put_hdr(struct sk_buff *skb,
4213                                      struct net_device *dev,
4214                                      struct mvpp2_tx_queue *txq,
4215                                      struct mvpp2_tx_queue *aggr_txq,
4216                                      struct mvpp2_txq_pcpu *txq_pcpu,
4217                                      int hdr_sz)
4218 {
4219         struct mvpp2_port *port = netdev_priv(dev);
4220         struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
4221         dma_addr_t addr;
4222
4223         mvpp2_txdesc_clear_ptp(port, tx_desc);
4224         mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
4225         mvpp2_txdesc_size_set(port, tx_desc, hdr_sz);
4226
4227         addr = txq_pcpu->tso_headers_dma +
4228                txq_pcpu->txq_put_index * TSO_HEADER_SIZE;
4229         mvpp2_txdesc_dma_addr_set(port, tx_desc, addr);
4230
4231         mvpp2_txdesc_cmd_set(port, tx_desc, mvpp2_skb_tx_csum(port, skb) |
4232                                             MVPP2_TXD_F_DESC |
4233                                             MVPP2_TXD_PADDING_DISABLE);
4234         mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB);
4235 }
4236
4237 static inline int mvpp2_tso_put_data(struct sk_buff *skb,
4238                                      struct net_device *dev, struct tso_t *tso,
4239                                      struct mvpp2_tx_queue *txq,
4240                                      struct mvpp2_tx_queue *aggr_txq,
4241                                      struct mvpp2_txq_pcpu *txq_pcpu,
4242                                      int sz, bool left, bool last)
4243 {
4244         struct mvpp2_port *port = netdev_priv(dev);
4245         struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
4246         dma_addr_t buf_dma_addr;
4247
4248         mvpp2_txdesc_clear_ptp(port, tx_desc);
4249         mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
4250         mvpp2_txdesc_size_set(port, tx_desc, sz);
4251
4252         buf_dma_addr = dma_map_single(dev->dev.parent, tso->data, sz,
4253                                       DMA_TO_DEVICE);
4254         if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) {
4255                 mvpp2_txq_desc_put(txq);
4256                 return -ENOMEM;
4257         }
4258
4259         mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr);
4260
4261         if (!left) {
4262                 mvpp2_txdesc_cmd_set(port, tx_desc, MVPP2_TXD_L_DESC);
4263                 if (last) {
4264                         mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc, MVPP2_TYPE_SKB);
4265                         return 0;
4266                 }
4267         } else {
4268                 mvpp2_txdesc_cmd_set(port, tx_desc, 0);
4269         }
4270
4271         mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB);
4272         return 0;
4273 }
4274
4275 static int mvpp2_tx_tso(struct sk_buff *skb, struct net_device *dev,
4276                         struct mvpp2_tx_queue *txq,
4277                         struct mvpp2_tx_queue *aggr_txq,
4278                         struct mvpp2_txq_pcpu *txq_pcpu)
4279 {
4280         struct mvpp2_port *port = netdev_priv(dev);
4281         int hdr_sz, i, len, descs = 0;
4282         struct tso_t tso;
4283
4284         /* Check number of available descriptors */
4285         if (mvpp2_aggr_desc_num_check(port, aggr_txq, tso_count_descs(skb)) ||
4286             mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu,
4287                                              tso_count_descs(skb)))
4288                 return 0;
4289
4290         hdr_sz = tso_start(skb, &tso);
4291
4292         len = skb->len - hdr_sz;
4293         while (len > 0) {
4294                 int left = min_t(int, skb_shinfo(skb)->gso_size, len);
4295                 char *hdr = txq_pcpu->tso_headers +
4296                             txq_pcpu->txq_put_index * TSO_HEADER_SIZE;
4297
4298                 len -= left;
4299                 descs++;
4300
4301                 tso_build_hdr(skb, hdr, &tso, left, len == 0);
4302                 mvpp2_tso_put_hdr(skb, dev, txq, aggr_txq, txq_pcpu, hdr_sz);
4303
4304                 while (left > 0) {
4305                         int sz = min_t(int, tso.size, left);
4306                         left -= sz;
4307                         descs++;
4308
4309                         if (mvpp2_tso_put_data(skb, dev, &tso, txq, aggr_txq,
4310                                                txq_pcpu, sz, left, len == 0))
4311                                 goto release;
4312                         tso_build_data(skb, &tso, sz);
4313                 }
4314         }
4315
4316         return descs;
4317
4318 release:
4319         for (i = descs - 1; i >= 0; i--) {
4320                 struct mvpp2_tx_desc *tx_desc = txq->descs + i;
4321                 tx_desc_unmap_put(port, txq, tx_desc);
4322         }
4323         return 0;
4324 }
4325
4326 /* Main tx processing */
4327 static netdev_tx_t mvpp2_tx(struct sk_buff *skb, struct net_device *dev)
4328 {
4329         struct mvpp2_port *port = netdev_priv(dev);
4330         struct mvpp2_tx_queue *txq, *aggr_txq;
4331         struct mvpp2_txq_pcpu *txq_pcpu;
4332         struct mvpp2_tx_desc *tx_desc;
4333         dma_addr_t buf_dma_addr;
4334         unsigned long flags = 0;
4335         unsigned int thread;
4336         int frags = 0;
4337         u16 txq_id;
4338         u32 tx_cmd;
4339
4340         thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
4341
4342         txq_id = skb_get_queue_mapping(skb);
4343         txq = port->txqs[txq_id];
4344         txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
4345         aggr_txq = &port->priv->aggr_txqs[thread];
4346
4347         if (test_bit(thread, &port->priv->lock_map))
4348                 spin_lock_irqsave(&port->tx_lock[thread], flags);
4349
4350         if (skb_is_gso(skb)) {
4351                 frags = mvpp2_tx_tso(skb, dev, txq, aggr_txq, txq_pcpu);
4352                 goto out;
4353         }
4354         frags = skb_shinfo(skb)->nr_frags + 1;
4355
4356         /* Check number of available descriptors */
4357         if (mvpp2_aggr_desc_num_check(port, aggr_txq, frags) ||
4358             mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu, frags)) {
4359                 frags = 0;
4360                 goto out;
4361         }
4362
4363         /* Get a descriptor for the first part of the packet */
4364         tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
4365         if (!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ||
4366             !mvpp2_tx_hw_tstamp(port, tx_desc, skb))
4367                 mvpp2_txdesc_clear_ptp(port, tx_desc);
4368         mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
4369         mvpp2_txdesc_size_set(port, tx_desc, skb_headlen(skb));
4370
4371         buf_dma_addr = dma_map_single(dev->dev.parent, skb->data,
4372                                       skb_headlen(skb), DMA_TO_DEVICE);
4373         if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) {
4374                 mvpp2_txq_desc_put(txq);
4375                 frags = 0;
4376                 goto out;
4377         }
4378
4379         mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr);
4380
4381         tx_cmd = mvpp2_skb_tx_csum(port, skb);
4382
4383         if (frags == 1) {
4384                 /* First and Last descriptor */
4385                 tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC;
4386                 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd);
4387                 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc, MVPP2_TYPE_SKB);
4388         } else {
4389                 /* First but not Last */
4390                 tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_PADDING_DISABLE;
4391                 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd);
4392                 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB);
4393
4394                 /* Continue with other skb fragments */
4395                 if (mvpp2_tx_frag_process(port, skb, aggr_txq, txq)) {
4396                         tx_desc_unmap_put(port, txq, tx_desc);
4397                         frags = 0;
4398                 }
4399         }
4400
4401 out:
4402         if (frags > 0) {
4403                 struct mvpp2_pcpu_stats *stats = per_cpu_ptr(port->stats, thread);
4404                 struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id);
4405
4406                 txq_pcpu->reserved_num -= frags;
4407                 txq_pcpu->count += frags;
4408                 aggr_txq->count += frags;
4409
4410                 /* Enable transmit */
4411                 wmb();
4412                 mvpp2_aggr_txq_pend_desc_add(port, frags);
4413
4414                 if (txq_pcpu->count >= txq_pcpu->stop_threshold)
4415                         netif_tx_stop_queue(nq);
4416
4417                 u64_stats_update_begin(&stats->syncp);
4418                 stats->tx_packets++;
4419                 stats->tx_bytes += skb->len;
4420                 u64_stats_update_end(&stats->syncp);
4421         } else {
4422                 dev->stats.tx_dropped++;
4423                 dev_kfree_skb_any(skb);
4424         }
4425
4426         /* Finalize TX processing */
4427         if (!port->has_tx_irqs && txq_pcpu->count >= txq->done_pkts_coal)
4428                 mvpp2_txq_done(port, txq, txq_pcpu);
4429
4430         /* Set the timer in case not all frags were processed */
4431         if (!port->has_tx_irqs && txq_pcpu->count <= frags &&
4432             txq_pcpu->count > 0) {
4433                 struct mvpp2_port_pcpu *port_pcpu = per_cpu_ptr(port->pcpu, thread);
4434
4435                 if (!port_pcpu->timer_scheduled) {
4436                         port_pcpu->timer_scheduled = true;
4437                         hrtimer_start(&port_pcpu->tx_done_timer,
4438                                       MVPP2_TXDONE_HRTIMER_PERIOD_NS,
4439                                       HRTIMER_MODE_REL_PINNED_SOFT);
4440                 }
4441         }
4442
4443         if (test_bit(thread, &port->priv->lock_map))
4444                 spin_unlock_irqrestore(&port->tx_lock[thread], flags);
4445
4446         return NETDEV_TX_OK;
4447 }
4448
4449 static inline void mvpp2_cause_error(struct net_device *dev, int cause)
4450 {
4451         if (cause & MVPP2_CAUSE_FCS_ERR_MASK)
4452                 netdev_err(dev, "FCS error\n");
4453         if (cause & MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK)
4454                 netdev_err(dev, "rx fifo overrun error\n");
4455         if (cause & MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK)
4456                 netdev_err(dev, "tx fifo underrun error\n");
4457 }
4458
4459 static int mvpp2_poll(struct napi_struct *napi, int budget)
4460 {
4461         u32 cause_rx_tx, cause_rx, cause_tx, cause_misc;
4462         int rx_done = 0;
4463         struct mvpp2_port *port = netdev_priv(napi->dev);
4464         struct mvpp2_queue_vector *qv;
4465         unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
4466
4467         qv = container_of(napi, struct mvpp2_queue_vector, napi);
4468
4469         /* Rx/Tx cause register
4470          *
4471          * Bits 0-15: each bit indicates received packets on the Rx queue
4472          * (bit 0 is for Rx queue 0).
4473          *
4474          * Bits 16-23: each bit indicates transmitted packets on the Tx queue
4475          * (bit 16 is for Tx queue 0).
4476          *
4477          * Each CPU has its own Rx/Tx cause register
4478          */
4479         cause_rx_tx = mvpp2_thread_read_relaxed(port->priv, qv->sw_thread_id,
4480                                                 MVPP2_ISR_RX_TX_CAUSE_REG(port->id));
4481
4482         cause_misc = cause_rx_tx & MVPP2_CAUSE_MISC_SUM_MASK;
4483         if (cause_misc) {
4484                 mvpp2_cause_error(port->dev, cause_misc);
4485
4486                 /* Clear the cause register */
4487                 mvpp2_write(port->priv, MVPP2_ISR_MISC_CAUSE_REG, 0);
4488                 mvpp2_thread_write(port->priv, thread,
4489                                    MVPP2_ISR_RX_TX_CAUSE_REG(port->id),
4490                                    cause_rx_tx & ~MVPP2_CAUSE_MISC_SUM_MASK);
4491         }
4492
4493         if (port->has_tx_irqs) {
4494                 cause_tx = cause_rx_tx & MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK;
4495                 if (cause_tx) {
4496                         cause_tx >>= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_OFFSET;
4497                         mvpp2_tx_done(port, cause_tx, qv->sw_thread_id);
4498                 }
4499         }
4500
4501         /* Process RX packets */
4502         cause_rx = cause_rx_tx &
4503                    MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version);
4504         cause_rx <<= qv->first_rxq;
4505         cause_rx |= qv->pending_cause_rx;
4506         while (cause_rx && budget > 0) {
4507                 int count;
4508                 struct mvpp2_rx_queue *rxq;
4509
4510                 rxq = mvpp2_get_rx_queue(port, cause_rx);
4511                 if (!rxq)
4512                         break;
4513
4514                 count = mvpp2_rx(port, napi, budget, rxq);
4515                 rx_done += count;
4516                 budget -= count;
4517                 if (budget > 0) {
4518                         /* Clear the bit associated to this Rx queue
4519                          * so that next iteration will continue from
4520                          * the next Rx queue.
4521                          */
4522                         cause_rx &= ~(1 << rxq->logic_rxq);
4523                 }
4524         }
4525
4526         if (budget > 0) {
4527                 cause_rx = 0;
4528                 napi_complete_done(napi, rx_done);
4529
4530                 mvpp2_qvec_interrupt_enable(qv);
4531         }
4532         qv->pending_cause_rx = cause_rx;
4533         return rx_done;
4534 }
4535
4536 static void mvpp22_mode_reconfigure(struct mvpp2_port *port)
4537 {
4538         u32 ctrl3;
4539
4540         /* Set the GMAC & XLG MAC in reset */
4541         mvpp2_mac_reset_assert(port);
4542
4543         /* Set the MPCS and XPCS in reset */
4544         mvpp22_pcs_reset_assert(port);
4545
4546         /* comphy reconfiguration */
4547         mvpp22_comphy_init(port);
4548
4549         /* gop reconfiguration */
4550         mvpp22_gop_init(port);
4551
4552         mvpp22_pcs_reset_deassert(port);
4553
4554         if (mvpp2_port_supports_xlg(port)) {
4555                 ctrl3 = readl(port->base + MVPP22_XLG_CTRL3_REG);
4556                 ctrl3 &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
4557
4558                 if (mvpp2_is_xlg(port->phy_interface))
4559                         ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_10G;
4560                 else
4561                         ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_GMAC;
4562
4563                 writel(ctrl3, port->base + MVPP22_XLG_CTRL3_REG);
4564         }
4565
4566         if (mvpp2_port_supports_xlg(port) && mvpp2_is_xlg(port->phy_interface))
4567                 mvpp2_xlg_max_rx_size_set(port);
4568         else
4569                 mvpp2_gmac_max_rx_size_set(port);
4570 }
4571
4572 /* Set hw internals when starting port */
4573 static void mvpp2_start_dev(struct mvpp2_port *port)
4574 {
4575         int i;
4576
4577         mvpp2_txp_max_tx_size_set(port);
4578
4579         for (i = 0; i < port->nqvecs; i++)
4580                 napi_enable(&port->qvecs[i].napi);
4581
4582         /* Enable interrupts on all threads */
4583         mvpp2_interrupts_enable(port);
4584
4585         if (port->priv->hw_version >= MVPP22)
4586                 mvpp22_mode_reconfigure(port);
4587
4588         if (port->phylink) {
4589                 phylink_start(port->phylink);
4590         } else {
4591                 mvpp2_acpi_start(port);
4592         }
4593
4594         netif_tx_start_all_queues(port->dev);
4595
4596         clear_bit(0, &port->state);
4597 }
4598
4599 /* Set hw internals when stopping port */
4600 static void mvpp2_stop_dev(struct mvpp2_port *port)
4601 {
4602         int i;
4603
4604         set_bit(0, &port->state);
4605
4606         /* Disable interrupts on all threads */
4607         mvpp2_interrupts_disable(port);
4608
4609         for (i = 0; i < port->nqvecs; i++)
4610                 napi_disable(&port->qvecs[i].napi);
4611
4612         if (port->phylink)
4613                 phylink_stop(port->phylink);
4614         phy_power_off(port->comphy);
4615 }
4616
4617 static int mvpp2_check_ringparam_valid(struct net_device *dev,
4618                                        struct ethtool_ringparam *ring)
4619 {
4620         u16 new_rx_pending = ring->rx_pending;
4621         u16 new_tx_pending = ring->tx_pending;
4622
4623         if (ring->rx_pending == 0 || ring->tx_pending == 0)
4624                 return -EINVAL;
4625
4626         if (ring->rx_pending > MVPP2_MAX_RXD_MAX)
4627                 new_rx_pending = MVPP2_MAX_RXD_MAX;
4628         else if (ring->rx_pending < MSS_THRESHOLD_START)
4629                 new_rx_pending = MSS_THRESHOLD_START;
4630         else if (!IS_ALIGNED(ring->rx_pending, 16))
4631                 new_rx_pending = ALIGN(ring->rx_pending, 16);
4632
4633         if (ring->tx_pending > MVPP2_MAX_TXD_MAX)
4634                 new_tx_pending = MVPP2_MAX_TXD_MAX;
4635         else if (!IS_ALIGNED(ring->tx_pending, 32))
4636                 new_tx_pending = ALIGN(ring->tx_pending, 32);
4637
4638         /* The Tx ring size cannot be smaller than the minimum number of
4639          * descriptors needed for TSO.
4640          */
4641         if (new_tx_pending < MVPP2_MAX_SKB_DESCS)
4642                 new_tx_pending = ALIGN(MVPP2_MAX_SKB_DESCS, 32);
4643
4644         if (ring->rx_pending != new_rx_pending) {
4645                 netdev_info(dev, "illegal Rx ring size value %d, round to %d\n",
4646                             ring->rx_pending, new_rx_pending);
4647                 ring->rx_pending = new_rx_pending;
4648         }
4649
4650         if (ring->tx_pending != new_tx_pending) {
4651                 netdev_info(dev, "illegal Tx ring size value %d, round to %d\n",
4652                             ring->tx_pending, new_tx_pending);
4653                 ring->tx_pending = new_tx_pending;
4654         }
4655
4656         return 0;
4657 }
4658
4659 static void mvpp21_get_mac_address(struct mvpp2_port *port, unsigned char *addr)
4660 {
4661         u32 mac_addr_l, mac_addr_m, mac_addr_h;
4662
4663         mac_addr_l = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
4664         mac_addr_m = readl(port->priv->lms_base + MVPP2_SRC_ADDR_MIDDLE);
4665         mac_addr_h = readl(port->priv->lms_base + MVPP2_SRC_ADDR_HIGH);
4666         addr[0] = (mac_addr_h >> 24) & 0xFF;
4667         addr[1] = (mac_addr_h >> 16) & 0xFF;
4668         addr[2] = (mac_addr_h >> 8) & 0xFF;
4669         addr[3] = mac_addr_h & 0xFF;
4670         addr[4] = mac_addr_m & 0xFF;
4671         addr[5] = (mac_addr_l >> MVPP2_GMAC_SA_LOW_OFFS) & 0xFF;
4672 }
4673
4674 static int mvpp2_irqs_init(struct mvpp2_port *port)
4675 {
4676         int err, i;
4677
4678         for (i = 0; i < port->nqvecs; i++) {
4679                 struct mvpp2_queue_vector *qv = port->qvecs + i;
4680
4681                 if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE) {
4682                         qv->mask = kzalloc(cpumask_size(), GFP_KERNEL);
4683                         if (!qv->mask) {
4684                                 err = -ENOMEM;
4685                                 goto err;
4686                         }
4687
4688                         irq_set_status_flags(qv->irq, IRQ_NO_BALANCING);
4689                 }
4690
4691                 err = request_irq(qv->irq, mvpp2_isr, 0, port->dev->name, qv);
4692                 if (err)
4693                         goto err;
4694
4695                 if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE) {
4696                         unsigned int cpu;
4697
4698                         for_each_present_cpu(cpu) {
4699                                 if (mvpp2_cpu_to_thread(port->priv, cpu) ==
4700                                     qv->sw_thread_id)
4701                                         cpumask_set_cpu(cpu, qv->mask);
4702                         }
4703
4704                         irq_set_affinity_hint(qv->irq, qv->mask);
4705                 }
4706         }
4707
4708         return 0;
4709 err:
4710         for (i = 0; i < port->nqvecs; i++) {
4711                 struct mvpp2_queue_vector *qv = port->qvecs + i;
4712
4713                 irq_set_affinity_hint(qv->irq, NULL);
4714                 kfree(qv->mask);
4715                 qv->mask = NULL;
4716                 free_irq(qv->irq, qv);
4717         }
4718
4719         return err;
4720 }
4721
4722 static void mvpp2_irqs_deinit(struct mvpp2_port *port)
4723 {
4724         int i;
4725
4726         for (i = 0; i < port->nqvecs; i++) {
4727                 struct mvpp2_queue_vector *qv = port->qvecs + i;
4728
4729                 irq_set_affinity_hint(qv->irq, NULL);
4730                 kfree(qv->mask);
4731                 qv->mask = NULL;
4732                 irq_clear_status_flags(qv->irq, IRQ_NO_BALANCING);
4733                 free_irq(qv->irq, qv);
4734         }
4735 }
4736
4737 static bool mvpp22_rss_is_supported(struct mvpp2_port *port)
4738 {
4739         return (queue_mode == MVPP2_QDIST_MULTI_MODE) &&
4740                 !(port->flags & MVPP2_F_LOOPBACK);
4741 }
4742
4743 static int mvpp2_open(struct net_device *dev)
4744 {
4745         struct mvpp2_port *port = netdev_priv(dev);
4746         struct mvpp2 *priv = port->priv;
4747         unsigned char mac_bcast[ETH_ALEN] = {
4748                         0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
4749         bool valid = false;
4750         int err;
4751
4752         err = mvpp2_prs_mac_da_accept(port, mac_bcast, true);
4753         if (err) {
4754                 netdev_err(dev, "mvpp2_prs_mac_da_accept BC failed\n");
4755                 return err;
4756         }
4757         err = mvpp2_prs_mac_da_accept(port, dev->dev_addr, true);
4758         if (err) {
4759                 netdev_err(dev, "mvpp2_prs_mac_da_accept own addr failed\n");
4760                 return err;
4761         }
4762         err = mvpp2_prs_tag_mode_set(port->priv, port->id, MVPP2_TAG_TYPE_MH);
4763         if (err) {
4764                 netdev_err(dev, "mvpp2_prs_tag_mode_set failed\n");
4765                 return err;
4766         }
4767         err = mvpp2_prs_def_flow(port);
4768         if (err) {
4769                 netdev_err(dev, "mvpp2_prs_def_flow failed\n");
4770                 return err;
4771         }
4772
4773         /* Allocate the Rx/Tx queues */
4774         err = mvpp2_setup_rxqs(port);
4775         if (err) {
4776                 netdev_err(port->dev, "cannot allocate Rx queues\n");
4777                 return err;
4778         }
4779
4780         err = mvpp2_setup_txqs(port);
4781         if (err) {
4782                 netdev_err(port->dev, "cannot allocate Tx queues\n");
4783                 goto err_cleanup_rxqs;
4784         }
4785
4786         err = mvpp2_irqs_init(port);
4787         if (err) {
4788                 netdev_err(port->dev, "cannot init IRQs\n");
4789                 goto err_cleanup_txqs;
4790         }
4791
4792         /* Phylink isn't supported yet in ACPI mode */
4793         if (port->of_node) {
4794                 err = phylink_of_phy_connect(port->phylink, port->of_node, 0);
4795                 if (err) {
4796                         netdev_err(port->dev, "could not attach PHY (%d)\n",
4797                                    err);
4798                         goto err_free_irq;
4799                 }
4800
4801                 valid = true;
4802         }
4803
4804         if (priv->hw_version >= MVPP22 && port->port_irq) {
4805                 err = request_irq(port->port_irq, mvpp2_port_isr, 0,
4806                                   dev->name, port);
4807                 if (err) {
4808                         netdev_err(port->dev,
4809                                    "cannot request port link/ptp IRQ %d\n",
4810                                    port->port_irq);
4811                         goto err_free_irq;
4812                 }
4813
4814                 mvpp22_gop_setup_irq(port);
4815
4816                 /* In default link is down */
4817                 netif_carrier_off(port->dev);
4818
4819                 valid = true;
4820         } else {
4821                 port->port_irq = 0;
4822         }
4823
4824         if (!valid) {
4825                 netdev_err(port->dev,
4826                            "invalid configuration: no dt or link IRQ");
4827                 err = -ENOENT;
4828                 goto err_free_irq;
4829         }
4830
4831         /* Unmask interrupts on all CPUs */
4832         on_each_cpu(mvpp2_interrupts_unmask, port, 1);
4833         mvpp2_shared_interrupt_mask_unmask(port, false);
4834
4835         mvpp2_start_dev(port);
4836
4837         /* Start hardware statistics gathering */
4838         queue_delayed_work(priv->stats_queue, &port->stats_work,
4839                            MVPP2_MIB_COUNTERS_STATS_DELAY);
4840
4841         return 0;
4842
4843 err_free_irq:
4844         mvpp2_irqs_deinit(port);
4845 err_cleanup_txqs:
4846         mvpp2_cleanup_txqs(port);
4847 err_cleanup_rxqs:
4848         mvpp2_cleanup_rxqs(port);
4849         return err;
4850 }
4851
4852 static int mvpp2_stop(struct net_device *dev)
4853 {
4854         struct mvpp2_port *port = netdev_priv(dev);
4855         struct mvpp2_port_pcpu *port_pcpu;
4856         unsigned int thread;
4857
4858         mvpp2_stop_dev(port);
4859
4860         /* Mask interrupts on all threads */
4861         on_each_cpu(mvpp2_interrupts_mask, port, 1);
4862         mvpp2_shared_interrupt_mask_unmask(port, true);
4863
4864         if (port->phylink)
4865                 phylink_disconnect_phy(port->phylink);
4866         if (port->port_irq)
4867                 free_irq(port->port_irq, port);
4868
4869         mvpp2_irqs_deinit(port);
4870         if (!port->has_tx_irqs) {
4871                 for (thread = 0; thread < port->priv->nthreads; thread++) {
4872                         port_pcpu = per_cpu_ptr(port->pcpu, thread);
4873
4874                         hrtimer_cancel(&port_pcpu->tx_done_timer);
4875                         port_pcpu->timer_scheduled = false;
4876                 }
4877         }
4878         mvpp2_cleanup_rxqs(port);
4879         mvpp2_cleanup_txqs(port);
4880
4881         cancel_delayed_work_sync(&port->stats_work);
4882
4883         mvpp2_mac_reset_assert(port);
4884         mvpp22_pcs_reset_assert(port);
4885
4886         return 0;
4887 }
4888
4889 static int mvpp2_prs_mac_da_accept_list(struct mvpp2_port *port,
4890                                         struct netdev_hw_addr_list *list)
4891 {
4892         struct netdev_hw_addr *ha;
4893         int ret;
4894
4895         netdev_hw_addr_list_for_each(ha, list) {
4896                 ret = mvpp2_prs_mac_da_accept(port, ha->addr, true);
4897                 if (ret)
4898                         return ret;
4899         }
4900
4901         return 0;
4902 }
4903
4904 static void mvpp2_set_rx_promisc(struct mvpp2_port *port, bool enable)
4905 {
4906         if (!enable && (port->dev->features & NETIF_F_HW_VLAN_CTAG_FILTER))
4907                 mvpp2_prs_vid_enable_filtering(port);
4908         else
4909                 mvpp2_prs_vid_disable_filtering(port);
4910
4911         mvpp2_prs_mac_promisc_set(port->priv, port->id,
4912                                   MVPP2_PRS_L2_UNI_CAST, enable);
4913
4914         mvpp2_prs_mac_promisc_set(port->priv, port->id,
4915                                   MVPP2_PRS_L2_MULTI_CAST, enable);
4916 }
4917
4918 static void mvpp2_set_rx_mode(struct net_device *dev)
4919 {
4920         struct mvpp2_port *port = netdev_priv(dev);
4921
4922         /* Clear the whole UC and MC list */
4923         mvpp2_prs_mac_del_all(port);
4924
4925         if (dev->flags & IFF_PROMISC) {
4926                 mvpp2_set_rx_promisc(port, true);
4927                 return;
4928         }
4929
4930         mvpp2_set_rx_promisc(port, false);
4931
4932         if (netdev_uc_count(dev) > MVPP2_PRS_MAC_UC_FILT_MAX ||
4933             mvpp2_prs_mac_da_accept_list(port, &dev->uc))
4934                 mvpp2_prs_mac_promisc_set(port->priv, port->id,
4935                                           MVPP2_PRS_L2_UNI_CAST, true);
4936
4937         if (dev->flags & IFF_ALLMULTI) {
4938                 mvpp2_prs_mac_promisc_set(port->priv, port->id,
4939                                           MVPP2_PRS_L2_MULTI_CAST, true);
4940                 return;
4941         }
4942
4943         if (netdev_mc_count(dev) > MVPP2_PRS_MAC_MC_FILT_MAX ||
4944             mvpp2_prs_mac_da_accept_list(port, &dev->mc))
4945                 mvpp2_prs_mac_promisc_set(port->priv, port->id,
4946                                           MVPP2_PRS_L2_MULTI_CAST, true);
4947 }
4948
4949 static int mvpp2_set_mac_address(struct net_device *dev, void *p)
4950 {
4951         const struct sockaddr *addr = p;
4952         int err;
4953
4954         if (!is_valid_ether_addr(addr->sa_data))
4955                 return -EADDRNOTAVAIL;
4956
4957         err = mvpp2_prs_update_mac_da(dev, addr->sa_data);
4958         if (err) {
4959                 /* Reconfigure parser accept the original MAC address */
4960                 mvpp2_prs_update_mac_da(dev, dev->dev_addr);
4961                 netdev_err(dev, "failed to change MAC address\n");
4962         }
4963         return err;
4964 }
4965
4966 /* Shut down all the ports, reconfigure the pools as percpu or shared,
4967  * then bring up again all ports.
4968  */
4969 static int mvpp2_bm_switch_buffers(struct mvpp2 *priv, bool percpu)
4970 {
4971         bool change_percpu = (percpu != priv->percpu_pools);
4972         int numbufs = MVPP2_BM_POOLS_NUM, i;
4973         struct mvpp2_port *port = NULL;
4974         bool status[MVPP2_MAX_PORTS];
4975
4976         for (i = 0; i < priv->port_count; i++) {
4977                 port = priv->port_list[i];
4978                 status[i] = netif_running(port->dev);
4979                 if (status[i])
4980                         mvpp2_stop(port->dev);
4981         }
4982
4983         /* nrxqs is the same for all ports */
4984         if (priv->percpu_pools)
4985                 numbufs = port->nrxqs * 2;
4986
4987         if (change_percpu)
4988                 mvpp2_bm_pool_update_priv_fc(priv, false);
4989
4990         for (i = 0; i < numbufs; i++)
4991                 mvpp2_bm_pool_destroy(port->dev->dev.parent, priv, &priv->bm_pools[i]);
4992
4993         devm_kfree(port->dev->dev.parent, priv->bm_pools);
4994         priv->percpu_pools = percpu;
4995         mvpp2_bm_init(port->dev->dev.parent, priv);
4996
4997         for (i = 0; i < priv->port_count; i++) {
4998                 port = priv->port_list[i];
4999                 mvpp2_swf_bm_pool_init(port);
5000                 if (status[i])
5001                         mvpp2_open(port->dev);
5002         }
5003
5004         if (change_percpu)
5005                 mvpp2_bm_pool_update_priv_fc(priv, true);
5006
5007         return 0;
5008 }
5009
5010 static int mvpp2_change_mtu(struct net_device *dev, int mtu)
5011 {
5012         struct mvpp2_port *port = netdev_priv(dev);
5013         bool running = netif_running(dev);
5014         struct mvpp2 *priv = port->priv;
5015         int err;
5016
5017         if (!IS_ALIGNED(MVPP2_RX_PKT_SIZE(mtu), 8)) {
5018                 netdev_info(dev, "illegal MTU value %d, round to %d\n", mtu,
5019                             ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8));
5020                 mtu = ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8);
5021         }
5022
5023         if (MVPP2_RX_PKT_SIZE(mtu) > MVPP2_BM_LONG_PKT_SIZE) {
5024                 if (port->xdp_prog) {
5025                         netdev_err(dev, "Jumbo frames are not supported with XDP\n");
5026                         return -EINVAL;
5027                 }
5028                 if (priv->percpu_pools) {
5029                         netdev_warn(dev, "mtu %d too high, switching to shared buffers", mtu);
5030                         mvpp2_bm_switch_buffers(priv, false);
5031                 }
5032         } else {
5033                 bool jumbo = false;
5034                 int i;
5035
5036                 for (i = 0; i < priv->port_count; i++)
5037                         if (priv->port_list[i] != port &&
5038                             MVPP2_RX_PKT_SIZE(priv->port_list[i]->dev->mtu) >
5039                             MVPP2_BM_LONG_PKT_SIZE) {
5040                                 jumbo = true;
5041                                 break;
5042                         }
5043
5044                 /* No port is using jumbo frames */
5045                 if (!jumbo) {
5046                         dev_info(port->dev->dev.parent,
5047                                  "all ports have a low MTU, switching to per-cpu buffers");
5048                         mvpp2_bm_switch_buffers(priv, true);
5049                 }
5050         }
5051
5052         if (running)
5053                 mvpp2_stop_dev(port);
5054
5055         err = mvpp2_bm_update_mtu(dev, mtu);
5056         if (err) {
5057                 netdev_err(dev, "failed to change MTU\n");
5058                 /* Reconfigure BM to the original MTU */
5059                 mvpp2_bm_update_mtu(dev, dev->mtu);
5060         } else {
5061                 port->pkt_size =  MVPP2_RX_PKT_SIZE(mtu);
5062         }
5063
5064         if (running) {
5065                 mvpp2_start_dev(port);
5066                 mvpp2_egress_enable(port);
5067                 mvpp2_ingress_enable(port);
5068         }
5069
5070         return err;
5071 }
5072
5073 static int mvpp2_check_pagepool_dma(struct mvpp2_port *port)
5074 {
5075         enum dma_data_direction dma_dir = DMA_FROM_DEVICE;
5076         struct mvpp2 *priv = port->priv;
5077         int err = -1, i;
5078
5079         if (!priv->percpu_pools)
5080                 return err;
5081
5082         if (!priv->page_pool[0])
5083                 return -ENOMEM;
5084
5085         for (i = 0; i < priv->port_count; i++) {
5086                 port = priv->port_list[i];
5087                 if (port->xdp_prog) {
5088                         dma_dir = DMA_BIDIRECTIONAL;
5089                         break;
5090                 }
5091         }
5092
5093         /* All pools are equal in terms of DMA direction */
5094         if (priv->page_pool[0]->p.dma_dir != dma_dir)
5095                 err = mvpp2_bm_switch_buffers(priv, true);
5096
5097         return err;
5098 }
5099
5100 static void
5101 mvpp2_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
5102 {
5103         struct mvpp2_port *port = netdev_priv(dev);
5104         unsigned int start;
5105         unsigned int cpu;
5106
5107         for_each_possible_cpu(cpu) {
5108                 struct mvpp2_pcpu_stats *cpu_stats;
5109                 u64 rx_packets;
5110                 u64 rx_bytes;
5111                 u64 tx_packets;
5112                 u64 tx_bytes;
5113
5114                 cpu_stats = per_cpu_ptr(port->stats, cpu);
5115                 do {
5116                         start = u64_stats_fetch_begin_irq(&cpu_stats->syncp);
5117                         rx_packets = cpu_stats->rx_packets;
5118                         rx_bytes   = cpu_stats->rx_bytes;
5119                         tx_packets = cpu_stats->tx_packets;
5120                         tx_bytes   = cpu_stats->tx_bytes;
5121                 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start));
5122
5123                 stats->rx_packets += rx_packets;
5124                 stats->rx_bytes   += rx_bytes;
5125                 stats->tx_packets += tx_packets;
5126                 stats->tx_bytes   += tx_bytes;
5127         }
5128
5129         stats->rx_errors        = dev->stats.rx_errors;
5130         stats->rx_dropped       = dev->stats.rx_dropped;
5131         stats->tx_dropped       = dev->stats.tx_dropped;
5132 }
5133
5134 static int mvpp2_set_ts_config(struct mvpp2_port *port, struct ifreq *ifr)
5135 {
5136         struct hwtstamp_config config;
5137         void __iomem *ptp;
5138         u32 gcr, int_mask;
5139
5140         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
5141                 return -EFAULT;
5142
5143         if (config.flags)
5144                 return -EINVAL;
5145
5146         if (config.tx_type != HWTSTAMP_TX_OFF &&
5147             config.tx_type != HWTSTAMP_TX_ON)
5148                 return -ERANGE;
5149
5150         ptp = port->priv->iface_base + MVPP22_PTP_BASE(port->gop_id);
5151
5152         int_mask = gcr = 0;
5153         if (config.tx_type != HWTSTAMP_TX_OFF) {
5154                 gcr |= MVPP22_PTP_GCR_TSU_ENABLE | MVPP22_PTP_GCR_TX_RESET;
5155                 int_mask |= MVPP22_PTP_INT_MASK_QUEUE1 |
5156                             MVPP22_PTP_INT_MASK_QUEUE0;
5157         }
5158
5159         /* It seems we must also release the TX reset when enabling the TSU */
5160         if (config.rx_filter != HWTSTAMP_FILTER_NONE)
5161                 gcr |= MVPP22_PTP_GCR_TSU_ENABLE | MVPP22_PTP_GCR_RX_RESET |
5162                        MVPP22_PTP_GCR_TX_RESET;
5163
5164         if (gcr & MVPP22_PTP_GCR_TSU_ENABLE)
5165                 mvpp22_tai_start(port->priv->tai);
5166
5167         if (config.rx_filter != HWTSTAMP_FILTER_NONE) {
5168                 config.rx_filter = HWTSTAMP_FILTER_ALL;
5169                 mvpp2_modify(ptp + MVPP22_PTP_GCR,
5170                              MVPP22_PTP_GCR_RX_RESET |
5171                              MVPP22_PTP_GCR_TX_RESET |
5172                              MVPP22_PTP_GCR_TSU_ENABLE, gcr);
5173                 port->rx_hwtstamp = true;
5174         } else {
5175                 port->rx_hwtstamp = false;
5176                 mvpp2_modify(ptp + MVPP22_PTP_GCR,
5177                              MVPP22_PTP_GCR_RX_RESET |
5178                              MVPP22_PTP_GCR_TX_RESET |
5179                              MVPP22_PTP_GCR_TSU_ENABLE, gcr);
5180         }
5181
5182         mvpp2_modify(ptp + MVPP22_PTP_INT_MASK,
5183                      MVPP22_PTP_INT_MASK_QUEUE1 |
5184                      MVPP22_PTP_INT_MASK_QUEUE0, int_mask);
5185
5186         if (!(gcr & MVPP22_PTP_GCR_TSU_ENABLE))
5187                 mvpp22_tai_stop(port->priv->tai);
5188
5189         port->tx_hwtstamp_type = config.tx_type;
5190
5191         if (copy_to_user(ifr->ifr_data, &config, sizeof(config)))
5192                 return -EFAULT;
5193
5194         return 0;
5195 }
5196
5197 static int mvpp2_get_ts_config(struct mvpp2_port *port, struct ifreq *ifr)
5198 {
5199         struct hwtstamp_config config;
5200
5201         memset(&config, 0, sizeof(config));
5202
5203         config.tx_type = port->tx_hwtstamp_type;
5204         config.rx_filter = port->rx_hwtstamp ?
5205                 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE;
5206
5207         if (copy_to_user(ifr->ifr_data, &config, sizeof(config)))
5208                 return -EFAULT;
5209
5210         return 0;
5211 }
5212
5213 static int mvpp2_ethtool_get_ts_info(struct net_device *dev,
5214                                      struct ethtool_ts_info *info)
5215 {
5216         struct mvpp2_port *port = netdev_priv(dev);
5217
5218         if (!port->hwtstamp)
5219                 return -EOPNOTSUPP;
5220
5221         info->phc_index = mvpp22_tai_ptp_clock_index(port->priv->tai);
5222         info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
5223                                 SOF_TIMESTAMPING_RX_SOFTWARE |
5224                                 SOF_TIMESTAMPING_SOFTWARE |
5225                                 SOF_TIMESTAMPING_TX_HARDWARE |
5226                                 SOF_TIMESTAMPING_RX_HARDWARE |
5227                                 SOF_TIMESTAMPING_RAW_HARDWARE;
5228         info->tx_types = BIT(HWTSTAMP_TX_OFF) |
5229                          BIT(HWTSTAMP_TX_ON);
5230         info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) |
5231                            BIT(HWTSTAMP_FILTER_ALL);
5232
5233         return 0;
5234 }
5235
5236 static int mvpp2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
5237 {
5238         struct mvpp2_port *port = netdev_priv(dev);
5239
5240         switch (cmd) {
5241         case SIOCSHWTSTAMP:
5242                 if (port->hwtstamp)
5243                         return mvpp2_set_ts_config(port, ifr);
5244                 break;
5245
5246         case SIOCGHWTSTAMP:
5247                 if (port->hwtstamp)
5248                         return mvpp2_get_ts_config(port, ifr);
5249                 break;
5250         }
5251
5252         if (!port->phylink)
5253                 return -ENOTSUPP;
5254
5255         return phylink_mii_ioctl(port->phylink, ifr, cmd);
5256 }
5257
5258 static int mvpp2_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid)
5259 {
5260         struct mvpp2_port *port = netdev_priv(dev);
5261         int ret;
5262
5263         ret = mvpp2_prs_vid_entry_add(port, vid);
5264         if (ret)
5265                 netdev_err(dev, "rx-vlan-filter offloading cannot accept more than %d VIDs per port\n",
5266                            MVPP2_PRS_VLAN_FILT_MAX - 1);
5267         return ret;
5268 }
5269
5270 static int mvpp2_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid)
5271 {
5272         struct mvpp2_port *port = netdev_priv(dev);
5273
5274         mvpp2_prs_vid_entry_remove(port, vid);
5275         return 0;
5276 }
5277
5278 static int mvpp2_set_features(struct net_device *dev,
5279                               netdev_features_t features)
5280 {
5281         netdev_features_t changed = dev->features ^ features;
5282         struct mvpp2_port *port = netdev_priv(dev);
5283
5284         if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) {
5285                 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) {
5286                         mvpp2_prs_vid_enable_filtering(port);
5287                 } else {
5288                         /* Invalidate all registered VID filters for this
5289                          * port
5290                          */
5291                         mvpp2_prs_vid_remove_all(port);
5292
5293                         mvpp2_prs_vid_disable_filtering(port);
5294                 }
5295         }
5296
5297         if (changed & NETIF_F_RXHASH) {
5298                 if (features & NETIF_F_RXHASH)
5299                         mvpp22_port_rss_enable(port);
5300                 else
5301                         mvpp22_port_rss_disable(port);
5302         }
5303
5304         return 0;
5305 }
5306
5307 static int mvpp2_xdp_setup(struct mvpp2_port *port, struct netdev_bpf *bpf)
5308 {
5309         struct bpf_prog *prog = bpf->prog, *old_prog;
5310         bool running = netif_running(port->dev);
5311         bool reset = !prog != !port->xdp_prog;
5312
5313         if (port->dev->mtu > ETH_DATA_LEN) {
5314                 NL_SET_ERR_MSG_MOD(bpf->extack, "XDP is not supported with jumbo frames enabled");
5315                 return -EOPNOTSUPP;
5316         }
5317
5318         if (!port->priv->percpu_pools) {
5319                 NL_SET_ERR_MSG_MOD(bpf->extack, "Per CPU Pools required for XDP");
5320                 return -EOPNOTSUPP;
5321         }
5322
5323         if (port->ntxqs < num_possible_cpus() * 2) {
5324                 NL_SET_ERR_MSG_MOD(bpf->extack, "XDP_TX needs two TX queues per CPU");
5325                 return -EOPNOTSUPP;
5326         }
5327
5328         /* device is up and bpf is added/removed, must setup the RX queues */
5329         if (running && reset)
5330                 mvpp2_stop(port->dev);
5331
5332         old_prog = xchg(&port->xdp_prog, prog);
5333         if (old_prog)
5334                 bpf_prog_put(old_prog);
5335
5336         /* bpf is just replaced, RXQ and MTU are already setup */
5337         if (!reset)
5338                 return 0;
5339
5340         /* device was up, restore the link */
5341         if (running)
5342                 mvpp2_open(port->dev);
5343
5344         /* Check Page Pool DMA Direction */
5345         mvpp2_check_pagepool_dma(port);
5346
5347         return 0;
5348 }
5349
5350 static int mvpp2_xdp(struct net_device *dev, struct netdev_bpf *xdp)
5351 {
5352         struct mvpp2_port *port = netdev_priv(dev);
5353
5354         switch (xdp->command) {
5355         case XDP_SETUP_PROG:
5356                 return mvpp2_xdp_setup(port, xdp);
5357         default:
5358                 return -EINVAL;
5359         }
5360 }
5361
5362 /* Ethtool methods */
5363
5364 static int mvpp2_ethtool_nway_reset(struct net_device *dev)
5365 {
5366         struct mvpp2_port *port = netdev_priv(dev);
5367
5368         if (!port->phylink)
5369                 return -ENOTSUPP;
5370
5371         return phylink_ethtool_nway_reset(port->phylink);
5372 }
5373
5374 /* Set interrupt coalescing for ethtools */
5375 static int mvpp2_ethtool_set_coalesce(struct net_device *dev,
5376                                       struct ethtool_coalesce *c)
5377 {
5378         struct mvpp2_port *port = netdev_priv(dev);
5379         int queue;
5380
5381         for (queue = 0; queue < port->nrxqs; queue++) {
5382                 struct mvpp2_rx_queue *rxq = port->rxqs[queue];
5383
5384                 rxq->time_coal = c->rx_coalesce_usecs;
5385                 rxq->pkts_coal = c->rx_max_coalesced_frames;
5386                 mvpp2_rx_pkts_coal_set(port, rxq);
5387                 mvpp2_rx_time_coal_set(port, rxq);
5388         }
5389
5390         if (port->has_tx_irqs) {
5391                 port->tx_time_coal = c->tx_coalesce_usecs;
5392                 mvpp2_tx_time_coal_set(port);
5393         }
5394
5395         for (queue = 0; queue < port->ntxqs; queue++) {
5396                 struct mvpp2_tx_queue *txq = port->txqs[queue];
5397
5398                 txq->done_pkts_coal = c->tx_max_coalesced_frames;
5399
5400                 if (port->has_tx_irqs)
5401                         mvpp2_tx_pkts_coal_set(port, txq);
5402         }
5403
5404         return 0;
5405 }
5406
5407 /* get coalescing for ethtools */
5408 static int mvpp2_ethtool_get_coalesce(struct net_device *dev,
5409                                       struct ethtool_coalesce *c)
5410 {
5411         struct mvpp2_port *port = netdev_priv(dev);
5412
5413         c->rx_coalesce_usecs       = port->rxqs[0]->time_coal;
5414         c->rx_max_coalesced_frames = port->rxqs[0]->pkts_coal;
5415         c->tx_max_coalesced_frames = port->txqs[0]->done_pkts_coal;
5416         c->tx_coalesce_usecs       = port->tx_time_coal;
5417         return 0;
5418 }
5419
5420 static void mvpp2_ethtool_get_drvinfo(struct net_device *dev,
5421                                       struct ethtool_drvinfo *drvinfo)
5422 {
5423         strlcpy(drvinfo->driver, MVPP2_DRIVER_NAME,
5424                 sizeof(drvinfo->driver));
5425         strlcpy(drvinfo->version, MVPP2_DRIVER_VERSION,
5426                 sizeof(drvinfo->version));
5427         strlcpy(drvinfo->bus_info, dev_name(&dev->dev),
5428                 sizeof(drvinfo->bus_info));
5429 }
5430
5431 static void mvpp2_ethtool_get_ringparam(struct net_device *dev,
5432                                         struct ethtool_ringparam *ring)
5433 {
5434         struct mvpp2_port *port = netdev_priv(dev);
5435
5436         ring->rx_max_pending = MVPP2_MAX_RXD_MAX;
5437         ring->tx_max_pending = MVPP2_MAX_TXD_MAX;
5438         ring->rx_pending = port->rx_ring_size;
5439         ring->tx_pending = port->tx_ring_size;
5440 }
5441
5442 static int mvpp2_ethtool_set_ringparam(struct net_device *dev,
5443                                        struct ethtool_ringparam *ring)
5444 {
5445         struct mvpp2_port *port = netdev_priv(dev);
5446         u16 prev_rx_ring_size = port->rx_ring_size;
5447         u16 prev_tx_ring_size = port->tx_ring_size;
5448         int err;
5449
5450         err = mvpp2_check_ringparam_valid(dev, ring);
5451         if (err)
5452                 return err;
5453
5454         if (!netif_running(dev)) {
5455                 port->rx_ring_size = ring->rx_pending;
5456                 port->tx_ring_size = ring->tx_pending;
5457                 return 0;
5458         }
5459
5460         /* The interface is running, so we have to force a
5461          * reallocation of the queues
5462          */
5463         mvpp2_stop_dev(port);
5464         mvpp2_cleanup_rxqs(port);
5465         mvpp2_cleanup_txqs(port);
5466
5467         port->rx_ring_size = ring->rx_pending;
5468         port->tx_ring_size = ring->tx_pending;
5469
5470         err = mvpp2_setup_rxqs(port);
5471         if (err) {
5472                 /* Reallocate Rx queues with the original ring size */
5473                 port->rx_ring_size = prev_rx_ring_size;
5474                 ring->rx_pending = prev_rx_ring_size;
5475                 err = mvpp2_setup_rxqs(port);
5476                 if (err)
5477                         goto err_out;
5478         }
5479         err = mvpp2_setup_txqs(port);
5480         if (err) {
5481                 /* Reallocate Tx queues with the original ring size */
5482                 port->tx_ring_size = prev_tx_ring_size;
5483                 ring->tx_pending = prev_tx_ring_size;
5484                 err = mvpp2_setup_txqs(port);
5485                 if (err)
5486                         goto err_clean_rxqs;
5487         }
5488
5489         mvpp2_start_dev(port);
5490         mvpp2_egress_enable(port);
5491         mvpp2_ingress_enable(port);
5492
5493         return 0;
5494
5495 err_clean_rxqs:
5496         mvpp2_cleanup_rxqs(port);
5497 err_out:
5498         netdev_err(dev, "failed to change ring parameters");
5499         return err;
5500 }
5501
5502 static void mvpp2_ethtool_get_pause_param(struct net_device *dev,
5503                                           struct ethtool_pauseparam *pause)
5504 {
5505         struct mvpp2_port *port = netdev_priv(dev);
5506
5507         if (!port->phylink)
5508                 return;
5509
5510         phylink_ethtool_get_pauseparam(port->phylink, pause);
5511 }
5512
5513 static int mvpp2_ethtool_set_pause_param(struct net_device *dev,
5514                                          struct ethtool_pauseparam *pause)
5515 {
5516         struct mvpp2_port *port = netdev_priv(dev);
5517
5518         if (!port->phylink)
5519                 return -ENOTSUPP;
5520
5521         return phylink_ethtool_set_pauseparam(port->phylink, pause);
5522 }
5523
5524 static int mvpp2_ethtool_get_link_ksettings(struct net_device *dev,
5525                                             struct ethtool_link_ksettings *cmd)
5526 {
5527         struct mvpp2_port *port = netdev_priv(dev);
5528
5529         if (!port->phylink)
5530                 return -ENOTSUPP;
5531
5532         return phylink_ethtool_ksettings_get(port->phylink, cmd);
5533 }
5534
5535 static int mvpp2_ethtool_set_link_ksettings(struct net_device *dev,
5536                                             const struct ethtool_link_ksettings *cmd)
5537 {
5538         struct mvpp2_port *port = netdev_priv(dev);
5539
5540         if (!port->phylink)
5541                 return -ENOTSUPP;
5542
5543         return phylink_ethtool_ksettings_set(port->phylink, cmd);
5544 }
5545
5546 static int mvpp2_ethtool_get_rxnfc(struct net_device *dev,
5547                                    struct ethtool_rxnfc *info, u32 *rules)
5548 {
5549         struct mvpp2_port *port = netdev_priv(dev);
5550         int ret = 0, i, loc = 0;
5551
5552         if (!mvpp22_rss_is_supported(port))
5553                 return -EOPNOTSUPP;
5554
5555         switch (info->cmd) {
5556         case ETHTOOL_GRXFH:
5557                 ret = mvpp2_ethtool_rxfh_get(port, info);
5558                 break;
5559         case ETHTOOL_GRXRINGS:
5560                 info->data = port->nrxqs;
5561                 break;
5562         case ETHTOOL_GRXCLSRLCNT:
5563                 info->rule_cnt = port->n_rfs_rules;
5564                 break;
5565         case ETHTOOL_GRXCLSRULE:
5566                 ret = mvpp2_ethtool_cls_rule_get(port, info);
5567                 break;
5568         case ETHTOOL_GRXCLSRLALL:
5569                 for (i = 0; i < MVPP2_N_RFS_ENTRIES_PER_FLOW; i++) {
5570                         if (port->rfs_rules[i])
5571                                 rules[loc++] = i;
5572                 }
5573                 break;
5574         default:
5575                 return -ENOTSUPP;
5576         }
5577
5578         return ret;
5579 }
5580
5581 static int mvpp2_ethtool_set_rxnfc(struct net_device *dev,
5582                                    struct ethtool_rxnfc *info)
5583 {
5584         struct mvpp2_port *port = netdev_priv(dev);
5585         int ret = 0;
5586
5587         if (!mvpp22_rss_is_supported(port))
5588                 return -EOPNOTSUPP;
5589
5590         switch (info->cmd) {
5591         case ETHTOOL_SRXFH:
5592                 ret = mvpp2_ethtool_rxfh_set(port, info);
5593                 break;
5594         case ETHTOOL_SRXCLSRLINS:
5595                 ret = mvpp2_ethtool_cls_rule_ins(port, info);
5596                 break;
5597         case ETHTOOL_SRXCLSRLDEL:
5598                 ret = mvpp2_ethtool_cls_rule_del(port, info);
5599                 break;
5600         default:
5601                 return -EOPNOTSUPP;
5602         }
5603         return ret;
5604 }
5605
5606 static u32 mvpp2_ethtool_get_rxfh_indir_size(struct net_device *dev)
5607 {
5608         struct mvpp2_port *port = netdev_priv(dev);
5609
5610         return mvpp22_rss_is_supported(port) ? MVPP22_RSS_TABLE_ENTRIES : 0;
5611 }
5612
5613 static int mvpp2_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
5614                                   u8 *hfunc)
5615 {
5616         struct mvpp2_port *port = netdev_priv(dev);
5617         int ret = 0;
5618
5619         if (!mvpp22_rss_is_supported(port))
5620                 return -EOPNOTSUPP;
5621
5622         if (indir)
5623                 ret = mvpp22_port_rss_ctx_indir_get(port, 0, indir);
5624
5625         if (hfunc)
5626                 *hfunc = ETH_RSS_HASH_CRC32;
5627
5628         return ret;
5629 }
5630
5631 static int mvpp2_ethtool_set_rxfh(struct net_device *dev, const u32 *indir,
5632                                   const u8 *key, const u8 hfunc)
5633 {
5634         struct mvpp2_port *port = netdev_priv(dev);
5635         int ret = 0;
5636
5637         if (!mvpp22_rss_is_supported(port))
5638                 return -EOPNOTSUPP;
5639
5640         if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_CRC32)
5641                 return -EOPNOTSUPP;
5642
5643         if (key)
5644                 return -EOPNOTSUPP;
5645
5646         if (indir)
5647                 ret = mvpp22_port_rss_ctx_indir_set(port, 0, indir);
5648
5649         return ret;
5650 }
5651
5652 static int mvpp2_ethtool_get_rxfh_context(struct net_device *dev, u32 *indir,
5653                                           u8 *key, u8 *hfunc, u32 rss_context)
5654 {
5655         struct mvpp2_port *port = netdev_priv(dev);
5656         int ret = 0;
5657
5658         if (!mvpp22_rss_is_supported(port))
5659                 return -EOPNOTSUPP;
5660         if (rss_context >= MVPP22_N_RSS_TABLES)
5661                 return -EINVAL;
5662
5663         if (hfunc)
5664                 *hfunc = ETH_RSS_HASH_CRC32;
5665
5666         if (indir)
5667                 ret = mvpp22_port_rss_ctx_indir_get(port, rss_context, indir);
5668
5669         return ret;
5670 }
5671
5672 static int mvpp2_ethtool_set_rxfh_context(struct net_device *dev,
5673                                           const u32 *indir, const u8 *key,
5674                                           const u8 hfunc, u32 *rss_context,
5675                                           bool delete)
5676 {
5677         struct mvpp2_port *port = netdev_priv(dev);
5678         int ret;
5679
5680         if (!mvpp22_rss_is_supported(port))
5681                 return -EOPNOTSUPP;
5682
5683         if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_CRC32)
5684                 return -EOPNOTSUPP;
5685
5686         if (key)
5687                 return -EOPNOTSUPP;
5688
5689         if (delete)
5690                 return mvpp22_port_rss_ctx_delete(port, *rss_context);
5691
5692         if (*rss_context == ETH_RXFH_CONTEXT_ALLOC) {
5693                 ret = mvpp22_port_rss_ctx_create(port, rss_context);
5694                 if (ret)
5695                         return ret;
5696         }
5697
5698         return mvpp22_port_rss_ctx_indir_set(port, *rss_context, indir);
5699 }
5700 /* Device ops */
5701
5702 static const struct net_device_ops mvpp2_netdev_ops = {
5703         .ndo_open               = mvpp2_open,
5704         .ndo_stop               = mvpp2_stop,
5705         .ndo_start_xmit         = mvpp2_tx,
5706         .ndo_set_rx_mode        = mvpp2_set_rx_mode,
5707         .ndo_set_mac_address    = mvpp2_set_mac_address,
5708         .ndo_change_mtu         = mvpp2_change_mtu,
5709         .ndo_get_stats64        = mvpp2_get_stats64,
5710         .ndo_do_ioctl           = mvpp2_ioctl,
5711         .ndo_vlan_rx_add_vid    = mvpp2_vlan_rx_add_vid,
5712         .ndo_vlan_rx_kill_vid   = mvpp2_vlan_rx_kill_vid,
5713         .ndo_set_features       = mvpp2_set_features,
5714         .ndo_bpf                = mvpp2_xdp,
5715         .ndo_xdp_xmit           = mvpp2_xdp_xmit,
5716 };
5717
5718 static const struct ethtool_ops mvpp2_eth_tool_ops = {
5719         .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
5720                                      ETHTOOL_COALESCE_MAX_FRAMES,
5721         .nway_reset             = mvpp2_ethtool_nway_reset,
5722         .get_link               = ethtool_op_get_link,
5723         .get_ts_info            = mvpp2_ethtool_get_ts_info,
5724         .set_coalesce           = mvpp2_ethtool_set_coalesce,
5725         .get_coalesce           = mvpp2_ethtool_get_coalesce,
5726         .get_drvinfo            = mvpp2_ethtool_get_drvinfo,
5727         .get_ringparam          = mvpp2_ethtool_get_ringparam,
5728         .set_ringparam          = mvpp2_ethtool_set_ringparam,
5729         .get_strings            = mvpp2_ethtool_get_strings,
5730         .get_ethtool_stats      = mvpp2_ethtool_get_stats,
5731         .get_sset_count         = mvpp2_ethtool_get_sset_count,
5732         .get_pauseparam         = mvpp2_ethtool_get_pause_param,
5733         .set_pauseparam         = mvpp2_ethtool_set_pause_param,
5734         .get_link_ksettings     = mvpp2_ethtool_get_link_ksettings,
5735         .set_link_ksettings     = mvpp2_ethtool_set_link_ksettings,
5736         .get_rxnfc              = mvpp2_ethtool_get_rxnfc,
5737         .set_rxnfc              = mvpp2_ethtool_set_rxnfc,
5738         .get_rxfh_indir_size    = mvpp2_ethtool_get_rxfh_indir_size,
5739         .get_rxfh               = mvpp2_ethtool_get_rxfh,
5740         .set_rxfh               = mvpp2_ethtool_set_rxfh,
5741         .get_rxfh_context       = mvpp2_ethtool_get_rxfh_context,
5742         .set_rxfh_context       = mvpp2_ethtool_set_rxfh_context,
5743 };
5744
5745 /* Used for PPv2.1, or PPv2.2 with the old Device Tree binding that
5746  * had a single IRQ defined per-port.
5747  */
5748 static int mvpp2_simple_queue_vectors_init(struct mvpp2_port *port,
5749                                            struct device_node *port_node)
5750 {
5751         struct mvpp2_queue_vector *v = &port->qvecs[0];
5752
5753         v->first_rxq = 0;
5754         v->nrxqs = port->nrxqs;
5755         v->type = MVPP2_QUEUE_VECTOR_SHARED;
5756         v->sw_thread_id = 0;
5757         v->sw_thread_mask = *cpumask_bits(cpu_online_mask);
5758         v->port = port;
5759         v->irq = irq_of_parse_and_map(port_node, 0);
5760         if (v->irq <= 0)
5761                 return -EINVAL;
5762         netif_napi_add(port->dev, &v->napi, mvpp2_poll,
5763                        NAPI_POLL_WEIGHT);
5764
5765         port->nqvecs = 1;
5766
5767         return 0;
5768 }
5769
5770 static int mvpp2_multi_queue_vectors_init(struct mvpp2_port *port,
5771                                           struct device_node *port_node)
5772 {
5773         struct mvpp2 *priv = port->priv;
5774         struct mvpp2_queue_vector *v;
5775         int i, ret;
5776
5777         switch (queue_mode) {
5778         case MVPP2_QDIST_SINGLE_MODE:
5779                 port->nqvecs = priv->nthreads + 1;
5780                 break;
5781         case MVPP2_QDIST_MULTI_MODE:
5782                 port->nqvecs = priv->nthreads;
5783                 break;
5784         }
5785
5786         for (i = 0; i < port->nqvecs; i++) {
5787                 char irqname[16];
5788
5789                 v = port->qvecs + i;
5790
5791                 v->port = port;
5792                 v->type = MVPP2_QUEUE_VECTOR_PRIVATE;
5793                 v->sw_thread_id = i;
5794                 v->sw_thread_mask = BIT(i);
5795
5796                 if (port->flags & MVPP2_F_DT_COMPAT)
5797                         snprintf(irqname, sizeof(irqname), "tx-cpu%d", i);
5798                 else
5799                         snprintf(irqname, sizeof(irqname), "hif%d", i);
5800
5801                 if (queue_mode == MVPP2_QDIST_MULTI_MODE) {
5802                         v->first_rxq = i;
5803                         v->nrxqs = 1;
5804                 } else if (queue_mode == MVPP2_QDIST_SINGLE_MODE &&
5805                            i == (port->nqvecs - 1)) {
5806                         v->first_rxq = 0;
5807                         v->nrxqs = port->nrxqs;
5808                         v->type = MVPP2_QUEUE_VECTOR_SHARED;
5809
5810                         if (port->flags & MVPP2_F_DT_COMPAT)
5811                                 strncpy(irqname, "rx-shared", sizeof(irqname));
5812                 }
5813
5814                 if (port_node)
5815                         v->irq = of_irq_get_byname(port_node, irqname);
5816                 else
5817                         v->irq = fwnode_irq_get(port->fwnode, i);
5818                 if (v->irq <= 0) {
5819                         ret = -EINVAL;
5820                         goto err;
5821                 }
5822
5823                 netif_napi_add(port->dev, &v->napi, mvpp2_poll,
5824                                NAPI_POLL_WEIGHT);
5825         }
5826
5827         return 0;
5828
5829 err:
5830         for (i = 0; i < port->nqvecs; i++)
5831                 irq_dispose_mapping(port->qvecs[i].irq);
5832         return ret;
5833 }
5834
5835 static int mvpp2_queue_vectors_init(struct mvpp2_port *port,
5836                                     struct device_node *port_node)
5837 {
5838         if (port->has_tx_irqs)
5839                 return mvpp2_multi_queue_vectors_init(port, port_node);
5840         else
5841                 return mvpp2_simple_queue_vectors_init(port, port_node);
5842 }
5843
5844 static void mvpp2_queue_vectors_deinit(struct mvpp2_port *port)
5845 {
5846         int i;
5847
5848         for (i = 0; i < port->nqvecs; i++)
5849                 irq_dispose_mapping(port->qvecs[i].irq);
5850 }
5851
5852 /* Configure Rx queue group interrupt for this port */
5853 static void mvpp2_rx_irqs_setup(struct mvpp2_port *port)
5854 {
5855         struct mvpp2 *priv = port->priv;
5856         u32 val;
5857         int i;
5858
5859         if (priv->hw_version == MVPP21) {
5860                 mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(port->id),
5861                             port->nrxqs);
5862                 return;
5863         }
5864
5865         /* Handle the more complicated PPv2.2 and PPv2.3 case */
5866         for (i = 0; i < port->nqvecs; i++) {
5867                 struct mvpp2_queue_vector *qv = port->qvecs + i;
5868
5869                 if (!qv->nrxqs)
5870                         continue;
5871
5872                 val = qv->sw_thread_id;
5873                 val |= port->id << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET;
5874                 mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val);
5875
5876                 val = qv->first_rxq;
5877                 val |= qv->nrxqs << MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET;
5878                 mvpp2_write(priv, MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val);
5879         }
5880 }
5881
5882 /* Initialize port HW */
5883 static int mvpp2_port_init(struct mvpp2_port *port)
5884 {
5885         struct device *dev = port->dev->dev.parent;
5886         struct mvpp2 *priv = port->priv;
5887         struct mvpp2_txq_pcpu *txq_pcpu;
5888         unsigned int thread;
5889         int queue, err, val;
5890
5891         /* Checks for hardware constraints */
5892         if (port->first_rxq + port->nrxqs >
5893             MVPP2_MAX_PORTS * priv->max_port_rxqs)
5894                 return -EINVAL;
5895
5896         if (port->nrxqs > priv->max_port_rxqs || port->ntxqs > MVPP2_MAX_TXQ)
5897                 return -EINVAL;
5898
5899         /* Disable port */
5900         mvpp2_egress_disable(port);
5901         mvpp2_port_disable(port);
5902
5903         if (mvpp2_is_xlg(port->phy_interface)) {
5904                 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
5905                 val &= ~MVPP22_XLG_CTRL0_FORCE_LINK_PASS;
5906                 val |= MVPP22_XLG_CTRL0_FORCE_LINK_DOWN;
5907                 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
5908         } else {
5909                 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
5910                 val &= ~MVPP2_GMAC_FORCE_LINK_PASS;
5911                 val |= MVPP2_GMAC_FORCE_LINK_DOWN;
5912                 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
5913         }
5914
5915         port->tx_time_coal = MVPP2_TXDONE_COAL_USEC;
5916
5917         port->txqs = devm_kcalloc(dev, port->ntxqs, sizeof(*port->txqs),
5918                                   GFP_KERNEL);
5919         if (!port->txqs)
5920                 return -ENOMEM;
5921
5922         /* Associate physical Tx queues to this port and initialize.
5923          * The mapping is predefined.
5924          */
5925         for (queue = 0; queue < port->ntxqs; queue++) {
5926                 int queue_phy_id = mvpp2_txq_phys(port->id, queue);
5927                 struct mvpp2_tx_queue *txq;
5928
5929                 txq = devm_kzalloc(dev, sizeof(*txq), GFP_KERNEL);
5930                 if (!txq) {
5931                         err = -ENOMEM;
5932                         goto err_free_percpu;
5933                 }
5934
5935                 txq->pcpu = alloc_percpu(struct mvpp2_txq_pcpu);
5936                 if (!txq->pcpu) {
5937                         err = -ENOMEM;
5938                         goto err_free_percpu;
5939                 }
5940
5941                 txq->id = queue_phy_id;
5942                 txq->log_id = queue;
5943                 txq->done_pkts_coal = MVPP2_TXDONE_COAL_PKTS_THRESH;
5944                 for (thread = 0; thread < priv->nthreads; thread++) {
5945                         txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
5946                         txq_pcpu->thread = thread;
5947                 }
5948
5949                 port->txqs[queue] = txq;
5950         }
5951
5952         port->rxqs = devm_kcalloc(dev, port->nrxqs, sizeof(*port->rxqs),
5953                                   GFP_KERNEL);
5954         if (!port->rxqs) {
5955                 err = -ENOMEM;
5956                 goto err_free_percpu;
5957         }
5958
5959         /* Allocate and initialize Rx queue for this port */
5960         for (queue = 0; queue < port->nrxqs; queue++) {
5961                 struct mvpp2_rx_queue *rxq;
5962
5963                 /* Map physical Rx queue to port's logical Rx queue */
5964                 rxq = devm_kzalloc(dev, sizeof(*rxq), GFP_KERNEL);
5965                 if (!rxq) {
5966                         err = -ENOMEM;
5967                         goto err_free_percpu;
5968                 }
5969                 /* Map this Rx queue to a physical queue */
5970                 rxq->id = port->first_rxq + queue;
5971                 rxq->port = port->id;
5972                 rxq->logic_rxq = queue;
5973
5974                 port->rxqs[queue] = rxq;
5975         }
5976
5977         mvpp2_rx_irqs_setup(port);
5978
5979         /* Create Rx descriptor rings */
5980         for (queue = 0; queue < port->nrxqs; queue++) {
5981                 struct mvpp2_rx_queue *rxq = port->rxqs[queue];
5982
5983                 rxq->size = port->rx_ring_size;
5984                 rxq->pkts_coal = MVPP2_RX_COAL_PKTS;
5985                 rxq->time_coal = MVPP2_RX_COAL_USEC;
5986         }
5987
5988         mvpp2_ingress_disable(port);
5989
5990         /* Port default configuration */
5991         mvpp2_defaults_set(port);
5992
5993         /* Port's classifier configuration */
5994         mvpp2_cls_oversize_rxq_set(port);
5995         mvpp2_cls_port_config(port);
5996
5997         if (mvpp22_rss_is_supported(port))
5998                 mvpp22_port_rss_init(port);
5999
6000         /* Provide an initial Rx packet size */
6001         port->pkt_size = MVPP2_RX_PKT_SIZE(port->dev->mtu);
6002
6003         /* Initialize pools for swf */
6004         err = mvpp2_swf_bm_pool_init(port);
6005         if (err)
6006                 goto err_free_percpu;
6007
6008         /* Clear all port stats */
6009         mvpp2_read_stats(port);
6010         memset(port->ethtool_stats, 0,
6011                MVPP2_N_ETHTOOL_STATS(port->ntxqs, port->nrxqs) * sizeof(u64));
6012
6013         return 0;
6014
6015 err_free_percpu:
6016         for (queue = 0; queue < port->ntxqs; queue++) {
6017                 if (!port->txqs[queue])
6018                         continue;
6019                 free_percpu(port->txqs[queue]->pcpu);
6020         }
6021         return err;
6022 }
6023
6024 static bool mvpp22_port_has_legacy_tx_irqs(struct device_node *port_node,
6025                                            unsigned long *flags)
6026 {
6027         char *irqs[5] = { "rx-shared", "tx-cpu0", "tx-cpu1", "tx-cpu2",
6028                           "tx-cpu3" };
6029         int i;
6030
6031         for (i = 0; i < 5; i++)
6032                 if (of_property_match_string(port_node, "interrupt-names",
6033                                              irqs[i]) < 0)
6034                         return false;
6035
6036         *flags |= MVPP2_F_DT_COMPAT;
6037         return true;
6038 }
6039
6040 /* Checks if the port dt description has the required Tx interrupts:
6041  * - PPv2.1: there are no such interrupts.
6042  * - PPv2.2 and PPv2.3:
6043  *   - The old DTs have: "rx-shared", "tx-cpuX" with X in [0...3]
6044  *   - The new ones have: "hifX" with X in [0..8]
6045  *
6046  * All those variants are supported to keep the backward compatibility.
6047  */
6048 static bool mvpp2_port_has_irqs(struct mvpp2 *priv,
6049                                 struct device_node *port_node,
6050                                 unsigned long *flags)
6051 {
6052         char name[5];
6053         int i;
6054
6055         /* ACPI */
6056         if (!port_node)
6057                 return true;
6058
6059         if (priv->hw_version == MVPP21)
6060                 return false;
6061
6062         if (mvpp22_port_has_legacy_tx_irqs(port_node, flags))
6063                 return true;
6064
6065         for (i = 0; i < MVPP2_MAX_THREADS; i++) {
6066                 snprintf(name, 5, "hif%d", i);
6067                 if (of_property_match_string(port_node, "interrupt-names",
6068                                              name) < 0)
6069                         return false;
6070         }
6071
6072         return true;
6073 }
6074
6075 static void mvpp2_port_copy_mac_addr(struct net_device *dev, struct mvpp2 *priv,
6076                                      struct fwnode_handle *fwnode,
6077                                      char **mac_from)
6078 {
6079         struct mvpp2_port *port = netdev_priv(dev);
6080         char hw_mac_addr[ETH_ALEN] = {0};
6081         char fw_mac_addr[ETH_ALEN];
6082
6083         if (fwnode_get_mac_address(fwnode, fw_mac_addr, ETH_ALEN)) {
6084                 *mac_from = "firmware node";
6085                 ether_addr_copy(dev->dev_addr, fw_mac_addr);
6086                 return;
6087         }
6088
6089         if (priv->hw_version == MVPP21) {
6090                 mvpp21_get_mac_address(port, hw_mac_addr);
6091                 if (is_valid_ether_addr(hw_mac_addr)) {
6092                         *mac_from = "hardware";
6093                         ether_addr_copy(dev->dev_addr, hw_mac_addr);
6094                         return;
6095                 }
6096         }
6097
6098         *mac_from = "random";
6099         eth_hw_addr_random(dev);
6100 }
6101
6102 static struct mvpp2_port *mvpp2_phylink_to_port(struct phylink_config *config)
6103 {
6104         return container_of(config, struct mvpp2_port, phylink_config);
6105 }
6106
6107 static struct mvpp2_port *mvpp2_pcs_to_port(struct phylink_pcs *pcs)
6108 {
6109         return container_of(pcs, struct mvpp2_port, phylink_pcs);
6110 }
6111
6112 static void mvpp2_xlg_pcs_get_state(struct phylink_pcs *pcs,
6113                                     struct phylink_link_state *state)
6114 {
6115         struct mvpp2_port *port = mvpp2_pcs_to_port(pcs);
6116         u32 val;
6117
6118         state->speed = SPEED_10000;
6119         state->duplex = 1;
6120         state->an_complete = 1;
6121
6122         val = readl(port->base + MVPP22_XLG_STATUS);
6123         state->link = !!(val & MVPP22_XLG_STATUS_LINK_UP);
6124
6125         state->pause = 0;
6126         val = readl(port->base + MVPP22_XLG_CTRL0_REG);
6127         if (val & MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN)
6128                 state->pause |= MLO_PAUSE_TX;
6129         if (val & MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN)
6130                 state->pause |= MLO_PAUSE_RX;
6131 }
6132
6133 static int mvpp2_xlg_pcs_config(struct phylink_pcs *pcs,
6134                                 unsigned int mode,
6135                                 phy_interface_t interface,
6136                                 const unsigned long *advertising,
6137                                 bool permit_pause_to_mac)
6138 {
6139         return 0;
6140 }
6141
6142 static const struct phylink_pcs_ops mvpp2_phylink_xlg_pcs_ops = {
6143         .pcs_get_state = mvpp2_xlg_pcs_get_state,
6144         .pcs_config = mvpp2_xlg_pcs_config,
6145 };
6146
6147 static void mvpp2_gmac_pcs_get_state(struct phylink_pcs *pcs,
6148                                      struct phylink_link_state *state)
6149 {
6150         struct mvpp2_port *port = mvpp2_pcs_to_port(pcs);
6151         u32 val;
6152
6153         val = readl(port->base + MVPP2_GMAC_STATUS0);
6154
6155         state->an_complete = !!(val & MVPP2_GMAC_STATUS0_AN_COMPLETE);
6156         state->link = !!(val & MVPP2_GMAC_STATUS0_LINK_UP);
6157         state->duplex = !!(val & MVPP2_GMAC_STATUS0_FULL_DUPLEX);
6158
6159         switch (port->phy_interface) {
6160         case PHY_INTERFACE_MODE_1000BASEX:
6161                 state->speed = SPEED_1000;
6162                 break;
6163         case PHY_INTERFACE_MODE_2500BASEX:
6164                 state->speed = SPEED_2500;
6165                 break;
6166         default:
6167                 if (val & MVPP2_GMAC_STATUS0_GMII_SPEED)
6168                         state->speed = SPEED_1000;
6169                 else if (val & MVPP2_GMAC_STATUS0_MII_SPEED)
6170                         state->speed = SPEED_100;
6171                 else
6172                         state->speed = SPEED_10;
6173         }
6174
6175         state->pause = 0;
6176         if (val & MVPP2_GMAC_STATUS0_RX_PAUSE)
6177                 state->pause |= MLO_PAUSE_RX;
6178         if (val & MVPP2_GMAC_STATUS0_TX_PAUSE)
6179                 state->pause |= MLO_PAUSE_TX;
6180 }
6181
6182 static int mvpp2_gmac_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
6183                                  phy_interface_t interface,
6184                                  const unsigned long *advertising,
6185                                  bool permit_pause_to_mac)
6186 {
6187         struct mvpp2_port *port = mvpp2_pcs_to_port(pcs);
6188         u32 mask, val, an, old_an, changed;
6189
6190         mask = MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS |
6191                MVPP2_GMAC_IN_BAND_AUTONEG |
6192                MVPP2_GMAC_AN_SPEED_EN |
6193                MVPP2_GMAC_FLOW_CTRL_AUTONEG |
6194                MVPP2_GMAC_AN_DUPLEX_EN;
6195
6196         if (phylink_autoneg_inband(mode)) {
6197                 mask |= MVPP2_GMAC_CONFIG_MII_SPEED |
6198                         MVPP2_GMAC_CONFIG_GMII_SPEED |
6199                         MVPP2_GMAC_CONFIG_FULL_DUPLEX;
6200                 val = MVPP2_GMAC_IN_BAND_AUTONEG;
6201
6202                 if (interface == PHY_INTERFACE_MODE_SGMII) {
6203                         /* SGMII mode receives the speed and duplex from PHY */
6204                         val |= MVPP2_GMAC_AN_SPEED_EN |
6205                                MVPP2_GMAC_AN_DUPLEX_EN;
6206                 } else {
6207                         /* 802.3z mode has fixed speed and duplex */
6208                         val |= MVPP2_GMAC_CONFIG_GMII_SPEED |
6209                                MVPP2_GMAC_CONFIG_FULL_DUPLEX;
6210
6211                         /* The FLOW_CTRL_AUTONEG bit selects either the hardware
6212                          * automatically or the bits in MVPP22_GMAC_CTRL_4_REG
6213                          * manually controls the GMAC pause modes.
6214                          */
6215                         if (permit_pause_to_mac)
6216                                 val |= MVPP2_GMAC_FLOW_CTRL_AUTONEG;
6217
6218                         /* Configure advertisement bits */
6219                         mask |= MVPP2_GMAC_FC_ADV_EN | MVPP2_GMAC_FC_ADV_ASM_EN;
6220                         if (phylink_test(advertising, Pause))
6221                                 val |= MVPP2_GMAC_FC_ADV_EN;
6222                         if (phylink_test(advertising, Asym_Pause))
6223                                 val |= MVPP2_GMAC_FC_ADV_ASM_EN;
6224                 }
6225         } else {
6226                 val = 0;
6227         }
6228
6229         old_an = an = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
6230         an = (an & ~mask) | val;
6231         changed = an ^ old_an;
6232         if (changed)
6233                 writel(an, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
6234
6235         /* We are only interested in the advertisement bits changing */
6236         return changed & (MVPP2_GMAC_FC_ADV_EN | MVPP2_GMAC_FC_ADV_ASM_EN);
6237 }
6238
6239 static void mvpp2_gmac_pcs_an_restart(struct phylink_pcs *pcs)
6240 {
6241         struct mvpp2_port *port = mvpp2_pcs_to_port(pcs);
6242         u32 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
6243
6244         writel(val | MVPP2_GMAC_IN_BAND_RESTART_AN,
6245                port->base + MVPP2_GMAC_AUTONEG_CONFIG);
6246         writel(val & ~MVPP2_GMAC_IN_BAND_RESTART_AN,
6247                port->base + MVPP2_GMAC_AUTONEG_CONFIG);
6248 }
6249
6250 static const struct phylink_pcs_ops mvpp2_phylink_gmac_pcs_ops = {
6251         .pcs_get_state = mvpp2_gmac_pcs_get_state,
6252         .pcs_config = mvpp2_gmac_pcs_config,
6253         .pcs_an_restart = mvpp2_gmac_pcs_an_restart,
6254 };
6255
6256 static void mvpp2_phylink_validate(struct phylink_config *config,
6257                                    unsigned long *supported,
6258                                    struct phylink_link_state *state)
6259 {
6260         struct mvpp2_port *port = mvpp2_phylink_to_port(config);
6261         __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
6262
6263         /* Invalid combinations */
6264         switch (state->interface) {
6265         case PHY_INTERFACE_MODE_10GBASER:
6266         case PHY_INTERFACE_MODE_XAUI:
6267                 if (!mvpp2_port_supports_xlg(port))
6268                         goto empty_set;
6269                 break;
6270         case PHY_INTERFACE_MODE_RGMII:
6271         case PHY_INTERFACE_MODE_RGMII_ID:
6272         case PHY_INTERFACE_MODE_RGMII_RXID:
6273         case PHY_INTERFACE_MODE_RGMII_TXID:
6274                 if (!mvpp2_port_supports_rgmii(port))
6275                         goto empty_set;
6276                 break;
6277         default:
6278                 break;
6279         }
6280
6281         phylink_set(mask, Autoneg);
6282         phylink_set_port_modes(mask);
6283
6284         if (port->priv->global_tx_fc) {
6285                 phylink_set(mask, Pause);
6286                 phylink_set(mask, Asym_Pause);
6287         }
6288
6289         switch (state->interface) {
6290         case PHY_INTERFACE_MODE_10GBASER:
6291         case PHY_INTERFACE_MODE_XAUI:
6292         case PHY_INTERFACE_MODE_NA:
6293                 if (mvpp2_port_supports_xlg(port)) {
6294                         phylink_set(mask, 10000baseT_Full);
6295                         phylink_set(mask, 10000baseCR_Full);
6296                         phylink_set(mask, 10000baseSR_Full);
6297                         phylink_set(mask, 10000baseLR_Full);
6298                         phylink_set(mask, 10000baseLRM_Full);
6299                         phylink_set(mask, 10000baseER_Full);
6300                         phylink_set(mask, 10000baseKR_Full);
6301                 }
6302                 if (state->interface != PHY_INTERFACE_MODE_NA)
6303                         break;
6304                 fallthrough;
6305         case PHY_INTERFACE_MODE_RGMII:
6306         case PHY_INTERFACE_MODE_RGMII_ID:
6307         case PHY_INTERFACE_MODE_RGMII_RXID:
6308         case PHY_INTERFACE_MODE_RGMII_TXID:
6309         case PHY_INTERFACE_MODE_SGMII:
6310                 phylink_set(mask, 10baseT_Half);
6311                 phylink_set(mask, 10baseT_Full);
6312                 phylink_set(mask, 100baseT_Half);
6313                 phylink_set(mask, 100baseT_Full);
6314                 phylink_set(mask, 1000baseT_Full);
6315                 phylink_set(mask, 1000baseX_Full);
6316                 if (state->interface != PHY_INTERFACE_MODE_NA)
6317                         break;
6318                 fallthrough;
6319         case PHY_INTERFACE_MODE_1000BASEX:
6320         case PHY_INTERFACE_MODE_2500BASEX:
6321                 if (port->comphy ||
6322                     state->interface != PHY_INTERFACE_MODE_2500BASEX) {
6323                         phylink_set(mask, 1000baseT_Full);
6324                         phylink_set(mask, 1000baseX_Full);
6325                 }
6326                 if (port->comphy ||
6327                     state->interface == PHY_INTERFACE_MODE_2500BASEX) {
6328                         phylink_set(mask, 2500baseT_Full);
6329                         phylink_set(mask, 2500baseX_Full);
6330                 }
6331                 break;
6332         default:
6333                 goto empty_set;
6334         }
6335
6336         bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
6337         bitmap_and(state->advertising, state->advertising, mask,
6338                    __ETHTOOL_LINK_MODE_MASK_NBITS);
6339
6340         phylink_helper_basex_speed(state);
6341         return;
6342
6343 empty_set:
6344         bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
6345 }
6346
6347 static void mvpp2_xlg_config(struct mvpp2_port *port, unsigned int mode,
6348                              const struct phylink_link_state *state)
6349 {
6350         u32 val;
6351
6352         mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG,
6353                      MVPP22_XLG_CTRL0_MAC_RESET_DIS,
6354                      MVPP22_XLG_CTRL0_MAC_RESET_DIS);
6355         mvpp2_modify(port->base + MVPP22_XLG_CTRL4_REG,
6356                      MVPP22_XLG_CTRL4_MACMODSELECT_GMAC |
6357                      MVPP22_XLG_CTRL4_EN_IDLE_CHECK |
6358                      MVPP22_XLG_CTRL4_FWD_FC | MVPP22_XLG_CTRL4_FWD_PFC,
6359                      MVPP22_XLG_CTRL4_FWD_FC | MVPP22_XLG_CTRL4_FWD_PFC);
6360
6361         /* Wait for reset to deassert */
6362         do {
6363                 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
6364         } while (!(val & MVPP22_XLG_CTRL0_MAC_RESET_DIS));
6365 }
6366
6367 static void mvpp2_gmac_config(struct mvpp2_port *port, unsigned int mode,
6368                               const struct phylink_link_state *state)
6369 {
6370         u32 old_ctrl0, ctrl0;
6371         u32 old_ctrl2, ctrl2;
6372         u32 old_ctrl4, ctrl4;
6373
6374         old_ctrl0 = ctrl0 = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
6375         old_ctrl2 = ctrl2 = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
6376         old_ctrl4 = ctrl4 = readl(port->base + MVPP22_GMAC_CTRL_4_REG);
6377
6378         ctrl0 &= ~MVPP2_GMAC_PORT_TYPE_MASK;
6379         ctrl2 &= ~(MVPP2_GMAC_INBAND_AN_MASK | MVPP2_GMAC_PCS_ENABLE_MASK | MVPP2_GMAC_FLOW_CTRL_MASK);
6380
6381         /* Configure port type */
6382         if (phy_interface_mode_is_8023z(state->interface)) {
6383                 ctrl2 |= MVPP2_GMAC_PCS_ENABLE_MASK;
6384                 ctrl4 &= ~MVPP22_CTRL4_EXT_PIN_GMII_SEL;
6385                 ctrl4 |= MVPP22_CTRL4_SYNC_BYPASS_DIS |
6386                          MVPP22_CTRL4_DP_CLK_SEL |
6387                          MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE;
6388         } else if (state->interface == PHY_INTERFACE_MODE_SGMII) {
6389                 ctrl2 |= MVPP2_GMAC_PCS_ENABLE_MASK | MVPP2_GMAC_INBAND_AN_MASK;
6390                 ctrl4 &= ~MVPP22_CTRL4_EXT_PIN_GMII_SEL;
6391                 ctrl4 |= MVPP22_CTRL4_SYNC_BYPASS_DIS |
6392                          MVPP22_CTRL4_DP_CLK_SEL |
6393                          MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE;
6394         } else if (phy_interface_mode_is_rgmii(state->interface)) {
6395                 ctrl4 &= ~MVPP22_CTRL4_DP_CLK_SEL;
6396                 ctrl4 |= MVPP22_CTRL4_EXT_PIN_GMII_SEL |
6397                          MVPP22_CTRL4_SYNC_BYPASS_DIS |
6398                          MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE;
6399         }
6400
6401         /* Configure negotiation style */
6402         if (!phylink_autoneg_inband(mode)) {
6403                 /* Phy or fixed speed - no in-band AN, nothing to do, leave the
6404                  * configured speed, duplex and flow control as-is.
6405                  */
6406         } else if (state->interface == PHY_INTERFACE_MODE_SGMII) {
6407                 /* SGMII in-band mode receives the speed and duplex from
6408                  * the PHY. Flow control information is not received. */
6409         } else if (phy_interface_mode_is_8023z(state->interface)) {
6410                 /* 1000BaseX and 2500BaseX ports cannot negotiate speed nor can
6411                  * they negotiate duplex: they are always operating with a fixed
6412                  * speed of 1000/2500Mbps in full duplex, so force 1000/2500
6413                  * speed and full duplex here.
6414                  */
6415                 ctrl0 |= MVPP2_GMAC_PORT_TYPE_MASK;
6416         }
6417
6418         if (old_ctrl0 != ctrl0)
6419                 writel(ctrl0, port->base + MVPP2_GMAC_CTRL_0_REG);
6420         if (old_ctrl2 != ctrl2)
6421                 writel(ctrl2, port->base + MVPP2_GMAC_CTRL_2_REG);
6422         if (old_ctrl4 != ctrl4)
6423                 writel(ctrl4, port->base + MVPP22_GMAC_CTRL_4_REG);
6424 }
6425
6426 static int mvpp2__mac_prepare(struct phylink_config *config, unsigned int mode,
6427                               phy_interface_t interface)
6428 {
6429         struct mvpp2_port *port = mvpp2_phylink_to_port(config);
6430
6431         /* Check for invalid configuration */
6432         if (mvpp2_is_xlg(interface) && port->gop_id != 0) {
6433                 netdev_err(port->dev, "Invalid mode on %s\n", port->dev->name);
6434                 return -EINVAL;
6435         }
6436
6437         if (port->phy_interface != interface ||
6438             phylink_autoneg_inband(mode)) {
6439                 /* Force the link down when changing the interface or if in
6440                  * in-band mode to ensure we do not change the configuration
6441                  * while the hardware is indicating link is up. We force both
6442                  * XLG and GMAC down to ensure that they're both in a known
6443                  * state.
6444                  */
6445                 mvpp2_modify(port->base + MVPP2_GMAC_AUTONEG_CONFIG,
6446                              MVPP2_GMAC_FORCE_LINK_PASS |
6447                              MVPP2_GMAC_FORCE_LINK_DOWN,
6448                              MVPP2_GMAC_FORCE_LINK_DOWN);
6449
6450                 if (mvpp2_port_supports_xlg(port))
6451                         mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG,
6452                                      MVPP22_XLG_CTRL0_FORCE_LINK_PASS |
6453                                      MVPP22_XLG_CTRL0_FORCE_LINK_DOWN,
6454                                      MVPP22_XLG_CTRL0_FORCE_LINK_DOWN);
6455         }
6456
6457         /* Make sure the port is disabled when reconfiguring the mode */
6458         mvpp2_port_disable(port);
6459
6460         if (port->phy_interface != interface) {
6461                 /* Place GMAC into reset */
6462                 mvpp2_modify(port->base + MVPP2_GMAC_CTRL_2_REG,
6463                              MVPP2_GMAC_PORT_RESET_MASK,
6464                              MVPP2_GMAC_PORT_RESET_MASK);
6465
6466                 if (port->priv->hw_version >= MVPP22) {
6467                         mvpp22_gop_mask_irq(port);
6468
6469                         phy_power_off(port->comphy);
6470                 }
6471         }
6472
6473         /* Select the appropriate PCS operations depending on the
6474          * configured interface mode. We will only switch to a mode
6475          * that the validate() checks have already passed.
6476          */
6477         if (mvpp2_is_xlg(interface))
6478                 port->phylink_pcs.ops = &mvpp2_phylink_xlg_pcs_ops;
6479         else
6480                 port->phylink_pcs.ops = &mvpp2_phylink_gmac_pcs_ops;
6481
6482         return 0;
6483 }
6484
6485 static int mvpp2_mac_prepare(struct phylink_config *config, unsigned int mode,
6486                              phy_interface_t interface)
6487 {
6488         struct mvpp2_port *port = mvpp2_phylink_to_port(config);
6489         int ret;
6490
6491         ret = mvpp2__mac_prepare(config, mode, interface);
6492         if (ret == 0)
6493                 phylink_set_pcs(port->phylink, &port->phylink_pcs);
6494
6495         return ret;
6496 }
6497
6498 static void mvpp2_mac_config(struct phylink_config *config, unsigned int mode,
6499                              const struct phylink_link_state *state)
6500 {
6501         struct mvpp2_port *port = mvpp2_phylink_to_port(config);
6502
6503         /* mac (re)configuration */
6504         if (mvpp2_is_xlg(state->interface))
6505                 mvpp2_xlg_config(port, mode, state);
6506         else if (phy_interface_mode_is_rgmii(state->interface) ||
6507                  phy_interface_mode_is_8023z(state->interface) ||
6508                  state->interface == PHY_INTERFACE_MODE_SGMII)
6509                 mvpp2_gmac_config(port, mode, state);
6510
6511         if (port->priv->hw_version == MVPP21 && port->flags & MVPP2_F_LOOPBACK)
6512                 mvpp2_port_loopback_set(port, state);
6513 }
6514
6515 static int mvpp2_mac_finish(struct phylink_config *config, unsigned int mode,
6516                             phy_interface_t interface)
6517 {
6518         struct mvpp2_port *port = mvpp2_phylink_to_port(config);
6519
6520         if (port->priv->hw_version >= MVPP22 &&
6521             port->phy_interface != interface) {
6522                 port->phy_interface = interface;
6523
6524                 /* Reconfigure the serdes lanes */
6525                 mvpp22_mode_reconfigure(port);
6526
6527                 /* Unmask interrupts */
6528                 mvpp22_gop_unmask_irq(port);
6529         }
6530
6531         if (!mvpp2_is_xlg(interface)) {
6532                 /* Release GMAC reset and wait */
6533                 mvpp2_modify(port->base + MVPP2_GMAC_CTRL_2_REG,
6534                              MVPP2_GMAC_PORT_RESET_MASK, 0);
6535
6536                 while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
6537                        MVPP2_GMAC_PORT_RESET_MASK)
6538                         continue;
6539         }
6540
6541         mvpp2_port_enable(port);
6542
6543         /* Allow the link to come up if in in-band mode, otherwise the
6544          * link is forced via mac_link_down()/mac_link_up()
6545          */
6546         if (phylink_autoneg_inband(mode)) {
6547                 if (mvpp2_is_xlg(interface))
6548                         mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG,
6549                                      MVPP22_XLG_CTRL0_FORCE_LINK_PASS |
6550                                      MVPP22_XLG_CTRL0_FORCE_LINK_DOWN, 0);
6551                 else
6552                         mvpp2_modify(port->base + MVPP2_GMAC_AUTONEG_CONFIG,
6553                                      MVPP2_GMAC_FORCE_LINK_PASS |
6554                                      MVPP2_GMAC_FORCE_LINK_DOWN, 0);
6555         }
6556
6557         return 0;
6558 }
6559
6560 static void mvpp2_mac_link_up(struct phylink_config *config,
6561                               struct phy_device *phy,
6562                               unsigned int mode, phy_interface_t interface,
6563                               int speed, int duplex,
6564                               bool tx_pause, bool rx_pause)
6565 {
6566         struct mvpp2_port *port = mvpp2_phylink_to_port(config);
6567         u32 val;
6568         int i;
6569
6570         if (mvpp2_is_xlg(interface)) {
6571                 if (!phylink_autoneg_inband(mode)) {
6572                         val = MVPP22_XLG_CTRL0_FORCE_LINK_PASS;
6573                         if (tx_pause)
6574                                 val |= MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN;
6575                         if (rx_pause)
6576                                 val |= MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN;
6577
6578                         mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG,
6579                                      MVPP22_XLG_CTRL0_FORCE_LINK_DOWN |
6580                                      MVPP22_XLG_CTRL0_FORCE_LINK_PASS |
6581                                      MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN |
6582                                      MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN, val);
6583                 }
6584         } else {
6585                 if (!phylink_autoneg_inband(mode)) {
6586                         val = MVPP2_GMAC_FORCE_LINK_PASS;
6587
6588                         if (speed == SPEED_1000 || speed == SPEED_2500)
6589                                 val |= MVPP2_GMAC_CONFIG_GMII_SPEED;
6590                         else if (speed == SPEED_100)
6591                                 val |= MVPP2_GMAC_CONFIG_MII_SPEED;
6592
6593                         if (duplex == DUPLEX_FULL)
6594                                 val |= MVPP2_GMAC_CONFIG_FULL_DUPLEX;
6595
6596                         mvpp2_modify(port->base + MVPP2_GMAC_AUTONEG_CONFIG,
6597                                      MVPP2_GMAC_FORCE_LINK_DOWN |
6598                                      MVPP2_GMAC_FORCE_LINK_PASS |
6599                                      MVPP2_GMAC_CONFIG_MII_SPEED |
6600                                      MVPP2_GMAC_CONFIG_GMII_SPEED |
6601                                      MVPP2_GMAC_CONFIG_FULL_DUPLEX, val);
6602                 }
6603
6604                 /* We can always update the flow control enable bits;
6605                  * these will only be effective if flow control AN
6606                  * (MVPP2_GMAC_FLOW_CTRL_AUTONEG) is disabled.
6607                  */
6608                 val = 0;
6609                 if (tx_pause)
6610                         val |= MVPP22_CTRL4_TX_FC_EN;
6611                 if (rx_pause)
6612                         val |= MVPP22_CTRL4_RX_FC_EN;
6613
6614                 mvpp2_modify(port->base + MVPP22_GMAC_CTRL_4_REG,
6615                              MVPP22_CTRL4_RX_FC_EN | MVPP22_CTRL4_TX_FC_EN,
6616                              val);
6617         }
6618
6619         if (port->priv->global_tx_fc) {
6620                 port->tx_fc = tx_pause;
6621                 if (tx_pause)
6622                         mvpp2_rxq_enable_fc(port);
6623                 else
6624                         mvpp2_rxq_disable_fc(port);
6625                 if (port->priv->percpu_pools) {
6626                         for (i = 0; i < port->nrxqs; i++)
6627                                 mvpp2_bm_pool_update_fc(port, &port->priv->bm_pools[i], tx_pause);
6628                 } else {
6629                         mvpp2_bm_pool_update_fc(port, port->pool_long, tx_pause);
6630                         mvpp2_bm_pool_update_fc(port, port->pool_short, tx_pause);
6631                 }
6632                 if (port->priv->hw_version == MVPP23)
6633                         mvpp23_rx_fifo_fc_en(port->priv, port->id, tx_pause);
6634         }
6635
6636         mvpp2_port_enable(port);
6637
6638         mvpp2_egress_enable(port);
6639         mvpp2_ingress_enable(port);
6640         netif_tx_wake_all_queues(port->dev);
6641 }
6642
6643 static void mvpp2_mac_link_down(struct phylink_config *config,
6644                                 unsigned int mode, phy_interface_t interface)
6645 {
6646         struct mvpp2_port *port = mvpp2_phylink_to_port(config);
6647         u32 val;
6648
6649         if (!phylink_autoneg_inband(mode)) {
6650                 if (mvpp2_is_xlg(interface)) {
6651                         val = readl(port->base + MVPP22_XLG_CTRL0_REG);
6652                         val &= ~MVPP22_XLG_CTRL0_FORCE_LINK_PASS;
6653                         val |= MVPP22_XLG_CTRL0_FORCE_LINK_DOWN;
6654                         writel(val, port->base + MVPP22_XLG_CTRL0_REG);
6655                 } else {
6656                         val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
6657                         val &= ~MVPP2_GMAC_FORCE_LINK_PASS;
6658                         val |= MVPP2_GMAC_FORCE_LINK_DOWN;
6659                         writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
6660                 }
6661         }
6662
6663         netif_tx_stop_all_queues(port->dev);
6664         mvpp2_egress_disable(port);
6665         mvpp2_ingress_disable(port);
6666
6667         mvpp2_port_disable(port);
6668 }
6669
6670 static const struct phylink_mac_ops mvpp2_phylink_ops = {
6671         .validate = mvpp2_phylink_validate,
6672         .mac_prepare = mvpp2_mac_prepare,
6673         .mac_config = mvpp2_mac_config,
6674         .mac_finish = mvpp2_mac_finish,
6675         .mac_link_up = mvpp2_mac_link_up,
6676         .mac_link_down = mvpp2_mac_link_down,
6677 };
6678
6679 /* Work-around for ACPI */
6680 static void mvpp2_acpi_start(struct mvpp2_port *port)
6681 {
6682         /* Phylink isn't used as of now for ACPI, so the MAC has to be
6683          * configured manually when the interface is started. This will
6684          * be removed as soon as the phylink ACPI support lands in.
6685          */
6686         struct phylink_link_state state = {
6687                 .interface = port->phy_interface,
6688         };
6689         mvpp2__mac_prepare(&port->phylink_config, MLO_AN_INBAND,
6690                            port->phy_interface);
6691         mvpp2_mac_config(&port->phylink_config, MLO_AN_INBAND, &state);
6692         port->phylink_pcs.ops->pcs_config(&port->phylink_pcs, MLO_AN_INBAND,
6693                                           port->phy_interface,
6694                                           state.advertising, false);
6695         mvpp2_mac_finish(&port->phylink_config, MLO_AN_INBAND,
6696                          port->phy_interface);
6697         mvpp2_mac_link_up(&port->phylink_config, NULL,
6698                           MLO_AN_INBAND, port->phy_interface,
6699                           SPEED_UNKNOWN, DUPLEX_UNKNOWN, false, false);
6700 }
6701
6702 /* Ports initialization */
6703 static int mvpp2_port_probe(struct platform_device *pdev,
6704                             struct fwnode_handle *port_fwnode,
6705                             struct mvpp2 *priv)
6706 {
6707         struct phy *comphy = NULL;
6708         struct mvpp2_port *port;
6709         struct mvpp2_port_pcpu *port_pcpu;
6710         struct device_node *port_node = to_of_node(port_fwnode);
6711         netdev_features_t features;
6712         struct net_device *dev;
6713         struct phylink *phylink;
6714         char *mac_from = "";
6715         unsigned int ntxqs, nrxqs, thread;
6716         unsigned long flags = 0;
6717         bool has_tx_irqs;
6718         u32 id;
6719         int phy_mode;
6720         int err, i;
6721
6722         has_tx_irqs = mvpp2_port_has_irqs(priv, port_node, &flags);
6723         if (!has_tx_irqs && queue_mode == MVPP2_QDIST_MULTI_MODE) {
6724                 dev_err(&pdev->dev,
6725                         "not enough IRQs to support multi queue mode\n");
6726                 return -EINVAL;
6727         }
6728
6729         ntxqs = MVPP2_MAX_TXQ;
6730         nrxqs = mvpp2_get_nrxqs(priv);
6731
6732         dev = alloc_etherdev_mqs(sizeof(*port), ntxqs, nrxqs);
6733         if (!dev)
6734                 return -ENOMEM;
6735
6736         phy_mode = fwnode_get_phy_mode(port_fwnode);
6737         if (phy_mode < 0) {
6738                 dev_err(&pdev->dev, "incorrect phy mode\n");
6739                 err = phy_mode;
6740                 goto err_free_netdev;
6741         }
6742
6743         /*
6744          * Rewrite 10GBASE-KR to 10GBASE-R for compatibility with existing DT.
6745          * Existing usage of 10GBASE-KR is not correct; no backplane
6746          * negotiation is done, and this driver does not actually support
6747          * 10GBASE-KR.
6748          */
6749         if (phy_mode == PHY_INTERFACE_MODE_10GKR)
6750                 phy_mode = PHY_INTERFACE_MODE_10GBASER;
6751
6752         if (port_node) {
6753                 comphy = devm_of_phy_get(&pdev->dev, port_node, NULL);
6754                 if (IS_ERR(comphy)) {
6755                         if (PTR_ERR(comphy) == -EPROBE_DEFER) {
6756                                 err = -EPROBE_DEFER;
6757                                 goto err_free_netdev;
6758                         }
6759                         comphy = NULL;
6760                 }
6761         }
6762
6763         if (fwnode_property_read_u32(port_fwnode, "port-id", &id)) {
6764                 err = -EINVAL;
6765                 dev_err(&pdev->dev, "missing port-id value\n");
6766                 goto err_free_netdev;
6767         }
6768
6769         dev->tx_queue_len = MVPP2_MAX_TXD_MAX;
6770         dev->watchdog_timeo = 5 * HZ;
6771         dev->netdev_ops = &mvpp2_netdev_ops;
6772         dev->ethtool_ops = &mvpp2_eth_tool_ops;
6773
6774         port = netdev_priv(dev);
6775         port->dev = dev;
6776         port->fwnode = port_fwnode;
6777         port->has_phy = !!of_find_property(port_node, "phy", NULL);
6778         port->ntxqs = ntxqs;
6779         port->nrxqs = nrxqs;
6780         port->priv = priv;
6781         port->has_tx_irqs = has_tx_irqs;
6782         port->flags = flags;
6783
6784         err = mvpp2_queue_vectors_init(port, port_node);
6785         if (err)
6786                 goto err_free_netdev;
6787
6788         if (port_node)
6789                 port->port_irq = of_irq_get_byname(port_node, "link");
6790         else
6791                 port->port_irq = fwnode_irq_get(port_fwnode, port->nqvecs + 1);
6792         if (port->port_irq == -EPROBE_DEFER) {
6793                 err = -EPROBE_DEFER;
6794                 goto err_deinit_qvecs;
6795         }
6796         if (port->port_irq <= 0)
6797                 /* the link irq is optional */
6798                 port->port_irq = 0;
6799
6800         if (fwnode_property_read_bool(port_fwnode, "marvell,loopback"))
6801                 port->flags |= MVPP2_F_LOOPBACK;
6802
6803         port->id = id;
6804         if (priv->hw_version == MVPP21)
6805                 port->first_rxq = port->id * port->nrxqs;
6806         else
6807                 port->first_rxq = port->id * priv->max_port_rxqs;
6808
6809         port->of_node = port_node;
6810         port->phy_interface = phy_mode;
6811         port->comphy = comphy;
6812
6813         if (priv->hw_version == MVPP21) {
6814                 port->base = devm_platform_ioremap_resource(pdev, 2 + id);
6815                 if (IS_ERR(port->base)) {
6816                         err = PTR_ERR(port->base);
6817                         goto err_free_irq;
6818                 }
6819
6820                 port->stats_base = port->priv->lms_base +
6821                                    MVPP21_MIB_COUNTERS_OFFSET +
6822                                    port->gop_id * MVPP21_MIB_COUNTERS_PORT_SZ;
6823         } else {
6824                 if (fwnode_property_read_u32(port_fwnode, "gop-port-id",
6825                                              &port->gop_id)) {
6826                         err = -EINVAL;
6827                         dev_err(&pdev->dev, "missing gop-port-id value\n");
6828                         goto err_deinit_qvecs;
6829                 }
6830
6831                 port->base = priv->iface_base + MVPP22_GMAC_BASE(port->gop_id);
6832                 port->stats_base = port->priv->iface_base +
6833                                    MVPP22_MIB_COUNTERS_OFFSET +
6834                                    port->gop_id * MVPP22_MIB_COUNTERS_PORT_SZ;
6835
6836                 /* We may want a property to describe whether we should use
6837                  * MAC hardware timestamping.
6838                  */
6839                 if (priv->tai)
6840                         port->hwtstamp = true;
6841         }
6842
6843         /* Alloc per-cpu and ethtool stats */
6844         port->stats = netdev_alloc_pcpu_stats(struct mvpp2_pcpu_stats);
6845         if (!port->stats) {
6846                 err = -ENOMEM;
6847                 goto err_free_irq;
6848         }
6849
6850         port->ethtool_stats = devm_kcalloc(&pdev->dev,
6851                                            MVPP2_N_ETHTOOL_STATS(ntxqs, nrxqs),
6852                                            sizeof(u64), GFP_KERNEL);
6853         if (!port->ethtool_stats) {
6854                 err = -ENOMEM;
6855                 goto err_free_stats;
6856         }
6857
6858         mutex_init(&port->gather_stats_lock);
6859         INIT_DELAYED_WORK(&port->stats_work, mvpp2_gather_hw_statistics);
6860
6861         mvpp2_port_copy_mac_addr(dev, priv, port_fwnode, &mac_from);
6862
6863         port->tx_ring_size = MVPP2_MAX_TXD_DFLT;
6864         port->rx_ring_size = MVPP2_MAX_RXD_DFLT;
6865         SET_NETDEV_DEV(dev, &pdev->dev);
6866
6867         err = mvpp2_port_init(port);
6868         if (err < 0) {
6869                 dev_err(&pdev->dev, "failed to init port %d\n", id);
6870                 goto err_free_stats;
6871         }
6872
6873         mvpp2_port_periodic_xon_disable(port);
6874
6875         mvpp2_mac_reset_assert(port);
6876         mvpp22_pcs_reset_assert(port);
6877
6878         port->pcpu = alloc_percpu(struct mvpp2_port_pcpu);
6879         if (!port->pcpu) {
6880                 err = -ENOMEM;
6881                 goto err_free_txq_pcpu;
6882         }
6883
6884         if (!port->has_tx_irqs) {
6885                 for (thread = 0; thread < priv->nthreads; thread++) {
6886                         port_pcpu = per_cpu_ptr(port->pcpu, thread);
6887
6888                         hrtimer_init(&port_pcpu->tx_done_timer, CLOCK_MONOTONIC,
6889                                      HRTIMER_MODE_REL_PINNED_SOFT);
6890                         port_pcpu->tx_done_timer.function = mvpp2_hr_timer_cb;
6891                         port_pcpu->timer_scheduled = false;
6892                         port_pcpu->dev = dev;
6893                 }
6894         }
6895
6896         features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
6897                    NETIF_F_TSO;
6898         dev->features = features | NETIF_F_RXCSUM;
6899         dev->hw_features |= features | NETIF_F_RXCSUM | NETIF_F_GRO |
6900                             NETIF_F_HW_VLAN_CTAG_FILTER;
6901
6902         if (mvpp22_rss_is_supported(port)) {
6903                 dev->hw_features |= NETIF_F_RXHASH;
6904                 dev->features |= NETIF_F_NTUPLE;
6905         }
6906
6907         if (!port->priv->percpu_pools)
6908                 mvpp2_set_hw_csum(port, port->pool_long->id);
6909
6910         dev->vlan_features |= features;
6911         dev->gso_max_segs = MVPP2_MAX_TSO_SEGS;
6912         dev->priv_flags |= IFF_UNICAST_FLT;
6913
6914         /* MTU range: 68 - 9704 */
6915         dev->min_mtu = ETH_MIN_MTU;
6916         /* 9704 == 9728 - 20 and rounding to 8 */
6917         dev->max_mtu = MVPP2_BM_JUMBO_PKT_SIZE;
6918         dev->dev.of_node = port_node;
6919
6920         /* Phylink isn't used w/ ACPI as of now */
6921         if (port_node) {
6922                 port->phylink_config.dev = &dev->dev;
6923                 port->phylink_config.type = PHYLINK_NETDEV;
6924
6925                 phylink = phylink_create(&port->phylink_config, port_fwnode,
6926                                          phy_mode, &mvpp2_phylink_ops);
6927                 if (IS_ERR(phylink)) {
6928                         err = PTR_ERR(phylink);
6929                         goto err_free_port_pcpu;
6930                 }
6931                 port->phylink = phylink;
6932         } else {
6933                 port->phylink = NULL;
6934         }
6935
6936         /* Cycle the comphy to power it down, saving 270mW per port -
6937          * don't worry about an error powering it up. When the comphy
6938          * driver does this, we can remove this code.
6939          */
6940         if (port->comphy) {
6941                 err = mvpp22_comphy_init(port);
6942                 if (err == 0)
6943                         phy_power_off(port->comphy);
6944         }
6945
6946         err = register_netdev(dev);
6947         if (err < 0) {
6948                 dev_err(&pdev->dev, "failed to register netdev\n");
6949                 goto err_phylink;
6950         }
6951         netdev_info(dev, "Using %s mac address %pM\n", mac_from, dev->dev_addr);
6952
6953         priv->port_list[priv->port_count++] = port;
6954
6955         return 0;
6956
6957 err_phylink:
6958         if (port->phylink)
6959                 phylink_destroy(port->phylink);
6960 err_free_port_pcpu:
6961         free_percpu(port->pcpu);
6962 err_free_txq_pcpu:
6963         for (i = 0; i < port->ntxqs; i++)
6964                 free_percpu(port->txqs[i]->pcpu);
6965 err_free_stats:
6966         free_percpu(port->stats);
6967 err_free_irq:
6968         if (port->port_irq)
6969                 irq_dispose_mapping(port->port_irq);
6970 err_deinit_qvecs:
6971         mvpp2_queue_vectors_deinit(port);
6972 err_free_netdev:
6973         free_netdev(dev);
6974         return err;
6975 }
6976
6977 /* Ports removal routine */
6978 static void mvpp2_port_remove(struct mvpp2_port *port)
6979 {
6980         int i;
6981
6982         unregister_netdev(port->dev);
6983         if (port->phylink)
6984                 phylink_destroy(port->phylink);
6985         free_percpu(port->pcpu);
6986         free_percpu(port->stats);
6987         for (i = 0; i < port->ntxqs; i++)
6988                 free_percpu(port->txqs[i]->pcpu);
6989         mvpp2_queue_vectors_deinit(port);
6990         if (port->port_irq)
6991                 irq_dispose_mapping(port->port_irq);
6992         free_netdev(port->dev);
6993 }
6994
6995 /* Initialize decoding windows */
6996 static void mvpp2_conf_mbus_windows(const struct mbus_dram_target_info *dram,
6997                                     struct mvpp2 *priv)
6998 {
6999         u32 win_enable;
7000         int i;
7001
7002         for (i = 0; i < 6; i++) {
7003                 mvpp2_write(priv, MVPP2_WIN_BASE(i), 0);
7004                 mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0);
7005
7006                 if (i < 4)
7007                         mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0);
7008         }
7009
7010         win_enable = 0;
7011
7012         for (i = 0; i < dram->num_cs; i++) {
7013                 const struct mbus_dram_window *cs = dram->cs + i;
7014
7015                 mvpp2_write(priv, MVPP2_WIN_BASE(i),
7016                             (cs->base & 0xffff0000) | (cs->mbus_attr << 8) |
7017                             dram->mbus_dram_target_id);
7018
7019                 mvpp2_write(priv, MVPP2_WIN_SIZE(i),
7020                             (cs->size - 1) & 0xffff0000);
7021
7022                 win_enable |= (1 << i);
7023         }
7024
7025         mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable);
7026 }
7027
7028 /* Initialize Rx FIFO's */
7029 static void mvpp2_rx_fifo_init(struct mvpp2 *priv)
7030 {
7031         int port;
7032
7033         for (port = 0; port < MVPP2_MAX_PORTS; port++) {
7034                 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
7035                             MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB);
7036                 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
7037                             MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB);
7038         }
7039
7040         mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
7041                     MVPP2_RX_FIFO_PORT_MIN_PKT);
7042         mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
7043 }
7044
7045 static void mvpp22_rx_fifo_set_hw(struct mvpp2 *priv, int port, int data_size)
7046 {
7047         int attr_size = MVPP2_RX_FIFO_PORT_ATTR_SIZE(data_size);
7048
7049         mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port), data_size);
7050         mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port), attr_size);
7051 }
7052
7053 /* Initialize TX FIFO's: the total FIFO size is 48kB on PPv2.2 and PPv2.3.
7054  * 4kB fixed space must be assigned for the loopback port.
7055  * Redistribute remaining avialable 44kB space among all active ports.
7056  * Guarantee minimum 32kB for 10G port and 8kB for port 1, capable of 2.5G
7057  * SGMII link.
7058  */
7059 static void mvpp22_rx_fifo_init(struct mvpp2 *priv)
7060 {
7061         int remaining_ports_count;
7062         unsigned long port_map;
7063         int size_remainder;
7064         int port, size;
7065
7066         /* The loopback requires fixed 4kB of the FIFO space assignment. */
7067         mvpp22_rx_fifo_set_hw(priv, MVPP2_LOOPBACK_PORT_INDEX,
7068                               MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB);
7069         port_map = priv->port_map & ~BIT(MVPP2_LOOPBACK_PORT_INDEX);
7070
7071         /* Set RX FIFO size to 0 for inactive ports. */
7072         for_each_clear_bit(port, &port_map, MVPP2_LOOPBACK_PORT_INDEX)
7073                 mvpp22_rx_fifo_set_hw(priv, port, 0);
7074
7075         /* Assign remaining RX FIFO space among all active ports. */
7076         size_remainder = MVPP2_RX_FIFO_PORT_DATA_SIZE_44KB;
7077         remaining_ports_count = hweight_long(port_map);
7078
7079         for_each_set_bit(port, &port_map, MVPP2_LOOPBACK_PORT_INDEX) {
7080                 if (remaining_ports_count == 1)
7081                         size = size_remainder;
7082                 else if (port == 0)
7083                         size = max(size_remainder / remaining_ports_count,
7084                                    MVPP2_RX_FIFO_PORT_DATA_SIZE_32KB);
7085                 else if (port == 1)
7086                         size = max(size_remainder / remaining_ports_count,
7087                                    MVPP2_RX_FIFO_PORT_DATA_SIZE_8KB);
7088                 else
7089                         size = size_remainder / remaining_ports_count;
7090
7091                 size_remainder -= size;
7092                 remaining_ports_count--;
7093
7094                 mvpp22_rx_fifo_set_hw(priv, port, size);
7095         }
7096
7097         mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
7098                     MVPP2_RX_FIFO_PORT_MIN_PKT);
7099         mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
7100 }
7101
7102 /* Configure Rx FIFO Flow control thresholds */
7103 static void mvpp23_rx_fifo_fc_set_tresh(struct mvpp2 *priv)
7104 {
7105         int port, val;
7106
7107         /* Port 0: maximum speed -10Gb/s port
7108          *         required by spec RX FIFO threshold 9KB
7109          * Port 1: maximum speed -5Gb/s port
7110          *         required by spec RX FIFO threshold 4KB
7111          * Port 2: maximum speed -1Gb/s port
7112          *         required by spec RX FIFO threshold 2KB
7113          */
7114
7115         /* Without loopback port */
7116         for (port = 0; port < (MVPP2_MAX_PORTS - 1); port++) {
7117                 if (port == 0) {
7118                         val = (MVPP23_PORT0_FIFO_TRSH / MVPP2_RX_FC_TRSH_UNIT)
7119                                 << MVPP2_RX_FC_TRSH_OFFS;
7120                         val &= MVPP2_RX_FC_TRSH_MASK;
7121                         mvpp2_write(priv, MVPP2_RX_FC_REG(port), val);
7122                 } else if (port == 1) {
7123                         val = (MVPP23_PORT1_FIFO_TRSH / MVPP2_RX_FC_TRSH_UNIT)
7124                                 << MVPP2_RX_FC_TRSH_OFFS;
7125                         val &= MVPP2_RX_FC_TRSH_MASK;
7126                         mvpp2_write(priv, MVPP2_RX_FC_REG(port), val);
7127                 } else {
7128                         val = (MVPP23_PORT2_FIFO_TRSH / MVPP2_RX_FC_TRSH_UNIT)
7129                                 << MVPP2_RX_FC_TRSH_OFFS;
7130                         val &= MVPP2_RX_FC_TRSH_MASK;
7131                         mvpp2_write(priv, MVPP2_RX_FC_REG(port), val);
7132                 }
7133         }
7134 }
7135
7136 /* Configure Rx FIFO Flow control thresholds */
7137 void mvpp23_rx_fifo_fc_en(struct mvpp2 *priv, int port, bool en)
7138 {
7139         int val;
7140
7141         val = mvpp2_read(priv, MVPP2_RX_FC_REG(port));
7142
7143         if (en)
7144                 val |= MVPP2_RX_FC_EN;
7145         else
7146                 val &= ~MVPP2_RX_FC_EN;
7147
7148         mvpp2_write(priv, MVPP2_RX_FC_REG(port), val);
7149 }
7150
7151 static void mvpp22_tx_fifo_set_hw(struct mvpp2 *priv, int port, int size)
7152 {
7153         int threshold = MVPP2_TX_FIFO_THRESHOLD(size);
7154
7155         mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), size);
7156         mvpp2_write(priv, MVPP22_TX_FIFO_THRESH_REG(port), threshold);
7157 }
7158
7159 /* Initialize TX FIFO's: the total FIFO size is 19kB on PPv2.2 and PPv2.3.
7160  * 1kB fixed space must be assigned for the loopback port.
7161  * Redistribute remaining avialable 18kB space among all active ports.
7162  * The 10G interface should use 10kB (which is maximum possible size
7163  * per single port).
7164  */
7165 static void mvpp22_tx_fifo_init(struct mvpp2 *priv)
7166 {
7167         int remaining_ports_count;
7168         unsigned long port_map;
7169         int size_remainder;
7170         int port, size;
7171
7172         /* The loopback requires fixed 1kB of the FIFO space assignment. */
7173         mvpp22_tx_fifo_set_hw(priv, MVPP2_LOOPBACK_PORT_INDEX,
7174                               MVPP22_TX_FIFO_DATA_SIZE_1KB);
7175         port_map = priv->port_map & ~BIT(MVPP2_LOOPBACK_PORT_INDEX);
7176
7177         /* Set TX FIFO size to 0 for inactive ports. */
7178         for_each_clear_bit(port, &port_map, MVPP2_LOOPBACK_PORT_INDEX)
7179                 mvpp22_tx_fifo_set_hw(priv, port, 0);
7180
7181         /* Assign remaining TX FIFO space among all active ports. */
7182         size_remainder = MVPP22_TX_FIFO_DATA_SIZE_18KB;
7183         remaining_ports_count = hweight_long(port_map);
7184
7185         for_each_set_bit(port, &port_map, MVPP2_LOOPBACK_PORT_INDEX) {
7186                 if (remaining_ports_count == 1)
7187                         size = min(size_remainder,
7188                                    MVPP22_TX_FIFO_DATA_SIZE_10KB);
7189                 else if (port == 0)
7190                         size = MVPP22_TX_FIFO_DATA_SIZE_10KB;
7191                 else
7192                         size = size_remainder / remaining_ports_count;
7193
7194                 size_remainder -= size;
7195                 remaining_ports_count--;
7196
7197                 mvpp22_tx_fifo_set_hw(priv, port, size);
7198         }
7199 }
7200
7201 static void mvpp2_axi_init(struct mvpp2 *priv)
7202 {
7203         u32 val, rdval, wrval;
7204
7205         mvpp2_write(priv, MVPP22_BM_ADDR_HIGH_RLS_REG, 0x0);
7206
7207         /* AXI Bridge Configuration */
7208
7209         rdval = MVPP22_AXI_CODE_CACHE_RD_CACHE
7210                 << MVPP22_AXI_ATTR_CACHE_OFFS;
7211         rdval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
7212                 << MVPP22_AXI_ATTR_DOMAIN_OFFS;
7213
7214         wrval = MVPP22_AXI_CODE_CACHE_WR_CACHE
7215                 << MVPP22_AXI_ATTR_CACHE_OFFS;
7216         wrval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
7217                 << MVPP22_AXI_ATTR_DOMAIN_OFFS;
7218
7219         /* BM */
7220         mvpp2_write(priv, MVPP22_AXI_BM_WR_ATTR_REG, wrval);
7221         mvpp2_write(priv, MVPP22_AXI_BM_RD_ATTR_REG, rdval);
7222
7223         /* Descriptors */
7224         mvpp2_write(priv, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, rdval);
7225         mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, wrval);
7226         mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, rdval);
7227         mvpp2_write(priv, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, wrval);
7228
7229         /* Buffer Data */
7230         mvpp2_write(priv, MVPP22_AXI_TX_DATA_RD_ATTR_REG, rdval);
7231         mvpp2_write(priv, MVPP22_AXI_RX_DATA_WR_ATTR_REG, wrval);
7232
7233         val = MVPP22_AXI_CODE_CACHE_NON_CACHE
7234                 << MVPP22_AXI_CODE_CACHE_OFFS;
7235         val |= MVPP22_AXI_CODE_DOMAIN_SYSTEM
7236                 << MVPP22_AXI_CODE_DOMAIN_OFFS;
7237         mvpp2_write(priv, MVPP22_AXI_RD_NORMAL_CODE_REG, val);
7238         mvpp2_write(priv, MVPP22_AXI_WR_NORMAL_CODE_REG, val);
7239
7240         val = MVPP22_AXI_CODE_CACHE_RD_CACHE
7241                 << MVPP22_AXI_CODE_CACHE_OFFS;
7242         val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
7243                 << MVPP22_AXI_CODE_DOMAIN_OFFS;
7244
7245         mvpp2_write(priv, MVPP22_AXI_RD_SNOOP_CODE_REG, val);
7246
7247         val = MVPP22_AXI_CODE_CACHE_WR_CACHE
7248                 << MVPP22_AXI_CODE_CACHE_OFFS;
7249         val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
7250                 << MVPP22_AXI_CODE_DOMAIN_OFFS;
7251
7252         mvpp2_write(priv, MVPP22_AXI_WR_SNOOP_CODE_REG, val);
7253 }
7254
7255 /* Initialize network controller common part HW */
7256 static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv)
7257 {
7258         const struct mbus_dram_target_info *dram_target_info;
7259         int err, i;
7260         u32 val;
7261
7262         /* MBUS windows configuration */
7263         dram_target_info = mv_mbus_dram_info();
7264         if (dram_target_info)
7265                 mvpp2_conf_mbus_windows(dram_target_info, priv);
7266
7267         if (priv->hw_version >= MVPP22)
7268                 mvpp2_axi_init(priv);
7269
7270         /* Disable HW PHY polling */
7271         if (priv->hw_version == MVPP21) {
7272                 val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
7273                 val |= MVPP2_PHY_AN_STOP_SMI0_MASK;
7274                 writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
7275         } else {
7276                 val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
7277                 val &= ~MVPP22_SMI_POLLING_EN;
7278                 writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
7279         }
7280
7281         /* Allocate and initialize aggregated TXQs */
7282         priv->aggr_txqs = devm_kcalloc(&pdev->dev, MVPP2_MAX_THREADS,
7283                                        sizeof(*priv->aggr_txqs),
7284                                        GFP_KERNEL);
7285         if (!priv->aggr_txqs)
7286                 return -ENOMEM;
7287
7288         for (i = 0; i < MVPP2_MAX_THREADS; i++) {
7289                 priv->aggr_txqs[i].id = i;
7290                 priv->aggr_txqs[i].size = MVPP2_AGGR_TXQ_SIZE;
7291                 err = mvpp2_aggr_txq_init(pdev, &priv->aggr_txqs[i], i, priv);
7292                 if (err < 0)
7293                         return err;
7294         }
7295
7296         /* Fifo Init */
7297         if (priv->hw_version == MVPP21) {
7298                 mvpp2_rx_fifo_init(priv);
7299         } else {
7300                 mvpp22_rx_fifo_init(priv);
7301                 mvpp22_tx_fifo_init(priv);
7302                 if (priv->hw_version == MVPP23)
7303                         mvpp23_rx_fifo_fc_set_tresh(priv);
7304         }
7305
7306         if (priv->hw_version == MVPP21)
7307                 writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT,
7308                        priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG);
7309
7310         /* Allow cache snoop when transmiting packets */
7311         mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1);
7312
7313         /* Buffer Manager initialization */
7314         err = mvpp2_bm_init(&pdev->dev, priv);
7315         if (err < 0)
7316                 return err;
7317
7318         /* Parser default initialization */
7319         err = mvpp2_prs_default_init(pdev, priv);
7320         if (err < 0)
7321                 return err;
7322
7323         /* Classifier default initialization */
7324         mvpp2_cls_init(priv);
7325
7326         return 0;
7327 }
7328
7329 static int mvpp2_get_sram(struct platform_device *pdev,
7330                           struct mvpp2 *priv)
7331 {
7332         struct resource *res;
7333
7334         res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
7335         if (!res) {
7336                 if (has_acpi_companion(&pdev->dev))
7337                         dev_warn(&pdev->dev, "ACPI is too old, Flow control not supported\n");
7338                 else
7339                         dev_warn(&pdev->dev, "DT is too old, Flow control not supported\n");
7340                 return 0;
7341         }
7342
7343         priv->cm3_base = devm_ioremap_resource(&pdev->dev, res);
7344
7345         return PTR_ERR_OR_ZERO(priv->cm3_base);
7346 }
7347
7348 static int mvpp2_probe(struct platform_device *pdev)
7349 {
7350         const struct acpi_device_id *acpi_id;
7351         struct fwnode_handle *fwnode = pdev->dev.fwnode;
7352         struct fwnode_handle *port_fwnode;
7353         struct mvpp2 *priv;
7354         struct resource *res;
7355         void __iomem *base;
7356         int i, shared;
7357         int err;
7358
7359         priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
7360         if (!priv)
7361                 return -ENOMEM;
7362
7363         if (has_acpi_companion(&pdev->dev)) {
7364                 acpi_id = acpi_match_device(pdev->dev.driver->acpi_match_table,
7365                                             &pdev->dev);
7366                 if (!acpi_id)
7367                         return -EINVAL;
7368                 priv->hw_version = (unsigned long)acpi_id->driver_data;
7369         } else {
7370                 priv->hw_version =
7371                         (unsigned long)of_device_get_match_data(&pdev->dev);
7372         }
7373
7374         /* multi queue mode isn't supported on PPV2.1, fallback to single
7375          * mode
7376          */
7377         if (priv->hw_version == MVPP21)
7378                 queue_mode = MVPP2_QDIST_SINGLE_MODE;
7379
7380         base = devm_platform_ioremap_resource(pdev, 0);
7381         if (IS_ERR(base))
7382                 return PTR_ERR(base);
7383
7384         if (priv->hw_version == MVPP21) {
7385                 priv->lms_base = devm_platform_ioremap_resource(pdev, 1);
7386                 if (IS_ERR(priv->lms_base))
7387                         return PTR_ERR(priv->lms_base);
7388         } else {
7389                 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
7390                 if (has_acpi_companion(&pdev->dev)) {
7391                         /* In case the MDIO memory region is declared in
7392                          * the ACPI, it can already appear as 'in-use'
7393                          * in the OS. Because it is overlapped by second
7394                          * region of the network controller, make
7395                          * sure it is released, before requesting it again.
7396                          * The care is taken by mvpp2 driver to avoid
7397                          * concurrent access to this memory region.
7398                          */
7399                         release_resource(res);
7400                 }
7401                 priv->iface_base = devm_ioremap_resource(&pdev->dev, res);
7402                 if (IS_ERR(priv->iface_base))
7403                         return PTR_ERR(priv->iface_base);
7404
7405                 /* Map CM3 SRAM */
7406                 err = mvpp2_get_sram(pdev, priv);
7407                 if (err)
7408                         dev_warn(&pdev->dev, "Fail to alloc CM3 SRAM\n");
7409
7410                 /* Enable global Flow Control only if handler to SRAM not NULL */
7411                 if (priv->cm3_base)
7412                         priv->global_tx_fc = true;
7413         }
7414
7415         if (priv->hw_version >= MVPP22 && dev_of_node(&pdev->dev)) {
7416                 priv->sysctrl_base =
7417                         syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
7418                                                         "marvell,system-controller");
7419                 if (IS_ERR(priv->sysctrl_base))
7420                         /* The system controller regmap is optional for dt
7421                          * compatibility reasons. When not provided, the
7422                          * configuration of the GoP relies on the
7423                          * firmware/bootloader.
7424                          */
7425                         priv->sysctrl_base = NULL;
7426         }
7427
7428         if (priv->hw_version >= MVPP22 &&
7429             mvpp2_get_nrxqs(priv) * 2 <= MVPP2_BM_MAX_POOLS)
7430                 priv->percpu_pools = 1;
7431
7432         mvpp2_setup_bm_pool();
7433
7434
7435         priv->nthreads = min_t(unsigned int, num_present_cpus(),
7436                                MVPP2_MAX_THREADS);
7437
7438         shared = num_present_cpus() - priv->nthreads;
7439         if (shared > 0)
7440                 bitmap_fill(&priv->lock_map,
7441                             min_t(int, shared, MVPP2_MAX_THREADS));
7442
7443         for (i = 0; i < MVPP2_MAX_THREADS; i++) {
7444                 u32 addr_space_sz;
7445
7446                 addr_space_sz = (priv->hw_version == MVPP21 ?
7447                                  MVPP21_ADDR_SPACE_SZ : MVPP22_ADDR_SPACE_SZ);
7448                 priv->swth_base[i] = base + i * addr_space_sz;
7449         }
7450
7451         if (priv->hw_version == MVPP21)
7452                 priv->max_port_rxqs = 8;
7453         else
7454                 priv->max_port_rxqs = 32;
7455
7456         if (dev_of_node(&pdev->dev)) {
7457                 priv->pp_clk = devm_clk_get(&pdev->dev, "pp_clk");
7458                 if (IS_ERR(priv->pp_clk))
7459                         return PTR_ERR(priv->pp_clk);
7460                 err = clk_prepare_enable(priv->pp_clk);
7461                 if (err < 0)
7462                         return err;
7463
7464                 priv->gop_clk = devm_clk_get(&pdev->dev, "gop_clk");
7465                 if (IS_ERR(priv->gop_clk)) {
7466                         err = PTR_ERR(priv->gop_clk);
7467                         goto err_pp_clk;
7468                 }
7469                 err = clk_prepare_enable(priv->gop_clk);
7470                 if (err < 0)
7471                         goto err_pp_clk;
7472
7473                 if (priv->hw_version >= MVPP22) {
7474                         priv->mg_clk = devm_clk_get(&pdev->dev, "mg_clk");
7475                         if (IS_ERR(priv->mg_clk)) {
7476                                 err = PTR_ERR(priv->mg_clk);
7477                                 goto err_gop_clk;
7478                         }
7479
7480                         err = clk_prepare_enable(priv->mg_clk);
7481                         if (err < 0)
7482                                 goto err_gop_clk;
7483
7484                         priv->mg_core_clk = devm_clk_get(&pdev->dev, "mg_core_clk");
7485                         if (IS_ERR(priv->mg_core_clk)) {
7486                                 priv->mg_core_clk = NULL;
7487                         } else {
7488                                 err = clk_prepare_enable(priv->mg_core_clk);
7489                                 if (err < 0)
7490                                         goto err_mg_clk;
7491                         }
7492                 }
7493
7494                 priv->axi_clk = devm_clk_get(&pdev->dev, "axi_clk");
7495                 if (IS_ERR(priv->axi_clk)) {
7496                         err = PTR_ERR(priv->axi_clk);
7497                         if (err == -EPROBE_DEFER)
7498                                 goto err_mg_core_clk;
7499                         priv->axi_clk = NULL;
7500                 } else {
7501                         err = clk_prepare_enable(priv->axi_clk);
7502                         if (err < 0)
7503                                 goto err_mg_core_clk;
7504                 }
7505
7506                 /* Get system's tclk rate */
7507                 priv->tclk = clk_get_rate(priv->pp_clk);
7508         } else if (device_property_read_u32(&pdev->dev, "clock-frequency",
7509                                             &priv->tclk)) {
7510                 dev_err(&pdev->dev, "missing clock-frequency value\n");
7511                 return -EINVAL;
7512         }
7513
7514         if (priv->hw_version >= MVPP22) {
7515                 err = dma_set_mask(&pdev->dev, MVPP2_DESC_DMA_MASK);
7516                 if (err)
7517                         goto err_axi_clk;
7518                 /* Sadly, the BM pools all share the same register to
7519                  * store the high 32 bits of their address. So they
7520                  * must all have the same high 32 bits, which forces
7521                  * us to restrict coherent memory to DMA_BIT_MASK(32).
7522                  */
7523                 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
7524                 if (err)
7525                         goto err_axi_clk;
7526         }
7527
7528         /* Map DTS-active ports. Should be done before FIFO mvpp2_init */
7529         fwnode_for_each_available_child_node(fwnode, port_fwnode) {
7530                 if (!fwnode_property_read_u32(port_fwnode, "port-id", &i))
7531                         priv->port_map |= BIT(i);
7532         }
7533
7534         if (mvpp2_read(priv, MVPP2_VER_ID_REG) == MVPP2_VER_PP23)
7535                 priv->hw_version = MVPP23;
7536
7537         /* Init mss lock */
7538         spin_lock_init(&priv->mss_spinlock);
7539
7540         /* Initialize network controller */
7541         err = mvpp2_init(pdev, priv);
7542         if (err < 0) {
7543                 dev_err(&pdev->dev, "failed to initialize controller\n");
7544                 goto err_axi_clk;
7545         }
7546
7547         err = mvpp22_tai_probe(&pdev->dev, priv);
7548         if (err < 0)
7549                 goto err_axi_clk;
7550
7551         /* Initialize ports */
7552         fwnode_for_each_available_child_node(fwnode, port_fwnode) {
7553                 err = mvpp2_port_probe(pdev, port_fwnode, priv);
7554                 if (err < 0)
7555                         goto err_port_probe;
7556         }
7557
7558         if (priv->port_count == 0) {
7559                 dev_err(&pdev->dev, "no ports enabled\n");
7560                 err = -ENODEV;
7561                 goto err_axi_clk;
7562         }
7563
7564         /* Statistics must be gathered regularly because some of them (like
7565          * packets counters) are 32-bit registers and could overflow quite
7566          * quickly. For instance, a 10Gb link used at full bandwidth with the
7567          * smallest packets (64B) will overflow a 32-bit counter in less than
7568          * 30 seconds. Then, use a workqueue to fill 64-bit counters.
7569          */
7570         snprintf(priv->queue_name, sizeof(priv->queue_name),
7571                  "stats-wq-%s%s", netdev_name(priv->port_list[0]->dev),
7572                  priv->port_count > 1 ? "+" : "");
7573         priv->stats_queue = create_singlethread_workqueue(priv->queue_name);
7574         if (!priv->stats_queue) {
7575                 err = -ENOMEM;
7576                 goto err_port_probe;
7577         }
7578
7579         if (priv->global_tx_fc && priv->hw_version >= MVPP22) {
7580                 err = mvpp2_enable_global_fc(priv);
7581                 if (err)
7582                         dev_warn(&pdev->dev, "Minimum of CM3 firmware 18.09 and chip revision B0 required for flow control\n");
7583         }
7584
7585         mvpp2_dbgfs_init(priv, pdev->name);
7586
7587         platform_set_drvdata(pdev, priv);
7588         return 0;
7589
7590 err_port_probe:
7591         i = 0;
7592         fwnode_for_each_available_child_node(fwnode, port_fwnode) {
7593                 if (priv->port_list[i])
7594                         mvpp2_port_remove(priv->port_list[i]);
7595                 i++;
7596         }
7597 err_axi_clk:
7598         clk_disable_unprepare(priv->axi_clk);
7599
7600 err_mg_core_clk:
7601         if (priv->hw_version >= MVPP22)
7602                 clk_disable_unprepare(priv->mg_core_clk);
7603 err_mg_clk:
7604         if (priv->hw_version >= MVPP22)
7605                 clk_disable_unprepare(priv->mg_clk);
7606 err_gop_clk:
7607         clk_disable_unprepare(priv->gop_clk);
7608 err_pp_clk:
7609         clk_disable_unprepare(priv->pp_clk);
7610         return err;
7611 }
7612
7613 static int mvpp2_remove(struct platform_device *pdev)
7614 {
7615         struct mvpp2 *priv = platform_get_drvdata(pdev);
7616         struct fwnode_handle *fwnode = pdev->dev.fwnode;
7617         int i = 0, poolnum = MVPP2_BM_POOLS_NUM;
7618         struct fwnode_handle *port_fwnode;
7619
7620         mvpp2_dbgfs_cleanup(priv);
7621
7622         fwnode_for_each_available_child_node(fwnode, port_fwnode) {
7623                 if (priv->port_list[i]) {
7624                         mutex_destroy(&priv->port_list[i]->gather_stats_lock);
7625                         mvpp2_port_remove(priv->port_list[i]);
7626                 }
7627                 i++;
7628         }
7629
7630         destroy_workqueue(priv->stats_queue);
7631
7632         if (priv->percpu_pools)
7633                 poolnum = mvpp2_get_nrxqs(priv) * 2;
7634
7635         for (i = 0; i < poolnum; i++) {
7636                 struct mvpp2_bm_pool *bm_pool = &priv->bm_pools[i];
7637
7638                 mvpp2_bm_pool_destroy(&pdev->dev, priv, bm_pool);
7639         }
7640
7641         for (i = 0; i < MVPP2_MAX_THREADS; i++) {
7642                 struct mvpp2_tx_queue *aggr_txq = &priv->aggr_txqs[i];
7643
7644                 dma_free_coherent(&pdev->dev,
7645                                   MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE,
7646                                   aggr_txq->descs,
7647                                   aggr_txq->descs_dma);
7648         }
7649
7650         if (is_acpi_node(port_fwnode))
7651                 return 0;
7652
7653         clk_disable_unprepare(priv->axi_clk);
7654         clk_disable_unprepare(priv->mg_core_clk);
7655         clk_disable_unprepare(priv->mg_clk);
7656         clk_disable_unprepare(priv->pp_clk);
7657         clk_disable_unprepare(priv->gop_clk);
7658
7659         return 0;
7660 }
7661
7662 static const struct of_device_id mvpp2_match[] = {
7663         {
7664                 .compatible = "marvell,armada-375-pp2",
7665                 .data = (void *)MVPP21,
7666         },
7667         {
7668                 .compatible = "marvell,armada-7k-pp22",
7669                 .data = (void *)MVPP22,
7670         },
7671         { }
7672 };
7673 MODULE_DEVICE_TABLE(of, mvpp2_match);
7674
7675 #ifdef CONFIG_ACPI
7676 static const struct acpi_device_id mvpp2_acpi_match[] = {
7677         { "MRVL0110", MVPP22 },
7678         { },
7679 };
7680 MODULE_DEVICE_TABLE(acpi, mvpp2_acpi_match);
7681 #endif
7682
7683 static struct platform_driver mvpp2_driver = {
7684         .probe = mvpp2_probe,
7685         .remove = mvpp2_remove,
7686         .driver = {
7687                 .name = MVPP2_DRIVER_NAME,
7688                 .of_match_table = mvpp2_match,
7689                 .acpi_match_table = ACPI_PTR(mvpp2_acpi_match),
7690         },
7691 };
7692
7693 module_platform_driver(mvpp2_driver);
7694
7695 MODULE_DESCRIPTION("Marvell PPv2 Ethernet Driver - www.marvell.com");
7696 MODULE_AUTHOR("Marcin Wojtas <mw@semihalf.com>");
7697 MODULE_LICENSE("GPL v2");