drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Driver for Marvell PPv2 network controller for Armada 375 SoC.
   4  *
   5  * Copyright (C) 2014 Marvell
   6  *
   7  * Marcin Wojtas <mw@semihalf.com>
   8  */
   9
  10 #include <linux/acpi.h>
  11 #include <linux/kernel.h>
  12 #include <linux/netdevice.h>
  13 #include <linux/etherdevice.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/skbuff.h>
  16 #include <linux/inetdevice.h>
  17 #include <linux/mbus.h>
  18 #include <linux/module.h>
  19 #include <linux/mfd/syscon.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/cpumask.h>
  22 #include <linux/of.h>
  23 #include <linux/of_irq.h>
  24 #include <linux/of_mdio.h>
  25 #include <linux/of_net.h>
  26 #include <linux/of_address.h>
  27 #include <linux/of_device.h>
  28 #include <linux/phy.h>
  29 #include <linux/phylink.h>
  30 #include <linux/phy/phy.h>
  31 #include <linux/ptp_classify.h>
  32 #include <linux/clk.h>
  33 #include <linux/hrtimer.h>
  34 #include <linux/ktime.h>
  35 #include <linux/regmap.h>
  36 #include <uapi/linux/ppp_defs.h>
  37 #include <net/ip.h>
  38 #include <net/ipv6.h>
  39 #include <net/tso.h>
  40 #include <linux/bpf_trace.h>
  41
  42 #include "mvpp2.h"
  43 #include "mvpp2_prs.h"
  44 #include "mvpp2_cls.h"
  45
  46 enum mvpp2_bm_pool_log_num {
  47         MVPP2_BM_SHORT,
  48         MVPP2_BM_LONG,
  49         MVPP2_BM_JUMBO,
  50         MVPP2_BM_POOLS_NUM
  51 };
  52
  53 static struct {
  54         int pkt_size;
  55         int buf_num;
  56 } mvpp2_pools[MVPP2_BM_POOLS_NUM];
  57
  58 /* The prototype is added here to be used in start_dev when using ACPI. This
  59  * will be removed once phylink is used for all modes (dt+ACPI).
  60  */
  61 static void mvpp2_acpi_start(struct mvpp2_port *port);
  62
  63 /* Queue modes */
  64 #define MVPP2_QDIST_SINGLE_MODE 0
  65 #define MVPP2_QDIST_MULTI_MODE  1
  66
  67 static int queue_mode = MVPP2_QDIST_MULTI_MODE;
  68
  69 module_param(queue_mode, int, 0444);
  70 MODULE_PARM_DESC(queue_mode, "Set queue_mode (single=0, multi=1)");
  71
  72 /* Utility/helper methods */
  73
  74 void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data)
  75 {
  76         writel(data, priv->swth_base[0] + offset);
  77 }
  78
  79 u32 mvpp2_read(struct mvpp2 *priv, u32 offset)
  80 {
  81         return readl(priv->swth_base[0] + offset);
  82 }
  83
  84 static u32 mvpp2_read_relaxed(struct mvpp2 *priv, u32 offset)
  85 {
  86         return readl_relaxed(priv->swth_base[0] + offset);
  87 }
  88
  89 static inline u32 mvpp2_cpu_to_thread(struct mvpp2 *priv, int cpu)
  90 {
  91         return cpu % priv->nthreads;
  92 }
  93
  94 static void mvpp2_cm3_write(struct mvpp2 *priv, u32 offset, u32 data)
  95 {
  96         writel(data, priv->cm3_base + offset);
  97 }
  98
  99 static u32 mvpp2_cm3_read(struct mvpp2 *priv, u32 offset)
 100 {
 101         return readl(priv->cm3_base + offset);
 102 }
 103
 104 static struct page_pool *
 105 mvpp2_create_page_pool(struct device *dev, int num, int len,
 106                        enum dma_data_direction dma_dir)
 107 {
 108         struct page_pool_params pp_params = {
 109                 /* internal DMA mapping in page_pool */
 110                 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV,
 111                 .pool_size = num,
 112                 .nid = NUMA_NO_NODE,
 113                 .dev = dev,
 114                 .dma_dir = dma_dir,
 115                 .offset = MVPP2_SKB_HEADROOM,
 116                 .max_len = len,
 117         };
 118
 119         return page_pool_create(&pp_params);
 120 }
 121
 122 /* These accessors should be used to access:
 123  *
 124  * - per-thread registers, where each thread has its own copy of the
 125  *   register.
 126  *
 127  *   MVPP2_BM_VIRT_ALLOC_REG
 128  *   MVPP2_BM_ADDR_HIGH_ALLOC
 129  *   MVPP22_BM_ADDR_HIGH_RLS_REG
 130  *   MVPP2_BM_VIRT_RLS_REG
 131  *   MVPP2_ISR_RX_TX_CAUSE_REG
 132  *   MVPP2_ISR_RX_TX_MASK_REG
 133  *   MVPP2_TXQ_NUM_REG
 134  *   MVPP2_AGGR_TXQ_UPDATE_REG
 135  *   MVPP2_TXQ_RSVD_REQ_REG
 136  *   MVPP2_TXQ_RSVD_RSLT_REG
 137  *   MVPP2_TXQ_SENT_REG
 138  *   MVPP2_RXQ_NUM_REG
 139  *
 140  * - global registers that must be accessed through a specific thread
 141  *   window, because they are related to an access to a per-thread
 142  *   register
 143  *
 144  *   MVPP2_BM_PHY_ALLOC_REG    (related to MVPP2_BM_VIRT_ALLOC_REG)
 145  *   MVPP2_BM_PHY_RLS_REG      (related to MVPP2_BM_VIRT_RLS_REG)
 146  *   MVPP2_RXQ_THRESH_REG      (related to MVPP2_RXQ_NUM_REG)
 147  *   MVPP2_RXQ_DESC_ADDR_REG   (related to MVPP2_RXQ_NUM_REG)
 148  *   MVPP2_RXQ_DESC_SIZE_REG   (related to MVPP2_RXQ_NUM_REG)
 149  *   MVPP2_RXQ_INDEX_REG       (related to MVPP2_RXQ_NUM_REG)
 150  *   MVPP2_TXQ_PENDING_REG     (related to MVPP2_TXQ_NUM_REG)
 151  *   MVPP2_TXQ_DESC_ADDR_REG   (related to MVPP2_TXQ_NUM_REG)
 152  *   MVPP2_TXQ_DESC_SIZE_REG   (related to MVPP2_TXQ_NUM_REG)
 153  *   MVPP2_TXQ_INDEX_REG       (related to MVPP2_TXQ_NUM_REG)
 154  *   MVPP2_TXQ_PENDING_REG     (related to MVPP2_TXQ_NUM_REG)
 155  *   MVPP2_TXQ_PREF_BUF_REG    (related to MVPP2_TXQ_NUM_REG)
 156  *   MVPP2_TXQ_PREF_BUF_REG    (related to MVPP2_TXQ_NUM_REG)
 157  */
 158 static void mvpp2_thread_write(struct mvpp2 *priv, unsigned int thread,
 159                                u32 offset, u32 data)
 160 {
 161         writel(data, priv->swth_base[thread] + offset);
 162 }
 163
 164 static u32 mvpp2_thread_read(struct mvpp2 *priv, unsigned int thread,
 165                              u32 offset)
 166 {
 167         return readl(priv->swth_base[thread] + offset);
 168 }
 169
 170 static void mvpp2_thread_write_relaxed(struct mvpp2 *priv, unsigned int thread,
 171                                        u32 offset, u32 data)
 172 {
 173         writel_relaxed(data, priv->swth_base[thread] + offset);
 174 }
 175
 176 static u32 mvpp2_thread_read_relaxed(struct mvpp2 *priv, unsigned int thread,
 177                                      u32 offset)
 178 {
 179         return readl_relaxed(priv->swth_base[thread] + offset);
 180 }
 181
 182 static dma_addr_t mvpp2_txdesc_dma_addr_get(struct mvpp2_port *port,
 183                                             struct mvpp2_tx_desc *tx_desc)
 184 {
 185         if (port->priv->hw_version == MVPP21)
 186                 return le32_to_cpu(tx_desc->pp21.buf_dma_addr);
 187         else
 188                 return le64_to_cpu(tx_desc->pp22.buf_dma_addr_ptp) &
 189                        MVPP2_DESC_DMA_MASK;
 190 }
 191
 192 static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port,
 193                                       struct mvpp2_tx_desc *tx_desc,
 194                                       dma_addr_t dma_addr)
 195 {
 196         dma_addr_t addr, offset;
 197
 198         addr = dma_addr & ~MVPP2_TX_DESC_ALIGN;
 199         offset = dma_addr & MVPP2_TX_DESC_ALIGN;
 200
 201         if (port->priv->hw_version == MVPP21) {
 202                 tx_desc->pp21.buf_dma_addr = cpu_to_le32(addr);
 203                 tx_desc->pp21.packet_offset = offset;
 204         } else {
 205                 __le64 val = cpu_to_le64(addr);
 206
 207                 tx_desc->pp22.buf_dma_addr_ptp &= ~cpu_to_le64(MVPP2_DESC_DMA_MASK);
 208                 tx_desc->pp22.buf_dma_addr_ptp |= val;
 209                 tx_desc->pp22.packet_offset = offset;
 210         }
 211 }
 212
 213 static size_t mvpp2_txdesc_size_get(struct mvpp2_port *port,
 214                                     struct mvpp2_tx_desc *tx_desc)
 215 {
 216         if (port->priv->hw_version == MVPP21)
 217                 return le16_to_cpu(tx_desc->pp21.data_size);
 218         else
 219                 return le16_to_cpu(tx_desc->pp22.data_size);
 220 }
 221
 222 static void mvpp2_txdesc_size_set(struct mvpp2_port *port,
 223                                   struct mvpp2_tx_desc *tx_desc,
 224                                   size_t size)
 225 {
 226         if (port->priv->hw_version == MVPP21)
 227                 tx_desc->pp21.data_size = cpu_to_le16(size);
 228         else
 229                 tx_desc->pp22.data_size = cpu_to_le16(size);
 230 }
 231
 232 static void mvpp2_txdesc_txq_set(struct mvpp2_port *port,
 233                                  struct mvpp2_tx_desc *tx_desc,
 234                                  unsigned int txq)
 235 {
 236         if (port->priv->hw_version == MVPP21)
 237                 tx_desc->pp21.phys_txq = txq;
 238         else
 239                 tx_desc->pp22.phys_txq = txq;
 240 }
 241
 242 static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port,
 243                                  struct mvpp2_tx_desc *tx_desc,
 244                                  unsigned int command)
 245 {
 246         if (port->priv->hw_version == MVPP21)
 247                 tx_desc->pp21.command = cpu_to_le32(command);
 248         else
 249                 tx_desc->pp22.command = cpu_to_le32(command);
 250 }
 251
 252 static unsigned int mvpp2_txdesc_offset_get(struct mvpp2_port *port,
 253                                             struct mvpp2_tx_desc *tx_desc)
 254 {
 255         if (port->priv->hw_version == MVPP21)
 256                 return tx_desc->pp21.packet_offset;
 257         else
 258                 return tx_desc->pp22.packet_offset;
 259 }
 260
 261 static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port,
 262                                             struct mvpp2_rx_desc *rx_desc)
 263 {
 264         if (port->priv->hw_version == MVPP21)
 265                 return le32_to_cpu(rx_desc->pp21.buf_dma_addr);
 266         else
 267                 return le64_to_cpu(rx_desc->pp22.buf_dma_addr_key_hash) &
 268                        MVPP2_DESC_DMA_MASK;
 269 }
 270
 271 static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port,
 272                                              struct mvpp2_rx_desc *rx_desc)
 273 {
 274         if (port->priv->hw_version == MVPP21)
 275                 return le32_to_cpu(rx_desc->pp21.buf_cookie);
 276         else
 277                 return le64_to_cpu(rx_desc->pp22.buf_cookie_misc) &
 278                        MVPP2_DESC_DMA_MASK;
 279 }
 280
 281 static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port,
 282                                     struct mvpp2_rx_desc *rx_desc)
 283 {
 284         if (port->priv->hw_version == MVPP21)
 285                 return le16_to_cpu(rx_desc->pp21.data_size);
 286         else
 287                 return le16_to_cpu(rx_desc->pp22.data_size);
 288 }
 289
 290 static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port,
 291                                    struct mvpp2_rx_desc *rx_desc)
 292 {
 293         if (port->priv->hw_version == MVPP21)
 294                 return le32_to_cpu(rx_desc->pp21.status);
 295         else
 296                 return le32_to_cpu(rx_desc->pp22.status);
 297 }
 298
 299 static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu)
 300 {
 301         txq_pcpu->txq_get_index++;
 302         if (txq_pcpu->txq_get_index == txq_pcpu->size)
 303                 txq_pcpu->txq_get_index = 0;
 304 }
 305
 306 static void mvpp2_txq_inc_put(struct mvpp2_port *port,
 307                               struct mvpp2_txq_pcpu *txq_pcpu,
 308                               void *data,
 309                               struct mvpp2_tx_desc *tx_desc,
 310                               enum mvpp2_tx_buf_type buf_type)
 311 {
 312         struct mvpp2_txq_pcpu_buf *tx_buf =
 313                 txq_pcpu->buffs + txq_pcpu->txq_put_index;
 314         tx_buf->type = buf_type;
 315         if (buf_type == MVPP2_TYPE_SKB)
 316                 tx_buf->skb = data;
 317         else
 318                 tx_buf->xdpf = data;
 319         tx_buf->size = mvpp2_txdesc_size_get(port, tx_desc);
 320         tx_buf->dma = mvpp2_txdesc_dma_addr_get(port, tx_desc) +
 321                 mvpp2_txdesc_offset_get(port, tx_desc);
 322         txq_pcpu->txq_put_index++;
 323         if (txq_pcpu->txq_put_index == txq_pcpu->size)
 324                 txq_pcpu->txq_put_index = 0;
 325 }
 326
 327 /* Get number of maximum RXQ */
 328 static int mvpp2_get_nrxqs(struct mvpp2 *priv)
 329 {
 330         unsigned int nrxqs;
 331
 332         if (priv->hw_version >= MVPP22 && queue_mode == MVPP2_QDIST_SINGLE_MODE)
 333                 return 1;
 334
 335         /* According to the PPv2.2 datasheet and our experiments on
 336          * PPv2.1, RX queues have an allocation granularity of 4 (when
 337          * more than a single one on PPv2.2).
 338          * Round up to nearest multiple of 4.
 339          */
 340         nrxqs = (num_possible_cpus() + 3) & ~0x3;
 341         if (nrxqs > MVPP2_PORT_MAX_RXQ)
 342                 nrxqs = MVPP2_PORT_MAX_RXQ;
 343
 344         return nrxqs;
 345 }
 346
 347 /* Get number of physical egress port */
 348 static inline int mvpp2_egress_port(struct mvpp2_port *port)
 349 {
 350         return MVPP2_MAX_TCONT + port->id;
 351 }
 352
 353 /* Get number of physical TXQ */
 354 static inline int mvpp2_txq_phys(int port, int txq)
 355 {
 356         return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq;
 357 }
 358
 359 /* Returns a struct page if page_pool is set, otherwise a buffer */
 360 static void *mvpp2_frag_alloc(const struct mvpp2_bm_pool *pool,
 361                               struct page_pool *page_pool)
 362 {
 363         if (page_pool)
 364                 return page_pool_dev_alloc_pages(page_pool);
 365
 366         if (likely(pool->frag_size <= PAGE_SIZE))
 367                 return netdev_alloc_frag(pool->frag_size);
 368
 369         return kmalloc(pool->frag_size, GFP_ATOMIC);
 370 }
 371
 372 static void mvpp2_frag_free(const struct mvpp2_bm_pool *pool,
 373                             struct page_pool *page_pool, void *data)
 374 {
 375         if (page_pool)
 376                 page_pool_put_full_page(page_pool, virt_to_head_page(data), false);
 377         else if (likely(pool->frag_size <= PAGE_SIZE))
 378                 skb_free_frag(data);
 379         else
 380                 kfree(data);
 381 }
 382
 383 /* Buffer Manager configuration routines */
 384
 385 /* Create pool */
 386 static int mvpp2_bm_pool_create(struct device *dev, struct mvpp2 *priv,
 387                                 struct mvpp2_bm_pool *bm_pool, int size)
 388 {
 389         u32 val;
 390
 391         /* Number of buffer pointers must be a multiple of 16, as per
 392          * hardware constraints
 393          */
 394         if (!IS_ALIGNED(size, 16))
 395                 return -EINVAL;
 396
 397         /* PPv2.1 needs 8 bytes per buffer pointer, PPv2.2 and PPv2.3 needs 16
 398          * bytes per buffer pointer
 399          */
 400         if (priv->hw_version == MVPP21)
 401                 bm_pool->size_bytes = 2 * sizeof(u32) * size;
 402         else
 403                 bm_pool->size_bytes = 2 * sizeof(u64) * size;
 404
 405         bm_pool->virt_addr = dma_alloc_coherent(dev, bm_pool->size_bytes,
 406                                                 &bm_pool->dma_addr,
 407                                                 GFP_KERNEL);
 408         if (!bm_pool->virt_addr)
 409                 return -ENOMEM;
 410
 411         if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr,
 412                         MVPP2_BM_POOL_PTR_ALIGN)) {
 413                 dma_free_coherent(dev, bm_pool->size_bytes,
 414                                   bm_pool->virt_addr, bm_pool->dma_addr);
 415                 dev_err(dev, "BM pool %d is not %d bytes aligned\n",
 416                         bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN);
 417                 return -ENOMEM;
 418         }
 419
 420         mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id),
 421                     lower_32_bits(bm_pool->dma_addr));
 422         mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size);
 423
 424         val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
 425         val |= MVPP2_BM_START_MASK;
 426
 427         val &= ~MVPP2_BM_LOW_THRESH_MASK;
 428         val &= ~MVPP2_BM_HIGH_THRESH_MASK;
 429
 430         /* Set 8 Pools BPPI threshold for MVPP23 */
 431         if (priv->hw_version == MVPP23) {
 432                 val |= MVPP2_BM_LOW_THRESH_VALUE(MVPP23_BM_BPPI_LOW_THRESH);
 433                 val |= MVPP2_BM_HIGH_THRESH_VALUE(MVPP23_BM_BPPI_HIGH_THRESH);
 434         } else {
 435                 val |= MVPP2_BM_LOW_THRESH_VALUE(MVPP2_BM_BPPI_LOW_THRESH);
 436                 val |= MVPP2_BM_HIGH_THRESH_VALUE(MVPP2_BM_BPPI_HIGH_THRESH);
 437         }
 438
 439         mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
 440
 441         bm_pool->size = size;
 442         bm_pool->pkt_size = 0;
 443         bm_pool->buf_num = 0;
 444
 445         return 0;
 446 }
 447
 448 /* Set pool buffer size */
 449 static void mvpp2_bm_pool_bufsize_set(struct mvpp2 *priv,
 450                                       struct mvpp2_bm_pool *bm_pool,
 451                                       int buf_size)
 452 {
 453         u32 val;
 454
 455         bm_pool->buf_size = buf_size;
 456
 457         val = ALIGN(buf_size, 1 << MVPP2_POOL_BUF_SIZE_OFFSET);
 458         mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val);
 459 }
 460
 461 static void mvpp2_bm_bufs_get_addrs(struct device *dev, struct mvpp2 *priv,
 462                                     struct mvpp2_bm_pool *bm_pool,
 463                                     dma_addr_t *dma_addr,
 464                                     phys_addr_t *phys_addr)
 465 {
 466         unsigned int thread = mvpp2_cpu_to_thread(priv, get_cpu());
 467
 468         *dma_addr = mvpp2_thread_read(priv, thread,
 469                                       MVPP2_BM_PHY_ALLOC_REG(bm_pool->id));
 470         *phys_addr = mvpp2_thread_read(priv, thread, MVPP2_BM_VIRT_ALLOC_REG);
 471
 472         if (priv->hw_version >= MVPP22) {
 473                 u32 val;
 474                 u32 dma_addr_highbits, phys_addr_highbits;
 475
 476                 val = mvpp2_thread_read(priv, thread, MVPP22_BM_ADDR_HIGH_ALLOC);
 477                 dma_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_PHYS_MASK);
 478                 phys_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_VIRT_MASK) >>
 479                         MVPP22_BM_ADDR_HIGH_VIRT_SHIFT;
 480
 481                 if (sizeof(dma_addr_t) == 8)
 482                         *dma_addr |= (u64)dma_addr_highbits << 32;
 483
 484                 if (sizeof(phys_addr_t) == 8)
 485                         *phys_addr |= (u64)phys_addr_highbits << 32;
 486         }
 487
 488         put_cpu();
 489 }
 490
 491 /* Free all buffers from the pool */
 492 static void mvpp2_bm_bufs_free(struct device *dev, struct mvpp2 *priv,
 493                                struct mvpp2_bm_pool *bm_pool, int buf_num)
 494 {
 495         struct page_pool *pp = NULL;
 496         int i;
 497
 498         if (buf_num > bm_pool->buf_num) {
 499                 WARN(1, "Pool does not have so many bufs pool(%d) bufs(%d)\n",
 500                      bm_pool->id, buf_num);
 501                 buf_num = bm_pool->buf_num;
 502         }
 503
 504         if (priv->percpu_pools)
 505                 pp = priv->page_pool[bm_pool->id];
 506
 507         for (i = 0; i < buf_num; i++) {
 508                 dma_addr_t buf_dma_addr;
 509                 phys_addr_t buf_phys_addr;
 510                 void *data;
 511
 512                 mvpp2_bm_bufs_get_addrs(dev, priv, bm_pool,
 513                                         &buf_dma_addr, &buf_phys_addr);
 514
 515                 if (!pp)
 516                         dma_unmap_single(dev, buf_dma_addr,
 517                                          bm_pool->buf_size, DMA_FROM_DEVICE);
 518
 519                 data = (void *)phys_to_virt(buf_phys_addr);
 520                 if (!data)
 521                         break;
 522
 523                 mvpp2_frag_free(bm_pool, pp, data);
 524         }
 525
 526         /* Update BM driver with number of buffers removed from pool */
 527         bm_pool->buf_num -= i;
 528 }
 529
 530 /* Check number of buffers in BM pool */
 531 static int mvpp2_check_hw_buf_num(struct mvpp2 *priv, struct mvpp2_bm_pool *bm_pool)
 532 {
 533         int buf_num = 0;
 534
 535         buf_num += mvpp2_read(priv, MVPP2_BM_POOL_PTRS_NUM_REG(bm_pool->id)) &
 536                                     MVPP22_BM_POOL_PTRS_NUM_MASK;
 537         buf_num += mvpp2_read(priv, MVPP2_BM_BPPI_PTRS_NUM_REG(bm_pool->id)) &
 538                                     MVPP2_BM_BPPI_PTR_NUM_MASK;
 539
 540         /* HW has one buffer ready which is not reflected in the counters */
 541         if (buf_num)
 542                 buf_num += 1;
 543
 544         return buf_num;
 545 }
 546
 547 /* Cleanup pool */
 548 static int mvpp2_bm_pool_destroy(struct device *dev, struct mvpp2 *priv,
 549                                  struct mvpp2_bm_pool *bm_pool)
 550 {
 551         int buf_num;
 552         u32 val;
 553
 554         buf_num = mvpp2_check_hw_buf_num(priv, bm_pool);
 555         mvpp2_bm_bufs_free(dev, priv, bm_pool, buf_num);
 556
 557         /* Check buffer counters after free */
 558         buf_num = mvpp2_check_hw_buf_num(priv, bm_pool);
 559         if (buf_num) {
 560                 WARN(1, "cannot free all buffers in pool %d, buf_num left %d\n",
 561                      bm_pool->id, bm_pool->buf_num);
 562                 return 0;
 563         }
 564
 565         val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
 566         val |= MVPP2_BM_STOP_MASK;
 567         mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
 568
 569         if (priv->percpu_pools) {
 570                 page_pool_destroy(priv->page_pool[bm_pool->id]);
 571                 priv->page_pool[bm_pool->id] = NULL;
 572         }
 573
 574         dma_free_coherent(dev, bm_pool->size_bytes,
 575                           bm_pool->virt_addr,
 576                           bm_pool->dma_addr);
 577         return 0;
 578 }
 579
 580 static int mvpp2_bm_pools_init(struct device *dev, struct mvpp2 *priv)
 581 {
 582         int i, err, size, poolnum = MVPP2_BM_POOLS_NUM;
 583         struct mvpp2_bm_pool *bm_pool;
 584
 585         if (priv->percpu_pools)
 586                 poolnum = mvpp2_get_nrxqs(priv) * 2;
 587
 588         /* Create all pools with maximum size */
 589         size = MVPP2_BM_POOL_SIZE_MAX;
 590         for (i = 0; i < poolnum; i++) {
 591                 bm_pool = &priv->bm_pools[i];
 592                 bm_pool->id = i;
 593                 err = mvpp2_bm_pool_create(dev, priv, bm_pool, size);
 594                 if (err)
 595                         goto err_unroll_pools;
 596                 mvpp2_bm_pool_bufsize_set(priv, bm_pool, 0);
 597         }
 598         return 0;
 599
 600 err_unroll_pools:
 601         dev_err(dev, "failed to create BM pool %d, size %d\n", i, size);
 602         for (i = i - 1; i >= 0; i--)
 603                 mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]);
 604         return err;
 605 }
 606
 607 /* Routine enable PPv23 8 pool mode */
 608 static void mvpp23_bm_set_8pool_mode(struct mvpp2 *priv)
 609 {
 610         int val;
 611
 612         val = mvpp2_read(priv, MVPP22_BM_POOL_BASE_ADDR_HIGH_REG);
 613         val |= MVPP23_BM_8POOL_MODE;
 614         mvpp2_write(priv, MVPP22_BM_POOL_BASE_ADDR_HIGH_REG, val);
 615 }
 616
 617 static int mvpp2_bm_init(struct device *dev, struct mvpp2 *priv)
 618 {
 619         enum dma_data_direction dma_dir = DMA_FROM_DEVICE;
 620         int i, err, poolnum = MVPP2_BM_POOLS_NUM;
 621         struct mvpp2_port *port;
 622
 623         if (priv->percpu_pools) {
 624                 for (i = 0; i < priv->port_count; i++) {
 625                         port = priv->port_list[i];
 626                         if (port->xdp_prog) {
 627                                 dma_dir = DMA_BIDIRECTIONAL;
 628                                 break;
 629                         }
 630                 }
 631
 632                 poolnum = mvpp2_get_nrxqs(priv) * 2;
 633                 for (i = 0; i < poolnum; i++) {
 634                         /* the pool in use */
 635                         int pn = i / (poolnum / 2);
 636
 637                         priv->page_pool[i] =
 638                                 mvpp2_create_page_pool(dev,
 639                                                        mvpp2_pools[pn].buf_num,
 640                                                        mvpp2_pools[pn].pkt_size,
 641                                                        dma_dir);
 642                         if (IS_ERR(priv->page_pool[i])) {
 643                                 int j;
 644
 645                                 for (j = 0; j < i; j++) {
 646                                         page_pool_destroy(priv->page_pool[j]);
 647                                         priv->page_pool[j] = NULL;
 648                                 }
 649                                 return PTR_ERR(priv->page_pool[i]);
 650                         }
 651                 }
 652         }
 653
 654         dev_info(dev, "using %d %s buffers\n", poolnum,
 655                  priv->percpu_pools ? "per-cpu" : "shared");
 656
 657         for (i = 0; i < poolnum; i++) {
 658                 /* Mask BM all interrupts */
 659                 mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0);
 660                 /* Clear BM cause register */
 661                 mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0);
 662         }
 663
 664         /* Allocate and initialize BM pools */
 665         priv->bm_pools = devm_kcalloc(dev, poolnum,
 666                                       sizeof(*priv->bm_pools), GFP_KERNEL);
 667         if (!priv->bm_pools)
 668                 return -ENOMEM;
 669
 670         if (priv->hw_version == MVPP23)
 671                 mvpp23_bm_set_8pool_mode(priv);
 672
 673         err = mvpp2_bm_pools_init(dev, priv);
 674         if (err < 0)
 675                 return err;
 676         return 0;
 677 }
 678
 679 static void mvpp2_setup_bm_pool(void)
 680 {
 681         /* Short pool */
 682         mvpp2_pools[MVPP2_BM_SHORT].buf_num  = MVPP2_BM_SHORT_BUF_NUM;
 683         mvpp2_pools[MVPP2_BM_SHORT].pkt_size = MVPP2_BM_SHORT_PKT_SIZE;
 684
 685         /* Long pool */
 686         mvpp2_pools[MVPP2_BM_LONG].buf_num  = MVPP2_BM_LONG_BUF_NUM;
 687         mvpp2_pools[MVPP2_BM_LONG].pkt_size = MVPP2_BM_LONG_PKT_SIZE;
 688
 689         /* Jumbo pool */
 690         mvpp2_pools[MVPP2_BM_JUMBO].buf_num  = MVPP2_BM_JUMBO_BUF_NUM;
 691         mvpp2_pools[MVPP2_BM_JUMBO].pkt_size = MVPP2_BM_JUMBO_PKT_SIZE;
 692 }
 693
 694 /* Attach long pool to rxq */
 695 static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port,
 696                                     int lrxq, int long_pool)
 697 {
 698         u32 val, mask;
 699         int prxq;
 700
 701         /* Get queue physical ID */
 702         prxq = port->rxqs[lrxq]->id;
 703
 704         if (port->priv->hw_version == MVPP21)
 705                 mask = MVPP21_RXQ_POOL_LONG_MASK;
 706         else
 707                 mask = MVPP22_RXQ_POOL_LONG_MASK;
 708
 709         val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
 710         val &= ~mask;
 711         val |= (long_pool << MVPP2_RXQ_POOL_LONG_OFFS) & mask;
 712         mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
 713 }
 714
 715 /* Attach short pool to rxq */
 716 static void mvpp2_rxq_short_pool_set(struct mvpp2_port *port,
 717                                      int lrxq, int short_pool)
 718 {
 719         u32 val, mask;
 720         int prxq;
 721
 722         /* Get queue physical ID */
 723         prxq = port->rxqs[lrxq]->id;
 724
 725         if (port->priv->hw_version == MVPP21)
 726                 mask = MVPP21_RXQ_POOL_SHORT_MASK;
 727         else
 728                 mask = MVPP22_RXQ_POOL_SHORT_MASK;
 729
 730         val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
 731         val &= ~mask;
 732         val |= (short_pool << MVPP2_RXQ_POOL_SHORT_OFFS) & mask;
 733         mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
 734 }
 735
 736 static void *mvpp2_buf_alloc(struct mvpp2_port *port,
 737                              struct mvpp2_bm_pool *bm_pool,
 738                              struct page_pool *page_pool,
 739                              dma_addr_t *buf_dma_addr,
 740                              phys_addr_t *buf_phys_addr,
 741                              gfp_t gfp_mask)
 742 {
 743         dma_addr_t dma_addr;
 744         struct page *page;
 745         void *data;
 746
 747         data = mvpp2_frag_alloc(bm_pool, page_pool);
 748         if (!data)
 749                 return NULL;
 750
 751         if (page_pool) {
 752                 page = (struct page *)data;
 753                 dma_addr = page_pool_get_dma_addr(page);
 754                 data = page_to_virt(page);
 755         } else {
 756                 dma_addr = dma_map_single(port->dev->dev.parent, data,
 757                                           MVPP2_RX_BUF_SIZE(bm_pool->pkt_size),
 758                                           DMA_FROM_DEVICE);
 759                 if (unlikely(dma_mapping_error(port->dev->dev.parent, dma_addr))) {
 760                         mvpp2_frag_free(bm_pool, NULL, data);
 761                         return NULL;
 762                 }
 763         }
 764         *buf_dma_addr = dma_addr;
 765         *buf_phys_addr = virt_to_phys(data);
 766
 767         return data;
 768 }
 769
 770 /* Routine enable flow control for RXQs condition */
 771 static void mvpp2_rxq_enable_fc(struct mvpp2_port *port)
 772 {
 773         int val, cm3_state, host_id, q;
 774         int fq = port->first_rxq;
 775         unsigned long flags;
 776
 777         spin_lock_irqsave(&port->priv->mss_spinlock, flags);
 778
 779         /* Remove Flow control enable bit to prevent race between FW and Kernel
 780          * If Flow control was enabled, it would be re-enabled.
 781          */
 782         val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG);
 783         cm3_state = (val & FLOW_CONTROL_ENABLE_BIT);
 784         val &= ~FLOW_CONTROL_ENABLE_BIT;
 785         mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val);
 786
 787         /* Set same Flow control for all RXQs */
 788         for (q = 0; q < port->nrxqs; q++) {
 789                 /* Set stop and start Flow control RXQ thresholds */
 790                 val = MSS_THRESHOLD_START;
 791                 val |= (MSS_THRESHOLD_STOP << MSS_RXQ_TRESH_STOP_OFFS);
 792                 mvpp2_cm3_write(port->priv, MSS_RXQ_TRESH_REG(q, fq), val);
 793
 794                 val = mvpp2_cm3_read(port->priv, MSS_RXQ_ASS_REG(q, fq));
 795                 /* Set RXQ port ID */
 796                 val &= ~(MSS_RXQ_ASS_PORTID_MASK << MSS_RXQ_ASS_Q_BASE(q, fq));
 797                 val |= (port->id << MSS_RXQ_ASS_Q_BASE(q, fq));
 798                 val &= ~(MSS_RXQ_ASS_HOSTID_MASK << (MSS_RXQ_ASS_Q_BASE(q, fq)
 799                         + MSS_RXQ_ASS_HOSTID_OFFS));
 800
 801                 /* Calculate RXQ host ID:
 802                  * In Single queue mode: Host ID equal to Host ID used for
 803                  *                       shared RX interrupt
 804                  * In Multi queue mode: Host ID equal to number of
 805                  *                      RXQ ID / number of CoS queues
 806                  * In Single resource mode: Host ID always equal to 0
 807                  */
 808                 if (queue_mode == MVPP2_QDIST_SINGLE_MODE)
 809                         host_id = port->nqvecs;
 810                 else if (queue_mode == MVPP2_QDIST_MULTI_MODE)
 811                         host_id = q;
 812                 else
 813                         host_id = 0;
 814
 815                 /* Set RXQ host ID */
 816                 val |= (host_id << (MSS_RXQ_ASS_Q_BASE(q, fq)
 817                         + MSS_RXQ_ASS_HOSTID_OFFS));
 818
 819                 mvpp2_cm3_write(port->priv, MSS_RXQ_ASS_REG(q, fq), val);
 820         }
 821
 822         /* Notify Firmware that Flow control config space ready for update */
 823         val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG);
 824         val |= FLOW_CONTROL_UPDATE_COMMAND_BIT;
 825         val |= cm3_state;
 826         mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val);
 827
 828         spin_unlock_irqrestore(&port->priv->mss_spinlock, flags);
 829 }
 830
 831 /* Routine disable flow control for RXQs condition */
 832 static void mvpp2_rxq_disable_fc(struct mvpp2_port *port)
 833 {
 834         int val, cm3_state, q;
 835         unsigned long flags;
 836         int fq = port->first_rxq;
 837
 838         spin_lock_irqsave(&port->priv->mss_spinlock, flags);
 839
 840         /* Remove Flow control enable bit to prevent race between FW and Kernel
 841          * If Flow control was enabled, it would be re-enabled.
 842          */
 843         val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG);
 844         cm3_state = (val & FLOW_CONTROL_ENABLE_BIT);
 845         val &= ~FLOW_CONTROL_ENABLE_BIT;
 846         mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val);
 847
 848         /* Disable Flow control for all RXQs */
 849         for (q = 0; q < port->nrxqs; q++) {
 850                 /* Set threshold 0 to disable Flow control */
 851                 val = 0;
 852                 val |= (0 << MSS_RXQ_TRESH_STOP_OFFS);
 853                 mvpp2_cm3_write(port->priv, MSS_RXQ_TRESH_REG(q, fq), val);
 854
 855                 val = mvpp2_cm3_read(port->priv, MSS_RXQ_ASS_REG(q, fq));
 856
 857                 val &= ~(MSS_RXQ_ASS_PORTID_MASK << MSS_RXQ_ASS_Q_BASE(q, fq));
 858
 859                 val &= ~(MSS_RXQ_ASS_HOSTID_MASK << (MSS_RXQ_ASS_Q_BASE(q, fq)
 860                         + MSS_RXQ_ASS_HOSTID_OFFS));
 861
 862                 mvpp2_cm3_write(port->priv, MSS_RXQ_ASS_REG(q, fq), val);
 863         }
 864
 865         /* Notify Firmware that Flow control config space ready for update */
 866         val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG);
 867         val |= FLOW_CONTROL_UPDATE_COMMAND_BIT;
 868         val |= cm3_state;
 869         mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val);
 870
 871         spin_unlock_irqrestore(&port->priv->mss_spinlock, flags);
 872 }
 873
 874 /* Routine disable/enable flow control for BM pool condition */
 875 static void mvpp2_bm_pool_update_fc(struct mvpp2_port *port,
 876                                     struct mvpp2_bm_pool *pool,
 877                                     bool en)
 878 {
 879         int val, cm3_state;
 880         unsigned long flags;
 881
 882         spin_lock_irqsave(&port->priv->mss_spinlock, flags);
 883
 884         /* Remove Flow control enable bit to prevent race between FW and Kernel
 885          * If Flow control were enabled, it would be re-enabled.
 886          */
 887         val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG);
 888         cm3_state = (val & FLOW_CONTROL_ENABLE_BIT);
 889         val &= ~FLOW_CONTROL_ENABLE_BIT;
 890         mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val);
 891
 892         /* Check if BM pool should be enabled/disable */
 893         if (en) {
 894                 /* Set BM pool start and stop thresholds per port */
 895                 val = mvpp2_cm3_read(port->priv, MSS_BUF_POOL_REG(pool->id));
 896                 val |= MSS_BUF_POOL_PORT_OFFS(port->id);
 897                 val &= ~MSS_BUF_POOL_START_MASK;
 898                 val |= (MSS_THRESHOLD_START << MSS_BUF_POOL_START_OFFS);
 899                 val &= ~MSS_BUF_POOL_STOP_MASK;
 900                 val |= MSS_THRESHOLD_STOP;
 901                 mvpp2_cm3_write(port->priv, MSS_BUF_POOL_REG(pool->id), val);
 902         } else {
 903                 /* Remove BM pool from the port */
 904                 val = mvpp2_cm3_read(port->priv, MSS_BUF_POOL_REG(pool->id));
 905                 val &= ~MSS_BUF_POOL_PORT_OFFS(port->id);
 906
 907                 /* Zero BM pool start and stop thresholds to disable pool
 908                  * flow control if pool empty (not used by any port)
 909                  */
 910                 if (!pool->buf_num) {
 911                         val &= ~MSS_BUF_POOL_START_MASK;
 912                         val &= ~MSS_BUF_POOL_STOP_MASK;
 913                 }
 914
 915                 mvpp2_cm3_write(port->priv, MSS_BUF_POOL_REG(pool->id), val);
 916         }
 917
 918         /* Notify Firmware that Flow control config space ready for update */
 919         val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG);
 920         val |= FLOW_CONTROL_UPDATE_COMMAND_BIT;
 921         val |= cm3_state;
 922         mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val);
 923
 924         spin_unlock_irqrestore(&port->priv->mss_spinlock, flags);
 925 }
 926
 927 /* disable/enable flow control for BM pool on all ports */
 928 static void mvpp2_bm_pool_update_priv_fc(struct mvpp2 *priv, bool en)
 929 {
 930         struct mvpp2_port *port;
 931         int i;
 932
 933         for (i = 0; i < priv->port_count; i++) {
 934                 port = priv->port_list[i];
 935                 if (port->priv->percpu_pools) {
 936                         for (i = 0; i < port->nrxqs; i++)
 937                                 mvpp2_bm_pool_update_fc(port, &port->priv->bm_pools[i],
 938                                                         port->tx_fc & en);
 939                 } else {
 940                         mvpp2_bm_pool_update_fc(port, port->pool_long, port->tx_fc & en);
 941                         mvpp2_bm_pool_update_fc(port, port->pool_short, port->tx_fc & en);
 942                 }
 943         }
 944 }
 945
 946 static int mvpp2_enable_global_fc(struct mvpp2 *priv)
 947 {
 948         int val, timeout = 0;
 949
 950         /* Enable global flow control. In this stage global
 951          * flow control enabled, but still disabled per port.
 952          */
 953         val = mvpp2_cm3_read(priv, MSS_FC_COM_REG);
 954         val |= FLOW_CONTROL_ENABLE_BIT;
 955         mvpp2_cm3_write(priv, MSS_FC_COM_REG, val);
 956
 957         /* Check if Firmware running and disable FC if not*/
 958         val |= FLOW_CONTROL_UPDATE_COMMAND_BIT;
 959         mvpp2_cm3_write(priv, MSS_FC_COM_REG, val);
 960
 961         while (timeout < MSS_FC_MAX_TIMEOUT) {
 962                 val = mvpp2_cm3_read(priv, MSS_FC_COM_REG);
 963
 964                 if (!(val & FLOW_CONTROL_UPDATE_COMMAND_BIT))
 965                         return 0;
 966                 usleep_range(10, 20);
 967                 timeout++;
 968         }
 969
 970         priv->global_tx_fc = false;
 971         return -EOPNOTSUPP;
 972 }
 973
 974 /* Release buffer to BM */
 975 static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
 976                                      dma_addr_t buf_dma_addr,
 977                                      phys_addr_t buf_phys_addr)
 978 {
 979         unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
 980         unsigned long flags = 0;
 981
 982         if (test_bit(thread, &port->priv->lock_map))
 983                 spin_lock_irqsave(&port->bm_lock[thread], flags);
 984
 985         if (port->priv->hw_version >= MVPP22) {
 986                 u32 val = 0;
 987
 988                 if (sizeof(dma_addr_t) == 8)
 989                         val |= upper_32_bits(buf_dma_addr) &
 990                                 MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK;
 991
 992                 if (sizeof(phys_addr_t) == 8)
 993                         val |= (upper_32_bits(buf_phys_addr)
 994                                 << MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT) &
 995                                 MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK;
 996
 997                 mvpp2_thread_write_relaxed(port->priv, thread,
 998                                            MVPP22_BM_ADDR_HIGH_RLS_REG, val);
 999         }
1000
1001         /* MVPP2_BM_VIRT_RLS_REG is not interpreted by HW, and simply
1002          * returned in the "cookie" field of the RX
1003          * descriptor. Instead of storing the virtual address, we
1004          * store the physical address
1005          */
1006         mvpp2_thread_write_relaxed(port->priv, thread,
1007                                    MVPP2_BM_VIRT_RLS_REG, buf_phys_addr);
1008         mvpp2_thread_write_relaxed(port->priv, thread,
1009                                    MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr);
1010
1011         if (test_bit(thread, &port->priv->lock_map))
1012                 spin_unlock_irqrestore(&port->bm_lock[thread], flags);
1013
1014         put_cpu();
1015 }
1016
1017 /* Allocate buffers for the pool */
1018 static int mvpp2_bm_bufs_add(struct mvpp2_port *port,
1019                              struct mvpp2_bm_pool *bm_pool, int buf_num)
1020 {
1021         int i, buf_size, total_size;
1022         dma_addr_t dma_addr;
1023         phys_addr_t phys_addr;
1024         struct page_pool *pp = NULL;
1025         void *buf;
1026
1027         if (port->priv->percpu_pools &&
1028             bm_pool->pkt_size > MVPP2_BM_LONG_PKT_SIZE) {
1029                 netdev_err(port->dev,
1030                            "attempted to use jumbo frames with per-cpu pools");
1031                 return 0;
1032         }
1033
1034         buf_size = MVPP2_RX_BUF_SIZE(bm_pool->pkt_size);
1035         total_size = MVPP2_RX_TOTAL_SIZE(buf_size);
1036
1037         if (buf_num < 0 ||
1038             (buf_num + bm_pool->buf_num > bm_pool->size)) {
1039                 netdev_err(port->dev,
1040                            "cannot allocate %d buffers for pool %d\n",
1041                            buf_num, bm_pool->id);
1042                 return 0;
1043         }
1044
1045         if (port->priv->percpu_pools)
1046                 pp = port->priv->page_pool[bm_pool->id];
1047         for (i = 0; i < buf_num; i++) {
1048                 buf = mvpp2_buf_alloc(port, bm_pool, pp, &dma_addr,
1049                                       &phys_addr, GFP_KERNEL);
1050                 if (!buf)
1051                         break;
1052
1053                 mvpp2_bm_pool_put(port, bm_pool->id, dma_addr,
1054                                   phys_addr);
1055         }
1056
1057         /* Update BM driver with number of buffers added to pool */
1058         bm_pool->buf_num += i;
1059
1060         netdev_dbg(port->dev,
1061                    "pool %d: pkt_size=%4d, buf_size=%4d, total_size=%4d\n",
1062                    bm_pool->id, bm_pool->pkt_size, buf_size, total_size);
1063
1064         netdev_dbg(port->dev,
1065                    "pool %d: %d of %d buffers added\n",
1066                    bm_pool->id, i, buf_num);
1067         return i;
1068 }
1069
1070 /* Notify the driver that BM pool is being used as specific type and return the
1071  * pool pointer on success
1072  */
1073 static struct mvpp2_bm_pool *
1074 mvpp2_bm_pool_use(struct mvpp2_port *port, unsigned pool, int pkt_size)
1075 {
1076         struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool];
1077         int num;
1078
1079         if ((port->priv->percpu_pools && pool > mvpp2_get_nrxqs(port->priv) * 2) ||
1080             (!port->priv->percpu_pools && pool >= MVPP2_BM_POOLS_NUM)) {
1081                 netdev_err(port->dev, "Invalid pool %d\n", pool);
1082                 return NULL;
1083         }
1084
1085         /* Allocate buffers in case BM pool is used as long pool, but packet
1086          * size doesn't match MTU or BM pool hasn't being used yet
1087          */
1088         if (new_pool->pkt_size == 0) {
1089                 int pkts_num;
1090
1091                 /* Set default buffer number or free all the buffers in case
1092                  * the pool is not empty
1093                  */
1094                 pkts_num = new_pool->buf_num;
1095                 if (pkts_num == 0) {
1096                         if (port->priv->percpu_pools) {
1097                                 if (pool < port->nrxqs)
1098                                         pkts_num = mvpp2_pools[MVPP2_BM_SHORT].buf_num;
1099                                 else
1100                                         pkts_num = mvpp2_pools[MVPP2_BM_LONG].buf_num;
1101                         } else {
1102                                 pkts_num = mvpp2_pools[pool].buf_num;
1103                         }
1104                 } else {
1105                         mvpp2_bm_bufs_free(port->dev->dev.parent,
1106                                            port->priv, new_pool, pkts_num);
1107                 }
1108
1109                 new_pool->pkt_size = pkt_size;
1110                 new_pool->frag_size =
1111                         SKB_DATA_ALIGN(MVPP2_RX_BUF_SIZE(pkt_size)) +
1112                         MVPP2_SKB_SHINFO_SIZE;
1113
1114                 /* Allocate buffers for this pool */
1115                 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num);
1116                 if (num != pkts_num) {
1117                         WARN(1, "pool %d: %d of %d allocated\n",
1118                              new_pool->id, num, pkts_num);
1119                         return NULL;
1120                 }
1121         }
1122
1123         mvpp2_bm_pool_bufsize_set(port->priv, new_pool,
1124                                   MVPP2_RX_BUF_SIZE(new_pool->pkt_size));
1125
1126         return new_pool;
1127 }
1128
1129 static struct mvpp2_bm_pool *
1130 mvpp2_bm_pool_use_percpu(struct mvpp2_port *port, int type,
1131                          unsigned int pool, int pkt_size)
1132 {
1133         struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool];
1134         int num;
1135
1136         if (pool > port->nrxqs * 2) {
1137                 netdev_err(port->dev, "Invalid pool %d\n", pool);
1138                 return NULL;
1139         }
1140
1141         /* Allocate buffers in case BM pool is used as long pool, but packet
1142          * size doesn't match MTU or BM pool hasn't being used yet
1143          */
1144         if (new_pool->pkt_size == 0) {
1145                 int pkts_num;
1146
1147                 /* Set default buffer number or free all the buffers in case
1148                  * the pool is not empty
1149                  */
1150                 pkts_num = new_pool->buf_num;
1151                 if (pkts_num == 0)
1152                         pkts_num = mvpp2_pools[type].buf_num;
1153                 else
1154                         mvpp2_bm_bufs_free(port->dev->dev.parent,
1155                                            port->priv, new_pool, pkts_num);
1156
1157                 new_pool->pkt_size = pkt_size;
1158                 new_pool->frag_size =
1159                         SKB_DATA_ALIGN(MVPP2_RX_BUF_SIZE(pkt_size)) +
1160                         MVPP2_SKB_SHINFO_SIZE;
1161
1162                 /* Allocate buffers for this pool */
1163                 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num);
1164                 if (num != pkts_num) {
1165                         WARN(1, "pool %d: %d of %d allocated\n",
1166                              new_pool->id, num, pkts_num);
1167                         return NULL;
1168                 }
1169         }
1170
1171         mvpp2_bm_pool_bufsize_set(port->priv, new_pool,
1172                                   MVPP2_RX_BUF_SIZE(new_pool->pkt_size));
1173
1174         return new_pool;
1175 }
1176
1177 /* Initialize pools for swf, shared buffers variant */
1178 static int mvpp2_swf_bm_pool_init_shared(struct mvpp2_port *port)
1179 {
1180         enum mvpp2_bm_pool_log_num long_log_pool, short_log_pool;
1181         int rxq;
1182
1183         /* If port pkt_size is higher than 1518B:
1184          * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool
1185          * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool
1186          */
1187         if (port->pkt_size > MVPP2_BM_LONG_PKT_SIZE) {
1188                 long_log_pool = MVPP2_BM_JUMBO;
1189                 short_log_pool = MVPP2_BM_LONG;
1190         } else {
1191                 long_log_pool = MVPP2_BM_LONG;
1192                 short_log_pool = MVPP2_BM_SHORT;
1193         }
1194
1195         if (!port->pool_long) {
1196                 port->pool_long =
1197                         mvpp2_bm_pool_use(port, long_log_pool,
1198                                           mvpp2_pools[long_log_pool].pkt_size);
1199                 if (!port->pool_long)
1200                         return -ENOMEM;
1201
1202                 port->pool_long->port_map |= BIT(port->id);
1203
1204                 for (rxq = 0; rxq < port->nrxqs; rxq++)
1205                         mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id);
1206         }
1207
1208         if (!port->pool_short) {
1209                 port->pool_short =
1210                         mvpp2_bm_pool_use(port, short_log_pool,
1211                                           mvpp2_pools[short_log_pool].pkt_size);
1212                 if (!port->pool_short)
1213                         return -ENOMEM;
1214
1215                 port->pool_short->port_map |= BIT(port->id);
1216
1217                 for (rxq = 0; rxq < port->nrxqs; rxq++)
1218                         mvpp2_rxq_short_pool_set(port, rxq,
1219                                                  port->pool_short->id);
1220         }
1221
1222         return 0;
1223 }
1224
1225 /* Initialize pools for swf, percpu buffers variant */
1226 static int mvpp2_swf_bm_pool_init_percpu(struct mvpp2_port *port)
1227 {
1228         struct mvpp2_bm_pool *bm_pool;
1229         int i;
1230
1231         for (i = 0; i < port->nrxqs; i++) {
1232                 bm_pool = mvpp2_bm_pool_use_percpu(port, MVPP2_BM_SHORT, i,
1233                                                    mvpp2_pools[MVPP2_BM_SHORT].pkt_size);
1234                 if (!bm_pool)
1235                         return -ENOMEM;
1236
1237                 bm_pool->port_map |= BIT(port->id);
1238                 mvpp2_rxq_short_pool_set(port, i, bm_pool->id);
1239         }
1240
1241         for (i = 0; i < port->nrxqs; i++) {
1242                 bm_pool = mvpp2_bm_pool_use_percpu(port, MVPP2_BM_LONG, i + port->nrxqs,
1243                                                    mvpp2_pools[MVPP2_BM_LONG].pkt_size);
1244                 if (!bm_pool)
1245                         return -ENOMEM;
1246
1247                 bm_pool->port_map |= BIT(port->id);
1248                 mvpp2_rxq_long_pool_set(port, i, bm_pool->id);
1249         }
1250
1251         port->pool_long = NULL;
1252         port->pool_short = NULL;
1253
1254         return 0;
1255 }
1256
1257 static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port)
1258 {
1259         if (port->priv->percpu_pools)
1260                 return mvpp2_swf_bm_pool_init_percpu(port);
1261         else
1262                 return mvpp2_swf_bm_pool_init_shared(port);
1263 }
1264
1265 static void mvpp2_set_hw_csum(struct mvpp2_port *port,
1266                               enum mvpp2_bm_pool_log_num new_long_pool)
1267 {
1268         const netdev_features_t csums = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1269
1270         /* Update L4 checksum when jumbo enable/disable on port.
1271          * Only port 0 supports hardware checksum offload due to
1272          * the Tx FIFO size limitation.
1273          * Also, don't set NETIF_F_HW_CSUM because L3_offset in TX descriptor
1274          * has 7 bits, so the maximum L3 offset is 128.
1275          */
1276         if (new_long_pool == MVPP2_BM_JUMBO && port->id != 0) {
1277                 port->dev->features &= ~csums;
1278                 port->dev->hw_features &= ~csums;
1279         } else {
1280                 port->dev->features |= csums;
1281                 port->dev->hw_features |= csums;
1282         }
1283 }
1284
1285 static int mvpp2_bm_update_mtu(struct net_device *dev, int mtu)
1286 {
1287         struct mvpp2_port *port = netdev_priv(dev);
1288         enum mvpp2_bm_pool_log_num new_long_pool;
1289         int pkt_size = MVPP2_RX_PKT_SIZE(mtu);
1290
1291         if (port->priv->percpu_pools)
1292                 goto out_set;
1293
1294         /* If port MTU is higher than 1518B:
1295          * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool
1296          * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool
1297          */
1298         if (pkt_size > MVPP2_BM_LONG_PKT_SIZE)
1299                 new_long_pool = MVPP2_BM_JUMBO;
1300         else
1301                 new_long_pool = MVPP2_BM_LONG;
1302
1303         if (new_long_pool != port->pool_long->id) {
1304                 if (port->tx_fc) {
1305                         if (pkt_size > MVPP2_BM_LONG_PKT_SIZE)
1306                                 mvpp2_bm_pool_update_fc(port,
1307                                                         port->pool_short,
1308                                                         false);
1309                         else
1310                                 mvpp2_bm_pool_update_fc(port, port->pool_long,
1311                                                         false);
1312                 }
1313
1314                 /* Remove port from old short & long pool */
1315                 port->pool_long = mvpp2_bm_pool_use(port, port->pool_long->id,
1316                                                     port->pool_long->pkt_size);
1317                 port->pool_long->port_map &= ~BIT(port->id);
1318                 port->pool_long = NULL;
1319
1320                 port->pool_short = mvpp2_bm_pool_use(port, port->pool_short->id,
1321                                                      port->pool_short->pkt_size);
1322                 port->pool_short->port_map &= ~BIT(port->id);
1323                 port->pool_short = NULL;
1324
1325                 port->pkt_size =  pkt_size;
1326
1327                 /* Add port to new short & long pool */
1328                 mvpp2_swf_bm_pool_init(port);
1329
1330                 mvpp2_set_hw_csum(port, new_long_pool);
1331
1332                 if (port->tx_fc) {
1333                         if (pkt_size > MVPP2_BM_LONG_PKT_SIZE)
1334                                 mvpp2_bm_pool_update_fc(port, port->pool_long,
1335                                                         true);
1336                         else
1337                                 mvpp2_bm_pool_update_fc(port, port->pool_short,
1338                                                         true);
1339                 }
1340
1341                 /* Update L4 checksum when jumbo enable/disable on port */
1342                 if (new_long_pool == MVPP2_BM_JUMBO && port->id != 0) {
1343                         dev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
1344                         dev->hw_features &= ~(NETIF_F_IP_CSUM |
1345                                               NETIF_F_IPV6_CSUM);
1346                 } else {
1347                         dev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1348                         dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1349                 }
1350         }
1351
1352 out_set:
1353         dev->mtu = mtu;
1354         dev->wanted_features = dev->features;
1355
1356         netdev_update_features(dev);
1357         return 0;
1358 }
1359
1360 static inline void mvpp2_interrupts_enable(struct mvpp2_port *port)
1361 {
1362         int i, sw_thread_mask = 0;
1363
1364         for (i = 0; i < port->nqvecs; i++)
1365                 sw_thread_mask |= port->qvecs[i].sw_thread_mask;
1366
1367         mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
1368                     MVPP2_ISR_ENABLE_INTERRUPT(sw_thread_mask));
1369 }
1370
1371 static inline void mvpp2_interrupts_disable(struct mvpp2_port *port)
1372 {
1373         int i, sw_thread_mask = 0;
1374
1375         for (i = 0; i < port->nqvecs; i++)
1376                 sw_thread_mask |= port->qvecs[i].sw_thread_mask;
1377
1378         mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
1379                     MVPP2_ISR_DISABLE_INTERRUPT(sw_thread_mask));
1380 }
1381
1382 static inline void mvpp2_qvec_interrupt_enable(struct mvpp2_queue_vector *qvec)
1383 {
1384         struct mvpp2_port *port = qvec->port;
1385
1386         mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
1387                     MVPP2_ISR_ENABLE_INTERRUPT(qvec->sw_thread_mask));
1388 }
1389
1390 static inline void mvpp2_qvec_interrupt_disable(struct mvpp2_queue_vector *qvec)
1391 {
1392         struct mvpp2_port *port = qvec->port;
1393
1394         mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
1395                     MVPP2_ISR_DISABLE_INTERRUPT(qvec->sw_thread_mask));
1396 }
1397
1398 /* Mask the current thread's Rx/Tx interrupts
1399  * Called by on_each_cpu(), guaranteed to run with migration disabled,
1400  * using smp_processor_id() is OK.
1401  */
1402 static void mvpp2_interrupts_mask(void *arg)
1403 {
1404         struct mvpp2_port *port = arg;
1405         int cpu = smp_processor_id();
1406         u32 thread;
1407
1408         /* If the thread isn't used, don't do anything */
1409         if (cpu > port->priv->nthreads)
1410                 return;
1411
1412         thread = mvpp2_cpu_to_thread(port->priv, cpu);
1413
1414         mvpp2_thread_write(port->priv, thread,
1415                            MVPP2_ISR_RX_TX_MASK_REG(port->id), 0);
1416         mvpp2_thread_write(port->priv, thread,
1417                            MVPP2_ISR_RX_ERR_CAUSE_REG(port->id), 0);
1418 }
1419
1420 /* Unmask the current thread's Rx/Tx interrupts.
1421  * Called by on_each_cpu(), guaranteed to run with migration disabled,
1422  * using smp_processor_id() is OK.
1423  */
1424 static void mvpp2_interrupts_unmask(void *arg)
1425 {
1426         struct mvpp2_port *port = arg;
1427         int cpu = smp_processor_id();
1428         u32 val, thread;
1429
1430         /* If the thread isn't used, don't do anything */
1431         if (cpu >= port->priv->nthreads)
1432                 return;
1433
1434         thread = mvpp2_cpu_to_thread(port->priv, cpu);
1435
1436         val = MVPP2_CAUSE_MISC_SUM_MASK |
1437                 MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version);
1438         if (port->has_tx_irqs)
1439                 val |= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK;
1440
1441         mvpp2_thread_write(port->priv, thread,
1442                            MVPP2_ISR_RX_TX_MASK_REG(port->id), val);
1443         mvpp2_thread_write(port->priv, thread,
1444                            MVPP2_ISR_RX_ERR_CAUSE_REG(port->id),
1445                            MVPP2_ISR_RX_ERR_CAUSE_NONOCC_MASK);
1446 }
1447
1448 static void
1449 mvpp2_shared_interrupt_mask_unmask(struct mvpp2_port *port, bool mask)
1450 {
1451         u32 val;
1452         int i;
1453
1454         if (port->priv->hw_version == MVPP21)
1455                 return;
1456
1457         if (mask)
1458                 val = 0;
1459         else
1460                 val = MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(MVPP22);
1461
1462         for (i = 0; i < port->nqvecs; i++) {
1463                 struct mvpp2_queue_vector *v = port->qvecs + i;
1464
1465                 if (v->type != MVPP2_QUEUE_VECTOR_SHARED)
1466                         continue;
1467
1468                 mvpp2_thread_write(port->priv, v->sw_thread_id,
1469                                    MVPP2_ISR_RX_TX_MASK_REG(port->id), val);
1470                 mvpp2_thread_write(port->priv, v->sw_thread_id,
1471                                    MVPP2_ISR_RX_ERR_CAUSE_REG(port->id),
1472                                    MVPP2_ISR_RX_ERR_CAUSE_NONOCC_MASK);
1473         }
1474 }
1475
1476 /* Only GOP port 0 has an XLG MAC */
1477 static bool mvpp2_port_supports_xlg(struct mvpp2_port *port)
1478 {
1479         return port->gop_id == 0;
1480 }
1481
1482 static bool mvpp2_port_supports_rgmii(struct mvpp2_port *port)
1483 {
1484         return !(port->priv->hw_version >= MVPP22 && port->gop_id == 0);
1485 }
1486
1487 /* Port configuration routines */
1488 static bool mvpp2_is_xlg(phy_interface_t interface)
1489 {
1490         return interface == PHY_INTERFACE_MODE_10GBASER ||
1491                interface == PHY_INTERFACE_MODE_XAUI;
1492 }
1493
1494 static void mvpp2_modify(void __iomem *ptr, u32 mask, u32 set)
1495 {
1496         u32 old, val;
1497
1498         old = val = readl(ptr);
1499         val &= ~mask;
1500         val |= set;
1501         if (old != val)
1502                 writel(val, ptr);
1503 }
1504
1505 static void mvpp22_gop_init_rgmii(struct mvpp2_port *port)
1506 {
1507         struct mvpp2 *priv = port->priv;
1508         u32 val;
1509
1510         regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val);
1511         val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT;
1512         regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val);
1513
1514         regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val);
1515         if (port->gop_id == 2)
1516                 val |= GENCONF_CTRL0_PORT2_RGMII;
1517         else if (port->gop_id == 3)
1518                 val |= GENCONF_CTRL0_PORT3_RGMII_MII;
1519         regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val);
1520 }
1521
1522 static void mvpp22_gop_init_sgmii(struct mvpp2_port *port)
1523 {
1524         struct mvpp2 *priv = port->priv;
1525         u32 val;
1526
1527         regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val);
1528         val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT |
1529                GENCONF_PORT_CTRL0_RX_DATA_SAMPLE;
1530         regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val);
1531
1532         if (port->gop_id > 1) {
1533                 regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val);
1534                 if (port->gop_id == 2)
1535                         val &= ~GENCONF_CTRL0_PORT2_RGMII;
1536                 else if (port->gop_id == 3)
1537                         val &= ~GENCONF_CTRL0_PORT3_RGMII_MII;
1538                 regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val);
1539         }
1540 }
1541
1542 static void mvpp22_gop_init_10gkr(struct mvpp2_port *port)
1543 {
1544         struct mvpp2 *priv = port->priv;
1545         void __iomem *mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id);
1546         void __iomem *xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id);
1547         u32 val;
1548
1549         val = readl(xpcs + MVPP22_XPCS_CFG0);
1550         val &= ~(MVPP22_XPCS_CFG0_PCS_MODE(0x3) |
1551                  MVPP22_XPCS_CFG0_ACTIVE_LANE(0x3));
1552         val |= MVPP22_XPCS_CFG0_ACTIVE_LANE(2);
1553         writel(val, xpcs + MVPP22_XPCS_CFG0);
1554
1555         val = readl(mpcs + MVPP22_MPCS_CTRL);
1556         val &= ~MVPP22_MPCS_CTRL_FWD_ERR_CONN;
1557         writel(val, mpcs + MVPP22_MPCS_CTRL);
1558
1559         val = readl(mpcs + MVPP22_MPCS_CLK_RESET);
1560         val &= ~MVPP22_MPCS_CLK_RESET_DIV_RATIO(0x7);
1561         val |= MVPP22_MPCS_CLK_RESET_DIV_RATIO(1);
1562         writel(val, mpcs + MVPP22_MPCS_CLK_RESET);
1563 }
1564
1565 static void mvpp22_gop_fca_enable_periodic(struct mvpp2_port *port, bool en)
1566 {
1567         struct mvpp2 *priv = port->priv;
1568         void __iomem *fca = priv->iface_base + MVPP22_FCA_BASE(port->gop_id);
1569         u32 val;
1570
1571         val = readl(fca + MVPP22_FCA_CONTROL_REG);
1572         val &= ~MVPP22_FCA_ENABLE_PERIODIC;
1573         if (en)
1574                 val |= MVPP22_FCA_ENABLE_PERIODIC;
1575         writel(val, fca + MVPP22_FCA_CONTROL_REG);
1576 }
1577
1578 static void mvpp22_gop_fca_set_timer(struct mvpp2_port *port, u32 timer)
1579 {
1580         struct mvpp2 *priv = port->priv;
1581         void __iomem *fca = priv->iface_base + MVPP22_FCA_BASE(port->gop_id);
1582         u32 lsb, msb;
1583
1584         lsb = timer & MVPP22_FCA_REG_MASK;
1585         msb = timer >> MVPP22_FCA_REG_SIZE;
1586
1587         writel(lsb, fca + MVPP22_PERIODIC_COUNTER_LSB_REG);
1588         writel(msb, fca + MVPP22_PERIODIC_COUNTER_MSB_REG);
1589 }
1590
1591 /* Set Flow Control timer x100 faster than pause quanta to ensure that link
1592  * partner won't send traffic if port is in XOFF mode.
1593  */
1594 static void mvpp22_gop_fca_set_periodic_timer(struct mvpp2_port *port)
1595 {
1596         u32 timer;
1597
1598         timer = (port->priv->tclk / (USEC_PER_SEC * FC_CLK_DIVIDER))
1599                 * FC_QUANTA;
1600
1601         mvpp22_gop_fca_enable_periodic(port, false);
1602
1603         mvpp22_gop_fca_set_timer(port, timer);
1604
1605         mvpp22_gop_fca_enable_periodic(port, true);
1606 }
1607
1608 static int mvpp22_gop_init(struct mvpp2_port *port)
1609 {
1610         struct mvpp2 *priv = port->priv;
1611         u32 val;
1612
1613         if (!priv->sysctrl_base)
1614                 return 0;
1615
1616         switch (port->phy_interface) {
1617         case PHY_INTERFACE_MODE_RGMII:
1618         case PHY_INTERFACE_MODE_RGMII_ID:
1619         case PHY_INTERFACE_MODE_RGMII_RXID:
1620         case PHY_INTERFACE_MODE_RGMII_TXID:
1621                 if (!mvpp2_port_supports_rgmii(port))
1622                         goto invalid_conf;
1623                 mvpp22_gop_init_rgmii(port);
1624                 break;
1625         case PHY_INTERFACE_MODE_SGMII:
1626         case PHY_INTERFACE_MODE_1000BASEX:
1627         case PHY_INTERFACE_MODE_2500BASEX:
1628                 mvpp22_gop_init_sgmii(port);
1629                 break;
1630         case PHY_INTERFACE_MODE_10GBASER:
1631                 if (!mvpp2_port_supports_xlg(port))
1632                         goto invalid_conf;
1633                 mvpp22_gop_init_10gkr(port);
1634                 break;
1635         default:
1636                 goto unsupported_conf;
1637         }
1638
1639         regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL1, &val);
1640         val |= GENCONF_PORT_CTRL1_RESET(port->gop_id) |
1641                GENCONF_PORT_CTRL1_EN(port->gop_id);
1642         regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL1, val);
1643
1644         regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val);
1645         val |= GENCONF_PORT_CTRL0_CLK_DIV_PHASE_CLR;
1646         regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val);
1647
1648         regmap_read(priv->sysctrl_base, GENCONF_SOFT_RESET1, &val);
1649         val |= GENCONF_SOFT_RESET1_GOP;
1650         regmap_write(priv->sysctrl_base, GENCONF_SOFT_RESET1, val);
1651
1652         mvpp22_gop_fca_set_periodic_timer(port);
1653
1654 unsupported_conf:
1655         return 0;
1656
1657 invalid_conf:
1658         netdev_err(port->dev, "Invalid port configuration\n");
1659         return -EINVAL;
1660 }
1661
1662 static void mvpp22_gop_unmask_irq(struct mvpp2_port *port)
1663 {
1664         u32 val;
1665
1666         if (phy_interface_mode_is_rgmii(port->phy_interface) ||
1667             phy_interface_mode_is_8023z(port->phy_interface) ||
1668             port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
1669                 /* Enable the GMAC link status irq for this port */
1670                 val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK);
1671                 val |= MVPP22_GMAC_INT_SUM_MASK_LINK_STAT;
1672                 writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK);
1673         }
1674
1675         if (mvpp2_port_supports_xlg(port)) {
1676                 /* Enable the XLG/GIG irqs for this port */
1677                 val = readl(port->base + MVPP22_XLG_EXT_INT_MASK);
1678                 if (mvpp2_is_xlg(port->phy_interface))
1679                         val |= MVPP22_XLG_EXT_INT_MASK_XLG;
1680                 else
1681                         val |= MVPP22_XLG_EXT_INT_MASK_GIG;
1682                 writel(val, port->base + MVPP22_XLG_EXT_INT_MASK);
1683         }
1684 }
1685
1686 static void mvpp22_gop_mask_irq(struct mvpp2_port *port)
1687 {
1688         u32 val;
1689
1690         if (mvpp2_port_supports_xlg(port)) {
1691                 val = readl(port->base + MVPP22_XLG_EXT_INT_MASK);
1692                 val &= ~(MVPP22_XLG_EXT_INT_MASK_XLG |
1693                          MVPP22_XLG_EXT_INT_MASK_GIG);
1694                 writel(val, port->base + MVPP22_XLG_EXT_INT_MASK);
1695         }
1696
1697         if (phy_interface_mode_is_rgmii(port->phy_interface) ||
1698             phy_interface_mode_is_8023z(port->phy_interface) ||
1699             port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
1700                 val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK);
1701                 val &= ~MVPP22_GMAC_INT_SUM_MASK_LINK_STAT;
1702                 writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK);
1703         }
1704 }
1705
1706 static void mvpp22_gop_setup_irq(struct mvpp2_port *port)
1707 {
1708         u32 val;
1709
1710         mvpp2_modify(port->base + MVPP22_GMAC_INT_SUM_MASK,
1711                      MVPP22_GMAC_INT_SUM_MASK_PTP,
1712                      MVPP22_GMAC_INT_SUM_MASK_PTP);
1713
1714         if (port->phylink ||
1715             phy_interface_mode_is_rgmii(port->phy_interface) ||
1716             phy_interface_mode_is_8023z(port->phy_interface) ||
1717             port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
1718                 val = readl(port->base + MVPP22_GMAC_INT_MASK);
1719                 val |= MVPP22_GMAC_INT_MASK_LINK_STAT;
1720                 writel(val, port->base + MVPP22_GMAC_INT_MASK);
1721         }
1722
1723         if (mvpp2_port_supports_xlg(port)) {
1724                 val = readl(port->base + MVPP22_XLG_INT_MASK);
1725                 val |= MVPP22_XLG_INT_MASK_LINK;
1726                 writel(val, port->base + MVPP22_XLG_INT_MASK);
1727
1728                 mvpp2_modify(port->base + MVPP22_XLG_EXT_INT_MASK,
1729                              MVPP22_XLG_EXT_INT_MASK_PTP,
1730                              MVPP22_XLG_EXT_INT_MASK_PTP);
1731         }
1732
1733         mvpp22_gop_unmask_irq(port);
1734 }
1735
1736 /* Sets the PHY mode of the COMPHY (which configures the serdes lanes).
1737  *
1738  * The PHY mode used by the PPv2 driver comes from the network subsystem, while
1739  * the one given to the COMPHY comes from the generic PHY subsystem. Hence they
1740  * differ.
1741  *
1742  * The COMPHY configures the serdes lanes regardless of the actual use of the
1743  * lanes by the physical layer. This is why configurations like
1744  * "PPv2 (2500BaseX) - COMPHY (2500SGMII)" are valid.
1745  */
1746 static int mvpp22_comphy_init(struct mvpp2_port *port)
1747 {
1748         int ret;
1749
1750         if (!port->comphy)
1751                 return 0;
1752
1753         ret = phy_set_mode_ext(port->comphy, PHY_MODE_ETHERNET,
1754                                port->phy_interface);
1755         if (ret)
1756                 return ret;
1757
1758         return phy_power_on(port->comphy);
1759 }
1760
1761 static void mvpp2_port_enable(struct mvpp2_port *port)
1762 {
1763         u32 val;
1764
1765         if (mvpp2_port_supports_xlg(port) &&
1766             mvpp2_is_xlg(port->phy_interface)) {
1767                 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
1768                 val |= MVPP22_XLG_CTRL0_PORT_EN;
1769                 val &= ~MVPP22_XLG_CTRL0_MIB_CNT_DIS;
1770                 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
1771         } else {
1772                 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
1773                 val |= MVPP2_GMAC_PORT_EN_MASK;
1774                 val |= MVPP2_GMAC_MIB_CNTR_EN_MASK;
1775                 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
1776         }
1777 }
1778
1779 static void mvpp2_port_disable(struct mvpp2_port *port)
1780 {
1781         u32 val;
1782
1783         if (mvpp2_port_supports_xlg(port) &&
1784             mvpp2_is_xlg(port->phy_interface)) {
1785                 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
1786                 val &= ~MVPP22_XLG_CTRL0_PORT_EN;
1787                 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
1788         }
1789
1790         val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
1791         val &= ~(MVPP2_GMAC_PORT_EN_MASK);
1792         writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
1793 }
1794
1795 /* Set IEEE 802.3x Flow Control Xon Packet Transmission Mode */
1796 static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port)
1797 {
1798         u32 val;
1799
1800         val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) &
1801                     ~MVPP2_GMAC_PERIODIC_XON_EN_MASK;
1802         writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
1803 }
1804
1805 /* Configure loopback port */
1806 static void mvpp2_port_loopback_set(struct mvpp2_port *port,
1807                                     const struct phylink_link_state *state)
1808 {
1809         u32 val;
1810
1811         val = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
1812
1813         if (state->speed == 1000)
1814                 val |= MVPP2_GMAC_GMII_LB_EN_MASK;
1815         else
1816                 val &= ~MVPP2_GMAC_GMII_LB_EN_MASK;
1817
1818         if (phy_interface_mode_is_8023z(state->interface) ||
1819             state->interface == PHY_INTERFACE_MODE_SGMII)
1820                 val |= MVPP2_GMAC_PCS_LB_EN_MASK;
1821         else
1822                 val &= ~MVPP2_GMAC_PCS_LB_EN_MASK;
1823
1824         writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
1825 }
1826
1827 enum {
1828         ETHTOOL_XDP_REDIRECT,
1829         ETHTOOL_XDP_PASS,
1830         ETHTOOL_XDP_DROP,
1831         ETHTOOL_XDP_TX,
1832         ETHTOOL_XDP_TX_ERR,
1833         ETHTOOL_XDP_XMIT,
1834         ETHTOOL_XDP_XMIT_ERR,
1835 };
1836
1837 struct mvpp2_ethtool_counter {
1838         unsigned int offset;
1839         const char string[ETH_GSTRING_LEN];
1840         bool reg_is_64b;
1841 };
1842
1843 static u64 mvpp2_read_count(struct mvpp2_port *port,
1844                             const struct mvpp2_ethtool_counter *counter)
1845 {
1846         u64 val;
1847
1848         val = readl(port->stats_base + counter->offset);
1849         if (counter->reg_is_64b)
1850                 val += (u64)readl(port->stats_base + counter->offset + 4) << 32;
1851
1852         return val;
1853 }
1854
1855 /* Some counters are accessed indirectly by first writing an index to
1856  * MVPP2_CTRS_IDX. The index can represent various resources depending on the
1857  * register we access, it can be a hit counter for some classification tables,
1858  * a counter specific to a rxq, a txq or a buffer pool.
1859  */
1860 static u32 mvpp2_read_index(struct mvpp2 *priv, u32 index, u32 reg)
1861 {
1862         mvpp2_write(priv, MVPP2_CTRS_IDX, index);
1863         return mvpp2_read(priv, reg);
1864 }
1865
1866 /* Due to the fact that software statistics and hardware statistics are, by
1867  * design, incremented at different moments in the chain of packet processing,
1868  * it is very likely that incoming packets could have been dropped after being
1869  * counted by hardware but before reaching software statistics (most probably
1870  * multicast packets), and in the oppposite way, during transmission, FCS bytes
1871  * are added in between as well as TSO skb will be split and header bytes added.
1872  * Hence, statistics gathered from userspace with ifconfig (software) and
1873  * ethtool (hardware) cannot be compared.
1874  */
1875 static const struct mvpp2_ethtool_counter mvpp2_ethtool_mib_regs[] = {
1876         { MVPP2_MIB_GOOD_OCTETS_RCVD, "good_octets_received", true },
1877         { MVPP2_MIB_BAD_OCTETS_RCVD, "bad_octets_received" },
1878         { MVPP2_MIB_CRC_ERRORS_SENT, "crc_errors_sent" },
1879         { MVPP2_MIB_UNICAST_FRAMES_RCVD, "unicast_frames_received" },
1880         { MVPP2_MIB_BROADCAST_FRAMES_RCVD, "broadcast_frames_received" },
1881         { MVPP2_MIB_MULTICAST_FRAMES_RCVD, "multicast_frames_received" },
1882         { MVPP2_MIB_FRAMES_64_OCTETS, "frames_64_octets" },
1883         { MVPP2_MIB_FRAMES_65_TO_127_OCTETS, "frames_65_to_127_octet" },
1884         { MVPP2_MIB_FRAMES_128_TO_255_OCTETS, "frames_128_to_255_octet" },
1885         { MVPP2_MIB_FRAMES_256_TO_511_OCTETS, "frames_256_to_511_octet" },
1886         { MVPP2_MIB_FRAMES_512_TO_1023_OCTETS, "frames_512_to_1023_octet" },
1887         { MVPP2_MIB_FRAMES_1024_TO_MAX_OCTETS, "frames_1024_to_max_octet" },
1888         { MVPP2_MIB_GOOD_OCTETS_SENT, "good_octets_sent", true },
1889         { MVPP2_MIB_UNICAST_FRAMES_SENT, "unicast_frames_sent" },
1890         { MVPP2_MIB_MULTICAST_FRAMES_SENT, "multicast_frames_sent" },
1891         { MVPP2_MIB_BROADCAST_FRAMES_SENT, "broadcast_frames_sent" },
1892         { MVPP2_MIB_FC_SENT, "fc_sent" },
1893         { MVPP2_MIB_FC_RCVD, "fc_received" },
1894         { MVPP2_MIB_RX_FIFO_OVERRUN, "rx_fifo_overrun" },
1895         { MVPP2_MIB_UNDERSIZE_RCVD, "undersize_received" },
1896         { MVPP2_MIB_FRAGMENTS_RCVD, "fragments_received" },
1897         { MVPP2_MIB_OVERSIZE_RCVD, "oversize_received" },
1898         { MVPP2_MIB_JABBER_RCVD, "jabber_received" },
1899         { MVPP2_MIB_MAC_RCV_ERROR, "mac_receive_error" },
1900         { MVPP2_MIB_BAD_CRC_EVENT, "bad_crc_event" },
1901         { MVPP2_MIB_COLLISION, "collision" },
1902         { MVPP2_MIB_LATE_COLLISION, "late_collision" },
1903 };
1904
1905 static const struct mvpp2_ethtool_counter mvpp2_ethtool_port_regs[] = {
1906         { MVPP2_OVERRUN_ETH_DROP, "rx_fifo_or_parser_overrun_drops" },
1907         { MVPP2_CLS_ETH_DROP, "rx_classifier_drops" },
1908 };
1909
1910 static const struct mvpp2_ethtool_counter mvpp2_ethtool_txq_regs[] = {
1911         { MVPP2_TX_DESC_ENQ_CTR, "txq_%d_desc_enqueue" },
1912         { MVPP2_TX_DESC_ENQ_TO_DDR_CTR, "txq_%d_desc_enqueue_to_ddr" },
1913         { MVPP2_TX_BUFF_ENQ_TO_DDR_CTR, "txq_%d_buff_euqueue_to_ddr" },
1914         { MVPP2_TX_DESC_ENQ_HW_FWD_CTR, "txq_%d_desc_hardware_forwarded" },
1915         { MVPP2_TX_PKTS_DEQ_CTR, "txq_%d_packets_dequeued" },
1916         { MVPP2_TX_PKTS_FULL_QUEUE_DROP_CTR, "txq_%d_queue_full_drops" },
1917         { MVPP2_TX_PKTS_EARLY_DROP_CTR, "txq_%d_packets_early_drops" },
1918         { MVPP2_TX_PKTS_BM_DROP_CTR, "txq_%d_packets_bm_drops" },
1919         { MVPP2_TX_PKTS_BM_MC_DROP_CTR, "txq_%d_packets_rep_bm_drops" },
1920 };
1921
1922 static const struct mvpp2_ethtool_counter mvpp2_ethtool_rxq_regs[] = {
1923         { MVPP2_RX_DESC_ENQ_CTR, "rxq_%d_desc_enqueue" },
1924         { MVPP2_RX_PKTS_FULL_QUEUE_DROP_CTR, "rxq_%d_queue_full_drops" },
1925         { MVPP2_RX_PKTS_EARLY_DROP_CTR, "rxq_%d_packets_early_drops" },
1926         { MVPP2_RX_PKTS_BM_DROP_CTR, "rxq_%d_packets_bm_drops" },
1927 };
1928
1929 static const struct mvpp2_ethtool_counter mvpp2_ethtool_xdp[] = {
1930         { ETHTOOL_XDP_REDIRECT, "rx_xdp_redirect", },
1931         { ETHTOOL_XDP_PASS, "rx_xdp_pass", },
1932         { ETHTOOL_XDP_DROP, "rx_xdp_drop", },
1933         { ETHTOOL_XDP_TX, "rx_xdp_tx", },
1934         { ETHTOOL_XDP_TX_ERR, "rx_xdp_tx_errors", },
1935         { ETHTOOL_XDP_XMIT, "tx_xdp_xmit", },
1936         { ETHTOOL_XDP_XMIT_ERR, "tx_xdp_xmit_errors", },
1937 };
1938
1939 #define MVPP2_N_ETHTOOL_STATS(ntxqs, nrxqs)     (ARRAY_SIZE(mvpp2_ethtool_mib_regs) + \
1940                                                  ARRAY_SIZE(mvpp2_ethtool_port_regs) + \
1941                                                  (ARRAY_SIZE(mvpp2_ethtool_txq_regs) * (ntxqs)) + \
1942                                                  (ARRAY_SIZE(mvpp2_ethtool_rxq_regs) * (nrxqs)) + \
1943                                                  ARRAY_SIZE(mvpp2_ethtool_xdp))
1944
1945 static void mvpp2_ethtool_get_strings(struct net_device *netdev, u32 sset,
1946                                       u8 *data)
1947 {
1948         struct mvpp2_port *port = netdev_priv(netdev);
1949         int i, q;
1950
1951         if (sset != ETH_SS_STATS)
1952                 return;
1953
1954         for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_mib_regs); i++) {
1955                 strscpy(data, mvpp2_ethtool_mib_regs[i].string,
1956                         ETH_GSTRING_LEN);
1957                 data += ETH_GSTRING_LEN;
1958         }
1959
1960         for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_port_regs); i++) {
1961                 strscpy(data, mvpp2_ethtool_port_regs[i].string,
1962                         ETH_GSTRING_LEN);
1963                 data += ETH_GSTRING_LEN;
1964         }
1965
1966         for (q = 0; q < port->ntxqs; q++) {
1967                 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_txq_regs); i++) {
1968                         snprintf(data, ETH_GSTRING_LEN,
1969                                  mvpp2_ethtool_txq_regs[i].string, q);
1970                         data += ETH_GSTRING_LEN;
1971                 }
1972         }
1973
1974         for (q = 0; q < port->nrxqs; q++) {
1975                 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_rxq_regs); i++) {
1976                         snprintf(data, ETH_GSTRING_LEN,
1977                                  mvpp2_ethtool_rxq_regs[i].string,
1978                                  q);
1979                         data += ETH_GSTRING_LEN;
1980                 }
1981         }
1982
1983         for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_xdp); i++) {
1984                 strscpy(data, mvpp2_ethtool_xdp[i].string,
1985                         ETH_GSTRING_LEN);
1986                 data += ETH_GSTRING_LEN;
1987         }
1988 }
1989
1990 static void
1991 mvpp2_get_xdp_stats(struct mvpp2_port *port, struct mvpp2_pcpu_stats *xdp_stats)
1992 {
1993         unsigned int start;
1994         unsigned int cpu;
1995
1996         /* Gather XDP Statistics */
1997         for_each_possible_cpu(cpu) {
1998                 struct mvpp2_pcpu_stats *cpu_stats;
1999                 u64     xdp_redirect;
2000                 u64     xdp_pass;
2001                 u64     xdp_drop;
2002                 u64     xdp_xmit;
2003                 u64     xdp_xmit_err;
2004                 u64     xdp_tx;
2005                 u64     xdp_tx_err;
2006
2007                 cpu_stats = per_cpu_ptr(port->stats, cpu);
2008                 do {
2009                         start = u64_stats_fetch_begin_irq(&cpu_stats->syncp);
2010                         xdp_redirect = cpu_stats->xdp_redirect;
2011                         xdp_pass   = cpu_stats->xdp_pass;
2012                         xdp_drop = cpu_stats->xdp_drop;
2013                         xdp_xmit   = cpu_stats->xdp_xmit;
2014                         xdp_xmit_err   = cpu_stats->xdp_xmit_err;
2015                         xdp_tx   = cpu_stats->xdp_tx;
2016                         xdp_tx_err   = cpu_stats->xdp_tx_err;
2017                 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start));
2018
2019                 xdp_stats->xdp_redirect += xdp_redirect;
2020                 xdp_stats->xdp_pass   += xdp_pass;
2021                 xdp_stats->xdp_drop += xdp_drop;
2022                 xdp_stats->xdp_xmit   += xdp_xmit;
2023                 xdp_stats->xdp_xmit_err   += xdp_xmit_err;
2024                 xdp_stats->xdp_tx   += xdp_tx;
2025                 xdp_stats->xdp_tx_err   += xdp_tx_err;
2026         }
2027 }
2028
2029 static void mvpp2_read_stats(struct mvpp2_port *port)
2030 {
2031         struct mvpp2_pcpu_stats xdp_stats = {};
2032         const struct mvpp2_ethtool_counter *s;
2033         u64 *pstats;
2034         int i, q;
2035
2036         pstats = port->ethtool_stats;
2037
2038         for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_mib_regs); i++)
2039                 *pstats++ += mvpp2_read_count(port, &mvpp2_ethtool_mib_regs[i]);
2040
2041         for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_port_regs); i++)
2042                 *pstats++ += mvpp2_read(port->priv,
2043                                         mvpp2_ethtool_port_regs[i].offset +
2044                                         4 * port->id);
2045
2046         for (q = 0; q < port->ntxqs; q++)
2047                 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_txq_regs); i++)
2048                         *pstats++ += mvpp2_read_index(port->priv,
2049                                                       MVPP22_CTRS_TX_CTR(port->id, q),
2050                                                       mvpp2_ethtool_txq_regs[i].offset);
2051
2052         /* Rxqs are numbered from 0 from the user standpoint, but not from the
2053          * driver's. We need to add the  port->first_rxq offset.
2054          */
2055         for (q = 0; q < port->nrxqs; q++)
2056                 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_rxq_regs); i++)
2057                         *pstats++ += mvpp2_read_index(port->priv,
2058                                                       port->first_rxq + q,
2059                                                       mvpp2_ethtool_rxq_regs[i].offset);
2060
2061         /* Gather XDP Statistics */
2062         mvpp2_get_xdp_stats(port, &xdp_stats);
2063
2064         for (i = 0, s = mvpp2_ethtool_xdp;
2065                  s < mvpp2_ethtool_xdp + ARRAY_SIZE(mvpp2_ethtool_xdp);
2066              s++, i++) {
2067                 switch (s->offset) {
2068                 case ETHTOOL_XDP_REDIRECT:
2069                         *pstats++ = xdp_stats.xdp_redirect;
2070                         break;
2071                 case ETHTOOL_XDP_PASS:
2072                         *pstats++ = xdp_stats.xdp_pass;
2073                         break;
2074                 case ETHTOOL_XDP_DROP:
2075                         *pstats++ = xdp_stats.xdp_drop;
2076                         break;
2077                 case ETHTOOL_XDP_TX:
2078                         *pstats++ = xdp_stats.xdp_tx;
2079                         break;
2080                 case ETHTOOL_XDP_TX_ERR:
2081                         *pstats++ = xdp_stats.xdp_tx_err;
2082                         break;
2083                 case ETHTOOL_XDP_XMIT:
2084                         *pstats++ = xdp_stats.xdp_xmit;
2085                         break;
2086                 case ETHTOOL_XDP_XMIT_ERR:
2087                         *pstats++ = xdp_stats.xdp_xmit_err;
2088                         break;
2089                 }
2090         }
2091 }
2092
2093 static void mvpp2_gather_hw_statistics(struct work_struct *work)
2094 {
2095         struct delayed_work *del_work = to_delayed_work(work);
2096         struct mvpp2_port *port = container_of(del_work, struct mvpp2_port,
2097                                                stats_work);
2098
2099         mutex_lock(&port->gather_stats_lock);
2100
2101         mvpp2_read_stats(port);
2102
2103         /* No need to read again the counters right after this function if it
2104          * was called asynchronously by the user (ie. use of ethtool).
2105          */
2106         cancel_delayed_work(&port->stats_work);
2107         queue_delayed_work(port->priv->stats_queue, &port->stats_work,
2108                            MVPP2_MIB_COUNTERS_STATS_DELAY);
2109
2110         mutex_unlock(&port->gather_stats_lock);
2111 }
2112
2113 static void mvpp2_ethtool_get_stats(struct net_device *dev,
2114                                     struct ethtool_stats *stats, u64 *data)
2115 {
2116         struct mvpp2_port *port = netdev_priv(dev);
2117
2118         /* Update statistics for the given port, then take the lock to avoid
2119          * concurrent accesses on the ethtool_stats structure during its copy.
2120          */
2121         mvpp2_gather_hw_statistics(&port->stats_work.work);
2122
2123         mutex_lock(&port->gather_stats_lock);
2124         memcpy(data, port->ethtool_stats,
2125                sizeof(u64) * MVPP2_N_ETHTOOL_STATS(port->ntxqs, port->nrxqs));
2126         mutex_unlock(&port->gather_stats_lock);
2127 }
2128
2129 static int mvpp2_ethtool_get_sset_count(struct net_device *dev, int sset)
2130 {
2131         struct mvpp2_port *port = netdev_priv(dev);
2132
2133         if (sset == ETH_SS_STATS)
2134                 return MVPP2_N_ETHTOOL_STATS(port->ntxqs, port->nrxqs);
2135
2136         return -EOPNOTSUPP;
2137 }
2138
2139 static void mvpp2_mac_reset_assert(struct mvpp2_port *port)
2140 {
2141         u32 val;
2142
2143         val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) |
2144               MVPP2_GMAC_PORT_RESET_MASK;
2145         writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
2146
2147         if (port->priv->hw_version >= MVPP22 && port->gop_id == 0) {
2148                 val = readl(port->base + MVPP22_XLG_CTRL0_REG) &
2149                       ~MVPP22_XLG_CTRL0_MAC_RESET_DIS;
2150                 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
2151         }
2152 }
2153
2154 static void mvpp22_pcs_reset_assert(struct mvpp2_port *port)
2155 {
2156         struct mvpp2 *priv = port->priv;
2157         void __iomem *mpcs, *xpcs;
2158         u32 val;
2159
2160         if (port->priv->hw_version == MVPP21 || port->gop_id != 0)
2161                 return;
2162
2163         mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id);
2164         xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id);
2165
2166         val = readl(mpcs + MVPP22_MPCS_CLK_RESET);
2167         val &= ~(MAC_CLK_RESET_MAC | MAC_CLK_RESET_SD_RX | MAC_CLK_RESET_SD_TX);
2168         val |= MVPP22_MPCS_CLK_RESET_DIV_SET;
2169         writel(val, mpcs + MVPP22_MPCS_CLK_RESET);
2170
2171         val = readl(xpcs + MVPP22_XPCS_CFG0);
2172         writel(val & ~MVPP22_XPCS_CFG0_RESET_DIS, xpcs + MVPP22_XPCS_CFG0);
2173 }
2174
2175 static void mvpp22_pcs_reset_deassert(struct mvpp2_port *port)
2176 {
2177         struct mvpp2 *priv = port->priv;
2178         void __iomem *mpcs, *xpcs;
2179         u32 val;
2180
2181         if (port->priv->hw_version == MVPP21 || port->gop_id != 0)
2182                 return;
2183
2184         mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id);
2185         xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id);
2186
2187         switch (port->phy_interface) {
2188         case PHY_INTERFACE_MODE_10GBASER:
2189                 val = readl(mpcs + MVPP22_MPCS_CLK_RESET);
2190                 val |= MAC_CLK_RESET_MAC | MAC_CLK_RESET_SD_RX |
2191                        MAC_CLK_RESET_SD_TX;
2192                 val &= ~MVPP22_MPCS_CLK_RESET_DIV_SET;
2193                 writel(val, mpcs + MVPP22_MPCS_CLK_RESET);
2194                 break;
2195         case PHY_INTERFACE_MODE_XAUI:
2196         case PHY_INTERFACE_MODE_RXAUI:
2197                 val = readl(xpcs + MVPP22_XPCS_CFG0);
2198                 writel(val | MVPP22_XPCS_CFG0_RESET_DIS, xpcs + MVPP22_XPCS_CFG0);
2199                 break;
2200         default:
2201                 break;
2202         }
2203 }
2204
2205 /* Change maximum receive size of the port */
2206 static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port)
2207 {
2208         u32 val;
2209
2210         val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
2211         val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK;
2212         val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) <<
2213                     MVPP2_GMAC_MAX_RX_SIZE_OFFS);
2214         writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
2215 }
2216
2217 /* Change maximum receive size of the port */
2218 static inline void mvpp2_xlg_max_rx_size_set(struct mvpp2_port *port)
2219 {
2220         u32 val;
2221
2222         val =  readl(port->base + MVPP22_XLG_CTRL1_REG);
2223         val &= ~MVPP22_XLG_CTRL1_FRAMESIZELIMIT_MASK;
2224         val |= ((port->pkt_size - MVPP2_MH_SIZE) / 2) <<
2225                MVPP22_XLG_CTRL1_FRAMESIZELIMIT_OFFS;
2226         writel(val, port->base + MVPP22_XLG_CTRL1_REG);
2227 }
2228
2229 /* Set defaults to the MVPP2 port */
2230 static void mvpp2_defaults_set(struct mvpp2_port *port)
2231 {
2232         int tx_port_num, val, queue, lrxq;
2233
2234         if (port->priv->hw_version == MVPP21) {
2235                 /* Update TX FIFO MIN Threshold */
2236                 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
2237                 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
2238                 /* Min. TX threshold must be less than minimal packet length */
2239                 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2);
2240                 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
2241         }
2242
2243         /* Disable Legacy WRR, Disable EJP, Release from reset */
2244         tx_port_num = mvpp2_egress_port(port);
2245         mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG,
2246                     tx_port_num);
2247         mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0);
2248
2249         /* Set TXQ scheduling to Round-Robin */
2250         mvpp2_write(port->priv, MVPP2_TXP_SCHED_FIXED_PRIO_REG, 0);
2251
2252         /* Close bandwidth for all queues */
2253         for (queue = 0; queue < MVPP2_MAX_TXQ; queue++)
2254                 mvpp2_write(port->priv,
2255                             MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(queue), 0);
2256
2257         /* Set refill period to 1 usec, refill tokens
2258          * and bucket size to maximum
2259          */
2260         mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG,
2261                     port->priv->tclk / USEC_PER_SEC);
2262         val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG);
2263         val &= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK;
2264         val |= MVPP2_TXP_REFILL_PERIOD_MASK(1);
2265         val |= MVPP2_TXP_REFILL_TOKENS_ALL_MASK;
2266         mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val);
2267         val = MVPP2_TXP_TOKEN_SIZE_MAX;
2268         mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
2269
2270         /* Set MaximumLowLatencyPacketSize value to 256 */
2271         mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id),
2272                     MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK |
2273                     MVPP2_RX_LOW_LATENCY_PKT_SIZE(256));
2274
2275         /* Enable Rx cache snoop */
2276         for (lrxq = 0; lrxq < port->nrxqs; lrxq++) {
2277                 queue = port->rxqs[lrxq]->id;
2278                 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
2279                 val |= MVPP2_SNOOP_PKT_SIZE_MASK |
2280                            MVPP2_SNOOP_BUF_HDR_MASK;
2281                 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
2282         }
2283
2284         /* At default, mask all interrupts to all present cpus */
2285         mvpp2_interrupts_disable(port);
2286 }
2287
2288 /* Enable/disable receiving packets */
2289 static void mvpp2_ingress_enable(struct mvpp2_port *port)
2290 {
2291         u32 val;
2292         int lrxq, queue;
2293
2294         for (lrxq = 0; lrxq < port->nrxqs; lrxq++) {
2295                 queue = port->rxqs[lrxq]->id;
2296                 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
2297                 val &= ~MVPP2_RXQ_DISABLE_MASK;
2298                 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
2299         }
2300 }
2301
2302 static void mvpp2_ingress_disable(struct mvpp2_port *port)
2303 {
2304         u32 val;
2305         int lrxq, queue;
2306
2307         for (lrxq = 0; lrxq < port->nrxqs; lrxq++) {
2308                 queue = port->rxqs[lrxq]->id;
2309                 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
2310                 val |= MVPP2_RXQ_DISABLE_MASK;
2311                 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
2312         }
2313 }
2314
2315 /* Enable transmit via physical egress queue
2316  * - HW starts take descriptors from DRAM
2317  */
2318 static void mvpp2_egress_enable(struct mvpp2_port *port)
2319 {
2320         u32 qmap;
2321         int queue;
2322         int tx_port_num = mvpp2_egress_port(port);
2323
2324         /* Enable all initialized TXs. */
2325         qmap = 0;
2326         for (queue = 0; queue < port->ntxqs; queue++) {
2327                 struct mvpp2_tx_queue *txq = port->txqs[queue];
2328
2329                 if (txq->descs)
2330                         qmap |= (1 << queue);
2331         }
2332
2333         mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
2334         mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap);
2335 }
2336
2337 /* Disable transmit via physical egress queue
2338  * - HW doesn't take descriptors from DRAM
2339  */
2340 static void mvpp2_egress_disable(struct mvpp2_port *port)
2341 {
2342         u32 reg_data;
2343         int delay;
2344         int tx_port_num = mvpp2_egress_port(port);
2345
2346         /* Issue stop command for active channels only */
2347         mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
2348         reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) &
2349                     MVPP2_TXP_SCHED_ENQ_MASK;
2350         if (reg_data != 0)
2351                 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG,
2352                             (reg_data << MVPP2_TXP_SCHED_DISQ_OFFSET));
2353
2354         /* Wait for all Tx activity to terminate. */
2355         delay = 0;
2356         do {
2357                 if (delay >= MVPP2_TX_DISABLE_TIMEOUT_MSEC) {
2358                         netdev_warn(port->dev,
2359                                     "Tx stop timed out, status=0x%08x\n",
2360                                     reg_data);
2361                         break;
2362                 }
2363                 mdelay(1);
2364                 delay++;
2365
2366                 /* Check port TX Command register that all
2367                  * Tx queues are stopped
2368                  */
2369                 reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG);
2370         } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK);
2371 }
2372
2373 /* Rx descriptors helper methods */
2374
2375 /* Get number of Rx descriptors occupied by received packets */
2376 static inline int
2377 mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id)
2378 {
2379         u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id));
2380
2381         return val & MVPP2_RXQ_OCCUPIED_MASK;
2382 }
2383
2384 /* Update Rx queue status with the number of occupied and available
2385  * Rx descriptor slots.
2386  */
2387 static inline void
2388 mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id,
2389                         int used_count, int free_count)
2390 {
2391         /* Decrement the number of used descriptors and increment count
2392          * increment the number of free descriptors.
2393          */
2394         u32 val = used_count | (free_count << MVPP2_RXQ_NUM_NEW_OFFSET);
2395
2396         mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val);
2397 }
2398
2399 /* Get pointer to next RX descriptor to be processed by SW */
2400 static inline struct mvpp2_rx_desc *
2401 mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue *rxq)
2402 {
2403         int rx_desc = rxq->next_desc_to_proc;
2404
2405         rxq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(rxq, rx_desc);
2406         prefetch(rxq->descs + rxq->next_desc_to_proc);
2407         return rxq->descs + rx_desc;
2408 }
2409
2410 /* Set rx queue offset */
2411 static void mvpp2_rxq_offset_set(struct mvpp2_port *port,
2412                                  int prxq, int offset)
2413 {
2414         u32 val;
2415
2416         /* Convert offset from bytes to units of 32 bytes */
2417         offset = offset >> 5;
2418
2419         val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
2420         val &= ~MVPP2_RXQ_PACKET_OFFSET_MASK;
2421
2422         /* Offset is in */
2423         val |= ((offset << MVPP2_RXQ_PACKET_OFFSET_OFFS) &
2424                     MVPP2_RXQ_PACKET_OFFSET_MASK);
2425
2426         mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
2427 }
2428
2429 /* Tx descriptors helper methods */
2430
2431 /* Get pointer to next Tx descriptor to be processed (send) by HW */
2432 static struct mvpp2_tx_desc *
2433 mvpp2_txq_next_desc_get(struct mvpp2_tx_queue *txq)
2434 {
2435         int tx_desc = txq->next_desc_to_proc;
2436
2437         txq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(txq, tx_desc);
2438         return txq->descs + tx_desc;
2439 }
2440
2441 /* Update HW with number of aggregated Tx descriptors to be sent
2442  *
2443  * Called only from mvpp2_tx(), so migration is disabled, using
2444  * smp_processor_id() is OK.
2445  */
2446 static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending)
2447 {
2448         /* aggregated access - relevant TXQ number is written in TX desc */
2449         mvpp2_thread_write(port->priv,
2450                            mvpp2_cpu_to_thread(port->priv, smp_processor_id()),
2451                            MVPP2_AGGR_TXQ_UPDATE_REG, pending);
2452 }
2453
2454 /* Check if there are enough free descriptors in aggregated txq.
2455  * If not, update the number of occupied descriptors and repeat the check.
2456  *
2457  * Called only from mvpp2_tx(), so migration is disabled, using
2458  * smp_processor_id() is OK.
2459  */
2460 static int mvpp2_aggr_desc_num_check(struct mvpp2_port *port,
2461                                      struct mvpp2_tx_queue *aggr_txq, int num)
2462 {
2463         if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE) {
2464                 /* Update number of occupied aggregated Tx descriptors */
2465                 unsigned int thread =
2466                         mvpp2_cpu_to_thread(port->priv, smp_processor_id());
2467                 u32 val = mvpp2_read_relaxed(port->priv,
2468                                              MVPP2_AGGR_TXQ_STATUS_REG(thread));
2469
2470                 aggr_txq->count = val & MVPP2_AGGR_TXQ_PENDING_MASK;
2471
2472                 if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE)
2473                         return -ENOMEM;
2474         }
2475         return 0;
2476 }
2477
2478 /* Reserved Tx descriptors allocation request
2479  *
2480  * Called only from mvpp2_txq_reserved_desc_num_proc(), itself called
2481  * only by mvpp2_tx(), so migration is disabled, using
2482  * smp_processor_id() is OK.
2483  */
2484 static int mvpp2_txq_alloc_reserved_desc(struct mvpp2_port *port,
2485                                          struct mvpp2_tx_queue *txq, int num)
2486 {
2487         unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
2488         struct mvpp2 *priv = port->priv;
2489         u32 val;
2490
2491         val = (txq->id << MVPP2_TXQ_RSVD_REQ_Q_OFFSET) | num;
2492         mvpp2_thread_write_relaxed(priv, thread, MVPP2_TXQ_RSVD_REQ_REG, val);
2493
2494         val = mvpp2_thread_read_relaxed(priv, thread, MVPP2_TXQ_RSVD_RSLT_REG);
2495
2496         return val & MVPP2_TXQ_RSVD_RSLT_MASK;
2497 }
2498
2499 /* Check if there are enough reserved descriptors for transmission.
2500  * If not, request chunk of reserved descriptors and check again.
2501  */
2502 static int mvpp2_txq_reserved_desc_num_proc(struct mvpp2_port *port,
2503                                             struct mvpp2_tx_queue *txq,
2504                                             struct mvpp2_txq_pcpu *txq_pcpu,
2505                                             int num)
2506 {
2507         int req, desc_count;
2508         unsigned int thread;
2509
2510         if (txq_pcpu->reserved_num >= num)
2511                 return 0;
2512
2513         /* Not enough descriptors reserved! Update the reserved descriptor
2514          * count and check again.
2515          */
2516
2517         desc_count = 0;
2518         /* Compute total of used descriptors */
2519         for (thread = 0; thread < port->priv->nthreads; thread++) {
2520                 struct mvpp2_txq_pcpu *txq_pcpu_aux;
2521
2522                 txq_pcpu_aux = per_cpu_ptr(txq->pcpu, thread);
2523                 desc_count += txq_pcpu_aux->count;
2524                 desc_count += txq_pcpu_aux->reserved_num;
2525         }
2526
2527         req = max(MVPP2_CPU_DESC_CHUNK, num - txq_pcpu->reserved_num);
2528         desc_count += req;
2529
2530         if (desc_count >
2531            (txq->size - (MVPP2_MAX_THREADS * MVPP2_CPU_DESC_CHUNK)))
2532                 return -ENOMEM;
2533
2534         txq_pcpu->reserved_num += mvpp2_txq_alloc_reserved_desc(port, txq, req);
2535
2536         /* OK, the descriptor could have been updated: check again. */
2537         if (txq_pcpu->reserved_num < num)
2538                 return -ENOMEM;
2539         return 0;
2540 }
2541
2542 /* Release the last allocated Tx descriptor. Useful to handle DMA
2543  * mapping failures in the Tx path.
2544  */
2545 static void mvpp2_txq_desc_put(struct mvpp2_tx_queue *txq)
2546 {
2547         if (txq->next_desc_to_proc == 0)
2548                 txq->next_desc_to_proc = txq->last_desc - 1;
2549         else
2550                 txq->next_desc_to_proc--;
2551 }
2552
2553 /* Set Tx descriptors fields relevant for CSUM calculation */
2554 static u32 mvpp2_txq_desc_csum(int l3_offs, __be16 l3_proto,
2555                                int ip_hdr_len, int l4_proto)
2556 {
2557         u32 command;
2558
2559         /* fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk,
2560          * G_L4_chk, L4_type required only for checksum calculation
2561          */
2562         command = (l3_offs << MVPP2_TXD_L3_OFF_SHIFT);
2563         command |= (ip_hdr_len << MVPP2_TXD_IP_HLEN_SHIFT);
2564         command |= MVPP2_TXD_IP_CSUM_DISABLE;
2565
2566         if (l3_proto == htons(ETH_P_IP)) {
2567                 command &= ~MVPP2_TXD_IP_CSUM_DISABLE;  /* enable IPv4 csum */
2568                 command &= ~MVPP2_TXD_L3_IP6;           /* enable IPv4 */
2569         } else {
2570                 command |= MVPP2_TXD_L3_IP6;            /* enable IPv6 */
2571         }
2572
2573         if (l4_proto == IPPROTO_TCP) {
2574                 command &= ~MVPP2_TXD_L4_UDP;           /* enable TCP */
2575                 command &= ~MVPP2_TXD_L4_CSUM_FRAG;     /* generate L4 csum */
2576         } else if (l4_proto == IPPROTO_UDP) {
2577                 command |= MVPP2_TXD_L4_UDP;            /* enable UDP */
2578                 command &= ~MVPP2_TXD_L4_CSUM_FRAG;     /* generate L4 csum */
2579         } else {
2580                 command |= MVPP2_TXD_L4_CSUM_NOT;
2581         }
2582
2583         return command;
2584 }
2585
2586 /* Get number of sent descriptors and decrement counter.
2587  * The number of sent descriptors is returned.
2588  * Per-thread access
2589  *
2590  * Called only from mvpp2_txq_done(), called from mvpp2_tx()
2591  * (migration disabled) and from the TX completion tasklet (migration
2592  * disabled) so using smp_processor_id() is OK.
2593  */
2594 static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port,
2595                                            struct mvpp2_tx_queue *txq)
2596 {
2597         u32 val;
2598
2599         /* Reading status reg resets transmitted descriptor counter */
2600         val = mvpp2_thread_read_relaxed(port->priv,
2601                                         mvpp2_cpu_to_thread(port->priv, smp_processor_id()),
2602                                         MVPP2_TXQ_SENT_REG(txq->id));
2603
2604         return (val & MVPP2_TRANSMITTED_COUNT_MASK) >>
2605                 MVPP2_TRANSMITTED_COUNT_OFFSET;
2606 }
2607
2608 /* Called through on_each_cpu(), so runs on all CPUs, with migration
2609  * disabled, therefore using smp_processor_id() is OK.
2610  */
2611 static void mvpp2_txq_sent_counter_clear(void *arg)
2612 {
2613         struct mvpp2_port *port = arg;
2614         int queue;
2615
2616         /* If the thread isn't used, don't do anything */
2617         if (smp_processor_id() >= port->priv->nthreads)
2618                 return;
2619
2620         for (queue = 0; queue < port->ntxqs; queue++) {
2621                 int id = port->txqs[queue]->id;
2622
2623                 mvpp2_thread_read(port->priv,
2624                                   mvpp2_cpu_to_thread(port->priv, smp_processor_id()),
2625                                   MVPP2_TXQ_SENT_REG(id));
2626         }
2627 }
2628
2629 /* Set max sizes for Tx queues */
2630 static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port)
2631 {
2632         u32     val, size, mtu;
2633         int     txq, tx_port_num;
2634
2635         mtu = port->pkt_size * 8;
2636         if (mtu > MVPP2_TXP_MTU_MAX)
2637                 mtu = MVPP2_TXP_MTU_MAX;
2638
2639         /* WA for wrong Token bucket update: Set MTU value = 3*real MTU value */
2640         mtu = 3 * mtu;
2641
2642         /* Indirect access to registers */
2643         tx_port_num = mvpp2_egress_port(port);
2644         mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
2645
2646         /* Set MTU */
2647         val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG);
2648         val &= ~MVPP2_TXP_MTU_MAX;
2649         val |= mtu;
2650         mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val);
2651
2652         /* TXP token size and all TXQs token size must be larger that MTU */
2653         val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG);
2654         size = val & MVPP2_TXP_TOKEN_SIZE_MAX;
2655         if (size < mtu) {
2656                 size = mtu;
2657                 val &= ~MVPP2_TXP_TOKEN_SIZE_MAX;
2658                 val |= size;
2659                 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
2660         }
2661
2662         for (txq = 0; txq < port->ntxqs; txq++) {
2663                 val = mvpp2_read(port->priv,
2664                                  MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq));
2665                 size = val & MVPP2_TXQ_TOKEN_SIZE_MAX;
2666
2667                 if (size < mtu) {
2668                         size = mtu;
2669                         val &= ~MVPP2_TXQ_TOKEN_SIZE_MAX;
2670                         val |= size;
2671                         mvpp2_write(port->priv,
2672                                     MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq),
2673                                     val);
2674                 }
2675         }
2676 }
2677
2678 /* Set the number of non-occupied descriptors threshold */
2679 static void mvpp2_set_rxq_free_tresh(struct mvpp2_port *port,
2680                                      struct mvpp2_rx_queue *rxq)
2681 {
2682         u32 val;
2683
2684         mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
2685
2686         val = mvpp2_read(port->priv, MVPP2_RXQ_THRESH_REG);
2687         val &= ~MVPP2_RXQ_NON_OCCUPIED_MASK;
2688         val |= MSS_THRESHOLD_STOP << MVPP2_RXQ_NON_OCCUPIED_OFFSET;
2689         mvpp2_write(port->priv, MVPP2_RXQ_THRESH_REG, val);
2690 }
2691
2692 /* Set the number of packets that will be received before Rx interrupt
2693  * will be generated by HW.
2694  */
2695 static void mvpp2_rx_pkts_coal_set(struct mvpp2_port *port,
2696                                    struct mvpp2_rx_queue *rxq)
2697 {
2698         unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
2699
2700         if (rxq->pkts_coal > MVPP2_OCCUPIED_THRESH_MASK)
2701                 rxq->pkts_coal = MVPP2_OCCUPIED_THRESH_MASK;
2702
2703         mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id);
2704         mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_THRESH_REG,
2705                            rxq->pkts_coal);
2706
2707         put_cpu();
2708 }
2709
2710 /* For some reason in the LSP this is done on each CPU. Why ? */
2711 static void mvpp2_tx_pkts_coal_set(struct mvpp2_port *port,
2712                                    struct mvpp2_tx_queue *txq)
2713 {
2714         unsigned int thread;
2715         u32 val;
2716
2717         if (txq->done_pkts_coal > MVPP2_TXQ_THRESH_MASK)
2718                 txq->done_pkts_coal = MVPP2_TXQ_THRESH_MASK;
2719
2720         val = (txq->done_pkts_coal << MVPP2_TXQ_THRESH_OFFSET);
2721         /* PKT-coalescing registers are per-queue + per-thread */
2722         for (thread = 0; thread < MVPP2_MAX_THREADS; thread++) {
2723                 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id);
2724                 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_THRESH_REG, val);
2725         }
2726 }
2727
2728 static u32 mvpp2_usec_to_cycles(u32 usec, unsigned long clk_hz)
2729 {
2730         u64 tmp = (u64)clk_hz * usec;
2731
2732         do_div(tmp, USEC_PER_SEC);
2733
2734         return tmp > U32_MAX ? U32_MAX : tmp;
2735 }
2736
2737 static u32 mvpp2_cycles_to_usec(u32 cycles, unsigned long clk_hz)
2738 {
2739         u64 tmp = (u64)cycles * USEC_PER_SEC;
2740
2741         do_div(tmp, clk_hz);
2742
2743         return tmp > U32_MAX ? U32_MAX : tmp;
2744 }
2745
2746 /* Set the time delay in usec before Rx interrupt */
2747 static void mvpp2_rx_time_coal_set(struct mvpp2_port *port,
2748                                    struct mvpp2_rx_queue *rxq)
2749 {
2750         unsigned long freq = port->priv->tclk;
2751         u32 val = mvpp2_usec_to_cycles(rxq->time_coal, freq);
2752
2753         if (val > MVPP2_MAX_ISR_RX_THRESHOLD) {
2754                 rxq->time_coal =
2755                         mvpp2_cycles_to_usec(MVPP2_MAX_ISR_RX_THRESHOLD, freq);
2756
2757                 /* re-evaluate to get actual register value */
2758                 val = mvpp2_usec_to_cycles(rxq->time_coal, freq);
2759         }
2760
2761         mvpp2_write(port->priv, MVPP2_ISR_RX_THRESHOLD_REG(rxq->id), val);
2762 }
2763
2764 static void mvpp2_tx_time_coal_set(struct mvpp2_port *port)
2765 {
2766         unsigned long freq = port->priv->tclk;
2767         u32 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq);
2768
2769         if (val > MVPP2_MAX_ISR_TX_THRESHOLD) {
2770                 port->tx_time_coal =
2771                         mvpp2_cycles_to_usec(MVPP2_MAX_ISR_TX_THRESHOLD, freq);
2772
2773                 /* re-evaluate to get actual register value */
2774                 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq);
2775         }
2776
2777         mvpp2_write(port->priv, MVPP2_ISR_TX_THRESHOLD_REG(port->id), val);
2778 }
2779
2780 /* Free Tx queue skbuffs */
2781 static void mvpp2_txq_bufs_free(struct mvpp2_port *port,
2782                                 struct mvpp2_tx_queue *txq,
2783                                 struct mvpp2_txq_pcpu *txq_pcpu, int num)
2784 {
2785         struct xdp_frame_bulk bq;
2786         int i;
2787
2788         xdp_frame_bulk_init(&bq);
2789
2790         rcu_read_lock(); /* need for xdp_return_frame_bulk */
2791
2792         for (i = 0; i < num; i++) {
2793                 struct mvpp2_txq_pcpu_buf *tx_buf =
2794                         txq_pcpu->buffs + txq_pcpu->txq_get_index;
2795
2796                 if (!IS_TSO_HEADER(txq_pcpu, tx_buf->dma) &&
2797                     tx_buf->type != MVPP2_TYPE_XDP_TX)
2798                         dma_unmap_single(port->dev->dev.parent, tx_buf->dma,
2799                                          tx_buf->size, DMA_TO_DEVICE);
2800                 if (tx_buf->type == MVPP2_TYPE_SKB && tx_buf->skb)
2801                         dev_kfree_skb_any(tx_buf->skb);
2802                 else if (tx_buf->type == MVPP2_TYPE_XDP_TX ||
2803                          tx_buf->type == MVPP2_TYPE_XDP_NDO)
2804                         xdp_return_frame_bulk(tx_buf->xdpf, &bq);
2805
2806                 mvpp2_txq_inc_get(txq_pcpu);
2807         }
2808         xdp_flush_frame_bulk(&bq);
2809
2810         rcu_read_unlock();
2811 }
2812
2813 static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port,
2814                                                         u32 cause)
2815 {
2816         int queue = fls(cause) - 1;
2817
2818         return port->rxqs[queue];
2819 }
2820
2821 static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port,
2822                                                         u32 cause)
2823 {
2824         int queue = fls(cause) - 1;
2825
2826         return port->txqs[queue];
2827 }
2828
2829 /* Handle end of transmission */
2830 static void mvpp2_txq_done(struct mvpp2_port *port, struct mvpp2_tx_queue *txq,
2831                            struct mvpp2_txq_pcpu *txq_pcpu)
2832 {
2833         struct netdev_queue *nq = netdev_get_tx_queue(port->dev, txq->log_id);
2834         int tx_done;
2835
2836         if (txq_pcpu->thread != mvpp2_cpu_to_thread(port->priv, smp_processor_id()))
2837                 netdev_err(port->dev, "wrong cpu on the end of Tx processing\n");
2838
2839         tx_done = mvpp2_txq_sent_desc_proc(port, txq);
2840         if (!tx_done)
2841                 return;
2842         mvpp2_txq_bufs_free(port, txq, txq_pcpu, tx_done);
2843
2844         txq_pcpu->count -= tx_done;
2845
2846         if (netif_tx_queue_stopped(nq))
2847                 if (txq_pcpu->count <= txq_pcpu->wake_threshold)
2848                         netif_tx_wake_queue(nq);
2849 }
2850
2851 static unsigned int mvpp2_tx_done(struct mvpp2_port *port, u32 cause,
2852                                   unsigned int thread)
2853 {
2854         struct mvpp2_tx_queue *txq;
2855         struct mvpp2_txq_pcpu *txq_pcpu;
2856         unsigned int tx_todo = 0;
2857
2858         while (cause) {
2859                 txq = mvpp2_get_tx_queue(port, cause);
2860                 if (!txq)
2861                         break;
2862
2863                 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
2864
2865                 if (txq_pcpu->count) {
2866                         mvpp2_txq_done(port, txq, txq_pcpu);
2867                         tx_todo += txq_pcpu->count;
2868                 }
2869
2870                 cause &= ~(1 << txq->log_id);
2871         }
2872         return tx_todo;
2873 }
2874
2875 /* Rx/Tx queue initialization/cleanup methods */
2876
2877 /* Allocate and initialize descriptors for aggr TXQ */
2878 static int mvpp2_aggr_txq_init(struct platform_device *pdev,
2879                                struct mvpp2_tx_queue *aggr_txq,
2880                                unsigned int thread, struct mvpp2 *priv)
2881 {
2882         u32 txq_dma;
2883
2884         /* Allocate memory for TX descriptors */
2885         aggr_txq->descs = dma_alloc_coherent(&pdev->dev,
2886                                              MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE,
2887                                              &aggr_txq->descs_dma, GFP_KERNEL);
2888         if (!aggr_txq->descs)
2889                 return -ENOMEM;
2890
2891         aggr_txq->last_desc = MVPP2_AGGR_TXQ_SIZE - 1;
2892
2893         /* Aggr TXQ no reset WA */
2894         aggr_txq->next_desc_to_proc = mvpp2_read(priv,
2895                                                  MVPP2_AGGR_TXQ_INDEX_REG(thread));
2896
2897         /* Set Tx descriptors queue starting address indirect
2898          * access
2899          */
2900         if (priv->hw_version == MVPP21)
2901                 txq_dma = aggr_txq->descs_dma;
2902         else
2903                 txq_dma = aggr_txq->descs_dma >>
2904                         MVPP22_AGGR_TXQ_DESC_ADDR_OFFS;
2905
2906         mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(thread), txq_dma);
2907         mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(thread),
2908                     MVPP2_AGGR_TXQ_SIZE);
2909
2910         return 0;
2911 }
2912
2913 /* Create a specified Rx queue */
2914 static int mvpp2_rxq_init(struct mvpp2_port *port,
2915                           struct mvpp2_rx_queue *rxq)
2916 {
2917         struct mvpp2 *priv = port->priv;
2918         unsigned int thread;
2919         u32 rxq_dma;
2920         int err;
2921
2922         rxq->size = port->rx_ring_size;
2923
2924         /* Allocate memory for RX descriptors */
2925         rxq->descs = dma_alloc_coherent(port->dev->dev.parent,
2926                                         rxq->size * MVPP2_DESC_ALIGNED_SIZE,
2927                                         &rxq->descs_dma, GFP_KERNEL);
2928         if (!rxq->descs)
2929                 return -ENOMEM;
2930
2931         rxq->last_desc = rxq->size - 1;
2932
2933         /* Zero occupied and non-occupied counters - direct access */
2934         mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
2935
2936         /* Set Rx descriptors queue starting address - indirect access */
2937         thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
2938         mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id);
2939         if (port->priv->hw_version == MVPP21)
2940                 rxq_dma = rxq->descs_dma;
2941         else
2942                 rxq_dma = rxq->descs_dma >> MVPP22_DESC_ADDR_OFFS;
2943         mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma);
2944         mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_SIZE_REG, rxq->size);
2945         mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_INDEX_REG, 0);
2946         put_cpu();
2947
2948         /* Set Offset */
2949         mvpp2_rxq_offset_set(port, rxq->id, MVPP2_SKB_HEADROOM);
2950
2951         /* Set coalescing pkts and time */
2952         mvpp2_rx_pkts_coal_set(port, rxq);
2953         mvpp2_rx_time_coal_set(port, rxq);
2954
2955         /* Set the number of non occupied descriptors threshold */
2956         mvpp2_set_rxq_free_tresh(port, rxq);
2957
2958         /* Add number of descriptors ready for receiving packets */
2959         mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size);
2960
2961         if (priv->percpu_pools) {
2962                 err = xdp_rxq_info_reg(&rxq->xdp_rxq_short, port->dev, rxq->id, 0);
2963                 if (err < 0)
2964                         goto err_free_dma;
2965
2966                 err = xdp_rxq_info_reg(&rxq->xdp_rxq_long, port->dev, rxq->id, 0);
2967                 if (err < 0)
2968                         goto err_unregister_rxq_short;
2969
2970                 /* Every RXQ has a pool for short and another for long packets */
2971                 err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq_short,
2972                                                  MEM_TYPE_PAGE_POOL,
2973                                                  priv->page_pool[rxq->logic_rxq]);
2974                 if (err < 0)
2975                         goto err_unregister_rxq_long;
2976
2977                 err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq_long,
2978                                                  MEM_TYPE_PAGE_POOL,
2979                                                  priv->page_pool[rxq->logic_rxq +
2980                                                                  port->nrxqs]);
2981                 if (err < 0)
2982                         goto err_unregister_mem_rxq_short;
2983         }
2984
2985         return 0;
2986
2987 err_unregister_mem_rxq_short:
2988         xdp_rxq_info_unreg_mem_model(&rxq->xdp_rxq_short);
2989 err_unregister_rxq_long:
2990         xdp_rxq_info_unreg(&rxq->xdp_rxq_long);
2991 err_unregister_rxq_short:
2992         xdp_rxq_info_unreg(&rxq->xdp_rxq_short);
2993 err_free_dma:
2994         dma_free_coherent(port->dev->dev.parent,
2995                           rxq->size * MVPP2_DESC_ALIGNED_SIZE,
2996                           rxq->descs, rxq->descs_dma);
2997         return err;
2998 }
2999
3000 /* Push packets received by the RXQ to BM pool */
3001 static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port,
3002                                 struct mvpp2_rx_queue *rxq)
3003 {
3004         int rx_received, i;
3005
3006         rx_received = mvpp2_rxq_received(port, rxq->id);
3007         if (!rx_received)
3008                 return;
3009
3010         for (i = 0; i < rx_received; i++) {
3011                 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
3012                 u32 status = mvpp2_rxdesc_status_get(port, rx_desc);
3013                 int pool;
3014
3015                 pool = (status & MVPP2_RXD_BM_POOL_ID_MASK) >>
3016                         MVPP2_RXD_BM_POOL_ID_OFFS;
3017
3018                 mvpp2_bm_pool_put(port, pool,
3019                                   mvpp2_rxdesc_dma_addr_get(port, rx_desc),
3020                                   mvpp2_rxdesc_cookie_get(port, rx_desc));
3021         }
3022         mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received);
3023 }
3024
3025 /* Cleanup Rx queue */
3026 static void mvpp2_rxq_deinit(struct mvpp2_port *port,
3027                              struct mvpp2_rx_queue *rxq)
3028 {
3029         unsigned int thread;
3030
3031         if (xdp_rxq_info_is_reg(&rxq->xdp_rxq_short))
3032                 xdp_rxq_info_unreg(&rxq->xdp_rxq_short);
3033
3034         if (xdp_rxq_info_is_reg(&rxq->xdp_rxq_long))
3035                 xdp_rxq_info_unreg(&rxq->xdp_rxq_long);
3036
3037         mvpp2_rxq_drop_pkts(port, rxq);
3038
3039         if (rxq->descs)
3040                 dma_free_coherent(port->dev->dev.parent,
3041                                   rxq->size * MVPP2_DESC_ALIGNED_SIZE,
3042                                   rxq->descs,
3043                                   rxq->descs_dma);
3044
3045         rxq->descs             = NULL;
3046         rxq->last_desc         = 0;
3047         rxq->next_desc_to_proc = 0;
3048         rxq->descs_dma         = 0;
3049
3050         /* Clear Rx descriptors queue starting address and size;
3051          * free descriptor number
3052          */
3053         mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
3054         thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
3055         mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id);
3056         mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_ADDR_REG, 0);
3057         mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_SIZE_REG, 0);
3058         put_cpu();
3059 }
3060
3061 /* Create and initialize a Tx queue */
3062 static int mvpp2_txq_init(struct mvpp2_port *port,
3063                           struct mvpp2_tx_queue *txq)
3064 {
3065         u32 val;
3066         unsigned int thread;
3067         int desc, desc_per_txq, tx_port_num;
3068         struct mvpp2_txq_pcpu *txq_pcpu;
3069
3070         txq->size = port->tx_ring_size;
3071
3072         /* Allocate memory for Tx descriptors */
3073         txq->descs = dma_alloc_coherent(port->dev->dev.parent,
3074                                 txq->size * MVPP2_DESC_ALIGNED_SIZE,
3075                                 &txq->descs_dma, GFP_KERNEL);
3076         if (!txq->descs)
3077                 return -ENOMEM;
3078
3079         txq->last_desc = txq->size - 1;
3080
3081         /* Set Tx descriptors queue starting address - indirect access */
3082         thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
3083         mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id);
3084         mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_ADDR_REG,
3085                            txq->descs_dma);
3086         mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_SIZE_REG,
3087                            txq->size & MVPP2_TXQ_DESC_SIZE_MASK);
3088         mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_INDEX_REG, 0);
3089         mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_RSVD_CLR_REG,
3090                            txq->id << MVPP2_TXQ_RSVD_CLR_OFFSET);
3091         val = mvpp2_thread_read(port->priv, thread, MVPP2_TXQ_PENDING_REG);
3092         val &= ~MVPP2_TXQ_PENDING_MASK;
3093         mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PENDING_REG, val);
3094
3095         /* Calculate base address in prefetch buffer. We reserve 16 descriptors
3096          * for each existing TXQ.
3097          * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT
3098          * GBE ports assumed to be continuous from 0 to MVPP2_MAX_PORTS
3099          */
3100         desc_per_txq = 16;
3101         desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) +
3102                (txq->log_id * desc_per_txq);
3103
3104         mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG,
3105                            MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 |
3106                            MVPP2_PREF_BUF_THRESH(desc_per_txq / 2));
3107         put_cpu();
3108
3109         /* WRR / EJP configuration - indirect access */
3110         tx_port_num = mvpp2_egress_port(port);
3111         mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
3112
3113         val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id));
3114         val &= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK;
3115         val |= MVPP2_TXQ_REFILL_PERIOD_MASK(1);
3116         val |= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK;
3117         mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val);
3118
3119         val = MVPP2_TXQ_TOKEN_SIZE_MAX;
3120         mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id),
3121                     val);
3122
3123         for (thread = 0; thread < port->priv->nthreads; thread++) {
3124                 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
3125                 txq_pcpu->size = txq->size;
3126                 txq_pcpu->buffs = kmalloc_array(txq_pcpu->size,
3127                                                 sizeof(*txq_pcpu->buffs),
3128                                                 GFP_KERNEL);
3129                 if (!txq_pcpu->buffs)
3130                         return -ENOMEM;
3131
3132                 txq_pcpu->count = 0;
3133                 txq_pcpu->reserved_num = 0;
3134                 txq_pcpu->txq_put_index = 0;
3135                 txq_pcpu->txq_get_index = 0;
3136                 txq_pcpu->tso_headers = NULL;
3137
3138                 txq_pcpu->stop_threshold = txq->size - MVPP2_MAX_SKB_DESCS;
3139                 txq_pcpu->wake_threshold = txq_pcpu->stop_threshold / 2;
3140
3141                 txq_pcpu->tso_headers =
3142                         dma_alloc_coherent(port->dev->dev.parent,
3143                                            txq_pcpu->size * TSO_HEADER_SIZE,
3144                                            &txq_pcpu->tso_headers_dma,
3145                                            GFP_KERNEL);
3146                 if (!txq_pcpu->tso_headers)
3147                         return -ENOMEM;
3148         }
3149
3150         return 0;
3151 }
3152
3153 /* Free allocated TXQ resources */
3154 static void mvpp2_txq_deinit(struct mvpp2_port *port,
3155                              struct mvpp2_tx_queue *txq)
3156 {
3157         struct mvpp2_txq_pcpu *txq_pcpu;
3158         unsigned int thread;
3159
3160         for (thread = 0; thread < port->priv->nthreads; thread++) {
3161                 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
3162                 kfree(txq_pcpu->buffs);
3163
3164                 if (txq_pcpu->tso_headers)
3165                         dma_free_coherent(port->dev->dev.parent,
3166                                           txq_pcpu->size * TSO_HEADER_SIZE,
3167                                           txq_pcpu->tso_headers,
3168                                           txq_pcpu->tso_headers_dma);
3169
3170                 txq_pcpu->tso_headers = NULL;
3171         }
3172
3173         if (txq->descs)
3174                 dma_free_coherent(port->dev->dev.parent,
3175                                   txq->size * MVPP2_DESC_ALIGNED_SIZE,
3176                                   txq->descs, txq->descs_dma);
3177
3178         txq->descs             = NULL;
3179         txq->last_desc         = 0;
3180         txq->next_desc_to_proc = 0;
3181         txq->descs_dma         = 0;
3182
3183         /* Set minimum bandwidth for disabled TXQs */
3184         mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->log_id), 0);
3185
3186         /* Set Tx descriptors queue starting address and size */
3187         thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
3188         mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id);
3189         mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_ADDR_REG, 0);
3190         mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_SIZE_REG, 0);
3191         put_cpu();
3192 }
3193
3194 /* Cleanup Tx ports */
3195 static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq)
3196 {
3197         struct mvpp2_txq_pcpu *txq_pcpu;
3198         int delay, pending;
3199         unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
3200         u32 val;
3201
3202         mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id);
3203         val = mvpp2_thread_read(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG);
3204         val |= MVPP2_TXQ_DRAIN_EN_MASK;
3205         mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, val);
3206
3207         /* The napi queue has been stopped so wait for all packets
3208          * to be transmitted.
3209          */
3210         delay = 0;
3211         do {
3212                 if (delay >= MVPP2_TX_PENDING_TIMEOUT_MSEC) {
3213                         netdev_warn(port->dev,
3214                                     "port %d: cleaning queue %d timed out\n",
3215                                     port->id, txq->log_id);
3216                         break;
3217                 }
3218                 mdelay(1);
3219                 delay++;
3220
3221                 pending = mvpp2_thread_read(port->priv, thread,
3222                                             MVPP2_TXQ_PENDING_REG);
3223                 pending &= MVPP2_TXQ_PENDING_MASK;
3224         } while (pending);
3225
3226         val &= ~MVPP2_TXQ_DRAIN_EN_MASK;
3227         mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, val);
3228         put_cpu();
3229
3230         for (thread = 0; thread < port->priv->nthreads; thread++) {
3231                 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
3232
3233                 /* Release all packets */
3234                 mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count);
3235
3236                 /* Reset queue */
3237                 txq_pcpu->count = 0;
3238                 txq_pcpu->txq_put_index = 0;
3239                 txq_pcpu->txq_get_index = 0;
3240         }
3241 }
3242
3243 /* Cleanup all Tx queues */
3244 static void mvpp2_cleanup_txqs(struct mvpp2_port *port)
3245 {
3246         struct mvpp2_tx_queue *txq;
3247         int queue;
3248         u32 val;
3249
3250         val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG);
3251
3252         /* Reset Tx ports and delete Tx queues */
3253         val |= MVPP2_TX_PORT_FLUSH_MASK(port->id);
3254         mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
3255
3256         for (queue = 0; queue < port->ntxqs; queue++) {
3257                 txq = port->txqs[queue];
3258                 mvpp2_txq_clean(port, txq);
3259                 mvpp2_txq_deinit(port, txq);
3260         }
3261
3262         on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1);
3263
3264         val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id);
3265         mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
3266 }
3267
3268 /* Cleanup all Rx queues */
3269 static void mvpp2_cleanup_rxqs(struct mvpp2_port *port)
3270 {
3271         int queue;
3272
3273         for (queue = 0; queue < port->nrxqs; queue++)
3274                 mvpp2_rxq_deinit(port, port->rxqs[queue]);
3275
3276         if (port->tx_fc)
3277                 mvpp2_rxq_disable_fc(port);
3278 }
3279
3280 /* Init all Rx queues for port */
3281 static int mvpp2_setup_rxqs(struct mvpp2_port *port)
3282 {
3283         int queue, err;
3284
3285         for (queue = 0; queue < port->nrxqs; queue++) {
3286                 err = mvpp2_rxq_init(port, port->rxqs[queue]);
3287                 if (err)
3288                         goto err_cleanup;
3289         }
3290
3291         if (port->tx_fc)
3292                 mvpp2_rxq_enable_fc(port);
3293
3294         return 0;
3295
3296 err_cleanup:
3297         mvpp2_cleanup_rxqs(port);
3298         return err;
3299 }
3300
3301 /* Init all tx queues for port */
3302 static int mvpp2_setup_txqs(struct mvpp2_port *port)
3303 {
3304         struct mvpp2_tx_queue *txq;
3305         int queue, err;
3306
3307         for (queue = 0; queue < port->ntxqs; queue++) {
3308                 txq = port->txqs[queue];
3309                 err = mvpp2_txq_init(port, txq);
3310                 if (err)
3311                         goto err_cleanup;
3312
3313                 /* Assign this queue to a CPU */
3314                 if (queue < num_possible_cpus())
3315                         netif_set_xps_queue(port->dev, cpumask_of(queue), queue);
3316         }
3317
3318         if (port->has_tx_irqs) {
3319                 mvpp2_tx_time_coal_set(port);
3320                 for (queue = 0; queue < port->ntxqs; queue++) {
3321                         txq = port->txqs[queue];
3322                         mvpp2_tx_pkts_coal_set(port, txq);
3323                 }
3324         }
3325
3326         on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1);
3327         return 0;
3328
3329 err_cleanup:
3330         mvpp2_cleanup_txqs(port);
3331         return err;
3332 }
3333
3334 /* The callback for per-port interrupt */
3335 static irqreturn_t mvpp2_isr(int irq, void *dev_id)
3336 {
3337         struct mvpp2_queue_vector *qv = dev_id;
3338
3339         mvpp2_qvec_interrupt_disable(qv);
3340
3341         napi_schedule(&qv->napi);
3342
3343         return IRQ_HANDLED;
3344 }
3345
3346 static void mvpp2_isr_handle_ptp_queue(struct mvpp2_port *port, int nq)
3347 {
3348         struct skb_shared_hwtstamps shhwtstamps;
3349         struct mvpp2_hwtstamp_queue *queue;
3350         struct sk_buff *skb;
3351         void __iomem *ptp_q;
3352         unsigned int id;
3353         u32 r0, r1, r2;
3354
3355         ptp_q = port->priv->iface_base + MVPP22_PTP_BASE(port->gop_id);
3356         if (nq)
3357                 ptp_q += MVPP22_PTP_TX_Q1_R0 - MVPP22_PTP_TX_Q0_R0;
3358
3359         queue = &port->tx_hwtstamp_queue[nq];
3360
3361         while (1) {
3362                 r0 = readl_relaxed(ptp_q + MVPP22_PTP_TX_Q0_R0) & 0xffff;
3363                 if (!r0)
3364                         break;
3365
3366                 r1 = readl_relaxed(ptp_q + MVPP22_PTP_TX_Q0_R1) & 0xffff;
3367                 r2 = readl_relaxed(ptp_q + MVPP22_PTP_TX_Q0_R2) & 0xffff;
3368
3369                 id = (r0 >> 1) & 31;
3370
3371                 skb = queue->skb[id];
3372                 queue->skb[id] = NULL;
3373                 if (skb) {
3374                         u32 ts = r2 << 19 | r1 << 3 | r0 >> 13;
3375
3376                         mvpp22_tai_tstamp(port->priv->tai, ts, &shhwtstamps);
3377                         skb_tstamp_tx(skb, &shhwtstamps);
3378                         dev_kfree_skb_any(skb);
3379                 }
3380         }
3381 }
3382
3383 static void mvpp2_isr_handle_ptp(struct mvpp2_port *port)
3384 {
3385         void __iomem *ptp;
3386         u32 val;
3387
3388         ptp = port->priv->iface_base + MVPP22_PTP_BASE(port->gop_id);
3389         val = readl(ptp + MVPP22_PTP_INT_CAUSE);
3390         if (val & MVPP22_PTP_INT_CAUSE_QUEUE0)
3391                 mvpp2_isr_handle_ptp_queue(port, 0);
3392         if (val & MVPP22_PTP_INT_CAUSE_QUEUE1)
3393                 mvpp2_isr_handle_ptp_queue(port, 1);
3394 }
3395
3396 static void mvpp2_isr_handle_link(struct mvpp2_port *port, bool link)
3397 {
3398         struct net_device *dev = port->dev;
3399
3400         if (port->phylink) {
3401                 phylink_mac_change(port->phylink, link);
3402                 return;
3403         }
3404
3405         if (!netif_running(dev))
3406                 return;
3407
3408         if (link) {
3409                 mvpp2_interrupts_enable(port);
3410
3411                 mvpp2_egress_enable(port);
3412                 mvpp2_ingress_enable(port);
3413                 netif_carrier_on(dev);
3414                 netif_tx_wake_all_queues(dev);
3415         } else {
3416                 netif_tx_stop_all_queues(dev);
3417                 netif_carrier_off(dev);
3418                 mvpp2_ingress_disable(port);
3419                 mvpp2_egress_disable(port);
3420
3421                 mvpp2_interrupts_disable(port);
3422         }
3423 }
3424
3425 static void mvpp2_isr_handle_xlg(struct mvpp2_port *port)
3426 {
3427         bool link;
3428         u32 val;
3429
3430         val = readl(port->base + MVPP22_XLG_INT_STAT);
3431         if (val & MVPP22_XLG_INT_STAT_LINK) {
3432                 val = readl(port->base + MVPP22_XLG_STATUS);
3433                 link = (val & MVPP22_XLG_STATUS_LINK_UP);
3434                 mvpp2_isr_handle_link(port, link);
3435         }
3436 }
3437
3438 static void mvpp2_isr_handle_gmac_internal(struct mvpp2_port *port)
3439 {
3440         bool link;
3441         u32 val;
3442
3443         if (phy_interface_mode_is_rgmii(port->phy_interface) ||
3444             phy_interface_mode_is_8023z(port->phy_interface) ||
3445             port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
3446                 val = readl(port->base + MVPP22_GMAC_INT_STAT);
3447                 if (val & MVPP22_GMAC_INT_STAT_LINK) {
3448                         val = readl(port->base + MVPP2_GMAC_STATUS0);
3449                         link = (val & MVPP2_GMAC_STATUS0_LINK_UP);
3450                         mvpp2_isr_handle_link(port, link);
3451                 }
3452         }
3453 }
3454
3455 /* Per-port interrupt for link status changes */
3456 static irqreturn_t mvpp2_port_isr(int irq, void *dev_id)
3457 {
3458         struct mvpp2_port *port = (struct mvpp2_port *)dev_id;
3459         u32 val;
3460
3461         mvpp22_gop_mask_irq(port);
3462
3463         if (mvpp2_port_supports_xlg(port) &&
3464             mvpp2_is_xlg(port->phy_interface)) {
3465                 /* Check the external status register */
3466                 val = readl(port->base + MVPP22_XLG_EXT_INT_STAT);
3467                 if (val & MVPP22_XLG_EXT_INT_STAT_XLG)
3468                         mvpp2_isr_handle_xlg(port);
3469                 if (val & MVPP22_XLG_EXT_INT_STAT_PTP)
3470                         mvpp2_isr_handle_ptp(port);
3471         } else {
3472                 /* If it's not the XLG, we must be using the GMAC.
3473                  * Check the summary status.
3474                  */
3475                 val = readl(port->base + MVPP22_GMAC_INT_SUM_STAT);
3476                 if (val & MVPP22_GMAC_INT_SUM_STAT_INTERNAL)
3477                         mvpp2_isr_handle_gmac_internal(port);
3478                 if (val & MVPP22_GMAC_INT_SUM_STAT_PTP)
3479                         mvpp2_isr_handle_ptp(port);
3480         }
3481
3482         mvpp22_gop_unmask_irq(port);
3483         return IRQ_HANDLED;
3484 }
3485
3486 static enum hrtimer_restart mvpp2_hr_timer_cb(struct hrtimer *timer)
3487 {
3488         struct net_device *dev;
3489         struct mvpp2_port *port;
3490         struct mvpp2_port_pcpu *port_pcpu;
3491         unsigned int tx_todo, cause;
3492
3493         port_pcpu = container_of(timer, struct mvpp2_port_pcpu, tx_done_timer);
3494         dev = port_pcpu->dev;
3495
3496         if (!netif_running(dev))
3497                 return HRTIMER_NORESTART;
3498
3499         port_pcpu->timer_scheduled = false;
3500         port = netdev_priv(dev);
3501
3502         /* Process all the Tx queues */
3503         cause = (1 << port->ntxqs) - 1;
3504         tx_todo = mvpp2_tx_done(port, cause,
3505                                 mvpp2_cpu_to_thread(port->priv, smp_processor_id()));
3506
3507         /* Set the timer in case not all the packets were processed */
3508         if (tx_todo && !port_pcpu->timer_scheduled) {
3509                 port_pcpu->timer_scheduled = true;
3510                 hrtimer_forward_now(&port_pcpu->tx_done_timer,
3511                                     MVPP2_TXDONE_HRTIMER_PERIOD_NS);
3512
3513                 return HRTIMER_RESTART;
3514         }
3515         return HRTIMER_NORESTART;
3516 }
3517
3518 /* Main RX/TX processing routines */
3519
3520 /* Display more error info */
3521 static void mvpp2_rx_error(struct mvpp2_port *port,
3522                            struct mvpp2_rx_desc *rx_desc)
3523 {
3524         u32 status = mvpp2_rxdesc_status_get(port, rx_desc);
3525         size_t sz = mvpp2_rxdesc_size_get(port, rx_desc);
3526         char *err_str = NULL;
3527
3528         switch (status & MVPP2_RXD_ERR_CODE_MASK) {
3529         case MVPP2_RXD_ERR_CRC:
3530                 err_str = "crc";
3531                 break;
3532         case MVPP2_RXD_ERR_OVERRUN:
3533                 err_str = "overrun";
3534                 break;
3535         case MVPP2_RXD_ERR_RESOURCE:
3536                 err_str = "resource";
3537                 break;
3538         }
3539         if (err_str && net_ratelimit())
3540                 netdev_err(port->dev,
3541                            "bad rx status %08x (%s error), size=%zu\n",
3542                            status, err_str, sz);
3543 }
3544
3545 /* Handle RX checksum offload */
3546 static void mvpp2_rx_csum(struct mvpp2_port *port, u32 status,
3547                           struct sk_buff *skb)
3548 {
3549         if (((status & MVPP2_RXD_L3_IP4) &&
3550              !(status & MVPP2_RXD_IP4_HEADER_ERR)) ||
3551             (status & MVPP2_RXD_L3_IP6))
3552                 if (((status & MVPP2_RXD_L4_UDP) ||
3553                      (status & MVPP2_RXD_L4_TCP)) &&
3554                      (status & MVPP2_RXD_L4_CSUM_OK)) {
3555                         skb->csum = 0;
3556                         skb->ip_summed = CHECKSUM_UNNECESSARY;
3557                         return;
3558                 }
3559
3560         skb->ip_summed = CHECKSUM_NONE;
3561 }
3562
3563 /* Allocate a new skb and add it to BM pool */
3564 static int mvpp2_rx_refill(struct mvpp2_port *port,
3565                            struct mvpp2_bm_pool *bm_pool,
3566                            struct page_pool *page_pool, int pool)
3567 {
3568         dma_addr_t dma_addr;
3569         phys_addr_t phys_addr;
3570         void *buf;
3571
3572         buf = mvpp2_buf_alloc(port, bm_pool, page_pool,
3573                               &dma_addr, &phys_addr, GFP_ATOMIC);
3574         if (!buf)
3575                 return -ENOMEM;
3576
3577         mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr);
3578
3579         return 0;
3580 }
3581
3582 /* Handle tx checksum */
3583 static u32 mvpp2_skb_tx_csum(struct mvpp2_port *port, struct sk_buff *skb)
3584 {
3585         if (skb->ip_summed == CHECKSUM_PARTIAL) {
3586                 int ip_hdr_len = 0;
3587                 u8 l4_proto;
3588                 __be16 l3_proto = vlan_get_protocol(skb);
3589
3590                 if (l3_proto == htons(ETH_P_IP)) {
3591                         struct iphdr *ip4h = ip_hdr(skb);
3592
3593                         /* Calculate IPv4 checksum and L4 checksum */
3594                         ip_hdr_len = ip4h->ihl;
3595                         l4_proto = ip4h->protocol;
3596                 } else if (l3_proto == htons(ETH_P_IPV6)) {
3597                         struct ipv6hdr *ip6h = ipv6_hdr(skb);
3598
3599                         /* Read l4_protocol from one of IPv6 extra headers */
3600                         if (skb_network_header_len(skb) > 0)
3601                                 ip_hdr_len = (skb_network_header_len(skb) >> 2);
3602                         l4_proto = ip6h->nexthdr;
3603                 } else {
3604                         return MVPP2_TXD_L4_CSUM_NOT;
3605                 }
3606
3607                 return mvpp2_txq_desc_csum(skb_network_offset(skb),
3608                                            l3_proto, ip_hdr_len, l4_proto);
3609         }
3610
3611         return MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE;
3612 }
3613
3614 static void mvpp2_xdp_finish_tx(struct mvpp2_port *port, u16 txq_id, int nxmit, int nxmit_byte)
3615 {
3616         unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
3617         struct mvpp2_tx_queue *aggr_txq;
3618         struct mvpp2_txq_pcpu *txq_pcpu;
3619         struct mvpp2_tx_queue *txq;
3620         struct netdev_queue *nq;
3621
3622         txq = port->txqs[txq_id];
3623         txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
3624         nq = netdev_get_tx_queue(port->dev, txq_id);
3625         aggr_txq = &port->priv->aggr_txqs[thread];
3626
3627         txq_pcpu->reserved_num -= nxmit;
3628         txq_pcpu->count += nxmit;
3629         aggr_txq->count += nxmit;
3630
3631         /* Enable transmit */
3632         wmb();
3633         mvpp2_aggr_txq_pend_desc_add(port, nxmit);
3634
3635         if (txq_pcpu->count >= txq_pcpu->stop_threshold)
3636                 netif_tx_stop_queue(nq);
3637
3638         /* Finalize TX processing */
3639         if (!port->has_tx_irqs && txq_pcpu->count >= txq->done_pkts_coal)
3640                 mvpp2_txq_done(port, txq, txq_pcpu);
3641 }
3642
3643 static int
3644 mvpp2_xdp_submit_frame(struct mvpp2_port *port, u16 txq_id,
3645                        struct xdp_frame *xdpf, bool dma_map)
3646 {
3647         unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
3648         u32 tx_cmd = MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE |
3649                      MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC;
3650         enum mvpp2_tx_buf_type buf_type;
3651         struct mvpp2_txq_pcpu *txq_pcpu;
3652         struct mvpp2_tx_queue *aggr_txq;
3653         struct mvpp2_tx_desc *tx_desc;
3654         struct mvpp2_tx_queue *txq;
3655         int ret = MVPP2_XDP_TX;
3656         dma_addr_t dma_addr;
3657
3658         txq = port->txqs[txq_id];
3659         txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
3660         aggr_txq = &port->priv->aggr_txqs[thread];
3661
3662         /* Check number of available descriptors */
3663         if (mvpp2_aggr_desc_num_check(port, aggr_txq, 1) ||
3664             mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu, 1)) {
3665                 ret = MVPP2_XDP_DROPPED;
3666                 goto out;
3667         }
3668
3669         /* Get a descriptor for the first part of the packet */
3670         tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
3671         mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
3672         mvpp2_txdesc_size_set(port, tx_desc, xdpf->len);
3673
3674         if (dma_map) {
3675                 /* XDP_REDIRECT or AF_XDP */
3676                 dma_addr = dma_map_single(port->dev->dev.parent, xdpf->data,
3677                                           xdpf->len, DMA_TO_DEVICE);
3678
3679                 if (unlikely(dma_mapping_error(port->dev->dev.parent, dma_addr))) {
3680                         mvpp2_txq_desc_put(txq);
3681                         ret = MVPP2_XDP_DROPPED;
3682                         goto out;
3683                 }
3684
3685                 buf_type = MVPP2_TYPE_XDP_NDO;
3686         } else {
3687                 /* XDP_TX */
3688                 struct page *page = virt_to_page(xdpf->data);
3689
3690                 dma_addr = page_pool_get_dma_addr(page) +
3691                            sizeof(*xdpf) + xdpf->headroom;
3692                 dma_sync_single_for_device(port->dev->dev.parent, dma_addr,
3693                                            xdpf->len, DMA_BIDIRECTIONAL);
3694
3695                 buf_type = MVPP2_TYPE_XDP_TX;
3696         }
3697
3698         mvpp2_txdesc_dma_addr_set(port, tx_desc, dma_addr);
3699
3700         mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd);
3701         mvpp2_txq_inc_put(port, txq_pcpu, xdpf, tx_desc, buf_type);
3702
3703 out:
3704         return ret;
3705 }
3706
3707 static int
3708 mvpp2_xdp_xmit_back(struct mvpp2_port *port, struct xdp_buff *xdp)
3709 {
3710         struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats);
3711         struct xdp_frame *xdpf;
3712         u16 txq_id;
3713         int ret;
3714
3715         xdpf = xdp_convert_buff_to_frame(xdp);
3716         if (unlikely(!xdpf))
3717                 return MVPP2_XDP_DROPPED;
3718
3719         /* The first of the TX queues are used for XPS,
3720          * the second half for XDP_TX
3721          */
3722         txq_id = mvpp2_cpu_to_thread(port->priv, smp_processor_id()) + (port->ntxqs / 2);
3723
3724         ret = mvpp2_xdp_submit_frame(port, txq_id, xdpf, false);
3725         if (ret == MVPP2_XDP_TX) {
3726                 u64_stats_update_begin(&stats->syncp);
3727                 stats->tx_bytes += xdpf->len;
3728                 stats->tx_packets++;
3729                 stats->xdp_tx++;
3730                 u64_stats_update_end(&stats->syncp);
3731
3732                 mvpp2_xdp_finish_tx(port, txq_id, 1, xdpf->len);
3733         } else {
3734                 u64_stats_update_begin(&stats->syncp);
3735                 stats->xdp_tx_err++;
3736                 u64_stats_update_end(&stats->syncp);
3737         }
3738
3739         return ret;
3740 }
3741
3742 static int
3743 mvpp2_xdp_xmit(struct net_device *dev, int num_frame,
3744                struct xdp_frame **frames, u32 flags)
3745 {
3746         struct mvpp2_port *port = netdev_priv(dev);
3747         int i, nxmit_byte = 0, nxmit = 0;
3748         struct mvpp2_pcpu_stats *stats;
3749         u16 txq_id;
3750         u32 ret;
3751
3752         if (unlikely(test_bit(0, &port->state)))
3753                 return -ENETDOWN;
3754
3755         if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
3756                 return -EINVAL;
3757
3758         /* The first of the TX queues are used for XPS,
3759          * the second half for XDP_TX
3760          */
3761         txq_id = mvpp2_cpu_to_thread(port->priv, smp_processor_id()) + (port->ntxqs / 2);
3762
3763         for (i = 0; i < num_frame; i++) {
3764                 ret = mvpp2_xdp_submit_frame(port, txq_id, frames[i], true);
3765                 if (ret != MVPP2_XDP_TX)
3766                         break;
3767
3768                 nxmit_byte += frames[i]->len;
3769                 nxmit++;
3770         }
3771
3772         if (likely(nxmit > 0))
3773                 mvpp2_xdp_finish_tx(port, txq_id, nxmit, nxmit_byte);
3774
3775         stats = this_cpu_ptr(port->stats);
3776         u64_stats_update_begin(&stats->syncp);
3777         stats->tx_bytes += nxmit_byte;
3778         stats->tx_packets += nxmit;
3779         stats->xdp_xmit += nxmit;
3780         stats->xdp_xmit_err += num_frame - nxmit;
3781         u64_stats_update_end(&stats->syncp);
3782
3783         return nxmit;
3784 }
3785
3786 static int
3787 mvpp2_run_xdp(struct mvpp2_port *port, struct bpf_prog *prog,
3788               struct xdp_buff *xdp, struct page_pool *pp,
3789               struct mvpp2_pcpu_stats *stats)
3790 {
3791         unsigned int len, sync, err;
3792         struct page *page;
3793         u32 ret, act;
3794
3795         len = xdp->data_end - xdp->data_hard_start - MVPP2_SKB_HEADROOM;
3796         act = bpf_prog_run_xdp(prog, xdp);
3797
3798         /* Due xdp_adjust_tail: DMA sync for_device cover max len CPU touch */
3799         sync = xdp->data_end - xdp->data_hard_start - MVPP2_SKB_HEADROOM;
3800         sync = max(sync, len);
3801
3802         switch (act) {
3803         case XDP_PASS:
3804                 stats->xdp_pass++;
3805                 ret = MVPP2_XDP_PASS;
3806                 break;
3807         case XDP_REDIRECT:
3808                 err = xdp_do_redirect(port->dev, xdp, prog);
3809                 if (unlikely(err)) {
3810                         ret = MVPP2_XDP_DROPPED;
3811                         page = virt_to_head_page(xdp->data);
3812                         page_pool_put_page(pp, page, sync, true);
3813                 } else {
3814                         ret = MVPP2_XDP_REDIR;
3815                         stats->xdp_redirect++;
3816                 }
3817                 break;
3818         case XDP_TX:
3819                 ret = mvpp2_xdp_xmit_back(port, xdp);
3820                 if (ret != MVPP2_XDP_TX) {
3821                         page = virt_to_head_page(xdp->data);
3822                         page_pool_put_page(pp, page, sync, true);
3823                 }
3824                 break;
3825         default:
3826                 bpf_warn_invalid_xdp_action(act);
3827                 fallthrough;
3828         case XDP_ABORTED:
3829                 trace_xdp_exception(port->dev, prog, act);
3830                 fallthrough;
3831         case XDP_DROP:
3832                 page = virt_to_head_page(xdp->data);
3833                 page_pool_put_page(pp, page, sync, true);
3834                 ret = MVPP2_XDP_DROPPED;
3835                 stats->xdp_drop++;
3836                 break;
3837         }
3838
3839         return ret;
3840 }
3841
3842 static void mvpp2_buff_hdr_pool_put(struct mvpp2_port *port, struct mvpp2_rx_desc *rx_desc,
3843                                     int pool, u32 rx_status)
3844 {
3845         phys_addr_t phys_addr, phys_addr_next;
3846         dma_addr_t dma_addr, dma_addr_next;
3847         struct mvpp2_buff_hdr *buff_hdr;
3848
3849         phys_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc);
3850         dma_addr = mvpp2_rxdesc_cookie_get(port, rx_desc);
3851
3852         do {
3853                 buff_hdr = (struct mvpp2_buff_hdr *)phys_to_virt(phys_addr);
3854
3855                 phys_addr_next = le32_to_cpu(buff_hdr->next_phys_addr);
3856                 dma_addr_next = le32_to_cpu(buff_hdr->next_dma_addr);
3857
3858                 if (port->priv->hw_version >= MVPP22) {
3859                         phys_addr_next |= ((u64)buff_hdr->next_phys_addr_high << 32);
3860                         dma_addr_next |= ((u64)buff_hdr->next_dma_addr_high << 32);
3861                 }
3862
3863                 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr);
3864
3865                 phys_addr = phys_addr_next;
3866                 dma_addr = dma_addr_next;
3867
3868         } while (!MVPP2_B_HDR_INFO_IS_LAST(le16_to_cpu(buff_hdr->info)));
3869 }
3870
3871 /* Main rx processing */
3872 static int mvpp2_rx(struct mvpp2_port *port, struct napi_struct *napi,
3873                     int rx_todo, struct mvpp2_rx_queue *rxq)
3874 {
3875         struct net_device *dev = port->dev;
3876         struct mvpp2_pcpu_stats ps = {};
3877         enum dma_data_direction dma_dir;
3878         struct bpf_prog *xdp_prog;
3879         struct xdp_buff xdp;
3880         int rx_received;
3881         int rx_done = 0;
3882         u32 xdp_ret = 0;
3883
3884         rcu_read_lock();
3885
3886         xdp_prog = READ_ONCE(port->xdp_prog);
3887
3888         /* Get number of received packets and clamp the to-do */
3889         rx_received = mvpp2_rxq_received(port, rxq->id);
3890         if (rx_todo > rx_received)
3891                 rx_todo = rx_received;
3892
3893         while (rx_done < rx_todo) {
3894                 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
3895                 struct mvpp2_bm_pool *bm_pool;
3896                 struct page_pool *pp = NULL;
3897                 struct sk_buff *skb;
3898                 unsigned int frag_size;
3899                 dma_addr_t dma_addr;
3900                 phys_addr_t phys_addr;
3901                 u32 rx_status, timestamp;
3902                 int pool, rx_bytes, err, ret;
3903                 struct page *page;
3904                 void *data;
3905
3906                 phys_addr = mvpp2_rxdesc_cookie_get(port, rx_desc);
3907                 data = (void *)phys_to_virt(phys_addr);
3908                 page = virt_to_page(data);
3909                 prefetch(page);
3910
3911                 rx_done++;
3912                 rx_status = mvpp2_rxdesc_status_get(port, rx_desc);
3913                 rx_bytes = mvpp2_rxdesc_size_get(port, rx_desc);
3914                 rx_bytes -= MVPP2_MH_SIZE;
3915                 dma_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc);
3916
3917                 pool = (rx_status & MVPP2_RXD_BM_POOL_ID_MASK) >>
3918                         MVPP2_RXD_BM_POOL_ID_OFFS;
3919                 bm_pool = &port->priv->bm_pools[pool];
3920
3921                 if (port->priv->percpu_pools) {
3922                         pp = port->priv->page_pool[pool];
3923                         dma_dir = page_pool_get_dma_dir(pp);
3924                 } else {
3925                         dma_dir = DMA_FROM_DEVICE;
3926                 }
3927
3928                 dma_sync_single_for_cpu(dev->dev.parent, dma_addr,
3929                                         rx_bytes + MVPP2_MH_SIZE,
3930                                         dma_dir);
3931
3932                 /* Buffer header not supported */
3933                 if (rx_status & MVPP2_RXD_BUF_HDR)
3934                         goto err_drop_frame;
3935
3936                 /* In case of an error, release the requested buffer pointer
3937                  * to the Buffer Manager. This request process is controlled
3938                  * by the hardware, and the information about the buffer is
3939                  * comprised by the RX descriptor.
3940                  */
3941                 if (rx_status & MVPP2_RXD_ERR_SUMMARY)
3942                         goto err_drop_frame;
3943
3944                 /* Prefetch header */
3945                 prefetch(data + MVPP2_MH_SIZE + MVPP2_SKB_HEADROOM);
3946
3947                 if (bm_pool->frag_size > PAGE_SIZE)
3948                         frag_size = 0;
3949                 else
3950                         frag_size = bm_pool->frag_size;
3951
3952                 if (xdp_prog) {
3953                         struct xdp_rxq_info *xdp_rxq;
3954
3955                         if (bm_pool->pkt_size == MVPP2_BM_SHORT_PKT_SIZE)
3956                                 xdp_rxq = &rxq->xdp_rxq_short;
3957                         else
3958                                 xdp_rxq = &rxq->xdp_rxq_long;
3959
3960                         xdp_init_buff(&xdp, PAGE_SIZE, xdp_rxq);
3961                         xdp_prepare_buff(&xdp, data,
3962                                          MVPP2_MH_SIZE + MVPP2_SKB_HEADROOM,
3963                                          rx_bytes, false);
3964
3965                         ret = mvpp2_run_xdp(port, xdp_prog, &xdp, pp, &ps);
3966
3967                         if (ret) {
3968                                 xdp_ret |= ret;
3969                                 err = mvpp2_rx_refill(port, bm_pool, pp, pool);
3970                                 if (err) {
3971                                         netdev_err(port->dev, "failed to refill BM pools\n");
3972                                         goto err_drop_frame;
3973                                 }
3974
3975                                 ps.rx_packets++;
3976                                 ps.rx_bytes += rx_bytes;
3977                                 continue;
3978                         }
3979                 }
3980
3981                 skb = build_skb(data, frag_size);
3982                 if (!skb) {
3983                         netdev_warn(port->dev, "skb build failed\n");
3984                         goto err_drop_frame;
3985                 }
3986
3987                 /* If we have RX hardware timestamping enabled, grab the
3988                  * timestamp from the queue and convert.
3989                  */
3990                 if (mvpp22_rx_hwtstamping(port)) {
3991                         timestamp = le32_to_cpu(rx_desc->pp22.timestamp);
3992                         mvpp22_tai_tstamp(port->priv->tai, timestamp,
3993                                          skb_hwtstamps(skb));
3994                 }
3995
3996                 err = mvpp2_rx_refill(port, bm_pool, pp, pool);
3997                 if (err) {
3998                         netdev_err(port->dev, "failed to refill BM pools\n");
3999                         dev_kfree_skb_any(skb);
4000                         goto err_drop_frame;
4001                 }
4002
4003                 if (pp)
4004                         skb_mark_for_recycle(skb, page, pp);
4005                 else
4006                         dma_unmap_single_attrs(dev->dev.parent, dma_addr,
4007                                                bm_pool->buf_size, DMA_FROM_DEVICE,
4008                                                DMA_ATTR_SKIP_CPU_SYNC);
4009
4010                 ps.rx_packets++;
4011                 ps.rx_bytes += rx_bytes;
4012
4013                 skb_reserve(skb, MVPP2_MH_SIZE + MVPP2_SKB_HEADROOM);
4014                 skb_put(skb, rx_bytes);
4015                 mvpp2_rx_csum(port, rx_status, skb);
4016                 skb->protocol = eth_type_trans(skb, dev);
4017
4018                 napi_gro_receive(napi, skb);
4019                 continue;
4020
4021 err_drop_frame:
4022                 dev->stats.rx_errors++;
4023                 mvpp2_rx_error(port, rx_desc);
4024                 /* Return the buffer to the pool */
4025                 if (rx_status & MVPP2_RXD_BUF_HDR)
4026                         mvpp2_buff_hdr_pool_put(port, rx_desc, pool, rx_status);
4027                 else
4028                         mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr);
4029         }
4030
4031         rcu_read_unlock();
4032
4033         if (xdp_ret & MVPP2_XDP_REDIR)
4034                 xdp_do_flush_map();
4035
4036         if (ps.rx_packets) {
4037                 struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats);
4038
4039                 u64_stats_update_begin(&stats->syncp);
4040                 stats->rx_packets += ps.rx_packets;
4041                 stats->rx_bytes   += ps.rx_bytes;
4042                 /* xdp */
4043                 stats->xdp_redirect += ps.xdp_redirect;
4044                 stats->xdp_pass += ps.xdp_pass;
4045                 stats->xdp_drop += ps.xdp_drop;
4046                 u64_stats_update_end(&stats->syncp);
4047         }
4048
4049         /* Update Rx queue management counters */
4050         wmb();
4051         mvpp2_rxq_status_update(port, rxq->id, rx_done, rx_done);
4052
4053         return rx_todo;
4054 }
4055
4056 static inline void
4057 tx_desc_unmap_put(struct mvpp2_port *port, struct mvpp2_tx_queue *txq,
4058                   struct mvpp2_tx_desc *desc)
4059 {
4060         unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
4061         struct mvpp2_txq_pcpu *txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
4062
4063         dma_addr_t buf_dma_addr =
4064                 mvpp2_txdesc_dma_addr_get(port, desc);
4065         size_t buf_sz =
4066                 mvpp2_txdesc_size_get(port, desc);
4067         if (!IS_TSO_HEADER(txq_pcpu, buf_dma_addr))
4068                 dma_unmap_single(port->dev->dev.parent, buf_dma_addr,
4069                                  buf_sz, DMA_TO_DEVICE);
4070         mvpp2_txq_desc_put(txq);
4071 }
4072
4073 static void mvpp2_txdesc_clear_ptp(struct mvpp2_port *port,
4074                                    struct mvpp2_tx_desc *desc)
4075 {
4076         /* We only need to clear the low bits */
4077         if (port->priv->hw_version >= MVPP22)
4078                 desc->pp22.ptp_descriptor &=
4079                         cpu_to_le32(~MVPP22_PTP_DESC_MASK_LOW);
4080 }
4081
4082 static bool mvpp2_tx_hw_tstamp(struct mvpp2_port *port,
4083                                struct mvpp2_tx_desc *tx_desc,
4084                                struct sk_buff *skb)
4085 {
4086         struct mvpp2_hwtstamp_queue *queue;
4087         unsigned int mtype, type, i;
4088         struct ptp_header *hdr;
4089         u64 ptpdesc;
4090
4091         if (port->priv->hw_version == MVPP21 ||
4092             port->tx_hwtstamp_type == HWTSTAMP_TX_OFF)
4093                 return false;
4094
4095         type = ptp_classify_raw(skb);
4096         if (!type)
4097                 return false;
4098
4099         hdr = ptp_parse_header(skb, type);
4100         if (!hdr)
4101                 return false;
4102
4103         skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4104
4105         ptpdesc = MVPP22_PTP_MACTIMESTAMPINGEN |
4106                   MVPP22_PTP_ACTION_CAPTURE;
4107         queue = &port->tx_hwtstamp_queue[0];
4108
4109         switch (type & PTP_CLASS_VMASK) {
4110         case PTP_CLASS_V1:
4111                 ptpdesc |= MVPP22_PTP_PACKETFORMAT(MVPP22_PTP_PKT_FMT_PTPV1);
4112                 break;
4113
4114         case PTP_CLASS_V2:
4115                 ptpdesc |= MVPP22_PTP_PACKETFORMAT(MVPP22_PTP_PKT_FMT_PTPV2);
4116                 mtype = hdr->tsmt & 15;
4117                 /* Direct PTP Sync messages to queue 1 */
4118                 if (mtype == 0) {
4119                         ptpdesc |= MVPP22_PTP_TIMESTAMPQUEUESELECT;
4120                         queue = &port->tx_hwtstamp_queue[1];
4121                 }
4122                 break;
4123         }
4124
4125         /* Take a reference on the skb and insert into our queue */
4126         i = queue->next;
4127         queue->next = (i + 1) & 31;
4128         if (queue->skb[i])
4129                 dev_kfree_skb_any(queue->skb[i]);
4130         queue->skb[i] = skb_get(skb);
4131
4132         ptpdesc |= MVPP22_PTP_TIMESTAMPENTRYID(i);
4133
4134         /*
4135          * 3:0          - PTPAction
4136          * 6:4          - PTPPacketFormat
4137          * 7            - PTP_CF_WraparoundCheckEn
4138          * 9:8          - IngressTimestampSeconds[1:0]
4139          * 10           - Reserved
4140          * 11           - MACTimestampingEn
4141          * 17:12        - PTP_TimestampQueueEntryID[5:0]
4142          * 18           - PTPTimestampQueueSelect
4143          * 19           - UDPChecksumUpdateEn
4144          * 27:20        - TimestampOffset
4145          *                      PTP, NTPTransmit, OWAMP/TWAMP - L3 to PTP header
4146          *                      NTPTs, Y.1731 - L3 to timestamp entry
4147          * 35:28        - UDP Checksum Offset
4148          *
4149          * stored in tx descriptor bits 75:64 (11:0) and 191:168 (35:12)
4150          */
4151         tx_desc->pp22.ptp_descriptor &=
4152                 cpu_to_le32(~MVPP22_PTP_DESC_MASK_LOW);
4153         tx_desc->pp22.ptp_descriptor |=
4154                 cpu_to_le32(ptpdesc & MVPP22_PTP_DESC_MASK_LOW);
4155         tx_desc->pp22.buf_dma_addr_ptp &= cpu_to_le64(~0xffffff0000000000ULL);
4156         tx_desc->pp22.buf_dma_addr_ptp |= cpu_to_le64((ptpdesc >> 12) << 40);
4157
4158         return true;
4159 }
4160
4161 /* Handle tx fragmentation processing */
4162 static int mvpp2_tx_frag_process(struct mvpp2_port *port, struct sk_buff *skb,
4163                                  struct mvpp2_tx_queue *aggr_txq,
4164                                  struct mvpp2_tx_queue *txq)
4165 {
4166         unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
4167         struct mvpp2_txq_pcpu *txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
4168         struct mvpp2_tx_desc *tx_desc;
4169         int i;
4170         dma_addr_t buf_dma_addr;
4171
4172         for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4173                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4174                 void *addr = skb_frag_address(frag);
4175
4176                 tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
4177                 mvpp2_txdesc_clear_ptp(port, tx_desc);
4178                 mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
4179                 mvpp2_txdesc_size_set(port, tx_desc, skb_frag_size(frag));
4180
4181                 buf_dma_addr = dma_map_single(port->dev->dev.parent, addr,
4182                                               skb_frag_size(frag),
4183                                               DMA_TO_DEVICE);
4184                 if (dma_mapping_error(port->dev->dev.parent, buf_dma_addr)) {
4185                         mvpp2_txq_desc_put(txq);
4186                         goto cleanup;
4187                 }
4188
4189                 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr);
4190
4191                 if (i == (skb_shinfo(skb)->nr_frags - 1)) {
4192                         /* Last descriptor */
4193                         mvpp2_txdesc_cmd_set(port, tx_desc,
4194                                              MVPP2_TXD_L_DESC);
4195                         mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc, MVPP2_TYPE_SKB);
4196                 } else {
4197                         /* Descriptor in the middle: Not First, Not Last */
4198                         mvpp2_txdesc_cmd_set(port, tx_desc, 0);
4199                         mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB);
4200                 }
4201         }
4202
4203         return 0;
4204 cleanup:
4205         /* Release all descriptors that were used to map fragments of
4206          * this packet, as well as the corresponding DMA mappings
4207          */
4208         for (i = i - 1; i >= 0; i--) {
4209                 tx_desc = txq->descs + i;
4210                 tx_desc_unmap_put(port, txq, tx_desc);
4211         }
4212
4213         return -ENOMEM;
4214 }
4215
4216 static inline void mvpp2_tso_put_hdr(struct sk_buff *skb,
4217                                      struct net_device *dev,
4218                                      struct mvpp2_tx_queue *txq,
4219                                      struct mvpp2_tx_queue *aggr_txq,
4220                                      struct mvpp2_txq_pcpu *txq_pcpu,
4221                                      int hdr_sz)
4222 {
4223         struct mvpp2_port *port = netdev_priv(dev);
4224         struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
4225         dma_addr_t addr;
4226
4227         mvpp2_txdesc_clear_ptp(port, tx_desc);
4228         mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
4229         mvpp2_txdesc_size_set(port, tx_desc, hdr_sz);
4230
4231         addr = txq_pcpu->tso_headers_dma +
4232                txq_pcpu->txq_put_index * TSO_HEADER_SIZE;
4233         mvpp2_txdesc_dma_addr_set(port, tx_desc, addr);
4234
4235         mvpp2_txdesc_cmd_set(port, tx_desc, mvpp2_skb_tx_csum(port, skb) |
4236                                             MVPP2_TXD_F_DESC |
4237                                             MVPP2_TXD_PADDING_DISABLE);
4238         mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB);
4239 }
4240
4241 static inline int mvpp2_tso_put_data(struct sk_buff *skb,
4242                                      struct net_device *dev, struct tso_t *tso,
4243                                      struct mvpp2_tx_queue *txq,
4244                                      struct mvpp2_tx_queue *aggr_txq,
4245                                      struct mvpp2_txq_pcpu *txq_pcpu,
4246                                      int sz, bool left, bool last)
4247 {
4248         struct mvpp2_port *port = netdev_priv(dev);
4249         struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
4250         dma_addr_t buf_dma_addr;
4251
4252         mvpp2_txdesc_clear_ptp(port, tx_desc);
4253         mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
4254         mvpp2_txdesc_size_set(port, tx_desc, sz);
4255
4256         buf_dma_addr = dma_map_single(dev->dev.parent, tso->data, sz,
4257                                       DMA_TO_DEVICE);
4258         if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) {
4259                 mvpp2_txq_desc_put(txq);
4260                 return -ENOMEM;
4261         }
4262
4263         mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr);
4264
4265         if (!left) {
4266                 mvpp2_txdesc_cmd_set(port, tx_desc, MVPP2_TXD_L_DESC);
4267                 if (last) {
4268                         mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc, MVPP2_TYPE_SKB);
4269                         return 0;
4270                 }
4271         } else {
4272                 mvpp2_txdesc_cmd_set(port, tx_desc, 0);
4273         }
4274
4275         mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB);
4276         return 0;
4277 }
4278
4279 static int mvpp2_tx_tso(struct sk_buff *skb, struct net_device *dev,
4280                         struct mvpp2_tx_queue *txq,
4281                         struct mvpp2_tx_queue *aggr_txq,
4282                         struct mvpp2_txq_pcpu *txq_pcpu)
4283 {
4284         struct mvpp2_port *port = netdev_priv(dev);
4285         int hdr_sz, i, len, descs = 0;
4286         struct tso_t tso;
4287
4288         /* Check number of available descriptors */
4289         if (mvpp2_aggr_desc_num_check(port, aggr_txq, tso_count_descs(skb)) ||
4290             mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu,
4291                                              tso_count_descs(skb)))
4292                 return 0;
4293
4294         hdr_sz = tso_start(skb, &tso);
4295
4296         len = skb->len - hdr_sz;
4297         while (len > 0) {
4298                 int left = min_t(int, skb_shinfo(skb)->gso_size, len);
4299                 char *hdr = txq_pcpu->tso_headers +
4300                             txq_pcpu->txq_put_index * TSO_HEADER_SIZE;
4301
4302                 len -= left;
4303                 descs++;
4304
4305                 tso_build_hdr(skb, hdr, &tso, left, len == 0);
4306                 mvpp2_tso_put_hdr(skb, dev, txq, aggr_txq, txq_pcpu, hdr_sz);
4307
4308                 while (left > 0) {
4309                         int sz = min_t(int, tso.size, left);
4310                         left -= sz;
4311                         descs++;
4312
4313                         if (mvpp2_tso_put_data(skb, dev, &tso, txq, aggr_txq,
4314                                                txq_pcpu, sz, left, len == 0))
4315                                 goto release;
4316                         tso_build_data(skb, &tso, sz);
4317                 }
4318         }
4319
4320         return descs;
4321
4322 release:
4323         for (i = descs - 1; i >= 0; i--) {
4324                 struct mvpp2_tx_desc *tx_desc = txq->descs + i;
4325                 tx_desc_unmap_put(port, txq, tx_desc);
4326         }
4327         return 0;
4328 }
4329
4330 /* Main tx processing */
4331 static netdev_tx_t mvpp2_tx(struct sk_buff *skb, struct net_device *dev)
4332 {
4333         struct mvpp2_port *port = netdev_priv(dev);
4334         struct mvpp2_tx_queue *txq, *aggr_txq;
4335         struct mvpp2_txq_pcpu *txq_pcpu;
4336         struct mvpp2_tx_desc *tx_desc;
4337         dma_addr_t buf_dma_addr;
4338         unsigned long flags = 0;
4339         unsigned int thread;
4340         int frags = 0;
4341         u16 txq_id;
4342         u32 tx_cmd;
4343
4344         thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
4345
4346         txq_id = skb_get_queue_mapping(skb);
4347         txq = port->txqs[txq_id];
4348         txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
4349         aggr_txq = &port->priv->aggr_txqs[thread];
4350
4351         if (test_bit(thread, &port->priv->lock_map))
4352                 spin_lock_irqsave(&port->tx_lock[thread], flags);
4353
4354         if (skb_is_gso(skb)) {
4355                 frags = mvpp2_tx_tso(skb, dev, txq, aggr_txq, txq_pcpu);
4356                 goto out;
4357         }
4358         frags = skb_shinfo(skb)->nr_frags + 1;
4359
4360         /* Check number of available descriptors */
4361         if (mvpp2_aggr_desc_num_check(port, aggr_txq, frags) ||
4362             mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu, frags)) {
4363                 frags = 0;
4364                 goto out;
4365         }
4366
4367         /* Get a descriptor for the first part of the packet */
4368         tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
4369         if (!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ||
4370             !mvpp2_tx_hw_tstamp(port, tx_desc, skb))
4371                 mvpp2_txdesc_clear_ptp(port, tx_desc);
4372         mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
4373         mvpp2_txdesc_size_set(port, tx_desc, skb_headlen(skb));
4374
4375         buf_dma_addr = dma_map_single(dev->dev.parent, skb->data,
4376                                       skb_headlen(skb), DMA_TO_DEVICE);
4377         if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) {
4378                 mvpp2_txq_desc_put(txq);
4379                 frags = 0;
4380                 goto out;
4381         }
4382
4383         mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr);
4384
4385         tx_cmd = mvpp2_skb_tx_csum(port, skb);
4386
4387         if (frags == 1) {
4388                 /* First and Last descriptor */
4389                 tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC;
4390                 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd);
4391                 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc, MVPP2_TYPE_SKB);
4392         } else {
4393                 /* First but not Last */
4394                 tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_PADDING_DISABLE;
4395                 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd);
4396                 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB);
4397
4398                 /* Continue with other skb fragments */
4399                 if (mvpp2_tx_frag_process(port, skb, aggr_txq, txq)) {
4400                         tx_desc_unmap_put(port, txq, tx_desc);
4401                         frags = 0;
4402                 }
4403         }
4404
4405 out:
4406         if (frags > 0) {
4407                 struct mvpp2_pcpu_stats *stats = per_cpu_ptr(port->stats, thread);
4408                 struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id);
4409
4410                 txq_pcpu->reserved_num -= frags;
4411                 txq_pcpu->count += frags;
4412                 aggr_txq->count += frags;
4413
4414                 /* Enable transmit */
4415                 wmb();
4416                 mvpp2_aggr_txq_pend_desc_add(port, frags);
4417
4418                 if (txq_pcpu->count >= txq_pcpu->stop_threshold)
4419                         netif_tx_stop_queue(nq);
4420
4421                 u64_stats_update_begin(&stats->syncp);
4422                 stats->tx_packets++;
4423                 stats->tx_bytes += skb->len;
4424                 u64_stats_update_end(&stats->syncp);
4425         } else {
4426                 dev->stats.tx_dropped++;
4427                 dev_kfree_skb_any(skb);
4428         }
4429
4430         /* Finalize TX processing */
4431         if (!port->has_tx_irqs && txq_pcpu->count >= txq->done_pkts_coal)
4432                 mvpp2_txq_done(port, txq, txq_pcpu);
4433
4434         /* Set the timer in case not all frags were processed */
4435         if (!port->has_tx_irqs && txq_pcpu->count <= frags &&
4436             txq_pcpu->count > 0) {
4437                 struct mvpp2_port_pcpu *port_pcpu = per_cpu_ptr(port->pcpu, thread);
4438
4439                 if (!port_pcpu->timer_scheduled) {
4440                         port_pcpu->timer_scheduled = true;
4441                         hrtimer_start(&port_pcpu->tx_done_timer,
4442                                       MVPP2_TXDONE_HRTIMER_PERIOD_NS,
4443                                       HRTIMER_MODE_REL_PINNED_SOFT);
4444                 }
4445         }
4446
4447         if (test_bit(thread, &port->priv->lock_map))
4448                 spin_unlock_irqrestore(&port->tx_lock[thread], flags);
4449
4450         return NETDEV_TX_OK;
4451 }
4452
4453 static inline void mvpp2_cause_error(struct net_device *dev, int cause)
4454 {
4455         if (cause & MVPP2_CAUSE_FCS_ERR_MASK)
4456                 netdev_err(dev, "FCS error\n");
4457         if (cause & MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK)
4458                 netdev_err(dev, "rx fifo overrun error\n");
4459         if (cause & MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK)
4460                 netdev_err(dev, "tx fifo underrun error\n");
4461 }
4462
4463 static int mvpp2_poll(struct napi_struct *napi, int budget)
4464 {
4465         u32 cause_rx_tx, cause_rx, cause_tx, cause_misc;
4466         int rx_done = 0;
4467         struct mvpp2_port *port = netdev_priv(napi->dev);
4468         struct mvpp2_queue_vector *qv;
4469         unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
4470
4471         qv = container_of(napi, struct mvpp2_queue_vector, napi);
4472
4473         /* Rx/Tx cause register
4474          *
4475          * Bits 0-15: each bit indicates received packets on the Rx queue
4476          * (bit 0 is for Rx queue 0).
4477          *
4478          * Bits 16-23: each bit indicates transmitted packets on the Tx queue
4479          * (bit 16 is for Tx queue 0).
4480          *
4481          * Each CPU has its own Rx/Tx cause register
4482          */
4483         cause_rx_tx = mvpp2_thread_read_relaxed(port->priv, qv->sw_thread_id,
4484                                                 MVPP2_ISR_RX_TX_CAUSE_REG(port->id));
4485
4486         cause_misc = cause_rx_tx & MVPP2_CAUSE_MISC_SUM_MASK;
4487         if (cause_misc) {
4488                 mvpp2_cause_error(port->dev, cause_misc);
4489
4490                 /* Clear the cause register */
4491                 mvpp2_write(port->priv, MVPP2_ISR_MISC_CAUSE_REG, 0);
4492                 mvpp2_thread_write(port->priv, thread,
4493                                    MVPP2_ISR_RX_TX_CAUSE_REG(port->id),
4494                                    cause_rx_tx & ~MVPP2_CAUSE_MISC_SUM_MASK);
4495         }
4496
4497         if (port->has_tx_irqs) {
4498                 cause_tx = cause_rx_tx & MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK;
4499                 if (cause_tx) {
4500                         cause_tx >>= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_OFFSET;
4501                         mvpp2_tx_done(port, cause_tx, qv->sw_thread_id);
4502                 }
4503         }
4504
4505         /* Process RX packets */
4506         cause_rx = cause_rx_tx &
4507                    MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version);
4508         cause_rx <<= qv->first_rxq;
4509         cause_rx |= qv->pending_cause_rx;
4510         while (cause_rx && budget > 0) {
4511                 int count;
4512                 struct mvpp2_rx_queue *rxq;
4513
4514                 rxq = mvpp2_get_rx_queue(port, cause_rx);
4515                 if (!rxq)
4516                         break;
4517
4518                 count = mvpp2_rx(port, napi, budget, rxq);
4519                 rx_done += count;
4520                 budget -= count;
4521                 if (budget > 0) {
4522                         /* Clear the bit associated to this Rx queue
4523                          * so that next iteration will continue from
4524                          * the next Rx queue.
4525                          */
4526                         cause_rx &= ~(1 << rxq->logic_rxq);
4527                 }
4528         }
4529
4530         if (budget > 0) {
4531                 cause_rx = 0;
4532                 napi_complete_done(napi, rx_done);
4533
4534                 mvpp2_qvec_interrupt_enable(qv);
4535         }
4536         qv->pending_cause_rx = cause_rx;
4537         return rx_done;
4538 }
4539
4540 static void mvpp22_mode_reconfigure(struct mvpp2_port *port)
4541 {
4542         u32 ctrl3;
4543
4544         /* Set the GMAC & XLG MAC in reset */
4545         mvpp2_mac_reset_assert(port);
4546
4547         /* Set the MPCS and XPCS in reset */
4548         mvpp22_pcs_reset_assert(port);
4549
4550         /* comphy reconfiguration */
4551         mvpp22_comphy_init(port);
4552
4553         /* gop reconfiguration */
4554         mvpp22_gop_init(port);
4555
4556         mvpp22_pcs_reset_deassert(port);
4557
4558         if (mvpp2_port_supports_xlg(port)) {
4559                 ctrl3 = readl(port->base + MVPP22_XLG_CTRL3_REG);
4560                 ctrl3 &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
4561
4562                 if (mvpp2_is_xlg(port->phy_interface))
4563                         ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_10G;
4564                 else
4565                         ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_GMAC;
4566
4567                 writel(ctrl3, port->base + MVPP22_XLG_CTRL3_REG);
4568         }
4569
4570         if (mvpp2_port_supports_xlg(port) && mvpp2_is_xlg(port->phy_interface))
4571                 mvpp2_xlg_max_rx_size_set(port);
4572         else
4573                 mvpp2_gmac_max_rx_size_set(port);
4574 }
4575
4576 /* Set hw internals when starting port */
4577 static void mvpp2_start_dev(struct mvpp2_port *port)
4578 {
4579         int i;
4580
4581         mvpp2_txp_max_tx_size_set(port);
4582
4583         for (i = 0; i < port->nqvecs; i++)
4584                 napi_enable(&port->qvecs[i].napi);
4585
4586         /* Enable interrupts on all threads */
4587         mvpp2_interrupts_enable(port);
4588
4589         if (port->priv->hw_version >= MVPP22)
4590                 mvpp22_mode_reconfigure(port);
4591
4592         if (port->phylink) {
4593                 phylink_start(port->phylink);
4594         } else {
4595                 mvpp2_acpi_start(port);
4596         }
4597
4598         netif_tx_start_all_queues(port->dev);
4599
4600         clear_bit(0, &port->state);
4601 }
4602
4603 /* Set hw internals when stopping port */
4604 static void mvpp2_stop_dev(struct mvpp2_port *port)
4605 {
4606         int i;
4607
4608         set_bit(0, &port->state);
4609
4610         /* Disable interrupts on all threads */
4611         mvpp2_interrupts_disable(port);
4612
4613         for (i = 0; i < port->nqvecs; i++)
4614                 napi_disable(&port->qvecs[i].napi);
4615
4616         if (port->phylink)
4617                 phylink_stop(port->phylink);
4618         phy_power_off(port->comphy);
4619 }
4620
4621 static int mvpp2_check_ringparam_valid(struct net_device *dev,
4622                                        struct ethtool_ringparam *ring)
4623 {
4624         u16 new_rx_pending = ring->rx_pending;
4625         u16 new_tx_pending = ring->tx_pending;
4626
4627         if (ring->rx_pending == 0 || ring->tx_pending == 0)
4628                 return -EINVAL;
4629
4630         if (ring->rx_pending > MVPP2_MAX_RXD_MAX)
4631                 new_rx_pending = MVPP2_MAX_RXD_MAX;
4632         else if (ring->rx_pending < MSS_THRESHOLD_START)
4633                 new_rx_pending = MSS_THRESHOLD_START;
4634         else if (!IS_ALIGNED(ring->rx_pending, 16))
4635                 new_rx_pending = ALIGN(ring->rx_pending, 16);
4636
4637         if (ring->tx_pending > MVPP2_MAX_TXD_MAX)
4638                 new_tx_pending = MVPP2_MAX_TXD_MAX;
4639         else if (!IS_ALIGNED(ring->tx_pending, 32))
4640                 new_tx_pending = ALIGN(ring->tx_pending, 32);
4641
4642         /* The Tx ring size cannot be smaller than the minimum number of
4643          * descriptors needed for TSO.
4644          */
4645         if (new_tx_pending < MVPP2_MAX_SKB_DESCS)
4646                 new_tx_pending = ALIGN(MVPP2_MAX_SKB_DESCS, 32);
4647
4648         if (ring->rx_pending != new_rx_pending) {
4649                 netdev_info(dev, "illegal Rx ring size value %d, round to %d\n",
4650                             ring->rx_pending, new_rx_pending);
4651                 ring->rx_pending = new_rx_pending;
4652         }
4653
4654         if (ring->tx_pending != new_tx_pending) {
4655                 netdev_info(dev, "illegal Tx ring size value %d, round to %d\n",
4656                             ring->tx_pending, new_tx_pending);
4657                 ring->tx_pending = new_tx_pending;
4658         }
4659
4660         return 0;
4661 }
4662
4663 static void mvpp21_get_mac_address(struct mvpp2_port *port, unsigned char *addr)
4664 {
4665         u32 mac_addr_l, mac_addr_m, mac_addr_h;
4666
4667         mac_addr_l = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
4668         mac_addr_m = readl(port->priv->lms_base + MVPP2_SRC_ADDR_MIDDLE);
4669         mac_addr_h = readl(port->priv->lms_base + MVPP2_SRC_ADDR_HIGH);
4670         addr[0] = (mac_addr_h >> 24) & 0xFF;
4671         addr[1] = (mac_addr_h >> 16) & 0xFF;
4672         addr[2] = (mac_addr_h >> 8) & 0xFF;
4673         addr[3] = mac_addr_h & 0xFF;
4674         addr[4] = mac_addr_m & 0xFF;
4675         addr[5] = (mac_addr_l >> MVPP2_GMAC_SA_LOW_OFFS) & 0xFF;
4676 }
4677
4678 static int mvpp2_irqs_init(struct mvpp2_port *port)
4679 {
4680         int err, i;
4681
4682         for (i = 0; i < port->nqvecs; i++) {
4683                 struct mvpp2_queue_vector *qv = port->qvecs + i;
4684
4685                 if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE) {
4686                         qv->mask = kzalloc(cpumask_size(), GFP_KERNEL);
4687                         if (!qv->mask) {
4688                                 err = -ENOMEM;
4689                                 goto err;
4690                         }
4691
4692                         irq_set_status_flags(qv->irq, IRQ_NO_BALANCING);
4693                 }
4694
4695                 err = request_irq(qv->irq, mvpp2_isr, 0, port->dev->name, qv);
4696                 if (err)
4697                         goto err;
4698
4699                 if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE) {
4700                         unsigned int cpu;
4701
4702                         for_each_present_cpu(cpu) {
4703                                 if (mvpp2_cpu_to_thread(port->priv, cpu) ==
4704                                     qv->sw_thread_id)
4705                                         cpumask_set_cpu(cpu, qv->mask);
4706                         }
4707
4708                         irq_set_affinity_hint(qv->irq, qv->mask);
4709                 }
4710         }
4711
4712         return 0;
4713 err:
4714         for (i = 0; i < port->nqvecs; i++) {
4715                 struct mvpp2_queue_vector *qv = port->qvecs + i;
4716
4717                 irq_set_affinity_hint(qv->irq, NULL);
4718                 kfree(qv->mask);
4719                 qv->mask = NULL;
4720                 free_irq(qv->irq, qv);
4721         }
4722
4723         return err;
4724 }
4725
4726 static void mvpp2_irqs_deinit(struct mvpp2_port *port)
4727 {
4728         int i;
4729
4730         for (i = 0; i < port->nqvecs; i++) {
4731                 struct mvpp2_queue_vector *qv = port->qvecs + i;
4732
4733                 irq_set_affinity_hint(qv->irq, NULL);
4734                 kfree(qv->mask);
4735                 qv->mask = NULL;
4736                 irq_clear_status_flags(qv->irq, IRQ_NO_BALANCING);
4737                 free_irq(qv->irq, qv);
4738         }
4739 }
4740
4741 static bool mvpp22_rss_is_supported(struct mvpp2_port *port)
4742 {
4743         return (queue_mode == MVPP2_QDIST_MULTI_MODE) &&
4744                 !(port->flags & MVPP2_F_LOOPBACK);
4745 }
4746
4747 static int mvpp2_open(struct net_device *dev)
4748 {
4749         struct mvpp2_port *port = netdev_priv(dev);
4750         struct mvpp2 *priv = port->priv;
4751         unsigned char mac_bcast[ETH_ALEN] = {
4752                         0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
4753         bool valid = false;
4754         int err;
4755
4756         err = mvpp2_prs_mac_da_accept(port, mac_bcast, true);
4757         if (err) {
4758                 netdev_err(dev, "mvpp2_prs_mac_da_accept BC failed\n");
4759                 return err;
4760         }
4761         err = mvpp2_prs_mac_da_accept(port, dev->dev_addr, true);
4762         if (err) {
4763                 netdev_err(dev, "mvpp2_prs_mac_da_accept own addr failed\n");
4764                 return err;
4765         }
4766         err = mvpp2_prs_tag_mode_set(port->priv, port->id, MVPP2_TAG_TYPE_MH);
4767         if (err) {
4768                 netdev_err(dev, "mvpp2_prs_tag_mode_set failed\n");
4769                 return err;
4770         }
4771         err = mvpp2_prs_def_flow(port);
4772         if (err) {
4773                 netdev_err(dev, "mvpp2_prs_def_flow failed\n");
4774                 return err;
4775         }
4776
4777         /* Allocate the Rx/Tx queues */
4778         err = mvpp2_setup_rxqs(port);
4779         if (err) {
4780                 netdev_err(port->dev, "cannot allocate Rx queues\n");
4781                 return err;
4782         }
4783
4784         err = mvpp2_setup_txqs(port);
4785         if (err) {
4786                 netdev_err(port->dev, "cannot allocate Tx queues\n");
4787                 goto err_cleanup_rxqs;
4788         }
4789
4790         err = mvpp2_irqs_init(port);
4791         if (err) {
4792                 netdev_err(port->dev, "cannot init IRQs\n");
4793                 goto err_cleanup_txqs;
4794         }
4795
4796         /* Phylink isn't supported yet in ACPI mode */
4797         if (port->of_node) {
4798                 err = phylink_of_phy_connect(port->phylink, port->of_node, 0);
4799                 if (err) {
4800                         netdev_err(port->dev, "could not attach PHY (%d)\n",
4801                                    err);
4802                         goto err_free_irq;
4803                 }
4804
4805                 valid = true;
4806         }
4807
4808         if (priv->hw_version >= MVPP22 && port->port_irq) {
4809                 err = request_irq(port->port_irq, mvpp2_port_isr, 0,
4810                                   dev->name, port);
4811                 if (err) {
4812                         netdev_err(port->dev,
4813                                    "cannot request port link/ptp IRQ %d\n",
4814                                    port->port_irq);
4815                         goto err_free_irq;
4816                 }
4817
4818                 mvpp22_gop_setup_irq(port);
4819
4820                 /* In default link is down */
4821                 netif_carrier_off(port->dev);
4822
4823                 valid = true;
4824         } else {
4825                 port->port_irq = 0;
4826         }
4827
4828         if (!valid) {
4829                 netdev_err(port->dev,
4830                            "invalid configuration: no dt or link IRQ");
4831                 err = -ENOENT;
4832                 goto err_free_irq;
4833         }
4834
4835         /* Unmask interrupts on all CPUs */
4836         on_each_cpu(mvpp2_interrupts_unmask, port, 1);
4837         mvpp2_shared_interrupt_mask_unmask(port, false);
4838
4839         mvpp2_start_dev(port);
4840
4841         /* Start hardware statistics gathering */
4842         queue_delayed_work(priv->stats_queue, &port->stats_work,
4843                            MVPP2_MIB_COUNTERS_STATS_DELAY);
4844
4845         return 0;
4846
4847 err_free_irq:
4848         mvpp2_irqs_deinit(port);
4849 err_cleanup_txqs:
4850         mvpp2_cleanup_txqs(port);
4851 err_cleanup_rxqs:
4852         mvpp2_cleanup_rxqs(port);
4853         return err;
4854 }
4855
4856 static int mvpp2_stop(struct net_device *dev)
4857 {
4858         struct mvpp2_port *port = netdev_priv(dev);
4859         struct mvpp2_port_pcpu *port_pcpu;
4860         unsigned int thread;
4861
4862         mvpp2_stop_dev(port);
4863
4864         /* Mask interrupts on all threads */
4865         on_each_cpu(mvpp2_interrupts_mask, port, 1);
4866         mvpp2_shared_interrupt_mask_unmask(port, true);
4867
4868         if (port->phylink)
4869                 phylink_disconnect_phy(port->phylink);
4870         if (port->port_irq)
4871                 free_irq(port->port_irq, port);
4872
4873         mvpp2_irqs_deinit(port);
4874         if (!port->has_tx_irqs) {
4875                 for (thread = 0; thread < port->priv->nthreads; thread++) {
4876                         port_pcpu = per_cpu_ptr(port->pcpu, thread);
4877
4878                         hrtimer_cancel(&port_pcpu->tx_done_timer);
4879                         port_pcpu->timer_scheduled = false;
4880                 }
4881         }
4882         mvpp2_cleanup_rxqs(port);
4883         mvpp2_cleanup_txqs(port);
4884
4885         cancel_delayed_work_sync(&port->stats_work);
4886
4887         mvpp2_mac_reset_assert(port);
4888         mvpp22_pcs_reset_assert(port);
4889
4890         return 0;
4891 }
4892
4893 static int mvpp2_prs_mac_da_accept_list(struct mvpp2_port *port,
4894                                         struct netdev_hw_addr_list *list)
4895 {
4896         struct netdev_hw_addr *ha;
4897         int ret;
4898
4899         netdev_hw_addr_list_for_each(ha, list) {
4900                 ret = mvpp2_prs_mac_da_accept(port, ha->addr, true);
4901                 if (ret)
4902                         return ret;
4903         }
4904
4905         return 0;
4906 }
4907
4908 static void mvpp2_set_rx_promisc(struct mvpp2_port *port, bool enable)
4909 {
4910         if (!enable && (port->dev->features & NETIF_F_HW_VLAN_CTAG_FILTER))
4911                 mvpp2_prs_vid_enable_filtering(port);
4912         else
4913                 mvpp2_prs_vid_disable_filtering(port);
4914
4915         mvpp2_prs_mac_promisc_set(port->priv, port->id,
4916                                   MVPP2_PRS_L2_UNI_CAST, enable);
4917
4918         mvpp2_prs_mac_promisc_set(port->priv, port->id,
4919                                   MVPP2_PRS_L2_MULTI_CAST, enable);
4920 }
4921
4922 static void mvpp2_set_rx_mode(struct net_device *dev)
4923 {
4924         struct mvpp2_port *port = netdev_priv(dev);
4925
4926         /* Clear the whole UC and MC list */
4927         mvpp2_prs_mac_del_all(port);
4928
4929         if (dev->flags & IFF_PROMISC) {
4930                 mvpp2_set_rx_promisc(port, true);
4931                 return;
4932         }
4933
4934         mvpp2_set_rx_promisc(port, false);
4935
4936         if (netdev_uc_count(dev) > MVPP2_PRS_MAC_UC_FILT_MAX ||
4937             mvpp2_prs_mac_da_accept_list(port, &dev->uc))
4938                 mvpp2_prs_mac_promisc_set(port->priv, port->id,
4939                                           MVPP2_PRS_L2_UNI_CAST, true);
4940
4941         if (dev->flags & IFF_ALLMULTI) {
4942                 mvpp2_prs_mac_promisc_set(port->priv, port->id,
4943                                           MVPP2_PRS_L2_MULTI_CAST, true);
4944                 return;
4945         }
4946
4947         if (netdev_mc_count(dev) > MVPP2_PRS_MAC_MC_FILT_MAX ||
4948             mvpp2_prs_mac_da_accept_list(port, &dev->mc))
4949                 mvpp2_prs_mac_promisc_set(port->priv, port->id,
4950                                           MVPP2_PRS_L2_MULTI_CAST, true);
4951 }
4952
4953 static int mvpp2_set_mac_address(struct net_device *dev, void *p)
4954 {
4955         const struct sockaddr *addr = p;
4956         int err;
4957
4958         if (!is_valid_ether_addr(addr->sa_data))
4959                 return -EADDRNOTAVAIL;
4960
4961         err = mvpp2_prs_update_mac_da(dev, addr->sa_data);
4962         if (err) {
4963                 /* Reconfigure parser accept the original MAC address */
4964                 mvpp2_prs_update_mac_da(dev, dev->dev_addr);
4965                 netdev_err(dev, "failed to change MAC address\n");
4966         }
4967         return err;
4968 }
4969
4970 /* Shut down all the ports, reconfigure the pools as percpu or shared,
4971  * then bring up again all ports.
4972  */
4973 static int mvpp2_bm_switch_buffers(struct mvpp2 *priv, bool percpu)
4974 {
4975         bool change_percpu = (percpu != priv->percpu_pools);
4976         int numbufs = MVPP2_BM_POOLS_NUM, i;
4977         struct mvpp2_port *port = NULL;
4978         bool status[MVPP2_MAX_PORTS];
4979
4980         for (i = 0; i < priv->port_count; i++) {
4981                 port = priv->port_list[i];
4982                 status[i] = netif_running(port->dev);
4983                 if (status[i])
4984                         mvpp2_stop(port->dev);
4985         }
4986
4987         /* nrxqs is the same for all ports */
4988         if (priv->percpu_pools)
4989                 numbufs = port->nrxqs * 2;
4990
4991         if (change_percpu)
4992                 mvpp2_bm_pool_update_priv_fc(priv, false);
4993
4994         for (i = 0; i < numbufs; i++)
4995                 mvpp2_bm_pool_destroy(port->dev->dev.parent, priv, &priv->bm_pools[i]);
4996
4997         devm_kfree(port->dev->dev.parent, priv->bm_pools);
4998         priv->percpu_pools = percpu;
4999         mvpp2_bm_init(port->dev->dev.parent, priv);
5000
5001         for (i = 0; i < priv->port_count; i++) {
5002                 port = priv->port_list[i];
5003                 mvpp2_swf_bm_pool_init(port);
5004                 if (status[i])
5005                         mvpp2_open(port->dev);
5006         }
5007
5008         if (change_percpu)
5009                 mvpp2_bm_pool_update_priv_fc(priv, true);
5010
5011         return 0;
5012 }
5013
5014 static int mvpp2_change_mtu(struct net_device *dev, int mtu)
5015 {
5016         struct mvpp2_port *port = netdev_priv(dev);
5017         bool running = netif_running(dev);
5018         struct mvpp2 *priv = port->priv;
5019         int err;
5020
5021         if (!IS_ALIGNED(MVPP2_RX_PKT_SIZE(mtu), 8)) {
5022                 netdev_info(dev, "illegal MTU value %d, round to %d\n", mtu,
5023                             ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8));
5024                 mtu = ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8);
5025         }
5026
5027         if (MVPP2_RX_PKT_SIZE(mtu) > MVPP2_BM_LONG_PKT_SIZE) {
5028                 if (port->xdp_prog) {
5029                         netdev_err(dev, "Jumbo frames are not supported with XDP\n");
5030                         return -EINVAL;
5031                 }
5032                 if (priv->percpu_pools) {
5033                         netdev_warn(dev, "mtu %d too high, switching to shared buffers", mtu);
5034                         mvpp2_bm_switch_buffers(priv, false);
5035                 }
5036         } else {
5037                 bool jumbo = false;
5038                 int i;
5039
5040                 for (i = 0; i < priv->port_count; i++)
5041                         if (priv->port_list[i] != port &&
5042                             MVPP2_RX_PKT_SIZE(priv->port_list[i]->dev->mtu) >
5043                             MVPP2_BM_LONG_PKT_SIZE) {
5044                                 jumbo = true;
5045                                 break;
5046                         }
5047
5048                 /* No port is using jumbo frames */
5049                 if (!jumbo) {
5050                         dev_info(port->dev->dev.parent,
5051                                  "all ports have a low MTU, switching to per-cpu buffers");
5052                         mvpp2_bm_switch_buffers(priv, true);
5053                 }
5054         }
5055
5056         if (running)
5057                 mvpp2_stop_dev(port);
5058
5059         err = mvpp2_bm_update_mtu(dev, mtu);
5060         if (err) {
5061                 netdev_err(dev, "failed to change MTU\n");
5062                 /* Reconfigure BM to the original MTU */
5063                 mvpp2_bm_update_mtu(dev, dev->mtu);
5064         } else {
5065                 port->pkt_size =  MVPP2_RX_PKT_SIZE(mtu);
5066         }
5067
5068         if (running) {
5069                 mvpp2_start_dev(port);
5070                 mvpp2_egress_enable(port);
5071                 mvpp2_ingress_enable(port);
5072         }
5073
5074         return err;
5075 }
5076
5077 static int mvpp2_check_pagepool_dma(struct mvpp2_port *port)
5078 {
5079         enum dma_data_direction dma_dir = DMA_FROM_DEVICE;
5080         struct mvpp2 *priv = port->priv;
5081         int err = -1, i;
5082
5083         if (!priv->percpu_pools)
5084                 return err;
5085
5086         if (!priv->page_pool[0])
5087                 return -ENOMEM;
5088
5089         for (i = 0; i < priv->port_count; i++) {
5090                 port = priv->port_list[i];
5091                 if (port->xdp_prog) {
5092                         dma_dir = DMA_BIDIRECTIONAL;
5093                         break;
5094                 }
5095         }
5096
5097         /* All pools are equal in terms of DMA direction */
5098         if (priv->page_pool[0]->p.dma_dir != dma_dir)
5099                 err = mvpp2_bm_switch_buffers(priv, true);
5100
5101         return err;
5102 }
5103
5104 static void
5105 mvpp2_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
5106 {
5107         struct mvpp2_port *port = netdev_priv(dev);
5108         unsigned int start;
5109         unsigned int cpu;
5110
5111         for_each_possible_cpu(cpu) {
5112                 struct mvpp2_pcpu_stats *cpu_stats;
5113                 u64 rx_packets;
5114                 u64 rx_bytes;
5115                 u64 tx_packets;
5116                 u64 tx_bytes;
5117
5118                 cpu_stats = per_cpu_ptr(port->stats, cpu);
5119                 do {
5120                         start = u64_stats_fetch_begin_irq(&cpu_stats->syncp);
5121                         rx_packets = cpu_stats->rx_packets;
5122                         rx_bytes   = cpu_stats->rx_bytes;
5123                         tx_packets = cpu_stats->tx_packets;
5124                         tx_bytes   = cpu_stats->tx_bytes;
5125                 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start));
5126
5127                 stats->rx_packets += rx_packets;
5128                 stats->rx_bytes   += rx_bytes;
5129                 stats->tx_packets += tx_packets;
5130                 stats->tx_bytes   += tx_bytes;
5131         }
5132
5133         stats->rx_errors        = dev->stats.rx_errors;
5134         stats->rx_dropped       = dev->stats.rx_dropped;
5135         stats->tx_dropped       = dev->stats.tx_dropped;
5136 }
5137
5138 static int mvpp2_set_ts_config(struct mvpp2_port *port, struct ifreq *ifr)
5139 {
5140         struct hwtstamp_config config;
5141         void __iomem *ptp;
5142         u32 gcr, int_mask;
5143
5144         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
5145                 return -EFAULT;
5146
5147         if (config.flags)
5148                 return -EINVAL;
5149
5150         if (config.tx_type != HWTSTAMP_TX_OFF &&
5151             config.tx_type != HWTSTAMP_TX_ON)
5152                 return -ERANGE;
5153
5154         ptp = port->priv->iface_base + MVPP22_PTP_BASE(port->gop_id);
5155
5156         int_mask = gcr = 0;
5157         if (config.tx_type != HWTSTAMP_TX_OFF) {
5158                 gcr |= MVPP22_PTP_GCR_TSU_ENABLE | MVPP22_PTP_GCR_TX_RESET;
5159                 int_mask |= MVPP22_PTP_INT_MASK_QUEUE1 |
5160                             MVPP22_PTP_INT_MASK_QUEUE0;
5161         }
5162
5163         /* It seems we must also release the TX reset when enabling the TSU */
5164         if (config.rx_filter != HWTSTAMP_FILTER_NONE)
5165                 gcr |= MVPP22_PTP_GCR_TSU_ENABLE | MVPP22_PTP_GCR_RX_RESET |
5166                        MVPP22_PTP_GCR_TX_RESET;
5167
5168         if (gcr & MVPP22_PTP_GCR_TSU_ENABLE)
5169                 mvpp22_tai_start(port->priv->tai);
5170
5171         if (config.rx_filter != HWTSTAMP_FILTER_NONE) {
5172                 config.rx_filter = HWTSTAMP_FILTER_ALL;
5173                 mvpp2_modify(ptp + MVPP22_PTP_GCR,
5174                              MVPP22_PTP_GCR_RX_RESET |
5175                              MVPP22_PTP_GCR_TX_RESET |
5176                              MVPP22_PTP_GCR_TSU_ENABLE, gcr);
5177                 port->rx_hwtstamp = true;
5178         } else {
5179                 port->rx_hwtstamp = false;
5180                 mvpp2_modify(ptp + MVPP22_PTP_GCR,
5181                              MVPP22_PTP_GCR_RX_RESET |
5182                              MVPP22_PTP_GCR_TX_RESET |
5183                              MVPP22_PTP_GCR_TSU_ENABLE, gcr);
5184         }
5185
5186         mvpp2_modify(ptp + MVPP22_PTP_INT_MASK,
5187                      MVPP22_PTP_INT_MASK_QUEUE1 |
5188                      MVPP22_PTP_INT_MASK_QUEUE0, int_mask);
5189
5190         if (!(gcr & MVPP22_PTP_GCR_TSU_ENABLE))
5191                 mvpp22_tai_stop(port->priv->tai);
5192
5193         port->tx_hwtstamp_type = config.tx_type;
5194
5195         if (copy_to_user(ifr->ifr_data, &config, sizeof(config)))
5196                 return -EFAULT;
5197
5198         return 0;
5199 }
5200
5201 static int mvpp2_get_ts_config(struct mvpp2_port *port, struct ifreq *ifr)
5202 {
5203         struct hwtstamp_config config;
5204
5205         memset(&config, 0, sizeof(config));
5206
5207         config.tx_type = port->tx_hwtstamp_type;
5208         config.rx_filter = port->rx_hwtstamp ?
5209                 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE;
5210
5211         if (copy_to_user(ifr->ifr_data, &config, sizeof(config)))
5212                 return -EFAULT;
5213
5214         return 0;
5215 }
5216
5217 static int mvpp2_ethtool_get_ts_info(struct net_device *dev,
5218                                      struct ethtool_ts_info *info)
5219 {
5220         struct mvpp2_port *port = netdev_priv(dev);
5221
5222         if (!port->hwtstamp)
5223                 return -EOPNOTSUPP;
5224
5225         info->phc_index = mvpp22_tai_ptp_clock_index(port->priv->tai);
5226         info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
5227                                 SOF_TIMESTAMPING_RX_SOFTWARE |
5228                                 SOF_TIMESTAMPING_SOFTWARE |
5229                                 SOF_TIMESTAMPING_TX_HARDWARE |
5230                                 SOF_TIMESTAMPING_RX_HARDWARE |
5231                                 SOF_TIMESTAMPING_RAW_HARDWARE;
5232         info->tx_types = BIT(HWTSTAMP_TX_OFF) |
5233                          BIT(HWTSTAMP_TX_ON);
5234         info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) |
5235                            BIT(HWTSTAMP_FILTER_ALL);
5236
5237         return 0;
5238 }
5239
5240 static int mvpp2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
5241 {
5242         struct mvpp2_port *port = netdev_priv(dev);
5243
5244         switch (cmd) {
5245         case SIOCSHWTSTAMP:
5246                 if (port->hwtstamp)
5247                         return mvpp2_set_ts_config(port, ifr);
5248                 break;
5249
5250         case SIOCGHWTSTAMP:
5251                 if (port->hwtstamp)
5252                         return mvpp2_get_ts_config(port, ifr);
5253                 break;
5254         }
5255
5256         if (!port->phylink)
5257                 return -ENOTSUPP;
5258
5259         return phylink_mii_ioctl(port->phylink, ifr, cmd);
5260 }
5261
5262 static int mvpp2_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid)
5263 {
5264         struct mvpp2_port *port = netdev_priv(dev);
5265         int ret;
5266
5267         ret = mvpp2_prs_vid_entry_add(port, vid);
5268         if (ret)
5269                 netdev_err(dev, "rx-vlan-filter offloading cannot accept more than %d VIDs per port\n",
5270                            MVPP2_PRS_VLAN_FILT_MAX - 1);
5271         return ret;
5272 }
5273
5274 static int mvpp2_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid)
5275 {
5276         struct mvpp2_port *port = netdev_priv(dev);
5277
5278         mvpp2_prs_vid_entry_remove(port, vid);
5279         return 0;
5280 }
5281
5282 static int mvpp2_set_features(struct net_device *dev,
5283                               netdev_features_t features)
5284 {
5285         netdev_features_t changed = dev->features ^ features;
5286         struct mvpp2_port *port = netdev_priv(dev);
5287
5288         if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) {
5289                 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) {
5290                         mvpp2_prs_vid_enable_filtering(port);
5291                 } else {
5292                         /* Invalidate all registered VID filters for this
5293                          * port
5294                          */
5295                         mvpp2_prs_vid_remove_all(port);
5296
5297                         mvpp2_prs_vid_disable_filtering(port);
5298                 }
5299         }
5300
5301         if (changed & NETIF_F_RXHASH) {
5302                 if (features & NETIF_F_RXHASH)
5303                         mvpp22_port_rss_enable(port);
5304                 else
5305                         mvpp22_port_rss_disable(port);
5306         }
5307
5308         return 0;
5309 }
5310
5311 static int mvpp2_xdp_setup(struct mvpp2_port *port, struct netdev_bpf *bpf)
5312 {
5313         struct bpf_prog *prog = bpf->prog, *old_prog;
5314         bool running = netif_running(port->dev);
5315         bool reset = !prog != !port->xdp_prog;
5316
5317         if (port->dev->mtu > ETH_DATA_LEN) {
5318                 NL_SET_ERR_MSG_MOD(bpf->extack, "XDP is not supported with jumbo frames enabled");
5319                 return -EOPNOTSUPP;
5320         }
5321
5322         if (!port->priv->percpu_pools) {
5323                 NL_SET_ERR_MSG_MOD(bpf->extack, "Per CPU Pools required for XDP");
5324                 return -EOPNOTSUPP;
5325         }
5326
5327         if (port->ntxqs < num_possible_cpus() * 2) {
5328                 NL_SET_ERR_MSG_MOD(bpf->extack, "XDP_TX needs two TX queues per CPU");
5329                 return -EOPNOTSUPP;
5330         }
5331
5332         /* device is up and bpf is added/removed, must setup the RX queues */
5333         if (running && reset)
5334                 mvpp2_stop(port->dev);
5335
5336         old_prog = xchg(&port->xdp_prog, prog);
5337         if (old_prog)
5338                 bpf_prog_put(old_prog);
5339
5340         /* bpf is just replaced, RXQ and MTU are already setup */
5341         if (!reset)
5342                 return 0;
5343
5344         /* device was up, restore the link */
5345         if (running)
5346                 mvpp2_open(port->dev);
5347
5348         /* Check Page Pool DMA Direction */
5349         mvpp2_check_pagepool_dma(port);
5350
5351         return 0;
5352 }
5353
5354 static int mvpp2_xdp(struct net_device *dev, struct netdev_bpf *xdp)
5355 {
5356         struct mvpp2_port *port = netdev_priv(dev);
5357
5358         switch (xdp->command) {
5359         case XDP_SETUP_PROG:
5360                 return mvpp2_xdp_setup(port, xdp);
5361         default:
5362                 return -EINVAL;
5363         }
5364 }
5365
5366 /* Ethtool methods */
5367
5368 static int mvpp2_ethtool_nway_reset(struct net_device *dev)
5369 {
5370         struct mvpp2_port *port = netdev_priv(dev);
5371
5372         if (!port->phylink)
5373                 return -ENOTSUPP;
5374
5375         return phylink_ethtool_nway_reset(port->phylink);
5376 }
5377
5378 /* Set interrupt coalescing for ethtools */
5379 static int mvpp2_ethtool_set_coalesce(struct net_device *dev,
5380                                       struct ethtool_coalesce *c)
5381 {
5382         struct mvpp2_port *port = netdev_priv(dev);
5383         int queue;
5384
5385         for (queue = 0; queue < port->nrxqs; queue++) {
5386                 struct mvpp2_rx_queue *rxq = port->rxqs[queue];
5387
5388                 rxq->time_coal = c->rx_coalesce_usecs;
5389                 rxq->pkts_coal = c->rx_max_coalesced_frames;
5390                 mvpp2_rx_pkts_coal_set(port, rxq);
5391                 mvpp2_rx_time_coal_set(port, rxq);
5392         }
5393
5394         if (port->has_tx_irqs) {
5395                 port->tx_time_coal = c->tx_coalesce_usecs;
5396                 mvpp2_tx_time_coal_set(port);
5397         }
5398
5399         for (queue = 0; queue < port->ntxqs; queue++) {
5400                 struct mvpp2_tx_queue *txq = port->txqs[queue];
5401
5402                 txq->done_pkts_coal = c->tx_max_coalesced_frames;
5403
5404                 if (port->has_tx_irqs)
5405                         mvpp2_tx_pkts_coal_set(port, txq);
5406         }
5407
5408         return 0;
5409 }
5410
5411 /* get coalescing for ethtools */
5412 static int mvpp2_ethtool_get_coalesce(struct net_device *dev,
5413                                       struct ethtool_coalesce *c)
5414 {
5415         struct mvpp2_port *port = netdev_priv(dev);
5416
5417         c->rx_coalesce_usecs       = port->rxqs[0]->time_coal;
5418         c->rx_max_coalesced_frames = port->rxqs[0]->pkts_coal;
5419         c->tx_max_coalesced_frames = port->txqs[0]->done_pkts_coal;
5420         c->tx_coalesce_usecs       = port->tx_time_coal;
5421         return 0;
5422 }
5423
5424 static void mvpp2_ethtool_get_drvinfo(struct net_device *dev,
5425                                       struct ethtool_drvinfo *drvinfo)
5426 {
5427         strlcpy(drvinfo->driver, MVPP2_DRIVER_NAME,
5428                 sizeof(drvinfo->driver));
5429         strlcpy(drvinfo->version, MVPP2_DRIVER_VERSION,
5430                 sizeof(drvinfo->version));
5431         strlcpy(drvinfo->bus_info, dev_name(&dev->dev),
5432                 sizeof(drvinfo->bus_info));
5433 }
5434
5435 static void mvpp2_ethtool_get_ringparam(struct net_device *dev,
5436                                         struct ethtool_ringparam *ring)
5437 {
5438         struct mvpp2_port *port = netdev_priv(dev);
5439
5440         ring->rx_max_pending = MVPP2_MAX_RXD_MAX;
5441         ring->tx_max_pending = MVPP2_MAX_TXD_MAX;
5442         ring->rx_pending = port->rx_ring_size;
5443         ring->tx_pending = port->tx_ring_size;
5444 }
5445
5446 static int mvpp2_ethtool_set_ringparam(struct net_device *dev,
5447                                        struct ethtool_ringparam *ring)
5448 {
5449         struct mvpp2_port *port = netdev_priv(dev);
5450         u16 prev_rx_ring_size = port->rx_ring_size;
5451         u16 prev_tx_ring_size = port->tx_ring_size;
5452         int err;
5453
5454         err = mvpp2_check_ringparam_valid(dev, ring);
5455         if (err)
5456                 return err;
5457
5458         if (!netif_running(dev)) {
5459                 port->rx_ring_size = ring->rx_pending;
5460                 port->tx_ring_size = ring->tx_pending;
5461                 return 0;
5462         }
5463
5464         /* The interface is running, so we have to force a
5465          * reallocation of the queues
5466          */
5467         mvpp2_stop_dev(port);
5468         mvpp2_cleanup_rxqs(port);
5469         mvpp2_cleanup_txqs(port);
5470
5471         port->rx_ring_size = ring->rx_pending;
5472         port->tx_ring_size = ring->tx_pending;
5473
5474         err = mvpp2_setup_rxqs(port);
5475         if (err) {
5476                 /* Reallocate Rx queues with the original ring size */
5477                 port->rx_ring_size = prev_rx_ring_size;
5478                 ring->rx_pending = prev_rx_ring_size;
5479                 err = mvpp2_setup_rxqs(port);
5480                 if (err)
5481                         goto err_out;
5482         }
5483         err = mvpp2_setup_txqs(port);
5484         if (err) {
5485                 /* Reallocate Tx queues with the original ring size */
5486                 port->tx_ring_size = prev_tx_ring_size;
5487                 ring->tx_pending = prev_tx_ring_size;
5488                 err = mvpp2_setup_txqs(port);
5489                 if (err)
5490                         goto err_clean_rxqs;
5491         }
5492
5493         mvpp2_start_dev(port);
5494         mvpp2_egress_enable(port);
5495         mvpp2_ingress_enable(port);
5496
5497         return 0;
5498
5499 err_clean_rxqs:
5500         mvpp2_cleanup_rxqs(port);
5501 err_out:
5502         netdev_err(dev, "failed to change ring parameters");
5503         return err;
5504 }
5505
5506 static void mvpp2_ethtool_get_pause_param(struct net_device *dev,
5507                                           struct ethtool_pauseparam *pause)
5508 {
5509         struct mvpp2_port *port = netdev_priv(dev);
5510
5511         if (!port->phylink)
5512                 return;
5513
5514         phylink_ethtool_get_pauseparam(port->phylink, pause);
5515 }
5516
5517 static int mvpp2_ethtool_set_pause_param(struct net_device *dev,
5518                                          struct ethtool_pauseparam *pause)
5519 {
5520         struct mvpp2_port *port = netdev_priv(dev);
5521
5522         if (!port->phylink)
5523                 return -ENOTSUPP;
5524
5525         return phylink_ethtool_set_pauseparam(port->phylink, pause);
5526 }
5527
5528 static int mvpp2_ethtool_get_link_ksettings(struct net_device *dev,
5529                                             struct ethtool_link_ksettings *cmd)
5530 {
5531         struct mvpp2_port *port = netdev_priv(dev);
5532
5533         if (!port->phylink)
5534                 return -ENOTSUPP;
5535
5536         return phylink_ethtool_ksettings_get(port->phylink, cmd);
5537 }
5538
5539 static int mvpp2_ethtool_set_link_ksettings(struct net_device *dev,
5540                                             const struct ethtool_link_ksettings *cmd)
5541 {
5542         struct mvpp2_port *port = netdev_priv(dev);
5543
5544         if (!port->phylink)
5545                 return -ENOTSUPP;
5546
5547         return phylink_ethtool_ksettings_set(port->phylink, cmd);
5548 }
5549
5550 static int mvpp2_ethtool_get_rxnfc(struct net_device *dev,
5551                                    struct ethtool_rxnfc *info, u32 *rules)
5552 {
5553         struct mvpp2_port *port = netdev_priv(dev);
5554         int ret = 0, i, loc = 0;
5555
5556         if (!mvpp22_rss_is_supported(port))
5557                 return -EOPNOTSUPP;
5558
5559         switch (info->cmd) {
5560         case ETHTOOL_GRXFH:
5561                 ret = mvpp2_ethtool_rxfh_get(port, info);
5562                 break;
5563         case ETHTOOL_GRXRINGS:
5564                 info->data = port->nrxqs;
5565                 break;
5566         case ETHTOOL_GRXCLSRLCNT:
5567                 info->rule_cnt = port->n_rfs_rules;
5568                 break;
5569         case ETHTOOL_GRXCLSRULE:
5570                 ret = mvpp2_ethtool_cls_rule_get(port, info);
5571                 break;
5572         case ETHTOOL_GRXCLSRLALL:
5573                 for (i = 0; i < MVPP2_N_RFS_ENTRIES_PER_FLOW; i++) {
5574                         if (port->rfs_rules[i])
5575                                 rules[loc++] = i;
5576                 }
5577                 break;
5578         default:
5579                 return -ENOTSUPP;
5580         }
5581
5582         return ret;
5583 }
5584
5585 static int mvpp2_ethtool_set_rxnfc(struct net_device *dev,
5586                                    struct ethtool_rxnfc *info)
5587 {
5588         struct mvpp2_port *port = netdev_priv(dev);
5589         int ret = 0;
5590
5591         if (!mvpp22_rss_is_supported(port))
5592                 return -EOPNOTSUPP;
5593
5594         switch (info->cmd) {
5595         case ETHTOOL_SRXFH:
5596                 ret = mvpp2_ethtool_rxfh_set(port, info);
5597                 break;
5598         case ETHTOOL_SRXCLSRLINS:
5599                 ret = mvpp2_ethtool_cls_rule_ins(port, info);
5600                 break;
5601         case ETHTOOL_SRXCLSRLDEL:
5602                 ret = mvpp2_ethtool_cls_rule_del(port, info);
5603                 break;
5604         default:
5605                 return -EOPNOTSUPP;
5606         }
5607         return ret;
5608 }
5609
5610 static u32 mvpp2_ethtool_get_rxfh_indir_size(struct net_device *dev)
5611 {
5612         struct mvpp2_port *port = netdev_priv(dev);
5613
5614         return mvpp22_rss_is_supported(port) ? MVPP22_RSS_TABLE_ENTRIES : 0;
5615 }
5616
5617 static int mvpp2_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
5618                                   u8 *hfunc)
5619 {
5620         struct mvpp2_port *port = netdev_priv(dev);
5621         int ret = 0;
5622
5623         if (!mvpp22_rss_is_supported(port))
5624                 return -EOPNOTSUPP;
5625
5626         if (indir)
5627                 ret = mvpp22_port_rss_ctx_indir_get(port, 0, indir);
5628
5629         if (hfunc)
5630                 *hfunc = ETH_RSS_HASH_CRC32;
5631
5632         return ret;
5633 }
5634
5635 static int mvpp2_ethtool_set_rxfh(struct net_device *dev, const u32 *indir,
5636                                   const u8 *key, const u8 hfunc)
5637 {
5638         struct mvpp2_port *port = netdev_priv(dev);
5639         int ret = 0;
5640
5641         if (!mvpp22_rss_is_supported(port))
5642                 return -EOPNOTSUPP;
5643
5644         if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_CRC32)
5645                 return -EOPNOTSUPP;
5646
5647         if (key)
5648                 return -EOPNOTSUPP;
5649
5650         if (indir)
5651                 ret = mvpp22_port_rss_ctx_indir_set(port, 0, indir);
5652
5653         return ret;
5654 }
5655
5656 static int mvpp2_ethtool_get_rxfh_context(struct net_device *dev, u32 *indir,
5657                                           u8 *key, u8 *hfunc, u32 rss_context)
5658 {
5659         struct mvpp2_port *port = netdev_priv(dev);
5660         int ret = 0;
5661
5662         if (!mvpp22_rss_is_supported(port))
5663                 return -EOPNOTSUPP;
5664         if (rss_context >= MVPP22_N_RSS_TABLES)
5665                 return -EINVAL;
5666
5667         if (hfunc)
5668                 *hfunc = ETH_RSS_HASH_CRC32;
5669
5670         if (indir)
5671                 ret = mvpp22_port_rss_ctx_indir_get(port, rss_context, indir);
5672
5673         return ret;
5674 }
5675
5676 static int mvpp2_ethtool_set_rxfh_context(struct net_device *dev,
5677                                           const u32 *indir, const u8 *key,
5678                                           const u8 hfunc, u32 *rss_context,
5679                                           bool delete)
5680 {
5681         struct mvpp2_port *port = netdev_priv(dev);
5682         int ret;
5683
5684         if (!mvpp22_rss_is_supported(port))
5685                 return -EOPNOTSUPP;
5686
5687         if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_CRC32)
5688                 return -EOPNOTSUPP;
5689
5690         if (key)
5691                 return -EOPNOTSUPP;
5692
5693         if (delete)
5694                 return mvpp22_port_rss_ctx_delete(port, *rss_context);
5695
5696         if (*rss_context == ETH_RXFH_CONTEXT_ALLOC) {
5697                 ret = mvpp22_port_rss_ctx_create(port, rss_context);
5698                 if (ret)
5699                         return ret;
5700         }
5701
5702         return mvpp22_port_rss_ctx_indir_set(port, *rss_context, indir);
5703 }
5704 /* Device ops */
5705
5706 static const struct net_device_ops mvpp2_netdev_ops = {
5707         .ndo_open               = mvpp2_open,
5708         .ndo_stop               = mvpp2_stop,
5709         .ndo_start_xmit         = mvpp2_tx,
5710         .ndo_set_rx_mode        = mvpp2_set_rx_mode,
5711         .ndo_set_mac_address    = mvpp2_set_mac_address,
5712         .ndo_change_mtu         = mvpp2_change_mtu,
5713         .ndo_get_stats64        = mvpp2_get_stats64,
5714         .ndo_do_ioctl           = mvpp2_ioctl,
5715         .ndo_vlan_rx_add_vid    = mvpp2_vlan_rx_add_vid,
5716         .ndo_vlan_rx_kill_vid   = mvpp2_vlan_rx_kill_vid,
5717         .ndo_set_features       = mvpp2_set_features,
5718         .ndo_bpf                = mvpp2_xdp,
5719         .ndo_xdp_xmit           = mvpp2_xdp_xmit,
5720 };
5721
5722 static const struct ethtool_ops mvpp2_eth_tool_ops = {
5723         .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
5724                                      ETHTOOL_COALESCE_MAX_FRAMES,
5725         .nway_reset             = mvpp2_ethtool_nway_reset,
5726         .get_link               = ethtool_op_get_link,
5727         .get_ts_info            = mvpp2_ethtool_get_ts_info,
5728         .set_coalesce           = mvpp2_ethtool_set_coalesce,
5729         .get_coalesce           = mvpp2_ethtool_get_coalesce,
5730         .get_drvinfo            = mvpp2_ethtool_get_drvinfo,
5731         .get_ringparam          = mvpp2_ethtool_get_ringparam,
5732         .set_ringparam          = mvpp2_ethtool_set_ringparam,
5733         .get_strings            = mvpp2_ethtool_get_strings,
5734         .get_ethtool_stats      = mvpp2_ethtool_get_stats,
5735         .get_sset_count         = mvpp2_ethtool_get_sset_count,
5736         .get_pauseparam         = mvpp2_ethtool_get_pause_param,
5737         .set_pauseparam         = mvpp2_ethtool_set_pause_param,
5738         .get_link_ksettings     = mvpp2_ethtool_get_link_ksettings,
5739         .set_link_ksettings     = mvpp2_ethtool_set_link_ksettings,
5740         .get_rxnfc              = mvpp2_ethtool_get_rxnfc,
5741         .set_rxnfc              = mvpp2_ethtool_set_rxnfc,
5742         .get_rxfh_indir_size    = mvpp2_ethtool_get_rxfh_indir_size,
5743         .get_rxfh               = mvpp2_ethtool_get_rxfh,
5744         .set_rxfh               = mvpp2_ethtool_set_rxfh,
5745         .get_rxfh_context       = mvpp2_ethtool_get_rxfh_context,
5746         .set_rxfh_context       = mvpp2_ethtool_set_rxfh_context,
5747 };
5748
5749 /* Used for PPv2.1, or PPv2.2 with the old Device Tree binding that
5750  * had a single IRQ defined per-port.
5751  */
5752 static int mvpp2_simple_queue_vectors_init(struct mvpp2_port *port,
5753                                            struct device_node *port_node)
5754 {
5755         struct mvpp2_queue_vector *v = &port->qvecs[0];
5756
5757         v->first_rxq = 0;
5758         v->nrxqs = port->nrxqs;
5759         v->type = MVPP2_QUEUE_VECTOR_SHARED;
5760         v->sw_thread_id = 0;
5761         v->sw_thread_mask = *cpumask_bits(cpu_online_mask);
5762         v->port = port;
5763         v->irq = irq_of_parse_and_map(port_node, 0);
5764         if (v->irq <= 0)
5765                 return -EINVAL;
5766         netif_napi_add(port->dev, &v->napi, mvpp2_poll,
5767                        NAPI_POLL_WEIGHT);
5768
5769         port->nqvecs = 1;
5770
5771         return 0;
5772 }
5773
5774 static int mvpp2_multi_queue_vectors_init(struct mvpp2_port *port,
5775                                           struct device_node *port_node)
5776 {
5777         struct mvpp2 *priv = port->priv;
5778         struct mvpp2_queue_vector *v;
5779         int i, ret;
5780
5781         switch (queue_mode) {
5782         case MVPP2_QDIST_SINGLE_MODE:
5783                 port->nqvecs = priv->nthreads + 1;
5784                 break;
5785         case MVPP2_QDIST_MULTI_MODE:
5786                 port->nqvecs = priv->nthreads;
5787                 break;
5788         }
5789
5790         for (i = 0; i < port->nqvecs; i++) {
5791                 char irqname[16];
5792
5793                 v = port->qvecs + i;
5794
5795                 v->port = port;
5796                 v->type = MVPP2_QUEUE_VECTOR_PRIVATE;
5797                 v->sw_thread_id = i;
5798                 v->sw_thread_mask = BIT(i);
5799
5800                 if (port->flags & MVPP2_F_DT_COMPAT)
5801                         snprintf(irqname, sizeof(irqname), "tx-cpu%d", i);
5802                 else
5803                         snprintf(irqname, sizeof(irqname), "hif%d", i);
5804
5805                 if (queue_mode == MVPP2_QDIST_MULTI_MODE) {
5806                         v->first_rxq = i;
5807                         v->nrxqs = 1;
5808                 } else if (queue_mode == MVPP2_QDIST_SINGLE_MODE &&
5809                            i == (port->nqvecs - 1)) {
5810                         v->first_rxq = 0;
5811                         v->nrxqs = port->nrxqs;
5812                         v->type = MVPP2_QUEUE_VECTOR_SHARED;
5813
5814                         if (port->flags & MVPP2_F_DT_COMPAT)
5815                                 strncpy(irqname, "rx-shared", sizeof(irqname));
5816                 }
5817
5818                 if (port_node)
5819                         v->irq = of_irq_get_byname(port_node, irqname);
5820                 else
5821                         v->irq = fwnode_irq_get(port->fwnode, i);
5822                 if (v->irq <= 0) {
5823                         ret = -EINVAL;
5824                         goto err;
5825                 }
5826
5827                 netif_napi_add(port->dev, &v->napi, mvpp2_poll,
5828                                NAPI_POLL_WEIGHT);
5829         }
5830
5831         return 0;
5832
5833 err:
5834         for (i = 0; i < port->nqvecs; i++)
5835                 irq_dispose_mapping(port->qvecs[i].irq);
5836         return ret;
5837 }
5838
5839 static int mvpp2_queue_vectors_init(struct mvpp2_port *port,
5840                                     struct device_node *port_node)
5841 {
5842         if (port->has_tx_irqs)
5843                 return mvpp2_multi_queue_vectors_init(port, port_node);
5844         else
5845                 return mvpp2_simple_queue_vectors_init(port, port_node);
5846 }
5847
5848 static void mvpp2_queue_vectors_deinit(struct mvpp2_port *port)
5849 {
5850         int i;
5851
5852         for (i = 0; i < port->nqvecs; i++)
5853                 irq_dispose_mapping(port->qvecs[i].irq);
5854 }
5855
5856 /* Configure Rx queue group interrupt for this port */
5857 static void mvpp2_rx_irqs_setup(struct mvpp2_port *port)
5858 {
5859         struct mvpp2 *priv = port->priv;
5860         u32 val;
5861         int i;
5862
5863         if (priv->hw_version == MVPP21) {
5864                 mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(port->id),
5865                             port->nrxqs);
5866                 return;
5867         }
5868
5869         /* Handle the more complicated PPv2.2 and PPv2.3 case */
5870         for (i = 0; i < port->nqvecs; i++) {
5871                 struct mvpp2_queue_vector *qv = port->qvecs + i;
5872
5873                 if (!qv->nrxqs)
5874                         continue;
5875
5876                 val = qv->sw_thread_id;
5877                 val |= port->id << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET;
5878                 mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val);
5879
5880                 val = qv->first_rxq;
5881                 val |= qv->nrxqs << MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET;
5882                 mvpp2_write(priv, MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val);
5883         }
5884 }
5885
5886 /* Initialize port HW */
5887 static int mvpp2_port_init(struct mvpp2_port *port)
5888 {
5889         struct device *dev = port->dev->dev.parent;
5890         struct mvpp2 *priv = port->priv;
5891         struct mvpp2_txq_pcpu *txq_pcpu;
5892         unsigned int thread;
5893         int queue, err, val;
5894
5895         /* Checks for hardware constraints */
5896         if (port->first_rxq + port->nrxqs >
5897             MVPP2_MAX_PORTS * priv->max_port_rxqs)
5898                 return -EINVAL;
5899
5900         if (port->nrxqs > priv->max_port_rxqs || port->ntxqs > MVPP2_MAX_TXQ)
5901                 return -EINVAL;
5902
5903         /* Disable port */
5904         mvpp2_egress_disable(port);
5905         mvpp2_port_disable(port);
5906
5907         if (mvpp2_is_xlg(port->phy_interface)) {
5908                 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
5909                 val &= ~MVPP22_XLG_CTRL0_FORCE_LINK_PASS;
5910                 val |= MVPP22_XLG_CTRL0_FORCE_LINK_DOWN;
5911                 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
5912         } else {
5913                 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
5914                 val &= ~MVPP2_GMAC_FORCE_LINK_PASS;
5915                 val |= MVPP2_GMAC_FORCE_LINK_DOWN;
5916                 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
5917         }
5918
5919         port->tx_time_coal = MVPP2_TXDONE_COAL_USEC;
5920
5921         port->txqs = devm_kcalloc(dev, port->ntxqs, sizeof(*port->txqs),
5922                                   GFP_KERNEL);
5923         if (!port->txqs)
5924                 return -ENOMEM;
5925
5926         /* Associate physical Tx queues to this port and initialize.
5927          * The mapping is predefined.
5928          */
5929         for (queue = 0; queue < port->ntxqs; queue++) {
5930                 int queue_phy_id = mvpp2_txq_phys(port->id, queue);
5931                 struct mvpp2_tx_queue *txq;
5932
5933                 txq = devm_kzalloc(dev, sizeof(*txq), GFP_KERNEL);
5934                 if (!txq) {
5935                         err = -ENOMEM;
5936                         goto err_free_percpu;
5937                 }
5938
5939                 txq->pcpu = alloc_percpu(struct mvpp2_txq_pcpu);
5940                 if (!txq->pcpu) {
5941                         err = -ENOMEM;
5942                         goto err_free_percpu;
5943                 }
5944
5945                 txq->id = queue_phy_id;
5946                 txq->log_id = queue;
5947                 txq->done_pkts_coal = MVPP2_TXDONE_COAL_PKTS_THRESH;
5948                 for (thread = 0; thread < priv->nthreads; thread++) {
5949                         txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
5950                         txq_pcpu->thread = thread;
5951                 }
5952
5953                 port->txqs[queue] = txq;
5954         }
5955
5956         port->rxqs = devm_kcalloc(dev, port->nrxqs, sizeof(*port->rxqs),
5957                                   GFP_KERNEL);
5958         if (!port->rxqs) {
5959                 err = -ENOMEM;
5960                 goto err_free_percpu;
5961         }
5962
5963         /* Allocate and initialize Rx queue for this port */
5964         for (queue = 0; queue < port->nrxqs; queue++) {
5965                 struct mvpp2_rx_queue *rxq;
5966
5967                 /* Map physical Rx queue to port's logical Rx queue */
5968                 rxq = devm_kzalloc(dev, sizeof(*rxq), GFP_KERNEL);
5969                 if (!rxq) {
5970                         err = -ENOMEM;
5971                         goto err_free_percpu;
5972                 }
5973                 /* Map this Rx queue to a physical queue */
5974                 rxq->id = port->first_rxq + queue;
5975                 rxq->port = port->id;
5976                 rxq->logic_rxq = queue;
5977
5978                 port->rxqs[queue] = rxq;
5979         }
5980
5981         mvpp2_rx_irqs_setup(port);
5982
5983         /* Create Rx descriptor rings */
5984         for (queue = 0; queue < port->nrxqs; queue++) {
5985                 struct mvpp2_rx_queue *rxq = port->rxqs[queue];
5986
5987                 rxq->size = port->rx_ring_size;
5988                 rxq->pkts_coal = MVPP2_RX_COAL_PKTS;
5989                 rxq->time_coal = MVPP2_RX_COAL_USEC;
5990         }
5991
5992         mvpp2_ingress_disable(port);
5993
5994         /* Port default configuration */
5995         mvpp2_defaults_set(port);
5996
5997         /* Port's classifier configuration */
5998         mvpp2_cls_oversize_rxq_set(port);
5999         mvpp2_cls_port_config(port);
6000
6001         if (mvpp22_rss_is_supported(port))
6002                 mvpp22_port_rss_init(port);
6003
6004         /* Provide an initial Rx packet size */
6005         port->pkt_size = MVPP2_RX_PKT_SIZE(port->dev->mtu);
6006
6007         /* Initialize pools for swf */
6008         err = mvpp2_swf_bm_pool_init(port);
6009         if (err)
6010                 goto err_free_percpu;
6011
6012         /* Clear all port stats */
6013         mvpp2_read_stats(port);
6014         memset(port->ethtool_stats, 0,
6015                MVPP2_N_ETHTOOL_STATS(port->ntxqs, port->nrxqs) * sizeof(u64));
6016
6017         return 0;
6018
6019 err_free_percpu:
6020         for (queue = 0; queue < port->ntxqs; queue++) {
6021                 if (!port->txqs[queue])
6022                         continue;
6023                 free_percpu(port->txqs[queue]->pcpu);
6024         }
6025         return err;
6026 }
6027
6028 static bool mvpp22_port_has_legacy_tx_irqs(struct device_node *port_node,
6029                                            unsigned long *flags)
6030 {
6031         char *irqs[5] = { "rx-shared", "tx-cpu0", "tx-cpu1", "tx-cpu2",
6032                           "tx-cpu3" };
6033         int i;
6034
6035         for (i = 0; i < 5; i++)
6036                 if (of_property_match_string(port_node, "interrupt-names",
6037                                              irqs[i]) < 0)
6038                         return false;
6039
6040         *flags |= MVPP2_F_DT_COMPAT;
6041         return true;
6042 }
6043
6044 /* Checks if the port dt description has the required Tx interrupts:
6045  * - PPv2.1: there are no such interrupts.
6046  * - PPv2.2 and PPv2.3:
6047  *   - The old DTs have: "rx-shared", "tx-cpuX" with X in [0...3]
6048  *   - The new ones have: "hifX" with X in [0..8]
6049  *
6050  * All those variants are supported to keep the backward compatibility.
6051  */
6052 static bool mvpp2_port_has_irqs(struct mvpp2 *priv,
6053                                 struct device_node *port_node,
6054                                 unsigned long *flags)
6055 {
6056         char name[5];
6057         int i;
6058
6059         /* ACPI */
6060         if (!port_node)
6061                 return true;
6062
6063         if (priv->hw_version == MVPP21)
6064                 return false;
6065
6066         if (mvpp22_port_has_legacy_tx_irqs(port_node, flags))
6067                 return true;
6068
6069         for (i = 0; i < MVPP2_MAX_THREADS; i++) {
6070                 snprintf(name, 5, "hif%d", i);
6071                 if (of_property_match_string(port_node, "interrupt-names",
6072                                              name) < 0)
6073                         return false;
6074         }
6075
6076         return true;
6077 }
6078
6079 static void mvpp2_port_copy_mac_addr(struct net_device *dev, struct mvpp2 *priv,
6080                                      struct fwnode_handle *fwnode,
6081                                      char **mac_from)
6082 {
6083         struct mvpp2_port *port = netdev_priv(dev);
6084         char hw_mac_addr[ETH_ALEN] = {0};
6085         char fw_mac_addr[ETH_ALEN];
6086
6087         if (fwnode_get_mac_address(fwnode, fw_mac_addr, ETH_ALEN)) {
6088                 *mac_from = "firmware node";
6089                 ether_addr_copy(dev->dev_addr, fw_mac_addr);
6090                 return;
6091         }
6092
6093         if (priv->hw_version == MVPP21) {
6094                 mvpp21_get_mac_address(port, hw_mac_addr);
6095                 if (is_valid_ether_addr(hw_mac_addr)) {
6096                         *mac_from = "hardware";
6097                         ether_addr_copy(dev->dev_addr, hw_mac_addr);
6098                         return;
6099                 }
6100         }
6101
6102         *mac_from = "random";
6103         eth_hw_addr_random(dev);
6104 }
6105
6106 static struct mvpp2_port *mvpp2_phylink_to_port(struct phylink_config *config)
6107 {
6108         return container_of(config, struct mvpp2_port, phylink_config);
6109 }
6110
6111 static struct mvpp2_port *mvpp2_pcs_to_port(struct phylink_pcs *pcs)
6112 {
6113         return container_of(pcs, struct mvpp2_port, phylink_pcs);
6114 }
6115
6116 static void mvpp2_xlg_pcs_get_state(struct phylink_pcs *pcs,
6117                                     struct phylink_link_state *state)
6118 {
6119         struct mvpp2_port *port = mvpp2_pcs_to_port(pcs);
6120         u32 val;
6121
6122         state->speed = SPEED_10000;
6123         state->duplex = 1;
6124         state->an_complete = 1;
6125
6126         val = readl(port->base + MVPP22_XLG_STATUS);
6127         state->link = !!(val & MVPP22_XLG_STATUS_LINK_UP);
6128
6129         state->pause = 0;
6130         val = readl(port->base + MVPP22_XLG_CTRL0_REG);
6131         if (val & MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN)
6132                 state->pause |= MLO_PAUSE_TX;
6133         if (val & MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN)
6134                 state->pause |= MLO_PAUSE_RX;
6135 }
6136
6137 static int mvpp2_xlg_pcs_config(struct phylink_pcs *pcs,
6138                                 unsigned int mode,
6139                                 phy_interface_t interface,
6140                                 const unsigned long *advertising,
6141                                 bool permit_pause_to_mac)
6142 {
6143         return 0;
6144 }
6145
6146 static const struct phylink_pcs_ops mvpp2_phylink_xlg_pcs_ops = {
6147         .pcs_get_state = mvpp2_xlg_pcs_get_state,
6148         .pcs_config = mvpp2_xlg_pcs_config,
6149 };
6150
6151 static void mvpp2_gmac_pcs_get_state(struct phylink_pcs *pcs,
6152                                      struct phylink_link_state *state)
6153 {
6154         struct mvpp2_port *port = mvpp2_pcs_to_port(pcs);
6155         u32 val;
6156
6157         val = readl(port->base + MVPP2_GMAC_STATUS0);
6158
6159         state->an_complete = !!(val & MVPP2_GMAC_STATUS0_AN_COMPLETE);
6160         state->link = !!(val & MVPP2_GMAC_STATUS0_LINK_UP);
6161         state->duplex = !!(val & MVPP2_GMAC_STATUS0_FULL_DUPLEX);
6162
6163         switch (port->phy_interface) {
6164         case PHY_INTERFACE_MODE_1000BASEX:
6165                 state->speed = SPEED_1000;
6166                 break;
6167         case PHY_INTERFACE_MODE_2500BASEX:
6168                 state->speed = SPEED_2500;
6169                 break;
6170         default:
6171                 if (val & MVPP2_GMAC_STATUS0_GMII_SPEED)
6172                         state->speed = SPEED_1000;
6173                 else if (val & MVPP2_GMAC_STATUS0_MII_SPEED)
6174                         state->speed = SPEED_100;
6175                 else
6176                         state->speed = SPEED_10;
6177         }
6178
6179         state->pause = 0;
6180         if (val & MVPP2_GMAC_STATUS0_RX_PAUSE)
6181                 state->pause |= MLO_PAUSE_RX;
6182         if (val & MVPP2_GMAC_STATUS0_TX_PAUSE)
6183                 state->pause |= MLO_PAUSE_TX;
6184 }
6185
6186 static int mvpp2_gmac_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
6187                                  phy_interface_t interface,
6188                                  const unsigned long *advertising,
6189                                  bool permit_pause_to_mac)
6190 {
6191         struct mvpp2_port *port = mvpp2_pcs_to_port(pcs);
6192         u32 mask, val, an, old_an, changed;
6193
6194         mask = MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS |
6195                MVPP2_GMAC_IN_BAND_AUTONEG |
6196                MVPP2_GMAC_AN_SPEED_EN |
6197                MVPP2_GMAC_FLOW_CTRL_AUTONEG |
6198                MVPP2_GMAC_AN_DUPLEX_EN;
6199
6200         if (phylink_autoneg_inband(mode)) {
6201                 mask |= MVPP2_GMAC_CONFIG_MII_SPEED |
6202                         MVPP2_GMAC_CONFIG_GMII_SPEED |
6203                         MVPP2_GMAC_CONFIG_FULL_DUPLEX;
6204                 val = MVPP2_GMAC_IN_BAND_AUTONEG;
6205
6206                 if (interface == PHY_INTERFACE_MODE_SGMII) {
6207                         /* SGMII mode receives the speed and duplex from PHY */
6208                         val |= MVPP2_GMAC_AN_SPEED_EN |
6209                                MVPP2_GMAC_AN_DUPLEX_EN;
6210                 } else {
6211                         /* 802.3z mode has fixed speed and duplex */
6212                         val |= MVPP2_GMAC_CONFIG_GMII_SPEED |
6213                                MVPP2_GMAC_CONFIG_FULL_DUPLEX;
6214
6215                         /* The FLOW_CTRL_AUTONEG bit selects either the hardware
6216                          * automatically or the bits in MVPP22_GMAC_CTRL_4_REG
6217                          * manually controls the GMAC pause modes.
6218                          */
6219                         if (permit_pause_to_mac)
6220                                 val |= MVPP2_GMAC_FLOW_CTRL_AUTONEG;
6221
6222                         /* Configure advertisement bits */
6223                         mask |= MVPP2_GMAC_FC_ADV_EN | MVPP2_GMAC_FC_ADV_ASM_EN;
6224                         if (phylink_test(advertising, Pause))
6225                                 val |= MVPP2_GMAC_FC_ADV_EN;
6226                         if (phylink_test(advertising, Asym_Pause))
6227                                 val |= MVPP2_GMAC_FC_ADV_ASM_EN;
6228                 }
6229         } else {
6230                 val = 0;
6231         }
6232
6233         old_an = an = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
6234         an = (an & ~mask) | val;
6235         changed = an ^ old_an;
6236         if (changed)
6237                 writel(an, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
6238
6239         /* We are only interested in the advertisement bits changing */
6240         return changed & (MVPP2_GMAC_FC_ADV_EN | MVPP2_GMAC_FC_ADV_ASM_EN);
6241 }
6242
6243 static void mvpp2_gmac_pcs_an_restart(struct phylink_pcs *pcs)
6244 {
6245         struct mvpp2_port *port = mvpp2_pcs_to_port(pcs);
6246         u32 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
6247
6248         writel(val | MVPP2_GMAC_IN_BAND_RESTART_AN,
6249                port->base + MVPP2_GMAC_AUTONEG_CONFIG);
6250         writel(val & ~MVPP2_GMAC_IN_BAND_RESTART_AN,
6251                port->base + MVPP2_GMAC_AUTONEG_CONFIG);
6252 }
6253
6254 static const struct phylink_pcs_ops mvpp2_phylink_gmac_pcs_ops = {
6255         .pcs_get_state = mvpp2_gmac_pcs_get_state,
6256         .pcs_config = mvpp2_gmac_pcs_config,
6257         .pcs_an_restart = mvpp2_gmac_pcs_an_restart,
6258 };
6259
6260 static void mvpp2_phylink_validate(struct phylink_config *config,
6261                                    unsigned long *supported,
6262                                    struct phylink_link_state *state)
6263 {
6264         struct mvpp2_port *port = mvpp2_phylink_to_port(config);
6265         __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
6266
6267         /* Invalid combinations */
6268         switch (state->interface) {
6269         case PHY_INTERFACE_MODE_10GBASER:
6270         case PHY_INTERFACE_MODE_XAUI:
6271                 if (!mvpp2_port_supports_xlg(port))
6272                         goto empty_set;
6273                 break;
6274         case PHY_INTERFACE_MODE_RGMII:
6275         case PHY_INTERFACE_MODE_RGMII_ID:
6276         case PHY_INTERFACE_MODE_RGMII_RXID:
6277         case PHY_INTERFACE_MODE_RGMII_TXID:
6278                 if (!mvpp2_port_supports_rgmii(port))
6279                         goto empty_set;
6280                 break;
6281         default:
6282                 break;
6283         }
6284
6285         phylink_set(mask, Autoneg);
6286         phylink_set_port_modes(mask);
6287
6288         if (port->priv->global_tx_fc) {
6289                 phylink_set(mask, Pause);
6290                 phylink_set(mask, Asym_Pause);
6291         }
6292
6293         switch (state->interface) {
6294         case PHY_INTERFACE_MODE_10GBASER:
6295         case PHY_INTERFACE_MODE_XAUI:
6296         case PHY_INTERFACE_MODE_NA:
6297                 if (mvpp2_port_supports_xlg(port)) {
6298                         phylink_set(mask, 10000baseT_Full);
6299                         phylink_set(mask, 10000baseCR_Full);
6300                         phylink_set(mask, 10000baseSR_Full);
6301                         phylink_set(mask, 10000baseLR_Full);
6302                         phylink_set(mask, 10000baseLRM_Full);
6303                         phylink_set(mask, 10000baseER_Full);
6304                         phylink_set(mask, 10000baseKR_Full);
6305                 }
6306                 if (state->interface != PHY_INTERFACE_MODE_NA)
6307                         break;
6308                 fallthrough;
6309         case PHY_INTERFACE_MODE_RGMII:
6310         case PHY_INTERFACE_MODE_RGMII_ID:
6311         case PHY_INTERFACE_MODE_RGMII_RXID:
6312         case PHY_INTERFACE_MODE_RGMII_TXID:
6313         case PHY_INTERFACE_MODE_SGMII:
6314                 phylink_set(mask, 10baseT_Half);
6315                 phylink_set(mask, 10baseT_Full);
6316                 phylink_set(mask, 100baseT_Half);
6317                 phylink_set(mask, 100baseT_Full);
6318                 phylink_set(mask, 1000baseT_Full);
6319                 phylink_set(mask, 1000baseX_Full);
6320                 if (state->interface != PHY_INTERFACE_MODE_NA)
6321                         break;
6322                 fallthrough;
6323         case PHY_INTERFACE_MODE_1000BASEX:
6324         case PHY_INTERFACE_MODE_2500BASEX:
6325                 if (port->comphy ||
6326                     state->interface != PHY_INTERFACE_MODE_2500BASEX) {
6327                         phylink_set(mask, 1000baseT_Full);
6328                         phylink_set(mask, 1000baseX_Full);
6329                 }
6330                 if (port->comphy ||
6331                     state->interface == PHY_INTERFACE_MODE_2500BASEX) {
6332                         phylink_set(mask, 2500baseT_Full);
6333                         phylink_set(mask, 2500baseX_Full);
6334                 }
6335                 break;
6336         default:
6337                 goto empty_set;
6338         }
6339
6340         bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
6341         bitmap_and(state->advertising, state->advertising, mask,
6342                    __ETHTOOL_LINK_MODE_MASK_NBITS);
6343
6344         phylink_helper_basex_speed(state);
6345         return;
6346
6347 empty_set:
6348         bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
6349 }
6350
6351 static void mvpp2_xlg_config(struct mvpp2_port *port, unsigned int mode,
6352                              const struct phylink_link_state *state)
6353 {
6354         u32 val;
6355
6356         mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG,
6357                      MVPP22_XLG_CTRL0_MAC_RESET_DIS,
6358                      MVPP22_XLG_CTRL0_MAC_RESET_DIS);
6359         mvpp2_modify(port->base + MVPP22_XLG_CTRL4_REG,
6360                      MVPP22_XLG_CTRL4_MACMODSELECT_GMAC |
6361                      MVPP22_XLG_CTRL4_EN_IDLE_CHECK |
6362                      MVPP22_XLG_CTRL4_FWD_FC | MVPP22_XLG_CTRL4_FWD_PFC,
6363                      MVPP22_XLG_CTRL4_FWD_FC | MVPP22_XLG_CTRL4_FWD_PFC);
6364
6365         /* Wait for reset to deassert */
6366         do {
6367                 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
6368         } while (!(val & MVPP22_XLG_CTRL0_MAC_RESET_DIS));
6369 }
6370
6371 static void mvpp2_gmac_config(struct mvpp2_port *port, unsigned int mode,
6372                               const struct phylink_link_state *state)
6373 {
6374         u32 old_ctrl0, ctrl0;
6375         u32 old_ctrl2, ctrl2;
6376         u32 old_ctrl4, ctrl4;
6377
6378         old_ctrl0 = ctrl0 = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
6379         old_ctrl2 = ctrl2 = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
6380         old_ctrl4 = ctrl4 = readl(port->base + MVPP22_GMAC_CTRL_4_REG);
6381
6382         ctrl0 &= ~MVPP2_GMAC_PORT_TYPE_MASK;
6383         ctrl2 &= ~(MVPP2_GMAC_INBAND_AN_MASK | MVPP2_GMAC_PCS_ENABLE_MASK | MVPP2_GMAC_FLOW_CTRL_MASK);
6384
6385         /* Configure port type */
6386         if (phy_interface_mode_is_8023z(state->interface)) {
6387                 ctrl2 |= MVPP2_GMAC_PCS_ENABLE_MASK;
6388                 ctrl4 &= ~MVPP22_CTRL4_EXT_PIN_GMII_SEL;
6389                 ctrl4 |= MVPP22_CTRL4_SYNC_BYPASS_DIS |
6390                          MVPP22_CTRL4_DP_CLK_SEL |
6391                          MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE;
6392         } else if (state->interface == PHY_INTERFACE_MODE_SGMII) {
6393                 ctrl2 |= MVPP2_GMAC_PCS_ENABLE_MASK | MVPP2_GMAC_INBAND_AN_MASK;
6394                 ctrl4 &= ~MVPP22_CTRL4_EXT_PIN_GMII_SEL;
6395                 ctrl4 |= MVPP22_CTRL4_SYNC_BYPASS_DIS |
6396                          MVPP22_CTRL4_DP_CLK_SEL |
6397                          MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE;
6398         } else if (phy_interface_mode_is_rgmii(state->interface)) {
6399                 ctrl4 &= ~MVPP22_CTRL4_DP_CLK_SEL;
6400                 ctrl4 |= MVPP22_CTRL4_EXT_PIN_GMII_SEL |
6401                          MVPP22_CTRL4_SYNC_BYPASS_DIS |
6402                          MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE;
6403         }
6404
6405         /* Configure negotiation style */
6406         if (!phylink_autoneg_inband(mode)) {
6407                 /* Phy or fixed speed - no in-band AN, nothing to do, leave the
6408                  * configured speed, duplex and flow control as-is.
6409                  */
6410         } else if (state->interface == PHY_INTERFACE_MODE_SGMII) {
6411                 /* SGMII in-band mode receives the speed and duplex from
6412                  * the PHY. Flow control information is not received. */
6413         } else if (phy_interface_mode_is_8023z(state->interface)) {
6414                 /* 1000BaseX and 2500BaseX ports cannot negotiate speed nor can
6415                  * they negotiate duplex: they are always operating with a fixed
6416                  * speed of 1000/2500Mbps in full duplex, so force 1000/2500
6417                  * speed and full duplex here.
6418                  */
6419                 ctrl0 |= MVPP2_GMAC_PORT_TYPE_MASK;
6420         }
6421
6422         if (old_ctrl0 != ctrl0)
6423                 writel(ctrl0, port->base + MVPP2_GMAC_CTRL_0_REG);
6424         if (old_ctrl2 != ctrl2)
6425                 writel(ctrl2, port->base + MVPP2_GMAC_CTRL_2_REG);
6426         if (old_ctrl4 != ctrl4)
6427                 writel(ctrl4, port->base + MVPP22_GMAC_CTRL_4_REG);
6428 }
6429
6430 static int mvpp2__mac_prepare(struct phylink_config *config, unsigned int mode,
6431                               phy_interface_t interface)
6432 {
6433         struct mvpp2_port *port = mvpp2_phylink_to_port(config);
6434
6435         /* Check for invalid configuration */
6436         if (mvpp2_is_xlg(interface) && port->gop_id != 0) {
6437                 netdev_err(port->dev, "Invalid mode on %s\n", port->dev->name);
6438                 return -EINVAL;
6439         }
6440
6441         if (port->phy_interface != interface ||
6442             phylink_autoneg_inband(mode)) {
6443                 /* Force the link down when changing the interface or if in
6444                  * in-band mode to ensure we do not change the configuration
6445                  * while the hardware is indicating link is up. We force both
6446                  * XLG and GMAC down to ensure that they're both in a known
6447                  * state.
6448                  */
6449                 mvpp2_modify(port->base + MVPP2_GMAC_AUTONEG_CONFIG,
6450                              MVPP2_GMAC_FORCE_LINK_PASS |
6451                              MVPP2_GMAC_FORCE_LINK_DOWN,
6452                              MVPP2_GMAC_FORCE_LINK_DOWN);
6453
6454                 if (mvpp2_port_supports_xlg(port))
6455                         mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG,
6456                                      MVPP22_XLG_CTRL0_FORCE_LINK_PASS |
6457                                      MVPP22_XLG_CTRL0_FORCE_LINK_DOWN,
6458                                      MVPP22_XLG_CTRL0_FORCE_LINK_DOWN);
6459         }
6460
6461         /* Make sure the port is disabled when reconfiguring the mode */
6462         mvpp2_port_disable(port);
6463
6464         if (port->phy_interface != interface) {
6465                 /* Place GMAC into reset */
6466                 mvpp2_modify(port->base + MVPP2_GMAC_CTRL_2_REG,
6467                              MVPP2_GMAC_PORT_RESET_MASK,
6468                              MVPP2_GMAC_PORT_RESET_MASK);
6469
6470                 if (port->priv->hw_version >= MVPP22) {
6471                         mvpp22_gop_mask_irq(port);
6472
6473                         phy_power_off(port->comphy);
6474                 }
6475         }
6476
6477         /* Select the appropriate PCS operations depending on the
6478          * configured interface mode. We will only switch to a mode
6479          * that the validate() checks have already passed.
6480          */
6481         if (mvpp2_is_xlg(interface))
6482                 port->phylink_pcs.ops = &mvpp2_phylink_xlg_pcs_ops;
6483         else
6484                 port->phylink_pcs.ops = &mvpp2_phylink_gmac_pcs_ops;
6485
6486         return 0;
6487 }
6488
6489 static int mvpp2_mac_prepare(struct phylink_config *config, unsigned int mode,
6490                              phy_interface_t interface)
6491 {
6492         struct mvpp2_port *port = mvpp2_phylink_to_port(config);
6493         int ret;
6494
6495         ret = mvpp2__mac_prepare(config, mode, interface);
6496         if (ret == 0)
6497                 phylink_set_pcs(port->phylink, &port->phylink_pcs);
6498
6499         return ret;
6500 }
6501
6502 static void mvpp2_mac_config(struct phylink_config *config, unsigned int mode,
6503                              const struct phylink_link_state *state)
6504 {
6505         struct mvpp2_port *port = mvpp2_phylink_to_port(config);
6506
6507         /* mac (re)configuration */
6508         if (mvpp2_is_xlg(state->interface))
6509                 mvpp2_xlg_config(port, mode, state);
6510         else if (phy_interface_mode_is_rgmii(state->interface) ||
6511                  phy_interface_mode_is_8023z(state->interface) ||
6512                  state->interface == PHY_INTERFACE_MODE_SGMII)
6513                 mvpp2_gmac_config(port, mode, state);
6514
6515         if (port->priv->hw_version == MVPP21 && port->flags & MVPP2_F_LOOPBACK)
6516                 mvpp2_port_loopback_set(port, state);
6517 }
6518
6519 static int mvpp2_mac_finish(struct phylink_config *config, unsigned int mode,
6520                             phy_interface_t interface)
6521 {
6522         struct mvpp2_port *port = mvpp2_phylink_to_port(config);
6523
6524         if (port->priv->hw_version >= MVPP22 &&
6525             port->phy_interface != interface) {
6526                 port->phy_interface = interface;
6527
6528                 /* Reconfigure the serdes lanes */
6529                 mvpp22_mode_reconfigure(port);
6530
6531                 /* Unmask interrupts */
6532                 mvpp22_gop_unmask_irq(port);
6533         }
6534
6535         if (!mvpp2_is_xlg(interface)) {
6536                 /* Release GMAC reset and wait */
6537                 mvpp2_modify(port->base + MVPP2_GMAC_CTRL_2_REG,
6538                              MVPP2_GMAC_PORT_RESET_MASK, 0);
6539
6540                 while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
6541                        MVPP2_GMAC_PORT_RESET_MASK)
6542                         continue;
6543         }
6544
6545         mvpp2_port_enable(port);
6546
6547         /* Allow the link to come up if in in-band mode, otherwise the
6548          * link is forced via mac_link_down()/mac_link_up()
6549          */
6550         if (phylink_autoneg_inband(mode)) {
6551                 if (mvpp2_is_xlg(interface))
6552                         mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG,
6553                                      MVPP22_XLG_CTRL0_FORCE_LINK_PASS |
6554                                      MVPP22_XLG_CTRL0_FORCE_LINK_DOWN, 0);
6555                 else
6556                         mvpp2_modify(port->base + MVPP2_GMAC_AUTONEG_CONFIG,
6557                                      MVPP2_GMAC_FORCE_LINK_PASS |
6558                                      MVPP2_GMAC_FORCE_LINK_DOWN, 0);
6559         }
6560
6561         return 0;
6562 }
6563
6564 static void mvpp2_mac_link_up(struct phylink_config *config,
6565                               struct phy_device *phy,
6566                               unsigned int mode, phy_interface_t interface,
6567                               int speed, int duplex,
6568                               bool tx_pause, bool rx_pause)
6569 {
6570         struct mvpp2_port *port = mvpp2_phylink_to_port(config);
6571         u32 val;
6572         int i;
6573
6574         if (mvpp2_is_xlg(interface)) {
6575                 if (!phylink_autoneg_inband(mode)) {
6576                         val = MVPP22_XLG_CTRL0_FORCE_LINK_PASS;
6577                         if (tx_pause)
6578                                 val |= MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN;
6579                         if (rx_pause)
6580                                 val |= MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN;
6581
6582                         mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG,
6583                                      MVPP22_XLG_CTRL0_FORCE_LINK_DOWN |
6584                                      MVPP22_XLG_CTRL0_FORCE_LINK_PASS |
6585                                      MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN |
6586                                      MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN, val);
6587                 }
6588         } else {
6589                 if (!phylink_autoneg_inband(mode)) {
6590                         val = MVPP2_GMAC_FORCE_LINK_PASS;
6591
6592                         if (speed == SPEED_1000 || speed == SPEED_2500)
6593                                 val |= MVPP2_GMAC_CONFIG_GMII_SPEED;
6594                         else if (speed == SPEED_100)
6595                                 val |= MVPP2_GMAC_CONFIG_MII_SPEED;
6596
6597                         if (duplex == DUPLEX_FULL)
6598                                 val |= MVPP2_GMAC_CONFIG_FULL_DUPLEX;
6599
6600                         mvpp2_modify(port->base + MVPP2_GMAC_AUTONEG_CONFIG,
6601                                      MVPP2_GMAC_FORCE_LINK_DOWN |
6602                                      MVPP2_GMAC_FORCE_LINK_PASS |
6603                                      MVPP2_GMAC_CONFIG_MII_SPEED |
6604                                      MVPP2_GMAC_CONFIG_GMII_SPEED |
6605                                      MVPP2_GMAC_CONFIG_FULL_DUPLEX, val);
6606                 }
6607
6608                 /* We can always update the flow control enable bits;
6609                  * these will only be effective if flow control AN
6610                  * (MVPP2_GMAC_FLOW_CTRL_AUTONEG) is disabled.
6611                  */
6612                 val = 0;
6613                 if (tx_pause)
6614                         val |= MVPP22_CTRL4_TX_FC_EN;
6615                 if (rx_pause)
6616                         val |= MVPP22_CTRL4_RX_FC_EN;
6617
6618                 mvpp2_modify(port->base + MVPP22_GMAC_CTRL_4_REG,
6619                              MVPP22_CTRL4_RX_FC_EN | MVPP22_CTRL4_TX_FC_EN,
6620                              val);
6621         }
6622
6623         if (port->priv->global_tx_fc) {
6624                 port->tx_fc = tx_pause;
6625                 if (tx_pause)
6626                         mvpp2_rxq_enable_fc(port);
6627                 else
6628                         mvpp2_rxq_disable_fc(port);
6629                 if (port->priv->percpu_pools) {
6630                         for (i = 0; i < port->nrxqs; i++)
6631                                 mvpp2_bm_pool_update_fc(port, &port->priv->bm_pools[i], tx_pause);
6632                 } else {
6633                         mvpp2_bm_pool_update_fc(port, port->pool_long, tx_pause);
6634                         mvpp2_bm_pool_update_fc(port, port->pool_short, tx_pause);
6635                 }
6636                 if (port->priv->hw_version == MVPP23)
6637                         mvpp23_rx_fifo_fc_en(port->priv, port->id, tx_pause);
6638         }
6639
6640         mvpp2_port_enable(port);
6641
6642         mvpp2_egress_enable(port);
6643         mvpp2_ingress_enable(port);
6644         netif_tx_wake_all_queues(port->dev);
6645 }
6646
6647 static void mvpp2_mac_link_down(struct phylink_config *config,
6648                                 unsigned int mode, phy_interface_t interface)
6649 {
6650         struct mvpp2_port *port = mvpp2_phylink_to_port(config);
6651         u32 val;
6652
6653         if (!phylink_autoneg_inband(mode)) {
6654                 if (mvpp2_is_xlg(interface)) {
6655                         val = readl(port->base + MVPP22_XLG_CTRL0_REG);
6656                         val &= ~MVPP22_XLG_CTRL0_FORCE_LINK_PASS;
6657                         val |= MVPP22_XLG_CTRL0_FORCE_LINK_DOWN;
6658                         writel(val, port->base + MVPP22_XLG_CTRL0_REG);
6659                 } else {
6660                         val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
6661                         val &= ~MVPP2_GMAC_FORCE_LINK_PASS;
6662                         val |= MVPP2_GMAC_FORCE_LINK_DOWN;
6663                         writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
6664                 }
6665         }
6666
6667         netif_tx_stop_all_queues(port->dev);
6668         mvpp2_egress_disable(port);
6669         mvpp2_ingress_disable(port);
6670
6671         mvpp2_port_disable(port);
6672 }
6673
6674 static const struct phylink_mac_ops mvpp2_phylink_ops = {
6675         .validate = mvpp2_phylink_validate,
6676         .mac_prepare = mvpp2_mac_prepare,
6677         .mac_config = mvpp2_mac_config,
6678         .mac_finish = mvpp2_mac_finish,
6679         .mac_link_up = mvpp2_mac_link_up,
6680         .mac_link_down = mvpp2_mac_link_down,
6681 };
6682
6683 /* Work-around for ACPI */
6684 static void mvpp2_acpi_start(struct mvpp2_port *port)
6685 {
6686         /* Phylink isn't used as of now for ACPI, so the MAC has to be
6687          * configured manually when the interface is started. This will
6688          * be removed as soon as the phylink ACPI support lands in.
6689          */
6690         struct phylink_link_state state = {
6691                 .interface = port->phy_interface,
6692         };
6693         mvpp2__mac_prepare(&port->phylink_config, MLO_AN_INBAND,
6694                            port->phy_interface);
6695         mvpp2_mac_config(&port->phylink_config, MLO_AN_INBAND, &state);
6696         port->phylink_pcs.ops->pcs_config(&port->phylink_pcs, MLO_AN_INBAND,
6697                                           port->phy_interface,
6698                                           state.advertising, false);
6699         mvpp2_mac_finish(&port->phylink_config, MLO_AN_INBAND,
6700                          port->phy_interface);
6701         mvpp2_mac_link_up(&port->phylink_config, NULL,
6702                           MLO_AN_INBAND, port->phy_interface,
6703                           SPEED_UNKNOWN, DUPLEX_UNKNOWN, false, false);
6704 }
6705
6706 /* Ports initialization */
6707 static int mvpp2_port_probe(struct platform_device *pdev,
6708                             struct fwnode_handle *port_fwnode,
6709                             struct mvpp2 *priv)
6710 {
6711         struct phy *comphy = NULL;
6712         struct mvpp2_port *port;
6713         struct mvpp2_port_pcpu *port_pcpu;
6714         struct device_node *port_node = to_of_node(port_fwnode);
6715         netdev_features_t features;
6716         struct net_device *dev;
6717         struct phylink *phylink;
6718         char *mac_from = "";
6719         unsigned int ntxqs, nrxqs, thread;
6720         unsigned long flags = 0;
6721         bool has_tx_irqs;
6722         u32 id;
6723         int phy_mode;
6724         int err, i;
6725
6726         has_tx_irqs = mvpp2_port_has_irqs(priv, port_node, &flags);
6727         if (!has_tx_irqs && queue_mode == MVPP2_QDIST_MULTI_MODE) {
6728                 dev_err(&pdev->dev,
6729                         "not enough IRQs to support multi queue mode\n");
6730                 return -EINVAL;
6731         }
6732
6733         ntxqs = MVPP2_MAX_TXQ;
6734         nrxqs = mvpp2_get_nrxqs(priv);
6735
6736         dev = alloc_etherdev_mqs(sizeof(*port), ntxqs, nrxqs);
6737         if (!dev)
6738                 return -ENOMEM;
6739
6740         phy_mode = fwnode_get_phy_mode(port_fwnode);
6741         if (phy_mode < 0) {
6742                 dev_err(&pdev->dev, "incorrect phy mode\n");
6743                 err = phy_mode;
6744                 goto err_free_netdev;
6745         }
6746
6747         /*
6748          * Rewrite 10GBASE-KR to 10GBASE-R for compatibility with existing DT.
6749          * Existing usage of 10GBASE-KR is not correct; no backplane
6750          * negotiation is done, and this driver does not actually support
6751          * 10GBASE-KR.
6752          */
6753         if (phy_mode == PHY_INTERFACE_MODE_10GKR)
6754                 phy_mode = PHY_INTERFACE_MODE_10GBASER;
6755
6756         if (port_node) {
6757                 comphy = devm_of_phy_get(&pdev->dev, port_node, NULL);
6758                 if (IS_ERR(comphy)) {
6759                         if (PTR_ERR(comphy) == -EPROBE_DEFER) {
6760                                 err = -EPROBE_DEFER;
6761                                 goto err_free_netdev;
6762                         }
6763                         comphy = NULL;
6764                 }
6765         }
6766
6767         if (fwnode_property_read_u32(port_fwnode, "port-id", &id)) {
6768                 err = -EINVAL;
6769                 dev_err(&pdev->dev, "missing port-id value\n");
6770                 goto err_free_netdev;
6771         }
6772
6773         dev->tx_queue_len = MVPP2_MAX_TXD_MAX;
6774         dev->watchdog_timeo = 5 * HZ;
6775         dev->netdev_ops = &mvpp2_netdev_ops;
6776         dev->ethtool_ops = &mvpp2_eth_tool_ops;
6777
6778         port = netdev_priv(dev);
6779         port->dev = dev;
6780         port->fwnode = port_fwnode;
6781         port->has_phy = !!of_find_property(port_node, "phy", NULL);
6782         port->ntxqs = ntxqs;
6783         port->nrxqs = nrxqs;
6784         port->priv = priv;
6785         port->has_tx_irqs = has_tx_irqs;
6786         port->flags = flags;
6787
6788         err = mvpp2_queue_vectors_init(port, port_node);
6789         if (err)
6790                 goto err_free_netdev;
6791
6792         if (port_node)
6793                 port->port_irq = of_irq_get_byname(port_node, "link");
6794         else
6795                 port->port_irq = fwnode_irq_get(port_fwnode, port->nqvecs + 1);
6796         if (port->port_irq == -EPROBE_DEFER) {
6797                 err = -EPROBE_DEFER;
6798                 goto err_deinit_qvecs;
6799         }
6800         if (port->port_irq <= 0)
6801                 /* the link irq is optional */
6802                 port->port_irq = 0;
6803
6804         if (fwnode_property_read_bool(port_fwnode, "marvell,loopback"))
6805                 port->flags |= MVPP2_F_LOOPBACK;
6806
6807         port->id = id;
6808         if (priv->hw_version == MVPP21)
6809                 port->first_rxq = port->id * port->nrxqs;
6810         else
6811                 port->first_rxq = port->id * priv->max_port_rxqs;
6812
6813         port->of_node = port_node;
6814         port->phy_interface = phy_mode;
6815         port->comphy = comphy;
6816
6817         if (priv->hw_version == MVPP21) {
6818                 port->base = devm_platform_ioremap_resource(pdev, 2 + id);
6819                 if (IS_ERR(port->base)) {
6820                         err = PTR_ERR(port->base);
6821                         goto err_free_irq;
6822                 }
6823
6824                 port->stats_base = port->priv->lms_base +
6825                                    MVPP21_MIB_COUNTERS_OFFSET +
6826                                    port->gop_id * MVPP21_MIB_COUNTERS_PORT_SZ;
6827         } else {
6828                 if (fwnode_property_read_u32(port_fwnode, "gop-port-id",
6829                                              &port->gop_id)) {
6830                         err = -EINVAL;
6831                         dev_err(&pdev->dev, "missing gop-port-id value\n");
6832                         goto err_deinit_qvecs;
6833                 }
6834
6835                 port->base = priv->iface_base + MVPP22_GMAC_BASE(port->gop_id);
6836                 port->stats_base = port->priv->iface_base +
6837                                    MVPP22_MIB_COUNTERS_OFFSET +
6838                                    port->gop_id * MVPP22_MIB_COUNTERS_PORT_SZ;
6839
6840                 /* We may want a property to describe whether we should use
6841                  * MAC hardware timestamping.
6842                  */
6843                 if (priv->tai)
6844                         port->hwtstamp = true;
6845         }
6846
6847         /* Alloc per-cpu and ethtool stats */
6848         port->stats = netdev_alloc_pcpu_stats(struct mvpp2_pcpu_stats);
6849         if (!port->stats) {
6850                 err = -ENOMEM;
6851                 goto err_free_irq;
6852         }
6853
6854         port->ethtool_stats = devm_kcalloc(&pdev->dev,
6855                                            MVPP2_N_ETHTOOL_STATS(ntxqs, nrxqs),
6856                                            sizeof(u64), GFP_KERNEL);
6857         if (!port->ethtool_stats) {
6858                 err = -ENOMEM;
6859                 goto err_free_stats;
6860         }
6861
6862         mutex_init(&port->gather_stats_lock);
6863         INIT_DELAYED_WORK(&port->stats_work, mvpp2_gather_hw_statistics);
6864
6865         mvpp2_port_copy_mac_addr(dev, priv, port_fwnode, &mac_from);
6866
6867         port->tx_ring_size = MVPP2_MAX_TXD_DFLT;
6868         port->rx_ring_size = MVPP2_MAX_RXD_DFLT;
6869         SET_NETDEV_DEV(dev, &pdev->dev);
6870
6871         err = mvpp2_port_init(port);
6872         if (err < 0) {
6873                 dev_err(&pdev->dev, "failed to init port %d\n", id);
6874                 goto err_free_stats;
6875         }
6876
6877         mvpp2_port_periodic_xon_disable(port);
6878
6879         mvpp2_mac_reset_assert(port);
6880         mvpp22_pcs_reset_assert(port);
6881
6882         port->pcpu = alloc_percpu(struct mvpp2_port_pcpu);
6883         if (!port->pcpu) {
6884                 err = -ENOMEM;
6885                 goto err_free_txq_pcpu;
6886         }
6887
6888         if (!port->has_tx_irqs) {
6889                 for (thread = 0; thread < priv->nthreads; thread++) {
6890                         port_pcpu = per_cpu_ptr(port->pcpu, thread);
6891
6892                         hrtimer_init(&port_pcpu->tx_done_timer, CLOCK_MONOTONIC,
6893                                      HRTIMER_MODE_REL_PINNED_SOFT);
6894                         port_pcpu->tx_done_timer.function = mvpp2_hr_timer_cb;
6895                         port_pcpu->timer_scheduled = false;
6896                         port_pcpu->dev = dev;
6897                 }
6898         }
6899
6900         features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
6901                    NETIF_F_TSO;
6902         dev->features = features | NETIF_F_RXCSUM;
6903         dev->hw_features |= features | NETIF_F_RXCSUM | NETIF_F_GRO |
6904                             NETIF_F_HW_VLAN_CTAG_FILTER;
6905
6906         if (mvpp22_rss_is_supported(port)) {
6907                 dev->hw_features |= NETIF_F_RXHASH;
6908                 dev->features |= NETIF_F_NTUPLE;
6909         }
6910
6911         if (!port->priv->percpu_pools)
6912                 mvpp2_set_hw_csum(port, port->pool_long->id);
6913
6914         dev->vlan_features |= features;
6915         dev->gso_max_segs = MVPP2_MAX_TSO_SEGS;
6916         dev->priv_flags |= IFF_UNICAST_FLT;
6917
6918         /* MTU range: 68 - 9704 */
6919         dev->min_mtu = ETH_MIN_MTU;
6920         /* 9704 == 9728 - 20 and rounding to 8 */
6921         dev->max_mtu = MVPP2_BM_JUMBO_PKT_SIZE;
6922         dev->dev.of_node = port_node;
6923
6924         /* Phylink isn't used w/ ACPI as of now */
6925         if (port_node) {
6926                 port->phylink_config.dev = &dev->dev;
6927                 port->phylink_config.type = PHYLINK_NETDEV;
6928
6929                 phylink = phylink_create(&port->phylink_config, port_fwnode,
6930                                          phy_mode, &mvpp2_phylink_ops);
6931                 if (IS_ERR(phylink)) {
6932                         err = PTR_ERR(phylink);
6933                         goto err_free_port_pcpu;
6934                 }
6935                 port->phylink = phylink;
6936         } else {
6937                 port->phylink = NULL;
6938         }
6939
6940         /* Cycle the comphy to power it down, saving 270mW per port -
6941          * don't worry about an error powering it up. When the comphy
6942          * driver does this, we can remove this code.
6943          */
6944         if (port->comphy) {
6945                 err = mvpp22_comphy_init(port);
6946                 if (err == 0)
6947                         phy_power_off(port->comphy);
6948         }
6949
6950         err = register_netdev(dev);
6951         if (err < 0) {
6952                 dev_err(&pdev->dev, "failed to register netdev\n");
6953                 goto err_phylink;
6954         }
6955         netdev_info(dev, "Using %s mac address %pM\n", mac_from, dev->dev_addr);
6956
6957         priv->port_list[priv->port_count++] = port;
6958
6959         return 0;
6960
6961 err_phylink:
6962         if (port->phylink)
6963                 phylink_destroy(port->phylink);
6964 err_free_port_pcpu:
6965         free_percpu(port->pcpu);
6966 err_free_txq_pcpu:
6967         for (i = 0; i < port->ntxqs; i++)
6968                 free_percpu(port->txqs[i]->pcpu);
6969 err_free_stats:
6970         free_percpu(port->stats);
6971 err_free_irq:
6972         if (port->port_irq)
6973                 irq_dispose_mapping(port->port_irq);
6974 err_deinit_qvecs:
6975         mvpp2_queue_vectors_deinit(port);
6976 err_free_netdev:
6977         free_netdev(dev);
6978         return err;
6979 }
6980
6981 /* Ports removal routine */
6982 static void mvpp2_port_remove(struct mvpp2_port *port)
6983 {
6984         int i;
6985
6986         unregister_netdev(port->dev);
6987         if (port->phylink)
6988                 phylink_destroy(port->phylink);
6989         free_percpu(port->pcpu);
6990         free_percpu(port->stats);
6991         for (i = 0; i < port->ntxqs; i++)
6992                 free_percpu(port->txqs[i]->pcpu);
6993         mvpp2_queue_vectors_deinit(port);
6994         if (port->port_irq)
6995                 irq_dispose_mapping(port->port_irq);
6996         free_netdev(port->dev);
6997 }
6998
6999 /* Initialize decoding windows */
7000 static void mvpp2_conf_mbus_windows(const struct mbus_dram_target_info *dram,
7001                                     struct mvpp2 *priv)
7002 {
7003         u32 win_enable;
7004         int i;
7005
7006         for (i = 0; i < 6; i++) {
7007                 mvpp2_write(priv, MVPP2_WIN_BASE(i), 0);
7008                 mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0);
7009
7010                 if (i < 4)
7011                         mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0);
7012         }
7013
7014         win_enable = 0;
7015
7016         for (i = 0; i < dram->num_cs; i++) {
7017                 const struct mbus_dram_window *cs = dram->cs + i;
7018
7019                 mvpp2_write(priv, MVPP2_WIN_BASE(i),
7020                             (cs->base & 0xffff0000) | (cs->mbus_attr << 8) |
7021                             dram->mbus_dram_target_id);
7022
7023                 mvpp2_write(priv, MVPP2_WIN_SIZE(i),
7024                             (cs->size - 1) & 0xffff0000);
7025
7026                 win_enable |= (1 << i);
7027         }
7028
7029         mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable);
7030 }
7031
7032 /* Initialize Rx FIFO's */
7033 static void mvpp2_rx_fifo_init(struct mvpp2 *priv)
7034 {
7035         int port;
7036
7037         for (port = 0; port < MVPP2_MAX_PORTS; port++) {
7038                 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
7039                             MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB);
7040                 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
7041                             MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB);
7042         }
7043
7044         mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
7045                     MVPP2_RX_FIFO_PORT_MIN_PKT);
7046         mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
7047 }
7048
7049 static void mvpp22_rx_fifo_set_hw(struct mvpp2 *priv, int port, int data_size)
7050 {
7051         int attr_size = MVPP2_RX_FIFO_PORT_ATTR_SIZE(data_size);
7052
7053         mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port), data_size);
7054         mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port), attr_size);
7055 }
7056
7057 /* Initialize TX FIFO's: the total FIFO size is 48kB on PPv2.2 and PPv2.3.
7058  * 4kB fixed space must be assigned for the loopback port.
7059  * Redistribute remaining avialable 44kB space among all active ports.
7060  * Guarantee minimum 32kB for 10G port and 8kB for port 1, capable of 2.5G
7061  * SGMII link.
7062  */
7063 static void mvpp22_rx_fifo_init(struct mvpp2 *priv)
7064 {
7065         int remaining_ports_count;
7066         unsigned long port_map;
7067         int size_remainder;
7068         int port, size;
7069
7070         /* The loopback requires fixed 4kB of the FIFO space assignment. */
7071         mvpp22_rx_fifo_set_hw(priv, MVPP2_LOOPBACK_PORT_INDEX,
7072                               MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB);
7073         port_map = priv->port_map & ~BIT(MVPP2_LOOPBACK_PORT_INDEX);
7074
7075         /* Set RX FIFO size to 0 for inactive ports. */
7076         for_each_clear_bit(port, &port_map, MVPP2_LOOPBACK_PORT_INDEX)
7077                 mvpp22_rx_fifo_set_hw(priv, port, 0);
7078
7079         /* Assign remaining RX FIFO space among all active ports. */
7080         size_remainder = MVPP2_RX_FIFO_PORT_DATA_SIZE_44KB;
7081         remaining_ports_count = hweight_long(port_map);
7082
7083         for_each_set_bit(port, &port_map, MVPP2_LOOPBACK_PORT_INDEX) {
7084                 if (remaining_ports_count == 1)
7085                         size = size_remainder;
7086                 else if (port == 0)
7087                         size = max(size_remainder / remaining_ports_count,
7088                                    MVPP2_RX_FIFO_PORT_DATA_SIZE_32KB);
7089                 else if (port == 1)
7090                         size = max(size_remainder / remaining_ports_count,
7091                                    MVPP2_RX_FIFO_PORT_DATA_SIZE_8KB);
7092                 else
7093                         size = size_remainder / remaining_ports_count;
7094
7095                 size_remainder -= size;
7096                 remaining_ports_count--;
7097
7098                 mvpp22_rx_fifo_set_hw(priv, port, size);
7099         }
7100
7101         mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
7102                     MVPP2_RX_FIFO_PORT_MIN_PKT);
7103         mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
7104 }
7105
7106 /* Configure Rx FIFO Flow control thresholds */
7107 static void mvpp23_rx_fifo_fc_set_tresh(struct mvpp2 *priv)
7108 {
7109         int port, val;
7110
7111         /* Port 0: maximum speed -10Gb/s port
7112          *         required by spec RX FIFO threshold 9KB
7113          * Port 1: maximum speed -5Gb/s port
7114          *         required by spec RX FIFO threshold 4KB
7115          * Port 2: maximum speed -1Gb/s port
7116          *         required by spec RX FIFO threshold 2KB
7117          */
7118
7119         /* Without loopback port */
7120         for (port = 0; port < (MVPP2_MAX_PORTS - 1); port++) {
7121                 if (port == 0) {
7122                         val = (MVPP23_PORT0_FIFO_TRSH / MVPP2_RX_FC_TRSH_UNIT)
7123                                 << MVPP2_RX_FC_TRSH_OFFS;
7124                         val &= MVPP2_RX_FC_TRSH_MASK;
7125                         mvpp2_write(priv, MVPP2_RX_FC_REG(port), val);
7126                 } else if (port == 1) {
7127                         val = (MVPP23_PORT1_FIFO_TRSH / MVPP2_RX_FC_TRSH_UNIT)
7128                                 << MVPP2_RX_FC_TRSH_OFFS;
7129                         val &= MVPP2_RX_FC_TRSH_MASK;
7130                         mvpp2_write(priv, MVPP2_RX_FC_REG(port), val);
7131                 } else {
7132                         val = (MVPP23_PORT2_FIFO_TRSH / MVPP2_RX_FC_TRSH_UNIT)
7133                                 << MVPP2_RX_FC_TRSH_OFFS;
7134                         val &= MVPP2_RX_FC_TRSH_MASK;
7135                         mvpp2_write(priv, MVPP2_RX_FC_REG(port), val);
7136                 }
7137         }
7138 }
7139
7140 /* Configure Rx FIFO Flow control thresholds */
7141 void mvpp23_rx_fifo_fc_en(struct mvpp2 *priv, int port, bool en)
7142 {
7143         int val;
7144
7145         val = mvpp2_read(priv, MVPP2_RX_FC_REG(port));
7146
7147         if (en)
7148                 val |= MVPP2_RX_FC_EN;
7149         else
7150                 val &= ~MVPP2_RX_FC_EN;
7151
7152         mvpp2_write(priv, MVPP2_RX_FC_REG(port), val);
7153 }
7154
7155 static void mvpp22_tx_fifo_set_hw(struct mvpp2 *priv, int port, int size)
7156 {
7157         int threshold = MVPP2_TX_FIFO_THRESHOLD(size);
7158
7159         mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), size);
7160         mvpp2_write(priv, MVPP22_TX_FIFO_THRESH_REG(port), threshold);
7161 }
7162
7163 /* Initialize TX FIFO's: the total FIFO size is 19kB on PPv2.2 and PPv2.3.
7164  * 1kB fixed space must be assigned for the loopback port.
7165  * Redistribute remaining avialable 18kB space among all active ports.
7166  * The 10G interface should use 10kB (which is maximum possible size
7167  * per single port).
7168  */
7169 static void mvpp22_tx_fifo_init(struct mvpp2 *priv)
7170 {
7171         int remaining_ports_count;
7172         unsigned long port_map;
7173         int size_remainder;
7174         int port, size;
7175
7176         /* The loopback requires fixed 1kB of the FIFO space assignment. */
7177         mvpp22_tx_fifo_set_hw(priv, MVPP2_LOOPBACK_PORT_INDEX,
7178                               MVPP22_TX_FIFO_DATA_SIZE_1KB);
7179         port_map = priv->port_map & ~BIT(MVPP2_LOOPBACK_PORT_INDEX);
7180
7181         /* Set TX FIFO size to 0 for inactive ports. */
7182         for_each_clear_bit(port, &port_map, MVPP2_LOOPBACK_PORT_INDEX)
7183                 mvpp22_tx_fifo_set_hw(priv, port, 0);
7184
7185         /* Assign remaining TX FIFO space among all active ports. */
7186         size_remainder = MVPP22_TX_FIFO_DATA_SIZE_18KB;
7187         remaining_ports_count = hweight_long(port_map);
7188
7189         for_each_set_bit(port, &port_map, MVPP2_LOOPBACK_PORT_INDEX) {
7190                 if (remaining_ports_count == 1)
7191                         size = min(size_remainder,
7192                                    MVPP22_TX_FIFO_DATA_SIZE_10KB);
7193                 else if (port == 0)
7194                         size = MVPP22_TX_FIFO_DATA_SIZE_10KB;
7195                 else
7196                         size = size_remainder / remaining_ports_count;
7197
7198                 size_remainder -= size;
7199                 remaining_ports_count--;
7200
7201                 mvpp22_tx_fifo_set_hw(priv, port, size);
7202         }
7203 }
7204
7205 static void mvpp2_axi_init(struct mvpp2 *priv)
7206 {
7207         u32 val, rdval, wrval;
7208
7209         mvpp2_write(priv, MVPP22_BM_ADDR_HIGH_RLS_REG, 0x0);
7210
7211         /* AXI Bridge Configuration */
7212
7213         rdval = MVPP22_AXI_CODE_CACHE_RD_CACHE
7214                 << MVPP22_AXI_ATTR_CACHE_OFFS;
7215         rdval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
7216                 << MVPP22_AXI_ATTR_DOMAIN_OFFS;
7217
7218         wrval = MVPP22_AXI_CODE_CACHE_WR_CACHE
7219                 << MVPP22_AXI_ATTR_CACHE_OFFS;
7220         wrval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
7221                 << MVPP22_AXI_ATTR_DOMAIN_OFFS;
7222
7223         /* BM */
7224         mvpp2_write(priv, MVPP22_AXI_BM_WR_ATTR_REG, wrval);
7225         mvpp2_write(priv, MVPP22_AXI_BM_RD_ATTR_REG, rdval);
7226
7227         /* Descriptors */
7228         mvpp2_write(priv, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, rdval);
7229         mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, wrval);
7230         mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, rdval);
7231         mvpp2_write(priv, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, wrval);
7232
7233         /* Buffer Data */
7234         mvpp2_write(priv, MVPP22_AXI_TX_DATA_RD_ATTR_REG, rdval);
7235         mvpp2_write(priv, MVPP22_AXI_RX_DATA_WR_ATTR_REG, wrval);
7236
7237         val = MVPP22_AXI_CODE_CACHE_NON_CACHE
7238                 << MVPP22_AXI_CODE_CACHE_OFFS;
7239         val |= MVPP22_AXI_CODE_DOMAIN_SYSTEM
7240                 << MVPP22_AXI_CODE_DOMAIN_OFFS;
7241         mvpp2_write(priv, MVPP22_AXI_RD_NORMAL_CODE_REG, val);
7242         mvpp2_write(priv, MVPP22_AXI_WR_NORMAL_CODE_REG, val);
7243
7244         val = MVPP22_AXI_CODE_CACHE_RD_CACHE
7245                 << MVPP22_AXI_CODE_CACHE_OFFS;
7246         val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
7247                 << MVPP22_AXI_CODE_DOMAIN_OFFS;
7248
7249         mvpp2_write(priv, MVPP22_AXI_RD_SNOOP_CODE_REG, val);
7250
7251         val = MVPP22_AXI_CODE_CACHE_WR_CACHE
7252                 << MVPP22_AXI_CODE_CACHE_OFFS;
7253         val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
7254                 << MVPP22_AXI_CODE_DOMAIN_OFFS;
7255
7256         mvpp2_write(priv, MVPP22_AXI_WR_SNOOP_CODE_REG, val);
7257 }
7258
7259 /* Initialize network controller common part HW */
7260 static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv)
7261 {
7262         const struct mbus_dram_target_info *dram_target_info;
7263         int err, i;
7264         u32 val;
7265
7266         /* MBUS windows configuration */
7267         dram_target_info = mv_mbus_dram_info();
7268         if (dram_target_info)
7269                 mvpp2_conf_mbus_windows(dram_target_info, priv);
7270
7271         if (priv->hw_version >= MVPP22)
7272                 mvpp2_axi_init(priv);
7273
7274         /* Disable HW PHY polling */
7275         if (priv->hw_version == MVPP21) {
7276                 val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
7277                 val |= MVPP2_PHY_AN_STOP_SMI0_MASK;
7278                 writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
7279         } else {
7280                 val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
7281                 val &= ~MVPP22_SMI_POLLING_EN;
7282                 writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
7283         }
7284
7285         /* Allocate and initialize aggregated TXQs */
7286         priv->aggr_txqs = devm_kcalloc(&pdev->dev, MVPP2_MAX_THREADS,
7287                                        sizeof(*priv->aggr_txqs),
7288                                        GFP_KERNEL);
7289         if (!priv->aggr_txqs)
7290                 return -ENOMEM;
7291
7292         for (i = 0; i < MVPP2_MAX_THREADS; i++) {
7293                 priv->aggr_txqs[i].id = i;
7294                 priv->aggr_txqs[i].size = MVPP2_AGGR_TXQ_SIZE;
7295                 err = mvpp2_aggr_txq_init(pdev, &priv->aggr_txqs[i], i, priv);
7296                 if (err < 0)
7297                         return err;
7298         }
7299
7300         /* Fifo Init */
7301         if (priv->hw_version == MVPP21) {
7302                 mvpp2_rx_fifo_init(priv);
7303         } else {
7304                 mvpp22_rx_fifo_init(priv);
7305                 mvpp22_tx_fifo_init(priv);
7306                 if (priv->hw_version == MVPP23)
7307                         mvpp23_rx_fifo_fc_set_tresh(priv);
7308         }
7309
7310         if (priv->hw_version == MVPP21)
7311                 writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT,
7312                        priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG);
7313
7314         /* Allow cache snoop when transmiting packets */
7315         mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1);
7316
7317         /* Buffer Manager initialization */
7318         err = mvpp2_bm_init(&pdev->dev, priv);
7319         if (err < 0)
7320                 return err;
7321
7322         /* Parser default initialization */
7323         err = mvpp2_prs_default_init(pdev, priv);
7324         if (err < 0)
7325                 return err;
7326
7327         /* Classifier default initialization */
7328         mvpp2_cls_init(priv);
7329
7330         return 0;
7331 }
7332
7333 static int mvpp2_get_sram(struct platform_device *pdev,
7334                           struct mvpp2 *priv)
7335 {
7336         struct resource *res;
7337
7338         res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
7339         if (!res) {
7340                 if (has_acpi_companion(&pdev->dev))
7341                         dev_warn(&pdev->dev, "ACPI is too old, Flow control not supported\n");
7342                 else
7343                         dev_warn(&pdev->dev, "DT is too old, Flow control not supported\n");
7344                 return 0;
7345         }
7346
7347         priv->cm3_base = devm_ioremap_resource(&pdev->dev, res);
7348
7349         return PTR_ERR_OR_ZERO(priv->cm3_base);
7350 }
7351
7352 static int mvpp2_probe(struct platform_device *pdev)
7353 {
7354         struct fwnode_handle *fwnode = pdev->dev.fwnode;
7355         struct fwnode_handle *port_fwnode;
7356         struct mvpp2 *priv;
7357         struct resource *res;
7358         void __iomem *base;
7359         int i, shared;
7360         int err;
7361
7362         priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
7363         if (!priv)
7364                 return -ENOMEM;
7365
7366         priv->hw_version = (unsigned long)device_get_match_data(&pdev->dev);
7367
7368         /* multi queue mode isn't supported on PPV2.1, fallback to single
7369          * mode
7370          */
7371         if (priv->hw_version == MVPP21)
7372                 queue_mode = MVPP2_QDIST_SINGLE_MODE;
7373
7374         base = devm_platform_ioremap_resource(pdev, 0);
7375         if (IS_ERR(base))
7376                 return PTR_ERR(base);
7377
7378         if (priv->hw_version == MVPP21) {
7379                 priv->lms_base = devm_platform_ioremap_resource(pdev, 1);
7380                 if (IS_ERR(priv->lms_base))
7381                         return PTR_ERR(priv->lms_base);
7382         } else {
7383                 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
7384                 if (!res) {
7385                         dev_err(&pdev->dev, "Invalid resource\n");
7386                         return -EINVAL;
7387                 }
7388                 if (has_acpi_companion(&pdev->dev)) {
7389                         /* In case the MDIO memory region is declared in
7390                          * the ACPI, it can already appear as 'in-use'
7391                          * in the OS. Because it is overlapped by second
7392                          * region of the network controller, make
7393                          * sure it is released, before requesting it again.
7394                          * The care is taken by mvpp2 driver to avoid
7395                          * concurrent access to this memory region.
7396                          */
7397                         release_resource(res);
7398                 }
7399                 priv->iface_base = devm_ioremap_resource(&pdev->dev, res);
7400                 if (IS_ERR(priv->iface_base))
7401                         return PTR_ERR(priv->iface_base);
7402
7403                 /* Map CM3 SRAM */
7404                 err = mvpp2_get_sram(pdev, priv);
7405                 if (err)
7406                         dev_warn(&pdev->dev, "Fail to alloc CM3 SRAM\n");
7407
7408                 /* Enable global Flow Control only if handler to SRAM not NULL */
7409                 if (priv->cm3_base)
7410                         priv->global_tx_fc = true;
7411         }
7412
7413         if (priv->hw_version >= MVPP22 && dev_of_node(&pdev->dev)) {
7414                 priv->sysctrl_base =
7415                         syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
7416                                                         "marvell,system-controller");
7417                 if (IS_ERR(priv->sysctrl_base))
7418                         /* The system controller regmap is optional for dt
7419                          * compatibility reasons. When not provided, the
7420                          * configuration of the GoP relies on the
7421                          * firmware/bootloader.
7422                          */
7423                         priv->sysctrl_base = NULL;
7424         }
7425
7426         if (priv->hw_version >= MVPP22 &&
7427             mvpp2_get_nrxqs(priv) * 2 <= MVPP2_BM_MAX_POOLS)
7428                 priv->percpu_pools = 1;
7429
7430         mvpp2_setup_bm_pool();
7431
7432
7433         priv->nthreads = min_t(unsigned int, num_present_cpus(),
7434                                MVPP2_MAX_THREADS);
7435
7436         shared = num_present_cpus() - priv->nthreads;
7437         if (shared > 0)
7438                 bitmap_fill(&priv->lock_map,
7439                             min_t(int, shared, MVPP2_MAX_THREADS));
7440
7441         for (i = 0; i < MVPP2_MAX_THREADS; i++) {
7442                 u32 addr_space_sz;
7443
7444                 addr_space_sz = (priv->hw_version == MVPP21 ?
7445                                  MVPP21_ADDR_SPACE_SZ : MVPP22_ADDR_SPACE_SZ);
7446                 priv->swth_base[i] = base + i * addr_space_sz;
7447         }
7448
7449         if (priv->hw_version == MVPP21)
7450                 priv->max_port_rxqs = 8;
7451         else
7452                 priv->max_port_rxqs = 32;
7453
7454         if (dev_of_node(&pdev->dev)) {
7455                 priv->pp_clk = devm_clk_get(&pdev->dev, "pp_clk");
7456                 if (IS_ERR(priv->pp_clk))
7457                         return PTR_ERR(priv->pp_clk);
7458                 err = clk_prepare_enable(priv->pp_clk);
7459                 if (err < 0)
7460                         return err;
7461
7462                 priv->gop_clk = devm_clk_get(&pdev->dev, "gop_clk");
7463                 if (IS_ERR(priv->gop_clk)) {
7464                         err = PTR_ERR(priv->gop_clk);
7465                         goto err_pp_clk;
7466                 }
7467                 err = clk_prepare_enable(priv->gop_clk);
7468                 if (err < 0)
7469                         goto err_pp_clk;
7470
7471                 if (priv->hw_version >= MVPP22) {
7472                         priv->mg_clk = devm_clk_get(&pdev->dev, "mg_clk");
7473                         if (IS_ERR(priv->mg_clk)) {
7474                                 err = PTR_ERR(priv->mg_clk);
7475                                 goto err_gop_clk;
7476                         }
7477
7478                         err = clk_prepare_enable(priv->mg_clk);
7479                         if (err < 0)
7480                                 goto err_gop_clk;
7481
7482                         priv->mg_core_clk = devm_clk_get_optional(&pdev->dev, "mg_core_clk");
7483                         if (IS_ERR(priv->mg_core_clk)) {
7484                                 err = PTR_ERR(priv->mg_core_clk);
7485                                 goto err_mg_clk;
7486                         }
7487
7488                         err = clk_prepare_enable(priv->mg_core_clk);
7489                         if (err < 0)
7490                                 goto err_mg_clk;
7491                 }
7492
7493                 priv->axi_clk = devm_clk_get_optional(&pdev->dev, "axi_clk");
7494                 if (IS_ERR(priv->axi_clk)) {
7495                         err = PTR_ERR(priv->axi_clk);
7496                         goto err_mg_core_clk;
7497                 }
7498
7499                 err = clk_prepare_enable(priv->axi_clk);
7500                 if (err < 0)
7501                         goto err_mg_core_clk;
7502
7503                 /* Get system's tclk rate */
7504                 priv->tclk = clk_get_rate(priv->pp_clk);
7505         } else {
7506                 err = device_property_read_u32(&pdev->dev, "clock-frequency", &priv->tclk);
7507                 if (err) {
7508                         dev_err(&pdev->dev, "missing clock-frequency value\n");
7509                         return err;
7510                 }
7511         }
7512
7513         if (priv->hw_version >= MVPP22) {
7514                 err = dma_set_mask(&pdev->dev, MVPP2_DESC_DMA_MASK);
7515                 if (err)
7516                         goto err_axi_clk;
7517                 /* Sadly, the BM pools all share the same register to
7518                  * store the high 32 bits of their address. So they
7519                  * must all have the same high 32 bits, which forces
7520                  * us to restrict coherent memory to DMA_BIT_MASK(32).
7521                  */
7522                 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
7523                 if (err)
7524                         goto err_axi_clk;
7525         }
7526
7527         /* Map DTS-active ports. Should be done before FIFO mvpp2_init */
7528         fwnode_for_each_available_child_node(fwnode, port_fwnode) {
7529                 if (!fwnode_property_read_u32(port_fwnode, "port-id", &i))
7530                         priv->port_map |= BIT(i);
7531         }
7532
7533         if (mvpp2_read(priv, MVPP2_VER_ID_REG) == MVPP2_VER_PP23)
7534                 priv->hw_version = MVPP23;
7535
7536         /* Init mss lock */
7537         spin_lock_init(&priv->mss_spinlock);
7538
7539         /* Initialize network controller */
7540         err = mvpp2_init(pdev, priv);
7541         if (err < 0) {
7542                 dev_err(&pdev->dev, "failed to initialize controller\n");
7543                 goto err_axi_clk;
7544         }
7545
7546         err = mvpp22_tai_probe(&pdev->dev, priv);
7547         if (err < 0)
7548                 goto err_axi_clk;
7549
7550         /* Initialize ports */
7551         fwnode_for_each_available_child_node(fwnode, port_fwnode) {
7552                 err = mvpp2_port_probe(pdev, port_fwnode, priv);
7553                 if (err < 0)
7554                         goto err_port_probe;
7555         }
7556
7557         if (priv->port_count == 0) {
7558                 dev_err(&pdev->dev, "no ports enabled\n");
7559                 err = -ENODEV;
7560                 goto err_axi_clk;
7561         }
7562
7563         /* Statistics must be gathered regularly because some of them (like
7564          * packets counters) are 32-bit registers and could overflow quite
7565          * quickly. For instance, a 10Gb link used at full bandwidth with the
7566          * smallest packets (64B) will overflow a 32-bit counter in less than
7567          * 30 seconds. Then, use a workqueue to fill 64-bit counters.
7568          */
7569         snprintf(priv->queue_name, sizeof(priv->queue_name),
7570                  "stats-wq-%s%s", netdev_name(priv->port_list[0]->dev),
7571                  priv->port_count > 1 ? "+" : "");
7572         priv->stats_queue = create_singlethread_workqueue(priv->queue_name);
7573         if (!priv->stats_queue) {
7574                 err = -ENOMEM;
7575                 goto err_port_probe;
7576         }
7577
7578         if (priv->global_tx_fc && priv->hw_version >= MVPP22) {
7579                 err = mvpp2_enable_global_fc(priv);
7580                 if (err)
7581                         dev_warn(&pdev->dev, "Minimum of CM3 firmware 18.09 and chip revision B0 required for flow control\n");
7582         }
7583
7584         mvpp2_dbgfs_init(priv, pdev->name);
7585
7586         platform_set_drvdata(pdev, priv);
7587         return 0;
7588
7589 err_port_probe:
7590         fwnode_handle_put(port_fwnode);
7591
7592         i = 0;
7593         fwnode_for_each_available_child_node(fwnode, port_fwnode) {
7594                 if (priv->port_list[i])
7595                         mvpp2_port_remove(priv->port_list[i]);
7596                 i++;
7597         }
7598 err_axi_clk:
7599         clk_disable_unprepare(priv->axi_clk);
7600 err_mg_core_clk:
7601         clk_disable_unprepare(priv->mg_core_clk);
7602 err_mg_clk:
7603         clk_disable_unprepare(priv->mg_clk);
7604 err_gop_clk:
7605         clk_disable_unprepare(priv->gop_clk);
7606 err_pp_clk:
7607         clk_disable_unprepare(priv->pp_clk);
7608         return err;
7609 }
7610
7611 static int mvpp2_remove(struct platform_device *pdev)
7612 {
7613         struct mvpp2 *priv = platform_get_drvdata(pdev);
7614         struct fwnode_handle *fwnode = pdev->dev.fwnode;
7615         int i = 0, poolnum = MVPP2_BM_POOLS_NUM;
7616         struct fwnode_handle *port_fwnode;
7617
7618         mvpp2_dbgfs_cleanup(priv);
7619
7620         fwnode_for_each_available_child_node(fwnode, port_fwnode) {
7621                 if (priv->port_list[i]) {
7622                         mutex_destroy(&priv->port_list[i]->gather_stats_lock);
7623                         mvpp2_port_remove(priv->port_list[i]);
7624                 }
7625                 i++;
7626         }
7627
7628         destroy_workqueue(priv->stats_queue);
7629
7630         if (priv->percpu_pools)
7631                 poolnum = mvpp2_get_nrxqs(priv) * 2;
7632
7633         for (i = 0; i < poolnum; i++) {
7634                 struct mvpp2_bm_pool *bm_pool = &priv->bm_pools[i];
7635
7636                 mvpp2_bm_pool_destroy(&pdev->dev, priv, bm_pool);
7637         }
7638
7639         for (i = 0; i < MVPP2_MAX_THREADS; i++) {
7640                 struct mvpp2_tx_queue *aggr_txq = &priv->aggr_txqs[i];
7641
7642                 dma_free_coherent(&pdev->dev,
7643                                   MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE,
7644                                   aggr_txq->descs,
7645                                   aggr_txq->descs_dma);
7646         }
7647
7648         if (is_acpi_node(port_fwnode))
7649                 return 0;
7650
7651         clk_disable_unprepare(priv->axi_clk);
7652         clk_disable_unprepare(priv->mg_core_clk);
7653         clk_disable_unprepare(priv->mg_clk);
7654         clk_disable_unprepare(priv->pp_clk);
7655         clk_disable_unprepare(priv->gop_clk);
7656
7657         return 0;
7658 }
7659
7660 static const struct of_device_id mvpp2_match[] = {
7661         {
7662                 .compatible = "marvell,armada-375-pp2",
7663                 .data = (void *)MVPP21,
7664         },
7665         {
7666                 .compatible = "marvell,armada-7k-pp22",
7667                 .data = (void *)MVPP22,
7668         },
7669         { }
7670 };
7671 MODULE_DEVICE_TABLE(of, mvpp2_match);
7672
7673 #ifdef CONFIG_ACPI
7674 static const struct acpi_device_id mvpp2_acpi_match[] = {
7675         { "MRVL0110", MVPP22 },
7676         { },
7677 };
7678 MODULE_DEVICE_TABLE(acpi, mvpp2_acpi_match);
7679 #endif
7680
7681 static struct platform_driver mvpp2_driver = {
7682         .probe = mvpp2_probe,
7683         .remove = mvpp2_remove,
7684         .driver = {
7685                 .name = MVPP2_DRIVER_NAME,
7686                 .of_match_table = mvpp2_match,
7687                 .acpi_match_table = ACPI_PTR(mvpp2_acpi_match),
7688         },
7689 };
7690
7691 module_platform_driver(mvpp2_driver);
7692
7693 MODULE_DESCRIPTION("Marvell PPv2 Ethernet Driver - www.marvell.com");
7694 MODULE_AUTHOR("Marcin Wojtas <mw@semihalf.com>");
7695 MODULE_LICENSE("GPL v2");