drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Driver for Marvell PPv2 network controller for Armada 375 SoC.
   4  *
   5  * Copyright (C) 2014 Marvell
   6  *
   7  * Marcin Wojtas <mw@semihalf.com>
   8  */
   9
  10 #include <linux/acpi.h>
  11 #include <linux/kernel.h>
  12 #include <linux/netdevice.h>
  13 #include <linux/etherdevice.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/skbuff.h>
  16 #include <linux/inetdevice.h>
  17 #include <linux/mbus.h>
  18 #include <linux/module.h>
  19 #include <linux/mfd/syscon.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/cpumask.h>
  22 #include <linux/of.h>
  23 #include <linux/of_irq.h>
  24 #include <linux/of_mdio.h>
  25 #include <linux/of_net.h>
  26 #include <linux/of_address.h>
  27 #include <linux/of_device.h>
  28 #include <linux/phy.h>
  29 #include <linux/phylink.h>
  30 #include <linux/phy/phy.h>
  31 #include <linux/clk.h>
  32 #include <linux/hrtimer.h>
  33 #include <linux/ktime.h>
  34 #include <linux/regmap.h>
  35 #include <uapi/linux/ppp_defs.h>
  36 #include <net/ip.h>
  37 #include <net/ipv6.h>
  38 #include <net/tso.h>
  39 #include <linux/bpf_trace.h>
  40
  41 #include "mvpp2.h"
  42 #include "mvpp2_prs.h"
  43 #include "mvpp2_cls.h"
  44
  45 enum mvpp2_bm_pool_log_num {
  46         MVPP2_BM_SHORT,
  47         MVPP2_BM_LONG,
  48         MVPP2_BM_JUMBO,
  49         MVPP2_BM_POOLS_NUM
  50 };
  51
  52 static struct {
  53         int pkt_size;
  54         int buf_num;
  55 } mvpp2_pools[MVPP2_BM_POOLS_NUM];
  56
  57 /* The prototype is added here to be used in start_dev when using ACPI. This
  58  * will be removed once phylink is used for all modes (dt+ACPI).
  59  */
  60 static void mvpp2_mac_config(struct phylink_config *config, unsigned int mode,
  61                              const struct phylink_link_state *state);
  62 static void mvpp2_mac_link_up(struct phylink_config *config,
  63                               struct phy_device *phy,
  64                               unsigned int mode, phy_interface_t interface,
  65                               int speed, int duplex,
  66                               bool tx_pause, bool rx_pause);
  67
  68 /* Queue modes */
  69 #define MVPP2_QDIST_SINGLE_MODE 0
  70 #define MVPP2_QDIST_MULTI_MODE  1
  71
  72 static int queue_mode = MVPP2_QDIST_MULTI_MODE;
  73
  74 module_param(queue_mode, int, 0444);
  75 MODULE_PARM_DESC(queue_mode, "Set queue_mode (single=0, multi=1)");
  76
  77 /* Utility/helper methods */
  78
  79 void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data)
  80 {
  81         writel(data, priv->swth_base[0] + offset);
  82 }
  83
  84 u32 mvpp2_read(struct mvpp2 *priv, u32 offset)
  85 {
  86         return readl(priv->swth_base[0] + offset);
  87 }
  88
  89 static u32 mvpp2_read_relaxed(struct mvpp2 *priv, u32 offset)
  90 {
  91         return readl_relaxed(priv->swth_base[0] + offset);
  92 }
  93
  94 static inline u32 mvpp2_cpu_to_thread(struct mvpp2 *priv, int cpu)
  95 {
  96         return cpu % priv->nthreads;
  97 }
  98
  99 static struct page_pool *
 100 mvpp2_create_page_pool(struct device *dev, int num, int len,
 101                        enum dma_data_direction dma_dir)
 102 {
 103         struct page_pool_params pp_params = {
 104                 /* internal DMA mapping in page_pool */
 105                 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV,
 106                 .pool_size = num,
 107                 .nid = NUMA_NO_NODE,
 108                 .dev = dev,
 109                 .dma_dir = dma_dir,
 110                 .offset = MVPP2_SKB_HEADROOM,
 111                 .max_len = len,
 112         };
 113
 114         return page_pool_create(&pp_params);
 115 }
 116
 117 /* These accessors should be used to access:
 118  *
 119  * - per-thread registers, where each thread has its own copy of the
 120  *   register.
 121  *
 122  *   MVPP2_BM_VIRT_ALLOC_REG
 123  *   MVPP2_BM_ADDR_HIGH_ALLOC
 124  *   MVPP22_BM_ADDR_HIGH_RLS_REG
 125  *   MVPP2_BM_VIRT_RLS_REG
 126  *   MVPP2_ISR_RX_TX_CAUSE_REG
 127  *   MVPP2_ISR_RX_TX_MASK_REG
 128  *   MVPP2_TXQ_NUM_REG
 129  *   MVPP2_AGGR_TXQ_UPDATE_REG
 130  *   MVPP2_TXQ_RSVD_REQ_REG
 131  *   MVPP2_TXQ_RSVD_RSLT_REG
 132  *   MVPP2_TXQ_SENT_REG
 133  *   MVPP2_RXQ_NUM_REG
 134  *
 135  * - global registers that must be accessed through a specific thread
 136  *   window, because they are related to an access to a per-thread
 137  *   register
 138  *
 139  *   MVPP2_BM_PHY_ALLOC_REG    (related to MVPP2_BM_VIRT_ALLOC_REG)
 140  *   MVPP2_BM_PHY_RLS_REG      (related to MVPP2_BM_VIRT_RLS_REG)
 141  *   MVPP2_RXQ_THRESH_REG      (related to MVPP2_RXQ_NUM_REG)
 142  *   MVPP2_RXQ_DESC_ADDR_REG   (related to MVPP2_RXQ_NUM_REG)
 143  *   MVPP2_RXQ_DESC_SIZE_REG   (related to MVPP2_RXQ_NUM_REG)
 144  *   MVPP2_RXQ_INDEX_REG       (related to MVPP2_RXQ_NUM_REG)
 145  *   MVPP2_TXQ_PENDING_REG     (related to MVPP2_TXQ_NUM_REG)
 146  *   MVPP2_TXQ_DESC_ADDR_REG   (related to MVPP2_TXQ_NUM_REG)
 147  *   MVPP2_TXQ_DESC_SIZE_REG   (related to MVPP2_TXQ_NUM_REG)
 148  *   MVPP2_TXQ_INDEX_REG       (related to MVPP2_TXQ_NUM_REG)
 149  *   MVPP2_TXQ_PENDING_REG     (related to MVPP2_TXQ_NUM_REG)
 150  *   MVPP2_TXQ_PREF_BUF_REG    (related to MVPP2_TXQ_NUM_REG)
 151  *   MVPP2_TXQ_PREF_BUF_REG    (related to MVPP2_TXQ_NUM_REG)
 152  */
 153 static void mvpp2_thread_write(struct mvpp2 *priv, unsigned int thread,
 154                                u32 offset, u32 data)
 155 {
 156         writel(data, priv->swth_base[thread] + offset);
 157 }
 158
 159 static u32 mvpp2_thread_read(struct mvpp2 *priv, unsigned int thread,
 160                              u32 offset)
 161 {
 162         return readl(priv->swth_base[thread] + offset);
 163 }
 164
 165 static void mvpp2_thread_write_relaxed(struct mvpp2 *priv, unsigned int thread,
 166                                        u32 offset, u32 data)
 167 {
 168         writel_relaxed(data, priv->swth_base[thread] + offset);
 169 }
 170
 171 static u32 mvpp2_thread_read_relaxed(struct mvpp2 *priv, unsigned int thread,
 172                                      u32 offset)
 173 {
 174         return readl_relaxed(priv->swth_base[thread] + offset);
 175 }
 176
 177 static dma_addr_t mvpp2_txdesc_dma_addr_get(struct mvpp2_port *port,
 178                                             struct mvpp2_tx_desc *tx_desc)
 179 {
 180         if (port->priv->hw_version == MVPP21)
 181                 return le32_to_cpu(tx_desc->pp21.buf_dma_addr);
 182         else
 183                 return le64_to_cpu(tx_desc->pp22.buf_dma_addr_ptp) &
 184                        MVPP2_DESC_DMA_MASK;
 185 }
 186
 187 static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port,
 188                                       struct mvpp2_tx_desc *tx_desc,
 189                                       dma_addr_t dma_addr)
 190 {
 191         dma_addr_t addr, offset;
 192
 193         addr = dma_addr & ~MVPP2_TX_DESC_ALIGN;
 194         offset = dma_addr & MVPP2_TX_DESC_ALIGN;
 195
 196         if (port->priv->hw_version == MVPP21) {
 197                 tx_desc->pp21.buf_dma_addr = cpu_to_le32(addr);
 198                 tx_desc->pp21.packet_offset = offset;
 199         } else {
 200                 __le64 val = cpu_to_le64(addr);
 201
 202                 tx_desc->pp22.buf_dma_addr_ptp &= ~cpu_to_le64(MVPP2_DESC_DMA_MASK);
 203                 tx_desc->pp22.buf_dma_addr_ptp |= val;
 204                 tx_desc->pp22.packet_offset = offset;
 205         }
 206 }
 207
 208 static size_t mvpp2_txdesc_size_get(struct mvpp2_port *port,
 209                                     struct mvpp2_tx_desc *tx_desc)
 210 {
 211         if (port->priv->hw_version == MVPP21)
 212                 return le16_to_cpu(tx_desc->pp21.data_size);
 213         else
 214                 return le16_to_cpu(tx_desc->pp22.data_size);
 215 }
 216
 217 static void mvpp2_txdesc_size_set(struct mvpp2_port *port,
 218                                   struct mvpp2_tx_desc *tx_desc,
 219                                   size_t size)
 220 {
 221         if (port->priv->hw_version == MVPP21)
 222                 tx_desc->pp21.data_size = cpu_to_le16(size);
 223         else
 224                 tx_desc->pp22.data_size = cpu_to_le16(size);
 225 }
 226
 227 static void mvpp2_txdesc_txq_set(struct mvpp2_port *port,
 228                                  struct mvpp2_tx_desc *tx_desc,
 229                                  unsigned int txq)
 230 {
 231         if (port->priv->hw_version == MVPP21)
 232                 tx_desc->pp21.phys_txq = txq;
 233         else
 234                 tx_desc->pp22.phys_txq = txq;
 235 }
 236
 237 static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port,
 238                                  struct mvpp2_tx_desc *tx_desc,
 239                                  unsigned int command)
 240 {
 241         if (port->priv->hw_version == MVPP21)
 242                 tx_desc->pp21.command = cpu_to_le32(command);
 243         else
 244                 tx_desc->pp22.command = cpu_to_le32(command);
 245 }
 246
 247 static unsigned int mvpp2_txdesc_offset_get(struct mvpp2_port *port,
 248                                             struct mvpp2_tx_desc *tx_desc)
 249 {
 250         if (port->priv->hw_version == MVPP21)
 251                 return tx_desc->pp21.packet_offset;
 252         else
 253                 return tx_desc->pp22.packet_offset;
 254 }
 255
 256 static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port,
 257                                             struct mvpp2_rx_desc *rx_desc)
 258 {
 259         if (port->priv->hw_version == MVPP21)
 260                 return le32_to_cpu(rx_desc->pp21.buf_dma_addr);
 261         else
 262                 return le64_to_cpu(rx_desc->pp22.buf_dma_addr_key_hash) &
 263                        MVPP2_DESC_DMA_MASK;
 264 }
 265
 266 static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port,
 267                                              struct mvpp2_rx_desc *rx_desc)
 268 {
 269         if (port->priv->hw_version == MVPP21)
 270                 return le32_to_cpu(rx_desc->pp21.buf_cookie);
 271         else
 272                 return le64_to_cpu(rx_desc->pp22.buf_cookie_misc) &
 273                        MVPP2_DESC_DMA_MASK;
 274 }
 275
 276 static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port,
 277                                     struct mvpp2_rx_desc *rx_desc)
 278 {
 279         if (port->priv->hw_version == MVPP21)
 280                 return le16_to_cpu(rx_desc->pp21.data_size);
 281         else
 282                 return le16_to_cpu(rx_desc->pp22.data_size);
 283 }
 284
 285 static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port,
 286                                    struct mvpp2_rx_desc *rx_desc)
 287 {
 288         if (port->priv->hw_version == MVPP21)
 289                 return le32_to_cpu(rx_desc->pp21.status);
 290         else
 291                 return le32_to_cpu(rx_desc->pp22.status);
 292 }
 293
 294 static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu)
 295 {
 296         txq_pcpu->txq_get_index++;
 297         if (txq_pcpu->txq_get_index == txq_pcpu->size)
 298                 txq_pcpu->txq_get_index = 0;
 299 }
 300
 301 static void mvpp2_txq_inc_put(struct mvpp2_port *port,
 302                               struct mvpp2_txq_pcpu *txq_pcpu,
 303                               void *data,
 304                               struct mvpp2_tx_desc *tx_desc,
 305                               enum mvpp2_tx_buf_type buf_type)
 306 {
 307         struct mvpp2_txq_pcpu_buf *tx_buf =
 308                 txq_pcpu->buffs + txq_pcpu->txq_put_index;
 309         tx_buf->type = buf_type;
 310         if (buf_type == MVPP2_TYPE_SKB)
 311                 tx_buf->skb = data;
 312         else
 313                 tx_buf->xdpf = data;
 314         tx_buf->size = mvpp2_txdesc_size_get(port, tx_desc);
 315         tx_buf->dma = mvpp2_txdesc_dma_addr_get(port, tx_desc) +
 316                 mvpp2_txdesc_offset_get(port, tx_desc);
 317         txq_pcpu->txq_put_index++;
 318         if (txq_pcpu->txq_put_index == txq_pcpu->size)
 319                 txq_pcpu->txq_put_index = 0;
 320 }
 321
 322 /* Get number of maximum RXQ */
 323 static int mvpp2_get_nrxqs(struct mvpp2 *priv)
 324 {
 325         unsigned int nrxqs;
 326
 327         if (priv->hw_version == MVPP22 && queue_mode == MVPP2_QDIST_SINGLE_MODE)
 328                 return 1;
 329
 330         /* According to the PPv2.2 datasheet and our experiments on
 331          * PPv2.1, RX queues have an allocation granularity of 4 (when
 332          * more than a single one on PPv2.2).
 333          * Round up to nearest multiple of 4.
 334          */
 335         nrxqs = (num_possible_cpus() + 3) & ~0x3;
 336         if (nrxqs > MVPP2_PORT_MAX_RXQ)
 337                 nrxqs = MVPP2_PORT_MAX_RXQ;
 338
 339         return nrxqs;
 340 }
 341
 342 /* Get number of physical egress port */
 343 static inline int mvpp2_egress_port(struct mvpp2_port *port)
 344 {
 345         return MVPP2_MAX_TCONT + port->id;
 346 }
 347
 348 /* Get number of physical TXQ */
 349 static inline int mvpp2_txq_phys(int port, int txq)
 350 {
 351         return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq;
 352 }
 353
 354 /* Returns a struct page if page_pool is set, otherwise a buffer */
 355 static void *mvpp2_frag_alloc(const struct mvpp2_bm_pool *pool,
 356                               struct page_pool *page_pool)
 357 {
 358         if (page_pool)
 359                 return page_pool_dev_alloc_pages(page_pool);
 360
 361         if (likely(pool->frag_size <= PAGE_SIZE))
 362                 return netdev_alloc_frag(pool->frag_size);
 363
 364         return kmalloc(pool->frag_size, GFP_ATOMIC);
 365 }
 366
 367 static void mvpp2_frag_free(const struct mvpp2_bm_pool *pool,
 368                             struct page_pool *page_pool, void *data)
 369 {
 370         if (page_pool)
 371                 page_pool_put_full_page(page_pool, virt_to_head_page(data), false);
 372         else if (likely(pool->frag_size <= PAGE_SIZE))
 373                 skb_free_frag(data);
 374         else
 375                 kfree(data);
 376 }
 377
 378 /* Buffer Manager configuration routines */
 379
 380 /* Create pool */
 381 static int mvpp2_bm_pool_create(struct device *dev, struct mvpp2 *priv,
 382                                 struct mvpp2_bm_pool *bm_pool, int size)
 383 {
 384         u32 val;
 385
 386         /* Number of buffer pointers must be a multiple of 16, as per
 387          * hardware constraints
 388          */
 389         if (!IS_ALIGNED(size, 16))
 390                 return -EINVAL;
 391
 392         /* PPv2.1 needs 8 bytes per buffer pointer, PPv2.2 needs 16
 393          * bytes per buffer pointer
 394          */
 395         if (priv->hw_version == MVPP21)
 396                 bm_pool->size_bytes = 2 * sizeof(u32) * size;
 397         else
 398                 bm_pool->size_bytes = 2 * sizeof(u64) * size;
 399
 400         bm_pool->virt_addr = dma_alloc_coherent(dev, bm_pool->size_bytes,
 401                                                 &bm_pool->dma_addr,
 402                                                 GFP_KERNEL);
 403         if (!bm_pool->virt_addr)
 404                 return -ENOMEM;
 405
 406         if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr,
 407                         MVPP2_BM_POOL_PTR_ALIGN)) {
 408                 dma_free_coherent(dev, bm_pool->size_bytes,
 409                                   bm_pool->virt_addr, bm_pool->dma_addr);
 410                 dev_err(dev, "BM pool %d is not %d bytes aligned\n",
 411                         bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN);
 412                 return -ENOMEM;
 413         }
 414
 415         mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id),
 416                     lower_32_bits(bm_pool->dma_addr));
 417         mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size);
 418
 419         val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
 420         val |= MVPP2_BM_START_MASK;
 421         mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
 422
 423         bm_pool->size = size;
 424         bm_pool->pkt_size = 0;
 425         bm_pool->buf_num = 0;
 426
 427         return 0;
 428 }
 429
 430 /* Set pool buffer size */
 431 static void mvpp2_bm_pool_bufsize_set(struct mvpp2 *priv,
 432                                       struct mvpp2_bm_pool *bm_pool,
 433                                       int buf_size)
 434 {
 435         u32 val;
 436
 437         bm_pool->buf_size = buf_size;
 438
 439         val = ALIGN(buf_size, 1 << MVPP2_POOL_BUF_SIZE_OFFSET);
 440         mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val);
 441 }
 442
 443 static void mvpp2_bm_bufs_get_addrs(struct device *dev, struct mvpp2 *priv,
 444                                     struct mvpp2_bm_pool *bm_pool,
 445                                     dma_addr_t *dma_addr,
 446                                     phys_addr_t *phys_addr)
 447 {
 448         unsigned int thread = mvpp2_cpu_to_thread(priv, get_cpu());
 449
 450         *dma_addr = mvpp2_thread_read(priv, thread,
 451                                       MVPP2_BM_PHY_ALLOC_REG(bm_pool->id));
 452         *phys_addr = mvpp2_thread_read(priv, thread, MVPP2_BM_VIRT_ALLOC_REG);
 453
 454         if (priv->hw_version == MVPP22) {
 455                 u32 val;
 456                 u32 dma_addr_highbits, phys_addr_highbits;
 457
 458                 val = mvpp2_thread_read(priv, thread, MVPP22_BM_ADDR_HIGH_ALLOC);
 459                 dma_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_PHYS_MASK);
 460                 phys_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_VIRT_MASK) >>
 461                         MVPP22_BM_ADDR_HIGH_VIRT_SHIFT;
 462
 463                 if (sizeof(dma_addr_t) == 8)
 464                         *dma_addr |= (u64)dma_addr_highbits << 32;
 465
 466                 if (sizeof(phys_addr_t) == 8)
 467                         *phys_addr |= (u64)phys_addr_highbits << 32;
 468         }
 469
 470         put_cpu();
 471 }
 472
 473 /* Free all buffers from the pool */
 474 static void mvpp2_bm_bufs_free(struct device *dev, struct mvpp2 *priv,
 475                                struct mvpp2_bm_pool *bm_pool, int buf_num)
 476 {
 477         struct page_pool *pp = NULL;
 478         int i;
 479
 480         if (buf_num > bm_pool->buf_num) {
 481                 WARN(1, "Pool does not have so many bufs pool(%d) bufs(%d)\n",
 482                      bm_pool->id, buf_num);
 483                 buf_num = bm_pool->buf_num;
 484         }
 485
 486         if (priv->percpu_pools)
 487                 pp = priv->page_pool[bm_pool->id];
 488
 489         for (i = 0; i < buf_num; i++) {
 490                 dma_addr_t buf_dma_addr;
 491                 phys_addr_t buf_phys_addr;
 492                 void *data;
 493
 494                 mvpp2_bm_bufs_get_addrs(dev, priv, bm_pool,
 495                                         &buf_dma_addr, &buf_phys_addr);
 496
 497                 if (!pp)
 498                         dma_unmap_single(dev, buf_dma_addr,
 499                                          bm_pool->buf_size, DMA_FROM_DEVICE);
 500
 501                 data = (void *)phys_to_virt(buf_phys_addr);
 502                 if (!data)
 503                         break;
 504
 505                 mvpp2_frag_free(bm_pool, pp, data);
 506         }
 507
 508         /* Update BM driver with number of buffers removed from pool */
 509         bm_pool->buf_num -= i;
 510 }
 511
 512 /* Check number of buffers in BM pool */
 513 static int mvpp2_check_hw_buf_num(struct mvpp2 *priv, struct mvpp2_bm_pool *bm_pool)
 514 {
 515         int buf_num = 0;
 516
 517         buf_num += mvpp2_read(priv, MVPP2_BM_POOL_PTRS_NUM_REG(bm_pool->id)) &
 518                                     MVPP22_BM_POOL_PTRS_NUM_MASK;
 519         buf_num += mvpp2_read(priv, MVPP2_BM_BPPI_PTRS_NUM_REG(bm_pool->id)) &
 520                                     MVPP2_BM_BPPI_PTR_NUM_MASK;
 521
 522         /* HW has one buffer ready which is not reflected in the counters */
 523         if (buf_num)
 524                 buf_num += 1;
 525
 526         return buf_num;
 527 }
 528
 529 /* Cleanup pool */
 530 static int mvpp2_bm_pool_destroy(struct device *dev, struct mvpp2 *priv,
 531                                  struct mvpp2_bm_pool *bm_pool)
 532 {
 533         int buf_num;
 534         u32 val;
 535
 536         buf_num = mvpp2_check_hw_buf_num(priv, bm_pool);
 537         mvpp2_bm_bufs_free(dev, priv, bm_pool, buf_num);
 538
 539         /* Check buffer counters after free */
 540         buf_num = mvpp2_check_hw_buf_num(priv, bm_pool);
 541         if (buf_num) {
 542                 WARN(1, "cannot free all buffers in pool %d, buf_num left %d\n",
 543                      bm_pool->id, bm_pool->buf_num);
 544                 return 0;
 545         }
 546
 547         val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
 548         val |= MVPP2_BM_STOP_MASK;
 549         mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
 550
 551         if (priv->percpu_pools) {
 552                 page_pool_destroy(priv->page_pool[bm_pool->id]);
 553                 priv->page_pool[bm_pool->id] = NULL;
 554         }
 555
 556         dma_free_coherent(dev, bm_pool->size_bytes,
 557                           bm_pool->virt_addr,
 558                           bm_pool->dma_addr);
 559         return 0;
 560 }
 561
 562 static int mvpp2_bm_pools_init(struct device *dev, struct mvpp2 *priv)
 563 {
 564         int i, err, size, poolnum = MVPP2_BM_POOLS_NUM;
 565         struct mvpp2_bm_pool *bm_pool;
 566
 567         if (priv->percpu_pools)
 568                 poolnum = mvpp2_get_nrxqs(priv) * 2;
 569
 570         /* Create all pools with maximum size */
 571         size = MVPP2_BM_POOL_SIZE_MAX;
 572         for (i = 0; i < poolnum; i++) {
 573                 bm_pool = &priv->bm_pools[i];
 574                 bm_pool->id = i;
 575                 err = mvpp2_bm_pool_create(dev, priv, bm_pool, size);
 576                 if (err)
 577                         goto err_unroll_pools;
 578                 mvpp2_bm_pool_bufsize_set(priv, bm_pool, 0);
 579         }
 580         return 0;
 581
 582 err_unroll_pools:
 583         dev_err(dev, "failed to create BM pool %d, size %d\n", i, size);
 584         for (i = i - 1; i >= 0; i--)
 585                 mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]);
 586         return err;
 587 }
 588
 589 static int mvpp2_bm_init(struct device *dev, struct mvpp2 *priv)
 590 {
 591         enum dma_data_direction dma_dir = DMA_FROM_DEVICE;
 592         int i, err, poolnum = MVPP2_BM_POOLS_NUM;
 593         struct mvpp2_port *port;
 594
 595         if (priv->percpu_pools) {
 596                 for (i = 0; i < priv->port_count; i++) {
 597                         port = priv->port_list[i];
 598                         if (port->xdp_prog) {
 599                                 dma_dir = DMA_BIDIRECTIONAL;
 600                                 break;
 601                         }
 602                 }
 603
 604                 poolnum = mvpp2_get_nrxqs(priv) * 2;
 605                 for (i = 0; i < poolnum; i++) {
 606                         /* the pool in use */
 607                         int pn = i / (poolnum / 2);
 608
 609                         priv->page_pool[i] =
 610                                 mvpp2_create_page_pool(dev,
 611                                                        mvpp2_pools[pn].buf_num,
 612                                                        mvpp2_pools[pn].pkt_size,
 613                                                        dma_dir);
 614                         if (IS_ERR(priv->page_pool[i])) {
 615                                 int j;
 616
 617                                 for (j = 0; j < i; j++) {
 618                                         page_pool_destroy(priv->page_pool[j]);
 619                                         priv->page_pool[j] = NULL;
 620                                 }
 621                                 return PTR_ERR(priv->page_pool[i]);
 622                         }
 623                 }
 624         }
 625
 626         dev_info(dev, "using %d %s buffers\n", poolnum,
 627                  priv->percpu_pools ? "per-cpu" : "shared");
 628
 629         for (i = 0; i < poolnum; i++) {
 630                 /* Mask BM all interrupts */
 631                 mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0);
 632                 /* Clear BM cause register */
 633                 mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0);
 634         }
 635
 636         /* Allocate and initialize BM pools */
 637         priv->bm_pools = devm_kcalloc(dev, poolnum,
 638                                       sizeof(*priv->bm_pools), GFP_KERNEL);
 639         if (!priv->bm_pools)
 640                 return -ENOMEM;
 641
 642         err = mvpp2_bm_pools_init(dev, priv);
 643         if (err < 0)
 644                 return err;
 645         return 0;
 646 }
 647
 648 static void mvpp2_setup_bm_pool(void)
 649 {
 650         /* Short pool */
 651         mvpp2_pools[MVPP2_BM_SHORT].buf_num  = MVPP2_BM_SHORT_BUF_NUM;
 652         mvpp2_pools[MVPP2_BM_SHORT].pkt_size = MVPP2_BM_SHORT_PKT_SIZE;
 653
 654         /* Long pool */
 655         mvpp2_pools[MVPP2_BM_LONG].buf_num  = MVPP2_BM_LONG_BUF_NUM;
 656         mvpp2_pools[MVPP2_BM_LONG].pkt_size = MVPP2_BM_LONG_PKT_SIZE;
 657
 658         /* Jumbo pool */
 659         mvpp2_pools[MVPP2_BM_JUMBO].buf_num  = MVPP2_BM_JUMBO_BUF_NUM;
 660         mvpp2_pools[MVPP2_BM_JUMBO].pkt_size = MVPP2_BM_JUMBO_PKT_SIZE;
 661 }
 662
 663 /* Attach long pool to rxq */
 664 static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port,
 665                                     int lrxq, int long_pool)
 666 {
 667         u32 val, mask;
 668         int prxq;
 669
 670         /* Get queue physical ID */
 671         prxq = port->rxqs[lrxq]->id;
 672
 673         if (port->priv->hw_version == MVPP21)
 674                 mask = MVPP21_RXQ_POOL_LONG_MASK;
 675         else
 676                 mask = MVPP22_RXQ_POOL_LONG_MASK;
 677
 678         val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
 679         val &= ~mask;
 680         val |= (long_pool << MVPP2_RXQ_POOL_LONG_OFFS) & mask;
 681         mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
 682 }
 683
 684 /* Attach short pool to rxq */
 685 static void mvpp2_rxq_short_pool_set(struct mvpp2_port *port,
 686                                      int lrxq, int short_pool)
 687 {
 688         u32 val, mask;
 689         int prxq;
 690
 691         /* Get queue physical ID */
 692         prxq = port->rxqs[lrxq]->id;
 693
 694         if (port->priv->hw_version == MVPP21)
 695                 mask = MVPP21_RXQ_POOL_SHORT_MASK;
 696         else
 697                 mask = MVPP22_RXQ_POOL_SHORT_MASK;
 698
 699         val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
 700         val &= ~mask;
 701         val |= (short_pool << MVPP2_RXQ_POOL_SHORT_OFFS) & mask;
 702         mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
 703 }
 704
 705 static void *mvpp2_buf_alloc(struct mvpp2_port *port,
 706                              struct mvpp2_bm_pool *bm_pool,
 707                              struct page_pool *page_pool,
 708                              dma_addr_t *buf_dma_addr,
 709                              phys_addr_t *buf_phys_addr,
 710                              gfp_t gfp_mask)
 711 {
 712         dma_addr_t dma_addr;
 713         struct page *page;
 714         void *data;
 715
 716         data = mvpp2_frag_alloc(bm_pool, page_pool);
 717         if (!data)
 718                 return NULL;
 719
 720         if (page_pool) {
 721                 page = (struct page *)data;
 722                 dma_addr = page_pool_get_dma_addr(page);
 723                 data = page_to_virt(page);
 724         } else {
 725                 dma_addr = dma_map_single(port->dev->dev.parent, data,
 726                                           MVPP2_RX_BUF_SIZE(bm_pool->pkt_size),
 727                                           DMA_FROM_DEVICE);
 728                 if (unlikely(dma_mapping_error(port->dev->dev.parent, dma_addr))) {
 729                         mvpp2_frag_free(bm_pool, NULL, data);
 730                         return NULL;
 731                 }
 732         }
 733         *buf_dma_addr = dma_addr;
 734         *buf_phys_addr = virt_to_phys(data);
 735
 736         return data;
 737 }
 738
 739 /* Release buffer to BM */
 740 static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
 741                                      dma_addr_t buf_dma_addr,
 742                                      phys_addr_t buf_phys_addr)
 743 {
 744         unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
 745         unsigned long flags = 0;
 746
 747         if (test_bit(thread, &port->priv->lock_map))
 748                 spin_lock_irqsave(&port->bm_lock[thread], flags);
 749
 750         if (port->priv->hw_version == MVPP22) {
 751                 u32 val = 0;
 752
 753                 if (sizeof(dma_addr_t) == 8)
 754                         val |= upper_32_bits(buf_dma_addr) &
 755                                 MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK;
 756
 757                 if (sizeof(phys_addr_t) == 8)
 758                         val |= (upper_32_bits(buf_phys_addr)
 759                                 << MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT) &
 760                                 MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK;
 761
 762                 mvpp2_thread_write_relaxed(port->priv, thread,
 763                                            MVPP22_BM_ADDR_HIGH_RLS_REG, val);
 764         }
 765
 766         /* MVPP2_BM_VIRT_RLS_REG is not interpreted by HW, and simply
 767          * returned in the "cookie" field of the RX
 768          * descriptor. Instead of storing the virtual address, we
 769          * store the physical address
 770          */
 771         mvpp2_thread_write_relaxed(port->priv, thread,
 772                                    MVPP2_BM_VIRT_RLS_REG, buf_phys_addr);
 773         mvpp2_thread_write_relaxed(port->priv, thread,
 774                                    MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr);
 775
 776         if (test_bit(thread, &port->priv->lock_map))
 777                 spin_unlock_irqrestore(&port->bm_lock[thread], flags);
 778
 779         put_cpu();
 780 }
 781
 782 /* Allocate buffers for the pool */
 783 static int mvpp2_bm_bufs_add(struct mvpp2_port *port,
 784                              struct mvpp2_bm_pool *bm_pool, int buf_num)
 785 {
 786         int i, buf_size, total_size;
 787         dma_addr_t dma_addr;
 788         phys_addr_t phys_addr;
 789         struct page_pool *pp = NULL;
 790         void *buf;
 791
 792         if (port->priv->percpu_pools &&
 793             bm_pool->pkt_size > MVPP2_BM_LONG_PKT_SIZE) {
 794                 netdev_err(port->dev,
 795                            "attempted to use jumbo frames with per-cpu pools");
 796                 return 0;
 797         }
 798
 799         buf_size = MVPP2_RX_BUF_SIZE(bm_pool->pkt_size);
 800         total_size = MVPP2_RX_TOTAL_SIZE(buf_size);
 801
 802         if (buf_num < 0 ||
 803             (buf_num + bm_pool->buf_num > bm_pool->size)) {
 804                 netdev_err(port->dev,
 805                            "cannot allocate %d buffers for pool %d\n",
 806                            buf_num, bm_pool->id);
 807                 return 0;
 808         }
 809
 810         if (port->priv->percpu_pools)
 811                 pp = port->priv->page_pool[bm_pool->id];
 812         for (i = 0; i < buf_num; i++) {
 813                 buf = mvpp2_buf_alloc(port, bm_pool, pp, &dma_addr,
 814                                       &phys_addr, GFP_KERNEL);
 815                 if (!buf)
 816                         break;
 817
 818                 mvpp2_bm_pool_put(port, bm_pool->id, dma_addr,
 819                                   phys_addr);
 820         }
 821
 822         /* Update BM driver with number of buffers added to pool */
 823         bm_pool->buf_num += i;
 824
 825         netdev_dbg(port->dev,
 826                    "pool %d: pkt_size=%4d, buf_size=%4d, total_size=%4d\n",
 827                    bm_pool->id, bm_pool->pkt_size, buf_size, total_size);
 828
 829         netdev_dbg(port->dev,
 830                    "pool %d: %d of %d buffers added\n",
 831                    bm_pool->id, i, buf_num);
 832         return i;
 833 }
 834
 835 /* Notify the driver that BM pool is being used as specific type and return the
 836  * pool pointer on success
 837  */
 838 static struct mvpp2_bm_pool *
 839 mvpp2_bm_pool_use(struct mvpp2_port *port, unsigned pool, int pkt_size)
 840 {
 841         struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool];
 842         int num;
 843
 844         if ((port->priv->percpu_pools && pool > mvpp2_get_nrxqs(port->priv) * 2) ||
 845             (!port->priv->percpu_pools && pool >= MVPP2_BM_POOLS_NUM)) {
 846                 netdev_err(port->dev, "Invalid pool %d\n", pool);
 847                 return NULL;
 848         }
 849
 850         /* Allocate buffers in case BM pool is used as long pool, but packet
 851          * size doesn't match MTU or BM pool hasn't being used yet
 852          */
 853         if (new_pool->pkt_size == 0) {
 854                 int pkts_num;
 855
 856                 /* Set default buffer number or free all the buffers in case
 857                  * the pool is not empty
 858                  */
 859                 pkts_num = new_pool->buf_num;
 860                 if (pkts_num == 0) {
 861                         if (port->priv->percpu_pools) {
 862                                 if (pool < port->nrxqs)
 863                                         pkts_num = mvpp2_pools[MVPP2_BM_SHORT].buf_num;
 864                                 else
 865                                         pkts_num = mvpp2_pools[MVPP2_BM_LONG].buf_num;
 866                         } else {
 867                                 pkts_num = mvpp2_pools[pool].buf_num;
 868                         }
 869                 } else {
 870                         mvpp2_bm_bufs_free(port->dev->dev.parent,
 871                                            port->priv, new_pool, pkts_num);
 872                 }
 873
 874                 new_pool->pkt_size = pkt_size;
 875                 new_pool->frag_size =
 876                         SKB_DATA_ALIGN(MVPP2_RX_BUF_SIZE(pkt_size)) +
 877                         MVPP2_SKB_SHINFO_SIZE;
 878
 879                 /* Allocate buffers for this pool */
 880                 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num);
 881                 if (num != pkts_num) {
 882                         WARN(1, "pool %d: %d of %d allocated\n",
 883                              new_pool->id, num, pkts_num);
 884                         return NULL;
 885                 }
 886         }
 887
 888         mvpp2_bm_pool_bufsize_set(port->priv, new_pool,
 889                                   MVPP2_RX_BUF_SIZE(new_pool->pkt_size));
 890
 891         return new_pool;
 892 }
 893
 894 static struct mvpp2_bm_pool *
 895 mvpp2_bm_pool_use_percpu(struct mvpp2_port *port, int type,
 896                          unsigned int pool, int pkt_size)
 897 {
 898         struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool];
 899         int num;
 900
 901         if (pool > port->nrxqs * 2) {
 902                 netdev_err(port->dev, "Invalid pool %d\n", pool);
 903                 return NULL;
 904         }
 905
 906         /* Allocate buffers in case BM pool is used as long pool, but packet
 907          * size doesn't match MTU or BM pool hasn't being used yet
 908          */
 909         if (new_pool->pkt_size == 0) {
 910                 int pkts_num;
 911
 912                 /* Set default buffer number or free all the buffers in case
 913                  * the pool is not empty
 914                  */
 915                 pkts_num = new_pool->buf_num;
 916                 if (pkts_num == 0)
 917                         pkts_num = mvpp2_pools[type].buf_num;
 918                 else
 919                         mvpp2_bm_bufs_free(port->dev->dev.parent,
 920                                            port->priv, new_pool, pkts_num);
 921
 922                 new_pool->pkt_size = pkt_size;
 923                 new_pool->frag_size =
 924                         SKB_DATA_ALIGN(MVPP2_RX_BUF_SIZE(pkt_size)) +
 925                         MVPP2_SKB_SHINFO_SIZE;
 926
 927                 /* Allocate buffers for this pool */
 928                 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num);
 929                 if (num != pkts_num) {
 930                         WARN(1, "pool %d: %d of %d allocated\n",
 931                              new_pool->id, num, pkts_num);
 932                         return NULL;
 933                 }
 934         }
 935
 936         mvpp2_bm_pool_bufsize_set(port->priv, new_pool,
 937                                   MVPP2_RX_BUF_SIZE(new_pool->pkt_size));
 938
 939         return new_pool;
 940 }
 941
 942 /* Initialize pools for swf, shared buffers variant */
 943 static int mvpp2_swf_bm_pool_init_shared(struct mvpp2_port *port)
 944 {
 945         enum mvpp2_bm_pool_log_num long_log_pool, short_log_pool;
 946         int rxq;
 947
 948         /* If port pkt_size is higher than 1518B:
 949          * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool
 950          * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool
 951          */
 952         if (port->pkt_size > MVPP2_BM_LONG_PKT_SIZE) {
 953                 long_log_pool = MVPP2_BM_JUMBO;
 954                 short_log_pool = MVPP2_BM_LONG;
 955         } else {
 956                 long_log_pool = MVPP2_BM_LONG;
 957                 short_log_pool = MVPP2_BM_SHORT;
 958         }
 959
 960         if (!port->pool_long) {
 961                 port->pool_long =
 962                         mvpp2_bm_pool_use(port, long_log_pool,
 963                                           mvpp2_pools[long_log_pool].pkt_size);
 964                 if (!port->pool_long)
 965                         return -ENOMEM;
 966
 967                 port->pool_long->port_map |= BIT(port->id);
 968
 969                 for (rxq = 0; rxq < port->nrxqs; rxq++)
 970                         mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id);
 971         }
 972
 973         if (!port->pool_short) {
 974                 port->pool_short =
 975                         mvpp2_bm_pool_use(port, short_log_pool,
 976                                           mvpp2_pools[short_log_pool].pkt_size);
 977                 if (!port->pool_short)
 978                         return -ENOMEM;
 979
 980                 port->pool_short->port_map |= BIT(port->id);
 981
 982                 for (rxq = 0; rxq < port->nrxqs; rxq++)
 983                         mvpp2_rxq_short_pool_set(port, rxq,
 984                                                  port->pool_short->id);
 985         }
 986
 987         return 0;
 988 }
 989
 990 /* Initialize pools for swf, percpu buffers variant */
 991 static int mvpp2_swf_bm_pool_init_percpu(struct mvpp2_port *port)
 992 {
 993         struct mvpp2_bm_pool *bm_pool;
 994         int i;
 995
 996         for (i = 0; i < port->nrxqs; i++) {
 997                 bm_pool = mvpp2_bm_pool_use_percpu(port, MVPP2_BM_SHORT, i,
 998                                                    mvpp2_pools[MVPP2_BM_SHORT].pkt_size);
 999                 if (!bm_pool)
1000                         return -ENOMEM;
1001
1002                 bm_pool->port_map |= BIT(port->id);
1003                 mvpp2_rxq_short_pool_set(port, i, bm_pool->id);
1004         }
1005
1006         for (i = 0; i < port->nrxqs; i++) {
1007                 bm_pool = mvpp2_bm_pool_use_percpu(port, MVPP2_BM_LONG, i + port->nrxqs,
1008                                                    mvpp2_pools[MVPP2_BM_LONG].pkt_size);
1009                 if (!bm_pool)
1010                         return -ENOMEM;
1011
1012                 bm_pool->port_map |= BIT(port->id);
1013                 mvpp2_rxq_long_pool_set(port, i, bm_pool->id);
1014         }
1015
1016         port->pool_long = NULL;
1017         port->pool_short = NULL;
1018
1019         return 0;
1020 }
1021
1022 static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port)
1023 {
1024         if (port->priv->percpu_pools)
1025                 return mvpp2_swf_bm_pool_init_percpu(port);
1026         else
1027                 return mvpp2_swf_bm_pool_init_shared(port);
1028 }
1029
1030 static void mvpp2_set_hw_csum(struct mvpp2_port *port,
1031                               enum mvpp2_bm_pool_log_num new_long_pool)
1032 {
1033         const netdev_features_t csums = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1034
1035         /* Update L4 checksum when jumbo enable/disable on port.
1036          * Only port 0 supports hardware checksum offload due to
1037          * the Tx FIFO size limitation.
1038          * Also, don't set NETIF_F_HW_CSUM because L3_offset in TX descriptor
1039          * has 7 bits, so the maximum L3 offset is 128.
1040          */
1041         if (new_long_pool == MVPP2_BM_JUMBO && port->id != 0) {
1042                 port->dev->features &= ~csums;
1043                 port->dev->hw_features &= ~csums;
1044         } else {
1045                 port->dev->features |= csums;
1046                 port->dev->hw_features |= csums;
1047         }
1048 }
1049
1050 static int mvpp2_bm_update_mtu(struct net_device *dev, int mtu)
1051 {
1052         struct mvpp2_port *port = netdev_priv(dev);
1053         enum mvpp2_bm_pool_log_num new_long_pool;
1054         int pkt_size = MVPP2_RX_PKT_SIZE(mtu);
1055
1056         if (port->priv->percpu_pools)
1057                 goto out_set;
1058
1059         /* If port MTU is higher than 1518B:
1060          * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool
1061          * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool
1062          */
1063         if (pkt_size > MVPP2_BM_LONG_PKT_SIZE)
1064                 new_long_pool = MVPP2_BM_JUMBO;
1065         else
1066                 new_long_pool = MVPP2_BM_LONG;
1067
1068         if (new_long_pool != port->pool_long->id) {
1069                 /* Remove port from old short & long pool */
1070                 port->pool_long = mvpp2_bm_pool_use(port, port->pool_long->id,
1071                                                     port->pool_long->pkt_size);
1072                 port->pool_long->port_map &= ~BIT(port->id);
1073                 port->pool_long = NULL;
1074
1075                 port->pool_short = mvpp2_bm_pool_use(port, port->pool_short->id,
1076                                                      port->pool_short->pkt_size);
1077                 port->pool_short->port_map &= ~BIT(port->id);
1078                 port->pool_short = NULL;
1079
1080                 port->pkt_size =  pkt_size;
1081
1082                 /* Add port to new short & long pool */
1083                 mvpp2_swf_bm_pool_init(port);
1084
1085                 mvpp2_set_hw_csum(port, new_long_pool);
1086         }
1087
1088 out_set:
1089         dev->mtu = mtu;
1090         dev->wanted_features = dev->features;
1091
1092         netdev_update_features(dev);
1093         return 0;
1094 }
1095
1096 static inline void mvpp2_interrupts_enable(struct mvpp2_port *port)
1097 {
1098         int i, sw_thread_mask = 0;
1099
1100         for (i = 0; i < port->nqvecs; i++)
1101                 sw_thread_mask |= port->qvecs[i].sw_thread_mask;
1102
1103         mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
1104                     MVPP2_ISR_ENABLE_INTERRUPT(sw_thread_mask));
1105 }
1106
1107 static inline void mvpp2_interrupts_disable(struct mvpp2_port *port)
1108 {
1109         int i, sw_thread_mask = 0;
1110
1111         for (i = 0; i < port->nqvecs; i++)
1112                 sw_thread_mask |= port->qvecs[i].sw_thread_mask;
1113
1114         mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
1115                     MVPP2_ISR_DISABLE_INTERRUPT(sw_thread_mask));
1116 }
1117
1118 static inline void mvpp2_qvec_interrupt_enable(struct mvpp2_queue_vector *qvec)
1119 {
1120         struct mvpp2_port *port = qvec->port;
1121
1122         mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
1123                     MVPP2_ISR_ENABLE_INTERRUPT(qvec->sw_thread_mask));
1124 }
1125
1126 static inline void mvpp2_qvec_interrupt_disable(struct mvpp2_queue_vector *qvec)
1127 {
1128         struct mvpp2_port *port = qvec->port;
1129
1130         mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
1131                     MVPP2_ISR_DISABLE_INTERRUPT(qvec->sw_thread_mask));
1132 }
1133
1134 /* Mask the current thread's Rx/Tx interrupts
1135  * Called by on_each_cpu(), guaranteed to run with migration disabled,
1136  * using smp_processor_id() is OK.
1137  */
1138 static void mvpp2_interrupts_mask(void *arg)
1139 {
1140         struct mvpp2_port *port = arg;
1141
1142         /* If the thread isn't used, don't do anything */
1143         if (smp_processor_id() > port->priv->nthreads)
1144                 return;
1145
1146         mvpp2_thread_write(port->priv,
1147                            mvpp2_cpu_to_thread(port->priv, smp_processor_id()),
1148                            MVPP2_ISR_RX_TX_MASK_REG(port->id), 0);
1149 }
1150
1151 /* Unmask the current thread's Rx/Tx interrupts.
1152  * Called by on_each_cpu(), guaranteed to run with migration disabled,
1153  * using smp_processor_id() is OK.
1154  */
1155 static void mvpp2_interrupts_unmask(void *arg)
1156 {
1157         struct mvpp2_port *port = arg;
1158         u32 val;
1159
1160         /* If the thread isn't used, don't do anything */
1161         if (smp_processor_id() > port->priv->nthreads)
1162                 return;
1163
1164         val = MVPP2_CAUSE_MISC_SUM_MASK |
1165                 MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version);
1166         if (port->has_tx_irqs)
1167                 val |= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK;
1168
1169         mvpp2_thread_write(port->priv,
1170                            mvpp2_cpu_to_thread(port->priv, smp_processor_id()),
1171                            MVPP2_ISR_RX_TX_MASK_REG(port->id), val);
1172 }
1173
1174 static void
1175 mvpp2_shared_interrupt_mask_unmask(struct mvpp2_port *port, bool mask)
1176 {
1177         u32 val;
1178         int i;
1179
1180         if (port->priv->hw_version != MVPP22)
1181                 return;
1182
1183         if (mask)
1184                 val = 0;
1185         else
1186                 val = MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(MVPP22);
1187
1188         for (i = 0; i < port->nqvecs; i++) {
1189                 struct mvpp2_queue_vector *v = port->qvecs + i;
1190
1191                 if (v->type != MVPP2_QUEUE_VECTOR_SHARED)
1192                         continue;
1193
1194                 mvpp2_thread_write(port->priv, v->sw_thread_id,
1195                                    MVPP2_ISR_RX_TX_MASK_REG(port->id), val);
1196         }
1197 }
1198
1199 /* Only GOP port 0 has an XLG MAC */
1200 static bool mvpp2_port_supports_xlg(struct mvpp2_port *port)
1201 {
1202         return port->gop_id == 0;
1203 }
1204
1205 static bool mvpp2_port_supports_rgmii(struct mvpp2_port *port)
1206 {
1207         return !(port->priv->hw_version == MVPP22 && port->gop_id == 0);
1208 }
1209
1210 /* Port configuration routines */
1211 static bool mvpp2_is_xlg(phy_interface_t interface)
1212 {
1213         return interface == PHY_INTERFACE_MODE_10GBASER ||
1214                interface == PHY_INTERFACE_MODE_XAUI;
1215 }
1216
1217 static void mvpp2_modify(void __iomem *ptr, u32 mask, u32 set)
1218 {
1219         u32 old, val;
1220
1221         old = val = readl(ptr);
1222         val &= ~mask;
1223         val |= set;
1224         if (old != val)
1225                 writel(val, ptr);
1226 }
1227
1228 static void mvpp22_gop_init_rgmii(struct mvpp2_port *port)
1229 {
1230         struct mvpp2 *priv = port->priv;
1231         u32 val;
1232
1233         regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val);
1234         val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT;
1235         regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val);
1236
1237         regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val);
1238         if (port->gop_id == 2)
1239                 val |= GENCONF_CTRL0_PORT0_RGMII | GENCONF_CTRL0_PORT1_RGMII;
1240         else if (port->gop_id == 3)
1241                 val |= GENCONF_CTRL0_PORT1_RGMII_MII;
1242         regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val);
1243 }
1244
1245 static void mvpp22_gop_init_sgmii(struct mvpp2_port *port)
1246 {
1247         struct mvpp2 *priv = port->priv;
1248         u32 val;
1249
1250         regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val);
1251         val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT |
1252                GENCONF_PORT_CTRL0_RX_DATA_SAMPLE;
1253         regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val);
1254
1255         if (port->gop_id > 1) {
1256                 regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val);
1257                 if (port->gop_id == 2)
1258                         val &= ~GENCONF_CTRL0_PORT0_RGMII;
1259                 else if (port->gop_id == 3)
1260                         val &= ~GENCONF_CTRL0_PORT1_RGMII_MII;
1261                 regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val);
1262         }
1263 }
1264
1265 static void mvpp22_gop_init_10gkr(struct mvpp2_port *port)
1266 {
1267         struct mvpp2 *priv = port->priv;
1268         void __iomem *mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id);
1269         void __iomem *xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id);
1270         u32 val;
1271
1272         val = readl(xpcs + MVPP22_XPCS_CFG0);
1273         val &= ~(MVPP22_XPCS_CFG0_PCS_MODE(0x3) |
1274                  MVPP22_XPCS_CFG0_ACTIVE_LANE(0x3));
1275         val |= MVPP22_XPCS_CFG0_ACTIVE_LANE(2);
1276         writel(val, xpcs + MVPP22_XPCS_CFG0);
1277
1278         val = readl(mpcs + MVPP22_MPCS_CTRL);
1279         val &= ~MVPP22_MPCS_CTRL_FWD_ERR_CONN;
1280         writel(val, mpcs + MVPP22_MPCS_CTRL);
1281
1282         val = readl(mpcs + MVPP22_MPCS_CLK_RESET);
1283         val &= ~MVPP22_MPCS_CLK_RESET_DIV_RATIO(0x7);
1284         val |= MVPP22_MPCS_CLK_RESET_DIV_RATIO(1);
1285         writel(val, mpcs + MVPP22_MPCS_CLK_RESET);
1286 }
1287
1288 static int mvpp22_gop_init(struct mvpp2_port *port)
1289 {
1290         struct mvpp2 *priv = port->priv;
1291         u32 val;
1292
1293         if (!priv->sysctrl_base)
1294                 return 0;
1295
1296         switch (port->phy_interface) {
1297         case PHY_INTERFACE_MODE_RGMII:
1298         case PHY_INTERFACE_MODE_RGMII_ID:
1299         case PHY_INTERFACE_MODE_RGMII_RXID:
1300         case PHY_INTERFACE_MODE_RGMII_TXID:
1301                 if (!mvpp2_port_supports_rgmii(port))
1302                         goto invalid_conf;
1303                 mvpp22_gop_init_rgmii(port);
1304                 break;
1305         case PHY_INTERFACE_MODE_SGMII:
1306         case PHY_INTERFACE_MODE_1000BASEX:
1307         case PHY_INTERFACE_MODE_2500BASEX:
1308                 mvpp22_gop_init_sgmii(port);
1309                 break;
1310         case PHY_INTERFACE_MODE_10GBASER:
1311                 if (!mvpp2_port_supports_xlg(port))
1312                         goto invalid_conf;
1313                 mvpp22_gop_init_10gkr(port);
1314                 break;
1315         default:
1316                 goto unsupported_conf;
1317         }
1318
1319         regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL1, &val);
1320         val |= GENCONF_PORT_CTRL1_RESET(port->gop_id) |
1321                GENCONF_PORT_CTRL1_EN(port->gop_id);
1322         regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL1, val);
1323
1324         regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val);
1325         val |= GENCONF_PORT_CTRL0_CLK_DIV_PHASE_CLR;
1326         regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val);
1327
1328         regmap_read(priv->sysctrl_base, GENCONF_SOFT_RESET1, &val);
1329         val |= GENCONF_SOFT_RESET1_GOP;
1330         regmap_write(priv->sysctrl_base, GENCONF_SOFT_RESET1, val);
1331
1332 unsupported_conf:
1333         return 0;
1334
1335 invalid_conf:
1336         netdev_err(port->dev, "Invalid port configuration\n");
1337         return -EINVAL;
1338 }
1339
1340 static void mvpp22_gop_unmask_irq(struct mvpp2_port *port)
1341 {
1342         u32 val;
1343
1344         if (phy_interface_mode_is_rgmii(port->phy_interface) ||
1345             phy_interface_mode_is_8023z(port->phy_interface) ||
1346             port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
1347                 /* Enable the GMAC link status irq for this port */
1348                 val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK);
1349                 val |= MVPP22_GMAC_INT_SUM_MASK_LINK_STAT;
1350                 writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK);
1351         }
1352
1353         if (mvpp2_port_supports_xlg(port)) {
1354                 /* Enable the XLG/GIG irqs for this port */
1355                 val = readl(port->base + MVPP22_XLG_EXT_INT_MASK);
1356                 if (mvpp2_is_xlg(port->phy_interface))
1357                         val |= MVPP22_XLG_EXT_INT_MASK_XLG;
1358                 else
1359                         val |= MVPP22_XLG_EXT_INT_MASK_GIG;
1360                 writel(val, port->base + MVPP22_XLG_EXT_INT_MASK);
1361         }
1362 }
1363
1364 static void mvpp22_gop_mask_irq(struct mvpp2_port *port)
1365 {
1366         u32 val;
1367
1368         if (mvpp2_port_supports_xlg(port)) {
1369                 val = readl(port->base + MVPP22_XLG_EXT_INT_MASK);
1370                 val &= ~(MVPP22_XLG_EXT_INT_MASK_XLG |
1371                          MVPP22_XLG_EXT_INT_MASK_GIG);
1372                 writel(val, port->base + MVPP22_XLG_EXT_INT_MASK);
1373         }
1374
1375         if (phy_interface_mode_is_rgmii(port->phy_interface) ||
1376             phy_interface_mode_is_8023z(port->phy_interface) ||
1377             port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
1378                 val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK);
1379                 val &= ~MVPP22_GMAC_INT_SUM_MASK_LINK_STAT;
1380                 writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK);
1381         }
1382 }
1383
1384 static void mvpp22_gop_setup_irq(struct mvpp2_port *port)
1385 {
1386         u32 val;
1387
1388         if (port->phylink ||
1389             phy_interface_mode_is_rgmii(port->phy_interface) ||
1390             phy_interface_mode_is_8023z(port->phy_interface) ||
1391             port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
1392                 val = readl(port->base + MVPP22_GMAC_INT_MASK);
1393                 val |= MVPP22_GMAC_INT_MASK_LINK_STAT;
1394                 writel(val, port->base + MVPP22_GMAC_INT_MASK);
1395         }
1396
1397         if (mvpp2_port_supports_xlg(port)) {
1398                 val = readl(port->base + MVPP22_XLG_INT_MASK);
1399                 val |= MVPP22_XLG_INT_MASK_LINK;
1400                 writel(val, port->base + MVPP22_XLG_INT_MASK);
1401         }
1402
1403         mvpp22_gop_unmask_irq(port);
1404 }
1405
1406 /* Sets the PHY mode of the COMPHY (which configures the serdes lanes).
1407  *
1408  * The PHY mode used by the PPv2 driver comes from the network subsystem, while
1409  * the one given to the COMPHY comes from the generic PHY subsystem. Hence they
1410  * differ.
1411  *
1412  * The COMPHY configures the serdes lanes regardless of the actual use of the
1413  * lanes by the physical layer. This is why configurations like
1414  * "PPv2 (2500BaseX) - COMPHY (2500SGMII)" are valid.
1415  */
1416 static int mvpp22_comphy_init(struct mvpp2_port *port)
1417 {
1418         int ret;
1419
1420         if (!port->comphy)
1421                 return 0;
1422
1423         ret = phy_set_mode_ext(port->comphy, PHY_MODE_ETHERNET,
1424                                port->phy_interface);
1425         if (ret)
1426                 return ret;
1427
1428         return phy_power_on(port->comphy);
1429 }
1430
1431 static void mvpp2_port_enable(struct mvpp2_port *port)
1432 {
1433         u32 val;
1434
1435         if (mvpp2_port_supports_xlg(port) &&
1436             mvpp2_is_xlg(port->phy_interface)) {
1437                 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
1438                 val |= MVPP22_XLG_CTRL0_PORT_EN;
1439                 val &= ~MVPP22_XLG_CTRL0_MIB_CNT_DIS;
1440                 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
1441         } else {
1442                 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
1443                 val |= MVPP2_GMAC_PORT_EN_MASK;
1444                 val |= MVPP2_GMAC_MIB_CNTR_EN_MASK;
1445                 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
1446         }
1447 }
1448
1449 static void mvpp2_port_disable(struct mvpp2_port *port)
1450 {
1451         u32 val;
1452
1453         if (mvpp2_port_supports_xlg(port) &&
1454             mvpp2_is_xlg(port->phy_interface)) {
1455                 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
1456                 val &= ~MVPP22_XLG_CTRL0_PORT_EN;
1457                 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
1458         }
1459
1460         val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
1461         val &= ~(MVPP2_GMAC_PORT_EN_MASK);
1462         writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
1463 }
1464
1465 /* Set IEEE 802.3x Flow Control Xon Packet Transmission Mode */
1466 static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port)
1467 {
1468         u32 val;
1469
1470         val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) &
1471                     ~MVPP2_GMAC_PERIODIC_XON_EN_MASK;
1472         writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
1473 }
1474
1475 /* Configure loopback port */
1476 static void mvpp2_port_loopback_set(struct mvpp2_port *port,
1477                                     const struct phylink_link_state *state)
1478 {
1479         u32 val;
1480
1481         val = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
1482
1483         if (state->speed == 1000)
1484                 val |= MVPP2_GMAC_GMII_LB_EN_MASK;
1485         else
1486                 val &= ~MVPP2_GMAC_GMII_LB_EN_MASK;
1487
1488         if (phy_interface_mode_is_8023z(port->phy_interface) ||
1489             port->phy_interface == PHY_INTERFACE_MODE_SGMII)
1490                 val |= MVPP2_GMAC_PCS_LB_EN_MASK;
1491         else
1492                 val &= ~MVPP2_GMAC_PCS_LB_EN_MASK;
1493
1494         writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
1495 }
1496
1497 enum {
1498         ETHTOOL_XDP_REDIRECT,
1499         ETHTOOL_XDP_PASS,
1500         ETHTOOL_XDP_DROP,
1501         ETHTOOL_XDP_TX,
1502         ETHTOOL_XDP_TX_ERR,
1503         ETHTOOL_XDP_XMIT,
1504         ETHTOOL_XDP_XMIT_ERR,
1505 };
1506
1507 struct mvpp2_ethtool_counter {
1508         unsigned int offset;
1509         const char string[ETH_GSTRING_LEN];
1510         bool reg_is_64b;
1511 };
1512
1513 static u64 mvpp2_read_count(struct mvpp2_port *port,
1514                             const struct mvpp2_ethtool_counter *counter)
1515 {
1516         u64 val;
1517
1518         val = readl(port->stats_base + counter->offset);
1519         if (counter->reg_is_64b)
1520                 val += (u64)readl(port->stats_base + counter->offset + 4) << 32;
1521
1522         return val;
1523 }
1524
1525 /* Some counters are accessed indirectly by first writing an index to
1526  * MVPP2_CTRS_IDX. The index can represent various resources depending on the
1527  * register we access, it can be a hit counter for some classification tables,
1528  * a counter specific to a rxq, a txq or a buffer pool.
1529  */
1530 static u32 mvpp2_read_index(struct mvpp2 *priv, u32 index, u32 reg)
1531 {
1532         mvpp2_write(priv, MVPP2_CTRS_IDX, index);
1533         return mvpp2_read(priv, reg);
1534 }
1535
1536 /* Due to the fact that software statistics and hardware statistics are, by
1537  * design, incremented at different moments in the chain of packet processing,
1538  * it is very likely that incoming packets could have been dropped after being
1539  * counted by hardware but before reaching software statistics (most probably
1540  * multicast packets), and in the oppposite way, during transmission, FCS bytes
1541  * are added in between as well as TSO skb will be split and header bytes added.
1542  * Hence, statistics gathered from userspace with ifconfig (software) and
1543  * ethtool (hardware) cannot be compared.
1544  */
1545 static const struct mvpp2_ethtool_counter mvpp2_ethtool_mib_regs[] = {
1546         { MVPP2_MIB_GOOD_OCTETS_RCVD, "good_octets_received", true },
1547         { MVPP2_MIB_BAD_OCTETS_RCVD, "bad_octets_received" },
1548         { MVPP2_MIB_CRC_ERRORS_SENT, "crc_errors_sent" },
1549         { MVPP2_MIB_UNICAST_FRAMES_RCVD, "unicast_frames_received" },
1550         { MVPP2_MIB_BROADCAST_FRAMES_RCVD, "broadcast_frames_received" },
1551         { MVPP2_MIB_MULTICAST_FRAMES_RCVD, "multicast_frames_received" },
1552         { MVPP2_MIB_FRAMES_64_OCTETS, "frames_64_octets" },
1553         { MVPP2_MIB_FRAMES_65_TO_127_OCTETS, "frames_65_to_127_octet" },
1554         { MVPP2_MIB_FRAMES_128_TO_255_OCTETS, "frames_128_to_255_octet" },
1555         { MVPP2_MIB_FRAMES_256_TO_511_OCTETS, "frames_256_to_511_octet" },
1556         { MVPP2_MIB_FRAMES_512_TO_1023_OCTETS, "frames_512_to_1023_octet" },
1557         { MVPP2_MIB_FRAMES_1024_TO_MAX_OCTETS, "frames_1024_to_max_octet" },
1558         { MVPP2_MIB_GOOD_OCTETS_SENT, "good_octets_sent", true },
1559         { MVPP2_MIB_UNICAST_FRAMES_SENT, "unicast_frames_sent" },
1560         { MVPP2_MIB_MULTICAST_FRAMES_SENT, "multicast_frames_sent" },
1561         { MVPP2_MIB_BROADCAST_FRAMES_SENT, "broadcast_frames_sent" },
1562         { MVPP2_MIB_FC_SENT, "fc_sent" },
1563         { MVPP2_MIB_FC_RCVD, "fc_received" },
1564         { MVPP2_MIB_RX_FIFO_OVERRUN, "rx_fifo_overrun" },
1565         { MVPP2_MIB_UNDERSIZE_RCVD, "undersize_received" },
1566         { MVPP2_MIB_FRAGMENTS_RCVD, "fragments_received" },
1567         { MVPP2_MIB_OVERSIZE_RCVD, "oversize_received" },
1568         { MVPP2_MIB_JABBER_RCVD, "jabber_received" },
1569         { MVPP2_MIB_MAC_RCV_ERROR, "mac_receive_error" },
1570         { MVPP2_MIB_BAD_CRC_EVENT, "bad_crc_event" },
1571         { MVPP2_MIB_COLLISION, "collision" },
1572         { MVPP2_MIB_LATE_COLLISION, "late_collision" },
1573 };
1574
1575 static const struct mvpp2_ethtool_counter mvpp2_ethtool_port_regs[] = {
1576         { MVPP2_OVERRUN_ETH_DROP, "rx_fifo_or_parser_overrun_drops" },
1577         { MVPP2_CLS_ETH_DROP, "rx_classifier_drops" },
1578 };
1579
1580 static const struct mvpp2_ethtool_counter mvpp2_ethtool_txq_regs[] = {
1581         { MVPP2_TX_DESC_ENQ_CTR, "txq_%d_desc_enqueue" },
1582         { MVPP2_TX_DESC_ENQ_TO_DDR_CTR, "txq_%d_desc_enqueue_to_ddr" },
1583         { MVPP2_TX_BUFF_ENQ_TO_DDR_CTR, "txq_%d_buff_euqueue_to_ddr" },
1584         { MVPP2_TX_DESC_ENQ_HW_FWD_CTR, "txq_%d_desc_hardware_forwarded" },
1585         { MVPP2_TX_PKTS_DEQ_CTR, "txq_%d_packets_dequeued" },
1586         { MVPP2_TX_PKTS_FULL_QUEUE_DROP_CTR, "txq_%d_queue_full_drops" },
1587         { MVPP2_TX_PKTS_EARLY_DROP_CTR, "txq_%d_packets_early_drops" },
1588         { MVPP2_TX_PKTS_BM_DROP_CTR, "txq_%d_packets_bm_drops" },
1589         { MVPP2_TX_PKTS_BM_MC_DROP_CTR, "txq_%d_packets_rep_bm_drops" },
1590 };
1591
1592 static const struct mvpp2_ethtool_counter mvpp2_ethtool_rxq_regs[] = {
1593         { MVPP2_RX_DESC_ENQ_CTR, "rxq_%d_desc_enqueue" },
1594         { MVPP2_RX_PKTS_FULL_QUEUE_DROP_CTR, "rxq_%d_queue_full_drops" },
1595         { MVPP2_RX_PKTS_EARLY_DROP_CTR, "rxq_%d_packets_early_drops" },
1596         { MVPP2_RX_PKTS_BM_DROP_CTR, "rxq_%d_packets_bm_drops" },
1597 };
1598
1599 static const struct mvpp2_ethtool_counter mvpp2_ethtool_xdp[] = {
1600         { ETHTOOL_XDP_REDIRECT, "rx_xdp_redirect", },
1601         { ETHTOOL_XDP_PASS, "rx_xdp_pass", },
1602         { ETHTOOL_XDP_DROP, "rx_xdp_drop", },
1603         { ETHTOOL_XDP_TX, "rx_xdp_tx", },
1604         { ETHTOOL_XDP_TX_ERR, "rx_xdp_tx_errors", },
1605         { ETHTOOL_XDP_XMIT, "tx_xdp_xmit", },
1606         { ETHTOOL_XDP_XMIT_ERR, "tx_xdp_xmit_errors", },
1607 };
1608
1609 #define MVPP2_N_ETHTOOL_STATS(ntxqs, nrxqs)     (ARRAY_SIZE(mvpp2_ethtool_mib_regs) + \
1610                                                  ARRAY_SIZE(mvpp2_ethtool_port_regs) + \
1611                                                  (ARRAY_SIZE(mvpp2_ethtool_txq_regs) * (ntxqs)) + \
1612                                                  (ARRAY_SIZE(mvpp2_ethtool_rxq_regs) * (nrxqs)) + \
1613                                                  ARRAY_SIZE(mvpp2_ethtool_xdp))
1614
1615 static void mvpp2_ethtool_get_strings(struct net_device *netdev, u32 sset,
1616                                       u8 *data)
1617 {
1618         struct mvpp2_port *port = netdev_priv(netdev);
1619         int i, q;
1620
1621         if (sset != ETH_SS_STATS)
1622                 return;
1623
1624         for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_mib_regs); i++) {
1625                 strscpy(data, mvpp2_ethtool_mib_regs[i].string,
1626                         ETH_GSTRING_LEN);
1627                 data += ETH_GSTRING_LEN;
1628         }
1629
1630         for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_port_regs); i++) {
1631                 strscpy(data, mvpp2_ethtool_port_regs[i].string,
1632                         ETH_GSTRING_LEN);
1633                 data += ETH_GSTRING_LEN;
1634         }
1635
1636         for (q = 0; q < port->ntxqs; q++) {
1637                 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_txq_regs); i++) {
1638                         snprintf(data, ETH_GSTRING_LEN,
1639                                  mvpp2_ethtool_txq_regs[i].string, q);
1640                         data += ETH_GSTRING_LEN;
1641                 }
1642         }
1643
1644         for (q = 0; q < port->nrxqs; q++) {
1645                 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_rxq_regs); i++) {
1646                         snprintf(data, ETH_GSTRING_LEN,
1647                                  mvpp2_ethtool_rxq_regs[i].string,
1648                                  q);
1649                         data += ETH_GSTRING_LEN;
1650                 }
1651         }
1652
1653         for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_xdp); i++) {
1654                 strscpy(data, mvpp2_ethtool_xdp[i].string,
1655                         ETH_GSTRING_LEN);
1656                 data += ETH_GSTRING_LEN;
1657         }
1658 }
1659
1660 static void
1661 mvpp2_get_xdp_stats(struct mvpp2_port *port, struct mvpp2_pcpu_stats *xdp_stats)
1662 {
1663         unsigned int start;
1664         unsigned int cpu;
1665
1666         /* Gather XDP Statistics */
1667         for_each_possible_cpu(cpu) {
1668                 struct mvpp2_pcpu_stats *cpu_stats;
1669                 u64     xdp_redirect;
1670                 u64     xdp_pass;
1671                 u64     xdp_drop;
1672                 u64     xdp_xmit;
1673                 u64     xdp_xmit_err;
1674                 u64     xdp_tx;
1675                 u64     xdp_tx_err;
1676
1677                 cpu_stats = per_cpu_ptr(port->stats, cpu);
1678                 do {
1679                         start = u64_stats_fetch_begin_irq(&cpu_stats->syncp);
1680                         xdp_redirect = cpu_stats->xdp_redirect;
1681                         xdp_pass   = cpu_stats->xdp_pass;
1682                         xdp_drop = cpu_stats->xdp_drop;
1683                         xdp_xmit   = cpu_stats->xdp_xmit;
1684                         xdp_xmit_err   = cpu_stats->xdp_xmit_err;
1685                         xdp_tx   = cpu_stats->xdp_tx;
1686                         xdp_tx_err   = cpu_stats->xdp_tx_err;
1687                 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start));
1688
1689                 xdp_stats->xdp_redirect += xdp_redirect;
1690                 xdp_stats->xdp_pass   += xdp_pass;
1691                 xdp_stats->xdp_drop += xdp_drop;
1692                 xdp_stats->xdp_xmit   += xdp_xmit;
1693                 xdp_stats->xdp_xmit_err   += xdp_xmit_err;
1694                 xdp_stats->xdp_tx   += xdp_tx;
1695                 xdp_stats->xdp_tx_err   += xdp_tx_err;
1696         }
1697 }
1698
1699 static void mvpp2_read_stats(struct mvpp2_port *port)
1700 {
1701         struct mvpp2_pcpu_stats xdp_stats = {};
1702         const struct mvpp2_ethtool_counter *s;
1703         u64 *pstats;
1704         int i, q;
1705
1706         pstats = port->ethtool_stats;
1707
1708         for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_mib_regs); i++)
1709                 *pstats++ += mvpp2_read_count(port, &mvpp2_ethtool_mib_regs[i]);
1710
1711         for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_port_regs); i++)
1712                 *pstats++ += mvpp2_read(port->priv,
1713                                         mvpp2_ethtool_port_regs[i].offset +
1714                                         4 * port->id);
1715
1716         for (q = 0; q < port->ntxqs; q++)
1717                 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_txq_regs); i++)
1718                         *pstats++ += mvpp2_read_index(port->priv,
1719                                                       MVPP22_CTRS_TX_CTR(port->id, q),
1720                                                       mvpp2_ethtool_txq_regs[i].offset);
1721
1722         /* Rxqs are numbered from 0 from the user standpoint, but not from the
1723          * driver's. We need to add the  port->first_rxq offset.
1724          */
1725         for (q = 0; q < port->nrxqs; q++)
1726                 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_rxq_regs); i++)
1727                         *pstats++ += mvpp2_read_index(port->priv,
1728                                                       port->first_rxq + q,
1729                                                       mvpp2_ethtool_rxq_regs[i].offset);
1730
1731         /* Gather XDP Statistics */
1732         mvpp2_get_xdp_stats(port, &xdp_stats);
1733
1734         for (i = 0, s = mvpp2_ethtool_xdp;
1735                  s < mvpp2_ethtool_xdp + ARRAY_SIZE(mvpp2_ethtool_xdp);
1736              s++, i++) {
1737                 switch (s->offset) {
1738                 case ETHTOOL_XDP_REDIRECT:
1739                         *pstats++ = xdp_stats.xdp_redirect;
1740                         break;
1741                 case ETHTOOL_XDP_PASS:
1742                         *pstats++ = xdp_stats.xdp_pass;
1743                         break;
1744                 case ETHTOOL_XDP_DROP:
1745                         *pstats++ = xdp_stats.xdp_drop;
1746                         break;
1747                 case ETHTOOL_XDP_TX:
1748                         *pstats++ = xdp_stats.xdp_tx;
1749                         break;
1750                 case ETHTOOL_XDP_TX_ERR:
1751                         *pstats++ = xdp_stats.xdp_tx_err;
1752                         break;
1753                 case ETHTOOL_XDP_XMIT:
1754                         *pstats++ = xdp_stats.xdp_xmit;
1755                         break;
1756                 case ETHTOOL_XDP_XMIT_ERR:
1757                         *pstats++ = xdp_stats.xdp_xmit_err;
1758                         break;
1759                 }
1760         }
1761 }
1762
1763 static void mvpp2_gather_hw_statistics(struct work_struct *work)
1764 {
1765         struct delayed_work *del_work = to_delayed_work(work);
1766         struct mvpp2_port *port = container_of(del_work, struct mvpp2_port,
1767                                                stats_work);
1768
1769         mutex_lock(&port->gather_stats_lock);
1770
1771         mvpp2_read_stats(port);
1772
1773         /* No need to read again the counters right after this function if it
1774          * was called asynchronously by the user (ie. use of ethtool).
1775          */
1776         cancel_delayed_work(&port->stats_work);
1777         queue_delayed_work(port->priv->stats_queue, &port->stats_work,
1778                            MVPP2_MIB_COUNTERS_STATS_DELAY);
1779
1780         mutex_unlock(&port->gather_stats_lock);
1781 }
1782
1783 static void mvpp2_ethtool_get_stats(struct net_device *dev,
1784                                     struct ethtool_stats *stats, u64 *data)
1785 {
1786         struct mvpp2_port *port = netdev_priv(dev);
1787
1788         /* Update statistics for the given port, then take the lock to avoid
1789          * concurrent accesses on the ethtool_stats structure during its copy.
1790          */
1791         mvpp2_gather_hw_statistics(&port->stats_work.work);
1792
1793         mutex_lock(&port->gather_stats_lock);
1794         memcpy(data, port->ethtool_stats,
1795                sizeof(u64) * MVPP2_N_ETHTOOL_STATS(port->ntxqs, port->nrxqs));
1796         mutex_unlock(&port->gather_stats_lock);
1797 }
1798
1799 static int mvpp2_ethtool_get_sset_count(struct net_device *dev, int sset)
1800 {
1801         struct mvpp2_port *port = netdev_priv(dev);
1802
1803         if (sset == ETH_SS_STATS)
1804                 return MVPP2_N_ETHTOOL_STATS(port->ntxqs, port->nrxqs);
1805
1806         return -EOPNOTSUPP;
1807 }
1808
1809 static void mvpp2_mac_reset_assert(struct mvpp2_port *port)
1810 {
1811         u32 val;
1812
1813         val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) |
1814               MVPP2_GMAC_PORT_RESET_MASK;
1815         writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
1816
1817         if (port->priv->hw_version == MVPP22 && port->gop_id == 0) {
1818                 val = readl(port->base + MVPP22_XLG_CTRL0_REG) &
1819                       ~MVPP22_XLG_CTRL0_MAC_RESET_DIS;
1820                 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
1821         }
1822 }
1823
1824 static void mvpp22_pcs_reset_assert(struct mvpp2_port *port)
1825 {
1826         struct mvpp2 *priv = port->priv;
1827         void __iomem *mpcs, *xpcs;
1828         u32 val;
1829
1830         if (port->priv->hw_version != MVPP22 || port->gop_id != 0)
1831                 return;
1832
1833         mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id);
1834         xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id);
1835
1836         val = readl(mpcs + MVPP22_MPCS_CLK_RESET);
1837         val &= ~(MAC_CLK_RESET_MAC | MAC_CLK_RESET_SD_RX | MAC_CLK_RESET_SD_TX);
1838         val |= MVPP22_MPCS_CLK_RESET_DIV_SET;
1839         writel(val, mpcs + MVPP22_MPCS_CLK_RESET);
1840
1841         val = readl(xpcs + MVPP22_XPCS_CFG0);
1842         writel(val & ~MVPP22_XPCS_CFG0_RESET_DIS, xpcs + MVPP22_XPCS_CFG0);
1843 }
1844
1845 static void mvpp22_pcs_reset_deassert(struct mvpp2_port *port)
1846 {
1847         struct mvpp2 *priv = port->priv;
1848         void __iomem *mpcs, *xpcs;
1849         u32 val;
1850
1851         if (port->priv->hw_version != MVPP22 || port->gop_id != 0)
1852                 return;
1853
1854         mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id);
1855         xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id);
1856
1857         switch (port->phy_interface) {
1858         case PHY_INTERFACE_MODE_10GBASER:
1859                 val = readl(mpcs + MVPP22_MPCS_CLK_RESET);
1860                 val |= MAC_CLK_RESET_MAC | MAC_CLK_RESET_SD_RX |
1861                        MAC_CLK_RESET_SD_TX;
1862                 val &= ~MVPP22_MPCS_CLK_RESET_DIV_SET;
1863                 writel(val, mpcs + MVPP22_MPCS_CLK_RESET);
1864                 break;
1865         case PHY_INTERFACE_MODE_XAUI:
1866         case PHY_INTERFACE_MODE_RXAUI:
1867                 val = readl(xpcs + MVPP22_XPCS_CFG0);
1868                 writel(val | MVPP22_XPCS_CFG0_RESET_DIS, xpcs + MVPP22_XPCS_CFG0);
1869                 break;
1870         default:
1871                 break;
1872         }
1873 }
1874
1875 /* Change maximum receive size of the port */
1876 static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port)
1877 {
1878         u32 val;
1879
1880         val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
1881         val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK;
1882         val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) <<
1883                     MVPP2_GMAC_MAX_RX_SIZE_OFFS);
1884         writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
1885 }
1886
1887 /* Change maximum receive size of the port */
1888 static inline void mvpp2_xlg_max_rx_size_set(struct mvpp2_port *port)
1889 {
1890         u32 val;
1891
1892         val =  readl(port->base + MVPP22_XLG_CTRL1_REG);
1893         val &= ~MVPP22_XLG_CTRL1_FRAMESIZELIMIT_MASK;
1894         val |= ((port->pkt_size - MVPP2_MH_SIZE) / 2) <<
1895                MVPP22_XLG_CTRL1_FRAMESIZELIMIT_OFFS;
1896         writel(val, port->base + MVPP22_XLG_CTRL1_REG);
1897 }
1898
1899 /* Set defaults to the MVPP2 port */
1900 static void mvpp2_defaults_set(struct mvpp2_port *port)
1901 {
1902         int tx_port_num, val, queue, lrxq;
1903
1904         if (port->priv->hw_version == MVPP21) {
1905                 /* Update TX FIFO MIN Threshold */
1906                 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
1907                 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
1908                 /* Min. TX threshold must be less than minimal packet length */
1909                 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2);
1910                 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
1911         }
1912
1913         /* Disable Legacy WRR, Disable EJP, Release from reset */
1914         tx_port_num = mvpp2_egress_port(port);
1915         mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG,
1916                     tx_port_num);
1917         mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0);
1918
1919         /* Set TXQ scheduling to Round-Robin */
1920         mvpp2_write(port->priv, MVPP2_TXP_SCHED_FIXED_PRIO_REG, 0);
1921
1922         /* Close bandwidth for all queues */
1923         for (queue = 0; queue < MVPP2_MAX_TXQ; queue++)
1924                 mvpp2_write(port->priv,
1925                             MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(queue), 0);
1926
1927         /* Set refill period to 1 usec, refill tokens
1928          * and bucket size to maximum
1929          */
1930         mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG,
1931                     port->priv->tclk / USEC_PER_SEC);
1932         val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG);
1933         val &= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK;
1934         val |= MVPP2_TXP_REFILL_PERIOD_MASK(1);
1935         val |= MVPP2_TXP_REFILL_TOKENS_ALL_MASK;
1936         mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val);
1937         val = MVPP2_TXP_TOKEN_SIZE_MAX;
1938         mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
1939
1940         /* Set MaximumLowLatencyPacketSize value to 256 */
1941         mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id),
1942                     MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK |
1943                     MVPP2_RX_LOW_LATENCY_PKT_SIZE(256));
1944
1945         /* Enable Rx cache snoop */
1946         for (lrxq = 0; lrxq < port->nrxqs; lrxq++) {
1947                 queue = port->rxqs[lrxq]->id;
1948                 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
1949                 val |= MVPP2_SNOOP_PKT_SIZE_MASK |
1950                            MVPP2_SNOOP_BUF_HDR_MASK;
1951                 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
1952         }
1953
1954         /* At default, mask all interrupts to all present cpus */
1955         mvpp2_interrupts_disable(port);
1956 }
1957
1958 /* Enable/disable receiving packets */
1959 static void mvpp2_ingress_enable(struct mvpp2_port *port)
1960 {
1961         u32 val;
1962         int lrxq, queue;
1963
1964         for (lrxq = 0; lrxq < port->nrxqs; lrxq++) {
1965                 queue = port->rxqs[lrxq]->id;
1966                 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
1967                 val &= ~MVPP2_RXQ_DISABLE_MASK;
1968                 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
1969         }
1970 }
1971
1972 static void mvpp2_ingress_disable(struct mvpp2_port *port)
1973 {
1974         u32 val;
1975         int lrxq, queue;
1976
1977         for (lrxq = 0; lrxq < port->nrxqs; lrxq++) {
1978                 queue = port->rxqs[lrxq]->id;
1979                 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
1980                 val |= MVPP2_RXQ_DISABLE_MASK;
1981                 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
1982         }
1983 }
1984
1985 /* Enable transmit via physical egress queue
1986  * - HW starts take descriptors from DRAM
1987  */
1988 static void mvpp2_egress_enable(struct mvpp2_port *port)
1989 {
1990         u32 qmap;
1991         int queue;
1992         int tx_port_num = mvpp2_egress_port(port);
1993
1994         /* Enable all initialized TXs. */
1995         qmap = 0;
1996         for (queue = 0; queue < port->ntxqs; queue++) {
1997                 struct mvpp2_tx_queue *txq = port->txqs[queue];
1998
1999                 if (txq->descs)
2000                         qmap |= (1 << queue);
2001         }
2002
2003         mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
2004         mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap);
2005 }
2006
2007 /* Disable transmit via physical egress queue
2008  * - HW doesn't take descriptors from DRAM
2009  */
2010 static void mvpp2_egress_disable(struct mvpp2_port *port)
2011 {
2012         u32 reg_data;
2013         int delay;
2014         int tx_port_num = mvpp2_egress_port(port);
2015
2016         /* Issue stop command for active channels only */
2017         mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
2018         reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) &
2019                     MVPP2_TXP_SCHED_ENQ_MASK;
2020         if (reg_data != 0)
2021                 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG,
2022                             (reg_data << MVPP2_TXP_SCHED_DISQ_OFFSET));
2023
2024         /* Wait for all Tx activity to terminate. */
2025         delay = 0;
2026         do {
2027                 if (delay >= MVPP2_TX_DISABLE_TIMEOUT_MSEC) {
2028                         netdev_warn(port->dev,
2029                                     "Tx stop timed out, status=0x%08x\n",
2030                                     reg_data);
2031                         break;
2032                 }
2033                 mdelay(1);
2034                 delay++;
2035
2036                 /* Check port TX Command register that all
2037                  * Tx queues are stopped
2038                  */
2039                 reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG);
2040         } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK);
2041 }
2042
2043 /* Rx descriptors helper methods */
2044
2045 /* Get number of Rx descriptors occupied by received packets */
2046 static inline int
2047 mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id)
2048 {
2049         u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id));
2050
2051         return val & MVPP2_RXQ_OCCUPIED_MASK;
2052 }
2053
2054 /* Update Rx queue status with the number of occupied and available
2055  * Rx descriptor slots.
2056  */
2057 static inline void
2058 mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id,
2059                         int used_count, int free_count)
2060 {
2061         /* Decrement the number of used descriptors and increment count
2062          * increment the number of free descriptors.
2063          */
2064         u32 val = used_count | (free_count << MVPP2_RXQ_NUM_NEW_OFFSET);
2065
2066         mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val);
2067 }
2068
2069 /* Get pointer to next RX descriptor to be processed by SW */
2070 static inline struct mvpp2_rx_desc *
2071 mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue *rxq)
2072 {
2073         int rx_desc = rxq->next_desc_to_proc;
2074
2075         rxq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(rxq, rx_desc);
2076         prefetch(rxq->descs + rxq->next_desc_to_proc);
2077         return rxq->descs + rx_desc;
2078 }
2079
2080 /* Set rx queue offset */
2081 static void mvpp2_rxq_offset_set(struct mvpp2_port *port,
2082                                  int prxq, int offset)
2083 {
2084         u32 val;
2085
2086         /* Convert offset from bytes to units of 32 bytes */
2087         offset = offset >> 5;
2088
2089         val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
2090         val &= ~MVPP2_RXQ_PACKET_OFFSET_MASK;
2091
2092         /* Offset is in */
2093         val |= ((offset << MVPP2_RXQ_PACKET_OFFSET_OFFS) &
2094                     MVPP2_RXQ_PACKET_OFFSET_MASK);
2095
2096         mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
2097 }
2098
2099 /* Tx descriptors helper methods */
2100
2101 /* Get pointer to next Tx descriptor to be processed (send) by HW */
2102 static struct mvpp2_tx_desc *
2103 mvpp2_txq_next_desc_get(struct mvpp2_tx_queue *txq)
2104 {
2105         int tx_desc = txq->next_desc_to_proc;
2106
2107         txq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(txq, tx_desc);
2108         return txq->descs + tx_desc;
2109 }
2110
2111 /* Update HW with number of aggregated Tx descriptors to be sent
2112  *
2113  * Called only from mvpp2_tx(), so migration is disabled, using
2114  * smp_processor_id() is OK.
2115  */
2116 static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending)
2117 {
2118         /* aggregated access - relevant TXQ number is written in TX desc */
2119         mvpp2_thread_write(port->priv,
2120                            mvpp2_cpu_to_thread(port->priv, smp_processor_id()),
2121                            MVPP2_AGGR_TXQ_UPDATE_REG, pending);
2122 }
2123
2124 /* Check if there are enough free descriptors in aggregated txq.
2125  * If not, update the number of occupied descriptors and repeat the check.
2126  *
2127  * Called only from mvpp2_tx(), so migration is disabled, using
2128  * smp_processor_id() is OK.
2129  */
2130 static int mvpp2_aggr_desc_num_check(struct mvpp2_port *port,
2131                                      struct mvpp2_tx_queue *aggr_txq, int num)
2132 {
2133         if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE) {
2134                 /* Update number of occupied aggregated Tx descriptors */
2135                 unsigned int thread =
2136                         mvpp2_cpu_to_thread(port->priv, smp_processor_id());
2137                 u32 val = mvpp2_read_relaxed(port->priv,
2138                                              MVPP2_AGGR_TXQ_STATUS_REG(thread));
2139
2140                 aggr_txq->count = val & MVPP2_AGGR_TXQ_PENDING_MASK;
2141
2142                 if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE)
2143                         return -ENOMEM;
2144         }
2145         return 0;
2146 }
2147
2148 /* Reserved Tx descriptors allocation request
2149  *
2150  * Called only from mvpp2_txq_reserved_desc_num_proc(), itself called
2151  * only by mvpp2_tx(), so migration is disabled, using
2152  * smp_processor_id() is OK.
2153  */
2154 static int mvpp2_txq_alloc_reserved_desc(struct mvpp2_port *port,
2155                                          struct mvpp2_tx_queue *txq, int num)
2156 {
2157         unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
2158         struct mvpp2 *priv = port->priv;
2159         u32 val;
2160
2161         val = (txq->id << MVPP2_TXQ_RSVD_REQ_Q_OFFSET) | num;
2162         mvpp2_thread_write_relaxed(priv, thread, MVPP2_TXQ_RSVD_REQ_REG, val);
2163
2164         val = mvpp2_thread_read_relaxed(priv, thread, MVPP2_TXQ_RSVD_RSLT_REG);
2165
2166         return val & MVPP2_TXQ_RSVD_RSLT_MASK;
2167 }
2168
2169 /* Check if there are enough reserved descriptors for transmission.
2170  * If not, request chunk of reserved descriptors and check again.
2171  */
2172 static int mvpp2_txq_reserved_desc_num_proc(struct mvpp2_port *port,
2173                                             struct mvpp2_tx_queue *txq,
2174                                             struct mvpp2_txq_pcpu *txq_pcpu,
2175                                             int num)
2176 {
2177         int req, desc_count;
2178         unsigned int thread;
2179
2180         if (txq_pcpu->reserved_num >= num)
2181                 return 0;
2182
2183         /* Not enough descriptors reserved! Update the reserved descriptor
2184          * count and check again.
2185          */
2186
2187         desc_count = 0;
2188         /* Compute total of used descriptors */
2189         for (thread = 0; thread < port->priv->nthreads; thread++) {
2190                 struct mvpp2_txq_pcpu *txq_pcpu_aux;
2191
2192                 txq_pcpu_aux = per_cpu_ptr(txq->pcpu, thread);
2193                 desc_count += txq_pcpu_aux->count;
2194                 desc_count += txq_pcpu_aux->reserved_num;
2195         }
2196
2197         req = max(MVPP2_CPU_DESC_CHUNK, num - txq_pcpu->reserved_num);
2198         desc_count += req;
2199
2200         if (desc_count >
2201            (txq->size - (MVPP2_MAX_THREADS * MVPP2_CPU_DESC_CHUNK)))
2202                 return -ENOMEM;
2203
2204         txq_pcpu->reserved_num += mvpp2_txq_alloc_reserved_desc(port, txq, req);
2205
2206         /* OK, the descriptor could have been updated: check again. */
2207         if (txq_pcpu->reserved_num < num)
2208                 return -ENOMEM;
2209         return 0;
2210 }
2211
2212 /* Release the last allocated Tx descriptor. Useful to handle DMA
2213  * mapping failures in the Tx path.
2214  */
2215 static void mvpp2_txq_desc_put(struct mvpp2_tx_queue *txq)
2216 {
2217         if (txq->next_desc_to_proc == 0)
2218                 txq->next_desc_to_proc = txq->last_desc - 1;
2219         else
2220                 txq->next_desc_to_proc--;
2221 }
2222
2223 /* Set Tx descriptors fields relevant for CSUM calculation */
2224 static u32 mvpp2_txq_desc_csum(int l3_offs, __be16 l3_proto,
2225                                int ip_hdr_len, int l4_proto)
2226 {
2227         u32 command;
2228
2229         /* fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk,
2230          * G_L4_chk, L4_type required only for checksum calculation
2231          */
2232         command = (l3_offs << MVPP2_TXD_L3_OFF_SHIFT);
2233         command |= (ip_hdr_len << MVPP2_TXD_IP_HLEN_SHIFT);
2234         command |= MVPP2_TXD_IP_CSUM_DISABLE;
2235
2236         if (l3_proto == htons(ETH_P_IP)) {
2237                 command &= ~MVPP2_TXD_IP_CSUM_DISABLE;  /* enable IPv4 csum */
2238                 command &= ~MVPP2_TXD_L3_IP6;           /* enable IPv4 */
2239         } else {
2240                 command |= MVPP2_TXD_L3_IP6;            /* enable IPv6 */
2241         }
2242
2243         if (l4_proto == IPPROTO_TCP) {
2244                 command &= ~MVPP2_TXD_L4_UDP;           /* enable TCP */
2245                 command &= ~MVPP2_TXD_L4_CSUM_FRAG;     /* generate L4 csum */
2246         } else if (l4_proto == IPPROTO_UDP) {
2247                 command |= MVPP2_TXD_L4_UDP;            /* enable UDP */
2248                 command &= ~MVPP2_TXD_L4_CSUM_FRAG;     /* generate L4 csum */
2249         } else {
2250                 command |= MVPP2_TXD_L4_CSUM_NOT;
2251         }
2252
2253         return command;
2254 }
2255
2256 /* Get number of sent descriptors and decrement counter.
2257  * The number of sent descriptors is returned.
2258  * Per-thread access
2259  *
2260  * Called only from mvpp2_txq_done(), called from mvpp2_tx()
2261  * (migration disabled) and from the TX completion tasklet (migration
2262  * disabled) so using smp_processor_id() is OK.
2263  */
2264 static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port,
2265                                            struct mvpp2_tx_queue *txq)
2266 {
2267         u32 val;
2268
2269         /* Reading status reg resets transmitted descriptor counter */
2270         val = mvpp2_thread_read_relaxed(port->priv,
2271                                         mvpp2_cpu_to_thread(port->priv, smp_processor_id()),
2272                                         MVPP2_TXQ_SENT_REG(txq->id));
2273
2274         return (val & MVPP2_TRANSMITTED_COUNT_MASK) >>
2275                 MVPP2_TRANSMITTED_COUNT_OFFSET;
2276 }
2277
2278 /* Called through on_each_cpu(), so runs on all CPUs, with migration
2279  * disabled, therefore using smp_processor_id() is OK.
2280  */
2281 static void mvpp2_txq_sent_counter_clear(void *arg)
2282 {
2283         struct mvpp2_port *port = arg;
2284         int queue;
2285
2286         /* If the thread isn't used, don't do anything */
2287         if (smp_processor_id() > port->priv->nthreads)
2288                 return;
2289
2290         for (queue = 0; queue < port->ntxqs; queue++) {
2291                 int id = port->txqs[queue]->id;
2292
2293                 mvpp2_thread_read(port->priv,
2294                                   mvpp2_cpu_to_thread(port->priv, smp_processor_id()),
2295                                   MVPP2_TXQ_SENT_REG(id));
2296         }
2297 }
2298
2299 /* Set max sizes for Tx queues */
2300 static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port)
2301 {
2302         u32     val, size, mtu;
2303         int     txq, tx_port_num;
2304
2305         mtu = port->pkt_size * 8;
2306         if (mtu > MVPP2_TXP_MTU_MAX)
2307                 mtu = MVPP2_TXP_MTU_MAX;
2308
2309         /* WA for wrong Token bucket update: Set MTU value = 3*real MTU value */
2310         mtu = 3 * mtu;
2311
2312         /* Indirect access to registers */
2313         tx_port_num = mvpp2_egress_port(port);
2314         mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
2315
2316         /* Set MTU */
2317         val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG);
2318         val &= ~MVPP2_TXP_MTU_MAX;
2319         val |= mtu;
2320         mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val);
2321
2322         /* TXP token size and all TXQs token size must be larger that MTU */
2323         val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG);
2324         size = val & MVPP2_TXP_TOKEN_SIZE_MAX;
2325         if (size < mtu) {
2326                 size = mtu;
2327                 val &= ~MVPP2_TXP_TOKEN_SIZE_MAX;
2328                 val |= size;
2329                 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
2330         }
2331
2332         for (txq = 0; txq < port->ntxqs; txq++) {
2333                 val = mvpp2_read(port->priv,
2334                                  MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq));
2335                 size = val & MVPP2_TXQ_TOKEN_SIZE_MAX;
2336
2337                 if (size < mtu) {
2338                         size = mtu;
2339                         val &= ~MVPP2_TXQ_TOKEN_SIZE_MAX;
2340                         val |= size;
2341                         mvpp2_write(port->priv,
2342                                     MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq),
2343                                     val);
2344                 }
2345         }
2346 }
2347
2348 /* Set the number of packets that will be received before Rx interrupt
2349  * will be generated by HW.
2350  */
2351 static void mvpp2_rx_pkts_coal_set(struct mvpp2_port *port,
2352                                    struct mvpp2_rx_queue *rxq)
2353 {
2354         unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
2355
2356         if (rxq->pkts_coal > MVPP2_OCCUPIED_THRESH_MASK)
2357                 rxq->pkts_coal = MVPP2_OCCUPIED_THRESH_MASK;
2358
2359         mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id);
2360         mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_THRESH_REG,
2361                            rxq->pkts_coal);
2362
2363         put_cpu();
2364 }
2365
2366 /* For some reason in the LSP this is done on each CPU. Why ? */
2367 static void mvpp2_tx_pkts_coal_set(struct mvpp2_port *port,
2368                                    struct mvpp2_tx_queue *txq)
2369 {
2370         unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
2371         u32 val;
2372
2373         if (txq->done_pkts_coal > MVPP2_TXQ_THRESH_MASK)
2374                 txq->done_pkts_coal = MVPP2_TXQ_THRESH_MASK;
2375
2376         val = (txq->done_pkts_coal << MVPP2_TXQ_THRESH_OFFSET);
2377         mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id);
2378         mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_THRESH_REG, val);
2379
2380         put_cpu();
2381 }
2382
2383 static u32 mvpp2_usec_to_cycles(u32 usec, unsigned long clk_hz)
2384 {
2385         u64 tmp = (u64)clk_hz * usec;
2386
2387         do_div(tmp, USEC_PER_SEC);
2388
2389         return tmp > U32_MAX ? U32_MAX : tmp;
2390 }
2391
2392 static u32 mvpp2_cycles_to_usec(u32 cycles, unsigned long clk_hz)
2393 {
2394         u64 tmp = (u64)cycles * USEC_PER_SEC;
2395
2396         do_div(tmp, clk_hz);
2397
2398         return tmp > U32_MAX ? U32_MAX : tmp;
2399 }
2400
2401 /* Set the time delay in usec before Rx interrupt */
2402 static void mvpp2_rx_time_coal_set(struct mvpp2_port *port,
2403                                    struct mvpp2_rx_queue *rxq)
2404 {
2405         unsigned long freq = port->priv->tclk;
2406         u32 val = mvpp2_usec_to_cycles(rxq->time_coal, freq);
2407
2408         if (val > MVPP2_MAX_ISR_RX_THRESHOLD) {
2409                 rxq->time_coal =
2410                         mvpp2_cycles_to_usec(MVPP2_MAX_ISR_RX_THRESHOLD, freq);
2411
2412                 /* re-evaluate to get actual register value */
2413                 val = mvpp2_usec_to_cycles(rxq->time_coal, freq);
2414         }
2415
2416         mvpp2_write(port->priv, MVPP2_ISR_RX_THRESHOLD_REG(rxq->id), val);
2417 }
2418
2419 static void mvpp2_tx_time_coal_set(struct mvpp2_port *port)
2420 {
2421         unsigned long freq = port->priv->tclk;
2422         u32 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq);
2423
2424         if (val > MVPP2_MAX_ISR_TX_THRESHOLD) {
2425                 port->tx_time_coal =
2426                         mvpp2_cycles_to_usec(MVPP2_MAX_ISR_TX_THRESHOLD, freq);
2427
2428                 /* re-evaluate to get actual register value */
2429                 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq);
2430         }
2431
2432         mvpp2_write(port->priv, MVPP2_ISR_TX_THRESHOLD_REG(port->id), val);
2433 }
2434
2435 /* Free Tx queue skbuffs */
2436 static void mvpp2_txq_bufs_free(struct mvpp2_port *port,
2437                                 struct mvpp2_tx_queue *txq,
2438                                 struct mvpp2_txq_pcpu *txq_pcpu, int num)
2439 {
2440         int i;
2441
2442         for (i = 0; i < num; i++) {
2443                 struct mvpp2_txq_pcpu_buf *tx_buf =
2444                         txq_pcpu->buffs + txq_pcpu->txq_get_index;
2445
2446                 if (!IS_TSO_HEADER(txq_pcpu, tx_buf->dma) &&
2447                     tx_buf->type != MVPP2_TYPE_XDP_TX)
2448                         dma_unmap_single(port->dev->dev.parent, tx_buf->dma,
2449                                          tx_buf->size, DMA_TO_DEVICE);
2450                 if (tx_buf->type == MVPP2_TYPE_SKB && tx_buf->skb)
2451                         dev_kfree_skb_any(tx_buf->skb);
2452                 else if (tx_buf->type == MVPP2_TYPE_XDP_TX ||
2453                          tx_buf->type == MVPP2_TYPE_XDP_NDO)
2454                         xdp_return_frame(tx_buf->xdpf);
2455
2456                 mvpp2_txq_inc_get(txq_pcpu);
2457         }
2458 }
2459
2460 static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port,
2461                                                         u32 cause)
2462 {
2463         int queue = fls(cause) - 1;
2464
2465         return port->rxqs[queue];
2466 }
2467
2468 static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port,
2469                                                         u32 cause)
2470 {
2471         int queue = fls(cause) - 1;
2472
2473         return port->txqs[queue];
2474 }
2475
2476 /* Handle end of transmission */
2477 static void mvpp2_txq_done(struct mvpp2_port *port, struct mvpp2_tx_queue *txq,
2478                            struct mvpp2_txq_pcpu *txq_pcpu)
2479 {
2480         struct netdev_queue *nq = netdev_get_tx_queue(port->dev, txq->log_id);
2481         int tx_done;
2482
2483         if (txq_pcpu->thread != mvpp2_cpu_to_thread(port->priv, smp_processor_id()))
2484                 netdev_err(port->dev, "wrong cpu on the end of Tx processing\n");
2485
2486         tx_done = mvpp2_txq_sent_desc_proc(port, txq);
2487         if (!tx_done)
2488                 return;
2489         mvpp2_txq_bufs_free(port, txq, txq_pcpu, tx_done);
2490
2491         txq_pcpu->count -= tx_done;
2492
2493         if (netif_tx_queue_stopped(nq))
2494                 if (txq_pcpu->count <= txq_pcpu->wake_threshold)
2495                         netif_tx_wake_queue(nq);
2496 }
2497
2498 static unsigned int mvpp2_tx_done(struct mvpp2_port *port, u32 cause,
2499                                   unsigned int thread)
2500 {
2501         struct mvpp2_tx_queue *txq;
2502         struct mvpp2_txq_pcpu *txq_pcpu;
2503         unsigned int tx_todo = 0;
2504
2505         while (cause) {
2506                 txq = mvpp2_get_tx_queue(port, cause);
2507                 if (!txq)
2508                         break;
2509
2510                 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
2511
2512                 if (txq_pcpu->count) {
2513                         mvpp2_txq_done(port, txq, txq_pcpu);
2514                         tx_todo += txq_pcpu->count;
2515                 }
2516
2517                 cause &= ~(1 << txq->log_id);
2518         }
2519         return tx_todo;
2520 }
2521
2522 /* Rx/Tx queue initialization/cleanup methods */
2523
2524 /* Allocate and initialize descriptors for aggr TXQ */
2525 static int mvpp2_aggr_txq_init(struct platform_device *pdev,
2526                                struct mvpp2_tx_queue *aggr_txq,
2527                                unsigned int thread, struct mvpp2 *priv)
2528 {
2529         u32 txq_dma;
2530
2531         /* Allocate memory for TX descriptors */
2532         aggr_txq->descs = dma_alloc_coherent(&pdev->dev,
2533                                              MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE,
2534                                              &aggr_txq->descs_dma, GFP_KERNEL);
2535         if (!aggr_txq->descs)
2536                 return -ENOMEM;
2537
2538         aggr_txq->last_desc = MVPP2_AGGR_TXQ_SIZE - 1;
2539
2540         /* Aggr TXQ no reset WA */
2541         aggr_txq->next_desc_to_proc = mvpp2_read(priv,
2542                                                  MVPP2_AGGR_TXQ_INDEX_REG(thread));
2543
2544         /* Set Tx descriptors queue starting address indirect
2545          * access
2546          */
2547         if (priv->hw_version == MVPP21)
2548                 txq_dma = aggr_txq->descs_dma;
2549         else
2550                 txq_dma = aggr_txq->descs_dma >>
2551                         MVPP22_AGGR_TXQ_DESC_ADDR_OFFS;
2552
2553         mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(thread), txq_dma);
2554         mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(thread),
2555                     MVPP2_AGGR_TXQ_SIZE);
2556
2557         return 0;
2558 }
2559
2560 /* Create a specified Rx queue */
2561 static int mvpp2_rxq_init(struct mvpp2_port *port,
2562                           struct mvpp2_rx_queue *rxq)
2563 {
2564         struct mvpp2 *priv = port->priv;
2565         unsigned int thread;
2566         u32 rxq_dma;
2567         int err;
2568
2569         rxq->size = port->rx_ring_size;
2570
2571         /* Allocate memory for RX descriptors */
2572         rxq->descs = dma_alloc_coherent(port->dev->dev.parent,
2573                                         rxq->size * MVPP2_DESC_ALIGNED_SIZE,
2574                                         &rxq->descs_dma, GFP_KERNEL);
2575         if (!rxq->descs)
2576                 return -ENOMEM;
2577
2578         rxq->last_desc = rxq->size - 1;
2579
2580         /* Zero occupied and non-occupied counters - direct access */
2581         mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
2582
2583         /* Set Rx descriptors queue starting address - indirect access */
2584         thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
2585         mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id);
2586         if (port->priv->hw_version == MVPP21)
2587                 rxq_dma = rxq->descs_dma;
2588         else
2589                 rxq_dma = rxq->descs_dma >> MVPP22_DESC_ADDR_OFFS;
2590         mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma);
2591         mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_SIZE_REG, rxq->size);
2592         mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_INDEX_REG, 0);
2593         put_cpu();
2594
2595         /* Set Offset */
2596         mvpp2_rxq_offset_set(port, rxq->id, MVPP2_SKB_HEADROOM);
2597
2598         /* Set coalescing pkts and time */
2599         mvpp2_rx_pkts_coal_set(port, rxq);
2600         mvpp2_rx_time_coal_set(port, rxq);
2601
2602         /* Add number of descriptors ready for receiving packets */
2603         mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size);
2604
2605         if (priv->percpu_pools) {
2606                 err = xdp_rxq_info_reg(&rxq->xdp_rxq_short, port->dev, rxq->id);
2607                 if (err < 0)
2608                         goto err_free_dma;
2609
2610                 err = xdp_rxq_info_reg(&rxq->xdp_rxq_long, port->dev, rxq->id);
2611                 if (err < 0)
2612                         goto err_unregister_rxq_short;
2613
2614                 /* Every RXQ has a pool for short and another for long packets */
2615                 err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq_short,
2616                                                  MEM_TYPE_PAGE_POOL,
2617                                                  priv->page_pool[rxq->logic_rxq]);
2618                 if (err < 0)
2619                         goto err_unregister_rxq_long;
2620
2621                 err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq_long,
2622                                                  MEM_TYPE_PAGE_POOL,
2623                                                  priv->page_pool[rxq->logic_rxq +
2624                                                                  port->nrxqs]);
2625                 if (err < 0)
2626                         goto err_unregister_mem_rxq_short;
2627         }
2628
2629         return 0;
2630
2631 err_unregister_mem_rxq_short:
2632         xdp_rxq_info_unreg_mem_model(&rxq->xdp_rxq_short);
2633 err_unregister_rxq_long:
2634         xdp_rxq_info_unreg(&rxq->xdp_rxq_long);
2635 err_unregister_rxq_short:
2636         xdp_rxq_info_unreg(&rxq->xdp_rxq_short);
2637 err_free_dma:
2638         dma_free_coherent(port->dev->dev.parent,
2639                           rxq->size * MVPP2_DESC_ALIGNED_SIZE,
2640                           rxq->descs, rxq->descs_dma);
2641         return err;
2642 }
2643
2644 /* Push packets received by the RXQ to BM pool */
2645 static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port,
2646                                 struct mvpp2_rx_queue *rxq)
2647 {
2648         int rx_received, i;
2649
2650         rx_received = mvpp2_rxq_received(port, rxq->id);
2651         if (!rx_received)
2652                 return;
2653
2654         for (i = 0; i < rx_received; i++) {
2655                 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
2656                 u32 status = mvpp2_rxdesc_status_get(port, rx_desc);
2657                 int pool;
2658
2659                 pool = (status & MVPP2_RXD_BM_POOL_ID_MASK) >>
2660                         MVPP2_RXD_BM_POOL_ID_OFFS;
2661
2662                 mvpp2_bm_pool_put(port, pool,
2663                                   mvpp2_rxdesc_dma_addr_get(port, rx_desc),
2664                                   mvpp2_rxdesc_cookie_get(port, rx_desc));
2665         }
2666         mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received);
2667 }
2668
2669 /* Cleanup Rx queue */
2670 static void mvpp2_rxq_deinit(struct mvpp2_port *port,
2671                              struct mvpp2_rx_queue *rxq)
2672 {
2673         unsigned int thread;
2674
2675         if (xdp_rxq_info_is_reg(&rxq->xdp_rxq_short))
2676                 xdp_rxq_info_unreg(&rxq->xdp_rxq_short);
2677
2678         if (xdp_rxq_info_is_reg(&rxq->xdp_rxq_long))
2679                 xdp_rxq_info_unreg(&rxq->xdp_rxq_long);
2680
2681         mvpp2_rxq_drop_pkts(port, rxq);
2682
2683         if (rxq->descs)
2684                 dma_free_coherent(port->dev->dev.parent,
2685                                   rxq->size * MVPP2_DESC_ALIGNED_SIZE,
2686                                   rxq->descs,
2687                                   rxq->descs_dma);
2688
2689         rxq->descs             = NULL;
2690         rxq->last_desc         = 0;
2691         rxq->next_desc_to_proc = 0;
2692         rxq->descs_dma         = 0;
2693
2694         /* Clear Rx descriptors queue starting address and size;
2695          * free descriptor number
2696          */
2697         mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
2698         thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
2699         mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id);
2700         mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_ADDR_REG, 0);
2701         mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_SIZE_REG, 0);
2702         put_cpu();
2703 }
2704
2705 /* Create and initialize a Tx queue */
2706 static int mvpp2_txq_init(struct mvpp2_port *port,
2707                           struct mvpp2_tx_queue *txq)
2708 {
2709         u32 val;
2710         unsigned int thread;
2711         int desc, desc_per_txq, tx_port_num;
2712         struct mvpp2_txq_pcpu *txq_pcpu;
2713
2714         txq->size = port->tx_ring_size;
2715
2716         /* Allocate memory for Tx descriptors */
2717         txq->descs = dma_alloc_coherent(port->dev->dev.parent,
2718                                 txq->size * MVPP2_DESC_ALIGNED_SIZE,
2719                                 &txq->descs_dma, GFP_KERNEL);
2720         if (!txq->descs)
2721                 return -ENOMEM;
2722
2723         txq->last_desc = txq->size - 1;
2724
2725         /* Set Tx descriptors queue starting address - indirect access */
2726         thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
2727         mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id);
2728         mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_ADDR_REG,
2729                            txq->descs_dma);
2730         mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_SIZE_REG,
2731                            txq->size & MVPP2_TXQ_DESC_SIZE_MASK);
2732         mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_INDEX_REG, 0);
2733         mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_RSVD_CLR_REG,
2734                            txq->id << MVPP2_TXQ_RSVD_CLR_OFFSET);
2735         val = mvpp2_thread_read(port->priv, thread, MVPP2_TXQ_PENDING_REG);
2736         val &= ~MVPP2_TXQ_PENDING_MASK;
2737         mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PENDING_REG, val);
2738
2739         /* Calculate base address in prefetch buffer. We reserve 16 descriptors
2740          * for each existing TXQ.
2741          * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT
2742          * GBE ports assumed to be continuous from 0 to MVPP2_MAX_PORTS
2743          */
2744         desc_per_txq = 16;
2745         desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) +
2746                (txq->log_id * desc_per_txq);
2747
2748         mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG,
2749                            MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 |
2750                            MVPP2_PREF_BUF_THRESH(desc_per_txq / 2));
2751         put_cpu();
2752
2753         /* WRR / EJP configuration - indirect access */
2754         tx_port_num = mvpp2_egress_port(port);
2755         mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
2756
2757         val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id));
2758         val &= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK;
2759         val |= MVPP2_TXQ_REFILL_PERIOD_MASK(1);
2760         val |= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK;
2761         mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val);
2762
2763         val = MVPP2_TXQ_TOKEN_SIZE_MAX;
2764         mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id),
2765                     val);
2766
2767         for (thread = 0; thread < port->priv->nthreads; thread++) {
2768                 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
2769                 txq_pcpu->size = txq->size;
2770                 txq_pcpu->buffs = kmalloc_array(txq_pcpu->size,
2771                                                 sizeof(*txq_pcpu->buffs),
2772                                                 GFP_KERNEL);
2773                 if (!txq_pcpu->buffs)
2774                         return -ENOMEM;
2775
2776                 txq_pcpu->count = 0;
2777                 txq_pcpu->reserved_num = 0;
2778                 txq_pcpu->txq_put_index = 0;
2779                 txq_pcpu->txq_get_index = 0;
2780                 txq_pcpu->tso_headers = NULL;
2781
2782                 txq_pcpu->stop_threshold = txq->size - MVPP2_MAX_SKB_DESCS;
2783                 txq_pcpu->wake_threshold = txq_pcpu->stop_threshold / 2;
2784
2785                 txq_pcpu->tso_headers =
2786                         dma_alloc_coherent(port->dev->dev.parent,
2787                                            txq_pcpu->size * TSO_HEADER_SIZE,
2788                                            &txq_pcpu->tso_headers_dma,
2789                                            GFP_KERNEL);
2790                 if (!txq_pcpu->tso_headers)
2791                         return -ENOMEM;
2792         }
2793
2794         return 0;
2795 }
2796
2797 /* Free allocated TXQ resources */
2798 static void mvpp2_txq_deinit(struct mvpp2_port *port,
2799                              struct mvpp2_tx_queue *txq)
2800 {
2801         struct mvpp2_txq_pcpu *txq_pcpu;
2802         unsigned int thread;
2803
2804         for (thread = 0; thread < port->priv->nthreads; thread++) {
2805                 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
2806                 kfree(txq_pcpu->buffs);
2807
2808                 if (txq_pcpu->tso_headers)
2809                         dma_free_coherent(port->dev->dev.parent,
2810                                           txq_pcpu->size * TSO_HEADER_SIZE,
2811                                           txq_pcpu->tso_headers,
2812                                           txq_pcpu->tso_headers_dma);
2813
2814                 txq_pcpu->tso_headers = NULL;
2815         }
2816
2817         if (txq->descs)
2818                 dma_free_coherent(port->dev->dev.parent,
2819                                   txq->size * MVPP2_DESC_ALIGNED_SIZE,
2820                                   txq->descs, txq->descs_dma);
2821
2822         txq->descs             = NULL;
2823         txq->last_desc         = 0;
2824         txq->next_desc_to_proc = 0;
2825         txq->descs_dma         = 0;
2826
2827         /* Set minimum bandwidth for disabled TXQs */
2828         mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->log_id), 0);
2829
2830         /* Set Tx descriptors queue starting address and size */
2831         thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
2832         mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id);
2833         mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_ADDR_REG, 0);
2834         mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_SIZE_REG, 0);
2835         put_cpu();
2836 }
2837
2838 /* Cleanup Tx ports */
2839 static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq)
2840 {
2841         struct mvpp2_txq_pcpu *txq_pcpu;
2842         int delay, pending;
2843         unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
2844         u32 val;
2845
2846         mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id);
2847         val = mvpp2_thread_read(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG);
2848         val |= MVPP2_TXQ_DRAIN_EN_MASK;
2849         mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, val);
2850
2851         /* The napi queue has been stopped so wait for all packets
2852          * to be transmitted.
2853          */
2854         delay = 0;
2855         do {
2856                 if (delay >= MVPP2_TX_PENDING_TIMEOUT_MSEC) {
2857                         netdev_warn(port->dev,
2858                                     "port %d: cleaning queue %d timed out\n",
2859                                     port->id, txq->log_id);
2860                         break;
2861                 }
2862                 mdelay(1);
2863                 delay++;
2864
2865                 pending = mvpp2_thread_read(port->priv, thread,
2866                                             MVPP2_TXQ_PENDING_REG);
2867                 pending &= MVPP2_TXQ_PENDING_MASK;
2868         } while (pending);
2869
2870         val &= ~MVPP2_TXQ_DRAIN_EN_MASK;
2871         mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, val);
2872         put_cpu();
2873
2874         for (thread = 0; thread < port->priv->nthreads; thread++) {
2875                 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
2876
2877                 /* Release all packets */
2878                 mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count);
2879
2880                 /* Reset queue */
2881                 txq_pcpu->count = 0;
2882                 txq_pcpu->txq_put_index = 0;
2883                 txq_pcpu->txq_get_index = 0;
2884         }
2885 }
2886
2887 /* Cleanup all Tx queues */
2888 static void mvpp2_cleanup_txqs(struct mvpp2_port *port)
2889 {
2890         struct mvpp2_tx_queue *txq;
2891         int queue;
2892         u32 val;
2893
2894         val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG);
2895
2896         /* Reset Tx ports and delete Tx queues */
2897         val |= MVPP2_TX_PORT_FLUSH_MASK(port->id);
2898         mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
2899
2900         for (queue = 0; queue < port->ntxqs; queue++) {
2901                 txq = port->txqs[queue];
2902                 mvpp2_txq_clean(port, txq);
2903                 mvpp2_txq_deinit(port, txq);
2904         }
2905
2906         on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1);
2907
2908         val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id);
2909         mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
2910 }
2911
2912 /* Cleanup all Rx queues */
2913 static void mvpp2_cleanup_rxqs(struct mvpp2_port *port)
2914 {
2915         int queue;
2916
2917         for (queue = 0; queue < port->nrxqs; queue++)
2918                 mvpp2_rxq_deinit(port, port->rxqs[queue]);
2919 }
2920
2921 /* Init all Rx queues for port */
2922 static int mvpp2_setup_rxqs(struct mvpp2_port *port)
2923 {
2924         int queue, err;
2925
2926         for (queue = 0; queue < port->nrxqs; queue++) {
2927                 err = mvpp2_rxq_init(port, port->rxqs[queue]);
2928                 if (err)
2929                         goto err_cleanup;
2930         }
2931         return 0;
2932
2933 err_cleanup:
2934         mvpp2_cleanup_rxqs(port);
2935         return err;
2936 }
2937
2938 /* Init all tx queues for port */
2939 static int mvpp2_setup_txqs(struct mvpp2_port *port)
2940 {
2941         struct mvpp2_tx_queue *txq;
2942         int queue, err;
2943
2944         for (queue = 0; queue < port->ntxqs; queue++) {
2945                 txq = port->txqs[queue];
2946                 err = mvpp2_txq_init(port, txq);
2947                 if (err)
2948                         goto err_cleanup;
2949
2950                 /* Assign this queue to a CPU */
2951                 if (queue < num_possible_cpus())
2952                         netif_set_xps_queue(port->dev, cpumask_of(queue), queue);
2953         }
2954
2955         if (port->has_tx_irqs) {
2956                 mvpp2_tx_time_coal_set(port);
2957                 for (queue = 0; queue < port->ntxqs; queue++) {
2958                         txq = port->txqs[queue];
2959                         mvpp2_tx_pkts_coal_set(port, txq);
2960                 }
2961         }
2962
2963         on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1);
2964         return 0;
2965
2966 err_cleanup:
2967         mvpp2_cleanup_txqs(port);
2968         return err;
2969 }
2970
2971 /* The callback for per-port interrupt */
2972 static irqreturn_t mvpp2_isr(int irq, void *dev_id)
2973 {
2974         struct mvpp2_queue_vector *qv = dev_id;
2975
2976         mvpp2_qvec_interrupt_disable(qv);
2977
2978         napi_schedule(&qv->napi);
2979
2980         return IRQ_HANDLED;
2981 }
2982
2983 /* Per-port interrupt for link status changes */
2984 static irqreturn_t mvpp2_link_status_isr(int irq, void *dev_id)
2985 {
2986         struct mvpp2_port *port = (struct mvpp2_port *)dev_id;
2987         struct net_device *dev = port->dev;
2988         bool event = false, link = false;
2989         u32 val;
2990
2991         mvpp22_gop_mask_irq(port);
2992
2993         if (mvpp2_port_supports_xlg(port) &&
2994             mvpp2_is_xlg(port->phy_interface)) {
2995                 val = readl(port->base + MVPP22_XLG_INT_STAT);
2996                 if (val & MVPP22_XLG_INT_STAT_LINK) {
2997                         event = true;
2998                         val = readl(port->base + MVPP22_XLG_STATUS);
2999                         if (val & MVPP22_XLG_STATUS_LINK_UP)
3000                                 link = true;
3001                 }
3002         } else if (phy_interface_mode_is_rgmii(port->phy_interface) ||
3003                    phy_interface_mode_is_8023z(port->phy_interface) ||
3004                    port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
3005                 val = readl(port->base + MVPP22_GMAC_INT_STAT);
3006                 if (val & MVPP22_GMAC_INT_STAT_LINK) {
3007                         event = true;
3008                         val = readl(port->base + MVPP2_GMAC_STATUS0);
3009                         if (val & MVPP2_GMAC_STATUS0_LINK_UP)
3010                                 link = true;
3011                 }
3012         }
3013
3014         if (port->phylink) {
3015                 phylink_mac_change(port->phylink, link);
3016                 goto handled;
3017         }
3018
3019         if (!netif_running(dev) || !event)
3020                 goto handled;
3021
3022         if (link) {
3023                 mvpp2_interrupts_enable(port);
3024
3025                 mvpp2_egress_enable(port);
3026                 mvpp2_ingress_enable(port);
3027                 netif_carrier_on(dev);
3028                 netif_tx_wake_all_queues(dev);
3029         } else {
3030                 netif_tx_stop_all_queues(dev);
3031                 netif_carrier_off(dev);
3032                 mvpp2_ingress_disable(port);
3033                 mvpp2_egress_disable(port);
3034
3035                 mvpp2_interrupts_disable(port);
3036         }
3037
3038 handled:
3039         mvpp22_gop_unmask_irq(port);
3040         return IRQ_HANDLED;
3041 }
3042
3043 static enum hrtimer_restart mvpp2_hr_timer_cb(struct hrtimer *timer)
3044 {
3045         struct net_device *dev;
3046         struct mvpp2_port *port;
3047         struct mvpp2_port_pcpu *port_pcpu;
3048         unsigned int tx_todo, cause;
3049
3050         port_pcpu = container_of(timer, struct mvpp2_port_pcpu, tx_done_timer);
3051         dev = port_pcpu->dev;
3052
3053         if (!netif_running(dev))
3054                 return HRTIMER_NORESTART;
3055
3056         port_pcpu->timer_scheduled = false;
3057         port = netdev_priv(dev);
3058
3059         /* Process all the Tx queues */
3060         cause = (1 << port->ntxqs) - 1;
3061         tx_todo = mvpp2_tx_done(port, cause,
3062                                 mvpp2_cpu_to_thread(port->priv, smp_processor_id()));
3063
3064         /* Set the timer in case not all the packets were processed */
3065         if (tx_todo && !port_pcpu->timer_scheduled) {
3066                 port_pcpu->timer_scheduled = true;
3067                 hrtimer_forward_now(&port_pcpu->tx_done_timer,
3068                                     MVPP2_TXDONE_HRTIMER_PERIOD_NS);
3069
3070                 return HRTIMER_RESTART;
3071         }
3072         return HRTIMER_NORESTART;
3073 }
3074
3075 /* Main RX/TX processing routines */
3076
3077 /* Display more error info */
3078 static void mvpp2_rx_error(struct mvpp2_port *port,
3079                            struct mvpp2_rx_desc *rx_desc)
3080 {
3081         u32 status = mvpp2_rxdesc_status_get(port, rx_desc);
3082         size_t sz = mvpp2_rxdesc_size_get(port, rx_desc);
3083         char *err_str = NULL;
3084
3085         switch (status & MVPP2_RXD_ERR_CODE_MASK) {
3086         case MVPP2_RXD_ERR_CRC:
3087                 err_str = "crc";
3088                 break;
3089         case MVPP2_RXD_ERR_OVERRUN:
3090                 err_str = "overrun";
3091                 break;
3092         case MVPP2_RXD_ERR_RESOURCE:
3093                 err_str = "resource";
3094                 break;
3095         }
3096         if (err_str && net_ratelimit())
3097                 netdev_err(port->dev,
3098                            "bad rx status %08x (%s error), size=%zu\n",
3099                            status, err_str, sz);
3100 }
3101
3102 /* Handle RX checksum offload */
3103 static void mvpp2_rx_csum(struct mvpp2_port *port, u32 status,
3104                           struct sk_buff *skb)
3105 {
3106         if (((status & MVPP2_RXD_L3_IP4) &&
3107              !(status & MVPP2_RXD_IP4_HEADER_ERR)) ||
3108             (status & MVPP2_RXD_L3_IP6))
3109                 if (((status & MVPP2_RXD_L4_UDP) ||
3110                      (status & MVPP2_RXD_L4_TCP)) &&
3111                      (status & MVPP2_RXD_L4_CSUM_OK)) {
3112                         skb->csum = 0;
3113                         skb->ip_summed = CHECKSUM_UNNECESSARY;
3114                         return;
3115                 }
3116
3117         skb->ip_summed = CHECKSUM_NONE;
3118 }
3119
3120 /* Allocate a new skb and add it to BM pool */
3121 static int mvpp2_rx_refill(struct mvpp2_port *port,
3122                            struct mvpp2_bm_pool *bm_pool,
3123                            struct page_pool *page_pool, int pool)
3124 {
3125         dma_addr_t dma_addr;
3126         phys_addr_t phys_addr;
3127         void *buf;
3128
3129         buf = mvpp2_buf_alloc(port, bm_pool, page_pool,
3130                               &dma_addr, &phys_addr, GFP_ATOMIC);
3131         if (!buf)
3132                 return -ENOMEM;
3133
3134         mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr);
3135
3136         return 0;
3137 }
3138
3139 /* Handle tx checksum */
3140 static u32 mvpp2_skb_tx_csum(struct mvpp2_port *port, struct sk_buff *skb)
3141 {
3142         if (skb->ip_summed == CHECKSUM_PARTIAL) {
3143                 int ip_hdr_len = 0;
3144                 u8 l4_proto;
3145                 __be16 l3_proto = vlan_get_protocol(skb);
3146
3147                 if (l3_proto == htons(ETH_P_IP)) {
3148                         struct iphdr *ip4h = ip_hdr(skb);
3149
3150                         /* Calculate IPv4 checksum and L4 checksum */
3151                         ip_hdr_len = ip4h->ihl;
3152                         l4_proto = ip4h->protocol;
3153                 } else if (l3_proto == htons(ETH_P_IPV6)) {
3154                         struct ipv6hdr *ip6h = ipv6_hdr(skb);
3155
3156                         /* Read l4_protocol from one of IPv6 extra headers */
3157                         if (skb_network_header_len(skb) > 0)
3158                                 ip_hdr_len = (skb_network_header_len(skb) >> 2);
3159                         l4_proto = ip6h->nexthdr;
3160                 } else {
3161                         return MVPP2_TXD_L4_CSUM_NOT;
3162                 }
3163
3164                 return mvpp2_txq_desc_csum(skb_network_offset(skb),
3165                                            l3_proto, ip_hdr_len, l4_proto);
3166         }
3167
3168         return MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE;
3169 }
3170
3171 static void mvpp2_xdp_finish_tx(struct mvpp2_port *port, u16 txq_id, int nxmit, int nxmit_byte)
3172 {
3173         unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
3174         struct mvpp2_tx_queue *aggr_txq;
3175         struct mvpp2_txq_pcpu *txq_pcpu;
3176         struct mvpp2_tx_queue *txq;
3177         struct netdev_queue *nq;
3178
3179         txq = port->txqs[txq_id];
3180         txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
3181         nq = netdev_get_tx_queue(port->dev, txq_id);
3182         aggr_txq = &port->priv->aggr_txqs[thread];
3183
3184         txq_pcpu->reserved_num -= nxmit;
3185         txq_pcpu->count += nxmit;
3186         aggr_txq->count += nxmit;
3187
3188         /* Enable transmit */
3189         wmb();
3190         mvpp2_aggr_txq_pend_desc_add(port, nxmit);
3191
3192         if (txq_pcpu->count >= txq_pcpu->stop_threshold)
3193                 netif_tx_stop_queue(nq);
3194
3195         /* Finalize TX processing */
3196         if (!port->has_tx_irqs && txq_pcpu->count >= txq->done_pkts_coal)
3197                 mvpp2_txq_done(port, txq, txq_pcpu);
3198 }
3199
3200 static int
3201 mvpp2_xdp_submit_frame(struct mvpp2_port *port, u16 txq_id,
3202                        struct xdp_frame *xdpf, bool dma_map)
3203 {
3204         unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
3205         u32 tx_cmd = MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE |
3206                      MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC;
3207         enum mvpp2_tx_buf_type buf_type;
3208         struct mvpp2_txq_pcpu *txq_pcpu;
3209         struct mvpp2_tx_queue *aggr_txq;
3210         struct mvpp2_tx_desc *tx_desc;
3211         struct mvpp2_tx_queue *txq;
3212         int ret = MVPP2_XDP_TX;
3213         dma_addr_t dma_addr;
3214
3215         txq = port->txqs[txq_id];
3216         txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
3217         aggr_txq = &port->priv->aggr_txqs[thread];
3218
3219         /* Check number of available descriptors */
3220         if (mvpp2_aggr_desc_num_check(port, aggr_txq, 1) ||
3221             mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu, 1)) {
3222                 ret = MVPP2_XDP_DROPPED;
3223                 goto out;
3224         }
3225
3226         /* Get a descriptor for the first part of the packet */
3227         tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
3228         mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
3229         mvpp2_txdesc_size_set(port, tx_desc, xdpf->len);
3230
3231         if (dma_map) {
3232                 /* XDP_REDIRECT or AF_XDP */
3233                 dma_addr = dma_map_single(port->dev->dev.parent, xdpf->data,
3234                                           xdpf->len, DMA_TO_DEVICE);
3235
3236                 if (unlikely(dma_mapping_error(port->dev->dev.parent, dma_addr))) {
3237                         mvpp2_txq_desc_put(txq);
3238                         ret = MVPP2_XDP_DROPPED;
3239                         goto out;
3240                 }
3241
3242                 buf_type = MVPP2_TYPE_XDP_NDO;
3243         } else {
3244                 /* XDP_TX */
3245                 struct page *page = virt_to_page(xdpf->data);
3246
3247                 dma_addr = page_pool_get_dma_addr(page) +
3248                            sizeof(*xdpf) + xdpf->headroom;
3249                 dma_sync_single_for_device(port->dev->dev.parent, dma_addr,
3250                                            xdpf->len, DMA_BIDIRECTIONAL);
3251
3252                 buf_type = MVPP2_TYPE_XDP_TX;
3253         }
3254
3255         mvpp2_txdesc_dma_addr_set(port, tx_desc, dma_addr);
3256
3257         mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd);
3258         mvpp2_txq_inc_put(port, txq_pcpu, xdpf, tx_desc, buf_type);
3259
3260 out:
3261         return ret;
3262 }
3263
3264 static int
3265 mvpp2_xdp_xmit_back(struct mvpp2_port *port, struct xdp_buff *xdp)
3266 {
3267         struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats);
3268         struct xdp_frame *xdpf;
3269         u16 txq_id;
3270         int ret;
3271
3272         xdpf = xdp_convert_buff_to_frame(xdp);
3273         if (unlikely(!xdpf))
3274                 return MVPP2_XDP_DROPPED;
3275
3276         /* The first of the TX queues are used for XPS,
3277          * the second half for XDP_TX
3278          */
3279         txq_id = mvpp2_cpu_to_thread(port->priv, smp_processor_id()) + (port->ntxqs / 2);
3280
3281         ret = mvpp2_xdp_submit_frame(port, txq_id, xdpf, false);
3282         if (ret == MVPP2_XDP_TX) {
3283                 u64_stats_update_begin(&stats->syncp);
3284                 stats->tx_bytes += xdpf->len;
3285                 stats->tx_packets++;
3286                 stats->xdp_tx++;
3287                 u64_stats_update_end(&stats->syncp);
3288
3289                 mvpp2_xdp_finish_tx(port, txq_id, 1, xdpf->len);
3290         } else {
3291                 u64_stats_update_begin(&stats->syncp);
3292                 stats->xdp_tx_err++;
3293                 u64_stats_update_end(&stats->syncp);
3294         }
3295
3296         return ret;
3297 }
3298
3299 static int
3300 mvpp2_xdp_xmit(struct net_device *dev, int num_frame,
3301                struct xdp_frame **frames, u32 flags)
3302 {
3303         struct mvpp2_port *port = netdev_priv(dev);
3304         int i, nxmit_byte = 0, nxmit = num_frame;
3305         struct mvpp2_pcpu_stats *stats;
3306         u16 txq_id;
3307         u32 ret;
3308
3309         if (unlikely(test_bit(0, &port->state)))
3310                 return -ENETDOWN;
3311
3312         if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
3313                 return -EINVAL;
3314
3315         /* The first of the TX queues are used for XPS,
3316          * the second half for XDP_TX
3317          */
3318         txq_id = mvpp2_cpu_to_thread(port->priv, smp_processor_id()) + (port->ntxqs / 2);
3319
3320         for (i = 0; i < num_frame; i++) {
3321                 ret = mvpp2_xdp_submit_frame(port, txq_id, frames[i], true);
3322                 if (ret == MVPP2_XDP_TX) {
3323                         nxmit_byte += frames[i]->len;
3324                 } else {
3325                         xdp_return_frame_rx_napi(frames[i]);
3326                         nxmit--;
3327                 }
3328         }
3329
3330         if (likely(nxmit > 0))
3331                 mvpp2_xdp_finish_tx(port, txq_id, nxmit, nxmit_byte);
3332
3333         stats = this_cpu_ptr(port->stats);
3334         u64_stats_update_begin(&stats->syncp);
3335         stats->tx_bytes += nxmit_byte;
3336         stats->tx_packets += nxmit;
3337         stats->xdp_xmit += nxmit;
3338         stats->xdp_xmit_err += num_frame - nxmit;
3339         u64_stats_update_end(&stats->syncp);
3340
3341         return nxmit;
3342 }
3343
3344 static int
3345 mvpp2_run_xdp(struct mvpp2_port *port, struct mvpp2_rx_queue *rxq,
3346               struct bpf_prog *prog, struct xdp_buff *xdp,
3347               struct page_pool *pp, struct mvpp2_pcpu_stats *stats)
3348 {
3349         unsigned int len, sync, err;
3350         struct page *page;
3351         u32 ret, act;
3352
3353         len = xdp->data_end - xdp->data_hard_start - MVPP2_SKB_HEADROOM;
3354         act = bpf_prog_run_xdp(prog, xdp);
3355
3356         /* Due xdp_adjust_tail: DMA sync for_device cover max len CPU touch */
3357         sync = xdp->data_end - xdp->data_hard_start - MVPP2_SKB_HEADROOM;
3358         sync = max(sync, len);
3359
3360         switch (act) {
3361         case XDP_PASS:
3362                 stats->xdp_pass++;
3363                 ret = MVPP2_XDP_PASS;
3364                 break;
3365         case XDP_REDIRECT:
3366                 err = xdp_do_redirect(port->dev, xdp, prog);
3367                 if (unlikely(err)) {
3368                         ret = MVPP2_XDP_DROPPED;
3369                         page = virt_to_head_page(xdp->data);
3370                         page_pool_put_page(pp, page, sync, true);
3371                 } else {
3372                         ret = MVPP2_XDP_REDIR;
3373                         stats->xdp_redirect++;
3374                 }
3375                 break;
3376         case XDP_TX:
3377                 ret = mvpp2_xdp_xmit_back(port, xdp);
3378                 if (ret != MVPP2_XDP_TX) {
3379                         page = virt_to_head_page(xdp->data);
3380                         page_pool_put_page(pp, page, sync, true);
3381                 }
3382                 break;
3383         default:
3384                 bpf_warn_invalid_xdp_action(act);
3385                 fallthrough;
3386         case XDP_ABORTED:
3387                 trace_xdp_exception(port->dev, prog, act);
3388                 fallthrough;
3389         case XDP_DROP:
3390                 page = virt_to_head_page(xdp->data);
3391                 page_pool_put_page(pp, page, sync, true);
3392                 ret = MVPP2_XDP_DROPPED;
3393                 stats->xdp_drop++;
3394                 break;
3395         }
3396
3397         return ret;
3398 }
3399
3400 /* Main rx processing */
3401 static int mvpp2_rx(struct mvpp2_port *port, struct napi_struct *napi,
3402                     int rx_todo, struct mvpp2_rx_queue *rxq)
3403 {
3404         struct net_device *dev = port->dev;
3405         struct mvpp2_pcpu_stats ps = {};
3406         enum dma_data_direction dma_dir;
3407         struct bpf_prog *xdp_prog;
3408         struct xdp_buff xdp;
3409         int rx_received;
3410         int rx_done = 0;
3411         u32 xdp_ret = 0;
3412
3413         rcu_read_lock();
3414
3415         xdp_prog = READ_ONCE(port->xdp_prog);
3416
3417         /* Get number of received packets and clamp the to-do */
3418         rx_received = mvpp2_rxq_received(port, rxq->id);
3419         if (rx_todo > rx_received)
3420                 rx_todo = rx_received;
3421
3422         while (rx_done < rx_todo) {
3423                 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
3424                 struct mvpp2_bm_pool *bm_pool;
3425                 struct page_pool *pp = NULL;
3426                 struct sk_buff *skb;
3427                 unsigned int frag_size;
3428                 dma_addr_t dma_addr;
3429                 phys_addr_t phys_addr;
3430                 u32 rx_status;
3431                 int pool, rx_bytes, err, ret;
3432                 void *data;
3433
3434                 rx_done++;
3435                 rx_status = mvpp2_rxdesc_status_get(port, rx_desc);
3436                 rx_bytes = mvpp2_rxdesc_size_get(port, rx_desc);
3437                 rx_bytes -= MVPP2_MH_SIZE;
3438                 dma_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc);
3439                 phys_addr = mvpp2_rxdesc_cookie_get(port, rx_desc);
3440                 data = (void *)phys_to_virt(phys_addr);
3441
3442                 pool = (rx_status & MVPP2_RXD_BM_POOL_ID_MASK) >>
3443                         MVPP2_RXD_BM_POOL_ID_OFFS;
3444                 bm_pool = &port->priv->bm_pools[pool];
3445
3446                 /* In case of an error, release the requested buffer pointer
3447                  * to the Buffer Manager. This request process is controlled
3448                  * by the hardware, and the information about the buffer is
3449                  * comprised by the RX descriptor.
3450                  */
3451                 if (rx_status & MVPP2_RXD_ERR_SUMMARY)
3452                         goto err_drop_frame;
3453
3454                 if (port->priv->percpu_pools) {
3455                         pp = port->priv->page_pool[pool];
3456                         dma_dir = page_pool_get_dma_dir(pp);
3457                 } else {
3458                         dma_dir = DMA_FROM_DEVICE;
3459                 }
3460
3461                 dma_sync_single_for_cpu(dev->dev.parent, dma_addr,
3462                                         rx_bytes + MVPP2_MH_SIZE,
3463                                         dma_dir);
3464
3465                 /* Prefetch header */
3466                 prefetch(data);
3467
3468                 if (bm_pool->frag_size > PAGE_SIZE)
3469                         frag_size = 0;
3470                 else
3471                         frag_size = bm_pool->frag_size;
3472
3473                 if (xdp_prog) {
3474                         xdp.data_hard_start = data;
3475                         xdp.data = data + MVPP2_MH_SIZE + MVPP2_SKB_HEADROOM;
3476                         xdp.data_end = xdp.data + rx_bytes;
3477                         xdp.frame_sz = PAGE_SIZE;
3478
3479                         if (bm_pool->pkt_size == MVPP2_BM_SHORT_PKT_SIZE)
3480                                 xdp.rxq = &rxq->xdp_rxq_short;
3481                         else
3482                                 xdp.rxq = &rxq->xdp_rxq_long;
3483
3484                         xdp_set_data_meta_invalid(&xdp);
3485
3486                         ret = mvpp2_run_xdp(port, rxq, xdp_prog, &xdp, pp, &ps);
3487
3488                         if (ret) {
3489                                 xdp_ret |= ret;
3490                                 err = mvpp2_rx_refill(port, bm_pool, pp, pool);
3491                                 if (err) {
3492                                         netdev_err(port->dev, "failed to refill BM pools\n");
3493                                         goto err_drop_frame;
3494                                 }
3495
3496                                 ps.rx_packets++;
3497                                 ps.rx_bytes += rx_bytes;
3498                                 continue;
3499                         }
3500                 }
3501
3502                 skb = build_skb(data, frag_size);
3503                 if (!skb) {
3504                         netdev_warn(port->dev, "skb build failed\n");
3505                         goto err_drop_frame;
3506                 }
3507
3508                 err = mvpp2_rx_refill(port, bm_pool, pp, pool);
3509                 if (err) {
3510                         netdev_err(port->dev, "failed to refill BM pools\n");
3511                         dev_kfree_skb_any(skb);
3512                         goto err_drop_frame;
3513                 }
3514
3515                 if (pp)
3516                         page_pool_release_page(pp, virt_to_page(data));
3517                 else
3518                         dma_unmap_single_attrs(dev->dev.parent, dma_addr,
3519                                                bm_pool->buf_size, DMA_FROM_DEVICE,
3520                                                DMA_ATTR_SKIP_CPU_SYNC);
3521
3522                 ps.rx_packets++;
3523                 ps.rx_bytes += rx_bytes;
3524
3525                 skb_reserve(skb, MVPP2_MH_SIZE + MVPP2_SKB_HEADROOM);
3526                 skb_put(skb, rx_bytes);
3527                 skb->protocol = eth_type_trans(skb, dev);
3528                 mvpp2_rx_csum(port, rx_status, skb);
3529
3530                 napi_gro_receive(napi, skb);
3531                 continue;
3532
3533 err_drop_frame:
3534                 dev->stats.rx_errors++;
3535                 mvpp2_rx_error(port, rx_desc);
3536                 /* Return the buffer to the pool */
3537                 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr);
3538         }
3539
3540         rcu_read_unlock();
3541
3542         if (xdp_ret & MVPP2_XDP_REDIR)
3543                 xdp_do_flush_map();
3544
3545         if (ps.rx_packets) {
3546                 struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats);
3547
3548                 u64_stats_update_begin(&stats->syncp);
3549                 stats->rx_packets += ps.rx_packets;
3550                 stats->rx_bytes   += ps.rx_bytes;
3551                 /* xdp */
3552                 stats->xdp_redirect += ps.xdp_redirect;
3553                 stats->xdp_pass += ps.xdp_pass;
3554                 stats->xdp_drop += ps.xdp_drop;
3555                 u64_stats_update_end(&stats->syncp);
3556         }
3557
3558         /* Update Rx queue management counters */
3559         wmb();
3560         mvpp2_rxq_status_update(port, rxq->id, rx_done, rx_done);
3561
3562         return rx_todo;
3563 }
3564
3565 static inline void
3566 tx_desc_unmap_put(struct mvpp2_port *port, struct mvpp2_tx_queue *txq,
3567                   struct mvpp2_tx_desc *desc)
3568 {
3569         unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
3570         struct mvpp2_txq_pcpu *txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
3571
3572         dma_addr_t buf_dma_addr =
3573                 mvpp2_txdesc_dma_addr_get(port, desc);
3574         size_t buf_sz =
3575                 mvpp2_txdesc_size_get(port, desc);
3576         if (!IS_TSO_HEADER(txq_pcpu, buf_dma_addr))
3577                 dma_unmap_single(port->dev->dev.parent, buf_dma_addr,
3578                                  buf_sz, DMA_TO_DEVICE);
3579         mvpp2_txq_desc_put(txq);
3580 }
3581
3582 /* Handle tx fragmentation processing */
3583 static int mvpp2_tx_frag_process(struct mvpp2_port *port, struct sk_buff *skb,
3584                                  struct mvpp2_tx_queue *aggr_txq,
3585                                  struct mvpp2_tx_queue *txq)
3586 {
3587         unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
3588         struct mvpp2_txq_pcpu *txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
3589         struct mvpp2_tx_desc *tx_desc;
3590         int i;
3591         dma_addr_t buf_dma_addr;
3592
3593         for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3594                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3595                 void *addr = skb_frag_address(frag);
3596
3597                 tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
3598                 mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
3599                 mvpp2_txdesc_size_set(port, tx_desc, skb_frag_size(frag));
3600
3601                 buf_dma_addr = dma_map_single(port->dev->dev.parent, addr,
3602                                               skb_frag_size(frag),
3603                                               DMA_TO_DEVICE);
3604                 if (dma_mapping_error(port->dev->dev.parent, buf_dma_addr)) {
3605                         mvpp2_txq_desc_put(txq);
3606                         goto cleanup;
3607                 }
3608
3609                 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr);
3610
3611                 if (i == (skb_shinfo(skb)->nr_frags - 1)) {
3612                         /* Last descriptor */
3613                         mvpp2_txdesc_cmd_set(port, tx_desc,
3614                                              MVPP2_TXD_L_DESC);
3615                         mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc, MVPP2_TYPE_SKB);
3616                 } else {
3617                         /* Descriptor in the middle: Not First, Not Last */
3618                         mvpp2_txdesc_cmd_set(port, tx_desc, 0);
3619                         mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB);
3620                 }
3621         }
3622
3623         return 0;
3624 cleanup:
3625         /* Release all descriptors that were used to map fragments of
3626          * this packet, as well as the corresponding DMA mappings
3627          */
3628         for (i = i - 1; i >= 0; i--) {
3629                 tx_desc = txq->descs + i;
3630                 tx_desc_unmap_put(port, txq, tx_desc);
3631         }
3632
3633         return -ENOMEM;
3634 }
3635
3636 static inline void mvpp2_tso_put_hdr(struct sk_buff *skb,
3637                                      struct net_device *dev,
3638                                      struct mvpp2_tx_queue *txq,
3639                                      struct mvpp2_tx_queue *aggr_txq,
3640                                      struct mvpp2_txq_pcpu *txq_pcpu,
3641                                      int hdr_sz)
3642 {
3643         struct mvpp2_port *port = netdev_priv(dev);
3644         struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
3645         dma_addr_t addr;
3646
3647         mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
3648         mvpp2_txdesc_size_set(port, tx_desc, hdr_sz);
3649
3650         addr = txq_pcpu->tso_headers_dma +
3651                txq_pcpu->txq_put_index * TSO_HEADER_SIZE;
3652         mvpp2_txdesc_dma_addr_set(port, tx_desc, addr);
3653
3654         mvpp2_txdesc_cmd_set(port, tx_desc, mvpp2_skb_tx_csum(port, skb) |
3655                                             MVPP2_TXD_F_DESC |
3656                                             MVPP2_TXD_PADDING_DISABLE);
3657         mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB);
3658 }
3659
3660 static inline int mvpp2_tso_put_data(struct sk_buff *skb,
3661                                      struct net_device *dev, struct tso_t *tso,
3662                                      struct mvpp2_tx_queue *txq,
3663                                      struct mvpp2_tx_queue *aggr_txq,
3664                                      struct mvpp2_txq_pcpu *txq_pcpu,
3665                                      int sz, bool left, bool last)
3666 {
3667         struct mvpp2_port *port = netdev_priv(dev);
3668         struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
3669         dma_addr_t buf_dma_addr;
3670
3671         mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
3672         mvpp2_txdesc_size_set(port, tx_desc, sz);
3673
3674         buf_dma_addr = dma_map_single(dev->dev.parent, tso->data, sz,
3675                                       DMA_TO_DEVICE);
3676         if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) {
3677                 mvpp2_txq_desc_put(txq);
3678                 return -ENOMEM;
3679         }
3680
3681         mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr);
3682
3683         if (!left) {
3684                 mvpp2_txdesc_cmd_set(port, tx_desc, MVPP2_TXD_L_DESC);
3685                 if (last) {
3686                         mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc, MVPP2_TYPE_SKB);
3687                         return 0;
3688                 }
3689         } else {
3690                 mvpp2_txdesc_cmd_set(port, tx_desc, 0);
3691         }
3692
3693         mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB);
3694         return 0;
3695 }
3696
3697 static int mvpp2_tx_tso(struct sk_buff *skb, struct net_device *dev,
3698                         struct mvpp2_tx_queue *txq,
3699                         struct mvpp2_tx_queue *aggr_txq,
3700                         struct mvpp2_txq_pcpu *txq_pcpu)
3701 {
3702         struct mvpp2_port *port = netdev_priv(dev);
3703         int hdr_sz, i, len, descs = 0;
3704         struct tso_t tso;
3705
3706         /* Check number of available descriptors */
3707         if (mvpp2_aggr_desc_num_check(port, aggr_txq, tso_count_descs(skb)) ||
3708             mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu,
3709                                              tso_count_descs(skb)))
3710                 return 0;
3711
3712         hdr_sz = tso_start(skb, &tso);
3713
3714         len = skb->len - hdr_sz;
3715         while (len > 0) {
3716                 int left = min_t(int, skb_shinfo(skb)->gso_size, len);
3717                 char *hdr = txq_pcpu->tso_headers +
3718                             txq_pcpu->txq_put_index * TSO_HEADER_SIZE;
3719
3720                 len -= left;
3721                 descs++;
3722
3723                 tso_build_hdr(skb, hdr, &tso, left, len == 0);
3724                 mvpp2_tso_put_hdr(skb, dev, txq, aggr_txq, txq_pcpu, hdr_sz);
3725
3726                 while (left > 0) {
3727                         int sz = min_t(int, tso.size, left);
3728                         left -= sz;
3729                         descs++;
3730
3731                         if (mvpp2_tso_put_data(skb, dev, &tso, txq, aggr_txq,
3732                                                txq_pcpu, sz, left, len == 0))
3733                                 goto release;
3734                         tso_build_data(skb, &tso, sz);
3735                 }
3736         }
3737
3738         return descs;
3739
3740 release:
3741         for (i = descs - 1; i >= 0; i--) {
3742                 struct mvpp2_tx_desc *tx_desc = txq->descs + i;
3743                 tx_desc_unmap_put(port, txq, tx_desc);
3744         }
3745         return 0;
3746 }
3747
3748 /* Main tx processing */
3749 static netdev_tx_t mvpp2_tx(struct sk_buff *skb, struct net_device *dev)
3750 {
3751         struct mvpp2_port *port = netdev_priv(dev);
3752         struct mvpp2_tx_queue *txq, *aggr_txq;
3753         struct mvpp2_txq_pcpu *txq_pcpu;
3754         struct mvpp2_tx_desc *tx_desc;
3755         dma_addr_t buf_dma_addr;
3756         unsigned long flags = 0;
3757         unsigned int thread;
3758         int frags = 0;
3759         u16 txq_id;
3760         u32 tx_cmd;
3761
3762         thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
3763
3764         txq_id = skb_get_queue_mapping(skb);
3765         txq = port->txqs[txq_id];
3766         txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
3767         aggr_txq = &port->priv->aggr_txqs[thread];
3768
3769         if (test_bit(thread, &port->priv->lock_map))
3770                 spin_lock_irqsave(&port->tx_lock[thread], flags);
3771
3772         if (skb_is_gso(skb)) {
3773                 frags = mvpp2_tx_tso(skb, dev, txq, aggr_txq, txq_pcpu);
3774                 goto out;
3775         }
3776         frags = skb_shinfo(skb)->nr_frags + 1;
3777
3778         /* Check number of available descriptors */
3779         if (mvpp2_aggr_desc_num_check(port, aggr_txq, frags) ||
3780             mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu, frags)) {
3781                 frags = 0;
3782                 goto out;
3783         }
3784
3785         /* Get a descriptor for the first part of the packet */
3786         tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
3787         mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
3788         mvpp2_txdesc_size_set(port, tx_desc, skb_headlen(skb));
3789
3790         buf_dma_addr = dma_map_single(dev->dev.parent, skb->data,
3791                                       skb_headlen(skb), DMA_TO_DEVICE);
3792         if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) {
3793                 mvpp2_txq_desc_put(txq);
3794                 frags = 0;
3795                 goto out;
3796         }
3797
3798         mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr);
3799
3800         tx_cmd = mvpp2_skb_tx_csum(port, skb);
3801
3802         if (frags == 1) {
3803                 /* First and Last descriptor */
3804                 tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC;
3805                 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd);
3806                 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc, MVPP2_TYPE_SKB);
3807         } else {
3808                 /* First but not Last */
3809                 tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_PADDING_DISABLE;
3810                 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd);
3811                 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB);
3812
3813                 /* Continue with other skb fragments */
3814                 if (mvpp2_tx_frag_process(port, skb, aggr_txq, txq)) {
3815                         tx_desc_unmap_put(port, txq, tx_desc);
3816                         frags = 0;
3817                 }
3818         }
3819
3820 out:
3821         if (frags > 0) {
3822                 struct mvpp2_pcpu_stats *stats = per_cpu_ptr(port->stats, thread);
3823                 struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id);
3824
3825                 txq_pcpu->reserved_num -= frags;
3826                 txq_pcpu->count += frags;
3827                 aggr_txq->count += frags;
3828
3829                 /* Enable transmit */
3830                 wmb();
3831                 mvpp2_aggr_txq_pend_desc_add(port, frags);
3832
3833                 if (txq_pcpu->count >= txq_pcpu->stop_threshold)
3834                         netif_tx_stop_queue(nq);
3835
3836                 u64_stats_update_begin(&stats->syncp);
3837                 stats->tx_packets++;
3838                 stats->tx_bytes += skb->len;
3839                 u64_stats_update_end(&stats->syncp);
3840         } else {
3841                 dev->stats.tx_dropped++;
3842                 dev_kfree_skb_any(skb);
3843         }
3844
3845         /* Finalize TX processing */
3846         if (!port->has_tx_irqs && txq_pcpu->count >= txq->done_pkts_coal)
3847                 mvpp2_txq_done(port, txq, txq_pcpu);
3848
3849         /* Set the timer in case not all frags were processed */
3850         if (!port->has_tx_irqs && txq_pcpu->count <= frags &&
3851             txq_pcpu->count > 0) {
3852                 struct mvpp2_port_pcpu *port_pcpu = per_cpu_ptr(port->pcpu, thread);
3853
3854                 if (!port_pcpu->timer_scheduled) {
3855                         port_pcpu->timer_scheduled = true;
3856                         hrtimer_start(&port_pcpu->tx_done_timer,
3857                                       MVPP2_TXDONE_HRTIMER_PERIOD_NS,
3858                                       HRTIMER_MODE_REL_PINNED_SOFT);
3859                 }
3860         }
3861
3862         if (test_bit(thread, &port->priv->lock_map))
3863                 spin_unlock_irqrestore(&port->tx_lock[thread], flags);
3864
3865         return NETDEV_TX_OK;
3866 }
3867
3868 static inline void mvpp2_cause_error(struct net_device *dev, int cause)
3869 {
3870         if (cause & MVPP2_CAUSE_FCS_ERR_MASK)
3871                 netdev_err(dev, "FCS error\n");
3872         if (cause & MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK)
3873                 netdev_err(dev, "rx fifo overrun error\n");
3874         if (cause & MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK)
3875                 netdev_err(dev, "tx fifo underrun error\n");
3876 }
3877
3878 static int mvpp2_poll(struct napi_struct *napi, int budget)
3879 {
3880         u32 cause_rx_tx, cause_rx, cause_tx, cause_misc;
3881         int rx_done = 0;
3882         struct mvpp2_port *port = netdev_priv(napi->dev);
3883         struct mvpp2_queue_vector *qv;
3884         unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
3885
3886         qv = container_of(napi, struct mvpp2_queue_vector, napi);
3887
3888         /* Rx/Tx cause register
3889          *
3890          * Bits 0-15: each bit indicates received packets on the Rx queue
3891          * (bit 0 is for Rx queue 0).
3892          *
3893          * Bits 16-23: each bit indicates transmitted packets on the Tx queue
3894          * (bit 16 is for Tx queue 0).
3895          *
3896          * Each CPU has its own Rx/Tx cause register
3897          */
3898         cause_rx_tx = mvpp2_thread_read_relaxed(port->priv, qv->sw_thread_id,
3899                                                 MVPP2_ISR_RX_TX_CAUSE_REG(port->id));
3900
3901         cause_misc = cause_rx_tx & MVPP2_CAUSE_MISC_SUM_MASK;
3902         if (cause_misc) {
3903                 mvpp2_cause_error(port->dev, cause_misc);
3904
3905                 /* Clear the cause register */
3906                 mvpp2_write(port->priv, MVPP2_ISR_MISC_CAUSE_REG, 0);
3907                 mvpp2_thread_write(port->priv, thread,
3908                                    MVPP2_ISR_RX_TX_CAUSE_REG(port->id),
3909                                    cause_rx_tx & ~MVPP2_CAUSE_MISC_SUM_MASK);
3910         }
3911
3912         if (port->has_tx_irqs) {
3913                 cause_tx = cause_rx_tx & MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK;
3914                 if (cause_tx) {
3915                         cause_tx >>= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_OFFSET;
3916                         mvpp2_tx_done(port, cause_tx, qv->sw_thread_id);
3917                 }
3918         }
3919
3920         /* Process RX packets */
3921         cause_rx = cause_rx_tx &
3922                    MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version);
3923         cause_rx <<= qv->first_rxq;
3924         cause_rx |= qv->pending_cause_rx;
3925         while (cause_rx && budget > 0) {
3926                 int count;
3927                 struct mvpp2_rx_queue *rxq;
3928
3929                 rxq = mvpp2_get_rx_queue(port, cause_rx);
3930                 if (!rxq)
3931                         break;
3932
3933                 count = mvpp2_rx(port, napi, budget, rxq);
3934                 rx_done += count;
3935                 budget -= count;
3936                 if (budget > 0) {
3937                         /* Clear the bit associated to this Rx queue
3938                          * so that next iteration will continue from
3939                          * the next Rx queue.
3940                          */
3941                         cause_rx &= ~(1 << rxq->logic_rxq);
3942                 }
3943         }
3944
3945         if (budget > 0) {
3946                 cause_rx = 0;
3947                 napi_complete_done(napi, rx_done);
3948
3949                 mvpp2_qvec_interrupt_enable(qv);
3950         }
3951         qv->pending_cause_rx = cause_rx;
3952         return rx_done;
3953 }
3954
3955 static void mvpp22_mode_reconfigure(struct mvpp2_port *port)
3956 {
3957         u32 ctrl3;
3958
3959         /* Set the GMAC & XLG MAC in reset */
3960         mvpp2_mac_reset_assert(port);
3961
3962         /* Set the MPCS and XPCS in reset */
3963         mvpp22_pcs_reset_assert(port);
3964
3965         /* comphy reconfiguration */
3966         mvpp22_comphy_init(port);
3967
3968         /* gop reconfiguration */
3969         mvpp22_gop_init(port);
3970
3971         mvpp22_pcs_reset_deassert(port);
3972
3973         if (mvpp2_port_supports_xlg(port)) {
3974                 ctrl3 = readl(port->base + MVPP22_XLG_CTRL3_REG);
3975                 ctrl3 &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
3976
3977                 if (mvpp2_is_xlg(port->phy_interface))
3978                         ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_10G;
3979                 else
3980                         ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_GMAC;
3981
3982                 writel(ctrl3, port->base + MVPP22_XLG_CTRL3_REG);
3983         }
3984
3985         if (mvpp2_port_supports_xlg(port) && mvpp2_is_xlg(port->phy_interface))
3986                 mvpp2_xlg_max_rx_size_set(port);
3987         else
3988                 mvpp2_gmac_max_rx_size_set(port);
3989 }
3990
3991 /* Set hw internals when starting port */
3992 static void mvpp2_start_dev(struct mvpp2_port *port)
3993 {
3994         int i;
3995
3996         mvpp2_txp_max_tx_size_set(port);
3997
3998         for (i = 0; i < port->nqvecs; i++)
3999                 napi_enable(&port->qvecs[i].napi);
4000
4001         /* Enable interrupts on all threads */
4002         mvpp2_interrupts_enable(port);
4003
4004         if (port->priv->hw_version == MVPP22)
4005                 mvpp22_mode_reconfigure(port);
4006
4007         if (port->phylink) {
4008                 phylink_start(port->phylink);
4009         } else {
4010                 /* Phylink isn't used as of now for ACPI, so the MAC has to be
4011                  * configured manually when the interface is started. This will
4012                  * be removed as soon as the phylink ACPI support lands in.
4013                  */
4014                 struct phylink_link_state state = {
4015                         .interface = port->phy_interface,
4016                 };
4017                 mvpp2_mac_config(&port->phylink_config, MLO_AN_INBAND, &state);
4018                 mvpp2_mac_link_up(&port->phylink_config, NULL,
4019                                   MLO_AN_INBAND, port->phy_interface,
4020                                   SPEED_UNKNOWN, DUPLEX_UNKNOWN, false, false);
4021         }
4022
4023         netif_tx_start_all_queues(port->dev);
4024
4025         clear_bit(0, &port->state);
4026 }
4027
4028 /* Set hw internals when stopping port */
4029 static void mvpp2_stop_dev(struct mvpp2_port *port)
4030 {
4031         int i;
4032
4033         set_bit(0, &port->state);
4034
4035         /* Disable interrupts on all threads */
4036         mvpp2_interrupts_disable(port);
4037
4038         for (i = 0; i < port->nqvecs; i++)
4039                 napi_disable(&port->qvecs[i].napi);
4040
4041         if (port->phylink)
4042                 phylink_stop(port->phylink);
4043         phy_power_off(port->comphy);
4044 }
4045
4046 static int mvpp2_check_ringparam_valid(struct net_device *dev,
4047                                        struct ethtool_ringparam *ring)
4048 {
4049         u16 new_rx_pending = ring->rx_pending;
4050         u16 new_tx_pending = ring->tx_pending;
4051
4052         if (ring->rx_pending == 0 || ring->tx_pending == 0)
4053                 return -EINVAL;
4054
4055         if (ring->rx_pending > MVPP2_MAX_RXD_MAX)
4056                 new_rx_pending = MVPP2_MAX_RXD_MAX;
4057         else if (!IS_ALIGNED(ring->rx_pending, 16))
4058                 new_rx_pending = ALIGN(ring->rx_pending, 16);
4059
4060         if (ring->tx_pending > MVPP2_MAX_TXD_MAX)
4061                 new_tx_pending = MVPP2_MAX_TXD_MAX;
4062         else if (!IS_ALIGNED(ring->tx_pending, 32))
4063                 new_tx_pending = ALIGN(ring->tx_pending, 32);
4064
4065         /* The Tx ring size cannot be smaller than the minimum number of
4066          * descriptors needed for TSO.
4067          */
4068         if (new_tx_pending < MVPP2_MAX_SKB_DESCS)
4069                 new_tx_pending = ALIGN(MVPP2_MAX_SKB_DESCS, 32);
4070
4071         if (ring->rx_pending != new_rx_pending) {
4072                 netdev_info(dev, "illegal Rx ring size value %d, round to %d\n",
4073                             ring->rx_pending, new_rx_pending);
4074                 ring->rx_pending = new_rx_pending;
4075         }
4076
4077         if (ring->tx_pending != new_tx_pending) {
4078                 netdev_info(dev, "illegal Tx ring size value %d, round to %d\n",
4079                             ring->tx_pending, new_tx_pending);
4080                 ring->tx_pending = new_tx_pending;
4081         }
4082
4083         return 0;
4084 }
4085
4086 static void mvpp21_get_mac_address(struct mvpp2_port *port, unsigned char *addr)
4087 {
4088         u32 mac_addr_l, mac_addr_m, mac_addr_h;
4089
4090         mac_addr_l = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
4091         mac_addr_m = readl(port->priv->lms_base + MVPP2_SRC_ADDR_MIDDLE);
4092         mac_addr_h = readl(port->priv->lms_base + MVPP2_SRC_ADDR_HIGH);
4093         addr[0] = (mac_addr_h >> 24) & 0xFF;
4094         addr[1] = (mac_addr_h >> 16) & 0xFF;
4095         addr[2] = (mac_addr_h >> 8) & 0xFF;
4096         addr[3] = mac_addr_h & 0xFF;
4097         addr[4] = mac_addr_m & 0xFF;
4098         addr[5] = (mac_addr_l >> MVPP2_GMAC_SA_LOW_OFFS) & 0xFF;
4099 }
4100
4101 static int mvpp2_irqs_init(struct mvpp2_port *port)
4102 {
4103         int err, i;
4104
4105         for (i = 0; i < port->nqvecs; i++) {
4106                 struct mvpp2_queue_vector *qv = port->qvecs + i;
4107
4108                 if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE) {
4109                         qv->mask = kzalloc(cpumask_size(), GFP_KERNEL);
4110                         if (!qv->mask) {
4111                                 err = -ENOMEM;
4112                                 goto err;
4113                         }
4114
4115                         irq_set_status_flags(qv->irq, IRQ_NO_BALANCING);
4116                 }
4117
4118                 err = request_irq(qv->irq, mvpp2_isr, 0, port->dev->name, qv);
4119                 if (err)
4120                         goto err;
4121
4122                 if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE) {
4123                         unsigned int cpu;
4124
4125                         for_each_present_cpu(cpu) {
4126                                 if (mvpp2_cpu_to_thread(port->priv, cpu) ==
4127                                     qv->sw_thread_id)
4128                                         cpumask_set_cpu(cpu, qv->mask);
4129                         }
4130
4131                         irq_set_affinity_hint(qv->irq, qv->mask);
4132                 }
4133         }
4134
4135         return 0;
4136 err:
4137         for (i = 0; i < port->nqvecs; i++) {
4138                 struct mvpp2_queue_vector *qv = port->qvecs + i;
4139
4140                 irq_set_affinity_hint(qv->irq, NULL);
4141                 kfree(qv->mask);
4142                 qv->mask = NULL;
4143                 free_irq(qv->irq, qv);
4144         }
4145
4146         return err;
4147 }
4148
4149 static void mvpp2_irqs_deinit(struct mvpp2_port *port)
4150 {
4151         int i;
4152
4153         for (i = 0; i < port->nqvecs; i++) {
4154                 struct mvpp2_queue_vector *qv = port->qvecs + i;
4155
4156                 irq_set_affinity_hint(qv->irq, NULL);
4157                 kfree(qv->mask);
4158                 qv->mask = NULL;
4159                 irq_clear_status_flags(qv->irq, IRQ_NO_BALANCING);
4160                 free_irq(qv->irq, qv);
4161         }
4162 }
4163
4164 static bool mvpp22_rss_is_supported(void)
4165 {
4166         return queue_mode == MVPP2_QDIST_MULTI_MODE;
4167 }
4168
4169 static int mvpp2_open(struct net_device *dev)
4170 {
4171         struct mvpp2_port *port = netdev_priv(dev);
4172         struct mvpp2 *priv = port->priv;
4173         unsigned char mac_bcast[ETH_ALEN] = {
4174                         0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
4175         bool valid = false;
4176         int err;
4177
4178         err = mvpp2_prs_mac_da_accept(port, mac_bcast, true);
4179         if (err) {
4180                 netdev_err(dev, "mvpp2_prs_mac_da_accept BC failed\n");
4181                 return err;
4182         }
4183         err = mvpp2_prs_mac_da_accept(port, dev->dev_addr, true);
4184         if (err) {
4185                 netdev_err(dev, "mvpp2_prs_mac_da_accept own addr failed\n");
4186                 return err;
4187         }
4188         err = mvpp2_prs_tag_mode_set(port->priv, port->id, MVPP2_TAG_TYPE_MH);
4189         if (err) {
4190                 netdev_err(dev, "mvpp2_prs_tag_mode_set failed\n");
4191                 return err;
4192         }
4193         err = mvpp2_prs_def_flow(port);
4194         if (err) {
4195                 netdev_err(dev, "mvpp2_prs_def_flow failed\n");
4196                 return err;
4197         }
4198
4199         /* Allocate the Rx/Tx queues */
4200         err = mvpp2_setup_rxqs(port);
4201         if (err) {
4202                 netdev_err(port->dev, "cannot allocate Rx queues\n");
4203                 return err;
4204         }
4205
4206         err = mvpp2_setup_txqs(port);
4207         if (err) {
4208                 netdev_err(port->dev, "cannot allocate Tx queues\n");
4209                 goto err_cleanup_rxqs;
4210         }
4211
4212         err = mvpp2_irqs_init(port);
4213         if (err) {
4214                 netdev_err(port->dev, "cannot init IRQs\n");
4215                 goto err_cleanup_txqs;
4216         }
4217
4218         /* Phylink isn't supported yet in ACPI mode */
4219         if (port->of_node) {
4220                 err = phylink_of_phy_connect(port->phylink, port->of_node, 0);
4221                 if (err) {
4222                         netdev_err(port->dev, "could not attach PHY (%d)\n",
4223                                    err);
4224                         goto err_free_irq;
4225                 }
4226
4227                 valid = true;
4228         }
4229
4230         if (priv->hw_version == MVPP22 && port->link_irq) {
4231                 err = request_irq(port->link_irq, mvpp2_link_status_isr, 0,
4232                                   dev->name, port);
4233                 if (err) {
4234                         netdev_err(port->dev, "cannot request link IRQ %d\n",
4235                                    port->link_irq);
4236                         goto err_free_irq;
4237                 }
4238
4239                 mvpp22_gop_setup_irq(port);
4240
4241                 /* In default link is down */
4242                 netif_carrier_off(port->dev);
4243
4244                 valid = true;
4245         } else {
4246                 port->link_irq = 0;
4247         }
4248
4249         if (!valid) {
4250                 netdev_err(port->dev,
4251                            "invalid configuration: no dt or link IRQ");
4252                 goto err_free_irq;
4253         }
4254
4255         /* Unmask interrupts on all CPUs */
4256         on_each_cpu(mvpp2_interrupts_unmask, port, 1);
4257         mvpp2_shared_interrupt_mask_unmask(port, false);
4258
4259         mvpp2_start_dev(port);
4260
4261         /* Start hardware statistics gathering */
4262         queue_delayed_work(priv->stats_queue, &port->stats_work,
4263                            MVPP2_MIB_COUNTERS_STATS_DELAY);
4264
4265         return 0;
4266
4267 err_free_irq:
4268         mvpp2_irqs_deinit(port);
4269 err_cleanup_txqs:
4270         mvpp2_cleanup_txqs(port);
4271 err_cleanup_rxqs:
4272         mvpp2_cleanup_rxqs(port);
4273         return err;
4274 }
4275
4276 static int mvpp2_stop(struct net_device *dev)
4277 {
4278         struct mvpp2_port *port = netdev_priv(dev);
4279         struct mvpp2_port_pcpu *port_pcpu;
4280         unsigned int thread;
4281
4282         mvpp2_stop_dev(port);
4283
4284         /* Mask interrupts on all threads */
4285         on_each_cpu(mvpp2_interrupts_mask, port, 1);
4286         mvpp2_shared_interrupt_mask_unmask(port, true);
4287
4288         if (port->phylink)
4289                 phylink_disconnect_phy(port->phylink);
4290         if (port->link_irq)
4291                 free_irq(port->link_irq, port);
4292
4293         mvpp2_irqs_deinit(port);
4294         if (!port->has_tx_irqs) {
4295                 for (thread = 0; thread < port->priv->nthreads; thread++) {
4296                         port_pcpu = per_cpu_ptr(port->pcpu, thread);
4297
4298                         hrtimer_cancel(&port_pcpu->tx_done_timer);
4299                         port_pcpu->timer_scheduled = false;
4300                 }
4301         }
4302         mvpp2_cleanup_rxqs(port);
4303         mvpp2_cleanup_txqs(port);
4304
4305         cancel_delayed_work_sync(&port->stats_work);
4306
4307         mvpp2_mac_reset_assert(port);
4308         mvpp22_pcs_reset_assert(port);
4309
4310         return 0;
4311 }
4312
4313 static int mvpp2_prs_mac_da_accept_list(struct mvpp2_port *port,
4314                                         struct netdev_hw_addr_list *list)
4315 {
4316         struct netdev_hw_addr *ha;
4317         int ret;
4318
4319         netdev_hw_addr_list_for_each(ha, list) {
4320                 ret = mvpp2_prs_mac_da_accept(port, ha->addr, true);
4321                 if (ret)
4322                         return ret;
4323         }
4324
4325         return 0;
4326 }
4327
4328 static void mvpp2_set_rx_promisc(struct mvpp2_port *port, bool enable)
4329 {
4330         if (!enable && (port->dev->features & NETIF_F_HW_VLAN_CTAG_FILTER))
4331                 mvpp2_prs_vid_enable_filtering(port);
4332         else
4333                 mvpp2_prs_vid_disable_filtering(port);
4334
4335         mvpp2_prs_mac_promisc_set(port->priv, port->id,
4336                                   MVPP2_PRS_L2_UNI_CAST, enable);
4337
4338         mvpp2_prs_mac_promisc_set(port->priv, port->id,
4339                                   MVPP2_PRS_L2_MULTI_CAST, enable);
4340 }
4341
4342 static void mvpp2_set_rx_mode(struct net_device *dev)
4343 {
4344         struct mvpp2_port *port = netdev_priv(dev);
4345
4346         /* Clear the whole UC and MC list */
4347         mvpp2_prs_mac_del_all(port);
4348
4349         if (dev->flags & IFF_PROMISC) {
4350                 mvpp2_set_rx_promisc(port, true);
4351                 return;
4352         }
4353
4354         mvpp2_set_rx_promisc(port, false);
4355
4356         if (netdev_uc_count(dev) > MVPP2_PRS_MAC_UC_FILT_MAX ||
4357             mvpp2_prs_mac_da_accept_list(port, &dev->uc))
4358                 mvpp2_prs_mac_promisc_set(port->priv, port->id,
4359                                           MVPP2_PRS_L2_UNI_CAST, true);
4360
4361         if (dev->flags & IFF_ALLMULTI) {
4362                 mvpp2_prs_mac_promisc_set(port->priv, port->id,
4363                                           MVPP2_PRS_L2_MULTI_CAST, true);
4364                 return;
4365         }
4366
4367         if (netdev_mc_count(dev) > MVPP2_PRS_MAC_MC_FILT_MAX ||
4368             mvpp2_prs_mac_da_accept_list(port, &dev->mc))
4369                 mvpp2_prs_mac_promisc_set(port->priv, port->id,
4370                                           MVPP2_PRS_L2_MULTI_CAST, true);
4371 }
4372
4373 static int mvpp2_set_mac_address(struct net_device *dev, void *p)
4374 {
4375         const struct sockaddr *addr = p;
4376         int err;
4377
4378         if (!is_valid_ether_addr(addr->sa_data))
4379                 return -EADDRNOTAVAIL;
4380
4381         err = mvpp2_prs_update_mac_da(dev, addr->sa_data);
4382         if (err) {
4383                 /* Reconfigure parser accept the original MAC address */
4384                 mvpp2_prs_update_mac_da(dev, dev->dev_addr);
4385                 netdev_err(dev, "failed to change MAC address\n");
4386         }
4387         return err;
4388 }
4389
4390 /* Shut down all the ports, reconfigure the pools as percpu or shared,
4391  * then bring up again all ports.
4392  */
4393 static int mvpp2_bm_switch_buffers(struct mvpp2 *priv, bool percpu)
4394 {
4395         int numbufs = MVPP2_BM_POOLS_NUM, i;
4396         struct mvpp2_port *port = NULL;
4397         bool status[MVPP2_MAX_PORTS];
4398
4399         for (i = 0; i < priv->port_count; i++) {
4400                 port = priv->port_list[i];
4401                 status[i] = netif_running(port->dev);
4402                 if (status[i])
4403                         mvpp2_stop(port->dev);
4404         }
4405
4406         /* nrxqs is the same for all ports */
4407         if (priv->percpu_pools)
4408                 numbufs = port->nrxqs * 2;
4409
4410         for (i = 0; i < numbufs; i++)
4411                 mvpp2_bm_pool_destroy(port->dev->dev.parent, priv, &priv->bm_pools[i]);
4412
4413         devm_kfree(port->dev->dev.parent, priv->bm_pools);
4414         priv->percpu_pools = percpu;
4415         mvpp2_bm_init(port->dev->dev.parent, priv);
4416
4417         for (i = 0; i < priv->port_count; i++) {
4418                 port = priv->port_list[i];
4419                 mvpp2_swf_bm_pool_init(port);
4420                 if (status[i])
4421                         mvpp2_open(port->dev);
4422         }
4423
4424         return 0;
4425 }
4426
4427 static int mvpp2_change_mtu(struct net_device *dev, int mtu)
4428 {
4429         struct mvpp2_port *port = netdev_priv(dev);
4430         bool running = netif_running(dev);
4431         struct mvpp2 *priv = port->priv;
4432         int err;
4433
4434         if (!IS_ALIGNED(MVPP2_RX_PKT_SIZE(mtu), 8)) {
4435                 netdev_info(dev, "illegal MTU value %d, round to %d\n", mtu,
4436                             ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8));
4437                 mtu = ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8);
4438         }
4439
4440         if (MVPP2_RX_PKT_SIZE(mtu) > MVPP2_BM_LONG_PKT_SIZE) {
4441                 if (port->xdp_prog) {
4442                         netdev_err(dev, "Jumbo frames are not supported with XDP\n");
4443                         return -EINVAL;
4444                 }
4445                 if (priv->percpu_pools) {
4446                         netdev_warn(dev, "mtu %d too high, switching to shared buffers", mtu);
4447                         mvpp2_bm_switch_buffers(priv, false);
4448                 }
4449         } else {
4450                 bool jumbo = false;
4451                 int i;
4452
4453                 for (i = 0; i < priv->port_count; i++)
4454                         if (priv->port_list[i] != port &&
4455                             MVPP2_RX_PKT_SIZE(priv->port_list[i]->dev->mtu) >
4456                             MVPP2_BM_LONG_PKT_SIZE) {
4457                                 jumbo = true;
4458                                 break;
4459                         }
4460
4461                 /* No port is using jumbo frames */
4462                 if (!jumbo) {
4463                         dev_info(port->dev->dev.parent,
4464                                  "all ports have a low MTU, switching to per-cpu buffers");
4465                         mvpp2_bm_switch_buffers(priv, true);
4466                 }
4467         }
4468
4469         if (running)
4470                 mvpp2_stop_dev(port);
4471
4472         err = mvpp2_bm_update_mtu(dev, mtu);
4473         if (err) {
4474                 netdev_err(dev, "failed to change MTU\n");
4475                 /* Reconfigure BM to the original MTU */
4476                 mvpp2_bm_update_mtu(dev, dev->mtu);
4477         } else {
4478                 port->pkt_size =  MVPP2_RX_PKT_SIZE(mtu);
4479         }
4480
4481         if (running) {
4482                 mvpp2_start_dev(port);
4483                 mvpp2_egress_enable(port);
4484                 mvpp2_ingress_enable(port);
4485         }
4486
4487         return err;
4488 }
4489
4490 static int mvpp2_check_pagepool_dma(struct mvpp2_port *port)
4491 {
4492         enum dma_data_direction dma_dir = DMA_FROM_DEVICE;
4493         struct mvpp2 *priv = port->priv;
4494         int err = -1, i;
4495
4496         if (!priv->percpu_pools)
4497                 return err;
4498
4499         if (!priv->page_pool[0])
4500                 return -ENOMEM;
4501
4502         for (i = 0; i < priv->port_count; i++) {
4503                 port = priv->port_list[i];
4504                 if (port->xdp_prog) {
4505                         dma_dir = DMA_BIDIRECTIONAL;
4506                         break;
4507                 }
4508         }
4509
4510         /* All pools are equal in terms of DMA direction */
4511         if (priv->page_pool[0]->p.dma_dir != dma_dir)
4512                 err = mvpp2_bm_switch_buffers(priv, true);
4513
4514         return err;
4515 }
4516
4517 static void
4518 mvpp2_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
4519 {
4520         struct mvpp2_port *port = netdev_priv(dev);
4521         unsigned int start;
4522         unsigned int cpu;
4523
4524         for_each_possible_cpu(cpu) {
4525                 struct mvpp2_pcpu_stats *cpu_stats;
4526                 u64 rx_packets;
4527                 u64 rx_bytes;
4528                 u64 tx_packets;
4529                 u64 tx_bytes;
4530
4531                 cpu_stats = per_cpu_ptr(port->stats, cpu);
4532                 do {
4533                         start = u64_stats_fetch_begin_irq(&cpu_stats->syncp);
4534                         rx_packets = cpu_stats->rx_packets;
4535                         rx_bytes   = cpu_stats->rx_bytes;
4536                         tx_packets = cpu_stats->tx_packets;
4537                         tx_bytes   = cpu_stats->tx_bytes;
4538                 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start));
4539
4540                 stats->rx_packets += rx_packets;
4541                 stats->rx_bytes   += rx_bytes;
4542                 stats->tx_packets += tx_packets;
4543                 stats->tx_bytes   += tx_bytes;
4544         }
4545
4546         stats->rx_errors        = dev->stats.rx_errors;
4547         stats->rx_dropped       = dev->stats.rx_dropped;
4548         stats->tx_dropped       = dev->stats.tx_dropped;
4549 }
4550
4551 static int mvpp2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4552 {
4553         struct mvpp2_port *port = netdev_priv(dev);
4554
4555         if (!port->phylink)
4556                 return -ENOTSUPP;
4557
4558         return phylink_mii_ioctl(port->phylink, ifr, cmd);
4559 }
4560
4561 static int mvpp2_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid)
4562 {
4563         struct mvpp2_port *port = netdev_priv(dev);
4564         int ret;
4565
4566         ret = mvpp2_prs_vid_entry_add(port, vid);
4567         if (ret)
4568                 netdev_err(dev, "rx-vlan-filter offloading cannot accept more than %d VIDs per port\n",
4569                            MVPP2_PRS_VLAN_FILT_MAX - 1);
4570         return ret;
4571 }
4572
4573 static int mvpp2_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid)
4574 {
4575         struct mvpp2_port *port = netdev_priv(dev);
4576
4577         mvpp2_prs_vid_entry_remove(port, vid);
4578         return 0;
4579 }
4580
4581 static int mvpp2_set_features(struct net_device *dev,
4582                               netdev_features_t features)
4583 {
4584         netdev_features_t changed = dev->features ^ features;
4585         struct mvpp2_port *port = netdev_priv(dev);
4586
4587         if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) {
4588                 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) {
4589                         mvpp2_prs_vid_enable_filtering(port);
4590                 } else {
4591                         /* Invalidate all registered VID filters for this
4592                          * port
4593                          */
4594                         mvpp2_prs_vid_remove_all(port);
4595
4596                         mvpp2_prs_vid_disable_filtering(port);
4597                 }
4598         }
4599
4600         if (changed & NETIF_F_RXHASH) {
4601                 if (features & NETIF_F_RXHASH)
4602                         mvpp22_port_rss_enable(port);
4603                 else
4604                         mvpp22_port_rss_disable(port);
4605         }
4606
4607         return 0;
4608 }
4609
4610 static int mvpp2_xdp_setup(struct mvpp2_port *port, struct netdev_bpf *bpf)
4611 {
4612         struct bpf_prog *prog = bpf->prog, *old_prog;
4613         bool running = netif_running(port->dev);
4614         bool reset = !prog != !port->xdp_prog;
4615
4616         if (port->dev->mtu > ETH_DATA_LEN) {
4617                 NL_SET_ERR_MSG_MOD(bpf->extack, "XDP is not supported with jumbo frames enabled");
4618                 return -EOPNOTSUPP;
4619         }
4620
4621         if (!port->priv->percpu_pools) {
4622                 NL_SET_ERR_MSG_MOD(bpf->extack, "Per CPU Pools required for XDP");
4623                 return -EOPNOTSUPP;
4624         }
4625
4626         if (port->ntxqs < num_possible_cpus() * 2) {
4627                 NL_SET_ERR_MSG_MOD(bpf->extack, "XDP_TX needs two TX queues per CPU");
4628                 return -EOPNOTSUPP;
4629         }
4630
4631         /* device is up and bpf is added/removed, must setup the RX queues */
4632         if (running && reset)
4633                 mvpp2_stop(port->dev);
4634
4635         old_prog = xchg(&port->xdp_prog, prog);
4636         if (old_prog)
4637                 bpf_prog_put(old_prog);
4638
4639         /* bpf is just replaced, RXQ and MTU are already setup */
4640         if (!reset)
4641                 return 0;
4642
4643         /* device was up, restore the link */
4644         if (running)
4645                 mvpp2_open(port->dev);
4646
4647         /* Check Page Pool DMA Direction */
4648         mvpp2_check_pagepool_dma(port);
4649
4650         return 0;
4651 }
4652
4653 static int mvpp2_xdp(struct net_device *dev, struct netdev_bpf *xdp)
4654 {
4655         struct mvpp2_port *port = netdev_priv(dev);
4656
4657         switch (xdp->command) {
4658         case XDP_SETUP_PROG:
4659                 return mvpp2_xdp_setup(port, xdp);
4660         default:
4661                 return -EINVAL;
4662         }
4663 }
4664
4665 /* Ethtool methods */
4666
4667 static int mvpp2_ethtool_nway_reset(struct net_device *dev)
4668 {
4669         struct mvpp2_port *port = netdev_priv(dev);
4670
4671         if (!port->phylink)
4672                 return -ENOTSUPP;
4673
4674         return phylink_ethtool_nway_reset(port->phylink);
4675 }
4676
4677 /* Set interrupt coalescing for ethtools */
4678 static int mvpp2_ethtool_set_coalesce(struct net_device *dev,
4679                                       struct ethtool_coalesce *c)
4680 {
4681         struct mvpp2_port *port = netdev_priv(dev);
4682         int queue;
4683
4684         for (queue = 0; queue < port->nrxqs; queue++) {
4685                 struct mvpp2_rx_queue *rxq = port->rxqs[queue];
4686
4687                 rxq->time_coal = c->rx_coalesce_usecs;
4688                 rxq->pkts_coal = c->rx_max_coalesced_frames;
4689                 mvpp2_rx_pkts_coal_set(port, rxq);
4690                 mvpp2_rx_time_coal_set(port, rxq);
4691         }
4692
4693         if (port->has_tx_irqs) {
4694                 port->tx_time_coal = c->tx_coalesce_usecs;
4695                 mvpp2_tx_time_coal_set(port);
4696         }
4697
4698         for (queue = 0; queue < port->ntxqs; queue++) {
4699                 struct mvpp2_tx_queue *txq = port->txqs[queue];
4700
4701                 txq->done_pkts_coal = c->tx_max_coalesced_frames;
4702
4703                 if (port->has_tx_irqs)
4704                         mvpp2_tx_pkts_coal_set(port, txq);
4705         }
4706
4707         return 0;
4708 }
4709
4710 /* get coalescing for ethtools */
4711 static int mvpp2_ethtool_get_coalesce(struct net_device *dev,
4712                                       struct ethtool_coalesce *c)
4713 {
4714         struct mvpp2_port *port = netdev_priv(dev);
4715
4716         c->rx_coalesce_usecs       = port->rxqs[0]->time_coal;
4717         c->rx_max_coalesced_frames = port->rxqs[0]->pkts_coal;
4718         c->tx_max_coalesced_frames = port->txqs[0]->done_pkts_coal;
4719         c->tx_coalesce_usecs       = port->tx_time_coal;
4720         return 0;
4721 }
4722
4723 static void mvpp2_ethtool_get_drvinfo(struct net_device *dev,
4724                                       struct ethtool_drvinfo *drvinfo)
4725 {
4726         strlcpy(drvinfo->driver, MVPP2_DRIVER_NAME,
4727                 sizeof(drvinfo->driver));
4728         strlcpy(drvinfo->version, MVPP2_DRIVER_VERSION,
4729                 sizeof(drvinfo->version));
4730         strlcpy(drvinfo->bus_info, dev_name(&dev->dev),
4731                 sizeof(drvinfo->bus_info));
4732 }
4733
4734 static void mvpp2_ethtool_get_ringparam(struct net_device *dev,
4735                                         struct ethtool_ringparam *ring)
4736 {
4737         struct mvpp2_port *port = netdev_priv(dev);
4738
4739         ring->rx_max_pending = MVPP2_MAX_RXD_MAX;
4740         ring->tx_max_pending = MVPP2_MAX_TXD_MAX;
4741         ring->rx_pending = port->rx_ring_size;
4742         ring->tx_pending = port->tx_ring_size;
4743 }
4744
4745 static int mvpp2_ethtool_set_ringparam(struct net_device *dev,
4746                                        struct ethtool_ringparam *ring)
4747 {
4748         struct mvpp2_port *port = netdev_priv(dev);
4749         u16 prev_rx_ring_size = port->rx_ring_size;
4750         u16 prev_tx_ring_size = port->tx_ring_size;
4751         int err;
4752
4753         err = mvpp2_check_ringparam_valid(dev, ring);
4754         if (err)
4755                 return err;
4756
4757         if (!netif_running(dev)) {
4758                 port->rx_ring_size = ring->rx_pending;
4759                 port->tx_ring_size = ring->tx_pending;
4760                 return 0;
4761         }
4762
4763         /* The interface is running, so we have to force a
4764          * reallocation of the queues
4765          */
4766         mvpp2_stop_dev(port);
4767         mvpp2_cleanup_rxqs(port);
4768         mvpp2_cleanup_txqs(port);
4769
4770         port->rx_ring_size = ring->rx_pending;
4771         port->tx_ring_size = ring->tx_pending;
4772
4773         err = mvpp2_setup_rxqs(port);
4774         if (err) {
4775                 /* Reallocate Rx queues with the original ring size */
4776                 port->rx_ring_size = prev_rx_ring_size;
4777                 ring->rx_pending = prev_rx_ring_size;
4778                 err = mvpp2_setup_rxqs(port);
4779                 if (err)
4780                         goto err_out;
4781         }
4782         err = mvpp2_setup_txqs(port);
4783         if (err) {
4784                 /* Reallocate Tx queues with the original ring size */
4785                 port->tx_ring_size = prev_tx_ring_size;
4786                 ring->tx_pending = prev_tx_ring_size;
4787                 err = mvpp2_setup_txqs(port);
4788                 if (err)
4789                         goto err_clean_rxqs;
4790         }
4791
4792         mvpp2_start_dev(port);
4793         mvpp2_egress_enable(port);
4794         mvpp2_ingress_enable(port);
4795
4796         return 0;
4797
4798 err_clean_rxqs:
4799         mvpp2_cleanup_rxqs(port);
4800 err_out:
4801         netdev_err(dev, "failed to change ring parameters");
4802         return err;
4803 }
4804
4805 static void mvpp2_ethtool_get_pause_param(struct net_device *dev,
4806                                           struct ethtool_pauseparam *pause)
4807 {
4808         struct mvpp2_port *port = netdev_priv(dev);
4809
4810         if (!port->phylink)
4811                 return;
4812
4813         phylink_ethtool_get_pauseparam(port->phylink, pause);
4814 }
4815
4816 static int mvpp2_ethtool_set_pause_param(struct net_device *dev,
4817                                          struct ethtool_pauseparam *pause)
4818 {
4819         struct mvpp2_port *port = netdev_priv(dev);
4820
4821         if (!port->phylink)
4822                 return -ENOTSUPP;
4823
4824         return phylink_ethtool_set_pauseparam(port->phylink, pause);
4825 }
4826
4827 static int mvpp2_ethtool_get_link_ksettings(struct net_device *dev,
4828                                             struct ethtool_link_ksettings *cmd)
4829 {
4830         struct mvpp2_port *port = netdev_priv(dev);
4831
4832         if (!port->phylink)
4833                 return -ENOTSUPP;
4834
4835         return phylink_ethtool_ksettings_get(port->phylink, cmd);
4836 }
4837
4838 static int mvpp2_ethtool_set_link_ksettings(struct net_device *dev,
4839                                             const struct ethtool_link_ksettings *cmd)
4840 {
4841         struct mvpp2_port *port = netdev_priv(dev);
4842
4843         if (!port->phylink)
4844                 return -ENOTSUPP;
4845
4846         return phylink_ethtool_ksettings_set(port->phylink, cmd);
4847 }
4848
4849 static int mvpp2_ethtool_get_rxnfc(struct net_device *dev,
4850                                    struct ethtool_rxnfc *info, u32 *rules)
4851 {
4852         struct mvpp2_port *port = netdev_priv(dev);
4853         int ret = 0, i, loc = 0;
4854
4855         if (!mvpp22_rss_is_supported())
4856                 return -EOPNOTSUPP;
4857
4858         switch (info->cmd) {
4859         case ETHTOOL_GRXFH:
4860                 ret = mvpp2_ethtool_rxfh_get(port, info);
4861                 break;
4862         case ETHTOOL_GRXRINGS:
4863                 info->data = port->nrxqs;
4864                 break;
4865         case ETHTOOL_GRXCLSRLCNT:
4866                 info->rule_cnt = port->n_rfs_rules;
4867                 break;
4868         case ETHTOOL_GRXCLSRULE:
4869                 ret = mvpp2_ethtool_cls_rule_get(port, info);
4870                 break;
4871         case ETHTOOL_GRXCLSRLALL:
4872                 for (i = 0; i < MVPP2_N_RFS_ENTRIES_PER_FLOW; i++) {
4873                         if (port->rfs_rules[i])
4874                                 rules[loc++] = i;
4875                 }
4876                 break;
4877         default:
4878                 return -ENOTSUPP;
4879         }
4880
4881         return ret;
4882 }
4883
4884 static int mvpp2_ethtool_set_rxnfc(struct net_device *dev,
4885                                    struct ethtool_rxnfc *info)
4886 {
4887         struct mvpp2_port *port = netdev_priv(dev);
4888         int ret = 0;
4889
4890         if (!mvpp22_rss_is_supported())
4891                 return -EOPNOTSUPP;
4892
4893         switch (info->cmd) {
4894         case ETHTOOL_SRXFH:
4895                 ret = mvpp2_ethtool_rxfh_set(port, info);
4896                 break;
4897         case ETHTOOL_SRXCLSRLINS:
4898                 ret = mvpp2_ethtool_cls_rule_ins(port, info);
4899                 break;
4900         case ETHTOOL_SRXCLSRLDEL:
4901                 ret = mvpp2_ethtool_cls_rule_del(port, info);
4902                 break;
4903         default:
4904                 return -EOPNOTSUPP;
4905         }
4906         return ret;
4907 }
4908
4909 static u32 mvpp2_ethtool_get_rxfh_indir_size(struct net_device *dev)
4910 {
4911         return mvpp22_rss_is_supported() ? MVPP22_RSS_TABLE_ENTRIES : 0;
4912 }
4913
4914 static int mvpp2_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
4915                                   u8 *hfunc)
4916 {
4917         struct mvpp2_port *port = netdev_priv(dev);
4918         int ret = 0;
4919
4920         if (!mvpp22_rss_is_supported())
4921                 return -EOPNOTSUPP;
4922
4923         if (indir)
4924                 ret = mvpp22_port_rss_ctx_indir_get(port, 0, indir);
4925
4926         if (hfunc)
4927                 *hfunc = ETH_RSS_HASH_CRC32;
4928
4929         return ret;
4930 }
4931
4932 static int mvpp2_ethtool_set_rxfh(struct net_device *dev, const u32 *indir,
4933                                   const u8 *key, const u8 hfunc)
4934 {
4935         struct mvpp2_port *port = netdev_priv(dev);
4936         int ret = 0;
4937
4938         if (!mvpp22_rss_is_supported())
4939                 return -EOPNOTSUPP;
4940
4941         if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_CRC32)
4942                 return -EOPNOTSUPP;
4943
4944         if (key)
4945                 return -EOPNOTSUPP;
4946
4947         if (indir)
4948                 ret = mvpp22_port_rss_ctx_indir_set(port, 0, indir);
4949
4950         return ret;
4951 }
4952
4953 static int mvpp2_ethtool_get_rxfh_context(struct net_device *dev, u32 *indir,
4954                                           u8 *key, u8 *hfunc, u32 rss_context)
4955 {
4956         struct mvpp2_port *port = netdev_priv(dev);
4957         int ret = 0;
4958
4959         if (!mvpp22_rss_is_supported())
4960                 return -EOPNOTSUPP;
4961         if (rss_context >= MVPP22_N_RSS_TABLES)
4962                 return -EINVAL;
4963
4964         if (hfunc)
4965                 *hfunc = ETH_RSS_HASH_CRC32;
4966
4967         if (indir)
4968                 ret = mvpp22_port_rss_ctx_indir_get(port, rss_context, indir);
4969
4970         return ret;
4971 }
4972
4973 static int mvpp2_ethtool_set_rxfh_context(struct net_device *dev,
4974                                           const u32 *indir, const u8 *key,
4975                                           const u8 hfunc, u32 *rss_context,
4976                                           bool delete)
4977 {
4978         struct mvpp2_port *port = netdev_priv(dev);
4979         int ret;
4980
4981         if (!mvpp22_rss_is_supported())
4982                 return -EOPNOTSUPP;
4983
4984         if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_CRC32)
4985                 return -EOPNOTSUPP;
4986
4987         if (key)
4988                 return -EOPNOTSUPP;
4989
4990         if (delete)
4991                 return mvpp22_port_rss_ctx_delete(port, *rss_context);
4992
4993         if (*rss_context == ETH_RXFH_CONTEXT_ALLOC) {
4994                 ret = mvpp22_port_rss_ctx_create(port, rss_context);
4995                 if (ret)
4996                         return ret;
4997         }
4998
4999         return mvpp22_port_rss_ctx_indir_set(port, *rss_context, indir);
5000 }
5001 /* Device ops */
5002
5003 static const struct net_device_ops mvpp2_netdev_ops = {
5004         .ndo_open               = mvpp2_open,
5005         .ndo_stop               = mvpp2_stop,
5006         .ndo_start_xmit         = mvpp2_tx,
5007         .ndo_set_rx_mode        = mvpp2_set_rx_mode,
5008         .ndo_set_mac_address    = mvpp2_set_mac_address,
5009         .ndo_change_mtu         = mvpp2_change_mtu,
5010         .ndo_get_stats64        = mvpp2_get_stats64,
5011         .ndo_do_ioctl           = mvpp2_ioctl,
5012         .ndo_vlan_rx_add_vid    = mvpp2_vlan_rx_add_vid,
5013         .ndo_vlan_rx_kill_vid   = mvpp2_vlan_rx_kill_vid,
5014         .ndo_set_features       = mvpp2_set_features,
5015         .ndo_bpf                = mvpp2_xdp,
5016         .ndo_xdp_xmit           = mvpp2_xdp_xmit,
5017 };
5018
5019 static const struct ethtool_ops mvpp2_eth_tool_ops = {
5020         .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
5021                                      ETHTOOL_COALESCE_MAX_FRAMES,
5022         .nway_reset             = mvpp2_ethtool_nway_reset,
5023         .get_link               = ethtool_op_get_link,
5024         .set_coalesce           = mvpp2_ethtool_set_coalesce,
5025         .get_coalesce           = mvpp2_ethtool_get_coalesce,
5026         .get_drvinfo            = mvpp2_ethtool_get_drvinfo,
5027         .get_ringparam          = mvpp2_ethtool_get_ringparam,
5028         .set_ringparam          = mvpp2_ethtool_set_ringparam,
5029         .get_strings            = mvpp2_ethtool_get_strings,
5030         .get_ethtool_stats      = mvpp2_ethtool_get_stats,
5031         .get_sset_count         = mvpp2_ethtool_get_sset_count,
5032         .get_pauseparam         = mvpp2_ethtool_get_pause_param,
5033         .set_pauseparam         = mvpp2_ethtool_set_pause_param,
5034         .get_link_ksettings     = mvpp2_ethtool_get_link_ksettings,
5035         .set_link_ksettings     = mvpp2_ethtool_set_link_ksettings,
5036         .get_rxnfc              = mvpp2_ethtool_get_rxnfc,
5037         .set_rxnfc              = mvpp2_ethtool_set_rxnfc,
5038         .get_rxfh_indir_size    = mvpp2_ethtool_get_rxfh_indir_size,
5039         .get_rxfh               = mvpp2_ethtool_get_rxfh,
5040         .set_rxfh               = mvpp2_ethtool_set_rxfh,
5041         .get_rxfh_context       = mvpp2_ethtool_get_rxfh_context,
5042         .set_rxfh_context       = mvpp2_ethtool_set_rxfh_context,
5043 };
5044
5045 /* Used for PPv2.1, or PPv2.2 with the old Device Tree binding that
5046  * had a single IRQ defined per-port.
5047  */
5048 static int mvpp2_simple_queue_vectors_init(struct mvpp2_port *port,
5049                                            struct device_node *port_node)
5050 {
5051         struct mvpp2_queue_vector *v = &port->qvecs[0];
5052
5053         v->first_rxq = 0;
5054         v->nrxqs = port->nrxqs;
5055         v->type = MVPP2_QUEUE_VECTOR_SHARED;
5056         v->sw_thread_id = 0;
5057         v->sw_thread_mask = *cpumask_bits(cpu_online_mask);
5058         v->port = port;
5059         v->irq = irq_of_parse_and_map(port_node, 0);
5060         if (v->irq <= 0)
5061                 return -EINVAL;
5062         netif_napi_add(port->dev, &v->napi, mvpp2_poll,
5063                        NAPI_POLL_WEIGHT);
5064
5065         port->nqvecs = 1;
5066
5067         return 0;
5068 }
5069
5070 static int mvpp2_multi_queue_vectors_init(struct mvpp2_port *port,
5071                                           struct device_node *port_node)
5072 {
5073         struct mvpp2 *priv = port->priv;
5074         struct mvpp2_queue_vector *v;
5075         int i, ret;
5076
5077         switch (queue_mode) {
5078         case MVPP2_QDIST_SINGLE_MODE:
5079                 port->nqvecs = priv->nthreads + 1;
5080                 break;
5081         case MVPP2_QDIST_MULTI_MODE:
5082                 port->nqvecs = priv->nthreads;
5083                 break;
5084         }
5085
5086         for (i = 0; i < port->nqvecs; i++) {
5087                 char irqname[16];
5088
5089                 v = port->qvecs + i;
5090
5091                 v->port = port;
5092                 v->type = MVPP2_QUEUE_VECTOR_PRIVATE;
5093                 v->sw_thread_id = i;
5094                 v->sw_thread_mask = BIT(i);
5095
5096                 if (port->flags & MVPP2_F_DT_COMPAT)
5097                         snprintf(irqname, sizeof(irqname), "tx-cpu%d", i);
5098                 else
5099                         snprintf(irqname, sizeof(irqname), "hif%d", i);
5100
5101                 if (queue_mode == MVPP2_QDIST_MULTI_MODE) {
5102                         v->first_rxq = i;
5103                         v->nrxqs = 1;
5104                 } else if (queue_mode == MVPP2_QDIST_SINGLE_MODE &&
5105                            i == (port->nqvecs - 1)) {
5106                         v->first_rxq = 0;
5107                         v->nrxqs = port->nrxqs;
5108                         v->type = MVPP2_QUEUE_VECTOR_SHARED;
5109
5110                         if (port->flags & MVPP2_F_DT_COMPAT)
5111                                 strncpy(irqname, "rx-shared", sizeof(irqname));
5112                 }
5113
5114                 if (port_node)
5115                         v->irq = of_irq_get_byname(port_node, irqname);
5116                 else
5117                         v->irq = fwnode_irq_get(port->fwnode, i);
5118                 if (v->irq <= 0) {
5119                         ret = -EINVAL;
5120                         goto err;
5121                 }
5122
5123                 netif_napi_add(port->dev, &v->napi, mvpp2_poll,
5124                                NAPI_POLL_WEIGHT);
5125         }
5126
5127         return 0;
5128
5129 err:
5130         for (i = 0; i < port->nqvecs; i++)
5131                 irq_dispose_mapping(port->qvecs[i].irq);
5132         return ret;
5133 }
5134
5135 static int mvpp2_queue_vectors_init(struct mvpp2_port *port,
5136                                     struct device_node *port_node)
5137 {
5138         if (port->has_tx_irqs)
5139                 return mvpp2_multi_queue_vectors_init(port, port_node);
5140         else
5141                 return mvpp2_simple_queue_vectors_init(port, port_node);
5142 }
5143
5144 static void mvpp2_queue_vectors_deinit(struct mvpp2_port *port)
5145 {
5146         int i;
5147
5148         for (i = 0; i < port->nqvecs; i++)
5149                 irq_dispose_mapping(port->qvecs[i].irq);
5150 }
5151
5152 /* Configure Rx queue group interrupt for this port */
5153 static void mvpp2_rx_irqs_setup(struct mvpp2_port *port)
5154 {
5155         struct mvpp2 *priv = port->priv;
5156         u32 val;
5157         int i;
5158
5159         if (priv->hw_version == MVPP21) {
5160                 mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(port->id),
5161                             port->nrxqs);
5162                 return;
5163         }
5164
5165         /* Handle the more complicated PPv2.2 case */
5166         for (i = 0; i < port->nqvecs; i++) {
5167                 struct mvpp2_queue_vector *qv = port->qvecs + i;
5168
5169                 if (!qv->nrxqs)
5170                         continue;
5171
5172                 val = qv->sw_thread_id;
5173                 val |= port->id << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET;
5174                 mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val);
5175
5176                 val = qv->first_rxq;
5177                 val |= qv->nrxqs << MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET;
5178                 mvpp2_write(priv, MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val);
5179         }
5180 }
5181
5182 /* Initialize port HW */
5183 static int mvpp2_port_init(struct mvpp2_port *port)
5184 {
5185         struct device *dev = port->dev->dev.parent;
5186         struct mvpp2 *priv = port->priv;
5187         struct mvpp2_txq_pcpu *txq_pcpu;
5188         unsigned int thread;
5189         int queue, err;
5190
5191         /* Checks for hardware constraints */
5192         if (port->first_rxq + port->nrxqs >
5193             MVPP2_MAX_PORTS * priv->max_port_rxqs)
5194                 return -EINVAL;
5195
5196         if (port->nrxqs > priv->max_port_rxqs || port->ntxqs > MVPP2_MAX_TXQ)
5197                 return -EINVAL;
5198
5199         /* Disable port */
5200         mvpp2_egress_disable(port);
5201         mvpp2_port_disable(port);
5202
5203         port->tx_time_coal = MVPP2_TXDONE_COAL_USEC;
5204
5205         port->txqs = devm_kcalloc(dev, port->ntxqs, sizeof(*port->txqs),
5206                                   GFP_KERNEL);
5207         if (!port->txqs)
5208                 return -ENOMEM;
5209
5210         /* Associate physical Tx queues to this port and initialize.
5211          * The mapping is predefined.
5212          */
5213         for (queue = 0; queue < port->ntxqs; queue++) {
5214                 int queue_phy_id = mvpp2_txq_phys(port->id, queue);
5215                 struct mvpp2_tx_queue *txq;
5216
5217                 txq = devm_kzalloc(dev, sizeof(*txq), GFP_KERNEL);
5218                 if (!txq) {
5219                         err = -ENOMEM;
5220                         goto err_free_percpu;
5221                 }
5222
5223                 txq->pcpu = alloc_percpu(struct mvpp2_txq_pcpu);
5224                 if (!txq->pcpu) {
5225                         err = -ENOMEM;
5226                         goto err_free_percpu;
5227                 }
5228
5229                 txq->id = queue_phy_id;
5230                 txq->log_id = queue;
5231                 txq->done_pkts_coal = MVPP2_TXDONE_COAL_PKTS_THRESH;
5232                 for (thread = 0; thread < priv->nthreads; thread++) {
5233                         txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
5234                         txq_pcpu->thread = thread;
5235                 }
5236
5237                 port->txqs[queue] = txq;
5238         }
5239
5240         port->rxqs = devm_kcalloc(dev, port->nrxqs, sizeof(*port->rxqs),
5241                                   GFP_KERNEL);
5242         if (!port->rxqs) {
5243                 err = -ENOMEM;
5244                 goto err_free_percpu;
5245         }
5246
5247         /* Allocate and initialize Rx queue for this port */
5248         for (queue = 0; queue < port->nrxqs; queue++) {
5249                 struct mvpp2_rx_queue *rxq;
5250
5251                 /* Map physical Rx queue to port's logical Rx queue */
5252                 rxq = devm_kzalloc(dev, sizeof(*rxq), GFP_KERNEL);
5253                 if (!rxq) {
5254                         err = -ENOMEM;
5255                         goto err_free_percpu;
5256                 }
5257                 /* Map this Rx queue to a physical queue */
5258                 rxq->id = port->first_rxq + queue;
5259                 rxq->port = port->id;
5260                 rxq->logic_rxq = queue;
5261
5262                 port->rxqs[queue] = rxq;
5263         }
5264
5265         mvpp2_rx_irqs_setup(port);
5266
5267         /* Create Rx descriptor rings */
5268         for (queue = 0; queue < port->nrxqs; queue++) {
5269                 struct mvpp2_rx_queue *rxq = port->rxqs[queue];
5270
5271                 rxq->size = port->rx_ring_size;
5272                 rxq->pkts_coal = MVPP2_RX_COAL_PKTS;
5273                 rxq->time_coal = MVPP2_RX_COAL_USEC;
5274         }
5275
5276         mvpp2_ingress_disable(port);
5277
5278         /* Port default configuration */
5279         mvpp2_defaults_set(port);
5280
5281         /* Port's classifier configuration */
5282         mvpp2_cls_oversize_rxq_set(port);
5283         mvpp2_cls_port_config(port);
5284
5285         if (mvpp22_rss_is_supported())
5286                 mvpp22_port_rss_init(port);
5287
5288         /* Provide an initial Rx packet size */
5289         port->pkt_size = MVPP2_RX_PKT_SIZE(port->dev->mtu);
5290
5291         /* Initialize pools for swf */
5292         err = mvpp2_swf_bm_pool_init(port);
5293         if (err)
5294                 goto err_free_percpu;
5295
5296         /* Clear all port stats */
5297         mvpp2_read_stats(port);
5298         memset(port->ethtool_stats, 0,
5299                MVPP2_N_ETHTOOL_STATS(port->ntxqs, port->nrxqs) * sizeof(u64));
5300
5301         return 0;
5302
5303 err_free_percpu:
5304         for (queue = 0; queue < port->ntxqs; queue++) {
5305                 if (!port->txqs[queue])
5306                         continue;
5307                 free_percpu(port->txqs[queue]->pcpu);
5308         }
5309         return err;
5310 }
5311
5312 static bool mvpp22_port_has_legacy_tx_irqs(struct device_node *port_node,
5313                                            unsigned long *flags)
5314 {
5315         char *irqs[5] = { "rx-shared", "tx-cpu0", "tx-cpu1", "tx-cpu2",
5316                           "tx-cpu3" };
5317         int i;
5318
5319         for (i = 0; i < 5; i++)
5320                 if (of_property_match_string(port_node, "interrupt-names",
5321                                              irqs[i]) < 0)
5322                         return false;
5323
5324         *flags |= MVPP2_F_DT_COMPAT;
5325         return true;
5326 }
5327
5328 /* Checks if the port dt description has the required Tx interrupts:
5329  * - PPv2.1: there are no such interrupts.
5330  * - PPv2.2:
5331  *   - The old DTs have: "rx-shared", "tx-cpuX" with X in [0...3]
5332  *   - The new ones have: "hifX" with X in [0..8]
5333  *
5334  * All those variants are supported to keep the backward compatibility.
5335  */
5336 static bool mvpp2_port_has_irqs(struct mvpp2 *priv,
5337                                 struct device_node *port_node,
5338                                 unsigned long *flags)
5339 {
5340         char name[5];
5341         int i;
5342
5343         /* ACPI */
5344         if (!port_node)
5345                 return true;
5346
5347         if (priv->hw_version == MVPP21)
5348                 return false;
5349
5350         if (mvpp22_port_has_legacy_tx_irqs(port_node, flags))
5351                 return true;
5352
5353         for (i = 0; i < MVPP2_MAX_THREADS; i++) {
5354                 snprintf(name, 5, "hif%d", i);
5355                 if (of_property_match_string(port_node, "interrupt-names",
5356                                              name) < 0)
5357                         return false;
5358         }
5359
5360         return true;
5361 }
5362
5363 static void mvpp2_port_copy_mac_addr(struct net_device *dev, struct mvpp2 *priv,
5364                                      struct fwnode_handle *fwnode,
5365                                      char **mac_from)
5366 {
5367         struct mvpp2_port *port = netdev_priv(dev);
5368         char hw_mac_addr[ETH_ALEN] = {0};
5369         char fw_mac_addr[ETH_ALEN];
5370
5371         if (fwnode_get_mac_address(fwnode, fw_mac_addr, ETH_ALEN)) {
5372                 *mac_from = "firmware node";
5373                 ether_addr_copy(dev->dev_addr, fw_mac_addr);
5374                 return;
5375         }
5376
5377         if (priv->hw_version == MVPP21) {
5378                 mvpp21_get_mac_address(port, hw_mac_addr);
5379                 if (is_valid_ether_addr(hw_mac_addr)) {
5380                         *mac_from = "hardware";
5381                         ether_addr_copy(dev->dev_addr, hw_mac_addr);
5382                         return;
5383                 }
5384         }
5385
5386         *mac_from = "random";
5387         eth_hw_addr_random(dev);
5388 }
5389
5390 static struct mvpp2_port *mvpp2_phylink_to_port(struct phylink_config *config)
5391 {
5392         return container_of(config, struct mvpp2_port, phylink_config);
5393 }
5394
5395 static void mvpp2_phylink_validate(struct phylink_config *config,
5396                                    unsigned long *supported,
5397                                    struct phylink_link_state *state)
5398 {
5399         struct mvpp2_port *port = mvpp2_phylink_to_port(config);
5400         __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
5401
5402         /* Invalid combinations */
5403         switch (state->interface) {
5404         case PHY_INTERFACE_MODE_10GBASER:
5405         case PHY_INTERFACE_MODE_XAUI:
5406                 if (!mvpp2_port_supports_xlg(port))
5407                         goto empty_set;
5408                 break;
5409         case PHY_INTERFACE_MODE_RGMII:
5410         case PHY_INTERFACE_MODE_RGMII_ID:
5411         case PHY_INTERFACE_MODE_RGMII_RXID:
5412         case PHY_INTERFACE_MODE_RGMII_TXID:
5413                 if (!mvpp2_port_supports_rgmii(port))
5414                         goto empty_set;
5415                 break;
5416         default:
5417                 break;
5418         }
5419
5420         phylink_set(mask, Autoneg);
5421         phylink_set_port_modes(mask);
5422         phylink_set(mask, Pause);
5423         phylink_set(mask, Asym_Pause);
5424
5425         switch (state->interface) {
5426         case PHY_INTERFACE_MODE_10GBASER:
5427         case PHY_INTERFACE_MODE_XAUI:
5428         case PHY_INTERFACE_MODE_NA:
5429                 if (mvpp2_port_supports_xlg(port)) {
5430                         phylink_set(mask, 10000baseT_Full);
5431                         phylink_set(mask, 10000baseCR_Full);
5432                         phylink_set(mask, 10000baseSR_Full);
5433                         phylink_set(mask, 10000baseLR_Full);
5434                         phylink_set(mask, 10000baseLRM_Full);
5435                         phylink_set(mask, 10000baseER_Full);
5436                         phylink_set(mask, 10000baseKR_Full);
5437                 }
5438                 if (state->interface != PHY_INTERFACE_MODE_NA)
5439                         break;
5440                 fallthrough;
5441         case PHY_INTERFACE_MODE_RGMII:
5442         case PHY_INTERFACE_MODE_RGMII_ID:
5443         case PHY_INTERFACE_MODE_RGMII_RXID:
5444         case PHY_INTERFACE_MODE_RGMII_TXID:
5445         case PHY_INTERFACE_MODE_SGMII:
5446                 phylink_set(mask, 10baseT_Half);
5447                 phylink_set(mask, 10baseT_Full);
5448                 phylink_set(mask, 100baseT_Half);
5449                 phylink_set(mask, 100baseT_Full);
5450                 phylink_set(mask, 1000baseT_Full);
5451                 phylink_set(mask, 1000baseX_Full);
5452                 if (state->interface != PHY_INTERFACE_MODE_NA)
5453                         break;
5454                 fallthrough;
5455         case PHY_INTERFACE_MODE_1000BASEX:
5456         case PHY_INTERFACE_MODE_2500BASEX:
5457                 if (port->comphy ||
5458                     state->interface != PHY_INTERFACE_MODE_2500BASEX) {
5459                         phylink_set(mask, 1000baseT_Full);
5460                         phylink_set(mask, 1000baseX_Full);
5461                 }
5462                 if (port->comphy ||
5463                     state->interface == PHY_INTERFACE_MODE_2500BASEX) {
5464                         phylink_set(mask, 2500baseT_Full);
5465                         phylink_set(mask, 2500baseX_Full);
5466                 }
5467                 break;
5468         default:
5469                 goto empty_set;
5470         }
5471
5472         bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
5473         bitmap_and(state->advertising, state->advertising, mask,
5474                    __ETHTOOL_LINK_MODE_MASK_NBITS);
5475
5476         phylink_helper_basex_speed(state);
5477         return;
5478
5479 empty_set:
5480         bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
5481 }
5482
5483 static void mvpp22_xlg_pcs_get_state(struct mvpp2_port *port,
5484                                      struct phylink_link_state *state)
5485 {
5486         u32 val;
5487
5488         state->speed = SPEED_10000;
5489         state->duplex = 1;
5490         state->an_complete = 1;
5491
5492         val = readl(port->base + MVPP22_XLG_STATUS);
5493         state->link = !!(val & MVPP22_XLG_STATUS_LINK_UP);
5494
5495         state->pause = 0;
5496         val = readl(port->base + MVPP22_XLG_CTRL0_REG);
5497         if (val & MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN)
5498                 state->pause |= MLO_PAUSE_TX;
5499         if (val & MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN)
5500                 state->pause |= MLO_PAUSE_RX;
5501 }
5502
5503 static void mvpp2_gmac_pcs_get_state(struct mvpp2_port *port,
5504                                      struct phylink_link_state *state)
5505 {
5506         u32 val;
5507
5508         val = readl(port->base + MVPP2_GMAC_STATUS0);
5509
5510         state->an_complete = !!(val & MVPP2_GMAC_STATUS0_AN_COMPLETE);
5511         state->link = !!(val & MVPP2_GMAC_STATUS0_LINK_UP);
5512         state->duplex = !!(val & MVPP2_GMAC_STATUS0_FULL_DUPLEX);
5513
5514         switch (port->phy_interface) {
5515         case PHY_INTERFACE_MODE_1000BASEX:
5516                 state->speed = SPEED_1000;
5517                 break;
5518         case PHY_INTERFACE_MODE_2500BASEX:
5519                 state->speed = SPEED_2500;
5520                 break;
5521         default:
5522                 if (val & MVPP2_GMAC_STATUS0_GMII_SPEED)
5523                         state->speed = SPEED_1000;
5524                 else if (val & MVPP2_GMAC_STATUS0_MII_SPEED)
5525                         state->speed = SPEED_100;
5526                 else
5527                         state->speed = SPEED_10;
5528         }
5529
5530         state->pause = 0;
5531         if (val & MVPP2_GMAC_STATUS0_RX_PAUSE)
5532                 state->pause |= MLO_PAUSE_RX;
5533         if (val & MVPP2_GMAC_STATUS0_TX_PAUSE)
5534                 state->pause |= MLO_PAUSE_TX;
5535 }
5536
5537 static void mvpp2_phylink_mac_pcs_get_state(struct phylink_config *config,
5538                                             struct phylink_link_state *state)
5539 {
5540         struct mvpp2_port *port = mvpp2_phylink_to_port(config);
5541
5542         if (port->priv->hw_version == MVPP22 && port->gop_id == 0) {
5543                 u32 mode = readl(port->base + MVPP22_XLG_CTRL3_REG);
5544                 mode &= MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
5545
5546                 if (mode == MVPP22_XLG_CTRL3_MACMODESELECT_10G) {
5547                         mvpp22_xlg_pcs_get_state(port, state);
5548                         return;
5549                 }
5550         }
5551
5552         mvpp2_gmac_pcs_get_state(port, state);
5553 }
5554
5555 static void mvpp2_mac_an_restart(struct phylink_config *config)
5556 {
5557         struct mvpp2_port *port = mvpp2_phylink_to_port(config);
5558         u32 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
5559
5560         writel(val | MVPP2_GMAC_IN_BAND_RESTART_AN,
5561                port->base + MVPP2_GMAC_AUTONEG_CONFIG);
5562         writel(val & ~MVPP2_GMAC_IN_BAND_RESTART_AN,
5563                port->base + MVPP2_GMAC_AUTONEG_CONFIG);
5564 }
5565
5566 static void mvpp2_xlg_config(struct mvpp2_port *port, unsigned int mode,
5567                              const struct phylink_link_state *state)
5568 {
5569         u32 val;
5570
5571         mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG,
5572                      MVPP22_XLG_CTRL0_MAC_RESET_DIS,
5573                      MVPP22_XLG_CTRL0_MAC_RESET_DIS);
5574         mvpp2_modify(port->base + MVPP22_XLG_CTRL4_REG,
5575                      MVPP22_XLG_CTRL4_MACMODSELECT_GMAC |
5576                      MVPP22_XLG_CTRL4_EN_IDLE_CHECK |
5577                      MVPP22_XLG_CTRL4_FWD_FC | MVPP22_XLG_CTRL4_FWD_PFC,
5578                      MVPP22_XLG_CTRL4_FWD_FC | MVPP22_XLG_CTRL4_FWD_PFC);
5579
5580         /* Wait for reset to deassert */
5581         do {
5582                 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
5583         } while (!(val & MVPP22_XLG_CTRL0_MAC_RESET_DIS));
5584 }
5585
5586 static void mvpp2_gmac_config(struct mvpp2_port *port, unsigned int mode,
5587                               const struct phylink_link_state *state)
5588 {
5589         u32 old_an, an;
5590         u32 old_ctrl0, ctrl0;
5591         u32 old_ctrl2, ctrl2;
5592         u32 old_ctrl4, ctrl4;
5593
5594         old_an = an = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
5595         old_ctrl0 = ctrl0 = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
5596         old_ctrl2 = ctrl2 = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
5597         old_ctrl4 = ctrl4 = readl(port->base + MVPP22_GMAC_CTRL_4_REG);
5598
5599         an &= ~(MVPP2_GMAC_AN_SPEED_EN | MVPP2_GMAC_FC_ADV_EN |
5600                 MVPP2_GMAC_FC_ADV_ASM_EN | MVPP2_GMAC_FLOW_CTRL_AUTONEG |
5601                 MVPP2_GMAC_AN_DUPLEX_EN | MVPP2_GMAC_IN_BAND_AUTONEG |
5602                 MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS);
5603         ctrl0 &= ~MVPP2_GMAC_PORT_TYPE_MASK;
5604         ctrl2 &= ~(MVPP2_GMAC_INBAND_AN_MASK | MVPP2_GMAC_PORT_RESET_MASK |
5605                    MVPP2_GMAC_PCS_ENABLE_MASK);
5606
5607         /* Configure port type */
5608         if (phy_interface_mode_is_8023z(state->interface)) {
5609                 ctrl2 |= MVPP2_GMAC_PCS_ENABLE_MASK;
5610                 ctrl4 &= ~MVPP22_CTRL4_EXT_PIN_GMII_SEL;
5611                 ctrl4 |= MVPP22_CTRL4_SYNC_BYPASS_DIS |
5612                          MVPP22_CTRL4_DP_CLK_SEL |
5613                          MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE;
5614         } else if (state->interface == PHY_INTERFACE_MODE_SGMII) {
5615                 ctrl2 |= MVPP2_GMAC_PCS_ENABLE_MASK | MVPP2_GMAC_INBAND_AN_MASK;
5616                 ctrl4 &= ~MVPP22_CTRL4_EXT_PIN_GMII_SEL;
5617                 ctrl4 |= MVPP22_CTRL4_SYNC_BYPASS_DIS |
5618                          MVPP22_CTRL4_DP_CLK_SEL |
5619                          MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE;
5620         } else if (phy_interface_mode_is_rgmii(state->interface)) {
5621                 ctrl4 &= ~MVPP22_CTRL4_DP_CLK_SEL;
5622                 ctrl4 |= MVPP22_CTRL4_EXT_PIN_GMII_SEL |
5623                          MVPP22_CTRL4_SYNC_BYPASS_DIS |
5624                          MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE;
5625         }
5626
5627         /* Configure advertisement bits */
5628         if (phylink_test(state->advertising, Pause))
5629                 an |= MVPP2_GMAC_FC_ADV_EN;
5630         if (phylink_test(state->advertising, Asym_Pause))
5631                 an |= MVPP2_GMAC_FC_ADV_ASM_EN;
5632
5633         /* Configure negotiation style */
5634         if (!phylink_autoneg_inband(mode)) {
5635                 /* Phy or fixed speed - no in-band AN, nothing to do, leave the
5636                  * configured speed, duplex and flow control as-is.
5637                  */
5638         } else if (state->interface == PHY_INTERFACE_MODE_SGMII) {
5639                 /* SGMII in-band mode receives the speed and duplex from
5640                  * the PHY. Flow control information is not received. */
5641                 an &= ~(MVPP2_GMAC_FORCE_LINK_DOWN |
5642                         MVPP2_GMAC_FORCE_LINK_PASS |
5643                         MVPP2_GMAC_CONFIG_MII_SPEED |
5644                         MVPP2_GMAC_CONFIG_GMII_SPEED |
5645                         MVPP2_GMAC_CONFIG_FULL_DUPLEX);
5646                 an |= MVPP2_GMAC_IN_BAND_AUTONEG |
5647                       MVPP2_GMAC_AN_SPEED_EN |
5648                       MVPP2_GMAC_AN_DUPLEX_EN;
5649         } else if (phy_interface_mode_is_8023z(state->interface)) {
5650                 /* 1000BaseX and 2500BaseX ports cannot negotiate speed nor can
5651                  * they negotiate duplex: they are always operating with a fixed
5652                  * speed of 1000/2500Mbps in full duplex, so force 1000/2500
5653                  * speed and full duplex here.
5654                  */
5655                 ctrl0 |= MVPP2_GMAC_PORT_TYPE_MASK;
5656                 an &= ~(MVPP2_GMAC_FORCE_LINK_DOWN |
5657                         MVPP2_GMAC_FORCE_LINK_PASS |
5658                         MVPP2_GMAC_CONFIG_MII_SPEED |
5659                         MVPP2_GMAC_CONFIG_GMII_SPEED |
5660                         MVPP2_GMAC_CONFIG_FULL_DUPLEX);
5661                 an |= MVPP2_GMAC_IN_BAND_AUTONEG |
5662                       MVPP2_GMAC_CONFIG_GMII_SPEED |
5663                       MVPP2_GMAC_CONFIG_FULL_DUPLEX;
5664
5665                 if (state->pause & MLO_PAUSE_AN && state->an_enabled)
5666                         an |= MVPP2_GMAC_FLOW_CTRL_AUTONEG;
5667         }
5668
5669 /* Some fields of the auto-negotiation register require the port to be down when
5670  * their value is updated.
5671  */
5672 #define MVPP2_GMAC_AN_PORT_DOWN_MASK    \
5673                 (MVPP2_GMAC_IN_BAND_AUTONEG | \
5674                  MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS | \
5675                  MVPP2_GMAC_CONFIG_MII_SPEED | MVPP2_GMAC_CONFIG_GMII_SPEED | \
5676                  MVPP2_GMAC_AN_SPEED_EN | MVPP2_GMAC_CONFIG_FULL_DUPLEX | \
5677                  MVPP2_GMAC_AN_DUPLEX_EN)
5678
5679         if ((old_ctrl0 ^ ctrl0) & MVPP2_GMAC_PORT_TYPE_MASK ||
5680             (old_ctrl2 ^ ctrl2) & MVPP2_GMAC_INBAND_AN_MASK ||
5681             (old_an ^ an) & MVPP2_GMAC_AN_PORT_DOWN_MASK) {
5682                 /* Force link down */
5683                 old_an &= ~MVPP2_GMAC_FORCE_LINK_PASS;
5684                 old_an |= MVPP2_GMAC_FORCE_LINK_DOWN;
5685                 writel(old_an, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
5686
5687                 /* Set the GMAC in a reset state - do this in a way that
5688                  * ensures we clear it below.
5689                  */
5690                 old_ctrl2 |= MVPP2_GMAC_PORT_RESET_MASK;
5691                 writel(old_ctrl2, port->base + MVPP2_GMAC_CTRL_2_REG);
5692         }
5693
5694         if (old_ctrl0 != ctrl0)
5695                 writel(ctrl0, port->base + MVPP2_GMAC_CTRL_0_REG);
5696         if (old_ctrl2 != ctrl2)
5697                 writel(ctrl2, port->base + MVPP2_GMAC_CTRL_2_REG);
5698         if (old_ctrl4 != ctrl4)
5699                 writel(ctrl4, port->base + MVPP22_GMAC_CTRL_4_REG);
5700         if (old_an != an)
5701                 writel(an, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
5702
5703         if (old_ctrl2 & MVPP2_GMAC_PORT_RESET_MASK) {
5704                 while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
5705                        MVPP2_GMAC_PORT_RESET_MASK)
5706                         continue;
5707         }
5708 }
5709
5710 static void mvpp2_mac_config(struct phylink_config *config, unsigned int mode,
5711                              const struct phylink_link_state *state)
5712 {
5713         struct mvpp2_port *port = mvpp2_phylink_to_port(config);
5714         bool change_interface = port->phy_interface != state->interface;
5715
5716         /* Check for invalid configuration */
5717         if (mvpp2_is_xlg(state->interface) && port->gop_id != 0) {
5718                 netdev_err(port->dev, "Invalid mode on %s\n", port->dev->name);
5719                 return;
5720         }
5721
5722         /* Make sure the port is disabled when reconfiguring the mode */
5723         mvpp2_port_disable(port);
5724
5725         if (port->priv->hw_version == MVPP22 && change_interface) {
5726                 mvpp22_gop_mask_irq(port);
5727
5728                 port->phy_interface = state->interface;
5729
5730                 /* Reconfigure the serdes lanes */
5731                 phy_power_off(port->comphy);
5732                 mvpp22_mode_reconfigure(port);
5733         }
5734
5735         /* mac (re)configuration */
5736         if (mvpp2_is_xlg(state->interface))
5737                 mvpp2_xlg_config(port, mode, state);
5738         else if (phy_interface_mode_is_rgmii(state->interface) ||
5739                  phy_interface_mode_is_8023z(state->interface) ||
5740                  state->interface == PHY_INTERFACE_MODE_SGMII)
5741                 mvpp2_gmac_config(port, mode, state);
5742
5743         if (port->priv->hw_version == MVPP21 && port->flags & MVPP2_F_LOOPBACK)
5744                 mvpp2_port_loopback_set(port, state);
5745
5746         if (port->priv->hw_version == MVPP22 && change_interface)
5747                 mvpp22_gop_unmask_irq(port);
5748
5749         mvpp2_port_enable(port);
5750 }
5751
5752 static void mvpp2_mac_link_up(struct phylink_config *config,
5753                               struct phy_device *phy,
5754                               unsigned int mode, phy_interface_t interface,
5755                               int speed, int duplex,
5756                               bool tx_pause, bool rx_pause)
5757 {
5758         struct mvpp2_port *port = mvpp2_phylink_to_port(config);
5759         u32 val;
5760
5761         if (mvpp2_is_xlg(interface)) {
5762                 if (!phylink_autoneg_inband(mode)) {
5763                         val = MVPP22_XLG_CTRL0_FORCE_LINK_PASS;
5764                         if (tx_pause)
5765                                 val |= MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN;
5766                         if (rx_pause)
5767                                 val |= MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN;
5768
5769                         mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG,
5770                                      MVPP22_XLG_CTRL0_FORCE_LINK_DOWN |
5771                                      MVPP22_XLG_CTRL0_FORCE_LINK_PASS |
5772                                      MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN |
5773                                      MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN, val);
5774                 }
5775         } else {
5776                 if (!phylink_autoneg_inband(mode)) {
5777                         val = MVPP2_GMAC_FORCE_LINK_PASS;
5778
5779                         if (speed == SPEED_1000 || speed == SPEED_2500)
5780                                 val |= MVPP2_GMAC_CONFIG_GMII_SPEED;
5781                         else if (speed == SPEED_100)
5782                                 val |= MVPP2_GMAC_CONFIG_MII_SPEED;
5783
5784                         if (duplex == DUPLEX_FULL)
5785                                 val |= MVPP2_GMAC_CONFIG_FULL_DUPLEX;
5786
5787                         mvpp2_modify(port->base + MVPP2_GMAC_AUTONEG_CONFIG,
5788                                      MVPP2_GMAC_FORCE_LINK_DOWN |
5789                                      MVPP2_GMAC_FORCE_LINK_PASS |
5790                                      MVPP2_GMAC_CONFIG_MII_SPEED |
5791                                      MVPP2_GMAC_CONFIG_GMII_SPEED |
5792                                      MVPP2_GMAC_CONFIG_FULL_DUPLEX, val);
5793                 }
5794
5795                 /* We can always update the flow control enable bits;
5796                  * these will only be effective if flow control AN
5797                  * (MVPP2_GMAC_FLOW_CTRL_AUTONEG) is disabled.
5798                  */
5799                 val = 0;
5800                 if (tx_pause)
5801                         val |= MVPP22_CTRL4_TX_FC_EN;
5802                 if (rx_pause)
5803                         val |= MVPP22_CTRL4_RX_FC_EN;
5804
5805                 mvpp2_modify(port->base + MVPP22_GMAC_CTRL_4_REG,
5806                              MVPP22_CTRL4_RX_FC_EN | MVPP22_CTRL4_TX_FC_EN,
5807                              val);
5808         }
5809
5810         mvpp2_port_enable(port);
5811
5812         mvpp2_egress_enable(port);
5813         mvpp2_ingress_enable(port);
5814         netif_tx_wake_all_queues(port->dev);
5815 }
5816
5817 static void mvpp2_mac_link_down(struct phylink_config *config,
5818                                 unsigned int mode, phy_interface_t interface)
5819 {
5820         struct mvpp2_port *port = mvpp2_phylink_to_port(config);
5821         u32 val;
5822
5823         if (!phylink_autoneg_inband(mode)) {
5824                 if (mvpp2_is_xlg(interface)) {
5825                         val = readl(port->base + MVPP22_XLG_CTRL0_REG);
5826                         val &= ~MVPP22_XLG_CTRL0_FORCE_LINK_PASS;
5827                         val |= MVPP22_XLG_CTRL0_FORCE_LINK_DOWN;
5828                         writel(val, port->base + MVPP22_XLG_CTRL0_REG);
5829                 } else {
5830                         val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
5831                         val &= ~MVPP2_GMAC_FORCE_LINK_PASS;
5832                         val |= MVPP2_GMAC_FORCE_LINK_DOWN;
5833                         writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
5834                 }
5835         }
5836
5837         netif_tx_stop_all_queues(port->dev);
5838         mvpp2_egress_disable(port);
5839         mvpp2_ingress_disable(port);
5840
5841         mvpp2_port_disable(port);
5842 }
5843
5844 static const struct phylink_mac_ops mvpp2_phylink_ops = {
5845         .validate = mvpp2_phylink_validate,
5846         .mac_pcs_get_state = mvpp2_phylink_mac_pcs_get_state,
5847         .mac_an_restart = mvpp2_mac_an_restart,
5848         .mac_config = mvpp2_mac_config,
5849         .mac_link_up = mvpp2_mac_link_up,
5850         .mac_link_down = mvpp2_mac_link_down,
5851 };
5852
5853 /* Ports initialization */
5854 static int mvpp2_port_probe(struct platform_device *pdev,
5855                             struct fwnode_handle *port_fwnode,
5856                             struct mvpp2 *priv)
5857 {
5858         struct phy *comphy = NULL;
5859         struct mvpp2_port *port;
5860         struct mvpp2_port_pcpu *port_pcpu;
5861         struct device_node *port_node = to_of_node(port_fwnode);
5862         netdev_features_t features;
5863         struct net_device *dev;
5864         struct phylink *phylink;
5865         char *mac_from = "";
5866         unsigned int ntxqs, nrxqs, thread;
5867         unsigned long flags = 0;
5868         bool has_tx_irqs;
5869         u32 id;
5870         int phy_mode;
5871         int err, i;
5872
5873         has_tx_irqs = mvpp2_port_has_irqs(priv, port_node, &flags);
5874         if (!has_tx_irqs && queue_mode == MVPP2_QDIST_MULTI_MODE) {
5875                 dev_err(&pdev->dev,
5876                         "not enough IRQs to support multi queue mode\n");
5877                 return -EINVAL;
5878         }
5879
5880         ntxqs = MVPP2_MAX_TXQ;
5881         nrxqs = mvpp2_get_nrxqs(priv);
5882
5883         dev = alloc_etherdev_mqs(sizeof(*port), ntxqs, nrxqs);
5884         if (!dev)
5885                 return -ENOMEM;
5886
5887         phy_mode = fwnode_get_phy_mode(port_fwnode);
5888         if (phy_mode < 0) {
5889                 dev_err(&pdev->dev, "incorrect phy mode\n");
5890                 err = phy_mode;
5891                 goto err_free_netdev;
5892         }
5893
5894         /*
5895          * Rewrite 10GBASE-KR to 10GBASE-R for compatibility with existing DT.
5896          * Existing usage of 10GBASE-KR is not correct; no backplane
5897          * negotiation is done, and this driver does not actually support
5898          * 10GBASE-KR.
5899          */
5900         if (phy_mode == PHY_INTERFACE_MODE_10GKR)
5901                 phy_mode = PHY_INTERFACE_MODE_10GBASER;
5902
5903         if (port_node) {
5904                 comphy = devm_of_phy_get(&pdev->dev, port_node, NULL);
5905                 if (IS_ERR(comphy)) {
5906                         if (PTR_ERR(comphy) == -EPROBE_DEFER) {
5907                                 err = -EPROBE_DEFER;
5908                                 goto err_free_netdev;
5909                         }
5910                         comphy = NULL;
5911                 }
5912         }
5913
5914         if (fwnode_property_read_u32(port_fwnode, "port-id", &id)) {
5915                 err = -EINVAL;
5916                 dev_err(&pdev->dev, "missing port-id value\n");
5917                 goto err_free_netdev;
5918         }
5919
5920         dev->tx_queue_len = MVPP2_MAX_TXD_MAX;
5921         dev->watchdog_timeo = 5 * HZ;
5922         dev->netdev_ops = &mvpp2_netdev_ops;
5923         dev->ethtool_ops = &mvpp2_eth_tool_ops;
5924
5925         port = netdev_priv(dev);
5926         port->dev = dev;
5927         port->fwnode = port_fwnode;
5928         port->has_phy = !!of_find_property(port_node, "phy", NULL);
5929         port->ntxqs = ntxqs;
5930         port->nrxqs = nrxqs;
5931         port->priv = priv;
5932         port->has_tx_irqs = has_tx_irqs;
5933         port->flags = flags;
5934
5935         err = mvpp2_queue_vectors_init(port, port_node);
5936         if (err)
5937                 goto err_free_netdev;
5938
5939         if (port_node)
5940                 port->link_irq = of_irq_get_byname(port_node, "link");
5941         else
5942                 port->link_irq = fwnode_irq_get(port_fwnode, port->nqvecs + 1);
5943         if (port->link_irq == -EPROBE_DEFER) {
5944                 err = -EPROBE_DEFER;
5945                 goto err_deinit_qvecs;
5946         }
5947         if (port->link_irq <= 0)
5948                 /* the link irq is optional */
5949                 port->link_irq = 0;
5950
5951         if (fwnode_property_read_bool(port_fwnode, "marvell,loopback"))
5952                 port->flags |= MVPP2_F_LOOPBACK;
5953
5954         port->id = id;
5955         if (priv->hw_version == MVPP21)
5956                 port->first_rxq = port->id * port->nrxqs;
5957         else
5958                 port->first_rxq = port->id * priv->max_port_rxqs;
5959
5960         port->of_node = port_node;
5961         port->phy_interface = phy_mode;
5962         port->comphy = comphy;
5963
5964         if (priv->hw_version == MVPP21) {
5965                 port->base = devm_platform_ioremap_resource(pdev, 2 + id);
5966                 if (IS_ERR(port->base)) {
5967                         err = PTR_ERR(port->base);
5968                         goto err_free_irq;
5969                 }
5970
5971                 port->stats_base = port->priv->lms_base +
5972                                    MVPP21_MIB_COUNTERS_OFFSET +
5973                                    port->gop_id * MVPP21_MIB_COUNTERS_PORT_SZ;
5974         } else {
5975                 if (fwnode_property_read_u32(port_fwnode, "gop-port-id",
5976                                              &port->gop_id)) {
5977                         err = -EINVAL;
5978                         dev_err(&pdev->dev, "missing gop-port-id value\n");
5979                         goto err_deinit_qvecs;
5980                 }
5981
5982                 port->base = priv->iface_base + MVPP22_GMAC_BASE(port->gop_id);
5983                 port->stats_base = port->priv->iface_base +
5984                                    MVPP22_MIB_COUNTERS_OFFSET +
5985                                    port->gop_id * MVPP22_MIB_COUNTERS_PORT_SZ;
5986         }
5987
5988         /* Alloc per-cpu and ethtool stats */
5989         port->stats = netdev_alloc_pcpu_stats(struct mvpp2_pcpu_stats);
5990         if (!port->stats) {
5991                 err = -ENOMEM;
5992                 goto err_free_irq;
5993         }
5994
5995         port->ethtool_stats = devm_kcalloc(&pdev->dev,
5996                                            MVPP2_N_ETHTOOL_STATS(ntxqs, nrxqs),
5997                                            sizeof(u64), GFP_KERNEL);
5998         if (!port->ethtool_stats) {
5999                 err = -ENOMEM;
6000                 goto err_free_stats;
6001         }
6002
6003         mutex_init(&port->gather_stats_lock);
6004         INIT_DELAYED_WORK(&port->stats_work, mvpp2_gather_hw_statistics);
6005
6006         mvpp2_port_copy_mac_addr(dev, priv, port_fwnode, &mac_from);
6007
6008         port->tx_ring_size = MVPP2_MAX_TXD_DFLT;
6009         port->rx_ring_size = MVPP2_MAX_RXD_DFLT;
6010         SET_NETDEV_DEV(dev, &pdev->dev);
6011
6012         err = mvpp2_port_init(port);
6013         if (err < 0) {
6014                 dev_err(&pdev->dev, "failed to init port %d\n", id);
6015                 goto err_free_stats;
6016         }
6017
6018         mvpp2_port_periodic_xon_disable(port);
6019
6020         mvpp2_mac_reset_assert(port);
6021         mvpp22_pcs_reset_assert(port);
6022
6023         port->pcpu = alloc_percpu(struct mvpp2_port_pcpu);
6024         if (!port->pcpu) {
6025                 err = -ENOMEM;
6026                 goto err_free_txq_pcpu;
6027         }
6028
6029         if (!port->has_tx_irqs) {
6030                 for (thread = 0; thread < priv->nthreads; thread++) {
6031                         port_pcpu = per_cpu_ptr(port->pcpu, thread);
6032
6033                         hrtimer_init(&port_pcpu->tx_done_timer, CLOCK_MONOTONIC,
6034                                      HRTIMER_MODE_REL_PINNED_SOFT);
6035                         port_pcpu->tx_done_timer.function = mvpp2_hr_timer_cb;
6036                         port_pcpu->timer_scheduled = false;
6037                         port_pcpu->dev = dev;
6038                 }
6039         }
6040
6041         features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
6042                    NETIF_F_TSO;
6043         dev->features = features | NETIF_F_RXCSUM;
6044         dev->hw_features |= features | NETIF_F_RXCSUM | NETIF_F_GRO |
6045                             NETIF_F_HW_VLAN_CTAG_FILTER;
6046
6047         if (mvpp22_rss_is_supported()) {
6048                 dev->hw_features |= NETIF_F_RXHASH;
6049                 dev->features |= NETIF_F_NTUPLE;
6050         }
6051
6052         if (!port->priv->percpu_pools)
6053                 mvpp2_set_hw_csum(port, port->pool_long->id);
6054
6055         dev->vlan_features |= features;
6056         dev->gso_max_segs = MVPP2_MAX_TSO_SEGS;
6057         dev->priv_flags |= IFF_UNICAST_FLT;
6058
6059         /* MTU range: 68 - 9704 */
6060         dev->min_mtu = ETH_MIN_MTU;
6061         /* 9704 == 9728 - 20 and rounding to 8 */
6062         dev->max_mtu = MVPP2_BM_JUMBO_PKT_SIZE;
6063         dev->dev.of_node = port_node;
6064
6065         /* Phylink isn't used w/ ACPI as of now */
6066         if (port_node) {
6067                 port->phylink_config.dev = &dev->dev;
6068                 port->phylink_config.type = PHYLINK_NETDEV;
6069
6070                 phylink = phylink_create(&port->phylink_config, port_fwnode,
6071                                          phy_mode, &mvpp2_phylink_ops);
6072                 if (IS_ERR(phylink)) {
6073                         err = PTR_ERR(phylink);
6074                         goto err_free_port_pcpu;
6075                 }
6076                 port->phylink = phylink;
6077         } else {
6078                 port->phylink = NULL;
6079         }
6080
6081         /* Cycle the comphy to power it down, saving 270mW per port -
6082          * don't worry about an error powering it up. When the comphy
6083          * driver does this, we can remove this code.
6084          */
6085         if (port->comphy) {
6086                 err = mvpp22_comphy_init(port);
6087                 if (err == 0)
6088                         phy_power_off(port->comphy);
6089         }
6090
6091         err = register_netdev(dev);
6092         if (err < 0) {
6093                 dev_err(&pdev->dev, "failed to register netdev\n");
6094                 goto err_phylink;
6095         }
6096         netdev_info(dev, "Using %s mac address %pM\n", mac_from, dev->dev_addr);
6097
6098         priv->port_list[priv->port_count++] = port;
6099
6100         return 0;
6101
6102 err_phylink:
6103         if (port->phylink)
6104                 phylink_destroy(port->phylink);
6105 err_free_port_pcpu:
6106         free_percpu(port->pcpu);
6107 err_free_txq_pcpu:
6108         for (i = 0; i < port->ntxqs; i++)
6109                 free_percpu(port->txqs[i]->pcpu);
6110 err_free_stats:
6111         free_percpu(port->stats);
6112 err_free_irq:
6113         if (port->link_irq)
6114                 irq_dispose_mapping(port->link_irq);
6115 err_deinit_qvecs:
6116         mvpp2_queue_vectors_deinit(port);
6117 err_free_netdev:
6118         free_netdev(dev);
6119         return err;
6120 }
6121
6122 /* Ports removal routine */
6123 static void mvpp2_port_remove(struct mvpp2_port *port)
6124 {
6125         int i;
6126
6127         unregister_netdev(port->dev);
6128         if (port->phylink)
6129                 phylink_destroy(port->phylink);
6130         free_percpu(port->pcpu);
6131         free_percpu(port->stats);
6132         for (i = 0; i < port->ntxqs; i++)
6133                 free_percpu(port->txqs[i]->pcpu);
6134         mvpp2_queue_vectors_deinit(port);
6135         if (port->link_irq)
6136                 irq_dispose_mapping(port->link_irq);
6137         free_netdev(port->dev);
6138 }
6139
6140 /* Initialize decoding windows */
6141 static void mvpp2_conf_mbus_windows(const struct mbus_dram_target_info *dram,
6142                                     struct mvpp2 *priv)
6143 {
6144         u32 win_enable;
6145         int i;
6146
6147         for (i = 0; i < 6; i++) {
6148                 mvpp2_write(priv, MVPP2_WIN_BASE(i), 0);
6149                 mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0);
6150
6151                 if (i < 4)
6152                         mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0);
6153         }
6154
6155         win_enable = 0;
6156
6157         for (i = 0; i < dram->num_cs; i++) {
6158                 const struct mbus_dram_window *cs = dram->cs + i;
6159
6160                 mvpp2_write(priv, MVPP2_WIN_BASE(i),
6161                             (cs->base & 0xffff0000) | (cs->mbus_attr << 8) |
6162                             dram->mbus_dram_target_id);
6163
6164                 mvpp2_write(priv, MVPP2_WIN_SIZE(i),
6165                             (cs->size - 1) & 0xffff0000);
6166
6167                 win_enable |= (1 << i);
6168         }
6169
6170         mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable);
6171 }
6172
6173 /* Initialize Rx FIFO's */
6174 static void mvpp2_rx_fifo_init(struct mvpp2 *priv)
6175 {
6176         int port;
6177
6178         for (port = 0; port < MVPP2_MAX_PORTS; port++) {
6179                 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
6180                             MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB);
6181                 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
6182                             MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB);
6183         }
6184
6185         mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
6186                     MVPP2_RX_FIFO_PORT_MIN_PKT);
6187         mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
6188 }
6189
6190 static void mvpp22_rx_fifo_init(struct mvpp2 *priv)
6191 {
6192         int port;
6193
6194         /* The FIFO size parameters are set depending on the maximum speed a
6195          * given port can handle:
6196          * - Port 0: 10Gbps
6197          * - Port 1: 2.5Gbps
6198          * - Ports 2 and 3: 1Gbps
6199          */
6200
6201         mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(0),
6202                     MVPP2_RX_FIFO_PORT_DATA_SIZE_32KB);
6203         mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(0),
6204                     MVPP2_RX_FIFO_PORT_ATTR_SIZE_32KB);
6205
6206         mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(1),
6207                     MVPP2_RX_FIFO_PORT_DATA_SIZE_8KB);
6208         mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(1),
6209                     MVPP2_RX_FIFO_PORT_ATTR_SIZE_8KB);
6210
6211         for (port = 2; port < MVPP2_MAX_PORTS; port++) {
6212                 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
6213                             MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB);
6214                 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
6215                             MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB);
6216         }
6217
6218         mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
6219                     MVPP2_RX_FIFO_PORT_MIN_PKT);
6220         mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
6221 }
6222
6223 /* Initialize Tx FIFO's: the total FIFO size is 19kB on PPv2.2 and 10G
6224  * interfaces must have a Tx FIFO size of 10kB. As only port 0 can do 10G,
6225  * configure its Tx FIFO size to 10kB and the others ports Tx FIFO size to 3kB.
6226  */
6227 static void mvpp22_tx_fifo_init(struct mvpp2 *priv)
6228 {
6229         int port, size, thrs;
6230
6231         for (port = 0; port < MVPP2_MAX_PORTS; port++) {
6232                 if (port == 0) {
6233                         size = MVPP22_TX_FIFO_DATA_SIZE_10KB;
6234                         thrs = MVPP2_TX_FIFO_THRESHOLD_10KB;
6235                 } else {
6236                         size = MVPP22_TX_FIFO_DATA_SIZE_3KB;
6237                         thrs = MVPP2_TX_FIFO_THRESHOLD_3KB;
6238                 }
6239                 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), size);
6240                 mvpp2_write(priv, MVPP22_TX_FIFO_THRESH_REG(port), thrs);
6241         }
6242 }
6243
6244 static void mvpp2_axi_init(struct mvpp2 *priv)
6245 {
6246         u32 val, rdval, wrval;
6247
6248         mvpp2_write(priv, MVPP22_BM_ADDR_HIGH_RLS_REG, 0x0);
6249
6250         /* AXI Bridge Configuration */
6251
6252         rdval = MVPP22_AXI_CODE_CACHE_RD_CACHE
6253                 << MVPP22_AXI_ATTR_CACHE_OFFS;
6254         rdval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
6255                 << MVPP22_AXI_ATTR_DOMAIN_OFFS;
6256
6257         wrval = MVPP22_AXI_CODE_CACHE_WR_CACHE
6258                 << MVPP22_AXI_ATTR_CACHE_OFFS;
6259         wrval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
6260                 << MVPP22_AXI_ATTR_DOMAIN_OFFS;
6261
6262         /* BM */
6263         mvpp2_write(priv, MVPP22_AXI_BM_WR_ATTR_REG, wrval);
6264         mvpp2_write(priv, MVPP22_AXI_BM_RD_ATTR_REG, rdval);
6265
6266         /* Descriptors */
6267         mvpp2_write(priv, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, rdval);
6268         mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, wrval);
6269         mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, rdval);
6270         mvpp2_write(priv, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, wrval);
6271
6272         /* Buffer Data */
6273         mvpp2_write(priv, MVPP22_AXI_TX_DATA_RD_ATTR_REG, rdval);
6274         mvpp2_write(priv, MVPP22_AXI_RX_DATA_WR_ATTR_REG, wrval);
6275
6276         val = MVPP22_AXI_CODE_CACHE_NON_CACHE
6277                 << MVPP22_AXI_CODE_CACHE_OFFS;
6278         val |= MVPP22_AXI_CODE_DOMAIN_SYSTEM
6279                 << MVPP22_AXI_CODE_DOMAIN_OFFS;
6280         mvpp2_write(priv, MVPP22_AXI_RD_NORMAL_CODE_REG, val);
6281         mvpp2_write(priv, MVPP22_AXI_WR_NORMAL_CODE_REG, val);
6282
6283         val = MVPP22_AXI_CODE_CACHE_RD_CACHE
6284                 << MVPP22_AXI_CODE_CACHE_OFFS;
6285         val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
6286                 << MVPP22_AXI_CODE_DOMAIN_OFFS;
6287
6288         mvpp2_write(priv, MVPP22_AXI_RD_SNOOP_CODE_REG, val);
6289
6290         val = MVPP22_AXI_CODE_CACHE_WR_CACHE
6291                 << MVPP22_AXI_CODE_CACHE_OFFS;
6292         val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
6293                 << MVPP22_AXI_CODE_DOMAIN_OFFS;
6294
6295         mvpp2_write(priv, MVPP22_AXI_WR_SNOOP_CODE_REG, val);
6296 }
6297
6298 /* Initialize network controller common part HW */
6299 static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv)
6300 {
6301         const struct mbus_dram_target_info *dram_target_info;
6302         int err, i;
6303         u32 val;
6304
6305         /* MBUS windows configuration */
6306         dram_target_info = mv_mbus_dram_info();
6307         if (dram_target_info)
6308                 mvpp2_conf_mbus_windows(dram_target_info, priv);
6309
6310         if (priv->hw_version == MVPP22)
6311                 mvpp2_axi_init(priv);
6312
6313         /* Disable HW PHY polling */
6314         if (priv->hw_version == MVPP21) {
6315                 val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
6316                 val |= MVPP2_PHY_AN_STOP_SMI0_MASK;
6317                 writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
6318         } else {
6319                 val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
6320                 val &= ~MVPP22_SMI_POLLING_EN;
6321                 writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
6322         }
6323
6324         /* Allocate and initialize aggregated TXQs */
6325         priv->aggr_txqs = devm_kcalloc(&pdev->dev, MVPP2_MAX_THREADS,
6326                                        sizeof(*priv->aggr_txqs),
6327                                        GFP_KERNEL);
6328         if (!priv->aggr_txqs)
6329                 return -ENOMEM;
6330
6331         for (i = 0; i < MVPP2_MAX_THREADS; i++) {
6332                 priv->aggr_txqs[i].id = i;
6333                 priv->aggr_txqs[i].size = MVPP2_AGGR_TXQ_SIZE;
6334                 err = mvpp2_aggr_txq_init(pdev, &priv->aggr_txqs[i], i, priv);
6335                 if (err < 0)
6336                         return err;
6337         }
6338
6339         /* Fifo Init */
6340         if (priv->hw_version == MVPP21) {
6341                 mvpp2_rx_fifo_init(priv);
6342         } else {
6343                 mvpp22_rx_fifo_init(priv);
6344                 mvpp22_tx_fifo_init(priv);
6345         }
6346
6347         if (priv->hw_version == MVPP21)
6348                 writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT,
6349                        priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG);
6350
6351         /* Allow cache snoop when transmiting packets */
6352         mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1);
6353
6354         /* Buffer Manager initialization */
6355         err = mvpp2_bm_init(&pdev->dev, priv);
6356         if (err < 0)
6357                 return err;
6358
6359         /* Parser default initialization */
6360         err = mvpp2_prs_default_init(pdev, priv);
6361         if (err < 0)
6362                 return err;
6363
6364         /* Classifier default initialization */
6365         mvpp2_cls_init(priv);
6366
6367         return 0;
6368 }
6369
6370 static int mvpp2_probe(struct platform_device *pdev)
6371 {
6372         const struct acpi_device_id *acpi_id;
6373         struct fwnode_handle *fwnode = pdev->dev.fwnode;
6374         struct fwnode_handle *port_fwnode;
6375         struct mvpp2 *priv;
6376         struct resource *res;
6377         void __iomem *base;
6378         int i, shared;
6379         int err;
6380
6381         priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
6382         if (!priv)
6383                 return -ENOMEM;
6384
6385         if (has_acpi_companion(&pdev->dev)) {
6386                 acpi_id = acpi_match_device(pdev->dev.driver->acpi_match_table,
6387                                             &pdev->dev);
6388                 if (!acpi_id)
6389                         return -EINVAL;
6390                 priv->hw_version = (unsigned long)acpi_id->driver_data;
6391         } else {
6392                 priv->hw_version =
6393                         (unsigned long)of_device_get_match_data(&pdev->dev);
6394         }
6395
6396         /* multi queue mode isn't supported on PPV2.1, fallback to single
6397          * mode
6398          */
6399         if (priv->hw_version == MVPP21)
6400                 queue_mode = MVPP2_QDIST_SINGLE_MODE;
6401
6402         base = devm_platform_ioremap_resource(pdev, 0);
6403         if (IS_ERR(base))
6404                 return PTR_ERR(base);
6405
6406         if (priv->hw_version == MVPP21) {
6407                 priv->lms_base = devm_platform_ioremap_resource(pdev, 1);
6408                 if (IS_ERR(priv->lms_base))
6409                         return PTR_ERR(priv->lms_base);
6410         } else {
6411                 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
6412                 if (has_acpi_companion(&pdev->dev)) {
6413                         /* In case the MDIO memory region is declared in
6414                          * the ACPI, it can already appear as 'in-use'
6415                          * in the OS. Because it is overlapped by second
6416                          * region of the network controller, make
6417                          * sure it is released, before requesting it again.
6418                          * The care is taken by mvpp2 driver to avoid
6419                          * concurrent access to this memory region.
6420                          */
6421                         release_resource(res);
6422                 }
6423                 priv->iface_base = devm_ioremap_resource(&pdev->dev, res);
6424                 if (IS_ERR(priv->iface_base))
6425                         return PTR_ERR(priv->iface_base);
6426         }
6427
6428         if (priv->hw_version == MVPP22 && dev_of_node(&pdev->dev)) {
6429                 priv->sysctrl_base =
6430                         syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
6431                                                         "marvell,system-controller");
6432                 if (IS_ERR(priv->sysctrl_base))
6433                         /* The system controller regmap is optional for dt
6434                          * compatibility reasons. When not provided, the
6435                          * configuration of the GoP relies on the
6436                          * firmware/bootloader.
6437                          */
6438                         priv->sysctrl_base = NULL;
6439         }
6440
6441         if (priv->hw_version == MVPP22 &&
6442             mvpp2_get_nrxqs(priv) * 2 <= MVPP2_BM_MAX_POOLS)
6443                 priv->percpu_pools = 1;
6444
6445         mvpp2_setup_bm_pool();
6446
6447
6448         priv->nthreads = min_t(unsigned int, num_present_cpus(),
6449                                MVPP2_MAX_THREADS);
6450
6451         shared = num_present_cpus() - priv->nthreads;
6452         if (shared > 0)
6453                 bitmap_fill(&priv->lock_map,
6454                             min_t(int, shared, MVPP2_MAX_THREADS));
6455
6456         for (i = 0; i < MVPP2_MAX_THREADS; i++) {
6457                 u32 addr_space_sz;
6458
6459                 addr_space_sz = (priv->hw_version == MVPP21 ?
6460                                  MVPP21_ADDR_SPACE_SZ : MVPP22_ADDR_SPACE_SZ);
6461                 priv->swth_base[i] = base + i * addr_space_sz;
6462         }
6463
6464         if (priv->hw_version == MVPP21)
6465                 priv->max_port_rxqs = 8;
6466         else
6467                 priv->max_port_rxqs = 32;
6468
6469         if (dev_of_node(&pdev->dev)) {
6470                 priv->pp_clk = devm_clk_get(&pdev->dev, "pp_clk");
6471                 if (IS_ERR(priv->pp_clk))
6472                         return PTR_ERR(priv->pp_clk);
6473                 err = clk_prepare_enable(priv->pp_clk);
6474                 if (err < 0)
6475                         return err;
6476
6477                 priv->gop_clk = devm_clk_get(&pdev->dev, "gop_clk");
6478                 if (IS_ERR(priv->gop_clk)) {
6479                         err = PTR_ERR(priv->gop_clk);
6480                         goto err_pp_clk;
6481                 }
6482                 err = clk_prepare_enable(priv->gop_clk);
6483                 if (err < 0)
6484                         goto err_pp_clk;
6485
6486                 if (priv->hw_version == MVPP22) {
6487                         priv->mg_clk = devm_clk_get(&pdev->dev, "mg_clk");
6488                         if (IS_ERR(priv->mg_clk)) {
6489                                 err = PTR_ERR(priv->mg_clk);
6490                                 goto err_gop_clk;
6491                         }
6492
6493                         err = clk_prepare_enable(priv->mg_clk);
6494                         if (err < 0)
6495                                 goto err_gop_clk;
6496
6497                         priv->mg_core_clk = devm_clk_get(&pdev->dev, "mg_core_clk");
6498                         if (IS_ERR(priv->mg_core_clk)) {
6499                                 priv->mg_core_clk = NULL;
6500                         } else {
6501                                 err = clk_prepare_enable(priv->mg_core_clk);
6502                                 if (err < 0)
6503                                         goto err_mg_clk;
6504                         }
6505                 }
6506
6507                 priv->axi_clk = devm_clk_get(&pdev->dev, "axi_clk");
6508                 if (IS_ERR(priv->axi_clk)) {
6509                         err = PTR_ERR(priv->axi_clk);
6510                         if (err == -EPROBE_DEFER)
6511                                 goto err_mg_core_clk;
6512                         priv->axi_clk = NULL;
6513                 } else {
6514                         err = clk_prepare_enable(priv->axi_clk);
6515                         if (err < 0)
6516                                 goto err_mg_core_clk;
6517                 }
6518
6519                 /* Get system's tclk rate */
6520                 priv->tclk = clk_get_rate(priv->pp_clk);
6521         } else if (device_property_read_u32(&pdev->dev, "clock-frequency",
6522                                             &priv->tclk)) {
6523                 dev_err(&pdev->dev, "missing clock-frequency value\n");
6524                 return -EINVAL;
6525         }
6526
6527         if (priv->hw_version == MVPP22) {
6528                 err = dma_set_mask(&pdev->dev, MVPP2_DESC_DMA_MASK);
6529                 if (err)
6530                         goto err_axi_clk;
6531                 /* Sadly, the BM pools all share the same register to
6532                  * store the high 32 bits of their address. So they
6533                  * must all have the same high 32 bits, which forces
6534                  * us to restrict coherent memory to DMA_BIT_MASK(32).
6535                  */
6536                 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
6537                 if (err)
6538                         goto err_axi_clk;
6539         }
6540
6541         /* Initialize network controller */
6542         err = mvpp2_init(pdev, priv);
6543         if (err < 0) {
6544                 dev_err(&pdev->dev, "failed to initialize controller\n");
6545                 goto err_axi_clk;
6546         }
6547
6548         /* Initialize ports */
6549         fwnode_for_each_available_child_node(fwnode, port_fwnode) {
6550                 err = mvpp2_port_probe(pdev, port_fwnode, priv);
6551                 if (err < 0)
6552                         goto err_port_probe;
6553         }
6554
6555         if (priv->port_count == 0) {
6556                 dev_err(&pdev->dev, "no ports enabled\n");
6557                 err = -ENODEV;
6558                 goto err_axi_clk;
6559         }
6560
6561         /* Statistics must be gathered regularly because some of them (like
6562          * packets counters) are 32-bit registers and could overflow quite
6563          * quickly. For instance, a 10Gb link used at full bandwidth with the
6564          * smallest packets (64B) will overflow a 32-bit counter in less than
6565          * 30 seconds. Then, use a workqueue to fill 64-bit counters.
6566          */
6567         snprintf(priv->queue_name, sizeof(priv->queue_name),
6568                  "stats-wq-%s%s", netdev_name(priv->port_list[0]->dev),
6569                  priv->port_count > 1 ? "+" : "");
6570         priv->stats_queue = create_singlethread_workqueue(priv->queue_name);
6571         if (!priv->stats_queue) {
6572                 err = -ENOMEM;
6573                 goto err_port_probe;
6574         }
6575
6576         mvpp2_dbgfs_init(priv, pdev->name);
6577
6578         platform_set_drvdata(pdev, priv);
6579         return 0;
6580
6581 err_port_probe:
6582         i = 0;
6583         fwnode_for_each_available_child_node(fwnode, port_fwnode) {
6584                 if (priv->port_list[i])
6585                         mvpp2_port_remove(priv->port_list[i]);
6586                 i++;
6587         }
6588 err_axi_clk:
6589         clk_disable_unprepare(priv->axi_clk);
6590
6591 err_mg_core_clk:
6592         if (priv->hw_version == MVPP22)
6593                 clk_disable_unprepare(priv->mg_core_clk);
6594 err_mg_clk:
6595         if (priv->hw_version == MVPP22)
6596                 clk_disable_unprepare(priv->mg_clk);
6597 err_gop_clk:
6598         clk_disable_unprepare(priv->gop_clk);
6599 err_pp_clk:
6600         clk_disable_unprepare(priv->pp_clk);
6601         return err;
6602 }
6603
6604 static int mvpp2_remove(struct platform_device *pdev)
6605 {
6606         struct mvpp2 *priv = platform_get_drvdata(pdev);
6607         struct fwnode_handle *fwnode = pdev->dev.fwnode;
6608         int i = 0, poolnum = MVPP2_BM_POOLS_NUM;
6609         struct fwnode_handle *port_fwnode;
6610
6611         mvpp2_dbgfs_cleanup(priv);
6612
6613         fwnode_for_each_available_child_node(fwnode, port_fwnode) {
6614                 if (priv->port_list[i]) {
6615                         mutex_destroy(&priv->port_list[i]->gather_stats_lock);
6616                         mvpp2_port_remove(priv->port_list[i]);
6617                 }
6618                 i++;
6619         }
6620
6621         destroy_workqueue(priv->stats_queue);
6622
6623         if (priv->percpu_pools)
6624                 poolnum = mvpp2_get_nrxqs(priv) * 2;
6625
6626         for (i = 0; i < poolnum; i++) {
6627                 struct mvpp2_bm_pool *bm_pool = &priv->bm_pools[i];
6628
6629                 mvpp2_bm_pool_destroy(&pdev->dev, priv, bm_pool);
6630         }
6631
6632         for (i = 0; i < MVPP2_MAX_THREADS; i++) {
6633                 struct mvpp2_tx_queue *aggr_txq = &priv->aggr_txqs[i];
6634
6635                 dma_free_coherent(&pdev->dev,
6636                                   MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE,
6637                                   aggr_txq->descs,
6638                                   aggr_txq->descs_dma);
6639         }
6640
6641         if (is_acpi_node(port_fwnode))
6642                 return 0;
6643
6644         clk_disable_unprepare(priv->axi_clk);
6645         clk_disable_unprepare(priv->mg_core_clk);
6646         clk_disable_unprepare(priv->mg_clk);
6647         clk_disable_unprepare(priv->pp_clk);
6648         clk_disable_unprepare(priv->gop_clk);
6649
6650         return 0;
6651 }
6652
6653 static const struct of_device_id mvpp2_match[] = {
6654         {
6655                 .compatible = "marvell,armada-375-pp2",
6656                 .data = (void *)MVPP21,
6657         },
6658         {
6659                 .compatible = "marvell,armada-7k-pp22",
6660                 .data = (void *)MVPP22,
6661         },
6662         { }
6663 };
6664 MODULE_DEVICE_TABLE(of, mvpp2_match);
6665
6666 static const struct acpi_device_id mvpp2_acpi_match[] = {
6667         { "MRVL0110", MVPP22 },
6668         { },
6669 };
6670 MODULE_DEVICE_TABLE(acpi, mvpp2_acpi_match);
6671
6672 static struct platform_driver mvpp2_driver = {
6673         .probe = mvpp2_probe,
6674         .remove = mvpp2_remove,
6675         .driver = {
6676                 .name = MVPP2_DRIVER_NAME,
6677                 .of_match_table = mvpp2_match,
6678                 .acpi_match_table = ACPI_PTR(mvpp2_acpi_match),
6679         },
6680 };
6681
6682 module_platform_driver(mvpp2_driver);
6683
6684 MODULE_DESCRIPTION("Marvell PPv2 Ethernet Driver - www.marvell.com");
6685 MODULE_AUTHOR("Marcin Wojtas <mw@semihalf.com>");
6686 MODULE_LICENSE("GPL v2");