2 * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs.
4 * Copyright (C) 2012 Marvell
6 * Rami Rosen <rosenr@marvell.com>
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
14 #include <linux/clk.h>
15 #include <linux/cpu.h>
16 #include <linux/etherdevice.h>
17 #include <linux/if_vlan.h>
18 #include <linux/inetdevice.h>
19 #include <linux/interrupt.h>
21 #include <linux/kernel.h>
22 #include <linux/mbus.h>
23 #include <linux/module.h>
24 #include <linux/netdevice.h>
26 #include <linux/of_address.h>
27 #include <linux/of_irq.h>
28 #include <linux/of_mdio.h>
29 #include <linux/of_net.h>
30 #include <linux/phy.h>
31 #include <linux/phylink.h>
32 #include <linux/platform_device.h>
33 #include <linux/skbuff.h>
35 #include "mvneta_bm.h"
41 #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2))
42 #define MVNETA_RXQ_HW_BUF_ALLOC BIT(0)
43 #define MVNETA_RXQ_SHORT_POOL_ID_SHIFT 4
44 #define MVNETA_RXQ_SHORT_POOL_ID_MASK 0x30
45 #define MVNETA_RXQ_LONG_POOL_ID_SHIFT 6
46 #define MVNETA_RXQ_LONG_POOL_ID_MASK 0xc0
47 #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8)
48 #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8)
49 #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2))
50 #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16)
51 #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2))
52 #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2))
53 #define MVNETA_RXQ_BUF_SIZE_SHIFT 19
54 #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19)
55 #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2))
56 #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff
57 #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2))
58 #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16
59 #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255
60 #define MVNETA_PORT_POOL_BUFFER_SZ_REG(pool) (0x1700 + ((pool) << 2))
61 #define MVNETA_PORT_POOL_BUFFER_SZ_SHIFT 3
62 #define MVNETA_PORT_POOL_BUFFER_SZ_MASK 0xfff8
63 #define MVNETA_PORT_RX_RESET 0x1cc0
64 #define MVNETA_PORT_RX_DMA_RESET BIT(0)
65 #define MVNETA_PHY_ADDR 0x2000
66 #define MVNETA_PHY_ADDR_MASK 0x1f
67 #define MVNETA_MBUS_RETRY 0x2010
68 #define MVNETA_UNIT_INTR_CAUSE 0x2080
69 #define MVNETA_UNIT_CONTROL 0x20B0
70 #define MVNETA_PHY_POLLING_ENABLE BIT(1)
71 #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3))
72 #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3))
73 #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2))
74 #define MVNETA_BASE_ADDR_ENABLE 0x2290
75 #define MVNETA_ACCESS_PROTECT_ENABLE 0x2294
76 #define MVNETA_PORT_CONFIG 0x2400
77 #define MVNETA_UNI_PROMISC_MODE BIT(0)
78 #define MVNETA_DEF_RXQ(q) ((q) << 1)
79 #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4)
80 #define MVNETA_TX_UNSET_ERR_SUM BIT(12)
81 #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16)
82 #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19)
83 #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22)
84 #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25)
85 #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \
86 MVNETA_DEF_RXQ_ARP(q) | \
87 MVNETA_DEF_RXQ_TCP(q) | \
88 MVNETA_DEF_RXQ_UDP(q) | \
89 MVNETA_DEF_RXQ_BPDU(q) | \
90 MVNETA_TX_UNSET_ERR_SUM | \
91 MVNETA_RX_CSUM_WITH_PSEUDO_HDR)
92 #define MVNETA_PORT_CONFIG_EXTEND 0x2404
93 #define MVNETA_MAC_ADDR_LOW 0x2414
94 #define MVNETA_MAC_ADDR_HIGH 0x2418
95 #define MVNETA_SDMA_CONFIG 0x241c
96 #define MVNETA_SDMA_BRST_SIZE_16 4
97 #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1)
98 #define MVNETA_RX_NO_DATA_SWAP BIT(4)
99 #define MVNETA_TX_NO_DATA_SWAP BIT(5)
100 #define MVNETA_DESC_SWAP BIT(6)
101 #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22)
102 #define MVNETA_PORT_STATUS 0x2444
103 #define MVNETA_TX_IN_PRGRS BIT(1)
104 #define MVNETA_TX_FIFO_EMPTY BIT(8)
105 #define MVNETA_RX_MIN_FRAME_SIZE 0x247c
106 #define MVNETA_SERDES_CFG 0x24A0
107 #define MVNETA_SGMII_SERDES_PROTO 0x0cc7
108 #define MVNETA_QSGMII_SERDES_PROTO 0x0667
109 #define MVNETA_TYPE_PRIO 0x24bc
110 #define MVNETA_FORCE_UNI BIT(21)
111 #define MVNETA_TXQ_CMD_1 0x24e4
112 #define MVNETA_TXQ_CMD 0x2448
113 #define MVNETA_TXQ_DISABLE_SHIFT 8
114 #define MVNETA_TXQ_ENABLE_MASK 0x000000ff
115 #define MVNETA_RX_DISCARD_FRAME_COUNT 0x2484
116 #define MVNETA_OVERRUN_FRAME_COUNT 0x2488
117 #define MVNETA_GMAC_CLOCK_DIVIDER 0x24f4
118 #define MVNETA_GMAC_1MS_CLOCK_ENABLE BIT(31)
119 #define MVNETA_ACC_MODE 0x2500
120 #define MVNETA_BM_ADDRESS 0x2504
121 #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2))
122 #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff
123 #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00
124 #define MVNETA_CPU_RXQ_ACCESS(rxq) BIT(rxq)
125 #define MVNETA_CPU_TXQ_ACCESS(txq) BIT(txq + 8)
126 #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2))
128 /* Exception Interrupt Port/Queue Cause register
130 * Their behavior depend of the mapping done using the PCPX2Q
131 * registers. For a given CPU if the bit associated to a queue is not
132 * set, then for the register a read from this CPU will always return
133 * 0 and a write won't do anything
136 #define MVNETA_INTR_NEW_CAUSE 0x25a0
137 #define MVNETA_INTR_NEW_MASK 0x25a4
139 /* bits 0..7 = TXQ SENT, one bit per queue.
140 * bits 8..15 = RXQ OCCUP, one bit per queue.
141 * bits 16..23 = RXQ FREE, one bit per queue.
142 * bit 29 = OLD_REG_SUM, see old reg ?
143 * bit 30 = TX_ERR_SUM, one bit for 4 ports
144 * bit 31 = MISC_SUM, one bit for 4 ports
146 #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0)
147 #define MVNETA_TX_INTR_MASK_ALL (0xff << 0)
148 #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8)
149 #define MVNETA_RX_INTR_MASK_ALL (0xff << 8)
150 #define MVNETA_MISCINTR_INTR_MASK BIT(31)
152 #define MVNETA_INTR_OLD_CAUSE 0x25a8
153 #define MVNETA_INTR_OLD_MASK 0x25ac
155 /* Data Path Port/Queue Cause Register */
156 #define MVNETA_INTR_MISC_CAUSE 0x25b0
157 #define MVNETA_INTR_MISC_MASK 0x25b4
159 #define MVNETA_CAUSE_PHY_STATUS_CHANGE BIT(0)
160 #define MVNETA_CAUSE_LINK_CHANGE BIT(1)
161 #define MVNETA_CAUSE_PTP BIT(4)
163 #define MVNETA_CAUSE_INTERNAL_ADDR_ERR BIT(7)
164 #define MVNETA_CAUSE_RX_OVERRUN BIT(8)
165 #define MVNETA_CAUSE_RX_CRC_ERROR BIT(9)
166 #define MVNETA_CAUSE_RX_LARGE_PKT BIT(10)
167 #define MVNETA_CAUSE_TX_UNDERUN BIT(11)
168 #define MVNETA_CAUSE_PRBS_ERR BIT(12)
169 #define MVNETA_CAUSE_PSC_SYNC_CHANGE BIT(13)
170 #define MVNETA_CAUSE_SERDES_SYNC_ERR BIT(14)
172 #define MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT 16
173 #define MVNETA_CAUSE_BMU_ALLOC_ERR_ALL_MASK (0xF << MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT)
174 #define MVNETA_CAUSE_BMU_ALLOC_ERR_MASK(pool) (1 << (MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT + (pool)))
176 #define MVNETA_CAUSE_TXQ_ERROR_SHIFT 24
177 #define MVNETA_CAUSE_TXQ_ERROR_ALL_MASK (0xFF << MVNETA_CAUSE_TXQ_ERROR_SHIFT)
178 #define MVNETA_CAUSE_TXQ_ERROR_MASK(q) (1 << (MVNETA_CAUSE_TXQ_ERROR_SHIFT + (q)))
180 #define MVNETA_INTR_ENABLE 0x25b8
181 #define MVNETA_TXQ_INTR_ENABLE_ALL_MASK 0x0000ff00
182 #define MVNETA_RXQ_INTR_ENABLE_ALL_MASK 0x000000ff
184 #define MVNETA_RXQ_CMD 0x2680
185 #define MVNETA_RXQ_DISABLE_SHIFT 8
186 #define MVNETA_RXQ_ENABLE_MASK 0x000000ff
187 #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4))
188 #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4))
189 #define MVNETA_GMAC_CTRL_0 0x2c00
190 #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2
191 #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc
192 #define MVNETA_GMAC0_PORT_1000BASE_X BIT(1)
193 #define MVNETA_GMAC0_PORT_ENABLE BIT(0)
194 #define MVNETA_GMAC_CTRL_2 0x2c08
195 #define MVNETA_GMAC2_INBAND_AN_ENABLE BIT(0)
196 #define MVNETA_GMAC2_PCS_ENABLE BIT(3)
197 #define MVNETA_GMAC2_PORT_RGMII BIT(4)
198 #define MVNETA_GMAC2_PORT_RESET BIT(6)
199 #define MVNETA_GMAC_STATUS 0x2c10
200 #define MVNETA_GMAC_LINK_UP BIT(0)
201 #define MVNETA_GMAC_SPEED_1000 BIT(1)
202 #define MVNETA_GMAC_SPEED_100 BIT(2)
203 #define MVNETA_GMAC_FULL_DUPLEX BIT(3)
204 #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4)
205 #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5)
206 #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6)
207 #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7)
208 #define MVNETA_GMAC_AN_COMPLETE BIT(11)
209 #define MVNETA_GMAC_SYNC_OK BIT(14)
210 #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c
211 #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0)
212 #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1)
213 #define MVNETA_GMAC_INBAND_AN_ENABLE BIT(2)
214 #define MVNETA_GMAC_AN_BYPASS_ENABLE BIT(3)
215 #define MVNETA_GMAC_INBAND_RESTART_AN BIT(4)
216 #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5)
217 #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6)
218 #define MVNETA_GMAC_AN_SPEED_EN BIT(7)
219 #define MVNETA_GMAC_CONFIG_FLOW_CTRL BIT(8)
220 #define MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL BIT(9)
221 #define MVNETA_GMAC_AN_FLOW_CTRL_EN BIT(11)
222 #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12)
223 #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13)
224 #define MVNETA_MIB_COUNTERS_BASE 0x3000
225 #define MVNETA_MIB_LATE_COLLISION 0x7c
226 #define MVNETA_DA_FILT_SPEC_MCAST 0x3400
227 #define MVNETA_DA_FILT_OTH_MCAST 0x3500
228 #define MVNETA_DA_FILT_UCAST_BASE 0x3600
229 #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2))
230 #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2))
231 #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000
232 #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16)
233 #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2))
234 #define MVNETA_TXQ_DEC_SENT_SHIFT 16
235 #define MVNETA_TXQ_DEC_SENT_MASK 0xff
236 #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2))
237 #define MVNETA_TXQ_SENT_DESC_SHIFT 16
238 #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000
239 #define MVNETA_PORT_TX_RESET 0x3cf0
240 #define MVNETA_PORT_TX_DMA_RESET BIT(0)
241 #define MVNETA_TX_MTU 0x3e0c
242 #define MVNETA_TX_TOKEN_SIZE 0x3e14
243 #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff
244 #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2))
245 #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff
247 #define MVNETA_LPI_CTRL_0 0x2cc0
248 #define MVNETA_LPI_CTRL_1 0x2cc4
249 #define MVNETA_LPI_REQUEST_ENABLE BIT(0)
250 #define MVNETA_LPI_CTRL_2 0x2cc8
251 #define MVNETA_LPI_STATUS 0x2ccc
253 #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
255 /* Descriptor ring Macros */
256 #define MVNETA_QUEUE_NEXT_DESC(q, index) \
257 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
259 /* Various constants */
262 #define MVNETA_TXDONE_COAL_PKTS 0 /* interrupt per packet */
263 #define MVNETA_RX_COAL_PKTS 32
264 #define MVNETA_RX_COAL_USEC 100
266 /* The two bytes Marvell header. Either contains a special value used
267 * by Marvell switches when a specific hardware mode is enabled (not
268 * supported by this driver) or is filled automatically by zeroes on
269 * the RX side. Those two bytes being at the front of the Ethernet
270 * header, they allow to have the IP header aligned on a 4 bytes
271 * boundary automatically: the hardware skips those two bytes on its
274 #define MVNETA_MH_SIZE 2
276 #define MVNETA_VLAN_TAG_LEN 4
278 #define MVNETA_TX_CSUM_DEF_SIZE 1600
279 #define MVNETA_TX_CSUM_MAX_SIZE 9800
280 #define MVNETA_ACC_MODE_EXT1 1
281 #define MVNETA_ACC_MODE_EXT2 2
283 #define MVNETA_MAX_DECODE_WIN 6
285 /* Timeout constants */
286 #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000
287 #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000
288 #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000
290 #define MVNETA_TX_MTU_MAX 0x3ffff
292 /* The RSS lookup table actually has 256 entries but we do not use
295 #define MVNETA_RSS_LU_TABLE_SIZE 1
297 /* Max number of Rx descriptors */
298 #define MVNETA_MAX_RXD 128
300 /* Max number of Tx descriptors */
301 #define MVNETA_MAX_TXD 532
303 /* Max number of allowed TCP segments for software TSO */
304 #define MVNETA_MAX_TSO_SEGS 100
306 #define MVNETA_MAX_SKB_DESCS (MVNETA_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
308 /* descriptor aligned size */
309 #define MVNETA_DESC_ALIGNED_SIZE 32
311 /* Number of bytes to be taken into account by HW when putting incoming data
312 * to the buffers. It is needed in case NET_SKB_PAD exceeds maximum packet
313 * offset supported in MVNETA_RXQ_CONFIG_REG(q) registers.
315 #define MVNETA_RX_PKT_OFFSET_CORRECTION 64
317 #define MVNETA_RX_PKT_SIZE(mtu) \
318 ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \
319 ETH_HLEN + ETH_FCS_LEN, \
322 #define IS_TSO_HEADER(txq, addr) \
323 ((addr >= txq->tso_hdrs_phys) && \
324 (addr < txq->tso_hdrs_phys + txq->size * TSO_HEADER_SIZE))
326 #define MVNETA_RX_GET_BM_POOL_ID(rxd) \
327 (((rxd)->status & MVNETA_RXD_BM_POOL_MASK) >> MVNETA_RXD_BM_POOL_SHIFT)
330 ETHTOOL_STAT_EEE_WAKEUP,
334 struct mvneta_statistic {
335 unsigned short offset;
337 const char name[ETH_GSTRING_LEN];
344 static const struct mvneta_statistic mvneta_statistics[] = {
345 { 0x3000, T_REG_64, "good_octets_received", },
346 { 0x3010, T_REG_32, "good_frames_received", },
347 { 0x3008, T_REG_32, "bad_octets_received", },
348 { 0x3014, T_REG_32, "bad_frames_received", },
349 { 0x3018, T_REG_32, "broadcast_frames_received", },
350 { 0x301c, T_REG_32, "multicast_frames_received", },
351 { 0x3050, T_REG_32, "unrec_mac_control_received", },
352 { 0x3058, T_REG_32, "good_fc_received", },
353 { 0x305c, T_REG_32, "bad_fc_received", },
354 { 0x3060, T_REG_32, "undersize_received", },
355 { 0x3064, T_REG_32, "fragments_received", },
356 { 0x3068, T_REG_32, "oversize_received", },
357 { 0x306c, T_REG_32, "jabber_received", },
358 { 0x3070, T_REG_32, "mac_receive_error", },
359 { 0x3074, T_REG_32, "bad_crc_event", },
360 { 0x3078, T_REG_32, "collision", },
361 { 0x307c, T_REG_32, "late_collision", },
362 { 0x2484, T_REG_32, "rx_discard", },
363 { 0x2488, T_REG_32, "rx_overrun", },
364 { 0x3020, T_REG_32, "frames_64_octets", },
365 { 0x3024, T_REG_32, "frames_65_to_127_octets", },
366 { 0x3028, T_REG_32, "frames_128_to_255_octets", },
367 { 0x302c, T_REG_32, "frames_256_to_511_octets", },
368 { 0x3030, T_REG_32, "frames_512_to_1023_octets", },
369 { 0x3034, T_REG_32, "frames_1024_to_max_octets", },
370 { 0x3038, T_REG_64, "good_octets_sent", },
371 { 0x3040, T_REG_32, "good_frames_sent", },
372 { 0x3044, T_REG_32, "excessive_collision", },
373 { 0x3048, T_REG_32, "multicast_frames_sent", },
374 { 0x304c, T_REG_32, "broadcast_frames_sent", },
375 { 0x3054, T_REG_32, "fc_sent", },
376 { 0x300c, T_REG_32, "internal_mac_transmit_err", },
377 { ETHTOOL_STAT_EEE_WAKEUP, T_SW, "eee_wakeup_errors", },
380 struct mvneta_pcpu_stats {
381 struct u64_stats_sync syncp;
388 struct mvneta_pcpu_port {
389 /* Pointer to the shared port */
390 struct mvneta_port *pp;
392 /* Pointer to the CPU-local NAPI struct */
393 struct napi_struct napi;
395 /* Cause of the previous interrupt */
401 struct mvneta_pcpu_port __percpu *ports;
402 struct mvneta_pcpu_stats __percpu *stats;
405 unsigned int frag_size;
407 struct mvneta_rx_queue *rxqs;
408 struct mvneta_tx_queue *txqs;
409 struct net_device *dev;
410 struct hlist_node node_online;
411 struct hlist_node node_dead;
413 /* Protect the access to the percpu interrupt registers,
414 * ensuring that the configuration remains coherent.
420 struct napi_struct napi;
430 phy_interface_t phy_interface;
431 struct device_node *dn;
432 unsigned int tx_csum_limit;
433 struct phylink *phylink;
435 struct mvneta_bm *bm_priv;
436 struct mvneta_bm_pool *pool_long;
437 struct mvneta_bm_pool *pool_short;
444 u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)];
446 u32 indir[MVNETA_RSS_LU_TABLE_SIZE];
448 /* Flags for special SoC configurations */
449 bool neta_armada3700;
450 u16 rx_offset_correction;
451 const struct mbus_dram_target_info *dram_target_info;
454 /* The mvneta_tx_desc and mvneta_rx_desc structures describe the
455 * layout of the transmit and reception DMA descriptors, and their
456 * layout is therefore defined by the hardware design
459 #define MVNETA_TX_L3_OFF_SHIFT 0
460 #define MVNETA_TX_IP_HLEN_SHIFT 8
461 #define MVNETA_TX_L4_UDP BIT(16)
462 #define MVNETA_TX_L3_IP6 BIT(17)
463 #define MVNETA_TXD_IP_CSUM BIT(18)
464 #define MVNETA_TXD_Z_PAD BIT(19)
465 #define MVNETA_TXD_L_DESC BIT(20)
466 #define MVNETA_TXD_F_DESC BIT(21)
467 #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \
468 MVNETA_TXD_L_DESC | \
470 #define MVNETA_TX_L4_CSUM_FULL BIT(30)
471 #define MVNETA_TX_L4_CSUM_NOT BIT(31)
473 #define MVNETA_RXD_ERR_CRC 0x0
474 #define MVNETA_RXD_BM_POOL_SHIFT 13
475 #define MVNETA_RXD_BM_POOL_MASK (BIT(13) | BIT(14))
476 #define MVNETA_RXD_ERR_SUMMARY BIT(16)
477 #define MVNETA_RXD_ERR_OVERRUN BIT(17)
478 #define MVNETA_RXD_ERR_LEN BIT(18)
479 #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18))
480 #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18))
481 #define MVNETA_RXD_L3_IP4 BIT(25)
482 #define MVNETA_RXD_FIRST_LAST_DESC (BIT(26) | BIT(27))
483 #define MVNETA_RXD_L4_CSUM_OK BIT(30)
485 #if defined(__LITTLE_ENDIAN)
486 struct mvneta_tx_desc {
487 u32 command; /* Options used by HW for packet transmitting.*/
488 u16 reserverd1; /* csum_l4 (for future use) */
489 u16 data_size; /* Data size of transmitted packet in bytes */
490 u32 buf_phys_addr; /* Physical addr of transmitted buffer */
491 u32 reserved2; /* hw_cmd - (for future use, PMT) */
492 u32 reserved3[4]; /* Reserved - (for future use) */
495 struct mvneta_rx_desc {
496 u32 status; /* Info about received packet */
497 u16 reserved1; /* pnc_info - (for future use, PnC) */
498 u16 data_size; /* Size of received packet in bytes */
500 u32 buf_phys_addr; /* Physical address of the buffer */
501 u32 reserved2; /* pnc_flow_id (for future use, PnC) */
503 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
504 u16 reserved3; /* prefetch_cmd, for future use */
505 u16 reserved4; /* csum_l4 - (for future use, PnC) */
507 u32 reserved5; /* pnc_extra PnC (for future use, PnC) */
508 u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */
511 struct mvneta_tx_desc {
512 u16 data_size; /* Data size of transmitted packet in bytes */
513 u16 reserverd1; /* csum_l4 (for future use) */
514 u32 command; /* Options used by HW for packet transmitting.*/
515 u32 reserved2; /* hw_cmd - (for future use, PMT) */
516 u32 buf_phys_addr; /* Physical addr of transmitted buffer */
517 u32 reserved3[4]; /* Reserved - (for future use) */
520 struct mvneta_rx_desc {
521 u16 data_size; /* Size of received packet in bytes */
522 u16 reserved1; /* pnc_info - (for future use, PnC) */
523 u32 status; /* Info about received packet */
525 u32 reserved2; /* pnc_flow_id (for future use, PnC) */
526 u32 buf_phys_addr; /* Physical address of the buffer */
528 u16 reserved4; /* csum_l4 - (for future use, PnC) */
529 u16 reserved3; /* prefetch_cmd, for future use */
530 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
532 u32 reserved5; /* pnc_extra PnC (for future use, PnC) */
533 u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */
537 struct mvneta_tx_queue {
538 /* Number of this TX queue, in the range 0-7 */
541 /* Number of TX DMA descriptors in the descriptor ring */
544 /* Number of currently used TX DMA descriptor in the
549 int tx_stop_threshold;
550 int tx_wake_threshold;
552 /* Array of transmitted skb */
553 struct sk_buff **tx_skb;
555 /* Index of last TX DMA descriptor that was inserted */
558 /* Index of the TX DMA descriptor to be cleaned up */
563 /* Virtual address of the TX DMA descriptors array */
564 struct mvneta_tx_desc *descs;
566 /* DMA address of the TX DMA descriptors array */
567 dma_addr_t descs_phys;
569 /* Index of the last TX DMA descriptor */
572 /* Index of the next TX DMA descriptor to process */
573 int next_desc_to_proc;
575 /* DMA buffers for TSO headers */
578 /* DMA address of TSO headers */
579 dma_addr_t tso_hdrs_phys;
581 /* Affinity mask for CPUs*/
582 cpumask_t affinity_mask;
585 struct mvneta_rx_queue {
586 /* rx queue number, in the range 0-7 */
589 /* num of rx descriptors in the rx descriptor ring */
592 /* counter of times when mvneta_refill() failed */
598 /* Virtual address of the RX buffer */
599 void **buf_virt_addr;
601 /* Virtual address of the RX DMA descriptors array */
602 struct mvneta_rx_desc *descs;
604 /* DMA address of the RX DMA descriptors array */
605 dma_addr_t descs_phys;
607 /* Index of the last RX DMA descriptor */
610 /* Index of the next RX DMA descriptor to process */
611 int next_desc_to_proc;
614 static enum cpuhp_state online_hpstate;
615 /* The hardware supports eight (8) rx queues, but we are only allowing
616 * the first one to be used. Therefore, let's just allocate one queue.
618 static int rxq_number = 8;
619 static int txq_number = 8;
623 static int rx_copybreak __read_mostly = 256;
625 /* HW BM need that each port be identify by a unique ID */
626 static int global_port_id;
628 #define MVNETA_DRIVER_NAME "mvneta"
629 #define MVNETA_DRIVER_VERSION "1.0"
631 /* Utility/helper methods */
633 /* Write helper method */
634 static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data)
636 writel(data, pp->base + offset);
639 /* Read helper method */
640 static u32 mvreg_read(struct mvneta_port *pp, u32 offset)
642 return readl(pp->base + offset);
645 /* Increment txq get counter */
646 static void mvneta_txq_inc_get(struct mvneta_tx_queue *txq)
648 txq->txq_get_index++;
649 if (txq->txq_get_index == txq->size)
650 txq->txq_get_index = 0;
653 /* Increment txq put counter */
654 static void mvneta_txq_inc_put(struct mvneta_tx_queue *txq)
656 txq->txq_put_index++;
657 if (txq->txq_put_index == txq->size)
658 txq->txq_put_index = 0;
662 /* Clear all MIB counters */
663 static void mvneta_mib_counters_clear(struct mvneta_port *pp)
668 /* Perform dummy reads from MIB counters */
669 for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4)
670 dummy = mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i));
671 dummy = mvreg_read(pp, MVNETA_RX_DISCARD_FRAME_COUNT);
672 dummy = mvreg_read(pp, MVNETA_OVERRUN_FRAME_COUNT);
675 /* Get System Network Statistics */
677 mvneta_get_stats64(struct net_device *dev,
678 struct rtnl_link_stats64 *stats)
680 struct mvneta_port *pp = netdev_priv(dev);
684 for_each_possible_cpu(cpu) {
685 struct mvneta_pcpu_stats *cpu_stats;
691 cpu_stats = per_cpu_ptr(pp->stats, cpu);
693 start = u64_stats_fetch_begin_irq(&cpu_stats->syncp);
694 rx_packets = cpu_stats->rx_packets;
695 rx_bytes = cpu_stats->rx_bytes;
696 tx_packets = cpu_stats->tx_packets;
697 tx_bytes = cpu_stats->tx_bytes;
698 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start));
700 stats->rx_packets += rx_packets;
701 stats->rx_bytes += rx_bytes;
702 stats->tx_packets += tx_packets;
703 stats->tx_bytes += tx_bytes;
706 stats->rx_errors = dev->stats.rx_errors;
707 stats->rx_dropped = dev->stats.rx_dropped;
709 stats->tx_dropped = dev->stats.tx_dropped;
712 /* Rx descriptors helper methods */
714 /* Checks whether the RX descriptor having this status is both the first
715 * and the last descriptor for the RX packet. Each RX packet is currently
716 * received through a single RX descriptor, so not having each RX
717 * descriptor with its first and last bits set is an error
719 static int mvneta_rxq_desc_is_first_last(u32 status)
721 return (status & MVNETA_RXD_FIRST_LAST_DESC) ==
722 MVNETA_RXD_FIRST_LAST_DESC;
725 /* Add number of descriptors ready to receive new packets */
726 static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp,
727 struct mvneta_rx_queue *rxq,
730 /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can
733 while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) {
734 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
735 (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX <<
736 MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
737 ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX;
740 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
741 (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
744 /* Get number of RX descriptors occupied by received packets */
745 static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp,
746 struct mvneta_rx_queue *rxq)
750 val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id));
751 return val & MVNETA_RXQ_OCCUPIED_ALL_MASK;
754 /* Update num of rx desc called upon return from rx path or
755 * from mvneta_rxq_drop_pkts().
757 static void mvneta_rxq_desc_num_update(struct mvneta_port *pp,
758 struct mvneta_rx_queue *rxq,
759 int rx_done, int rx_filled)
763 if ((rx_done <= 0xff) && (rx_filled <= 0xff)) {
765 (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT);
766 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
770 /* Only 255 descriptors can be added at once */
771 while ((rx_done > 0) || (rx_filled > 0)) {
772 if (rx_done <= 0xff) {
779 if (rx_filled <= 0xff) {
780 val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
783 val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
786 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
790 /* Get pointer to next RX descriptor to be processed by SW */
791 static struct mvneta_rx_desc *
792 mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq)
794 int rx_desc = rxq->next_desc_to_proc;
796 rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc);
797 prefetch(rxq->descs + rxq->next_desc_to_proc);
798 return rxq->descs + rx_desc;
801 /* Change maximum receive size of the port. */
802 static void mvneta_max_rx_size_set(struct mvneta_port *pp, int max_rx_size)
806 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
807 val &= ~MVNETA_GMAC_MAX_RX_SIZE_MASK;
808 val |= ((max_rx_size - MVNETA_MH_SIZE) / 2) <<
809 MVNETA_GMAC_MAX_RX_SIZE_SHIFT;
810 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
814 /* Set rx queue offset */
815 static void mvneta_rxq_offset_set(struct mvneta_port *pp,
816 struct mvneta_rx_queue *rxq,
821 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
822 val &= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK;
825 val |= MVNETA_RXQ_PKT_OFFSET_MASK(offset >> 3);
826 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
830 /* Tx descriptors helper methods */
832 /* Update HW with number of TX descriptors to be sent */
833 static void mvneta_txq_pend_desc_add(struct mvneta_port *pp,
834 struct mvneta_tx_queue *txq,
839 pend_desc += txq->pending;
841 /* Only 255 Tx descriptors can be added at once */
843 val = min(pend_desc, 255);
844 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
846 } while (pend_desc > 0);
850 /* Get pointer to next TX descriptor to be processed (send) by HW */
851 static struct mvneta_tx_desc *
852 mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq)
854 int tx_desc = txq->next_desc_to_proc;
856 txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc);
857 return txq->descs + tx_desc;
860 /* Release the last allocated TX descriptor. Useful to handle DMA
861 * mapping failures in the TX path.
863 static void mvneta_txq_desc_put(struct mvneta_tx_queue *txq)
865 if (txq->next_desc_to_proc == 0)
866 txq->next_desc_to_proc = txq->last_desc - 1;
868 txq->next_desc_to_proc--;
871 /* Set rxq buf size */
872 static void mvneta_rxq_buf_size_set(struct mvneta_port *pp,
873 struct mvneta_rx_queue *rxq,
878 val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id));
880 val &= ~MVNETA_RXQ_BUF_SIZE_MASK;
881 val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT);
883 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val);
886 /* Disable buffer management (BM) */
887 static void mvneta_rxq_bm_disable(struct mvneta_port *pp,
888 struct mvneta_rx_queue *rxq)
892 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
893 val &= ~MVNETA_RXQ_HW_BUF_ALLOC;
894 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
897 /* Enable buffer management (BM) */
898 static void mvneta_rxq_bm_enable(struct mvneta_port *pp,
899 struct mvneta_rx_queue *rxq)
903 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
904 val |= MVNETA_RXQ_HW_BUF_ALLOC;
905 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
908 /* Notify HW about port's assignment of pool for bigger packets */
909 static void mvneta_rxq_long_pool_set(struct mvneta_port *pp,
910 struct mvneta_rx_queue *rxq)
914 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
915 val &= ~MVNETA_RXQ_LONG_POOL_ID_MASK;
916 val |= (pp->pool_long->id << MVNETA_RXQ_LONG_POOL_ID_SHIFT);
918 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
921 /* Notify HW about port's assignment of pool for smaller packets */
922 static void mvneta_rxq_short_pool_set(struct mvneta_port *pp,
923 struct mvneta_rx_queue *rxq)
927 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
928 val &= ~MVNETA_RXQ_SHORT_POOL_ID_MASK;
929 val |= (pp->pool_short->id << MVNETA_RXQ_SHORT_POOL_ID_SHIFT);
931 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
934 /* Set port's receive buffer size for assigned BM pool */
935 static inline void mvneta_bm_pool_bufsize_set(struct mvneta_port *pp,
941 if (!IS_ALIGNED(buf_size, 8)) {
942 dev_warn(pp->dev->dev.parent,
943 "illegal buf_size value %d, round to %d\n",
944 buf_size, ALIGN(buf_size, 8));
945 buf_size = ALIGN(buf_size, 8);
948 val = mvreg_read(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id));
949 val |= buf_size & MVNETA_PORT_POOL_BUFFER_SZ_MASK;
950 mvreg_write(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id), val);
953 /* Configure MBUS window in order to enable access BM internal SRAM */
954 static int mvneta_mbus_io_win_set(struct mvneta_port *pp, u32 base, u32 wsize,
957 u32 win_enable, win_protect;
960 win_enable = mvreg_read(pp, MVNETA_BASE_ADDR_ENABLE);
962 if (pp->bm_win_id < 0) {
963 /* Find first not occupied window */
964 for (i = 0; i < MVNETA_MAX_DECODE_WIN; i++) {
965 if (win_enable & (1 << i)) {
970 if (i == MVNETA_MAX_DECODE_WIN)
976 mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
977 mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
980 mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
982 mvreg_write(pp, MVNETA_WIN_BASE(i), (base & 0xffff0000) |
983 (attr << 8) | target);
985 mvreg_write(pp, MVNETA_WIN_SIZE(i), (wsize - 1) & 0xffff0000);
987 win_protect = mvreg_read(pp, MVNETA_ACCESS_PROTECT_ENABLE);
988 win_protect |= 3 << (2 * i);
989 mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect);
991 win_enable &= ~(1 << i);
992 mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
997 static int mvneta_bm_port_mbus_init(struct mvneta_port *pp)
1003 /* Get BM window information */
1004 err = mvebu_mbus_get_io_win_info(pp->bm_priv->bppi_phys_addr, &wsize,
1011 /* Open NETA -> BM window */
1012 err = mvneta_mbus_io_win_set(pp, pp->bm_priv->bppi_phys_addr, wsize,
1015 netdev_info(pp->dev, "fail to configure mbus window to BM\n");
1021 /* Assign and initialize pools for port. In case of fail
1022 * buffer manager will remain disabled for current port.
1024 static int mvneta_bm_port_init(struct platform_device *pdev,
1025 struct mvneta_port *pp)
1027 struct device_node *dn = pdev->dev.of_node;
1028 u32 long_pool_id, short_pool_id;
1030 if (!pp->neta_armada3700) {
1033 ret = mvneta_bm_port_mbus_init(pp);
1038 if (of_property_read_u32(dn, "bm,pool-long", &long_pool_id)) {
1039 netdev_info(pp->dev, "missing long pool id\n");
1043 /* Create port's long pool depending on mtu */
1044 pp->pool_long = mvneta_bm_pool_use(pp->bm_priv, long_pool_id,
1045 MVNETA_BM_LONG, pp->id,
1046 MVNETA_RX_PKT_SIZE(pp->dev->mtu));
1047 if (!pp->pool_long) {
1048 netdev_info(pp->dev, "fail to obtain long pool for port\n");
1052 pp->pool_long->port_map |= 1 << pp->id;
1054 mvneta_bm_pool_bufsize_set(pp, pp->pool_long->buf_size,
1057 /* If short pool id is not defined, assume using single pool */
1058 if (of_property_read_u32(dn, "bm,pool-short", &short_pool_id))
1059 short_pool_id = long_pool_id;
1061 /* Create port's short pool */
1062 pp->pool_short = mvneta_bm_pool_use(pp->bm_priv, short_pool_id,
1063 MVNETA_BM_SHORT, pp->id,
1064 MVNETA_BM_SHORT_PKT_SIZE);
1065 if (!pp->pool_short) {
1066 netdev_info(pp->dev, "fail to obtain short pool for port\n");
1067 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id);
1071 if (short_pool_id != long_pool_id) {
1072 pp->pool_short->port_map |= 1 << pp->id;
1073 mvneta_bm_pool_bufsize_set(pp, pp->pool_short->buf_size,
1074 pp->pool_short->id);
1080 /* Update settings of a pool for bigger packets */
1081 static void mvneta_bm_update_mtu(struct mvneta_port *pp, int mtu)
1083 struct mvneta_bm_pool *bm_pool = pp->pool_long;
1084 struct hwbm_pool *hwbm_pool = &bm_pool->hwbm_pool;
1087 /* Release all buffers from long pool */
1088 mvneta_bm_bufs_free(pp->bm_priv, bm_pool, 1 << pp->id);
1089 if (hwbm_pool->buf_num) {
1090 WARN(1, "cannot free all buffers in pool %d\n",
1095 bm_pool->pkt_size = MVNETA_RX_PKT_SIZE(mtu);
1096 bm_pool->buf_size = MVNETA_RX_BUF_SIZE(bm_pool->pkt_size);
1097 hwbm_pool->frag_size = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +
1098 SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(bm_pool->pkt_size));
1100 /* Fill entire long pool */
1101 num = hwbm_pool_add(hwbm_pool, hwbm_pool->size, GFP_ATOMIC);
1102 if (num != hwbm_pool->size) {
1103 WARN(1, "pool %d: %d of %d allocated\n",
1104 bm_pool->id, num, hwbm_pool->size);
1107 mvneta_bm_pool_bufsize_set(pp, bm_pool->buf_size, bm_pool->id);
1112 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id);
1113 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, 1 << pp->id);
1116 mvreg_write(pp, MVNETA_ACC_MODE, MVNETA_ACC_MODE_EXT1);
1117 netdev_info(pp->dev, "fail to update MTU, fall back to software BM\n");
1120 /* Start the Ethernet port RX and TX activity */
1121 static void mvneta_port_up(struct mvneta_port *pp)
1126 /* Enable all initialized TXs. */
1128 for (queue = 0; queue < txq_number; queue++) {
1129 struct mvneta_tx_queue *txq = &pp->txqs[queue];
1131 q_map |= (1 << queue);
1133 mvreg_write(pp, MVNETA_TXQ_CMD, q_map);
1135 /* Enable all initialized RXQs. */
1136 for (queue = 0; queue < rxq_number; queue++) {
1137 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
1140 q_map |= (1 << queue);
1142 mvreg_write(pp, MVNETA_RXQ_CMD, q_map);
1145 /* Stop the Ethernet port activity */
1146 static void mvneta_port_down(struct mvneta_port *pp)
1151 /* Stop Rx port activity. Check port Rx activity. */
1152 val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK;
1154 /* Issue stop command for active channels only */
1156 mvreg_write(pp, MVNETA_RXQ_CMD,
1157 val << MVNETA_RXQ_DISABLE_SHIFT);
1159 /* Wait for all Rx activity to terminate. */
1162 if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) {
1163 netdev_warn(pp->dev,
1164 "TIMEOUT for RX stopped ! rx_queue_cmd: 0x%08x\n",
1170 val = mvreg_read(pp, MVNETA_RXQ_CMD);
1171 } while (val & MVNETA_RXQ_ENABLE_MASK);
1173 /* Stop Tx port activity. Check port Tx activity. Issue stop
1174 * command for active channels only
1176 val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK;
1179 mvreg_write(pp, MVNETA_TXQ_CMD,
1180 (val << MVNETA_TXQ_DISABLE_SHIFT));
1182 /* Wait for all Tx activity to terminate. */
1185 if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) {
1186 netdev_warn(pp->dev,
1187 "TIMEOUT for TX stopped status=0x%08x\n",
1193 /* Check TX Command reg that all Txqs are stopped */
1194 val = mvreg_read(pp, MVNETA_TXQ_CMD);
1196 } while (val & MVNETA_TXQ_ENABLE_MASK);
1198 /* Double check to verify that TX FIFO is empty */
1201 if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) {
1202 netdev_warn(pp->dev,
1203 "TX FIFO empty timeout status=0x%08x\n",
1209 val = mvreg_read(pp, MVNETA_PORT_STATUS);
1210 } while (!(val & MVNETA_TX_FIFO_EMPTY) &&
1211 (val & MVNETA_TX_IN_PRGRS));
1216 /* Enable the port by setting the port enable bit of the MAC control register */
1217 static void mvneta_port_enable(struct mvneta_port *pp)
1222 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
1223 val |= MVNETA_GMAC0_PORT_ENABLE;
1224 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
1227 /* Disable the port and wait for about 200 usec before retuning */
1228 static void mvneta_port_disable(struct mvneta_port *pp)
1232 /* Reset the Enable bit in the Serial Control Register */
1233 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
1234 val &= ~MVNETA_GMAC0_PORT_ENABLE;
1235 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
1240 /* Multicast tables methods */
1242 /* Set all entries in Unicast MAC Table; queue==-1 means reject all */
1243 static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue)
1251 val = 0x1 | (queue << 1);
1252 val |= (val << 24) | (val << 16) | (val << 8);
1255 for (offset = 0; offset <= 0xc; offset += 4)
1256 mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val);
1259 /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */
1260 static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue)
1268 val = 0x1 | (queue << 1);
1269 val |= (val << 24) | (val << 16) | (val << 8);
1272 for (offset = 0; offset <= 0xfc; offset += 4)
1273 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val);
1277 /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */
1278 static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue)
1284 memset(pp->mcast_count, 0, sizeof(pp->mcast_count));
1287 memset(pp->mcast_count, 1, sizeof(pp->mcast_count));
1288 val = 0x1 | (queue << 1);
1289 val |= (val << 24) | (val << 16) | (val << 8);
1292 for (offset = 0; offset <= 0xfc; offset += 4)
1293 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val);
1296 static void mvneta_percpu_unmask_interrupt(void *arg)
1298 struct mvneta_port *pp = arg;
1300 /* All the queue are unmasked, but actually only the ones
1301 * mapped to this CPU will be unmasked
1303 mvreg_write(pp, MVNETA_INTR_NEW_MASK,
1304 MVNETA_RX_INTR_MASK_ALL |
1305 MVNETA_TX_INTR_MASK_ALL |
1306 MVNETA_MISCINTR_INTR_MASK);
1309 static void mvneta_percpu_mask_interrupt(void *arg)
1311 struct mvneta_port *pp = arg;
1313 /* All the queue are masked, but actually only the ones
1314 * mapped to this CPU will be masked
1316 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
1317 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
1318 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
1321 static void mvneta_percpu_clear_intr_cause(void *arg)
1323 struct mvneta_port *pp = arg;
1325 /* All the queue are cleared, but actually only the ones
1326 * mapped to this CPU will be cleared
1328 mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0);
1329 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
1330 mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
1333 /* This method sets defaults to the NETA port:
1334 * Clears interrupt Cause and Mask registers.
1335 * Clears all MAC tables.
1336 * Sets defaults to all registers.
1337 * Resets RX and TX descriptor rings.
1339 * This method can be called after mvneta_port_down() to return the port
1340 * settings to defaults.
1342 static void mvneta_defaults_set(struct mvneta_port *pp)
1347 int max_cpu = num_present_cpus();
1349 /* Clear all Cause registers */
1350 on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true);
1352 /* Mask all interrupts */
1353 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
1354 mvreg_write(pp, MVNETA_INTR_ENABLE, 0);
1356 /* Enable MBUS Retry bit16 */
1357 mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20);
1359 /* Set CPU queue access map. CPUs are assigned to the RX and
1360 * TX queues modulo their number. If there is only one TX
1361 * queue then it is assigned to the CPU associated to the
1364 for_each_present_cpu(cpu) {
1365 int rxq_map = 0, txq_map = 0;
1367 if (!pp->neta_armada3700) {
1368 for (rxq = 0; rxq < rxq_number; rxq++)
1369 if ((rxq % max_cpu) == cpu)
1370 rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq);
1372 for (txq = 0; txq < txq_number; txq++)
1373 if ((txq % max_cpu) == cpu)
1374 txq_map |= MVNETA_CPU_TXQ_ACCESS(txq);
1376 /* With only one TX queue we configure a special case
1377 * which will allow to get all the irq on a single
1380 if (txq_number == 1)
1381 txq_map = (cpu == pp->rxq_def) ?
1382 MVNETA_CPU_TXQ_ACCESS(1) : 0;
1385 txq_map = MVNETA_CPU_TXQ_ACCESS_ALL_MASK;
1386 rxq_map = MVNETA_CPU_RXQ_ACCESS_ALL_MASK;
1389 mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map);
1392 /* Reset RX and TX DMAs */
1393 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
1394 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
1396 /* Disable Legacy WRR, Disable EJP, Release from reset */
1397 mvreg_write(pp, MVNETA_TXQ_CMD_1, 0);
1398 for (queue = 0; queue < txq_number; queue++) {
1399 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0);
1400 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0);
1403 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
1404 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
1406 /* Set Port Acceleration Mode */
1408 /* HW buffer management + legacy parser */
1409 val = MVNETA_ACC_MODE_EXT2;
1411 /* SW buffer management + legacy parser */
1412 val = MVNETA_ACC_MODE_EXT1;
1413 mvreg_write(pp, MVNETA_ACC_MODE, val);
1416 mvreg_write(pp, MVNETA_BM_ADDRESS, pp->bm_priv->bppi_phys_addr);
1418 /* Update val of portCfg register accordingly with all RxQueue types */
1419 val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def);
1420 mvreg_write(pp, MVNETA_PORT_CONFIG, val);
1423 mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val);
1424 mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64);
1426 /* Build PORT_SDMA_CONFIG_REG */
1429 /* Default burst size */
1430 val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
1431 val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
1432 val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP;
1434 #if defined(__BIG_ENDIAN)
1435 val |= MVNETA_DESC_SWAP;
1438 /* Assign port SDMA configuration */
1439 mvreg_write(pp, MVNETA_SDMA_CONFIG, val);
1441 /* Disable PHY polling in hardware, since we're using the
1442 * kernel phylib to do this.
1444 val = mvreg_read(pp, MVNETA_UNIT_CONTROL);
1445 val &= ~MVNETA_PHY_POLLING_ENABLE;
1446 mvreg_write(pp, MVNETA_UNIT_CONTROL, val);
1448 mvneta_set_ucast_table(pp, -1);
1449 mvneta_set_special_mcast_table(pp, -1);
1450 mvneta_set_other_mcast_table(pp, -1);
1452 /* Set port interrupt enable register - default enable all */
1453 mvreg_write(pp, MVNETA_INTR_ENABLE,
1454 (MVNETA_RXQ_INTR_ENABLE_ALL_MASK
1455 | MVNETA_TXQ_INTR_ENABLE_ALL_MASK));
1457 mvneta_mib_counters_clear(pp);
1460 /* Set max sizes for tx queues */
1461 static void mvneta_txq_max_tx_size_set(struct mvneta_port *pp, int max_tx_size)
1467 mtu = max_tx_size * 8;
1468 if (mtu > MVNETA_TX_MTU_MAX)
1469 mtu = MVNETA_TX_MTU_MAX;
1472 val = mvreg_read(pp, MVNETA_TX_MTU);
1473 val &= ~MVNETA_TX_MTU_MAX;
1475 mvreg_write(pp, MVNETA_TX_MTU, val);
1477 /* TX token size and all TXQs token size must be larger that MTU */
1478 val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE);
1480 size = val & MVNETA_TX_TOKEN_SIZE_MAX;
1483 val &= ~MVNETA_TX_TOKEN_SIZE_MAX;
1485 mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val);
1487 for (queue = 0; queue < txq_number; queue++) {
1488 val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue));
1490 size = val & MVNETA_TXQ_TOKEN_SIZE_MAX;
1493 val &= ~MVNETA_TXQ_TOKEN_SIZE_MAX;
1495 mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val);
1500 /* Set unicast address */
1501 static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble,
1504 unsigned int unicast_reg;
1505 unsigned int tbl_offset;
1506 unsigned int reg_offset;
1508 /* Locate the Unicast table entry */
1509 last_nibble = (0xf & last_nibble);
1511 /* offset from unicast tbl base */
1512 tbl_offset = (last_nibble / 4) * 4;
1514 /* offset within the above reg */
1515 reg_offset = last_nibble % 4;
1517 unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset));
1520 /* Clear accepts frame bit at specified unicast DA tbl entry */
1521 unicast_reg &= ~(0xff << (8 * reg_offset));
1523 unicast_reg &= ~(0xff << (8 * reg_offset));
1524 unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
1527 mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg);
1530 /* Set mac address */
1531 static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr,
1538 mac_l = (addr[4] << 8) | (addr[5]);
1539 mac_h = (addr[0] << 24) | (addr[1] << 16) |
1540 (addr[2] << 8) | (addr[3] << 0);
1542 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l);
1543 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h);
1546 /* Accept frames of this address */
1547 mvneta_set_ucast_addr(pp, addr[5], queue);
1550 /* Set the number of packets that will be received before RX interrupt
1551 * will be generated by HW.
1553 static void mvneta_rx_pkts_coal_set(struct mvneta_port *pp,
1554 struct mvneta_rx_queue *rxq, u32 value)
1556 mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id),
1557 value | MVNETA_RXQ_NON_OCCUPIED(0));
1560 /* Set the time delay in usec before RX interrupt will be generated by
1563 static void mvneta_rx_time_coal_set(struct mvneta_port *pp,
1564 struct mvneta_rx_queue *rxq, u32 value)
1567 unsigned long clk_rate;
1569 clk_rate = clk_get_rate(pp->clk);
1570 val = (clk_rate / 1000000) * value;
1572 mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val);
1575 /* Set threshold for TX_DONE pkts coalescing */
1576 static void mvneta_tx_done_pkts_coal_set(struct mvneta_port *pp,
1577 struct mvneta_tx_queue *txq, u32 value)
1581 val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id));
1583 val &= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK;
1584 val |= MVNETA_TXQ_SENT_THRESH_MASK(value);
1586 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val);
1589 /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
1590 static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc,
1591 u32 phys_addr, void *virt_addr,
1592 struct mvneta_rx_queue *rxq)
1596 rx_desc->buf_phys_addr = phys_addr;
1597 i = rx_desc - rxq->descs;
1598 rxq->buf_virt_addr[i] = virt_addr;
1601 /* Decrement sent descriptors counter */
1602 static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp,
1603 struct mvneta_tx_queue *txq,
1608 /* Only 255 TX descriptors can be updated at once */
1609 while (sent_desc > 0xff) {
1610 val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT;
1611 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
1612 sent_desc = sent_desc - 0xff;
1615 val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT;
1616 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
1619 /* Get number of TX descriptors already sent by HW */
1620 static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp,
1621 struct mvneta_tx_queue *txq)
1626 val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id));
1627 sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >>
1628 MVNETA_TXQ_SENT_DESC_SHIFT;
1633 /* Get number of sent descriptors and decrement counter.
1634 * The number of sent descriptors is returned.
1636 static int mvneta_txq_sent_desc_proc(struct mvneta_port *pp,
1637 struct mvneta_tx_queue *txq)
1641 /* Get number of sent descriptors */
1642 sent_desc = mvneta_txq_sent_desc_num_get(pp, txq);
1644 /* Decrement sent descriptors counter */
1646 mvneta_txq_sent_desc_dec(pp, txq, sent_desc);
1651 /* Set TXQ descriptors fields relevant for CSUM calculation */
1652 static u32 mvneta_txq_desc_csum(int l3_offs, int l3_proto,
1653 int ip_hdr_len, int l4_proto)
1657 /* Fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk,
1658 * G_L4_chk, L4_type; required only for checksum
1661 command = l3_offs << MVNETA_TX_L3_OFF_SHIFT;
1662 command |= ip_hdr_len << MVNETA_TX_IP_HLEN_SHIFT;
1664 if (l3_proto == htons(ETH_P_IP))
1665 command |= MVNETA_TXD_IP_CSUM;
1667 command |= MVNETA_TX_L3_IP6;
1669 if (l4_proto == IPPROTO_TCP)
1670 command |= MVNETA_TX_L4_CSUM_FULL;
1671 else if (l4_proto == IPPROTO_UDP)
1672 command |= MVNETA_TX_L4_UDP | MVNETA_TX_L4_CSUM_FULL;
1674 command |= MVNETA_TX_L4_CSUM_NOT;
1680 /* Display more error info */
1681 static void mvneta_rx_error(struct mvneta_port *pp,
1682 struct mvneta_rx_desc *rx_desc)
1684 u32 status = rx_desc->status;
1686 if (!mvneta_rxq_desc_is_first_last(status)) {
1688 "bad rx status %08x (buffer oversize), size=%d\n",
1689 status, rx_desc->data_size);
1693 switch (status & MVNETA_RXD_ERR_CODE_MASK) {
1694 case MVNETA_RXD_ERR_CRC:
1695 netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n",
1696 status, rx_desc->data_size);
1698 case MVNETA_RXD_ERR_OVERRUN:
1699 netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n",
1700 status, rx_desc->data_size);
1702 case MVNETA_RXD_ERR_LEN:
1703 netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n",
1704 status, rx_desc->data_size);
1706 case MVNETA_RXD_ERR_RESOURCE:
1707 netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n",
1708 status, rx_desc->data_size);
1713 /* Handle RX checksum offload based on the descriptor's status */
1714 static void mvneta_rx_csum(struct mvneta_port *pp, u32 status,
1715 struct sk_buff *skb)
1717 if ((status & MVNETA_RXD_L3_IP4) &&
1718 (status & MVNETA_RXD_L4_CSUM_OK)) {
1720 skb->ip_summed = CHECKSUM_UNNECESSARY;
1724 skb->ip_summed = CHECKSUM_NONE;
1727 /* Return tx queue pointer (find last set bit) according to <cause> returned
1728 * form tx_done reg. <cause> must not be null. The return value is always a
1729 * valid queue for matching the first one found in <cause>.
1731 static struct mvneta_tx_queue *mvneta_tx_done_policy(struct mvneta_port *pp,
1734 int queue = fls(cause) - 1;
1736 return &pp->txqs[queue];
1739 /* Free tx queue skbuffs */
1740 static void mvneta_txq_bufs_free(struct mvneta_port *pp,
1741 struct mvneta_tx_queue *txq, int num,
1742 struct netdev_queue *nq)
1744 unsigned int bytes_compl = 0, pkts_compl = 0;
1747 for (i = 0; i < num; i++) {
1748 struct mvneta_tx_desc *tx_desc = txq->descs +
1750 struct sk_buff *skb = txq->tx_skb[txq->txq_get_index];
1753 bytes_compl += skb->len;
1757 mvneta_txq_inc_get(txq);
1759 if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr))
1760 dma_unmap_single(pp->dev->dev.parent,
1761 tx_desc->buf_phys_addr,
1762 tx_desc->data_size, DMA_TO_DEVICE);
1765 dev_kfree_skb_any(skb);
1768 netdev_tx_completed_queue(nq, pkts_compl, bytes_compl);
1771 /* Handle end of transmission */
1772 static void mvneta_txq_done(struct mvneta_port *pp,
1773 struct mvneta_tx_queue *txq)
1775 struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id);
1778 tx_done = mvneta_txq_sent_desc_proc(pp, txq);
1782 mvneta_txq_bufs_free(pp, txq, tx_done, nq);
1784 txq->count -= tx_done;
1786 if (netif_tx_queue_stopped(nq)) {
1787 if (txq->count <= txq->tx_wake_threshold)
1788 netif_tx_wake_queue(nq);
1792 void *mvneta_frag_alloc(unsigned int frag_size)
1794 if (likely(frag_size <= PAGE_SIZE))
1795 return netdev_alloc_frag(frag_size);
1797 return kmalloc(frag_size, GFP_ATOMIC);
1799 EXPORT_SYMBOL_GPL(mvneta_frag_alloc);
1801 void mvneta_frag_free(unsigned int frag_size, void *data)
1803 if (likely(frag_size <= PAGE_SIZE))
1804 skb_free_frag(data);
1808 EXPORT_SYMBOL_GPL(mvneta_frag_free);
1810 /* Refill processing for SW buffer management */
1811 static int mvneta_rx_refill(struct mvneta_port *pp,
1812 struct mvneta_rx_desc *rx_desc,
1813 struct mvneta_rx_queue *rxq)
1816 dma_addr_t phys_addr;
1819 data = mvneta_frag_alloc(pp->frag_size);
1823 phys_addr = dma_map_single(pp->dev->dev.parent, data,
1824 MVNETA_RX_BUF_SIZE(pp->pkt_size),
1826 if (unlikely(dma_mapping_error(pp->dev->dev.parent, phys_addr))) {
1827 mvneta_frag_free(pp->frag_size, data);
1831 phys_addr += pp->rx_offset_correction;
1832 mvneta_rx_desc_fill(rx_desc, phys_addr, data, rxq);
1836 /* Handle tx checksum */
1837 static u32 mvneta_skb_tx_csum(struct mvneta_port *pp, struct sk_buff *skb)
1839 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1841 __be16 l3_proto = vlan_get_protocol(skb);
1844 if (l3_proto == htons(ETH_P_IP)) {
1845 struct iphdr *ip4h = ip_hdr(skb);
1847 /* Calculate IPv4 checksum and L4 checksum */
1848 ip_hdr_len = ip4h->ihl;
1849 l4_proto = ip4h->protocol;
1850 } else if (l3_proto == htons(ETH_P_IPV6)) {
1851 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1853 /* Read l4_protocol from one of IPv6 extra headers */
1854 if (skb_network_header_len(skb) > 0)
1855 ip_hdr_len = (skb_network_header_len(skb) >> 2);
1856 l4_proto = ip6h->nexthdr;
1858 return MVNETA_TX_L4_CSUM_NOT;
1860 return mvneta_txq_desc_csum(skb_network_offset(skb),
1861 l3_proto, ip_hdr_len, l4_proto);
1864 return MVNETA_TX_L4_CSUM_NOT;
1867 /* Drop packets received by the RXQ and free buffers */
1868 static void mvneta_rxq_drop_pkts(struct mvneta_port *pp,
1869 struct mvneta_rx_queue *rxq)
1873 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
1875 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
1878 for (i = 0; i < rx_done; i++) {
1879 struct mvneta_rx_desc *rx_desc =
1880 mvneta_rxq_next_desc_get(rxq);
1881 u8 pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc);
1882 struct mvneta_bm_pool *bm_pool;
1884 bm_pool = &pp->bm_priv->bm_pools[pool_id];
1885 /* Return dropped buffer to the pool */
1886 mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool,
1887 rx_desc->buf_phys_addr);
1892 for (i = 0; i < rxq->size; i++) {
1893 struct mvneta_rx_desc *rx_desc = rxq->descs + i;
1894 void *data = rxq->buf_virt_addr[i];
1896 dma_unmap_single(pp->dev->dev.parent, rx_desc->buf_phys_addr,
1897 MVNETA_RX_BUF_SIZE(pp->pkt_size), DMA_FROM_DEVICE);
1898 mvneta_frag_free(pp->frag_size, data);
1902 /* Main rx processing when using software buffer management */
1903 static int mvneta_rx_swbm(struct mvneta_port *pp, int rx_todo,
1904 struct mvneta_rx_queue *rxq)
1906 struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports);
1907 struct net_device *dev = pp->dev;
1912 /* Get number of received packets */
1913 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
1915 if (rx_todo > rx_done)
1920 /* Fairness NAPI loop */
1921 while (rx_done < rx_todo) {
1922 struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq);
1923 struct sk_buff *skb;
1924 unsigned char *data;
1925 dma_addr_t phys_addr;
1926 u32 rx_status, frag_size;
1927 int rx_bytes, err, index;
1930 rx_status = rx_desc->status;
1931 rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE);
1932 index = rx_desc - rxq->descs;
1933 data = rxq->buf_virt_addr[index];
1934 phys_addr = rx_desc->buf_phys_addr;
1936 if (!mvneta_rxq_desc_is_first_last(rx_status) ||
1937 (rx_status & MVNETA_RXD_ERR_SUMMARY)) {
1938 mvneta_rx_error(pp, rx_desc);
1940 dev->stats.rx_errors++;
1941 /* leave the descriptor untouched */
1945 if (rx_bytes <= rx_copybreak) {
1946 /* better copy a small frame and not unmap the DMA region */
1947 skb = netdev_alloc_skb_ip_align(dev, rx_bytes);
1949 goto err_drop_frame;
1951 dma_sync_single_range_for_cpu(dev->dev.parent,
1953 MVNETA_MH_SIZE + NET_SKB_PAD,
1956 skb_put_data(skb, data + MVNETA_MH_SIZE + NET_SKB_PAD,
1959 skb->protocol = eth_type_trans(skb, dev);
1960 mvneta_rx_csum(pp, rx_status, skb);
1961 napi_gro_receive(&port->napi, skb);
1964 rcvd_bytes += rx_bytes;
1966 /* leave the descriptor and buffer untouched */
1970 /* Refill processing */
1971 err = mvneta_rx_refill(pp, rx_desc, rxq);
1973 netdev_err(dev, "Linux processing - Can't refill\n");
1975 goto err_drop_frame;
1978 frag_size = pp->frag_size;
1980 skb = build_skb(data, frag_size > PAGE_SIZE ? 0 : frag_size);
1982 /* After refill old buffer has to be unmapped regardless
1983 * the skb is successfully built or not.
1985 dma_unmap_single(dev->dev.parent, phys_addr,
1986 MVNETA_RX_BUF_SIZE(pp->pkt_size),
1990 goto err_drop_frame;
1993 rcvd_bytes += rx_bytes;
1995 /* Linux processing */
1996 skb_reserve(skb, MVNETA_MH_SIZE + NET_SKB_PAD);
1997 skb_put(skb, rx_bytes);
1999 skb->protocol = eth_type_trans(skb, dev);
2001 mvneta_rx_csum(pp, rx_status, skb);
2003 napi_gro_receive(&port->napi, skb);
2007 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
2009 u64_stats_update_begin(&stats->syncp);
2010 stats->rx_packets += rcvd_pkts;
2011 stats->rx_bytes += rcvd_bytes;
2012 u64_stats_update_end(&stats->syncp);
2015 /* Update rxq management counters */
2016 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
2021 /* Main rx processing when using hardware buffer management */
2022 static int mvneta_rx_hwbm(struct mvneta_port *pp, int rx_todo,
2023 struct mvneta_rx_queue *rxq)
2025 struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports);
2026 struct net_device *dev = pp->dev;
2031 /* Get number of received packets */
2032 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
2034 if (rx_todo > rx_done)
2039 /* Fairness NAPI loop */
2040 while (rx_done < rx_todo) {
2041 struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq);
2042 struct mvneta_bm_pool *bm_pool = NULL;
2043 struct sk_buff *skb;
2044 unsigned char *data;
2045 dma_addr_t phys_addr;
2046 u32 rx_status, frag_size;
2051 rx_status = rx_desc->status;
2052 rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE);
2053 data = (u8 *)(uintptr_t)rx_desc->buf_cookie;
2054 phys_addr = rx_desc->buf_phys_addr;
2055 pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc);
2056 bm_pool = &pp->bm_priv->bm_pools[pool_id];
2058 if (!mvneta_rxq_desc_is_first_last(rx_status) ||
2059 (rx_status & MVNETA_RXD_ERR_SUMMARY)) {
2060 err_drop_frame_ret_pool:
2061 /* Return the buffer to the pool */
2062 mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool,
2063 rx_desc->buf_phys_addr);
2065 dev->stats.rx_errors++;
2066 mvneta_rx_error(pp, rx_desc);
2067 /* leave the descriptor untouched */
2071 if (rx_bytes <= rx_copybreak) {
2072 /* better copy a small frame and not unmap the DMA region */
2073 skb = netdev_alloc_skb_ip_align(dev, rx_bytes);
2075 goto err_drop_frame_ret_pool;
2077 dma_sync_single_range_for_cpu(dev->dev.parent,
2078 rx_desc->buf_phys_addr,
2079 MVNETA_MH_SIZE + NET_SKB_PAD,
2082 skb_put_data(skb, data + MVNETA_MH_SIZE + NET_SKB_PAD,
2085 skb->protocol = eth_type_trans(skb, dev);
2086 mvneta_rx_csum(pp, rx_status, skb);
2087 napi_gro_receive(&port->napi, skb);
2090 rcvd_bytes += rx_bytes;
2092 /* Return the buffer to the pool */
2093 mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool,
2094 rx_desc->buf_phys_addr);
2096 /* leave the descriptor and buffer untouched */
2100 /* Refill processing */
2101 err = hwbm_pool_refill(&bm_pool->hwbm_pool, GFP_ATOMIC);
2103 netdev_err(dev, "Linux processing - Can't refill\n");
2105 goto err_drop_frame_ret_pool;
2108 frag_size = bm_pool->hwbm_pool.frag_size;
2110 skb = build_skb(data, frag_size > PAGE_SIZE ? 0 : frag_size);
2112 /* After refill old buffer has to be unmapped regardless
2113 * the skb is successfully built or not.
2115 dma_unmap_single(&pp->bm_priv->pdev->dev, phys_addr,
2116 bm_pool->buf_size, DMA_FROM_DEVICE);
2118 goto err_drop_frame;
2121 rcvd_bytes += rx_bytes;
2123 /* Linux processing */
2124 skb_reserve(skb, MVNETA_MH_SIZE + NET_SKB_PAD);
2125 skb_put(skb, rx_bytes);
2127 skb->protocol = eth_type_trans(skb, dev);
2129 mvneta_rx_csum(pp, rx_status, skb);
2131 napi_gro_receive(&port->napi, skb);
2135 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
2137 u64_stats_update_begin(&stats->syncp);
2138 stats->rx_packets += rcvd_pkts;
2139 stats->rx_bytes += rcvd_bytes;
2140 u64_stats_update_end(&stats->syncp);
2143 /* Update rxq management counters */
2144 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
2150 mvneta_tso_put_hdr(struct sk_buff *skb,
2151 struct mvneta_port *pp, struct mvneta_tx_queue *txq)
2153 struct mvneta_tx_desc *tx_desc;
2154 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2156 txq->tx_skb[txq->txq_put_index] = NULL;
2157 tx_desc = mvneta_txq_next_desc_get(txq);
2158 tx_desc->data_size = hdr_len;
2159 tx_desc->command = mvneta_skb_tx_csum(pp, skb);
2160 tx_desc->command |= MVNETA_TXD_F_DESC;
2161 tx_desc->buf_phys_addr = txq->tso_hdrs_phys +
2162 txq->txq_put_index * TSO_HEADER_SIZE;
2163 mvneta_txq_inc_put(txq);
2167 mvneta_tso_put_data(struct net_device *dev, struct mvneta_tx_queue *txq,
2168 struct sk_buff *skb, char *data, int size,
2169 bool last_tcp, bool is_last)
2171 struct mvneta_tx_desc *tx_desc;
2173 tx_desc = mvneta_txq_next_desc_get(txq);
2174 tx_desc->data_size = size;
2175 tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, data,
2176 size, DMA_TO_DEVICE);
2177 if (unlikely(dma_mapping_error(dev->dev.parent,
2178 tx_desc->buf_phys_addr))) {
2179 mvneta_txq_desc_put(txq);
2183 tx_desc->command = 0;
2184 txq->tx_skb[txq->txq_put_index] = NULL;
2187 /* last descriptor in the TCP packet */
2188 tx_desc->command = MVNETA_TXD_L_DESC;
2190 /* last descriptor in SKB */
2192 txq->tx_skb[txq->txq_put_index] = skb;
2194 mvneta_txq_inc_put(txq);
2198 static int mvneta_tx_tso(struct sk_buff *skb, struct net_device *dev,
2199 struct mvneta_tx_queue *txq)
2201 int total_len, data_left;
2203 struct mvneta_port *pp = netdev_priv(dev);
2205 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2208 /* Count needed descriptors */
2209 if ((txq->count + tso_count_descs(skb)) >= txq->size)
2212 if (skb_headlen(skb) < (skb_transport_offset(skb) + tcp_hdrlen(skb))) {
2213 pr_info("*** Is this even possible???!?!?\n");
2217 /* Initialize the TSO handler, and prepare the first payload */
2218 tso_start(skb, &tso);
2220 total_len = skb->len - hdr_len;
2221 while (total_len > 0) {
2224 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
2225 total_len -= data_left;
2228 /* prepare packet headers: MAC + IP + TCP */
2229 hdr = txq->tso_hdrs + txq->txq_put_index * TSO_HEADER_SIZE;
2230 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
2232 mvneta_tso_put_hdr(skb, pp, txq);
2234 while (data_left > 0) {
2238 size = min_t(int, tso.size, data_left);
2240 if (mvneta_tso_put_data(dev, txq, skb,
2247 tso_build_data(skb, &tso, size);
2254 /* Release all used data descriptors; header descriptors must not
2257 for (i = desc_count - 1; i >= 0; i--) {
2258 struct mvneta_tx_desc *tx_desc = txq->descs + i;
2259 if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr))
2260 dma_unmap_single(pp->dev->dev.parent,
2261 tx_desc->buf_phys_addr,
2264 mvneta_txq_desc_put(txq);
2269 /* Handle tx fragmentation processing */
2270 static int mvneta_tx_frag_process(struct mvneta_port *pp, struct sk_buff *skb,
2271 struct mvneta_tx_queue *txq)
2273 struct mvneta_tx_desc *tx_desc;
2274 int i, nr_frags = skb_shinfo(skb)->nr_frags;
2276 for (i = 0; i < nr_frags; i++) {
2277 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2278 void *addr = page_address(frag->page.p) + frag->page_offset;
2280 tx_desc = mvneta_txq_next_desc_get(txq);
2281 tx_desc->data_size = frag->size;
2283 tx_desc->buf_phys_addr =
2284 dma_map_single(pp->dev->dev.parent, addr,
2285 tx_desc->data_size, DMA_TO_DEVICE);
2287 if (dma_mapping_error(pp->dev->dev.parent,
2288 tx_desc->buf_phys_addr)) {
2289 mvneta_txq_desc_put(txq);
2293 if (i == nr_frags - 1) {
2294 /* Last descriptor */
2295 tx_desc->command = MVNETA_TXD_L_DESC | MVNETA_TXD_Z_PAD;
2296 txq->tx_skb[txq->txq_put_index] = skb;
2298 /* Descriptor in the middle: Not First, Not Last */
2299 tx_desc->command = 0;
2300 txq->tx_skb[txq->txq_put_index] = NULL;
2302 mvneta_txq_inc_put(txq);
2308 /* Release all descriptors that were used to map fragments of
2309 * this packet, as well as the corresponding DMA mappings
2311 for (i = i - 1; i >= 0; i--) {
2312 tx_desc = txq->descs + i;
2313 dma_unmap_single(pp->dev->dev.parent,
2314 tx_desc->buf_phys_addr,
2317 mvneta_txq_desc_put(txq);
2323 /* Main tx processing */
2324 static int mvneta_tx(struct sk_buff *skb, struct net_device *dev)
2326 struct mvneta_port *pp = netdev_priv(dev);
2327 u16 txq_id = skb_get_queue_mapping(skb);
2328 struct mvneta_tx_queue *txq = &pp->txqs[txq_id];
2329 struct mvneta_tx_desc *tx_desc;
2334 if (!netif_running(dev))
2337 if (skb_is_gso(skb)) {
2338 frags = mvneta_tx_tso(skb, dev, txq);
2342 frags = skb_shinfo(skb)->nr_frags + 1;
2344 /* Get a descriptor for the first part of the packet */
2345 tx_desc = mvneta_txq_next_desc_get(txq);
2347 tx_cmd = mvneta_skb_tx_csum(pp, skb);
2349 tx_desc->data_size = skb_headlen(skb);
2351 tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, skb->data,
2354 if (unlikely(dma_mapping_error(dev->dev.parent,
2355 tx_desc->buf_phys_addr))) {
2356 mvneta_txq_desc_put(txq);
2362 /* First and Last descriptor */
2363 tx_cmd |= MVNETA_TXD_FLZ_DESC;
2364 tx_desc->command = tx_cmd;
2365 txq->tx_skb[txq->txq_put_index] = skb;
2366 mvneta_txq_inc_put(txq);
2368 /* First but not Last */
2369 tx_cmd |= MVNETA_TXD_F_DESC;
2370 txq->tx_skb[txq->txq_put_index] = NULL;
2371 mvneta_txq_inc_put(txq);
2372 tx_desc->command = tx_cmd;
2373 /* Continue with other skb fragments */
2374 if (mvneta_tx_frag_process(pp, skb, txq)) {
2375 dma_unmap_single(dev->dev.parent,
2376 tx_desc->buf_phys_addr,
2379 mvneta_txq_desc_put(txq);
2387 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
2388 struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id);
2390 netdev_tx_sent_queue(nq, len);
2392 txq->count += frags;
2393 if (txq->count >= txq->tx_stop_threshold)
2394 netif_tx_stop_queue(nq);
2396 if (!skb->xmit_more || netif_xmit_stopped(nq) ||
2397 txq->pending + frags > MVNETA_TXQ_DEC_SENT_MASK)
2398 mvneta_txq_pend_desc_add(pp, txq, frags);
2400 txq->pending += frags;
2402 u64_stats_update_begin(&stats->syncp);
2403 stats->tx_packets++;
2404 stats->tx_bytes += len;
2405 u64_stats_update_end(&stats->syncp);
2407 dev->stats.tx_dropped++;
2408 dev_kfree_skb_any(skb);
2411 return NETDEV_TX_OK;
2415 /* Free tx resources, when resetting a port */
2416 static void mvneta_txq_done_force(struct mvneta_port *pp,
2417 struct mvneta_tx_queue *txq)
2420 struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id);
2421 int tx_done = txq->count;
2423 mvneta_txq_bufs_free(pp, txq, tx_done, nq);
2427 txq->txq_put_index = 0;
2428 txq->txq_get_index = 0;
2431 /* Handle tx done - called in softirq context. The <cause_tx_done> argument
2432 * must be a valid cause according to MVNETA_TXQ_INTR_MASK_ALL.
2434 static void mvneta_tx_done_gbe(struct mvneta_port *pp, u32 cause_tx_done)
2436 struct mvneta_tx_queue *txq;
2437 struct netdev_queue *nq;
2439 while (cause_tx_done) {
2440 txq = mvneta_tx_done_policy(pp, cause_tx_done);
2442 nq = netdev_get_tx_queue(pp->dev, txq->id);
2443 __netif_tx_lock(nq, smp_processor_id());
2446 mvneta_txq_done(pp, txq);
2448 __netif_tx_unlock(nq);
2449 cause_tx_done &= ~((1 << txq->id));
2453 /* Compute crc8 of the specified address, using a unique algorithm ,
2454 * according to hw spec, different than generic crc8 algorithm
2456 static int mvneta_addr_crc(unsigned char *addr)
2461 for (i = 0; i < ETH_ALEN; i++) {
2464 crc = (crc ^ addr[i]) << 8;
2465 for (j = 7; j >= 0; j--) {
2466 if (crc & (0x100 << j))
2474 /* This method controls the net device special MAC multicast support.
2475 * The Special Multicast Table for MAC addresses supports MAC of the form
2476 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
2477 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
2478 * Table entries in the DA-Filter table. This method set the Special
2479 * Multicast Table appropriate entry.
2481 static void mvneta_set_special_mcast_addr(struct mvneta_port *pp,
2482 unsigned char last_byte,
2485 unsigned int smc_table_reg;
2486 unsigned int tbl_offset;
2487 unsigned int reg_offset;
2489 /* Register offset from SMC table base */
2490 tbl_offset = (last_byte / 4);
2491 /* Entry offset within the above reg */
2492 reg_offset = last_byte % 4;
2494 smc_table_reg = mvreg_read(pp, (MVNETA_DA_FILT_SPEC_MCAST
2498 smc_table_reg &= ~(0xff << (8 * reg_offset));
2500 smc_table_reg &= ~(0xff << (8 * reg_offset));
2501 smc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
2504 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4,
2508 /* This method controls the network device Other MAC multicast support.
2509 * The Other Multicast Table is used for multicast of another type.
2510 * A CRC-8 is used as an index to the Other Multicast Table entries
2511 * in the DA-Filter table.
2512 * The method gets the CRC-8 value from the calling routine and
2513 * sets the Other Multicast Table appropriate entry according to the
2516 static void mvneta_set_other_mcast_addr(struct mvneta_port *pp,
2520 unsigned int omc_table_reg;
2521 unsigned int tbl_offset;
2522 unsigned int reg_offset;
2524 tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */
2525 reg_offset = crc8 % 4; /* Entry offset within the above reg */
2527 omc_table_reg = mvreg_read(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset);
2530 /* Clear accepts frame bit at specified Other DA table entry */
2531 omc_table_reg &= ~(0xff << (8 * reg_offset));
2533 omc_table_reg &= ~(0xff << (8 * reg_offset));
2534 omc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
2537 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg);
2540 /* The network device supports multicast using two tables:
2541 * 1) Special Multicast Table for MAC addresses of the form
2542 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
2543 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
2544 * Table entries in the DA-Filter table.
2545 * 2) Other Multicast Table for multicast of another type. A CRC-8 value
2546 * is used as an index to the Other Multicast Table entries in the
2549 static int mvneta_mcast_addr_set(struct mvneta_port *pp, unsigned char *p_addr,
2552 unsigned char crc_result = 0;
2554 if (memcmp(p_addr, "\x01\x00\x5e\x00\x00", 5) == 0) {
2555 mvneta_set_special_mcast_addr(pp, p_addr[5], queue);
2559 crc_result = mvneta_addr_crc(p_addr);
2561 if (pp->mcast_count[crc_result] == 0) {
2562 netdev_info(pp->dev, "No valid Mcast for crc8=0x%02x\n",
2567 pp->mcast_count[crc_result]--;
2568 if (pp->mcast_count[crc_result] != 0) {
2569 netdev_info(pp->dev,
2570 "After delete there are %d valid Mcast for crc8=0x%02x\n",
2571 pp->mcast_count[crc_result], crc_result);
2575 pp->mcast_count[crc_result]++;
2577 mvneta_set_other_mcast_addr(pp, crc_result, queue);
2582 /* Configure Fitering mode of Ethernet port */
2583 static void mvneta_rx_unicast_promisc_set(struct mvneta_port *pp,
2586 u32 port_cfg_reg, val;
2588 port_cfg_reg = mvreg_read(pp, MVNETA_PORT_CONFIG);
2590 val = mvreg_read(pp, MVNETA_TYPE_PRIO);
2592 /* Set / Clear UPM bit in port configuration register */
2594 /* Accept all Unicast addresses */
2595 port_cfg_reg |= MVNETA_UNI_PROMISC_MODE;
2596 val |= MVNETA_FORCE_UNI;
2597 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff);
2598 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff);
2600 /* Reject all Unicast addresses */
2601 port_cfg_reg &= ~MVNETA_UNI_PROMISC_MODE;
2602 val &= ~MVNETA_FORCE_UNI;
2605 mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg);
2606 mvreg_write(pp, MVNETA_TYPE_PRIO, val);
2609 /* register unicast and multicast addresses */
2610 static void mvneta_set_rx_mode(struct net_device *dev)
2612 struct mvneta_port *pp = netdev_priv(dev);
2613 struct netdev_hw_addr *ha;
2615 if (dev->flags & IFF_PROMISC) {
2616 /* Accept all: Multicast + Unicast */
2617 mvneta_rx_unicast_promisc_set(pp, 1);
2618 mvneta_set_ucast_table(pp, pp->rxq_def);
2619 mvneta_set_special_mcast_table(pp, pp->rxq_def);
2620 mvneta_set_other_mcast_table(pp, pp->rxq_def);
2622 /* Accept single Unicast */
2623 mvneta_rx_unicast_promisc_set(pp, 0);
2624 mvneta_set_ucast_table(pp, -1);
2625 mvneta_mac_addr_set(pp, dev->dev_addr, pp->rxq_def);
2627 if (dev->flags & IFF_ALLMULTI) {
2628 /* Accept all multicast */
2629 mvneta_set_special_mcast_table(pp, pp->rxq_def);
2630 mvneta_set_other_mcast_table(pp, pp->rxq_def);
2632 /* Accept only initialized multicast */
2633 mvneta_set_special_mcast_table(pp, -1);
2634 mvneta_set_other_mcast_table(pp, -1);
2636 if (!netdev_mc_empty(dev)) {
2637 netdev_for_each_mc_addr(ha, dev) {
2638 mvneta_mcast_addr_set(pp, ha->addr,
2646 /* Interrupt handling - the callback for request_irq() */
2647 static irqreturn_t mvneta_isr(int irq, void *dev_id)
2649 struct mvneta_port *pp = (struct mvneta_port *)dev_id;
2651 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
2652 napi_schedule(&pp->napi);
2657 /* Interrupt handling - the callback for request_percpu_irq() */
2658 static irqreturn_t mvneta_percpu_isr(int irq, void *dev_id)
2660 struct mvneta_pcpu_port *port = (struct mvneta_pcpu_port *)dev_id;
2662 disable_percpu_irq(port->pp->dev->irq);
2663 napi_schedule(&port->napi);
2668 static void mvneta_link_change(struct mvneta_port *pp)
2670 u32 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS);
2672 phylink_mac_change(pp->phylink, !!(gmac_stat & MVNETA_GMAC_LINK_UP));
2676 * Bits 0 - 7 of the causeRxTx register indicate that are transmitted
2677 * packets on the corresponding TXQ (Bit 0 is for TX queue 1).
2678 * Bits 8 -15 of the cause Rx Tx register indicate that are received
2679 * packets on the corresponding RXQ (Bit 8 is for RX queue 0).
2680 * Each CPU has its own causeRxTx register
2682 static int mvneta_poll(struct napi_struct *napi, int budget)
2687 struct mvneta_port *pp = netdev_priv(napi->dev);
2688 struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports);
2690 if (!netif_running(pp->dev)) {
2691 napi_complete(napi);
2695 /* Read cause register */
2696 cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE);
2697 if (cause_rx_tx & MVNETA_MISCINTR_INTR_MASK) {
2698 u32 cause_misc = mvreg_read(pp, MVNETA_INTR_MISC_CAUSE);
2700 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
2702 if (cause_misc & (MVNETA_CAUSE_PHY_STATUS_CHANGE |
2703 MVNETA_CAUSE_LINK_CHANGE))
2704 mvneta_link_change(pp);
2707 /* Release Tx descriptors */
2708 if (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL) {
2709 mvneta_tx_done_gbe(pp, (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL));
2710 cause_rx_tx &= ~MVNETA_TX_INTR_MASK_ALL;
2713 /* For the case where the last mvneta_poll did not process all
2716 rx_queue = fls(((cause_rx_tx >> 8) & 0xff));
2718 cause_rx_tx |= pp->neta_armada3700 ? pp->cause_rx_tx :
2722 rx_queue = rx_queue - 1;
2724 rx_done = mvneta_rx_hwbm(pp, budget, &pp->rxqs[rx_queue]);
2726 rx_done = mvneta_rx_swbm(pp, budget, &pp->rxqs[rx_queue]);
2729 if (rx_done < budget) {
2731 napi_complete_done(napi, rx_done);
2733 if (pp->neta_armada3700) {
2734 unsigned long flags;
2736 local_irq_save(flags);
2737 mvreg_write(pp, MVNETA_INTR_NEW_MASK,
2738 MVNETA_RX_INTR_MASK(rxq_number) |
2739 MVNETA_TX_INTR_MASK(txq_number) |
2740 MVNETA_MISCINTR_INTR_MASK);
2741 local_irq_restore(flags);
2743 enable_percpu_irq(pp->dev->irq, 0);
2747 if (pp->neta_armada3700)
2748 pp->cause_rx_tx = cause_rx_tx;
2750 port->cause_rx_tx = cause_rx_tx;
2755 /* Handle rxq fill: allocates rxq skbs; called when initializing a port */
2756 static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq,
2761 for (i = 0; i < num; i++) {
2762 memset(rxq->descs + i, 0, sizeof(struct mvneta_rx_desc));
2763 if (mvneta_rx_refill(pp, rxq->descs + i, rxq) != 0) {
2764 netdev_err(pp->dev, "%s:rxq %d, %d of %d buffs filled\n",
2765 __func__, rxq->id, i, num);
2770 /* Add this number of RX descriptors as non occupied (ready to
2773 mvneta_rxq_non_occup_desc_add(pp, rxq, i);
2778 /* Free all packets pending transmit from all TXQs and reset TX port */
2779 static void mvneta_tx_reset(struct mvneta_port *pp)
2783 /* free the skb's in the tx ring */
2784 for (queue = 0; queue < txq_number; queue++)
2785 mvneta_txq_done_force(pp, &pp->txqs[queue]);
2787 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
2788 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
2791 static void mvneta_rx_reset(struct mvneta_port *pp)
2793 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
2794 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
2797 /* Rx/Tx queue initialization/cleanup methods */
2799 /* Create a specified RX queue */
2800 static int mvneta_rxq_init(struct mvneta_port *pp,
2801 struct mvneta_rx_queue *rxq)
2804 rxq->size = pp->rx_ring_size;
2806 /* Allocate memory for RX descriptors */
2807 rxq->descs = dma_alloc_coherent(pp->dev->dev.parent,
2808 rxq->size * MVNETA_DESC_ALIGNED_SIZE,
2809 &rxq->descs_phys, GFP_KERNEL);
2813 rxq->last_desc = rxq->size - 1;
2815 /* Set Rx descriptors queue starting address */
2816 mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys);
2817 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size);
2820 mvneta_rxq_offset_set(pp, rxq, NET_SKB_PAD - pp->rx_offset_correction);
2822 /* Set coalescing pkts and time */
2823 mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal);
2824 mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal);
2827 /* Fill RXQ with buffers from RX pool */
2828 mvneta_rxq_buf_size_set(pp, rxq,
2829 MVNETA_RX_BUF_SIZE(pp->pkt_size));
2830 mvneta_rxq_bm_disable(pp, rxq);
2831 mvneta_rxq_fill(pp, rxq, rxq->size);
2833 mvneta_rxq_bm_enable(pp, rxq);
2834 mvneta_rxq_long_pool_set(pp, rxq);
2835 mvneta_rxq_short_pool_set(pp, rxq);
2836 mvneta_rxq_non_occup_desc_add(pp, rxq, rxq->size);
2842 /* Cleanup Rx queue */
2843 static void mvneta_rxq_deinit(struct mvneta_port *pp,
2844 struct mvneta_rx_queue *rxq)
2846 mvneta_rxq_drop_pkts(pp, rxq);
2849 dma_free_coherent(pp->dev->dev.parent,
2850 rxq->size * MVNETA_DESC_ALIGNED_SIZE,
2856 rxq->next_desc_to_proc = 0;
2857 rxq->descs_phys = 0;
2860 /* Create and initialize a tx queue */
2861 static int mvneta_txq_init(struct mvneta_port *pp,
2862 struct mvneta_tx_queue *txq)
2866 txq->size = pp->tx_ring_size;
2868 /* A queue must always have room for at least one skb.
2869 * Therefore, stop the queue when the free entries reaches
2870 * the maximum number of descriptors per skb.
2872 txq->tx_stop_threshold = txq->size - MVNETA_MAX_SKB_DESCS;
2873 txq->tx_wake_threshold = txq->tx_stop_threshold / 2;
2876 /* Allocate memory for TX descriptors */
2877 txq->descs = dma_alloc_coherent(pp->dev->dev.parent,
2878 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2879 &txq->descs_phys, GFP_KERNEL);
2883 txq->last_desc = txq->size - 1;
2885 /* Set maximum bandwidth for enabled TXQs */
2886 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff);
2887 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff);
2889 /* Set Tx descriptors queue starting address */
2890 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys);
2891 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size);
2893 txq->tx_skb = kmalloc_array(txq->size, sizeof(*txq->tx_skb),
2896 dma_free_coherent(pp->dev->dev.parent,
2897 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2898 txq->descs, txq->descs_phys);
2902 /* Allocate DMA buffers for TSO MAC/IP/TCP headers */
2903 txq->tso_hdrs = dma_alloc_coherent(pp->dev->dev.parent,
2904 txq->size * TSO_HEADER_SIZE,
2905 &txq->tso_hdrs_phys, GFP_KERNEL);
2906 if (!txq->tso_hdrs) {
2908 dma_free_coherent(pp->dev->dev.parent,
2909 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2910 txq->descs, txq->descs_phys);
2913 mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal);
2915 /* Setup XPS mapping */
2917 cpu = txq->id % num_present_cpus();
2919 cpu = pp->rxq_def % num_present_cpus();
2920 cpumask_set_cpu(cpu, &txq->affinity_mask);
2921 netif_set_xps_queue(pp->dev, &txq->affinity_mask, txq->id);
2926 /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/
2927 static void mvneta_txq_deinit(struct mvneta_port *pp,
2928 struct mvneta_tx_queue *txq)
2930 struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id);
2935 dma_free_coherent(pp->dev->dev.parent,
2936 txq->size * TSO_HEADER_SIZE,
2937 txq->tso_hdrs, txq->tso_hdrs_phys);
2939 dma_free_coherent(pp->dev->dev.parent,
2940 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2941 txq->descs, txq->descs_phys);
2943 netdev_tx_reset_queue(nq);
2947 txq->next_desc_to_proc = 0;
2948 txq->descs_phys = 0;
2950 /* Set minimum bandwidth for disabled TXQs */
2951 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0);
2952 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0);
2954 /* Set Tx descriptors queue starting address and size */
2955 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0);
2956 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0);
2959 /* Cleanup all Tx queues */
2960 static void mvneta_cleanup_txqs(struct mvneta_port *pp)
2964 for (queue = 0; queue < txq_number; queue++)
2965 mvneta_txq_deinit(pp, &pp->txqs[queue]);
2968 /* Cleanup all Rx queues */
2969 static void mvneta_cleanup_rxqs(struct mvneta_port *pp)
2973 for (queue = 0; queue < rxq_number; queue++)
2974 mvneta_rxq_deinit(pp, &pp->rxqs[queue]);
2978 /* Init all Rx queues */
2979 static int mvneta_setup_rxqs(struct mvneta_port *pp)
2983 for (queue = 0; queue < rxq_number; queue++) {
2984 int err = mvneta_rxq_init(pp, &pp->rxqs[queue]);
2987 netdev_err(pp->dev, "%s: can't create rxq=%d\n",
2989 mvneta_cleanup_rxqs(pp);
2997 /* Init all tx queues */
2998 static int mvneta_setup_txqs(struct mvneta_port *pp)
3002 for (queue = 0; queue < txq_number; queue++) {
3003 int err = mvneta_txq_init(pp, &pp->txqs[queue]);
3005 netdev_err(pp->dev, "%s: can't create txq=%d\n",
3007 mvneta_cleanup_txqs(pp);
3015 static void mvneta_start_dev(struct mvneta_port *pp)
3019 mvneta_max_rx_size_set(pp, pp->pkt_size);
3020 mvneta_txq_max_tx_size_set(pp, pp->pkt_size);
3022 /* start the Rx/Tx activity */
3023 mvneta_port_enable(pp);
3025 if (!pp->neta_armada3700) {
3026 /* Enable polling on the port */
3027 for_each_online_cpu(cpu) {
3028 struct mvneta_pcpu_port *port =
3029 per_cpu_ptr(pp->ports, cpu);
3031 napi_enable(&port->napi);
3034 napi_enable(&pp->napi);
3037 /* Unmask interrupts. It has to be done from each CPU */
3038 on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true);
3040 mvreg_write(pp, MVNETA_INTR_MISC_MASK,
3041 MVNETA_CAUSE_PHY_STATUS_CHANGE |
3042 MVNETA_CAUSE_LINK_CHANGE);
3044 phylink_start(pp->phylink);
3045 netif_tx_start_all_queues(pp->dev);
3048 static void mvneta_stop_dev(struct mvneta_port *pp)
3052 phylink_stop(pp->phylink);
3054 if (!pp->neta_armada3700) {
3055 for_each_online_cpu(cpu) {
3056 struct mvneta_pcpu_port *port =
3057 per_cpu_ptr(pp->ports, cpu);
3059 napi_disable(&port->napi);
3062 napi_disable(&pp->napi);
3065 netif_carrier_off(pp->dev);
3067 mvneta_port_down(pp);
3068 netif_tx_stop_all_queues(pp->dev);
3070 /* Stop the port activity */
3071 mvneta_port_disable(pp);
3073 /* Clear all ethernet port interrupts */
3074 on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true);
3076 /* Mask all ethernet port interrupts */
3077 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
3079 mvneta_tx_reset(pp);
3080 mvneta_rx_reset(pp);
3083 static void mvneta_percpu_enable(void *arg)
3085 struct mvneta_port *pp = arg;
3087 enable_percpu_irq(pp->dev->irq, IRQ_TYPE_NONE);
3090 static void mvneta_percpu_disable(void *arg)
3092 struct mvneta_port *pp = arg;
3094 disable_percpu_irq(pp->dev->irq);
3097 /* Change the device mtu */
3098 static int mvneta_change_mtu(struct net_device *dev, int mtu)
3100 struct mvneta_port *pp = netdev_priv(dev);
3103 if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu), 8)) {
3104 netdev_info(dev, "Illegal MTU value %d, rounding to %d\n",
3105 mtu, ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8));
3106 mtu = ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8);
3111 if (!netif_running(dev)) {
3113 mvneta_bm_update_mtu(pp, mtu);
3115 netdev_update_features(dev);
3119 /* The interface is running, so we have to force a
3120 * reallocation of the queues
3122 mvneta_stop_dev(pp);
3123 on_each_cpu(mvneta_percpu_disable, pp, true);
3125 mvneta_cleanup_txqs(pp);
3126 mvneta_cleanup_rxqs(pp);
3129 mvneta_bm_update_mtu(pp, mtu);
3131 pp->pkt_size = MVNETA_RX_PKT_SIZE(dev->mtu);
3132 pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) +
3133 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3135 ret = mvneta_setup_rxqs(pp);
3137 netdev_err(dev, "unable to setup rxqs after MTU change\n");
3141 ret = mvneta_setup_txqs(pp);
3143 netdev_err(dev, "unable to setup txqs after MTU change\n");
3147 on_each_cpu(mvneta_percpu_enable, pp, true);
3148 mvneta_start_dev(pp);
3151 netdev_update_features(dev);
3156 static netdev_features_t mvneta_fix_features(struct net_device *dev,
3157 netdev_features_t features)
3159 struct mvneta_port *pp = netdev_priv(dev);
3161 if (pp->tx_csum_limit && dev->mtu > pp->tx_csum_limit) {
3162 features &= ~(NETIF_F_IP_CSUM | NETIF_F_TSO);
3164 "Disable IP checksum for MTU greater than %dB\n",
3171 /* Get mac address */
3172 static void mvneta_get_mac_addr(struct mvneta_port *pp, unsigned char *addr)
3174 u32 mac_addr_l, mac_addr_h;
3176 mac_addr_l = mvreg_read(pp, MVNETA_MAC_ADDR_LOW);
3177 mac_addr_h = mvreg_read(pp, MVNETA_MAC_ADDR_HIGH);
3178 addr[0] = (mac_addr_h >> 24) & 0xFF;
3179 addr[1] = (mac_addr_h >> 16) & 0xFF;
3180 addr[2] = (mac_addr_h >> 8) & 0xFF;
3181 addr[3] = mac_addr_h & 0xFF;
3182 addr[4] = (mac_addr_l >> 8) & 0xFF;
3183 addr[5] = mac_addr_l & 0xFF;
3186 /* Handle setting mac address */
3187 static int mvneta_set_mac_addr(struct net_device *dev, void *addr)
3189 struct mvneta_port *pp = netdev_priv(dev);
3190 struct sockaddr *sockaddr = addr;
3193 ret = eth_prepare_mac_addr_change(dev, addr);
3196 /* Remove previous address table entry */
3197 mvneta_mac_addr_set(pp, dev->dev_addr, -1);
3199 /* Set new addr in hw */
3200 mvneta_mac_addr_set(pp, sockaddr->sa_data, pp->rxq_def);
3202 eth_commit_mac_addr_change(dev, addr);
3206 static void mvneta_validate(struct net_device *ndev, unsigned long *supported,
3207 struct phylink_link_state *state)
3209 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
3211 /* We only support QSGMII, SGMII, 802.3z and RGMII modes */
3212 if (state->interface != PHY_INTERFACE_MODE_NA &&
3213 state->interface != PHY_INTERFACE_MODE_QSGMII &&
3214 state->interface != PHY_INTERFACE_MODE_SGMII &&
3215 !phy_interface_mode_is_8023z(state->interface) &&
3216 !phy_interface_mode_is_rgmii(state->interface)) {
3217 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
3221 /* Allow all the expected bits */
3222 phylink_set(mask, Autoneg);
3223 phylink_set_port_modes(mask);
3225 /* Asymmetric pause is unsupported */
3226 phylink_set(mask, Pause);
3227 /* Half-duplex at speeds higher than 100Mbit is unsupported */
3228 phylink_set(mask, 1000baseT_Full);
3229 phylink_set(mask, 1000baseX_Full);
3231 if (!phy_interface_mode_is_8023z(state->interface)) {
3232 /* 10M and 100M are only supported in non-802.3z mode */
3233 phylink_set(mask, 10baseT_Half);
3234 phylink_set(mask, 10baseT_Full);
3235 phylink_set(mask, 100baseT_Half);
3236 phylink_set(mask, 100baseT_Full);
3239 bitmap_and(supported, supported, mask,
3240 __ETHTOOL_LINK_MODE_MASK_NBITS);
3241 bitmap_and(state->advertising, state->advertising, mask,
3242 __ETHTOOL_LINK_MODE_MASK_NBITS);
3245 static int mvneta_mac_link_state(struct net_device *ndev,
3246 struct phylink_link_state *state)
3248 struct mvneta_port *pp = netdev_priv(ndev);
3251 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS);
3253 if (gmac_stat & MVNETA_GMAC_SPEED_1000)
3254 state->speed = SPEED_1000;
3255 else if (gmac_stat & MVNETA_GMAC_SPEED_100)
3256 state->speed = SPEED_100;
3258 state->speed = SPEED_10;
3260 state->an_complete = !!(gmac_stat & MVNETA_GMAC_AN_COMPLETE);
3261 state->link = !!(gmac_stat & MVNETA_GMAC_LINK_UP);
3262 state->duplex = !!(gmac_stat & MVNETA_GMAC_FULL_DUPLEX);
3265 if (gmac_stat & MVNETA_GMAC_RX_FLOW_CTRL_ENABLE)
3266 state->pause |= MLO_PAUSE_RX;
3267 if (gmac_stat & MVNETA_GMAC_TX_FLOW_CTRL_ENABLE)
3268 state->pause |= MLO_PAUSE_TX;
3273 static void mvneta_mac_an_restart(struct net_device *ndev)
3275 struct mvneta_port *pp = netdev_priv(ndev);
3276 u32 gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
3278 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
3279 gmac_an | MVNETA_GMAC_INBAND_RESTART_AN);
3280 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
3281 gmac_an & ~MVNETA_GMAC_INBAND_RESTART_AN);
3284 static void mvneta_mac_config(struct net_device *ndev, unsigned int mode,
3285 const struct phylink_link_state *state)
3287 struct mvneta_port *pp = netdev_priv(ndev);
3288 u32 new_ctrl0, gmac_ctrl0 = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
3289 u32 new_ctrl2, gmac_ctrl2 = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
3290 u32 new_clk, gmac_clk = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER);
3291 u32 new_an, gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
3293 new_ctrl0 = gmac_ctrl0 & ~MVNETA_GMAC0_PORT_1000BASE_X;
3294 new_ctrl2 = gmac_ctrl2 & ~(MVNETA_GMAC2_INBAND_AN_ENABLE |
3295 MVNETA_GMAC2_PORT_RESET);
3296 new_clk = gmac_clk & ~MVNETA_GMAC_1MS_CLOCK_ENABLE;
3297 new_an = gmac_an & ~(MVNETA_GMAC_INBAND_AN_ENABLE |
3298 MVNETA_GMAC_INBAND_RESTART_AN |
3299 MVNETA_GMAC_CONFIG_MII_SPEED |
3300 MVNETA_GMAC_CONFIG_GMII_SPEED |
3301 MVNETA_GMAC_AN_SPEED_EN |
3302 MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL |
3303 MVNETA_GMAC_CONFIG_FLOW_CTRL |
3304 MVNETA_GMAC_AN_FLOW_CTRL_EN |
3305 MVNETA_GMAC_CONFIG_FULL_DUPLEX |
3306 MVNETA_GMAC_AN_DUPLEX_EN);
3308 /* Even though it might look weird, when we're configured in
3309 * SGMII or QSGMII mode, the RGMII bit needs to be set.
3311 new_ctrl2 |= MVNETA_GMAC2_PORT_RGMII;
3313 if (state->interface == PHY_INTERFACE_MODE_QSGMII ||
3314 state->interface == PHY_INTERFACE_MODE_SGMII ||
3315 phy_interface_mode_is_8023z(state->interface))
3316 new_ctrl2 |= MVNETA_GMAC2_PCS_ENABLE;
3318 if (phylink_test(state->advertising, Pause))
3319 new_an |= MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL;
3320 if (state->pause & MLO_PAUSE_TXRX_MASK)
3321 new_an |= MVNETA_GMAC_CONFIG_FLOW_CTRL;
3323 if (!phylink_autoneg_inband(mode)) {
3324 /* Phy or fixed speed */
3326 new_an |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
3328 if (state->speed == SPEED_1000)
3329 new_an |= MVNETA_GMAC_CONFIG_GMII_SPEED;
3330 else if (state->speed == SPEED_100)
3331 new_an |= MVNETA_GMAC_CONFIG_MII_SPEED;
3332 } else if (state->interface == PHY_INTERFACE_MODE_SGMII) {
3333 /* SGMII mode receives the state from the PHY */
3334 new_ctrl2 |= MVNETA_GMAC2_INBAND_AN_ENABLE;
3335 new_clk |= MVNETA_GMAC_1MS_CLOCK_ENABLE;
3336 new_an = (new_an & ~(MVNETA_GMAC_FORCE_LINK_DOWN |
3337 MVNETA_GMAC_FORCE_LINK_PASS)) |
3338 MVNETA_GMAC_INBAND_AN_ENABLE |
3339 MVNETA_GMAC_AN_SPEED_EN |
3340 MVNETA_GMAC_AN_DUPLEX_EN;
3342 /* 802.3z negotiation - only 1000base-X */
3343 new_ctrl0 |= MVNETA_GMAC0_PORT_1000BASE_X;
3344 new_clk |= MVNETA_GMAC_1MS_CLOCK_ENABLE;
3345 new_an = (new_an & ~(MVNETA_GMAC_FORCE_LINK_DOWN |
3346 MVNETA_GMAC_FORCE_LINK_PASS)) |
3347 MVNETA_GMAC_INBAND_AN_ENABLE |
3348 MVNETA_GMAC_CONFIG_GMII_SPEED |
3349 /* The MAC only supports FD mode */
3350 MVNETA_GMAC_CONFIG_FULL_DUPLEX;
3352 if (state->pause & MLO_PAUSE_AN && state->an_enabled)
3353 new_an |= MVNETA_GMAC_AN_FLOW_CTRL_EN;
3356 /* Armada 370 documentation says we can only change the port mode
3357 * and in-band enable when the link is down, so force it down
3358 * while making these changes. We also do this for GMAC_CTRL2 */
3359 if ((new_ctrl0 ^ gmac_ctrl0) & MVNETA_GMAC0_PORT_1000BASE_X ||
3360 (new_ctrl2 ^ gmac_ctrl2) & MVNETA_GMAC2_INBAND_AN_ENABLE ||
3361 (new_an ^ gmac_an) & MVNETA_GMAC_INBAND_AN_ENABLE) {
3362 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
3363 (gmac_an & ~MVNETA_GMAC_FORCE_LINK_PASS) |
3364 MVNETA_GMAC_FORCE_LINK_DOWN);
3367 if (new_ctrl0 != gmac_ctrl0)
3368 mvreg_write(pp, MVNETA_GMAC_CTRL_0, new_ctrl0);
3369 if (new_ctrl2 != gmac_ctrl2)
3370 mvreg_write(pp, MVNETA_GMAC_CTRL_2, new_ctrl2);
3371 if (new_clk != gmac_clk)
3372 mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, new_clk);
3373 if (new_an != gmac_an)
3374 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, new_an);
3376 if (gmac_ctrl2 & MVNETA_GMAC2_PORT_RESET) {
3377 while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) &
3378 MVNETA_GMAC2_PORT_RESET) != 0)
3383 static void mvneta_set_eee(struct mvneta_port *pp, bool enable)
3387 lpi_ctl1 = mvreg_read(pp, MVNETA_LPI_CTRL_1);
3389 lpi_ctl1 |= MVNETA_LPI_REQUEST_ENABLE;
3391 lpi_ctl1 &= ~MVNETA_LPI_REQUEST_ENABLE;
3392 mvreg_write(pp, MVNETA_LPI_CTRL_1, lpi_ctl1);
3395 static void mvneta_mac_link_down(struct net_device *ndev, unsigned int mode,
3396 phy_interface_t interface)
3398 struct mvneta_port *pp = netdev_priv(ndev);
3401 mvneta_port_down(pp);
3403 if (!phylink_autoneg_inband(mode)) {
3404 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
3405 val &= ~MVNETA_GMAC_FORCE_LINK_PASS;
3406 val |= MVNETA_GMAC_FORCE_LINK_DOWN;
3407 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
3410 pp->eee_active = false;
3411 mvneta_set_eee(pp, false);
3414 static void mvneta_mac_link_up(struct net_device *ndev, unsigned int mode,
3415 phy_interface_t interface,
3416 struct phy_device *phy)
3418 struct mvneta_port *pp = netdev_priv(ndev);
3421 if (!phylink_autoneg_inband(mode)) {
3422 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
3423 val &= ~MVNETA_GMAC_FORCE_LINK_DOWN;
3424 val |= MVNETA_GMAC_FORCE_LINK_PASS;
3425 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
3430 if (phy && pp->eee_enabled) {
3431 pp->eee_active = phy_init_eee(phy, 0) >= 0;
3432 mvneta_set_eee(pp, pp->eee_active && pp->tx_lpi_enabled);
3436 static const struct phylink_mac_ops mvneta_phylink_ops = {
3437 .validate = mvneta_validate,
3438 .mac_link_state = mvneta_mac_link_state,
3439 .mac_an_restart = mvneta_mac_an_restart,
3440 .mac_config = mvneta_mac_config,
3441 .mac_link_down = mvneta_mac_link_down,
3442 .mac_link_up = mvneta_mac_link_up,
3445 static int mvneta_mdio_probe(struct mvneta_port *pp)
3447 struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL };
3448 int err = phylink_of_phy_connect(pp->phylink, pp->dn, 0);
3451 netdev_err(pp->dev, "could not attach PHY: %d\n", err);
3453 phylink_ethtool_get_wol(pp->phylink, &wol);
3454 device_set_wakeup_capable(&pp->dev->dev, !!wol.supported);
3459 static void mvneta_mdio_remove(struct mvneta_port *pp)
3461 phylink_disconnect_phy(pp->phylink);
3464 /* Electing a CPU must be done in an atomic way: it should be done
3465 * after or before the removal/insertion of a CPU and this function is
3468 static void mvneta_percpu_elect(struct mvneta_port *pp)
3470 int elected_cpu = 0, max_cpu, cpu, i = 0;
3472 /* Use the cpu associated to the rxq when it is online, in all
3473 * the other cases, use the cpu 0 which can't be offline.
3475 if (cpu_online(pp->rxq_def))
3476 elected_cpu = pp->rxq_def;
3478 max_cpu = num_present_cpus();
3480 for_each_online_cpu(cpu) {
3481 int rxq_map = 0, txq_map = 0;
3484 for (rxq = 0; rxq < rxq_number; rxq++)
3485 if ((rxq % max_cpu) == cpu)
3486 rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq);
3488 if (cpu == elected_cpu)
3489 /* Map the default receive queue queue to the
3492 rxq_map |= MVNETA_CPU_RXQ_ACCESS(pp->rxq_def);
3494 /* We update the TX queue map only if we have one
3495 * queue. In this case we associate the TX queue to
3496 * the CPU bound to the default RX queue
3498 if (txq_number == 1)
3499 txq_map = (cpu == elected_cpu) ?
3500 MVNETA_CPU_TXQ_ACCESS(1) : 0;
3502 txq_map = mvreg_read(pp, MVNETA_CPU_MAP(cpu)) &
3503 MVNETA_CPU_TXQ_ACCESS_ALL_MASK;
3505 mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map);
3507 /* Update the interrupt mask on each CPU according the
3510 smp_call_function_single(cpu, mvneta_percpu_unmask_interrupt,
3517 static int mvneta_cpu_online(unsigned int cpu, struct hlist_node *node)
3520 struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port,
3522 struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu);
3525 spin_lock(&pp->lock);
3527 * Configuring the driver for a new CPU while the driver is
3528 * stopping is racy, so just avoid it.
3530 if (pp->is_stopped) {
3531 spin_unlock(&pp->lock);
3534 netif_tx_stop_all_queues(pp->dev);
3537 * We have to synchronise on tha napi of each CPU except the one
3538 * just being woken up
3540 for_each_online_cpu(other_cpu) {
3541 if (other_cpu != cpu) {
3542 struct mvneta_pcpu_port *other_port =
3543 per_cpu_ptr(pp->ports, other_cpu);
3545 napi_synchronize(&other_port->napi);
3549 /* Mask all ethernet port interrupts */
3550 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
3551 napi_enable(&port->napi);
3554 * Enable per-CPU interrupts on the CPU that is
3557 mvneta_percpu_enable(pp);
3560 * Enable per-CPU interrupt on the one CPU we care
3563 mvneta_percpu_elect(pp);
3565 /* Unmask all ethernet port interrupts */
3566 on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true);
3567 mvreg_write(pp, MVNETA_INTR_MISC_MASK,
3568 MVNETA_CAUSE_PHY_STATUS_CHANGE |
3569 MVNETA_CAUSE_LINK_CHANGE);
3570 netif_tx_start_all_queues(pp->dev);
3571 spin_unlock(&pp->lock);
3575 static int mvneta_cpu_down_prepare(unsigned int cpu, struct hlist_node *node)
3577 struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port,
3579 struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu);
3582 * Thanks to this lock we are sure that any pending cpu election is
3585 spin_lock(&pp->lock);
3586 /* Mask all ethernet port interrupts */
3587 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
3588 spin_unlock(&pp->lock);
3590 napi_synchronize(&port->napi);
3591 napi_disable(&port->napi);
3592 /* Disable per-CPU interrupts on the CPU that is brought down. */
3593 mvneta_percpu_disable(pp);
3597 static int mvneta_cpu_dead(unsigned int cpu, struct hlist_node *node)
3599 struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port,
3602 /* Check if a new CPU must be elected now this on is down */
3603 spin_lock(&pp->lock);
3604 mvneta_percpu_elect(pp);
3605 spin_unlock(&pp->lock);
3606 /* Unmask all ethernet port interrupts */
3607 on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true);
3608 mvreg_write(pp, MVNETA_INTR_MISC_MASK,
3609 MVNETA_CAUSE_PHY_STATUS_CHANGE |
3610 MVNETA_CAUSE_LINK_CHANGE);
3611 netif_tx_start_all_queues(pp->dev);
3615 static int mvneta_open(struct net_device *dev)
3617 struct mvneta_port *pp = netdev_priv(dev);
3620 pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu);
3621 pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) +
3622 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3624 ret = mvneta_setup_rxqs(pp);
3628 ret = mvneta_setup_txqs(pp);
3630 goto err_cleanup_rxqs;
3632 /* Connect to port interrupt line */
3633 if (pp->neta_armada3700)
3634 ret = request_irq(pp->dev->irq, mvneta_isr, 0,
3637 ret = request_percpu_irq(pp->dev->irq, mvneta_percpu_isr,
3638 dev->name, pp->ports);
3640 netdev_err(pp->dev, "cannot request irq %d\n", pp->dev->irq);
3641 goto err_cleanup_txqs;
3644 if (!pp->neta_armada3700) {
3645 /* Enable per-CPU interrupt on all the CPU to handle our RX
3648 on_each_cpu(mvneta_percpu_enable, pp, true);
3650 pp->is_stopped = false;
3651 /* Register a CPU notifier to handle the case where our CPU
3652 * might be taken offline.
3654 ret = cpuhp_state_add_instance_nocalls(online_hpstate,
3659 ret = cpuhp_state_add_instance_nocalls(CPUHP_NET_MVNETA_DEAD,
3662 goto err_free_online_hp;
3665 /* In default link is down */
3666 netif_carrier_off(pp->dev);
3668 ret = mvneta_mdio_probe(pp);
3670 netdev_err(dev, "cannot probe MDIO bus\n");
3671 goto err_free_dead_hp;
3674 mvneta_start_dev(pp);
3679 if (!pp->neta_armada3700)
3680 cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD,
3683 if (!pp->neta_armada3700)
3684 cpuhp_state_remove_instance_nocalls(online_hpstate,
3687 if (pp->neta_armada3700) {
3688 free_irq(pp->dev->irq, pp);
3690 on_each_cpu(mvneta_percpu_disable, pp, true);
3691 free_percpu_irq(pp->dev->irq, pp->ports);
3694 mvneta_cleanup_txqs(pp);
3696 mvneta_cleanup_rxqs(pp);
3700 /* Stop the port, free port interrupt line */
3701 static int mvneta_stop(struct net_device *dev)
3703 struct mvneta_port *pp = netdev_priv(dev);
3705 if (!pp->neta_armada3700) {
3706 /* Inform that we are stopping so we don't want to setup the
3707 * driver for new CPUs in the notifiers. The code of the
3708 * notifier for CPU online is protected by the same spinlock,
3709 * so when we get the lock, the notifer work is done.
3711 spin_lock(&pp->lock);
3712 pp->is_stopped = true;
3713 spin_unlock(&pp->lock);
3715 mvneta_stop_dev(pp);
3716 mvneta_mdio_remove(pp);
3718 cpuhp_state_remove_instance_nocalls(online_hpstate,
3720 cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD,
3722 on_each_cpu(mvneta_percpu_disable, pp, true);
3723 free_percpu_irq(dev->irq, pp->ports);
3725 mvneta_stop_dev(pp);
3726 mvneta_mdio_remove(pp);
3727 free_irq(dev->irq, pp);
3730 mvneta_cleanup_rxqs(pp);
3731 mvneta_cleanup_txqs(pp);
3736 static int mvneta_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3738 struct mvneta_port *pp = netdev_priv(dev);
3740 return phylink_mii_ioctl(pp->phylink, ifr, cmd);
3743 /* Ethtool methods */
3745 /* Set link ksettings (phy address, speed) for ethtools */
3747 mvneta_ethtool_set_link_ksettings(struct net_device *ndev,
3748 const struct ethtool_link_ksettings *cmd)
3750 struct mvneta_port *pp = netdev_priv(ndev);
3752 return phylink_ethtool_ksettings_set(pp->phylink, cmd);
3755 /* Get link ksettings for ethtools */
3757 mvneta_ethtool_get_link_ksettings(struct net_device *ndev,
3758 struct ethtool_link_ksettings *cmd)
3760 struct mvneta_port *pp = netdev_priv(ndev);
3762 return phylink_ethtool_ksettings_get(pp->phylink, cmd);
3765 static int mvneta_ethtool_nway_reset(struct net_device *dev)
3767 struct mvneta_port *pp = netdev_priv(dev);
3769 return phylink_ethtool_nway_reset(pp->phylink);
3772 /* Set interrupt coalescing for ethtools */
3773 static int mvneta_ethtool_set_coalesce(struct net_device *dev,
3774 struct ethtool_coalesce *c)
3776 struct mvneta_port *pp = netdev_priv(dev);
3779 for (queue = 0; queue < rxq_number; queue++) {
3780 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
3781 rxq->time_coal = c->rx_coalesce_usecs;
3782 rxq->pkts_coal = c->rx_max_coalesced_frames;
3783 mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal);
3784 mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal);
3787 for (queue = 0; queue < txq_number; queue++) {
3788 struct mvneta_tx_queue *txq = &pp->txqs[queue];
3789 txq->done_pkts_coal = c->tx_max_coalesced_frames;
3790 mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal);
3796 /* get coalescing for ethtools */
3797 static int mvneta_ethtool_get_coalesce(struct net_device *dev,
3798 struct ethtool_coalesce *c)
3800 struct mvneta_port *pp = netdev_priv(dev);
3802 c->rx_coalesce_usecs = pp->rxqs[0].time_coal;
3803 c->rx_max_coalesced_frames = pp->rxqs[0].pkts_coal;
3805 c->tx_max_coalesced_frames = pp->txqs[0].done_pkts_coal;
3810 static void mvneta_ethtool_get_drvinfo(struct net_device *dev,
3811 struct ethtool_drvinfo *drvinfo)
3813 strlcpy(drvinfo->driver, MVNETA_DRIVER_NAME,
3814 sizeof(drvinfo->driver));
3815 strlcpy(drvinfo->version, MVNETA_DRIVER_VERSION,
3816 sizeof(drvinfo->version));
3817 strlcpy(drvinfo->bus_info, dev_name(&dev->dev),
3818 sizeof(drvinfo->bus_info));
3822 static void mvneta_ethtool_get_ringparam(struct net_device *netdev,
3823 struct ethtool_ringparam *ring)
3825 struct mvneta_port *pp = netdev_priv(netdev);
3827 ring->rx_max_pending = MVNETA_MAX_RXD;
3828 ring->tx_max_pending = MVNETA_MAX_TXD;
3829 ring->rx_pending = pp->rx_ring_size;
3830 ring->tx_pending = pp->tx_ring_size;
3833 static int mvneta_ethtool_set_ringparam(struct net_device *dev,
3834 struct ethtool_ringparam *ring)
3836 struct mvneta_port *pp = netdev_priv(dev);
3838 if ((ring->rx_pending == 0) || (ring->tx_pending == 0))
3840 pp->rx_ring_size = ring->rx_pending < MVNETA_MAX_RXD ?
3841 ring->rx_pending : MVNETA_MAX_RXD;
3843 pp->tx_ring_size = clamp_t(u16, ring->tx_pending,
3844 MVNETA_MAX_SKB_DESCS * 2, MVNETA_MAX_TXD);
3845 if (pp->tx_ring_size != ring->tx_pending)
3846 netdev_warn(dev, "TX queue size set to %u (requested %u)\n",
3847 pp->tx_ring_size, ring->tx_pending);
3849 if (netif_running(dev)) {
3851 if (mvneta_open(dev)) {
3853 "error on opening device after ring param change\n");
3861 static void mvneta_ethtool_get_pauseparam(struct net_device *dev,
3862 struct ethtool_pauseparam *pause)
3864 struct mvneta_port *pp = netdev_priv(dev);
3866 phylink_ethtool_get_pauseparam(pp->phylink, pause);
3869 static int mvneta_ethtool_set_pauseparam(struct net_device *dev,
3870 struct ethtool_pauseparam *pause)
3872 struct mvneta_port *pp = netdev_priv(dev);
3874 return phylink_ethtool_set_pauseparam(pp->phylink, pause);
3877 static void mvneta_ethtool_get_strings(struct net_device *netdev, u32 sset,
3880 if (sset == ETH_SS_STATS) {
3883 for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++)
3884 memcpy(data + i * ETH_GSTRING_LEN,
3885 mvneta_statistics[i].name, ETH_GSTRING_LEN);
3889 static void mvneta_ethtool_update_stats(struct mvneta_port *pp)
3891 const struct mvneta_statistic *s;
3892 void __iomem *base = pp->base;
3897 for (i = 0, s = mvneta_statistics;
3898 s < mvneta_statistics + ARRAY_SIZE(mvneta_statistics);
3904 val = readl_relaxed(base + s->offset);
3907 /* Docs say to read low 32-bit then high */
3908 low = readl_relaxed(base + s->offset);
3909 high = readl_relaxed(base + s->offset + 4);
3910 val = (u64)high << 32 | low;
3913 switch (s->offset) {
3914 case ETHTOOL_STAT_EEE_WAKEUP:
3915 val = phylink_get_eee_err(pp->phylink);
3921 pp->ethtool_stats[i] += val;
3925 static void mvneta_ethtool_get_stats(struct net_device *dev,
3926 struct ethtool_stats *stats, u64 *data)
3928 struct mvneta_port *pp = netdev_priv(dev);
3931 mvneta_ethtool_update_stats(pp);
3933 for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++)
3934 *data++ = pp->ethtool_stats[i];
3937 static int mvneta_ethtool_get_sset_count(struct net_device *dev, int sset)
3939 if (sset == ETH_SS_STATS)
3940 return ARRAY_SIZE(mvneta_statistics);
3944 static u32 mvneta_ethtool_get_rxfh_indir_size(struct net_device *dev)
3946 return MVNETA_RSS_LU_TABLE_SIZE;
3949 static int mvneta_ethtool_get_rxnfc(struct net_device *dev,
3950 struct ethtool_rxnfc *info,
3951 u32 *rules __always_unused)
3953 switch (info->cmd) {
3954 case ETHTOOL_GRXRINGS:
3955 info->data = rxq_number;
3964 static int mvneta_config_rss(struct mvneta_port *pp)
3969 netif_tx_stop_all_queues(pp->dev);
3971 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
3973 /* We have to synchronise on the napi of each CPU */
3974 for_each_online_cpu(cpu) {
3975 struct mvneta_pcpu_port *pcpu_port =
3976 per_cpu_ptr(pp->ports, cpu);
3978 napi_synchronize(&pcpu_port->napi);
3979 napi_disable(&pcpu_port->napi);
3982 pp->rxq_def = pp->indir[0];
3984 /* Update unicast mapping */
3985 mvneta_set_rx_mode(pp->dev);
3987 /* Update val of portCfg register accordingly with all RxQueue types */
3988 val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def);
3989 mvreg_write(pp, MVNETA_PORT_CONFIG, val);
3991 /* Update the elected CPU matching the new rxq_def */
3992 spin_lock(&pp->lock);
3993 mvneta_percpu_elect(pp);
3994 spin_unlock(&pp->lock);
3996 /* We have to synchronise on the napi of each CPU */
3997 for_each_online_cpu(cpu) {
3998 struct mvneta_pcpu_port *pcpu_port =
3999 per_cpu_ptr(pp->ports, cpu);
4001 napi_enable(&pcpu_port->napi);
4004 netif_tx_start_all_queues(pp->dev);
4009 static int mvneta_ethtool_set_rxfh(struct net_device *dev, const u32 *indir,
4010 const u8 *key, const u8 hfunc)
4012 struct mvneta_port *pp = netdev_priv(dev);
4014 /* Current code for Armada 3700 doesn't support RSS features yet */
4015 if (pp->neta_armada3700)
4018 /* We require at least one supported parameter to be changed
4019 * and no change in any of the unsupported parameters
4022 (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP))
4028 memcpy(pp->indir, indir, MVNETA_RSS_LU_TABLE_SIZE);
4030 return mvneta_config_rss(pp);
4033 static int mvneta_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
4036 struct mvneta_port *pp = netdev_priv(dev);
4038 /* Current code for Armada 3700 doesn't support RSS features yet */
4039 if (pp->neta_armada3700)
4043 *hfunc = ETH_RSS_HASH_TOP;
4048 memcpy(indir, pp->indir, MVNETA_RSS_LU_TABLE_SIZE);
4053 static void mvneta_ethtool_get_wol(struct net_device *dev,
4054 struct ethtool_wolinfo *wol)
4056 struct mvneta_port *pp = netdev_priv(dev);
4058 phylink_ethtool_get_wol(pp->phylink, wol);
4061 static int mvneta_ethtool_set_wol(struct net_device *dev,
4062 struct ethtool_wolinfo *wol)
4064 struct mvneta_port *pp = netdev_priv(dev);
4067 ret = phylink_ethtool_set_wol(pp->phylink, wol);
4069 device_set_wakeup_enable(&dev->dev, !!wol->wolopts);
4074 static int mvneta_ethtool_get_eee(struct net_device *dev,
4075 struct ethtool_eee *eee)
4077 struct mvneta_port *pp = netdev_priv(dev);
4080 lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0);
4082 eee->eee_enabled = pp->eee_enabled;
4083 eee->eee_active = pp->eee_active;
4084 eee->tx_lpi_enabled = pp->tx_lpi_enabled;
4085 eee->tx_lpi_timer = (lpi_ctl0) >> 8; // * scale;
4087 return phylink_ethtool_get_eee(pp->phylink, eee);
4090 static int mvneta_ethtool_set_eee(struct net_device *dev,
4091 struct ethtool_eee *eee)
4093 struct mvneta_port *pp = netdev_priv(dev);
4096 /* The Armada 37x documents do not give limits for this other than
4097 * it being an 8-bit register. */
4098 if (eee->tx_lpi_enabled &&
4099 (eee->tx_lpi_timer < 0 || eee->tx_lpi_timer > 255))
4102 lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0);
4103 lpi_ctl0 &= ~(0xff << 8);
4104 lpi_ctl0 |= eee->tx_lpi_timer << 8;
4105 mvreg_write(pp, MVNETA_LPI_CTRL_0, lpi_ctl0);
4107 pp->eee_enabled = eee->eee_enabled;
4108 pp->tx_lpi_enabled = eee->tx_lpi_enabled;
4110 mvneta_set_eee(pp, eee->tx_lpi_enabled && eee->eee_enabled);
4112 return phylink_ethtool_set_eee(pp->phylink, eee);
4115 static const struct net_device_ops mvneta_netdev_ops = {
4116 .ndo_open = mvneta_open,
4117 .ndo_stop = mvneta_stop,
4118 .ndo_start_xmit = mvneta_tx,
4119 .ndo_set_rx_mode = mvneta_set_rx_mode,
4120 .ndo_set_mac_address = mvneta_set_mac_addr,
4121 .ndo_change_mtu = mvneta_change_mtu,
4122 .ndo_fix_features = mvneta_fix_features,
4123 .ndo_get_stats64 = mvneta_get_stats64,
4124 .ndo_do_ioctl = mvneta_ioctl,
4127 static const struct ethtool_ops mvneta_eth_tool_ops = {
4128 .nway_reset = mvneta_ethtool_nway_reset,
4129 .get_link = ethtool_op_get_link,
4130 .set_coalesce = mvneta_ethtool_set_coalesce,
4131 .get_coalesce = mvneta_ethtool_get_coalesce,
4132 .get_drvinfo = mvneta_ethtool_get_drvinfo,
4133 .get_ringparam = mvneta_ethtool_get_ringparam,
4134 .set_ringparam = mvneta_ethtool_set_ringparam,
4135 .get_pauseparam = mvneta_ethtool_get_pauseparam,
4136 .set_pauseparam = mvneta_ethtool_set_pauseparam,
4137 .get_strings = mvneta_ethtool_get_strings,
4138 .get_ethtool_stats = mvneta_ethtool_get_stats,
4139 .get_sset_count = mvneta_ethtool_get_sset_count,
4140 .get_rxfh_indir_size = mvneta_ethtool_get_rxfh_indir_size,
4141 .get_rxnfc = mvneta_ethtool_get_rxnfc,
4142 .get_rxfh = mvneta_ethtool_get_rxfh,
4143 .set_rxfh = mvneta_ethtool_set_rxfh,
4144 .get_link_ksettings = mvneta_ethtool_get_link_ksettings,
4145 .set_link_ksettings = mvneta_ethtool_set_link_ksettings,
4146 .get_wol = mvneta_ethtool_get_wol,
4147 .set_wol = mvneta_ethtool_set_wol,
4148 .get_eee = mvneta_ethtool_get_eee,
4149 .set_eee = mvneta_ethtool_set_eee,
4153 static int mvneta_init(struct device *dev, struct mvneta_port *pp)
4158 mvneta_port_disable(pp);
4160 /* Set port default values */
4161 mvneta_defaults_set(pp);
4163 pp->txqs = devm_kcalloc(dev, txq_number, sizeof(*pp->txqs), GFP_KERNEL);
4167 /* Initialize TX descriptor rings */
4168 for (queue = 0; queue < txq_number; queue++) {
4169 struct mvneta_tx_queue *txq = &pp->txqs[queue];
4171 txq->size = pp->tx_ring_size;
4172 txq->done_pkts_coal = MVNETA_TXDONE_COAL_PKTS;
4175 pp->rxqs = devm_kcalloc(dev, rxq_number, sizeof(*pp->rxqs), GFP_KERNEL);
4179 /* Create Rx descriptor rings */
4180 for (queue = 0; queue < rxq_number; queue++) {
4181 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
4183 rxq->size = pp->rx_ring_size;
4184 rxq->pkts_coal = MVNETA_RX_COAL_PKTS;
4185 rxq->time_coal = MVNETA_RX_COAL_USEC;
4187 = devm_kmalloc_array(pp->dev->dev.parent,
4189 sizeof(*rxq->buf_virt_addr),
4191 if (!rxq->buf_virt_addr)
4198 /* platform glue : initialize decoding windows */
4199 static void mvneta_conf_mbus_windows(struct mvneta_port *pp,
4200 const struct mbus_dram_target_info *dram)
4206 for (i = 0; i < 6; i++) {
4207 mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
4208 mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
4211 mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
4218 for (i = 0; i < dram->num_cs; i++) {
4219 const struct mbus_dram_window *cs = dram->cs + i;
4221 mvreg_write(pp, MVNETA_WIN_BASE(i),
4222 (cs->base & 0xffff0000) |
4223 (cs->mbus_attr << 8) |
4224 dram->mbus_dram_target_id);
4226 mvreg_write(pp, MVNETA_WIN_SIZE(i),
4227 (cs->size - 1) & 0xffff0000);
4229 win_enable &= ~(1 << i);
4230 win_protect |= 3 << (2 * i);
4233 /* For Armada3700 open default 4GB Mbus window, leaving
4234 * arbitration of target/attribute to a different layer
4237 mvreg_write(pp, MVNETA_WIN_SIZE(0), 0xffff0000);
4238 win_enable &= ~BIT(0);
4242 mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
4243 mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect);
4246 /* Power up the port */
4247 static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode)
4249 /* MAC Cause register should be cleared */
4250 mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0);
4252 if (phy_mode == PHY_INTERFACE_MODE_QSGMII)
4253 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO);
4254 else if (phy_mode == PHY_INTERFACE_MODE_SGMII ||
4255 phy_mode == PHY_INTERFACE_MODE_1000BASEX)
4256 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO);
4257 else if (!phy_interface_mode_is_rgmii(phy_mode))
4263 /* Device initialization routine */
4264 static int mvneta_probe(struct platform_device *pdev)
4266 struct resource *res;
4267 struct device_node *dn = pdev->dev.of_node;
4268 struct device_node *bm_node;
4269 struct mvneta_port *pp;
4270 struct net_device *dev;
4271 struct phylink *phylink;
4272 const char *dt_mac_addr;
4273 char hw_mac_addr[ETH_ALEN];
4274 const char *mac_from;
4280 dev = alloc_etherdev_mqs(sizeof(struct mvneta_port), txq_number, rxq_number);
4284 dev->irq = irq_of_parse_and_map(dn, 0);
4285 if (dev->irq == 0) {
4287 goto err_free_netdev;
4290 phy_mode = of_get_phy_mode(dn);
4292 dev_err(&pdev->dev, "incorrect phy-mode\n");
4297 phylink = phylink_create(dev, pdev->dev.fwnode, phy_mode,
4298 &mvneta_phylink_ops);
4299 if (IS_ERR(phylink)) {
4300 err = PTR_ERR(phylink);
4304 dev->tx_queue_len = MVNETA_MAX_TXD;
4305 dev->watchdog_timeo = 5 * HZ;
4306 dev->netdev_ops = &mvneta_netdev_ops;
4308 dev->ethtool_ops = &mvneta_eth_tool_ops;
4310 pp = netdev_priv(dev);
4311 spin_lock_init(&pp->lock);
4312 pp->phylink = phylink;
4313 pp->phy_interface = phy_mode;
4316 pp->rxq_def = rxq_def;
4318 /* Set RX packet offset correction for platforms, whose
4319 * NET_SKB_PAD, exceeds 64B. It should be 64B for 64-bit
4320 * platforms and 0B for 32-bit ones.
4322 pp->rx_offset_correction =
4323 max(0, NET_SKB_PAD - MVNETA_RX_PKT_OFFSET_CORRECTION);
4325 pp->indir[0] = rxq_def;
4327 /* Get special SoC configurations */
4328 if (of_device_is_compatible(dn, "marvell,armada-3700-neta"))
4329 pp->neta_armada3700 = true;
4331 pp->clk = devm_clk_get(&pdev->dev, "core");
4332 if (IS_ERR(pp->clk))
4333 pp->clk = devm_clk_get(&pdev->dev, NULL);
4334 if (IS_ERR(pp->clk)) {
4335 err = PTR_ERR(pp->clk);
4336 goto err_free_phylink;
4339 clk_prepare_enable(pp->clk);
4341 pp->clk_bus = devm_clk_get(&pdev->dev, "bus");
4342 if (!IS_ERR(pp->clk_bus))
4343 clk_prepare_enable(pp->clk_bus);
4345 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4346 pp->base = devm_ioremap_resource(&pdev->dev, res);
4347 if (IS_ERR(pp->base)) {
4348 err = PTR_ERR(pp->base);
4352 /* Alloc per-cpu port structure */
4353 pp->ports = alloc_percpu(struct mvneta_pcpu_port);
4359 /* Alloc per-cpu stats */
4360 pp->stats = netdev_alloc_pcpu_stats(struct mvneta_pcpu_stats);
4363 goto err_free_ports;
4366 dt_mac_addr = of_get_mac_address(dn);
4368 mac_from = "device tree";
4369 memcpy(dev->dev_addr, dt_mac_addr, ETH_ALEN);
4371 mvneta_get_mac_addr(pp, hw_mac_addr);
4372 if (is_valid_ether_addr(hw_mac_addr)) {
4373 mac_from = "hardware";
4374 memcpy(dev->dev_addr, hw_mac_addr, ETH_ALEN);
4376 mac_from = "random";
4377 eth_hw_addr_random(dev);
4381 if (!of_property_read_u32(dn, "tx-csum-limit", &tx_csum_limit)) {
4382 if (tx_csum_limit < 0 ||
4383 tx_csum_limit > MVNETA_TX_CSUM_MAX_SIZE) {
4384 tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE;
4385 dev_info(&pdev->dev,
4386 "Wrong TX csum limit in DT, set to %dB\n",
4387 MVNETA_TX_CSUM_DEF_SIZE);
4389 } else if (of_device_is_compatible(dn, "marvell,armada-370-neta")) {
4390 tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE;
4392 tx_csum_limit = MVNETA_TX_CSUM_MAX_SIZE;
4395 pp->tx_csum_limit = tx_csum_limit;
4397 pp->dram_target_info = mv_mbus_dram_info();
4398 /* Armada3700 requires setting default configuration of Mbus
4399 * windows, however without using filled mbus_dram_target_info
4402 if (pp->dram_target_info || pp->neta_armada3700)
4403 mvneta_conf_mbus_windows(pp, pp->dram_target_info);
4405 pp->tx_ring_size = MVNETA_MAX_TXD;
4406 pp->rx_ring_size = MVNETA_MAX_RXD;
4409 SET_NETDEV_DEV(dev, &pdev->dev);
4411 pp->id = global_port_id++;
4413 /* Obtain access to BM resources if enabled and already initialized */
4414 bm_node = of_parse_phandle(dn, "buffer-manager", 0);
4415 if (bm_node && bm_node->data) {
4416 pp->bm_priv = bm_node->data;
4417 err = mvneta_bm_port_init(pdev, pp);
4419 dev_info(&pdev->dev, "use SW buffer management\n");
4423 of_node_put(bm_node);
4425 err = mvneta_init(&pdev->dev, pp);
4429 err = mvneta_port_power_up(pp, phy_mode);
4431 dev_err(&pdev->dev, "can't power up port\n");
4435 /* Armada3700 network controller does not support per-cpu
4436 * operation, so only single NAPI should be initialized.
4438 if (pp->neta_armada3700) {
4439 netif_napi_add(dev, &pp->napi, mvneta_poll, NAPI_POLL_WEIGHT);
4441 for_each_present_cpu(cpu) {
4442 struct mvneta_pcpu_port *port =
4443 per_cpu_ptr(pp->ports, cpu);
4445 netif_napi_add(dev, &port->napi, mvneta_poll,
4451 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_TSO;
4452 dev->hw_features |= dev->features;
4453 dev->vlan_features |= dev->features;
4454 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
4455 dev->gso_max_segs = MVNETA_MAX_TSO_SEGS;
4457 /* MTU range: 68 - 9676 */
4458 dev->min_mtu = ETH_MIN_MTU;
4459 /* 9676 == 9700 - 20 and rounding to 8 */
4460 dev->max_mtu = 9676;
4462 err = register_netdev(dev);
4464 dev_err(&pdev->dev, "failed to register\n");
4465 goto err_free_stats;
4468 netdev_info(dev, "Using %s mac address %pM\n", mac_from,
4471 platform_set_drvdata(pdev, pp->dev);
4476 unregister_netdev(dev);
4478 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id);
4479 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short,
4483 free_percpu(pp->stats);
4485 free_percpu(pp->ports);
4487 clk_disable_unprepare(pp->clk_bus);
4488 clk_disable_unprepare(pp->clk);
4491 phylink_destroy(pp->phylink);
4493 irq_dispose_mapping(dev->irq);
4499 /* Device removal routine */
4500 static int mvneta_remove(struct platform_device *pdev)
4502 struct net_device *dev = platform_get_drvdata(pdev);
4503 struct mvneta_port *pp = netdev_priv(dev);
4505 unregister_netdev(dev);
4506 clk_disable_unprepare(pp->clk_bus);
4507 clk_disable_unprepare(pp->clk);
4508 free_percpu(pp->ports);
4509 free_percpu(pp->stats);
4510 irq_dispose_mapping(dev->irq);
4511 phylink_destroy(pp->phylink);
4515 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id);
4516 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short,
4523 #ifdef CONFIG_PM_SLEEP
4524 static int mvneta_suspend(struct device *device)
4526 struct net_device *dev = dev_get_drvdata(device);
4527 struct mvneta_port *pp = netdev_priv(dev);
4530 if (netif_running(dev))
4533 netif_device_detach(dev);
4534 clk_disable_unprepare(pp->clk_bus);
4535 clk_disable_unprepare(pp->clk);
4539 static int mvneta_resume(struct device *device)
4541 struct platform_device *pdev = to_platform_device(device);
4542 struct net_device *dev = dev_get_drvdata(device);
4543 struct mvneta_port *pp = netdev_priv(dev);
4546 clk_prepare_enable(pp->clk);
4547 if (!IS_ERR(pp->clk_bus))
4548 clk_prepare_enable(pp->clk_bus);
4549 if (pp->dram_target_info || pp->neta_armada3700)
4550 mvneta_conf_mbus_windows(pp, pp->dram_target_info);
4552 err = mvneta_bm_port_init(pdev, pp);
4554 dev_info(&pdev->dev, "use SW buffer management\n");
4558 mvneta_defaults_set(pp);
4559 err = mvneta_port_power_up(pp, pp->phy_interface);
4561 dev_err(device, "can't power up port\n");
4565 netif_device_attach(dev);
4567 if (netif_running(dev)) {
4569 mvneta_set_rx_mode(dev);
4577 static SIMPLE_DEV_PM_OPS(mvneta_pm_ops, mvneta_suspend, mvneta_resume);
4579 static const struct of_device_id mvneta_match[] = {
4580 { .compatible = "marvell,armada-370-neta" },
4581 { .compatible = "marvell,armada-xp-neta" },
4582 { .compatible = "marvell,armada-3700-neta" },
4585 MODULE_DEVICE_TABLE(of, mvneta_match);
4587 static struct platform_driver mvneta_driver = {
4588 .probe = mvneta_probe,
4589 .remove = mvneta_remove,
4591 .name = MVNETA_DRIVER_NAME,
4592 .of_match_table = mvneta_match,
4593 .pm = &mvneta_pm_ops,
4597 static int __init mvneta_driver_init(void)
4601 ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, "net/mvmeta:online",
4603 mvneta_cpu_down_prepare);
4606 online_hpstate = ret;
4607 ret = cpuhp_setup_state_multi(CPUHP_NET_MVNETA_DEAD, "net/mvneta:dead",
4608 NULL, mvneta_cpu_dead);
4612 ret = platform_driver_register(&mvneta_driver);
4618 cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD);
4620 cpuhp_remove_multi_state(online_hpstate);
4624 module_init(mvneta_driver_init);
4626 static void __exit mvneta_driver_exit(void)
4628 platform_driver_unregister(&mvneta_driver);
4629 cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD);
4630 cpuhp_remove_multi_state(online_hpstate);
4632 module_exit(mvneta_driver_exit);
4634 MODULE_DESCRIPTION("Marvell NETA Ethernet Driver - www.marvell.com");
4635 MODULE_AUTHOR("Rami Rosen <rosenr@marvell.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
4636 MODULE_LICENSE("GPL");
4638 module_param(rxq_number, int, 0444);
4639 module_param(txq_number, int, 0444);
4641 module_param(rxq_def, int, 0444);
4642 module_param(rx_copybreak, int, 0644);