2 * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs.
4 * Copyright (C) 2012 Marvell
6 * Rami Rosen <rosenr@marvell.com>
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
14 #include <linux/clk.h>
15 #include <linux/cpu.h>
16 #include <linux/etherdevice.h>
17 #include <linux/if_vlan.h>
18 #include <linux/inetdevice.h>
19 #include <linux/interrupt.h>
21 #include <linux/kernel.h>
22 #include <linux/mbus.h>
23 #include <linux/module.h>
24 #include <linux/netdevice.h>
26 #include <linux/of_address.h>
27 #include <linux/of_irq.h>
28 #include <linux/of_mdio.h>
29 #include <linux/of_net.h>
30 #include <linux/phy/phy.h>
31 #include <linux/phy.h>
32 #include <linux/phylink.h>
33 #include <linux/platform_device.h>
34 #include <linux/skbuff.h>
36 #include "mvneta_bm.h"
40 #include <net/page_pool.h>
41 #include <linux/bpf_trace.h>
44 #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2))
45 #define MVNETA_RXQ_HW_BUF_ALLOC BIT(0)
46 #define MVNETA_RXQ_SHORT_POOL_ID_SHIFT 4
47 #define MVNETA_RXQ_SHORT_POOL_ID_MASK 0x30
48 #define MVNETA_RXQ_LONG_POOL_ID_SHIFT 6
49 #define MVNETA_RXQ_LONG_POOL_ID_MASK 0xc0
50 #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8)
51 #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8)
52 #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2))
53 #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16)
54 #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2))
55 #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2))
56 #define MVNETA_RXQ_BUF_SIZE_SHIFT 19
57 #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19)
58 #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2))
59 #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff
60 #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2))
61 #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16
62 #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255
63 #define MVNETA_PORT_POOL_BUFFER_SZ_REG(pool) (0x1700 + ((pool) << 2))
64 #define MVNETA_PORT_POOL_BUFFER_SZ_SHIFT 3
65 #define MVNETA_PORT_POOL_BUFFER_SZ_MASK 0xfff8
66 #define MVNETA_PORT_RX_RESET 0x1cc0
67 #define MVNETA_PORT_RX_DMA_RESET BIT(0)
68 #define MVNETA_PHY_ADDR 0x2000
69 #define MVNETA_PHY_ADDR_MASK 0x1f
70 #define MVNETA_MBUS_RETRY 0x2010
71 #define MVNETA_UNIT_INTR_CAUSE 0x2080
72 #define MVNETA_UNIT_CONTROL 0x20B0
73 #define MVNETA_PHY_POLLING_ENABLE BIT(1)
74 #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3))
75 #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3))
76 #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2))
77 #define MVNETA_BASE_ADDR_ENABLE 0x2290
78 #define MVNETA_ACCESS_PROTECT_ENABLE 0x2294
79 #define MVNETA_PORT_CONFIG 0x2400
80 #define MVNETA_UNI_PROMISC_MODE BIT(0)
81 #define MVNETA_DEF_RXQ(q) ((q) << 1)
82 #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4)
83 #define MVNETA_TX_UNSET_ERR_SUM BIT(12)
84 #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16)
85 #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19)
86 #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22)
87 #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25)
88 #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \
89 MVNETA_DEF_RXQ_ARP(q) | \
90 MVNETA_DEF_RXQ_TCP(q) | \
91 MVNETA_DEF_RXQ_UDP(q) | \
92 MVNETA_DEF_RXQ_BPDU(q) | \
93 MVNETA_TX_UNSET_ERR_SUM | \
94 MVNETA_RX_CSUM_WITH_PSEUDO_HDR)
95 #define MVNETA_PORT_CONFIG_EXTEND 0x2404
96 #define MVNETA_MAC_ADDR_LOW 0x2414
97 #define MVNETA_MAC_ADDR_HIGH 0x2418
98 #define MVNETA_SDMA_CONFIG 0x241c
99 #define MVNETA_SDMA_BRST_SIZE_16 4
100 #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1)
101 #define MVNETA_RX_NO_DATA_SWAP BIT(4)
102 #define MVNETA_TX_NO_DATA_SWAP BIT(5)
103 #define MVNETA_DESC_SWAP BIT(6)
104 #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22)
105 #define MVNETA_PORT_STATUS 0x2444
106 #define MVNETA_TX_IN_PRGRS BIT(1)
107 #define MVNETA_TX_FIFO_EMPTY BIT(8)
108 #define MVNETA_RX_MIN_FRAME_SIZE 0x247c
109 /* Only exists on Armada XP and Armada 370 */
110 #define MVNETA_SERDES_CFG 0x24A0
111 #define MVNETA_SGMII_SERDES_PROTO 0x0cc7
112 #define MVNETA_QSGMII_SERDES_PROTO 0x0667
113 #define MVNETA_HSGMII_SERDES_PROTO 0x1107
114 #define MVNETA_TYPE_PRIO 0x24bc
115 #define MVNETA_FORCE_UNI BIT(21)
116 #define MVNETA_TXQ_CMD_1 0x24e4
117 #define MVNETA_TXQ_CMD 0x2448
118 #define MVNETA_TXQ_DISABLE_SHIFT 8
119 #define MVNETA_TXQ_ENABLE_MASK 0x000000ff
120 #define MVNETA_RX_DISCARD_FRAME_COUNT 0x2484
121 #define MVNETA_OVERRUN_FRAME_COUNT 0x2488
122 #define MVNETA_GMAC_CLOCK_DIVIDER 0x24f4
123 #define MVNETA_GMAC_1MS_CLOCK_ENABLE BIT(31)
124 #define MVNETA_ACC_MODE 0x2500
125 #define MVNETA_BM_ADDRESS 0x2504
126 #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2))
127 #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff
128 #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00
129 #define MVNETA_CPU_RXQ_ACCESS(rxq) BIT(rxq)
130 #define MVNETA_CPU_TXQ_ACCESS(txq) BIT(txq + 8)
131 #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2))
133 /* Exception Interrupt Port/Queue Cause register
135 * Their behavior depend of the mapping done using the PCPX2Q
136 * registers. For a given CPU if the bit associated to a queue is not
137 * set, then for the register a read from this CPU will always return
138 * 0 and a write won't do anything
141 #define MVNETA_INTR_NEW_CAUSE 0x25a0
142 #define MVNETA_INTR_NEW_MASK 0x25a4
144 /* bits 0..7 = TXQ SENT, one bit per queue.
145 * bits 8..15 = RXQ OCCUP, one bit per queue.
146 * bits 16..23 = RXQ FREE, one bit per queue.
147 * bit 29 = OLD_REG_SUM, see old reg ?
148 * bit 30 = TX_ERR_SUM, one bit for 4 ports
149 * bit 31 = MISC_SUM, one bit for 4 ports
151 #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0)
152 #define MVNETA_TX_INTR_MASK_ALL (0xff << 0)
153 #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8)
154 #define MVNETA_RX_INTR_MASK_ALL (0xff << 8)
155 #define MVNETA_MISCINTR_INTR_MASK BIT(31)
157 #define MVNETA_INTR_OLD_CAUSE 0x25a8
158 #define MVNETA_INTR_OLD_MASK 0x25ac
160 /* Data Path Port/Queue Cause Register */
161 #define MVNETA_INTR_MISC_CAUSE 0x25b0
162 #define MVNETA_INTR_MISC_MASK 0x25b4
164 #define MVNETA_CAUSE_PHY_STATUS_CHANGE BIT(0)
165 #define MVNETA_CAUSE_LINK_CHANGE BIT(1)
166 #define MVNETA_CAUSE_PTP BIT(4)
168 #define MVNETA_CAUSE_INTERNAL_ADDR_ERR BIT(7)
169 #define MVNETA_CAUSE_RX_OVERRUN BIT(8)
170 #define MVNETA_CAUSE_RX_CRC_ERROR BIT(9)
171 #define MVNETA_CAUSE_RX_LARGE_PKT BIT(10)
172 #define MVNETA_CAUSE_TX_UNDERUN BIT(11)
173 #define MVNETA_CAUSE_PRBS_ERR BIT(12)
174 #define MVNETA_CAUSE_PSC_SYNC_CHANGE BIT(13)
175 #define MVNETA_CAUSE_SERDES_SYNC_ERR BIT(14)
177 #define MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT 16
178 #define MVNETA_CAUSE_BMU_ALLOC_ERR_ALL_MASK (0xF << MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT)
179 #define MVNETA_CAUSE_BMU_ALLOC_ERR_MASK(pool) (1 << (MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT + (pool)))
181 #define MVNETA_CAUSE_TXQ_ERROR_SHIFT 24
182 #define MVNETA_CAUSE_TXQ_ERROR_ALL_MASK (0xFF << MVNETA_CAUSE_TXQ_ERROR_SHIFT)
183 #define MVNETA_CAUSE_TXQ_ERROR_MASK(q) (1 << (MVNETA_CAUSE_TXQ_ERROR_SHIFT + (q)))
185 #define MVNETA_INTR_ENABLE 0x25b8
186 #define MVNETA_TXQ_INTR_ENABLE_ALL_MASK 0x0000ff00
187 #define MVNETA_RXQ_INTR_ENABLE_ALL_MASK 0x000000ff
189 #define MVNETA_RXQ_CMD 0x2680
190 #define MVNETA_RXQ_DISABLE_SHIFT 8
191 #define MVNETA_RXQ_ENABLE_MASK 0x000000ff
192 #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4))
193 #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4))
194 #define MVNETA_GMAC_CTRL_0 0x2c00
195 #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2
196 #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc
197 #define MVNETA_GMAC0_PORT_1000BASE_X BIT(1)
198 #define MVNETA_GMAC0_PORT_ENABLE BIT(0)
199 #define MVNETA_GMAC_CTRL_2 0x2c08
200 #define MVNETA_GMAC2_INBAND_AN_ENABLE BIT(0)
201 #define MVNETA_GMAC2_PCS_ENABLE BIT(3)
202 #define MVNETA_GMAC2_PORT_RGMII BIT(4)
203 #define MVNETA_GMAC2_PORT_RESET BIT(6)
204 #define MVNETA_GMAC_STATUS 0x2c10
205 #define MVNETA_GMAC_LINK_UP BIT(0)
206 #define MVNETA_GMAC_SPEED_1000 BIT(1)
207 #define MVNETA_GMAC_SPEED_100 BIT(2)
208 #define MVNETA_GMAC_FULL_DUPLEX BIT(3)
209 #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4)
210 #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5)
211 #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6)
212 #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7)
213 #define MVNETA_GMAC_AN_COMPLETE BIT(11)
214 #define MVNETA_GMAC_SYNC_OK BIT(14)
215 #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c
216 #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0)
217 #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1)
218 #define MVNETA_GMAC_INBAND_AN_ENABLE BIT(2)
219 #define MVNETA_GMAC_AN_BYPASS_ENABLE BIT(3)
220 #define MVNETA_GMAC_INBAND_RESTART_AN BIT(4)
221 #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5)
222 #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6)
223 #define MVNETA_GMAC_AN_SPEED_EN BIT(7)
224 #define MVNETA_GMAC_CONFIG_FLOW_CTRL BIT(8)
225 #define MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL BIT(9)
226 #define MVNETA_GMAC_AN_FLOW_CTRL_EN BIT(11)
227 #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12)
228 #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13)
229 #define MVNETA_GMAC_CTRL_4 0x2c90
230 #define MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE BIT(1)
231 #define MVNETA_MIB_COUNTERS_BASE 0x3000
232 #define MVNETA_MIB_LATE_COLLISION 0x7c
233 #define MVNETA_DA_FILT_SPEC_MCAST 0x3400
234 #define MVNETA_DA_FILT_OTH_MCAST 0x3500
235 #define MVNETA_DA_FILT_UCAST_BASE 0x3600
236 #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2))
237 #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2))
238 #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000
239 #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16)
240 #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2))
241 #define MVNETA_TXQ_DEC_SENT_SHIFT 16
242 #define MVNETA_TXQ_DEC_SENT_MASK 0xff
243 #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2))
244 #define MVNETA_TXQ_SENT_DESC_SHIFT 16
245 #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000
246 #define MVNETA_PORT_TX_RESET 0x3cf0
247 #define MVNETA_PORT_TX_DMA_RESET BIT(0)
248 #define MVNETA_TX_MTU 0x3e0c
249 #define MVNETA_TX_TOKEN_SIZE 0x3e14
250 #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff
251 #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2))
252 #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff
254 #define MVNETA_LPI_CTRL_0 0x2cc0
255 #define MVNETA_LPI_CTRL_1 0x2cc4
256 #define MVNETA_LPI_REQUEST_ENABLE BIT(0)
257 #define MVNETA_LPI_CTRL_2 0x2cc8
258 #define MVNETA_LPI_STATUS 0x2ccc
260 #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
262 /* Descriptor ring Macros */
263 #define MVNETA_QUEUE_NEXT_DESC(q, index) \
264 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
266 /* Various constants */
269 #define MVNETA_TXDONE_COAL_PKTS 0 /* interrupt per packet */
270 #define MVNETA_RX_COAL_PKTS 32
271 #define MVNETA_RX_COAL_USEC 100
273 /* The two bytes Marvell header. Either contains a special value used
274 * by Marvell switches when a specific hardware mode is enabled (not
275 * supported by this driver) or is filled automatically by zeroes on
276 * the RX side. Those two bytes being at the front of the Ethernet
277 * header, they allow to have the IP header aligned on a 4 bytes
278 * boundary automatically: the hardware skips those two bytes on its
281 #define MVNETA_MH_SIZE 2
283 #define MVNETA_VLAN_TAG_LEN 4
285 #define MVNETA_TX_CSUM_DEF_SIZE 1600
286 #define MVNETA_TX_CSUM_MAX_SIZE 9800
287 #define MVNETA_ACC_MODE_EXT1 1
288 #define MVNETA_ACC_MODE_EXT2 2
290 #define MVNETA_MAX_DECODE_WIN 6
292 /* Timeout constants */
293 #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000
294 #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000
295 #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000
297 #define MVNETA_TX_MTU_MAX 0x3ffff
299 /* The RSS lookup table actually has 256 entries but we do not use
302 #define MVNETA_RSS_LU_TABLE_SIZE 1
304 /* Max number of Rx descriptors */
305 #define MVNETA_MAX_RXD 512
307 /* Max number of Tx descriptors */
308 #define MVNETA_MAX_TXD 1024
310 /* Max number of allowed TCP segments for software TSO */
311 #define MVNETA_MAX_TSO_SEGS 100
313 #define MVNETA_MAX_SKB_DESCS (MVNETA_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
315 /* descriptor aligned size */
316 #define MVNETA_DESC_ALIGNED_SIZE 32
318 /* Number of bytes to be taken into account by HW when putting incoming data
319 * to the buffers. It is needed in case NET_SKB_PAD exceeds maximum packet
320 * offset supported in MVNETA_RXQ_CONFIG_REG(q) registers.
322 #define MVNETA_RX_PKT_OFFSET_CORRECTION 64
324 #define MVNETA_RX_PKT_SIZE(mtu) \
325 ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \
326 ETH_HLEN + ETH_FCS_LEN, \
329 /* Driver assumes that the last 3 bits are 0 */
330 #define MVNETA_SKB_HEADROOM ALIGN(max(NET_SKB_PAD, XDP_PACKET_HEADROOM), 8)
331 #define MVNETA_SKB_PAD (SKB_DATA_ALIGN(sizeof(struct skb_shared_info) + \
332 MVNETA_SKB_HEADROOM))
333 #define MVNETA_SKB_SIZE(len) (SKB_DATA_ALIGN(len) + MVNETA_SKB_PAD)
334 #define MVNETA_MAX_RX_BUF_SIZE (PAGE_SIZE - MVNETA_SKB_PAD)
336 #define IS_TSO_HEADER(txq, addr) \
337 ((addr >= txq->tso_hdrs_phys) && \
338 (addr < txq->tso_hdrs_phys + txq->size * TSO_HEADER_SIZE))
340 #define MVNETA_RX_GET_BM_POOL_ID(rxd) \
341 (((rxd)->status & MVNETA_RXD_BM_POOL_MASK) >> MVNETA_RXD_BM_POOL_SHIFT)
344 ETHTOOL_STAT_EEE_WAKEUP,
345 ETHTOOL_STAT_SKB_ALLOC_ERR,
346 ETHTOOL_STAT_REFILL_ERR,
347 ETHTOOL_XDP_REDIRECT,
353 ETHTOOL_XDP_XMIT_ERR,
357 struct mvneta_statistic {
358 unsigned short offset;
360 const char name[ETH_GSTRING_LEN];
367 #define MVNETA_XDP_PASS 0
368 #define MVNETA_XDP_DROPPED BIT(0)
369 #define MVNETA_XDP_TX BIT(1)
370 #define MVNETA_XDP_REDIR BIT(2)
372 static const struct mvneta_statistic mvneta_statistics[] = {
373 { 0x3000, T_REG_64, "good_octets_received", },
374 { 0x3010, T_REG_32, "good_frames_received", },
375 { 0x3008, T_REG_32, "bad_octets_received", },
376 { 0x3014, T_REG_32, "bad_frames_received", },
377 { 0x3018, T_REG_32, "broadcast_frames_received", },
378 { 0x301c, T_REG_32, "multicast_frames_received", },
379 { 0x3050, T_REG_32, "unrec_mac_control_received", },
380 { 0x3058, T_REG_32, "good_fc_received", },
381 { 0x305c, T_REG_32, "bad_fc_received", },
382 { 0x3060, T_REG_32, "undersize_received", },
383 { 0x3064, T_REG_32, "fragments_received", },
384 { 0x3068, T_REG_32, "oversize_received", },
385 { 0x306c, T_REG_32, "jabber_received", },
386 { 0x3070, T_REG_32, "mac_receive_error", },
387 { 0x3074, T_REG_32, "bad_crc_event", },
388 { 0x3078, T_REG_32, "collision", },
389 { 0x307c, T_REG_32, "late_collision", },
390 { 0x2484, T_REG_32, "rx_discard", },
391 { 0x2488, T_REG_32, "rx_overrun", },
392 { 0x3020, T_REG_32, "frames_64_octets", },
393 { 0x3024, T_REG_32, "frames_65_to_127_octets", },
394 { 0x3028, T_REG_32, "frames_128_to_255_octets", },
395 { 0x302c, T_REG_32, "frames_256_to_511_octets", },
396 { 0x3030, T_REG_32, "frames_512_to_1023_octets", },
397 { 0x3034, T_REG_32, "frames_1024_to_max_octets", },
398 { 0x3038, T_REG_64, "good_octets_sent", },
399 { 0x3040, T_REG_32, "good_frames_sent", },
400 { 0x3044, T_REG_32, "excessive_collision", },
401 { 0x3048, T_REG_32, "multicast_frames_sent", },
402 { 0x304c, T_REG_32, "broadcast_frames_sent", },
403 { 0x3054, T_REG_32, "fc_sent", },
404 { 0x300c, T_REG_32, "internal_mac_transmit_err", },
405 { ETHTOOL_STAT_EEE_WAKEUP, T_SW, "eee_wakeup_errors", },
406 { ETHTOOL_STAT_SKB_ALLOC_ERR, T_SW, "skb_alloc_errors", },
407 { ETHTOOL_STAT_REFILL_ERR, T_SW, "refill_errors", },
408 { ETHTOOL_XDP_REDIRECT, T_SW, "rx_xdp_redirect", },
409 { ETHTOOL_XDP_PASS, T_SW, "rx_xdp_pass", },
410 { ETHTOOL_XDP_DROP, T_SW, "rx_xdp_drop", },
411 { ETHTOOL_XDP_TX, T_SW, "rx_xdp_tx", },
412 { ETHTOOL_XDP_TX_ERR, T_SW, "rx_xdp_tx_errors", },
413 { ETHTOOL_XDP_XMIT, T_SW, "tx_xdp_xmit", },
414 { ETHTOOL_XDP_XMIT_ERR, T_SW, "tx_xdp_xmit_errors", },
417 struct mvneta_stats {
432 struct mvneta_ethtool_stats {
433 struct mvneta_stats ps;
438 struct mvneta_pcpu_stats {
439 struct u64_stats_sync syncp;
441 struct mvneta_ethtool_stats es;
446 struct mvneta_pcpu_port {
447 /* Pointer to the shared port */
448 struct mvneta_port *pp;
450 /* Pointer to the CPU-local NAPI struct */
451 struct napi_struct napi;
453 /* Cause of the previous interrupt */
463 struct mvneta_pcpu_port __percpu *ports;
464 struct mvneta_pcpu_stats __percpu *stats;
470 struct mvneta_rx_queue *rxqs;
471 struct mvneta_tx_queue *txqs;
472 struct net_device *dev;
473 struct hlist_node node_online;
474 struct hlist_node node_dead;
476 /* Protect the access to the percpu interrupt registers,
477 * ensuring that the configuration remains coherent.
483 struct napi_struct napi;
485 struct bpf_prog *xdp_prog;
495 phy_interface_t phy_interface;
496 struct device_node *dn;
497 unsigned int tx_csum_limit;
498 struct phylink *phylink;
499 struct phylink_config phylink_config;
502 struct mvneta_bm *bm_priv;
503 struct mvneta_bm_pool *pool_long;
504 struct mvneta_bm_pool *pool_short;
511 u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)];
513 u32 indir[MVNETA_RSS_LU_TABLE_SIZE];
515 /* Flags for special SoC configurations */
516 bool neta_armada3700;
517 u16 rx_offset_correction;
518 const struct mbus_dram_target_info *dram_target_info;
521 /* The mvneta_tx_desc and mvneta_rx_desc structures describe the
522 * layout of the transmit and reception DMA descriptors, and their
523 * layout is therefore defined by the hardware design
526 #define MVNETA_TX_L3_OFF_SHIFT 0
527 #define MVNETA_TX_IP_HLEN_SHIFT 8
528 #define MVNETA_TX_L4_UDP BIT(16)
529 #define MVNETA_TX_L3_IP6 BIT(17)
530 #define MVNETA_TXD_IP_CSUM BIT(18)
531 #define MVNETA_TXD_Z_PAD BIT(19)
532 #define MVNETA_TXD_L_DESC BIT(20)
533 #define MVNETA_TXD_F_DESC BIT(21)
534 #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \
535 MVNETA_TXD_L_DESC | \
537 #define MVNETA_TX_L4_CSUM_FULL BIT(30)
538 #define MVNETA_TX_L4_CSUM_NOT BIT(31)
540 #define MVNETA_RXD_ERR_CRC 0x0
541 #define MVNETA_RXD_BM_POOL_SHIFT 13
542 #define MVNETA_RXD_BM_POOL_MASK (BIT(13) | BIT(14))
543 #define MVNETA_RXD_ERR_SUMMARY BIT(16)
544 #define MVNETA_RXD_ERR_OVERRUN BIT(17)
545 #define MVNETA_RXD_ERR_LEN BIT(18)
546 #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18))
547 #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18))
548 #define MVNETA_RXD_L3_IP4 BIT(25)
549 #define MVNETA_RXD_LAST_DESC BIT(26)
550 #define MVNETA_RXD_FIRST_DESC BIT(27)
551 #define MVNETA_RXD_FIRST_LAST_DESC (MVNETA_RXD_FIRST_DESC | \
552 MVNETA_RXD_LAST_DESC)
553 #define MVNETA_RXD_L4_CSUM_OK BIT(30)
555 #if defined(__LITTLE_ENDIAN)
556 struct mvneta_tx_desc {
557 u32 command; /* Options used by HW for packet transmitting.*/
558 u16 reserved1; /* csum_l4 (for future use) */
559 u16 data_size; /* Data size of transmitted packet in bytes */
560 u32 buf_phys_addr; /* Physical addr of transmitted buffer */
561 u32 reserved2; /* hw_cmd - (for future use, PMT) */
562 u32 reserved3[4]; /* Reserved - (for future use) */
565 struct mvneta_rx_desc {
566 u32 status; /* Info about received packet */
567 u16 reserved1; /* pnc_info - (for future use, PnC) */
568 u16 data_size; /* Size of received packet in bytes */
570 u32 buf_phys_addr; /* Physical address of the buffer */
571 u32 reserved2; /* pnc_flow_id (for future use, PnC) */
573 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
574 u16 reserved3; /* prefetch_cmd, for future use */
575 u16 reserved4; /* csum_l4 - (for future use, PnC) */
577 u32 reserved5; /* pnc_extra PnC (for future use, PnC) */
578 u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */
581 struct mvneta_tx_desc {
582 u16 data_size; /* Data size of transmitted packet in bytes */
583 u16 reserved1; /* csum_l4 (for future use) */
584 u32 command; /* Options used by HW for packet transmitting.*/
585 u32 reserved2; /* hw_cmd - (for future use, PMT) */
586 u32 buf_phys_addr; /* Physical addr of transmitted buffer */
587 u32 reserved3[4]; /* Reserved - (for future use) */
590 struct mvneta_rx_desc {
591 u16 data_size; /* Size of received packet in bytes */
592 u16 reserved1; /* pnc_info - (for future use, PnC) */
593 u32 status; /* Info about received packet */
595 u32 reserved2; /* pnc_flow_id (for future use, PnC) */
596 u32 buf_phys_addr; /* Physical address of the buffer */
598 u16 reserved4; /* csum_l4 - (for future use, PnC) */
599 u16 reserved3; /* prefetch_cmd, for future use */
600 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
602 u32 reserved5; /* pnc_extra PnC (for future use, PnC) */
603 u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */
607 enum mvneta_tx_buf_type {
613 struct mvneta_tx_buf {
614 enum mvneta_tx_buf_type type;
616 struct xdp_frame *xdpf;
621 struct mvneta_tx_queue {
622 /* Number of this TX queue, in the range 0-7 */
625 /* Number of TX DMA descriptors in the descriptor ring */
628 /* Number of currently used TX DMA descriptor in the
633 int tx_stop_threshold;
634 int tx_wake_threshold;
636 /* Array of transmitted buffers */
637 struct mvneta_tx_buf *buf;
639 /* Index of last TX DMA descriptor that was inserted */
642 /* Index of the TX DMA descriptor to be cleaned up */
647 /* Virtual address of the TX DMA descriptors array */
648 struct mvneta_tx_desc *descs;
650 /* DMA address of the TX DMA descriptors array */
651 dma_addr_t descs_phys;
653 /* Index of the last TX DMA descriptor */
656 /* Index of the next TX DMA descriptor to process */
657 int next_desc_to_proc;
659 /* DMA buffers for TSO headers */
662 /* DMA address of TSO headers */
663 dma_addr_t tso_hdrs_phys;
665 /* Affinity mask for CPUs*/
666 cpumask_t affinity_mask;
669 struct mvneta_rx_queue {
670 /* rx queue number, in the range 0-7 */
673 /* num of rx descriptors in the rx descriptor ring */
680 struct page_pool *page_pool;
681 struct xdp_rxq_info xdp_rxq;
683 /* Virtual address of the RX buffer */
684 void **buf_virt_addr;
686 /* Virtual address of the RX DMA descriptors array */
687 struct mvneta_rx_desc *descs;
689 /* DMA address of the RX DMA descriptors array */
690 dma_addr_t descs_phys;
692 /* Index of the last RX DMA descriptor */
695 /* Index of the next RX DMA descriptor to process */
696 int next_desc_to_proc;
698 /* Index of first RX DMA descriptor to refill */
702 /* pointer to uncomplete skb buffer */
707 static enum cpuhp_state online_hpstate;
708 /* The hardware supports eight (8) rx queues, but we are only allowing
709 * the first one to be used. Therefore, let's just allocate one queue.
711 static int rxq_number = 8;
712 static int txq_number = 8;
716 static int rx_copybreak __read_mostly = 256;
718 /* HW BM need that each port be identify by a unique ID */
719 static int global_port_id;
721 #define MVNETA_DRIVER_NAME "mvneta"
722 #define MVNETA_DRIVER_VERSION "1.0"
724 /* Utility/helper methods */
726 /* Write helper method */
727 static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data)
729 writel(data, pp->base + offset);
732 /* Read helper method */
733 static u32 mvreg_read(struct mvneta_port *pp, u32 offset)
735 return readl(pp->base + offset);
738 /* Increment txq get counter */
739 static void mvneta_txq_inc_get(struct mvneta_tx_queue *txq)
741 txq->txq_get_index++;
742 if (txq->txq_get_index == txq->size)
743 txq->txq_get_index = 0;
746 /* Increment txq put counter */
747 static void mvneta_txq_inc_put(struct mvneta_tx_queue *txq)
749 txq->txq_put_index++;
750 if (txq->txq_put_index == txq->size)
751 txq->txq_put_index = 0;
755 /* Clear all MIB counters */
756 static void mvneta_mib_counters_clear(struct mvneta_port *pp)
761 /* Perform dummy reads from MIB counters */
762 for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4)
763 dummy = mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i));
764 dummy = mvreg_read(pp, MVNETA_RX_DISCARD_FRAME_COUNT);
765 dummy = mvreg_read(pp, MVNETA_OVERRUN_FRAME_COUNT);
768 /* Get System Network Statistics */
770 mvneta_get_stats64(struct net_device *dev,
771 struct rtnl_link_stats64 *stats)
773 struct mvneta_port *pp = netdev_priv(dev);
777 for_each_possible_cpu(cpu) {
778 struct mvneta_pcpu_stats *cpu_stats;
786 cpu_stats = per_cpu_ptr(pp->stats, cpu);
788 start = u64_stats_fetch_begin_irq(&cpu_stats->syncp);
789 rx_packets = cpu_stats->es.ps.rx_packets;
790 rx_bytes = cpu_stats->es.ps.rx_bytes;
791 rx_dropped = cpu_stats->rx_dropped;
792 rx_errors = cpu_stats->rx_errors;
793 tx_packets = cpu_stats->es.ps.tx_packets;
794 tx_bytes = cpu_stats->es.ps.tx_bytes;
795 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start));
797 stats->rx_packets += rx_packets;
798 stats->rx_bytes += rx_bytes;
799 stats->rx_dropped += rx_dropped;
800 stats->rx_errors += rx_errors;
801 stats->tx_packets += tx_packets;
802 stats->tx_bytes += tx_bytes;
805 stats->tx_dropped = dev->stats.tx_dropped;
808 /* Rx descriptors helper methods */
810 /* Checks whether the RX descriptor having this status is both the first
811 * and the last descriptor for the RX packet. Each RX packet is currently
812 * received through a single RX descriptor, so not having each RX
813 * descriptor with its first and last bits set is an error
815 static int mvneta_rxq_desc_is_first_last(u32 status)
817 return (status & MVNETA_RXD_FIRST_LAST_DESC) ==
818 MVNETA_RXD_FIRST_LAST_DESC;
821 /* Add number of descriptors ready to receive new packets */
822 static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp,
823 struct mvneta_rx_queue *rxq,
826 /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can
829 while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) {
830 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
831 (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX <<
832 MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
833 ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX;
836 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
837 (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
840 /* Get number of RX descriptors occupied by received packets */
841 static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp,
842 struct mvneta_rx_queue *rxq)
846 val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id));
847 return val & MVNETA_RXQ_OCCUPIED_ALL_MASK;
850 /* Update num of rx desc called upon return from rx path or
851 * from mvneta_rxq_drop_pkts().
853 static void mvneta_rxq_desc_num_update(struct mvneta_port *pp,
854 struct mvneta_rx_queue *rxq,
855 int rx_done, int rx_filled)
859 if ((rx_done <= 0xff) && (rx_filled <= 0xff)) {
861 (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT);
862 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
866 /* Only 255 descriptors can be added at once */
867 while ((rx_done > 0) || (rx_filled > 0)) {
868 if (rx_done <= 0xff) {
875 if (rx_filled <= 0xff) {
876 val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
879 val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
882 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
886 /* Get pointer to next RX descriptor to be processed by SW */
887 static struct mvneta_rx_desc *
888 mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq)
890 int rx_desc = rxq->next_desc_to_proc;
892 rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc);
893 prefetch(rxq->descs + rxq->next_desc_to_proc);
894 return rxq->descs + rx_desc;
897 /* Change maximum receive size of the port. */
898 static void mvneta_max_rx_size_set(struct mvneta_port *pp, int max_rx_size)
902 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
903 val &= ~MVNETA_GMAC_MAX_RX_SIZE_MASK;
904 val |= ((max_rx_size - MVNETA_MH_SIZE) / 2) <<
905 MVNETA_GMAC_MAX_RX_SIZE_SHIFT;
906 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
910 /* Set rx queue offset */
911 static void mvneta_rxq_offset_set(struct mvneta_port *pp,
912 struct mvneta_rx_queue *rxq,
917 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
918 val &= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK;
921 val |= MVNETA_RXQ_PKT_OFFSET_MASK(offset >> 3);
922 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
926 /* Tx descriptors helper methods */
928 /* Update HW with number of TX descriptors to be sent */
929 static void mvneta_txq_pend_desc_add(struct mvneta_port *pp,
930 struct mvneta_tx_queue *txq,
935 pend_desc += txq->pending;
937 /* Only 255 Tx descriptors can be added at once */
939 val = min(pend_desc, 255);
940 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
942 } while (pend_desc > 0);
946 /* Get pointer to next TX descriptor to be processed (send) by HW */
947 static struct mvneta_tx_desc *
948 mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq)
950 int tx_desc = txq->next_desc_to_proc;
952 txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc);
953 return txq->descs + tx_desc;
956 /* Release the last allocated TX descriptor. Useful to handle DMA
957 * mapping failures in the TX path.
959 static void mvneta_txq_desc_put(struct mvneta_tx_queue *txq)
961 if (txq->next_desc_to_proc == 0)
962 txq->next_desc_to_proc = txq->last_desc - 1;
964 txq->next_desc_to_proc--;
967 /* Set rxq buf size */
968 static void mvneta_rxq_buf_size_set(struct mvneta_port *pp,
969 struct mvneta_rx_queue *rxq,
974 val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id));
976 val &= ~MVNETA_RXQ_BUF_SIZE_MASK;
977 val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT);
979 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val);
982 /* Disable buffer management (BM) */
983 static void mvneta_rxq_bm_disable(struct mvneta_port *pp,
984 struct mvneta_rx_queue *rxq)
988 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
989 val &= ~MVNETA_RXQ_HW_BUF_ALLOC;
990 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
993 /* Enable buffer management (BM) */
994 static void mvneta_rxq_bm_enable(struct mvneta_port *pp,
995 struct mvneta_rx_queue *rxq)
999 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
1000 val |= MVNETA_RXQ_HW_BUF_ALLOC;
1001 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
1004 /* Notify HW about port's assignment of pool for bigger packets */
1005 static void mvneta_rxq_long_pool_set(struct mvneta_port *pp,
1006 struct mvneta_rx_queue *rxq)
1010 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
1011 val &= ~MVNETA_RXQ_LONG_POOL_ID_MASK;
1012 val |= (pp->pool_long->id << MVNETA_RXQ_LONG_POOL_ID_SHIFT);
1014 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
1017 /* Notify HW about port's assignment of pool for smaller packets */
1018 static void mvneta_rxq_short_pool_set(struct mvneta_port *pp,
1019 struct mvneta_rx_queue *rxq)
1023 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
1024 val &= ~MVNETA_RXQ_SHORT_POOL_ID_MASK;
1025 val |= (pp->pool_short->id << MVNETA_RXQ_SHORT_POOL_ID_SHIFT);
1027 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
1030 /* Set port's receive buffer size for assigned BM pool */
1031 static inline void mvneta_bm_pool_bufsize_set(struct mvneta_port *pp,
1037 if (!IS_ALIGNED(buf_size, 8)) {
1038 dev_warn(pp->dev->dev.parent,
1039 "illegal buf_size value %d, round to %d\n",
1040 buf_size, ALIGN(buf_size, 8));
1041 buf_size = ALIGN(buf_size, 8);
1044 val = mvreg_read(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id));
1045 val |= buf_size & MVNETA_PORT_POOL_BUFFER_SZ_MASK;
1046 mvreg_write(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id), val);
1049 /* Configure MBUS window in order to enable access BM internal SRAM */
1050 static int mvneta_mbus_io_win_set(struct mvneta_port *pp, u32 base, u32 wsize,
1053 u32 win_enable, win_protect;
1056 win_enable = mvreg_read(pp, MVNETA_BASE_ADDR_ENABLE);
1058 if (pp->bm_win_id < 0) {
1059 /* Find first not occupied window */
1060 for (i = 0; i < MVNETA_MAX_DECODE_WIN; i++) {
1061 if (win_enable & (1 << i)) {
1066 if (i == MVNETA_MAX_DECODE_WIN)
1072 mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
1073 mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
1076 mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
1078 mvreg_write(pp, MVNETA_WIN_BASE(i), (base & 0xffff0000) |
1079 (attr << 8) | target);
1081 mvreg_write(pp, MVNETA_WIN_SIZE(i), (wsize - 1) & 0xffff0000);
1083 win_protect = mvreg_read(pp, MVNETA_ACCESS_PROTECT_ENABLE);
1084 win_protect |= 3 << (2 * i);
1085 mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect);
1087 win_enable &= ~(1 << i);
1088 mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
1093 static int mvneta_bm_port_mbus_init(struct mvneta_port *pp)
1099 /* Get BM window information */
1100 err = mvebu_mbus_get_io_win_info(pp->bm_priv->bppi_phys_addr, &wsize,
1107 /* Open NETA -> BM window */
1108 err = mvneta_mbus_io_win_set(pp, pp->bm_priv->bppi_phys_addr, wsize,
1111 netdev_info(pp->dev, "fail to configure mbus window to BM\n");
1117 /* Assign and initialize pools for port. In case of fail
1118 * buffer manager will remain disabled for current port.
1120 static int mvneta_bm_port_init(struct platform_device *pdev,
1121 struct mvneta_port *pp)
1123 struct device_node *dn = pdev->dev.of_node;
1124 u32 long_pool_id, short_pool_id;
1126 if (!pp->neta_armada3700) {
1129 ret = mvneta_bm_port_mbus_init(pp);
1134 if (of_property_read_u32(dn, "bm,pool-long", &long_pool_id)) {
1135 netdev_info(pp->dev, "missing long pool id\n");
1139 /* Create port's long pool depending on mtu */
1140 pp->pool_long = mvneta_bm_pool_use(pp->bm_priv, long_pool_id,
1141 MVNETA_BM_LONG, pp->id,
1142 MVNETA_RX_PKT_SIZE(pp->dev->mtu));
1143 if (!pp->pool_long) {
1144 netdev_info(pp->dev, "fail to obtain long pool for port\n");
1148 pp->pool_long->port_map |= 1 << pp->id;
1150 mvneta_bm_pool_bufsize_set(pp, pp->pool_long->buf_size,
1153 /* If short pool id is not defined, assume using single pool */
1154 if (of_property_read_u32(dn, "bm,pool-short", &short_pool_id))
1155 short_pool_id = long_pool_id;
1157 /* Create port's short pool */
1158 pp->pool_short = mvneta_bm_pool_use(pp->bm_priv, short_pool_id,
1159 MVNETA_BM_SHORT, pp->id,
1160 MVNETA_BM_SHORT_PKT_SIZE);
1161 if (!pp->pool_short) {
1162 netdev_info(pp->dev, "fail to obtain short pool for port\n");
1163 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id);
1167 if (short_pool_id != long_pool_id) {
1168 pp->pool_short->port_map |= 1 << pp->id;
1169 mvneta_bm_pool_bufsize_set(pp, pp->pool_short->buf_size,
1170 pp->pool_short->id);
1176 /* Update settings of a pool for bigger packets */
1177 static void mvneta_bm_update_mtu(struct mvneta_port *pp, int mtu)
1179 struct mvneta_bm_pool *bm_pool = pp->pool_long;
1180 struct hwbm_pool *hwbm_pool = &bm_pool->hwbm_pool;
1183 /* Release all buffers from long pool */
1184 mvneta_bm_bufs_free(pp->bm_priv, bm_pool, 1 << pp->id);
1185 if (hwbm_pool->buf_num) {
1186 WARN(1, "cannot free all buffers in pool %d\n",
1191 bm_pool->pkt_size = MVNETA_RX_PKT_SIZE(mtu);
1192 bm_pool->buf_size = MVNETA_RX_BUF_SIZE(bm_pool->pkt_size);
1193 hwbm_pool->frag_size = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +
1194 SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(bm_pool->pkt_size));
1196 /* Fill entire long pool */
1197 num = hwbm_pool_add(hwbm_pool, hwbm_pool->size);
1198 if (num != hwbm_pool->size) {
1199 WARN(1, "pool %d: %d of %d allocated\n",
1200 bm_pool->id, num, hwbm_pool->size);
1203 mvneta_bm_pool_bufsize_set(pp, bm_pool->buf_size, bm_pool->id);
1208 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id);
1209 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, 1 << pp->id);
1212 pp->rx_offset_correction = MVNETA_SKB_HEADROOM;
1213 mvreg_write(pp, MVNETA_ACC_MODE, MVNETA_ACC_MODE_EXT1);
1214 netdev_info(pp->dev, "fail to update MTU, fall back to software BM\n");
1217 /* Start the Ethernet port RX and TX activity */
1218 static void mvneta_port_up(struct mvneta_port *pp)
1223 /* Enable all initialized TXs. */
1225 for (queue = 0; queue < txq_number; queue++) {
1226 struct mvneta_tx_queue *txq = &pp->txqs[queue];
1228 q_map |= (1 << queue);
1230 mvreg_write(pp, MVNETA_TXQ_CMD, q_map);
1233 /* Enable all initialized RXQs. */
1234 for (queue = 0; queue < rxq_number; queue++) {
1235 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
1238 q_map |= (1 << queue);
1240 mvreg_write(pp, MVNETA_RXQ_CMD, q_map);
1243 /* Stop the Ethernet port activity */
1244 static void mvneta_port_down(struct mvneta_port *pp)
1249 /* Stop Rx port activity. Check port Rx activity. */
1250 val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK;
1252 /* Issue stop command for active channels only */
1254 mvreg_write(pp, MVNETA_RXQ_CMD,
1255 val << MVNETA_RXQ_DISABLE_SHIFT);
1257 /* Wait for all Rx activity to terminate. */
1260 if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) {
1261 netdev_warn(pp->dev,
1262 "TIMEOUT for RX stopped ! rx_queue_cmd: 0x%08x\n",
1268 val = mvreg_read(pp, MVNETA_RXQ_CMD);
1269 } while (val & MVNETA_RXQ_ENABLE_MASK);
1271 /* Stop Tx port activity. Check port Tx activity. Issue stop
1272 * command for active channels only
1274 val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK;
1277 mvreg_write(pp, MVNETA_TXQ_CMD,
1278 (val << MVNETA_TXQ_DISABLE_SHIFT));
1280 /* Wait for all Tx activity to terminate. */
1283 if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) {
1284 netdev_warn(pp->dev,
1285 "TIMEOUT for TX stopped status=0x%08x\n",
1291 /* Check TX Command reg that all Txqs are stopped */
1292 val = mvreg_read(pp, MVNETA_TXQ_CMD);
1294 } while (val & MVNETA_TXQ_ENABLE_MASK);
1296 /* Double check to verify that TX FIFO is empty */
1299 if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) {
1300 netdev_warn(pp->dev,
1301 "TX FIFO empty timeout status=0x%08x\n",
1307 val = mvreg_read(pp, MVNETA_PORT_STATUS);
1308 } while (!(val & MVNETA_TX_FIFO_EMPTY) &&
1309 (val & MVNETA_TX_IN_PRGRS));
1314 /* Enable the port by setting the port enable bit of the MAC control register */
1315 static void mvneta_port_enable(struct mvneta_port *pp)
1320 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
1321 val |= MVNETA_GMAC0_PORT_ENABLE;
1322 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
1325 /* Disable the port and wait for about 200 usec before retuning */
1326 static void mvneta_port_disable(struct mvneta_port *pp)
1330 /* Reset the Enable bit in the Serial Control Register */
1331 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
1332 val &= ~MVNETA_GMAC0_PORT_ENABLE;
1333 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
1338 /* Multicast tables methods */
1340 /* Set all entries in Unicast MAC Table; queue==-1 means reject all */
1341 static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue)
1349 val = 0x1 | (queue << 1);
1350 val |= (val << 24) | (val << 16) | (val << 8);
1353 for (offset = 0; offset <= 0xc; offset += 4)
1354 mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val);
1357 /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */
1358 static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue)
1366 val = 0x1 | (queue << 1);
1367 val |= (val << 24) | (val << 16) | (val << 8);
1370 for (offset = 0; offset <= 0xfc; offset += 4)
1371 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val);
1375 /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */
1376 static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue)
1382 memset(pp->mcast_count, 0, sizeof(pp->mcast_count));
1385 memset(pp->mcast_count, 1, sizeof(pp->mcast_count));
1386 val = 0x1 | (queue << 1);
1387 val |= (val << 24) | (val << 16) | (val << 8);
1390 for (offset = 0; offset <= 0xfc; offset += 4)
1391 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val);
1394 static void mvneta_percpu_unmask_interrupt(void *arg)
1396 struct mvneta_port *pp = arg;
1398 /* All the queue are unmasked, but actually only the ones
1399 * mapped to this CPU will be unmasked
1401 mvreg_write(pp, MVNETA_INTR_NEW_MASK,
1402 MVNETA_RX_INTR_MASK_ALL |
1403 MVNETA_TX_INTR_MASK_ALL |
1404 MVNETA_MISCINTR_INTR_MASK);
1407 static void mvneta_percpu_mask_interrupt(void *arg)
1409 struct mvneta_port *pp = arg;
1411 /* All the queue are masked, but actually only the ones
1412 * mapped to this CPU will be masked
1414 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
1415 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
1416 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
1419 static void mvneta_percpu_clear_intr_cause(void *arg)
1421 struct mvneta_port *pp = arg;
1423 /* All the queue are cleared, but actually only the ones
1424 * mapped to this CPU will be cleared
1426 mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0);
1427 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
1428 mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
1431 /* This method sets defaults to the NETA port:
1432 * Clears interrupt Cause and Mask registers.
1433 * Clears all MAC tables.
1434 * Sets defaults to all registers.
1435 * Resets RX and TX descriptor rings.
1437 * This method can be called after mvneta_port_down() to return the port
1438 * settings to defaults.
1440 static void mvneta_defaults_set(struct mvneta_port *pp)
1445 int max_cpu = num_present_cpus();
1447 /* Clear all Cause registers */
1448 on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true);
1450 /* Mask all interrupts */
1451 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
1452 mvreg_write(pp, MVNETA_INTR_ENABLE, 0);
1454 /* Enable MBUS Retry bit16 */
1455 mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20);
1457 /* Set CPU queue access map. CPUs are assigned to the RX and
1458 * TX queues modulo their number. If there is only one TX
1459 * queue then it is assigned to the CPU associated to the
1462 for_each_present_cpu(cpu) {
1463 int rxq_map = 0, txq_map = 0;
1465 if (!pp->neta_armada3700) {
1466 for (rxq = 0; rxq < rxq_number; rxq++)
1467 if ((rxq % max_cpu) == cpu)
1468 rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq);
1470 for (txq = 0; txq < txq_number; txq++)
1471 if ((txq % max_cpu) == cpu)
1472 txq_map |= MVNETA_CPU_TXQ_ACCESS(txq);
1474 /* With only one TX queue we configure a special case
1475 * which will allow to get all the irq on a single
1478 if (txq_number == 1)
1479 txq_map = (cpu == pp->rxq_def) ?
1480 MVNETA_CPU_TXQ_ACCESS(1) : 0;
1483 txq_map = MVNETA_CPU_TXQ_ACCESS_ALL_MASK;
1484 rxq_map = MVNETA_CPU_RXQ_ACCESS_ALL_MASK;
1487 mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map);
1490 /* Reset RX and TX DMAs */
1491 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
1492 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
1494 /* Disable Legacy WRR, Disable EJP, Release from reset */
1495 mvreg_write(pp, MVNETA_TXQ_CMD_1, 0);
1496 for (queue = 0; queue < txq_number; queue++) {
1497 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0);
1498 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0);
1501 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
1502 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
1504 /* Set Port Acceleration Mode */
1506 /* HW buffer management + legacy parser */
1507 val = MVNETA_ACC_MODE_EXT2;
1509 /* SW buffer management + legacy parser */
1510 val = MVNETA_ACC_MODE_EXT1;
1511 mvreg_write(pp, MVNETA_ACC_MODE, val);
1514 mvreg_write(pp, MVNETA_BM_ADDRESS, pp->bm_priv->bppi_phys_addr);
1516 /* Update val of portCfg register accordingly with all RxQueue types */
1517 val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def);
1518 mvreg_write(pp, MVNETA_PORT_CONFIG, val);
1521 mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val);
1522 mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64);
1524 /* Build PORT_SDMA_CONFIG_REG */
1527 /* Default burst size */
1528 val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
1529 val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
1530 val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP;
1532 #if defined(__BIG_ENDIAN)
1533 val |= MVNETA_DESC_SWAP;
1536 /* Assign port SDMA configuration */
1537 mvreg_write(pp, MVNETA_SDMA_CONFIG, val);
1539 /* Disable PHY polling in hardware, since we're using the
1540 * kernel phylib to do this.
1542 val = mvreg_read(pp, MVNETA_UNIT_CONTROL);
1543 val &= ~MVNETA_PHY_POLLING_ENABLE;
1544 mvreg_write(pp, MVNETA_UNIT_CONTROL, val);
1546 mvneta_set_ucast_table(pp, -1);
1547 mvneta_set_special_mcast_table(pp, -1);
1548 mvneta_set_other_mcast_table(pp, -1);
1550 /* Set port interrupt enable register - default enable all */
1551 mvreg_write(pp, MVNETA_INTR_ENABLE,
1552 (MVNETA_RXQ_INTR_ENABLE_ALL_MASK
1553 | MVNETA_TXQ_INTR_ENABLE_ALL_MASK));
1555 mvneta_mib_counters_clear(pp);
1558 /* Set max sizes for tx queues */
1559 static void mvneta_txq_max_tx_size_set(struct mvneta_port *pp, int max_tx_size)
1565 mtu = max_tx_size * 8;
1566 if (mtu > MVNETA_TX_MTU_MAX)
1567 mtu = MVNETA_TX_MTU_MAX;
1570 val = mvreg_read(pp, MVNETA_TX_MTU);
1571 val &= ~MVNETA_TX_MTU_MAX;
1573 mvreg_write(pp, MVNETA_TX_MTU, val);
1575 /* TX token size and all TXQs token size must be larger that MTU */
1576 val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE);
1578 size = val & MVNETA_TX_TOKEN_SIZE_MAX;
1581 val &= ~MVNETA_TX_TOKEN_SIZE_MAX;
1583 mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val);
1585 for (queue = 0; queue < txq_number; queue++) {
1586 val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue));
1588 size = val & MVNETA_TXQ_TOKEN_SIZE_MAX;
1591 val &= ~MVNETA_TXQ_TOKEN_SIZE_MAX;
1593 mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val);
1598 /* Set unicast address */
1599 static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble,
1602 unsigned int unicast_reg;
1603 unsigned int tbl_offset;
1604 unsigned int reg_offset;
1606 /* Locate the Unicast table entry */
1607 last_nibble = (0xf & last_nibble);
1609 /* offset from unicast tbl base */
1610 tbl_offset = (last_nibble / 4) * 4;
1612 /* offset within the above reg */
1613 reg_offset = last_nibble % 4;
1615 unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset));
1618 /* Clear accepts frame bit at specified unicast DA tbl entry */
1619 unicast_reg &= ~(0xff << (8 * reg_offset));
1621 unicast_reg &= ~(0xff << (8 * reg_offset));
1622 unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
1625 mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg);
1628 /* Set mac address */
1629 static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr,
1636 mac_l = (addr[4] << 8) | (addr[5]);
1637 mac_h = (addr[0] << 24) | (addr[1] << 16) |
1638 (addr[2] << 8) | (addr[3] << 0);
1640 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l);
1641 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h);
1644 /* Accept frames of this address */
1645 mvneta_set_ucast_addr(pp, addr[5], queue);
1648 /* Set the number of packets that will be received before RX interrupt
1649 * will be generated by HW.
1651 static void mvneta_rx_pkts_coal_set(struct mvneta_port *pp,
1652 struct mvneta_rx_queue *rxq, u32 value)
1654 mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id),
1655 value | MVNETA_RXQ_NON_OCCUPIED(0));
1658 /* Set the time delay in usec before RX interrupt will be generated by
1661 static void mvneta_rx_time_coal_set(struct mvneta_port *pp,
1662 struct mvneta_rx_queue *rxq, u32 value)
1665 unsigned long clk_rate;
1667 clk_rate = clk_get_rate(pp->clk);
1668 val = (clk_rate / 1000000) * value;
1670 mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val);
1673 /* Set threshold for TX_DONE pkts coalescing */
1674 static void mvneta_tx_done_pkts_coal_set(struct mvneta_port *pp,
1675 struct mvneta_tx_queue *txq, u32 value)
1679 val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id));
1681 val &= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK;
1682 val |= MVNETA_TXQ_SENT_THRESH_MASK(value);
1684 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val);
1687 /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
1688 static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc,
1689 u32 phys_addr, void *virt_addr,
1690 struct mvneta_rx_queue *rxq)
1694 rx_desc->buf_phys_addr = phys_addr;
1695 i = rx_desc - rxq->descs;
1696 rxq->buf_virt_addr[i] = virt_addr;
1699 /* Decrement sent descriptors counter */
1700 static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp,
1701 struct mvneta_tx_queue *txq,
1706 /* Only 255 TX descriptors can be updated at once */
1707 while (sent_desc > 0xff) {
1708 val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT;
1709 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
1710 sent_desc = sent_desc - 0xff;
1713 val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT;
1714 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
1717 /* Get number of TX descriptors already sent by HW */
1718 static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp,
1719 struct mvneta_tx_queue *txq)
1724 val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id));
1725 sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >>
1726 MVNETA_TXQ_SENT_DESC_SHIFT;
1731 /* Get number of sent descriptors and decrement counter.
1732 * The number of sent descriptors is returned.
1734 static int mvneta_txq_sent_desc_proc(struct mvneta_port *pp,
1735 struct mvneta_tx_queue *txq)
1739 /* Get number of sent descriptors */
1740 sent_desc = mvneta_txq_sent_desc_num_get(pp, txq);
1742 /* Decrement sent descriptors counter */
1744 mvneta_txq_sent_desc_dec(pp, txq, sent_desc);
1749 /* Set TXQ descriptors fields relevant for CSUM calculation */
1750 static u32 mvneta_txq_desc_csum(int l3_offs, int l3_proto,
1751 int ip_hdr_len, int l4_proto)
1755 /* Fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk,
1756 * G_L4_chk, L4_type; required only for checksum
1759 command = l3_offs << MVNETA_TX_L3_OFF_SHIFT;
1760 command |= ip_hdr_len << MVNETA_TX_IP_HLEN_SHIFT;
1762 if (l3_proto == htons(ETH_P_IP))
1763 command |= MVNETA_TXD_IP_CSUM;
1765 command |= MVNETA_TX_L3_IP6;
1767 if (l4_proto == IPPROTO_TCP)
1768 command |= MVNETA_TX_L4_CSUM_FULL;
1769 else if (l4_proto == IPPROTO_UDP)
1770 command |= MVNETA_TX_L4_UDP | MVNETA_TX_L4_CSUM_FULL;
1772 command |= MVNETA_TX_L4_CSUM_NOT;
1778 /* Display more error info */
1779 static void mvneta_rx_error(struct mvneta_port *pp,
1780 struct mvneta_rx_desc *rx_desc)
1782 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
1783 u32 status = rx_desc->status;
1785 /* update per-cpu counter */
1786 u64_stats_update_begin(&stats->syncp);
1788 u64_stats_update_end(&stats->syncp);
1790 switch (status & MVNETA_RXD_ERR_CODE_MASK) {
1791 case MVNETA_RXD_ERR_CRC:
1792 netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n",
1793 status, rx_desc->data_size);
1795 case MVNETA_RXD_ERR_OVERRUN:
1796 netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n",
1797 status, rx_desc->data_size);
1799 case MVNETA_RXD_ERR_LEN:
1800 netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n",
1801 status, rx_desc->data_size);
1803 case MVNETA_RXD_ERR_RESOURCE:
1804 netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n",
1805 status, rx_desc->data_size);
1810 /* Handle RX checksum offload based on the descriptor's status */
1811 static void mvneta_rx_csum(struct mvneta_port *pp, u32 status,
1812 struct sk_buff *skb)
1814 if ((pp->dev->features & NETIF_F_RXCSUM) &&
1815 (status & MVNETA_RXD_L3_IP4) &&
1816 (status & MVNETA_RXD_L4_CSUM_OK)) {
1818 skb->ip_summed = CHECKSUM_UNNECESSARY;
1822 skb->ip_summed = CHECKSUM_NONE;
1825 /* Return tx queue pointer (find last set bit) according to <cause> returned
1826 * form tx_done reg. <cause> must not be null. The return value is always a
1827 * valid queue for matching the first one found in <cause>.
1829 static struct mvneta_tx_queue *mvneta_tx_done_policy(struct mvneta_port *pp,
1832 int queue = fls(cause) - 1;
1834 return &pp->txqs[queue];
1837 /* Free tx queue skbuffs */
1838 static void mvneta_txq_bufs_free(struct mvneta_port *pp,
1839 struct mvneta_tx_queue *txq, int num,
1840 struct netdev_queue *nq)
1842 unsigned int bytes_compl = 0, pkts_compl = 0;
1845 for (i = 0; i < num; i++) {
1846 struct mvneta_tx_buf *buf = &txq->buf[txq->txq_get_index];
1847 struct mvneta_tx_desc *tx_desc = txq->descs +
1850 mvneta_txq_inc_get(txq);
1852 if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr) &&
1853 buf->type != MVNETA_TYPE_XDP_TX)
1854 dma_unmap_single(pp->dev->dev.parent,
1855 tx_desc->buf_phys_addr,
1856 tx_desc->data_size, DMA_TO_DEVICE);
1857 if (buf->type == MVNETA_TYPE_SKB && buf->skb) {
1858 bytes_compl += buf->skb->len;
1860 dev_kfree_skb_any(buf->skb);
1861 } else if (buf->type == MVNETA_TYPE_XDP_TX ||
1862 buf->type == MVNETA_TYPE_XDP_NDO) {
1863 xdp_return_frame(buf->xdpf);
1867 netdev_tx_completed_queue(nq, pkts_compl, bytes_compl);
1870 /* Handle end of transmission */
1871 static void mvneta_txq_done(struct mvneta_port *pp,
1872 struct mvneta_tx_queue *txq)
1874 struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id);
1877 tx_done = mvneta_txq_sent_desc_proc(pp, txq);
1881 mvneta_txq_bufs_free(pp, txq, tx_done, nq);
1883 txq->count -= tx_done;
1885 if (netif_tx_queue_stopped(nq)) {
1886 if (txq->count <= txq->tx_wake_threshold)
1887 netif_tx_wake_queue(nq);
1891 /* Refill processing for SW buffer management */
1892 /* Allocate page per descriptor */
1893 static int mvneta_rx_refill(struct mvneta_port *pp,
1894 struct mvneta_rx_desc *rx_desc,
1895 struct mvneta_rx_queue *rxq,
1898 dma_addr_t phys_addr;
1901 page = page_pool_alloc_pages(rxq->page_pool,
1902 gfp_mask | __GFP_NOWARN);
1906 phys_addr = page_pool_get_dma_addr(page) + pp->rx_offset_correction;
1907 mvneta_rx_desc_fill(rx_desc, phys_addr, page, rxq);
1912 /* Handle tx checksum */
1913 static u32 mvneta_skb_tx_csum(struct mvneta_port *pp, struct sk_buff *skb)
1915 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1917 __be16 l3_proto = vlan_get_protocol(skb);
1920 if (l3_proto == htons(ETH_P_IP)) {
1921 struct iphdr *ip4h = ip_hdr(skb);
1923 /* Calculate IPv4 checksum and L4 checksum */
1924 ip_hdr_len = ip4h->ihl;
1925 l4_proto = ip4h->protocol;
1926 } else if (l3_proto == htons(ETH_P_IPV6)) {
1927 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1929 /* Read l4_protocol from one of IPv6 extra headers */
1930 if (skb_network_header_len(skb) > 0)
1931 ip_hdr_len = (skb_network_header_len(skb) >> 2);
1932 l4_proto = ip6h->nexthdr;
1934 return MVNETA_TX_L4_CSUM_NOT;
1936 return mvneta_txq_desc_csum(skb_network_offset(skb),
1937 l3_proto, ip_hdr_len, l4_proto);
1940 return MVNETA_TX_L4_CSUM_NOT;
1943 /* Drop packets received by the RXQ and free buffers */
1944 static void mvneta_rxq_drop_pkts(struct mvneta_port *pp,
1945 struct mvneta_rx_queue *rxq)
1949 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
1951 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
1954 for (i = 0; i < rx_done; i++) {
1955 struct mvneta_rx_desc *rx_desc =
1956 mvneta_rxq_next_desc_get(rxq);
1957 u8 pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc);
1958 struct mvneta_bm_pool *bm_pool;
1960 bm_pool = &pp->bm_priv->bm_pools[pool_id];
1961 /* Return dropped buffer to the pool */
1962 mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool,
1963 rx_desc->buf_phys_addr);
1968 for (i = 0; i < rxq->size; i++) {
1969 struct mvneta_rx_desc *rx_desc = rxq->descs + i;
1970 void *data = rxq->buf_virt_addr[i];
1971 if (!data || !(rx_desc->buf_phys_addr))
1974 page_pool_put_full_page(rxq->page_pool, data, false);
1976 if (xdp_rxq_info_is_reg(&rxq->xdp_rxq))
1977 xdp_rxq_info_unreg(&rxq->xdp_rxq);
1978 page_pool_destroy(rxq->page_pool);
1979 rxq->page_pool = NULL;
1983 mvneta_update_stats(struct mvneta_port *pp,
1984 struct mvneta_stats *ps)
1986 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
1988 u64_stats_update_begin(&stats->syncp);
1989 stats->es.ps.rx_packets += ps->rx_packets;
1990 stats->es.ps.rx_bytes += ps->rx_bytes;
1992 stats->es.ps.xdp_redirect += ps->xdp_redirect;
1993 stats->es.ps.xdp_pass += ps->xdp_pass;
1994 stats->es.ps.xdp_drop += ps->xdp_drop;
1995 u64_stats_update_end(&stats->syncp);
1999 int mvneta_rx_refill_queue(struct mvneta_port *pp, struct mvneta_rx_queue *rxq)
2001 struct mvneta_rx_desc *rx_desc;
2002 int curr_desc = rxq->first_to_refill;
2005 for (i = 0; (i < rxq->refill_num) && (i < 64); i++) {
2006 rx_desc = rxq->descs + curr_desc;
2007 if (!(rx_desc->buf_phys_addr)) {
2008 if (mvneta_rx_refill(pp, rx_desc, rxq, GFP_ATOMIC)) {
2009 struct mvneta_pcpu_stats *stats;
2011 pr_err("Can't refill queue %d. Done %d from %d\n",
2012 rxq->id, i, rxq->refill_num);
2014 stats = this_cpu_ptr(pp->stats);
2015 u64_stats_update_begin(&stats->syncp);
2016 stats->es.refill_error++;
2017 u64_stats_update_end(&stats->syncp);
2021 curr_desc = MVNETA_QUEUE_NEXT_DESC(rxq, curr_desc);
2023 rxq->refill_num -= i;
2024 rxq->first_to_refill = curr_desc;
2030 mvneta_xdp_put_buff(struct mvneta_port *pp, struct mvneta_rx_queue *rxq,
2031 struct xdp_buff *xdp, int sync_len, bool napi)
2033 struct skb_shared_info *sinfo = xdp_get_shared_info_from_buff(xdp);
2036 page_pool_put_page(rxq->page_pool, virt_to_head_page(xdp->data),
2038 for (i = 0; i < sinfo->nr_frags; i++)
2039 page_pool_put_full_page(rxq->page_pool,
2040 skb_frag_page(&sinfo->frags[i]), napi);
2044 mvneta_xdp_submit_frame(struct mvneta_port *pp, struct mvneta_tx_queue *txq,
2045 struct xdp_frame *xdpf, bool dma_map)
2047 struct mvneta_tx_desc *tx_desc;
2048 struct mvneta_tx_buf *buf;
2049 dma_addr_t dma_addr;
2051 if (txq->count >= txq->tx_stop_threshold)
2052 return MVNETA_XDP_DROPPED;
2054 tx_desc = mvneta_txq_next_desc_get(txq);
2056 buf = &txq->buf[txq->txq_put_index];
2059 dma_addr = dma_map_single(pp->dev->dev.parent, xdpf->data,
2060 xdpf->len, DMA_TO_DEVICE);
2061 if (dma_mapping_error(pp->dev->dev.parent, dma_addr)) {
2062 mvneta_txq_desc_put(txq);
2063 return MVNETA_XDP_DROPPED;
2065 buf->type = MVNETA_TYPE_XDP_NDO;
2067 struct page *page = virt_to_page(xdpf->data);
2069 dma_addr = page_pool_get_dma_addr(page) +
2070 sizeof(*xdpf) + xdpf->headroom;
2071 dma_sync_single_for_device(pp->dev->dev.parent, dma_addr,
2072 xdpf->len, DMA_BIDIRECTIONAL);
2073 buf->type = MVNETA_TYPE_XDP_TX;
2077 tx_desc->command = MVNETA_TXD_FLZ_DESC;
2078 tx_desc->buf_phys_addr = dma_addr;
2079 tx_desc->data_size = xdpf->len;
2081 mvneta_txq_inc_put(txq);
2085 return MVNETA_XDP_TX;
2089 mvneta_xdp_xmit_back(struct mvneta_port *pp, struct xdp_buff *xdp)
2091 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
2092 struct mvneta_tx_queue *txq;
2093 struct netdev_queue *nq;
2094 struct xdp_frame *xdpf;
2098 xdpf = xdp_convert_buff_to_frame(xdp);
2099 if (unlikely(!xdpf))
2100 return MVNETA_XDP_DROPPED;
2102 cpu = smp_processor_id();
2103 txq = &pp->txqs[cpu % txq_number];
2104 nq = netdev_get_tx_queue(pp->dev, txq->id);
2106 __netif_tx_lock(nq, cpu);
2107 ret = mvneta_xdp_submit_frame(pp, txq, xdpf, false);
2108 if (ret == MVNETA_XDP_TX) {
2109 u64_stats_update_begin(&stats->syncp);
2110 stats->es.ps.tx_bytes += xdpf->len;
2111 stats->es.ps.tx_packets++;
2112 stats->es.ps.xdp_tx++;
2113 u64_stats_update_end(&stats->syncp);
2115 mvneta_txq_pend_desc_add(pp, txq, 0);
2117 u64_stats_update_begin(&stats->syncp);
2118 stats->es.ps.xdp_tx_err++;
2119 u64_stats_update_end(&stats->syncp);
2121 __netif_tx_unlock(nq);
2127 mvneta_xdp_xmit(struct net_device *dev, int num_frame,
2128 struct xdp_frame **frames, u32 flags)
2130 struct mvneta_port *pp = netdev_priv(dev);
2131 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
2132 int i, nxmit_byte = 0, nxmit = num_frame;
2133 int cpu = smp_processor_id();
2134 struct mvneta_tx_queue *txq;
2135 struct netdev_queue *nq;
2138 if (unlikely(test_bit(__MVNETA_DOWN, &pp->state)))
2141 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
2144 txq = &pp->txqs[cpu % txq_number];
2145 nq = netdev_get_tx_queue(pp->dev, txq->id);
2147 __netif_tx_lock(nq, cpu);
2148 for (i = 0; i < num_frame; i++) {
2149 ret = mvneta_xdp_submit_frame(pp, txq, frames[i], true);
2150 if (ret == MVNETA_XDP_TX) {
2151 nxmit_byte += frames[i]->len;
2153 xdp_return_frame_rx_napi(frames[i]);
2158 if (unlikely(flags & XDP_XMIT_FLUSH))
2159 mvneta_txq_pend_desc_add(pp, txq, 0);
2160 __netif_tx_unlock(nq);
2162 u64_stats_update_begin(&stats->syncp);
2163 stats->es.ps.tx_bytes += nxmit_byte;
2164 stats->es.ps.tx_packets += nxmit;
2165 stats->es.ps.xdp_xmit += nxmit;
2166 stats->es.ps.xdp_xmit_err += num_frame - nxmit;
2167 u64_stats_update_end(&stats->syncp);
2173 mvneta_run_xdp(struct mvneta_port *pp, struct mvneta_rx_queue *rxq,
2174 struct bpf_prog *prog, struct xdp_buff *xdp,
2175 u32 frame_sz, struct mvneta_stats *stats)
2177 unsigned int len, data_len, sync;
2180 len = xdp->data_end - xdp->data_hard_start - pp->rx_offset_correction;
2181 data_len = xdp->data_end - xdp->data;
2182 act = bpf_prog_run_xdp(prog, xdp);
2184 /* Due xdp_adjust_tail: DMA sync for_device cover max len CPU touch */
2185 sync = xdp->data_end - xdp->data_hard_start - pp->rx_offset_correction;
2186 sync = max(sync, len);
2191 return MVNETA_XDP_PASS;
2192 case XDP_REDIRECT: {
2195 err = xdp_do_redirect(pp->dev, xdp, prog);
2196 if (unlikely(err)) {
2197 mvneta_xdp_put_buff(pp, rxq, xdp, sync, true);
2198 ret = MVNETA_XDP_DROPPED;
2200 ret = MVNETA_XDP_REDIR;
2201 stats->xdp_redirect++;
2206 ret = mvneta_xdp_xmit_back(pp, xdp);
2207 if (ret != MVNETA_XDP_TX)
2208 mvneta_xdp_put_buff(pp, rxq, xdp, sync, true);
2211 bpf_warn_invalid_xdp_action(act);
2214 trace_xdp_exception(pp->dev, prog, act);
2217 mvneta_xdp_put_buff(pp, rxq, xdp, sync, true);
2218 ret = MVNETA_XDP_DROPPED;
2223 stats->rx_bytes += frame_sz + xdp->data_end - xdp->data - data_len;
2224 stats->rx_packets++;
2230 mvneta_swbm_rx_frame(struct mvneta_port *pp,
2231 struct mvneta_rx_desc *rx_desc,
2232 struct mvneta_rx_queue *rxq,
2233 struct xdp_buff *xdp,
2235 struct mvneta_stats *stats)
2237 unsigned char *data = page_address(page);
2238 int data_len = -MVNETA_MH_SIZE, len;
2239 struct net_device *dev = pp->dev;
2240 enum dma_data_direction dma_dir;
2241 struct skb_shared_info *sinfo;
2243 if (MVNETA_SKB_SIZE(rx_desc->data_size) > PAGE_SIZE) {
2244 len = MVNETA_MAX_RX_BUF_SIZE;
2247 len = rx_desc->data_size;
2248 data_len += len - ETH_FCS_LEN;
2251 dma_dir = page_pool_get_dma_dir(rxq->page_pool);
2252 dma_sync_single_for_cpu(dev->dev.parent,
2253 rx_desc->buf_phys_addr,
2256 /* Prefetch header */
2259 xdp->data_hard_start = data;
2260 xdp->data = data + pp->rx_offset_correction + MVNETA_MH_SIZE;
2261 xdp->data_end = xdp->data + data_len;
2262 xdp_set_data_meta_invalid(xdp);
2264 sinfo = xdp_get_shared_info_from_buff(xdp);
2265 sinfo->nr_frags = 0;
2267 rxq->left_size = rx_desc->data_size - len;
2268 rx_desc->buf_phys_addr = 0;
2272 mvneta_swbm_add_rx_fragment(struct mvneta_port *pp,
2273 struct mvneta_rx_desc *rx_desc,
2274 struct mvneta_rx_queue *rxq,
2275 struct xdp_buff *xdp,
2278 struct skb_shared_info *sinfo = xdp_get_shared_info_from_buff(xdp);
2279 struct net_device *dev = pp->dev;
2280 enum dma_data_direction dma_dir;
2283 if (rxq->left_size > MVNETA_MAX_RX_BUF_SIZE) {
2284 len = MVNETA_MAX_RX_BUF_SIZE;
2287 len = rxq->left_size;
2288 data_len = len - ETH_FCS_LEN;
2290 dma_dir = page_pool_get_dma_dir(rxq->page_pool);
2291 dma_sync_single_for_cpu(dev->dev.parent,
2292 rx_desc->buf_phys_addr,
2295 if (data_len > 0 && sinfo->nr_frags < MAX_SKB_FRAGS) {
2296 skb_frag_t *frag = &sinfo->frags[sinfo->nr_frags];
2298 skb_frag_off_set(frag, pp->rx_offset_correction);
2299 skb_frag_size_set(frag, data_len);
2300 __skb_frag_set_page(frag, page);
2303 rx_desc->buf_phys_addr = 0;
2305 rxq->left_size -= len;
2308 static struct sk_buff *
2309 mvneta_swbm_build_skb(struct mvneta_port *pp, struct mvneta_rx_queue *rxq,
2310 struct xdp_buff *xdp, u32 desc_status)
2312 struct skb_shared_info *sinfo = xdp_get_shared_info_from_buff(xdp);
2313 int i, num_frags = sinfo->nr_frags;
2314 skb_frag_t frags[MAX_SKB_FRAGS];
2315 struct sk_buff *skb;
2317 memcpy(frags, sinfo->frags, sizeof(skb_frag_t) * num_frags);
2319 skb = build_skb(xdp->data_hard_start, PAGE_SIZE);
2321 return ERR_PTR(-ENOMEM);
2323 page_pool_release_page(rxq->page_pool, virt_to_page(xdp->data));
2325 skb_reserve(skb, xdp->data - xdp->data_hard_start);
2326 skb_put(skb, xdp->data_end - xdp->data);
2327 mvneta_rx_csum(pp, desc_status, skb);
2329 for (i = 0; i < num_frags; i++) {
2330 struct page *page = skb_frag_page(&frags[i]);
2332 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
2333 page, skb_frag_off(&frags[i]),
2334 skb_frag_size(&frags[i]), PAGE_SIZE);
2335 page_pool_release_page(rxq->page_pool, page);
2341 /* Main rx processing when using software buffer management */
2342 static int mvneta_rx_swbm(struct napi_struct *napi,
2343 struct mvneta_port *pp, int budget,
2344 struct mvneta_rx_queue *rxq)
2346 int rx_proc = 0, rx_todo, refill;
2347 struct net_device *dev = pp->dev;
2348 struct xdp_buff xdp_buf = {
2349 .frame_sz = PAGE_SIZE,
2350 .rxq = &rxq->xdp_rxq,
2352 struct mvneta_stats ps = {};
2353 struct bpf_prog *xdp_prog;
2354 u32 desc_status, frame_sz;
2356 /* Get number of received packets */
2357 rx_todo = mvneta_rxq_busy_desc_num_get(pp, rxq);
2360 xdp_prog = READ_ONCE(pp->xdp_prog);
2362 /* Fairness NAPI loop */
2363 while (rx_proc < budget && rx_proc < rx_todo) {
2364 struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq);
2365 u32 rx_status, index;
2366 struct sk_buff *skb;
2369 index = rx_desc - rxq->descs;
2370 page = (struct page *)rxq->buf_virt_addr[index];
2372 rx_status = rx_desc->status;
2376 if (rx_status & MVNETA_RXD_FIRST_DESC) {
2377 /* Check errors only for FIRST descriptor */
2378 if (rx_status & MVNETA_RXD_ERR_SUMMARY) {
2379 mvneta_rx_error(pp, rx_desc);
2383 frame_sz = rx_desc->data_size - ETH_FCS_LEN;
2384 desc_status = rx_desc->status;
2386 mvneta_swbm_rx_frame(pp, rx_desc, rxq, &xdp_buf, page,
2389 if (unlikely(!xdp_buf.data_hard_start))
2392 mvneta_swbm_add_rx_fragment(pp, rx_desc, rxq, &xdp_buf,
2394 } /* Middle or Last descriptor */
2396 if (!(rx_status & MVNETA_RXD_LAST_DESC))
2397 /* no last descriptor this time */
2400 if (rxq->left_size) {
2402 mvneta_xdp_put_buff(pp, rxq, &xdp_buf, -1, true);
2407 mvneta_run_xdp(pp, rxq, xdp_prog, &xdp_buf, frame_sz, &ps))
2410 skb = mvneta_swbm_build_skb(pp, rxq, &xdp_buf, desc_status);
2412 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
2414 mvneta_xdp_put_buff(pp, rxq, &xdp_buf, -1, true);
2416 u64_stats_update_begin(&stats->syncp);
2417 stats->es.skb_alloc_error++;
2418 stats->rx_dropped++;
2419 u64_stats_update_end(&stats->syncp);
2424 ps.rx_bytes += skb->len;
2427 skb->protocol = eth_type_trans(skb, dev);
2428 napi_gro_receive(napi, skb);
2430 xdp_buf.data_hard_start = NULL;
2434 if (xdp_buf.data_hard_start)
2435 mvneta_xdp_put_buff(pp, rxq, &xdp_buf, -1, true);
2437 if (ps.xdp_redirect)
2441 mvneta_update_stats(pp, &ps);
2443 /* return some buffers to hardware queue, one at a time is too slow */
2444 refill = mvneta_rx_refill_queue(pp, rxq);
2446 /* Update rxq management counters */
2447 mvneta_rxq_desc_num_update(pp, rxq, rx_proc, refill);
2449 return ps.rx_packets;
2452 /* Main rx processing when using hardware buffer management */
2453 static int mvneta_rx_hwbm(struct napi_struct *napi,
2454 struct mvneta_port *pp, int rx_todo,
2455 struct mvneta_rx_queue *rxq)
2457 struct net_device *dev = pp->dev;
2462 /* Get number of received packets */
2463 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
2465 if (rx_todo > rx_done)
2470 /* Fairness NAPI loop */
2471 while (rx_done < rx_todo) {
2472 struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq);
2473 struct mvneta_bm_pool *bm_pool = NULL;
2474 struct sk_buff *skb;
2475 unsigned char *data;
2476 dma_addr_t phys_addr;
2477 u32 rx_status, frag_size;
2482 rx_status = rx_desc->status;
2483 rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE);
2484 data = (u8 *)(uintptr_t)rx_desc->buf_cookie;
2485 phys_addr = rx_desc->buf_phys_addr;
2486 pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc);
2487 bm_pool = &pp->bm_priv->bm_pools[pool_id];
2489 if (!mvneta_rxq_desc_is_first_last(rx_status) ||
2490 (rx_status & MVNETA_RXD_ERR_SUMMARY)) {
2491 err_drop_frame_ret_pool:
2492 /* Return the buffer to the pool */
2493 mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool,
2494 rx_desc->buf_phys_addr);
2496 mvneta_rx_error(pp, rx_desc);
2497 /* leave the descriptor untouched */
2501 if (rx_bytes <= rx_copybreak) {
2502 /* better copy a small frame and not unmap the DMA region */
2503 skb = netdev_alloc_skb_ip_align(dev, rx_bytes);
2505 goto err_drop_frame_ret_pool;
2507 dma_sync_single_range_for_cpu(&pp->bm_priv->pdev->dev,
2508 rx_desc->buf_phys_addr,
2509 MVNETA_MH_SIZE + NET_SKB_PAD,
2512 skb_put_data(skb, data + MVNETA_MH_SIZE + NET_SKB_PAD,
2515 skb->protocol = eth_type_trans(skb, dev);
2516 mvneta_rx_csum(pp, rx_status, skb);
2517 napi_gro_receive(napi, skb);
2520 rcvd_bytes += rx_bytes;
2522 /* Return the buffer to the pool */
2523 mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool,
2524 rx_desc->buf_phys_addr);
2526 /* leave the descriptor and buffer untouched */
2530 /* Refill processing */
2531 err = hwbm_pool_refill(&bm_pool->hwbm_pool, GFP_ATOMIC);
2533 struct mvneta_pcpu_stats *stats;
2535 netdev_err(dev, "Linux processing - Can't refill\n");
2537 stats = this_cpu_ptr(pp->stats);
2538 u64_stats_update_begin(&stats->syncp);
2539 stats->es.refill_error++;
2540 u64_stats_update_end(&stats->syncp);
2542 goto err_drop_frame_ret_pool;
2545 frag_size = bm_pool->hwbm_pool.frag_size;
2547 skb = build_skb(data, frag_size > PAGE_SIZE ? 0 : frag_size);
2549 /* After refill old buffer has to be unmapped regardless
2550 * the skb is successfully built or not.
2552 dma_unmap_single(&pp->bm_priv->pdev->dev, phys_addr,
2553 bm_pool->buf_size, DMA_FROM_DEVICE);
2555 goto err_drop_frame;
2558 rcvd_bytes += rx_bytes;
2560 /* Linux processing */
2561 skb_reserve(skb, MVNETA_MH_SIZE + NET_SKB_PAD);
2562 skb_put(skb, rx_bytes);
2564 skb->protocol = eth_type_trans(skb, dev);
2566 mvneta_rx_csum(pp, rx_status, skb);
2568 napi_gro_receive(napi, skb);
2572 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
2574 u64_stats_update_begin(&stats->syncp);
2575 stats->es.ps.rx_packets += rcvd_pkts;
2576 stats->es.ps.rx_bytes += rcvd_bytes;
2577 u64_stats_update_end(&stats->syncp);
2580 /* Update rxq management counters */
2581 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
2587 mvneta_tso_put_hdr(struct sk_buff *skb,
2588 struct mvneta_port *pp, struct mvneta_tx_queue *txq)
2590 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2591 struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index];
2592 struct mvneta_tx_desc *tx_desc;
2594 tx_desc = mvneta_txq_next_desc_get(txq);
2595 tx_desc->data_size = hdr_len;
2596 tx_desc->command = mvneta_skb_tx_csum(pp, skb);
2597 tx_desc->command |= MVNETA_TXD_F_DESC;
2598 tx_desc->buf_phys_addr = txq->tso_hdrs_phys +
2599 txq->txq_put_index * TSO_HEADER_SIZE;
2600 buf->type = MVNETA_TYPE_SKB;
2603 mvneta_txq_inc_put(txq);
2607 mvneta_tso_put_data(struct net_device *dev, struct mvneta_tx_queue *txq,
2608 struct sk_buff *skb, char *data, int size,
2609 bool last_tcp, bool is_last)
2611 struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index];
2612 struct mvneta_tx_desc *tx_desc;
2614 tx_desc = mvneta_txq_next_desc_get(txq);
2615 tx_desc->data_size = size;
2616 tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, data,
2617 size, DMA_TO_DEVICE);
2618 if (unlikely(dma_mapping_error(dev->dev.parent,
2619 tx_desc->buf_phys_addr))) {
2620 mvneta_txq_desc_put(txq);
2624 tx_desc->command = 0;
2625 buf->type = MVNETA_TYPE_SKB;
2629 /* last descriptor in the TCP packet */
2630 tx_desc->command = MVNETA_TXD_L_DESC;
2632 /* last descriptor in SKB */
2636 mvneta_txq_inc_put(txq);
2640 static int mvneta_tx_tso(struct sk_buff *skb, struct net_device *dev,
2641 struct mvneta_tx_queue *txq)
2643 int hdr_len, total_len, data_left;
2645 struct mvneta_port *pp = netdev_priv(dev);
2649 /* Count needed descriptors */
2650 if ((txq->count + tso_count_descs(skb)) >= txq->size)
2653 if (skb_headlen(skb) < (skb_transport_offset(skb) + tcp_hdrlen(skb))) {
2654 pr_info("*** Is this even possible???!?!?\n");
2658 /* Initialize the TSO handler, and prepare the first payload */
2659 hdr_len = tso_start(skb, &tso);
2661 total_len = skb->len - hdr_len;
2662 while (total_len > 0) {
2665 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
2666 total_len -= data_left;
2669 /* prepare packet headers: MAC + IP + TCP */
2670 hdr = txq->tso_hdrs + txq->txq_put_index * TSO_HEADER_SIZE;
2671 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
2673 mvneta_tso_put_hdr(skb, pp, txq);
2675 while (data_left > 0) {
2679 size = min_t(int, tso.size, data_left);
2681 if (mvneta_tso_put_data(dev, txq, skb,
2688 tso_build_data(skb, &tso, size);
2695 /* Release all used data descriptors; header descriptors must not
2698 for (i = desc_count - 1; i >= 0; i--) {
2699 struct mvneta_tx_desc *tx_desc = txq->descs + i;
2700 if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr))
2701 dma_unmap_single(pp->dev->dev.parent,
2702 tx_desc->buf_phys_addr,
2705 mvneta_txq_desc_put(txq);
2710 /* Handle tx fragmentation processing */
2711 static int mvneta_tx_frag_process(struct mvneta_port *pp, struct sk_buff *skb,
2712 struct mvneta_tx_queue *txq)
2714 struct mvneta_tx_desc *tx_desc;
2715 int i, nr_frags = skb_shinfo(skb)->nr_frags;
2717 for (i = 0; i < nr_frags; i++) {
2718 struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index];
2719 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2720 void *addr = skb_frag_address(frag);
2722 tx_desc = mvneta_txq_next_desc_get(txq);
2723 tx_desc->data_size = skb_frag_size(frag);
2725 tx_desc->buf_phys_addr =
2726 dma_map_single(pp->dev->dev.parent, addr,
2727 tx_desc->data_size, DMA_TO_DEVICE);
2729 if (dma_mapping_error(pp->dev->dev.parent,
2730 tx_desc->buf_phys_addr)) {
2731 mvneta_txq_desc_put(txq);
2735 if (i == nr_frags - 1) {
2736 /* Last descriptor */
2737 tx_desc->command = MVNETA_TXD_L_DESC | MVNETA_TXD_Z_PAD;
2740 /* Descriptor in the middle: Not First, Not Last */
2741 tx_desc->command = 0;
2744 buf->type = MVNETA_TYPE_SKB;
2745 mvneta_txq_inc_put(txq);
2751 /* Release all descriptors that were used to map fragments of
2752 * this packet, as well as the corresponding DMA mappings
2754 for (i = i - 1; i >= 0; i--) {
2755 tx_desc = txq->descs + i;
2756 dma_unmap_single(pp->dev->dev.parent,
2757 tx_desc->buf_phys_addr,
2760 mvneta_txq_desc_put(txq);
2766 /* Main tx processing */
2767 static netdev_tx_t mvneta_tx(struct sk_buff *skb, struct net_device *dev)
2769 struct mvneta_port *pp = netdev_priv(dev);
2770 u16 txq_id = skb_get_queue_mapping(skb);
2771 struct mvneta_tx_queue *txq = &pp->txqs[txq_id];
2772 struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index];
2773 struct mvneta_tx_desc *tx_desc;
2778 if (!netif_running(dev))
2781 if (skb_is_gso(skb)) {
2782 frags = mvneta_tx_tso(skb, dev, txq);
2786 frags = skb_shinfo(skb)->nr_frags + 1;
2788 /* Get a descriptor for the first part of the packet */
2789 tx_desc = mvneta_txq_next_desc_get(txq);
2791 tx_cmd = mvneta_skb_tx_csum(pp, skb);
2793 tx_desc->data_size = skb_headlen(skb);
2795 tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, skb->data,
2798 if (unlikely(dma_mapping_error(dev->dev.parent,
2799 tx_desc->buf_phys_addr))) {
2800 mvneta_txq_desc_put(txq);
2805 buf->type = MVNETA_TYPE_SKB;
2807 /* First and Last descriptor */
2808 tx_cmd |= MVNETA_TXD_FLZ_DESC;
2809 tx_desc->command = tx_cmd;
2811 mvneta_txq_inc_put(txq);
2813 /* First but not Last */
2814 tx_cmd |= MVNETA_TXD_F_DESC;
2816 mvneta_txq_inc_put(txq);
2817 tx_desc->command = tx_cmd;
2818 /* Continue with other skb fragments */
2819 if (mvneta_tx_frag_process(pp, skb, txq)) {
2820 dma_unmap_single(dev->dev.parent,
2821 tx_desc->buf_phys_addr,
2824 mvneta_txq_desc_put(txq);
2832 struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id);
2833 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
2835 netdev_tx_sent_queue(nq, len);
2837 txq->count += frags;
2838 if (txq->count >= txq->tx_stop_threshold)
2839 netif_tx_stop_queue(nq);
2841 if (!netdev_xmit_more() || netif_xmit_stopped(nq) ||
2842 txq->pending + frags > MVNETA_TXQ_DEC_SENT_MASK)
2843 mvneta_txq_pend_desc_add(pp, txq, frags);
2845 txq->pending += frags;
2847 u64_stats_update_begin(&stats->syncp);
2848 stats->es.ps.tx_bytes += len;
2849 stats->es.ps.tx_packets++;
2850 u64_stats_update_end(&stats->syncp);
2852 dev->stats.tx_dropped++;
2853 dev_kfree_skb_any(skb);
2856 return NETDEV_TX_OK;
2860 /* Free tx resources, when resetting a port */
2861 static void mvneta_txq_done_force(struct mvneta_port *pp,
2862 struct mvneta_tx_queue *txq)
2865 struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id);
2866 int tx_done = txq->count;
2868 mvneta_txq_bufs_free(pp, txq, tx_done, nq);
2872 txq->txq_put_index = 0;
2873 txq->txq_get_index = 0;
2876 /* Handle tx done - called in softirq context. The <cause_tx_done> argument
2877 * must be a valid cause according to MVNETA_TXQ_INTR_MASK_ALL.
2879 static void mvneta_tx_done_gbe(struct mvneta_port *pp, u32 cause_tx_done)
2881 struct mvneta_tx_queue *txq;
2882 struct netdev_queue *nq;
2883 int cpu = smp_processor_id();
2885 while (cause_tx_done) {
2886 txq = mvneta_tx_done_policy(pp, cause_tx_done);
2888 nq = netdev_get_tx_queue(pp->dev, txq->id);
2889 __netif_tx_lock(nq, cpu);
2892 mvneta_txq_done(pp, txq);
2894 __netif_tx_unlock(nq);
2895 cause_tx_done &= ~((1 << txq->id));
2899 /* Compute crc8 of the specified address, using a unique algorithm ,
2900 * according to hw spec, different than generic crc8 algorithm
2902 static int mvneta_addr_crc(unsigned char *addr)
2907 for (i = 0; i < ETH_ALEN; i++) {
2910 crc = (crc ^ addr[i]) << 8;
2911 for (j = 7; j >= 0; j--) {
2912 if (crc & (0x100 << j))
2920 /* This method controls the net device special MAC multicast support.
2921 * The Special Multicast Table for MAC addresses supports MAC of the form
2922 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
2923 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
2924 * Table entries in the DA-Filter table. This method set the Special
2925 * Multicast Table appropriate entry.
2927 static void mvneta_set_special_mcast_addr(struct mvneta_port *pp,
2928 unsigned char last_byte,
2931 unsigned int smc_table_reg;
2932 unsigned int tbl_offset;
2933 unsigned int reg_offset;
2935 /* Register offset from SMC table base */
2936 tbl_offset = (last_byte / 4);
2937 /* Entry offset within the above reg */
2938 reg_offset = last_byte % 4;
2940 smc_table_reg = mvreg_read(pp, (MVNETA_DA_FILT_SPEC_MCAST
2944 smc_table_reg &= ~(0xff << (8 * reg_offset));
2946 smc_table_reg &= ~(0xff << (8 * reg_offset));
2947 smc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
2950 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4,
2954 /* This method controls the network device Other MAC multicast support.
2955 * The Other Multicast Table is used for multicast of another type.
2956 * A CRC-8 is used as an index to the Other Multicast Table entries
2957 * in the DA-Filter table.
2958 * The method gets the CRC-8 value from the calling routine and
2959 * sets the Other Multicast Table appropriate entry according to the
2962 static void mvneta_set_other_mcast_addr(struct mvneta_port *pp,
2966 unsigned int omc_table_reg;
2967 unsigned int tbl_offset;
2968 unsigned int reg_offset;
2970 tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */
2971 reg_offset = crc8 % 4; /* Entry offset within the above reg */
2973 omc_table_reg = mvreg_read(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset);
2976 /* Clear accepts frame bit at specified Other DA table entry */
2977 omc_table_reg &= ~(0xff << (8 * reg_offset));
2979 omc_table_reg &= ~(0xff << (8 * reg_offset));
2980 omc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
2983 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg);
2986 /* The network device supports multicast using two tables:
2987 * 1) Special Multicast Table for MAC addresses of the form
2988 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
2989 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
2990 * Table entries in the DA-Filter table.
2991 * 2) Other Multicast Table for multicast of another type. A CRC-8 value
2992 * is used as an index to the Other Multicast Table entries in the
2995 static int mvneta_mcast_addr_set(struct mvneta_port *pp, unsigned char *p_addr,
2998 unsigned char crc_result = 0;
3000 if (memcmp(p_addr, "\x01\x00\x5e\x00\x00", 5) == 0) {
3001 mvneta_set_special_mcast_addr(pp, p_addr[5], queue);
3005 crc_result = mvneta_addr_crc(p_addr);
3007 if (pp->mcast_count[crc_result] == 0) {
3008 netdev_info(pp->dev, "No valid Mcast for crc8=0x%02x\n",
3013 pp->mcast_count[crc_result]--;
3014 if (pp->mcast_count[crc_result] != 0) {
3015 netdev_info(pp->dev,
3016 "After delete there are %d valid Mcast for crc8=0x%02x\n",
3017 pp->mcast_count[crc_result], crc_result);
3021 pp->mcast_count[crc_result]++;
3023 mvneta_set_other_mcast_addr(pp, crc_result, queue);
3028 /* Configure Fitering mode of Ethernet port */
3029 static void mvneta_rx_unicast_promisc_set(struct mvneta_port *pp,
3032 u32 port_cfg_reg, val;
3034 port_cfg_reg = mvreg_read(pp, MVNETA_PORT_CONFIG);
3036 val = mvreg_read(pp, MVNETA_TYPE_PRIO);
3038 /* Set / Clear UPM bit in port configuration register */
3040 /* Accept all Unicast addresses */
3041 port_cfg_reg |= MVNETA_UNI_PROMISC_MODE;
3042 val |= MVNETA_FORCE_UNI;
3043 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff);
3044 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff);
3046 /* Reject all Unicast addresses */
3047 port_cfg_reg &= ~MVNETA_UNI_PROMISC_MODE;
3048 val &= ~MVNETA_FORCE_UNI;
3051 mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg);
3052 mvreg_write(pp, MVNETA_TYPE_PRIO, val);
3055 /* register unicast and multicast addresses */
3056 static void mvneta_set_rx_mode(struct net_device *dev)
3058 struct mvneta_port *pp = netdev_priv(dev);
3059 struct netdev_hw_addr *ha;
3061 if (dev->flags & IFF_PROMISC) {
3062 /* Accept all: Multicast + Unicast */
3063 mvneta_rx_unicast_promisc_set(pp, 1);
3064 mvneta_set_ucast_table(pp, pp->rxq_def);
3065 mvneta_set_special_mcast_table(pp, pp->rxq_def);
3066 mvneta_set_other_mcast_table(pp, pp->rxq_def);
3068 /* Accept single Unicast */
3069 mvneta_rx_unicast_promisc_set(pp, 0);
3070 mvneta_set_ucast_table(pp, -1);
3071 mvneta_mac_addr_set(pp, dev->dev_addr, pp->rxq_def);
3073 if (dev->flags & IFF_ALLMULTI) {
3074 /* Accept all multicast */
3075 mvneta_set_special_mcast_table(pp, pp->rxq_def);
3076 mvneta_set_other_mcast_table(pp, pp->rxq_def);
3078 /* Accept only initialized multicast */
3079 mvneta_set_special_mcast_table(pp, -1);
3080 mvneta_set_other_mcast_table(pp, -1);
3082 if (!netdev_mc_empty(dev)) {
3083 netdev_for_each_mc_addr(ha, dev) {
3084 mvneta_mcast_addr_set(pp, ha->addr,
3092 /* Interrupt handling - the callback for request_irq() */
3093 static irqreturn_t mvneta_isr(int irq, void *dev_id)
3095 struct mvneta_port *pp = (struct mvneta_port *)dev_id;
3097 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
3098 napi_schedule(&pp->napi);
3103 /* Interrupt handling - the callback for request_percpu_irq() */
3104 static irqreturn_t mvneta_percpu_isr(int irq, void *dev_id)
3106 struct mvneta_pcpu_port *port = (struct mvneta_pcpu_port *)dev_id;
3108 disable_percpu_irq(port->pp->dev->irq);
3109 napi_schedule(&port->napi);
3114 static void mvneta_link_change(struct mvneta_port *pp)
3116 u32 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS);
3118 phylink_mac_change(pp->phylink, !!(gmac_stat & MVNETA_GMAC_LINK_UP));
3122 * Bits 0 - 7 of the causeRxTx register indicate that are transmitted
3123 * packets on the corresponding TXQ (Bit 0 is for TX queue 1).
3124 * Bits 8 -15 of the cause Rx Tx register indicate that are received
3125 * packets on the corresponding RXQ (Bit 8 is for RX queue 0).
3126 * Each CPU has its own causeRxTx register
3128 static int mvneta_poll(struct napi_struct *napi, int budget)
3133 struct mvneta_port *pp = netdev_priv(napi->dev);
3134 struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports);
3136 if (!netif_running(pp->dev)) {
3137 napi_complete(napi);
3141 /* Read cause register */
3142 cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE);
3143 if (cause_rx_tx & MVNETA_MISCINTR_INTR_MASK) {
3144 u32 cause_misc = mvreg_read(pp, MVNETA_INTR_MISC_CAUSE);
3146 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
3148 if (cause_misc & (MVNETA_CAUSE_PHY_STATUS_CHANGE |
3149 MVNETA_CAUSE_LINK_CHANGE))
3150 mvneta_link_change(pp);
3153 /* Release Tx descriptors */
3154 if (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL) {
3155 mvneta_tx_done_gbe(pp, (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL));
3156 cause_rx_tx &= ~MVNETA_TX_INTR_MASK_ALL;
3159 /* For the case where the last mvneta_poll did not process all
3162 cause_rx_tx |= pp->neta_armada3700 ? pp->cause_rx_tx :
3165 rx_queue = fls(((cause_rx_tx >> 8) & 0xff));
3167 rx_queue = rx_queue - 1;
3169 rx_done = mvneta_rx_hwbm(napi, pp, budget,
3170 &pp->rxqs[rx_queue]);
3172 rx_done = mvneta_rx_swbm(napi, pp, budget,
3173 &pp->rxqs[rx_queue]);
3176 if (rx_done < budget) {
3178 napi_complete_done(napi, rx_done);
3180 if (pp->neta_armada3700) {
3181 unsigned long flags;
3183 local_irq_save(flags);
3184 mvreg_write(pp, MVNETA_INTR_NEW_MASK,
3185 MVNETA_RX_INTR_MASK(rxq_number) |
3186 MVNETA_TX_INTR_MASK(txq_number) |
3187 MVNETA_MISCINTR_INTR_MASK);
3188 local_irq_restore(flags);
3190 enable_percpu_irq(pp->dev->irq, 0);
3194 if (pp->neta_armada3700)
3195 pp->cause_rx_tx = cause_rx_tx;
3197 port->cause_rx_tx = cause_rx_tx;
3202 static int mvneta_create_page_pool(struct mvneta_port *pp,
3203 struct mvneta_rx_queue *rxq, int size)
3205 struct bpf_prog *xdp_prog = READ_ONCE(pp->xdp_prog);
3206 struct page_pool_params pp_params = {
3208 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV,
3210 .nid = NUMA_NO_NODE,
3211 .dev = pp->dev->dev.parent,
3212 .dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE,
3213 .offset = pp->rx_offset_correction,
3214 .max_len = MVNETA_MAX_RX_BUF_SIZE,
3218 rxq->page_pool = page_pool_create(&pp_params);
3219 if (IS_ERR(rxq->page_pool)) {
3220 err = PTR_ERR(rxq->page_pool);
3221 rxq->page_pool = NULL;
3225 err = xdp_rxq_info_reg(&rxq->xdp_rxq, pp->dev, rxq->id);
3229 err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq, MEM_TYPE_PAGE_POOL,
3232 goto err_unregister_rxq;
3237 xdp_rxq_info_unreg(&rxq->xdp_rxq);
3239 page_pool_destroy(rxq->page_pool);
3240 rxq->page_pool = NULL;
3244 /* Handle rxq fill: allocates rxq skbs; called when initializing a port */
3245 static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq,
3250 err = mvneta_create_page_pool(pp, rxq, num);
3254 for (i = 0; i < num; i++) {
3255 memset(rxq->descs + i, 0, sizeof(struct mvneta_rx_desc));
3256 if (mvneta_rx_refill(pp, rxq->descs + i, rxq,
3259 "%s:rxq %d, %d of %d buffs filled\n",
3260 __func__, rxq->id, i, num);
3265 /* Add this number of RX descriptors as non occupied (ready to
3268 mvneta_rxq_non_occup_desc_add(pp, rxq, i);
3273 /* Free all packets pending transmit from all TXQs and reset TX port */
3274 static void mvneta_tx_reset(struct mvneta_port *pp)
3278 /* free the skb's in the tx ring */
3279 for (queue = 0; queue < txq_number; queue++)
3280 mvneta_txq_done_force(pp, &pp->txqs[queue]);
3282 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
3283 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
3286 static void mvneta_rx_reset(struct mvneta_port *pp)
3288 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
3289 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
3292 /* Rx/Tx queue initialization/cleanup methods */
3294 static int mvneta_rxq_sw_init(struct mvneta_port *pp,
3295 struct mvneta_rx_queue *rxq)
3297 rxq->size = pp->rx_ring_size;
3299 /* Allocate memory for RX descriptors */
3300 rxq->descs = dma_alloc_coherent(pp->dev->dev.parent,
3301 rxq->size * MVNETA_DESC_ALIGNED_SIZE,
3302 &rxq->descs_phys, GFP_KERNEL);
3306 rxq->last_desc = rxq->size - 1;
3311 static void mvneta_rxq_hw_init(struct mvneta_port *pp,
3312 struct mvneta_rx_queue *rxq)
3314 /* Set Rx descriptors queue starting address */
3315 mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys);
3316 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size);
3318 /* Set coalescing pkts and time */
3319 mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal);
3320 mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal);
3324 mvneta_rxq_offset_set(pp, rxq, 0);
3325 mvneta_rxq_buf_size_set(pp, rxq, PAGE_SIZE < SZ_64K ?
3326 MVNETA_MAX_RX_BUF_SIZE :
3327 MVNETA_RX_BUF_SIZE(pp->pkt_size));
3328 mvneta_rxq_bm_disable(pp, rxq);
3329 mvneta_rxq_fill(pp, rxq, rxq->size);
3332 mvneta_rxq_offset_set(pp, rxq,
3333 NET_SKB_PAD - pp->rx_offset_correction);
3335 mvneta_rxq_bm_enable(pp, rxq);
3336 /* Fill RXQ with buffers from RX pool */
3337 mvneta_rxq_long_pool_set(pp, rxq);
3338 mvneta_rxq_short_pool_set(pp, rxq);
3339 mvneta_rxq_non_occup_desc_add(pp, rxq, rxq->size);
3343 /* Create a specified RX queue */
3344 static int mvneta_rxq_init(struct mvneta_port *pp,
3345 struct mvneta_rx_queue *rxq)
3350 ret = mvneta_rxq_sw_init(pp, rxq);
3354 mvneta_rxq_hw_init(pp, rxq);
3359 /* Cleanup Rx queue */
3360 static void mvneta_rxq_deinit(struct mvneta_port *pp,
3361 struct mvneta_rx_queue *rxq)
3363 mvneta_rxq_drop_pkts(pp, rxq);
3366 dev_kfree_skb_any(rxq->skb);
3369 dma_free_coherent(pp->dev->dev.parent,
3370 rxq->size * MVNETA_DESC_ALIGNED_SIZE,
3376 rxq->next_desc_to_proc = 0;
3377 rxq->descs_phys = 0;
3378 rxq->first_to_refill = 0;
3379 rxq->refill_num = 0;
3384 static int mvneta_txq_sw_init(struct mvneta_port *pp,
3385 struct mvneta_tx_queue *txq)
3389 txq->size = pp->tx_ring_size;
3391 /* A queue must always have room for at least one skb.
3392 * Therefore, stop the queue when the free entries reaches
3393 * the maximum number of descriptors per skb.
3395 txq->tx_stop_threshold = txq->size - MVNETA_MAX_SKB_DESCS;
3396 txq->tx_wake_threshold = txq->tx_stop_threshold / 2;
3398 /* Allocate memory for TX descriptors */
3399 txq->descs = dma_alloc_coherent(pp->dev->dev.parent,
3400 txq->size * MVNETA_DESC_ALIGNED_SIZE,
3401 &txq->descs_phys, GFP_KERNEL);
3405 txq->last_desc = txq->size - 1;
3407 txq->buf = kmalloc_array(txq->size, sizeof(*txq->buf), GFP_KERNEL);
3409 dma_free_coherent(pp->dev->dev.parent,
3410 txq->size * MVNETA_DESC_ALIGNED_SIZE,
3411 txq->descs, txq->descs_phys);
3415 /* Allocate DMA buffers for TSO MAC/IP/TCP headers */
3416 txq->tso_hdrs = dma_alloc_coherent(pp->dev->dev.parent,
3417 txq->size * TSO_HEADER_SIZE,
3418 &txq->tso_hdrs_phys, GFP_KERNEL);
3419 if (!txq->tso_hdrs) {
3421 dma_free_coherent(pp->dev->dev.parent,
3422 txq->size * MVNETA_DESC_ALIGNED_SIZE,
3423 txq->descs, txq->descs_phys);
3427 /* Setup XPS mapping */
3429 cpu = txq->id % num_present_cpus();
3431 cpu = pp->rxq_def % num_present_cpus();
3432 cpumask_set_cpu(cpu, &txq->affinity_mask);
3433 netif_set_xps_queue(pp->dev, &txq->affinity_mask, txq->id);
3438 static void mvneta_txq_hw_init(struct mvneta_port *pp,
3439 struct mvneta_tx_queue *txq)
3441 /* Set maximum bandwidth for enabled TXQs */
3442 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff);
3443 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff);
3445 /* Set Tx descriptors queue starting address */
3446 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys);
3447 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size);
3449 mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal);
3452 /* Create and initialize a tx queue */
3453 static int mvneta_txq_init(struct mvneta_port *pp,
3454 struct mvneta_tx_queue *txq)
3458 ret = mvneta_txq_sw_init(pp, txq);
3462 mvneta_txq_hw_init(pp, txq);
3467 /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/
3468 static void mvneta_txq_sw_deinit(struct mvneta_port *pp,
3469 struct mvneta_tx_queue *txq)
3471 struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id);
3476 dma_free_coherent(pp->dev->dev.parent,
3477 txq->size * TSO_HEADER_SIZE,
3478 txq->tso_hdrs, txq->tso_hdrs_phys);
3480 dma_free_coherent(pp->dev->dev.parent,
3481 txq->size * MVNETA_DESC_ALIGNED_SIZE,
3482 txq->descs, txq->descs_phys);
3484 netdev_tx_reset_queue(nq);
3488 txq->next_desc_to_proc = 0;
3489 txq->descs_phys = 0;
3492 static void mvneta_txq_hw_deinit(struct mvneta_port *pp,
3493 struct mvneta_tx_queue *txq)
3495 /* Set minimum bandwidth for disabled TXQs */
3496 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0);
3497 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0);
3499 /* Set Tx descriptors queue starting address and size */
3500 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0);
3501 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0);
3504 static void mvneta_txq_deinit(struct mvneta_port *pp,
3505 struct mvneta_tx_queue *txq)
3507 mvneta_txq_sw_deinit(pp, txq);
3508 mvneta_txq_hw_deinit(pp, txq);
3511 /* Cleanup all Tx queues */
3512 static void mvneta_cleanup_txqs(struct mvneta_port *pp)
3516 for (queue = 0; queue < txq_number; queue++)
3517 mvneta_txq_deinit(pp, &pp->txqs[queue]);
3520 /* Cleanup all Rx queues */
3521 static void mvneta_cleanup_rxqs(struct mvneta_port *pp)
3525 for (queue = 0; queue < rxq_number; queue++)
3526 mvneta_rxq_deinit(pp, &pp->rxqs[queue]);
3530 /* Init all Rx queues */
3531 static int mvneta_setup_rxqs(struct mvneta_port *pp)
3535 for (queue = 0; queue < rxq_number; queue++) {
3536 int err = mvneta_rxq_init(pp, &pp->rxqs[queue]);
3539 netdev_err(pp->dev, "%s: can't create rxq=%d\n",
3541 mvneta_cleanup_rxqs(pp);
3549 /* Init all tx queues */
3550 static int mvneta_setup_txqs(struct mvneta_port *pp)
3554 for (queue = 0; queue < txq_number; queue++) {
3555 int err = mvneta_txq_init(pp, &pp->txqs[queue]);
3557 netdev_err(pp->dev, "%s: can't create txq=%d\n",
3559 mvneta_cleanup_txqs(pp);
3567 static int mvneta_comphy_init(struct mvneta_port *pp, phy_interface_t interface)
3571 ret = phy_set_mode_ext(pp->comphy, PHY_MODE_ETHERNET, interface);
3575 return phy_power_on(pp->comphy);
3578 static int mvneta_config_interface(struct mvneta_port *pp,
3579 phy_interface_t interface)
3584 if (interface == PHY_INTERFACE_MODE_SGMII ||
3585 interface == PHY_INTERFACE_MODE_1000BASEX ||
3586 interface == PHY_INTERFACE_MODE_2500BASEX) {
3587 ret = mvneta_comphy_init(pp, interface);
3590 switch (interface) {
3591 case PHY_INTERFACE_MODE_QSGMII:
3592 mvreg_write(pp, MVNETA_SERDES_CFG,
3593 MVNETA_QSGMII_SERDES_PROTO);
3596 case PHY_INTERFACE_MODE_SGMII:
3597 case PHY_INTERFACE_MODE_1000BASEX:
3598 mvreg_write(pp, MVNETA_SERDES_CFG,
3599 MVNETA_SGMII_SERDES_PROTO);
3602 case PHY_INTERFACE_MODE_2500BASEX:
3603 mvreg_write(pp, MVNETA_SERDES_CFG,
3604 MVNETA_HSGMII_SERDES_PROTO);
3611 pp->phy_interface = interface;
3616 static void mvneta_start_dev(struct mvneta_port *pp)
3620 WARN_ON(mvneta_config_interface(pp, pp->phy_interface));
3622 mvneta_max_rx_size_set(pp, pp->pkt_size);
3623 mvneta_txq_max_tx_size_set(pp, pp->pkt_size);
3625 /* start the Rx/Tx activity */
3626 mvneta_port_enable(pp);
3628 if (!pp->neta_armada3700) {
3629 /* Enable polling on the port */
3630 for_each_online_cpu(cpu) {
3631 struct mvneta_pcpu_port *port =
3632 per_cpu_ptr(pp->ports, cpu);
3634 napi_enable(&port->napi);
3637 napi_enable(&pp->napi);
3640 /* Unmask interrupts. It has to be done from each CPU */
3641 on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true);
3643 mvreg_write(pp, MVNETA_INTR_MISC_MASK,
3644 MVNETA_CAUSE_PHY_STATUS_CHANGE |
3645 MVNETA_CAUSE_LINK_CHANGE);
3647 phylink_start(pp->phylink);
3649 /* We may have called phy_speed_down before */
3650 phylink_speed_up(pp->phylink);
3652 netif_tx_start_all_queues(pp->dev);
3654 clear_bit(__MVNETA_DOWN, &pp->state);
3657 static void mvneta_stop_dev(struct mvneta_port *pp)
3661 set_bit(__MVNETA_DOWN, &pp->state);
3663 if (device_may_wakeup(&pp->dev->dev))
3664 phylink_speed_down(pp->phylink, false);
3666 phylink_stop(pp->phylink);
3668 if (!pp->neta_armada3700) {
3669 for_each_online_cpu(cpu) {
3670 struct mvneta_pcpu_port *port =
3671 per_cpu_ptr(pp->ports, cpu);
3673 napi_disable(&port->napi);
3676 napi_disable(&pp->napi);
3679 netif_carrier_off(pp->dev);
3681 mvneta_port_down(pp);
3682 netif_tx_stop_all_queues(pp->dev);
3684 /* Stop the port activity */
3685 mvneta_port_disable(pp);
3687 /* Clear all ethernet port interrupts */
3688 on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true);
3690 /* Mask all ethernet port interrupts */
3691 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
3693 mvneta_tx_reset(pp);
3694 mvneta_rx_reset(pp);
3696 WARN_ON(phy_power_off(pp->comphy));
3699 static void mvneta_percpu_enable(void *arg)
3701 struct mvneta_port *pp = arg;
3703 enable_percpu_irq(pp->dev->irq, IRQ_TYPE_NONE);
3706 static void mvneta_percpu_disable(void *arg)
3708 struct mvneta_port *pp = arg;
3710 disable_percpu_irq(pp->dev->irq);
3713 /* Change the device mtu */
3714 static int mvneta_change_mtu(struct net_device *dev, int mtu)
3716 struct mvneta_port *pp = netdev_priv(dev);
3719 if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu), 8)) {
3720 netdev_info(dev, "Illegal MTU value %d, rounding to %d\n",
3721 mtu, ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8));
3722 mtu = ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8);
3725 if (pp->xdp_prog && mtu > MVNETA_MAX_RX_BUF_SIZE) {
3726 netdev_info(dev, "Illegal MTU value %d for XDP mode\n", mtu);
3732 if (!netif_running(dev)) {
3734 mvneta_bm_update_mtu(pp, mtu);
3736 netdev_update_features(dev);
3740 /* The interface is running, so we have to force a
3741 * reallocation of the queues
3743 mvneta_stop_dev(pp);
3744 on_each_cpu(mvneta_percpu_disable, pp, true);
3746 mvneta_cleanup_txqs(pp);
3747 mvneta_cleanup_rxqs(pp);
3750 mvneta_bm_update_mtu(pp, mtu);
3752 pp->pkt_size = MVNETA_RX_PKT_SIZE(dev->mtu);
3754 ret = mvneta_setup_rxqs(pp);
3756 netdev_err(dev, "unable to setup rxqs after MTU change\n");
3760 ret = mvneta_setup_txqs(pp);
3762 netdev_err(dev, "unable to setup txqs after MTU change\n");
3766 on_each_cpu(mvneta_percpu_enable, pp, true);
3767 mvneta_start_dev(pp);
3769 netdev_update_features(dev);
3774 static netdev_features_t mvneta_fix_features(struct net_device *dev,
3775 netdev_features_t features)
3777 struct mvneta_port *pp = netdev_priv(dev);
3779 if (pp->tx_csum_limit && dev->mtu > pp->tx_csum_limit) {
3780 features &= ~(NETIF_F_IP_CSUM | NETIF_F_TSO);
3782 "Disable IP checksum for MTU greater than %dB\n",
3789 /* Get mac address */
3790 static void mvneta_get_mac_addr(struct mvneta_port *pp, unsigned char *addr)
3792 u32 mac_addr_l, mac_addr_h;
3794 mac_addr_l = mvreg_read(pp, MVNETA_MAC_ADDR_LOW);
3795 mac_addr_h = mvreg_read(pp, MVNETA_MAC_ADDR_HIGH);
3796 addr[0] = (mac_addr_h >> 24) & 0xFF;
3797 addr[1] = (mac_addr_h >> 16) & 0xFF;
3798 addr[2] = (mac_addr_h >> 8) & 0xFF;
3799 addr[3] = mac_addr_h & 0xFF;
3800 addr[4] = (mac_addr_l >> 8) & 0xFF;
3801 addr[5] = mac_addr_l & 0xFF;
3804 /* Handle setting mac address */
3805 static int mvneta_set_mac_addr(struct net_device *dev, void *addr)
3807 struct mvneta_port *pp = netdev_priv(dev);
3808 struct sockaddr *sockaddr = addr;
3811 ret = eth_prepare_mac_addr_change(dev, addr);
3814 /* Remove previous address table entry */
3815 mvneta_mac_addr_set(pp, dev->dev_addr, -1);
3817 /* Set new addr in hw */
3818 mvneta_mac_addr_set(pp, sockaddr->sa_data, pp->rxq_def);
3820 eth_commit_mac_addr_change(dev, addr);
3824 static void mvneta_validate(struct phylink_config *config,
3825 unsigned long *supported,
3826 struct phylink_link_state *state)
3828 struct net_device *ndev = to_net_dev(config->dev);
3829 struct mvneta_port *pp = netdev_priv(ndev);
3830 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
3832 /* We only support QSGMII, SGMII, 802.3z and RGMII modes */
3833 if (state->interface != PHY_INTERFACE_MODE_NA &&
3834 state->interface != PHY_INTERFACE_MODE_QSGMII &&
3835 state->interface != PHY_INTERFACE_MODE_SGMII &&
3836 !phy_interface_mode_is_8023z(state->interface) &&
3837 !phy_interface_mode_is_rgmii(state->interface)) {
3838 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
3842 /* Allow all the expected bits */
3843 phylink_set(mask, Autoneg);
3844 phylink_set_port_modes(mask);
3846 /* Asymmetric pause is unsupported */
3847 phylink_set(mask, Pause);
3849 /* Half-duplex at speeds higher than 100Mbit is unsupported */
3850 if (pp->comphy || state->interface != PHY_INTERFACE_MODE_2500BASEX) {
3851 phylink_set(mask, 1000baseT_Full);
3852 phylink_set(mask, 1000baseX_Full);
3854 if (pp->comphy || state->interface == PHY_INTERFACE_MODE_2500BASEX) {
3855 phylink_set(mask, 2500baseT_Full);
3856 phylink_set(mask, 2500baseX_Full);
3859 if (!phy_interface_mode_is_8023z(state->interface)) {
3860 /* 10M and 100M are only supported in non-802.3z mode */
3861 phylink_set(mask, 10baseT_Half);
3862 phylink_set(mask, 10baseT_Full);
3863 phylink_set(mask, 100baseT_Half);
3864 phylink_set(mask, 100baseT_Full);
3867 bitmap_and(supported, supported, mask,
3868 __ETHTOOL_LINK_MODE_MASK_NBITS);
3869 bitmap_and(state->advertising, state->advertising, mask,
3870 __ETHTOOL_LINK_MODE_MASK_NBITS);
3872 /* We can only operate at 2500BaseX or 1000BaseX. If requested
3873 * to advertise both, only report advertising at 2500BaseX.
3875 phylink_helper_basex_speed(state);
3878 static void mvneta_mac_pcs_get_state(struct phylink_config *config,
3879 struct phylink_link_state *state)
3881 struct net_device *ndev = to_net_dev(config->dev);
3882 struct mvneta_port *pp = netdev_priv(ndev);
3885 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS);
3887 if (gmac_stat & MVNETA_GMAC_SPEED_1000)
3889 state->interface == PHY_INTERFACE_MODE_2500BASEX ?
3890 SPEED_2500 : SPEED_1000;
3891 else if (gmac_stat & MVNETA_GMAC_SPEED_100)
3892 state->speed = SPEED_100;
3894 state->speed = SPEED_10;
3896 state->an_complete = !!(gmac_stat & MVNETA_GMAC_AN_COMPLETE);
3897 state->link = !!(gmac_stat & MVNETA_GMAC_LINK_UP);
3898 state->duplex = !!(gmac_stat & MVNETA_GMAC_FULL_DUPLEX);
3901 if (gmac_stat & MVNETA_GMAC_RX_FLOW_CTRL_ENABLE)
3902 state->pause |= MLO_PAUSE_RX;
3903 if (gmac_stat & MVNETA_GMAC_TX_FLOW_CTRL_ENABLE)
3904 state->pause |= MLO_PAUSE_TX;
3907 static void mvneta_mac_an_restart(struct phylink_config *config)
3909 struct net_device *ndev = to_net_dev(config->dev);
3910 struct mvneta_port *pp = netdev_priv(ndev);
3911 u32 gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
3913 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
3914 gmac_an | MVNETA_GMAC_INBAND_RESTART_AN);
3915 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
3916 gmac_an & ~MVNETA_GMAC_INBAND_RESTART_AN);
3919 static void mvneta_mac_config(struct phylink_config *config, unsigned int mode,
3920 const struct phylink_link_state *state)
3922 struct net_device *ndev = to_net_dev(config->dev);
3923 struct mvneta_port *pp = netdev_priv(ndev);
3924 u32 new_ctrl0, gmac_ctrl0 = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
3925 u32 new_ctrl2, gmac_ctrl2 = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
3926 u32 new_ctrl4, gmac_ctrl4 = mvreg_read(pp, MVNETA_GMAC_CTRL_4);
3927 u32 new_clk, gmac_clk = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER);
3928 u32 new_an, gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
3930 new_ctrl0 = gmac_ctrl0 & ~MVNETA_GMAC0_PORT_1000BASE_X;
3931 new_ctrl2 = gmac_ctrl2 & ~(MVNETA_GMAC2_INBAND_AN_ENABLE |
3932 MVNETA_GMAC2_PORT_RESET);
3933 new_ctrl4 = gmac_ctrl4 & ~(MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE);
3934 new_clk = gmac_clk & ~MVNETA_GMAC_1MS_CLOCK_ENABLE;
3935 new_an = gmac_an & ~(MVNETA_GMAC_INBAND_AN_ENABLE |
3936 MVNETA_GMAC_INBAND_RESTART_AN |
3937 MVNETA_GMAC_AN_SPEED_EN |
3938 MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL |
3939 MVNETA_GMAC_AN_FLOW_CTRL_EN |
3940 MVNETA_GMAC_AN_DUPLEX_EN);
3942 /* Even though it might look weird, when we're configured in
3943 * SGMII or QSGMII mode, the RGMII bit needs to be set.
3945 new_ctrl2 |= MVNETA_GMAC2_PORT_RGMII;
3947 if (state->interface == PHY_INTERFACE_MODE_QSGMII ||
3948 state->interface == PHY_INTERFACE_MODE_SGMII ||
3949 phy_interface_mode_is_8023z(state->interface))
3950 new_ctrl2 |= MVNETA_GMAC2_PCS_ENABLE;
3952 if (phylink_test(state->advertising, Pause))
3953 new_an |= MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL;
3955 if (!phylink_autoneg_inband(mode)) {
3956 /* Phy or fixed speed - nothing to do, leave the
3957 * configured speed, duplex and flow control as-is.
3959 } else if (state->interface == PHY_INTERFACE_MODE_SGMII) {
3960 /* SGMII mode receives the state from the PHY */
3961 new_ctrl2 |= MVNETA_GMAC2_INBAND_AN_ENABLE;
3962 new_clk |= MVNETA_GMAC_1MS_CLOCK_ENABLE;
3963 new_an = (new_an & ~(MVNETA_GMAC_FORCE_LINK_DOWN |
3964 MVNETA_GMAC_FORCE_LINK_PASS |
3965 MVNETA_GMAC_CONFIG_MII_SPEED |
3966 MVNETA_GMAC_CONFIG_GMII_SPEED |
3967 MVNETA_GMAC_CONFIG_FULL_DUPLEX)) |
3968 MVNETA_GMAC_INBAND_AN_ENABLE |
3969 MVNETA_GMAC_AN_SPEED_EN |
3970 MVNETA_GMAC_AN_DUPLEX_EN;
3972 /* 802.3z negotiation - only 1000base-X */
3973 new_ctrl0 |= MVNETA_GMAC0_PORT_1000BASE_X;
3974 new_clk |= MVNETA_GMAC_1MS_CLOCK_ENABLE;
3975 new_an = (new_an & ~(MVNETA_GMAC_FORCE_LINK_DOWN |
3976 MVNETA_GMAC_FORCE_LINK_PASS |
3977 MVNETA_GMAC_CONFIG_MII_SPEED)) |
3978 MVNETA_GMAC_INBAND_AN_ENABLE |
3979 MVNETA_GMAC_CONFIG_GMII_SPEED |
3980 /* The MAC only supports FD mode */
3981 MVNETA_GMAC_CONFIG_FULL_DUPLEX;
3983 if (state->pause & MLO_PAUSE_AN && state->an_enabled)
3984 new_an |= MVNETA_GMAC_AN_FLOW_CTRL_EN;
3987 /* Armada 370 documentation says we can only change the port mode
3988 * and in-band enable when the link is down, so force it down
3989 * while making these changes. We also do this for GMAC_CTRL2 */
3990 if ((new_ctrl0 ^ gmac_ctrl0) & MVNETA_GMAC0_PORT_1000BASE_X ||
3991 (new_ctrl2 ^ gmac_ctrl2) & MVNETA_GMAC2_INBAND_AN_ENABLE ||
3992 (new_an ^ gmac_an) & MVNETA_GMAC_INBAND_AN_ENABLE) {
3993 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
3994 (gmac_an & ~MVNETA_GMAC_FORCE_LINK_PASS) |
3995 MVNETA_GMAC_FORCE_LINK_DOWN);
3999 /* When at 2.5G, the link partner can send frames with shortened
4002 if (state->interface == PHY_INTERFACE_MODE_2500BASEX)
4003 new_ctrl4 |= MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE;
4005 if (pp->phy_interface != state->interface) {
4007 WARN_ON(phy_power_off(pp->comphy));
4008 WARN_ON(mvneta_config_interface(pp, state->interface));
4011 if (new_ctrl0 != gmac_ctrl0)
4012 mvreg_write(pp, MVNETA_GMAC_CTRL_0, new_ctrl0);
4013 if (new_ctrl2 != gmac_ctrl2)
4014 mvreg_write(pp, MVNETA_GMAC_CTRL_2, new_ctrl2);
4015 if (new_ctrl4 != gmac_ctrl4)
4016 mvreg_write(pp, MVNETA_GMAC_CTRL_4, new_ctrl4);
4017 if (new_clk != gmac_clk)
4018 mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, new_clk);
4019 if (new_an != gmac_an)
4020 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, new_an);
4022 if (gmac_ctrl2 & MVNETA_GMAC2_PORT_RESET) {
4023 while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) &
4024 MVNETA_GMAC2_PORT_RESET) != 0)
4029 static void mvneta_set_eee(struct mvneta_port *pp, bool enable)
4033 lpi_ctl1 = mvreg_read(pp, MVNETA_LPI_CTRL_1);
4035 lpi_ctl1 |= MVNETA_LPI_REQUEST_ENABLE;
4037 lpi_ctl1 &= ~MVNETA_LPI_REQUEST_ENABLE;
4038 mvreg_write(pp, MVNETA_LPI_CTRL_1, lpi_ctl1);
4041 static void mvneta_mac_link_down(struct phylink_config *config,
4042 unsigned int mode, phy_interface_t interface)
4044 struct net_device *ndev = to_net_dev(config->dev);
4045 struct mvneta_port *pp = netdev_priv(ndev);
4048 mvneta_port_down(pp);
4050 if (!phylink_autoneg_inband(mode)) {
4051 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
4052 val &= ~MVNETA_GMAC_FORCE_LINK_PASS;
4053 val |= MVNETA_GMAC_FORCE_LINK_DOWN;
4054 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
4057 pp->eee_active = false;
4058 mvneta_set_eee(pp, false);
4061 static void mvneta_mac_link_up(struct phylink_config *config,
4062 struct phy_device *phy,
4063 unsigned int mode, phy_interface_t interface,
4064 int speed, int duplex,
4065 bool tx_pause, bool rx_pause)
4067 struct net_device *ndev = to_net_dev(config->dev);
4068 struct mvneta_port *pp = netdev_priv(ndev);
4071 if (!phylink_autoneg_inband(mode)) {
4072 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
4073 val &= ~(MVNETA_GMAC_FORCE_LINK_DOWN |
4074 MVNETA_GMAC_CONFIG_MII_SPEED |
4075 MVNETA_GMAC_CONFIG_GMII_SPEED |
4076 MVNETA_GMAC_CONFIG_FLOW_CTRL |
4077 MVNETA_GMAC_CONFIG_FULL_DUPLEX);
4078 val |= MVNETA_GMAC_FORCE_LINK_PASS;
4080 if (speed == SPEED_1000 || speed == SPEED_2500)
4081 val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
4082 else if (speed == SPEED_100)
4083 val |= MVNETA_GMAC_CONFIG_MII_SPEED;
4085 if (duplex == DUPLEX_FULL)
4086 val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
4088 if (tx_pause || rx_pause)
4089 val |= MVNETA_GMAC_CONFIG_FLOW_CTRL;
4091 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
4093 /* When inband doesn't cover flow control or flow control is
4094 * disabled, we need to manually configure it. This bit will
4095 * only have effect if MVNETA_GMAC_AN_FLOW_CTRL_EN is unset.
4097 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
4098 val &= ~MVNETA_GMAC_CONFIG_FLOW_CTRL;
4100 if (tx_pause || rx_pause)
4101 val |= MVNETA_GMAC_CONFIG_FLOW_CTRL;
4103 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
4108 if (phy && pp->eee_enabled) {
4109 pp->eee_active = phy_init_eee(phy, 0) >= 0;
4110 mvneta_set_eee(pp, pp->eee_active && pp->tx_lpi_enabled);
4114 static const struct phylink_mac_ops mvneta_phylink_ops = {
4115 .validate = mvneta_validate,
4116 .mac_pcs_get_state = mvneta_mac_pcs_get_state,
4117 .mac_an_restart = mvneta_mac_an_restart,
4118 .mac_config = mvneta_mac_config,
4119 .mac_link_down = mvneta_mac_link_down,
4120 .mac_link_up = mvneta_mac_link_up,
4123 static int mvneta_mdio_probe(struct mvneta_port *pp)
4125 struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL };
4126 int err = phylink_of_phy_connect(pp->phylink, pp->dn, 0);
4129 netdev_err(pp->dev, "could not attach PHY: %d\n", err);
4131 phylink_ethtool_get_wol(pp->phylink, &wol);
4132 device_set_wakeup_capable(&pp->dev->dev, !!wol.supported);
4134 /* PHY WoL may be enabled but device wakeup disabled */
4136 device_set_wakeup_enable(&pp->dev->dev, !!wol.wolopts);
4141 static void mvneta_mdio_remove(struct mvneta_port *pp)
4143 phylink_disconnect_phy(pp->phylink);
4146 /* Electing a CPU must be done in an atomic way: it should be done
4147 * after or before the removal/insertion of a CPU and this function is
4150 static void mvneta_percpu_elect(struct mvneta_port *pp)
4152 int elected_cpu = 0, max_cpu, cpu, i = 0;
4154 /* Use the cpu associated to the rxq when it is online, in all
4155 * the other cases, use the cpu 0 which can't be offline.
4157 if (cpu_online(pp->rxq_def))
4158 elected_cpu = pp->rxq_def;
4160 max_cpu = num_present_cpus();
4162 for_each_online_cpu(cpu) {
4163 int rxq_map = 0, txq_map = 0;
4166 for (rxq = 0; rxq < rxq_number; rxq++)
4167 if ((rxq % max_cpu) == cpu)
4168 rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq);
4170 if (cpu == elected_cpu)
4171 /* Map the default receive queue queue to the
4174 rxq_map |= MVNETA_CPU_RXQ_ACCESS(pp->rxq_def);
4176 /* We update the TX queue map only if we have one
4177 * queue. In this case we associate the TX queue to
4178 * the CPU bound to the default RX queue
4180 if (txq_number == 1)
4181 txq_map = (cpu == elected_cpu) ?
4182 MVNETA_CPU_TXQ_ACCESS(1) : 0;
4184 txq_map = mvreg_read(pp, MVNETA_CPU_MAP(cpu)) &
4185 MVNETA_CPU_TXQ_ACCESS_ALL_MASK;
4187 mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map);
4189 /* Update the interrupt mask on each CPU according the
4192 smp_call_function_single(cpu, mvneta_percpu_unmask_interrupt,
4199 static int mvneta_cpu_online(unsigned int cpu, struct hlist_node *node)
4202 struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port,
4204 struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu);
4207 spin_lock(&pp->lock);
4209 * Configuring the driver for a new CPU while the driver is
4210 * stopping is racy, so just avoid it.
4212 if (pp->is_stopped) {
4213 spin_unlock(&pp->lock);
4216 netif_tx_stop_all_queues(pp->dev);
4219 * We have to synchronise on tha napi of each CPU except the one
4220 * just being woken up
4222 for_each_online_cpu(other_cpu) {
4223 if (other_cpu != cpu) {
4224 struct mvneta_pcpu_port *other_port =
4225 per_cpu_ptr(pp->ports, other_cpu);
4227 napi_synchronize(&other_port->napi);
4231 /* Mask all ethernet port interrupts */
4232 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
4233 napi_enable(&port->napi);
4236 * Enable per-CPU interrupts on the CPU that is
4239 mvneta_percpu_enable(pp);
4242 * Enable per-CPU interrupt on the one CPU we care
4245 mvneta_percpu_elect(pp);
4247 /* Unmask all ethernet port interrupts */
4248 on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true);
4249 mvreg_write(pp, MVNETA_INTR_MISC_MASK,
4250 MVNETA_CAUSE_PHY_STATUS_CHANGE |
4251 MVNETA_CAUSE_LINK_CHANGE);
4252 netif_tx_start_all_queues(pp->dev);
4253 spin_unlock(&pp->lock);
4257 static int mvneta_cpu_down_prepare(unsigned int cpu, struct hlist_node *node)
4259 struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port,
4261 struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu);
4264 * Thanks to this lock we are sure that any pending cpu election is
4267 spin_lock(&pp->lock);
4268 /* Mask all ethernet port interrupts */
4269 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
4270 spin_unlock(&pp->lock);
4272 napi_synchronize(&port->napi);
4273 napi_disable(&port->napi);
4274 /* Disable per-CPU interrupts on the CPU that is brought down. */
4275 mvneta_percpu_disable(pp);
4279 static int mvneta_cpu_dead(unsigned int cpu, struct hlist_node *node)
4281 struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port,
4284 /* Check if a new CPU must be elected now this on is down */
4285 spin_lock(&pp->lock);
4286 mvneta_percpu_elect(pp);
4287 spin_unlock(&pp->lock);
4288 /* Unmask all ethernet port interrupts */
4289 on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true);
4290 mvreg_write(pp, MVNETA_INTR_MISC_MASK,
4291 MVNETA_CAUSE_PHY_STATUS_CHANGE |
4292 MVNETA_CAUSE_LINK_CHANGE);
4293 netif_tx_start_all_queues(pp->dev);
4297 static int mvneta_open(struct net_device *dev)
4299 struct mvneta_port *pp = netdev_priv(dev);
4302 pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu);
4304 ret = mvneta_setup_rxqs(pp);
4308 ret = mvneta_setup_txqs(pp);
4310 goto err_cleanup_rxqs;
4312 /* Connect to port interrupt line */
4313 if (pp->neta_armada3700)
4314 ret = request_irq(pp->dev->irq, mvneta_isr, 0,
4317 ret = request_percpu_irq(pp->dev->irq, mvneta_percpu_isr,
4318 dev->name, pp->ports);
4320 netdev_err(pp->dev, "cannot request irq %d\n", pp->dev->irq);
4321 goto err_cleanup_txqs;
4324 if (!pp->neta_armada3700) {
4325 /* Enable per-CPU interrupt on all the CPU to handle our RX
4328 on_each_cpu(mvneta_percpu_enable, pp, true);
4330 pp->is_stopped = false;
4331 /* Register a CPU notifier to handle the case where our CPU
4332 * might be taken offline.
4334 ret = cpuhp_state_add_instance_nocalls(online_hpstate,
4339 ret = cpuhp_state_add_instance_nocalls(CPUHP_NET_MVNETA_DEAD,
4342 goto err_free_online_hp;
4345 ret = mvneta_mdio_probe(pp);
4347 netdev_err(dev, "cannot probe MDIO bus\n");
4348 goto err_free_dead_hp;
4351 mvneta_start_dev(pp);
4356 if (!pp->neta_armada3700)
4357 cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD,
4360 if (!pp->neta_armada3700)
4361 cpuhp_state_remove_instance_nocalls(online_hpstate,
4364 if (pp->neta_armada3700) {
4365 free_irq(pp->dev->irq, pp);
4367 on_each_cpu(mvneta_percpu_disable, pp, true);
4368 free_percpu_irq(pp->dev->irq, pp->ports);
4371 mvneta_cleanup_txqs(pp);
4373 mvneta_cleanup_rxqs(pp);
4377 /* Stop the port, free port interrupt line */
4378 static int mvneta_stop(struct net_device *dev)
4380 struct mvneta_port *pp = netdev_priv(dev);
4382 if (!pp->neta_armada3700) {
4383 /* Inform that we are stopping so we don't want to setup the
4384 * driver for new CPUs in the notifiers. The code of the
4385 * notifier for CPU online is protected by the same spinlock,
4386 * so when we get the lock, the notifer work is done.
4388 spin_lock(&pp->lock);
4389 pp->is_stopped = true;
4390 spin_unlock(&pp->lock);
4392 mvneta_stop_dev(pp);
4393 mvneta_mdio_remove(pp);
4395 cpuhp_state_remove_instance_nocalls(online_hpstate,
4397 cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD,
4399 on_each_cpu(mvneta_percpu_disable, pp, true);
4400 free_percpu_irq(dev->irq, pp->ports);
4402 mvneta_stop_dev(pp);
4403 mvneta_mdio_remove(pp);
4404 free_irq(dev->irq, pp);
4407 mvneta_cleanup_rxqs(pp);
4408 mvneta_cleanup_txqs(pp);
4413 static int mvneta_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4415 struct mvneta_port *pp = netdev_priv(dev);
4417 return phylink_mii_ioctl(pp->phylink, ifr, cmd);
4420 static int mvneta_xdp_setup(struct net_device *dev, struct bpf_prog *prog,
4421 struct netlink_ext_ack *extack)
4423 bool need_update, running = netif_running(dev);
4424 struct mvneta_port *pp = netdev_priv(dev);
4425 struct bpf_prog *old_prog;
4427 if (prog && dev->mtu > MVNETA_MAX_RX_BUF_SIZE) {
4428 NL_SET_ERR_MSG_MOD(extack, "Jumbo frames not supported on XDP");
4433 NL_SET_ERR_MSG_MOD(extack,
4434 "Hardware Buffer Management not supported on XDP");
4438 need_update = !!pp->xdp_prog != !!prog;
4439 if (running && need_update)
4442 old_prog = xchg(&pp->xdp_prog, prog);
4444 bpf_prog_put(old_prog);
4446 if (running && need_update)
4447 return mvneta_open(dev);
4452 static int mvneta_xdp(struct net_device *dev, struct netdev_bpf *xdp)
4454 struct mvneta_port *pp = netdev_priv(dev);
4456 switch (xdp->command) {
4457 case XDP_SETUP_PROG:
4458 return mvneta_xdp_setup(dev, xdp->prog, xdp->extack);
4459 case XDP_QUERY_PROG:
4460 xdp->prog_id = pp->xdp_prog ? pp->xdp_prog->aux->id : 0;
4467 /* Ethtool methods */
4469 /* Set link ksettings (phy address, speed) for ethtools */
4471 mvneta_ethtool_set_link_ksettings(struct net_device *ndev,
4472 const struct ethtool_link_ksettings *cmd)
4474 struct mvneta_port *pp = netdev_priv(ndev);
4476 return phylink_ethtool_ksettings_set(pp->phylink, cmd);
4479 /* Get link ksettings for ethtools */
4481 mvneta_ethtool_get_link_ksettings(struct net_device *ndev,
4482 struct ethtool_link_ksettings *cmd)
4484 struct mvneta_port *pp = netdev_priv(ndev);
4486 return phylink_ethtool_ksettings_get(pp->phylink, cmd);
4489 static int mvneta_ethtool_nway_reset(struct net_device *dev)
4491 struct mvneta_port *pp = netdev_priv(dev);
4493 return phylink_ethtool_nway_reset(pp->phylink);
4496 /* Set interrupt coalescing for ethtools */
4497 static int mvneta_ethtool_set_coalesce(struct net_device *dev,
4498 struct ethtool_coalesce *c)
4500 struct mvneta_port *pp = netdev_priv(dev);
4503 for (queue = 0; queue < rxq_number; queue++) {
4504 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
4505 rxq->time_coal = c->rx_coalesce_usecs;
4506 rxq->pkts_coal = c->rx_max_coalesced_frames;
4507 mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal);
4508 mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal);
4511 for (queue = 0; queue < txq_number; queue++) {
4512 struct mvneta_tx_queue *txq = &pp->txqs[queue];
4513 txq->done_pkts_coal = c->tx_max_coalesced_frames;
4514 mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal);
4520 /* get coalescing for ethtools */
4521 static int mvneta_ethtool_get_coalesce(struct net_device *dev,
4522 struct ethtool_coalesce *c)
4524 struct mvneta_port *pp = netdev_priv(dev);
4526 c->rx_coalesce_usecs = pp->rxqs[0].time_coal;
4527 c->rx_max_coalesced_frames = pp->rxqs[0].pkts_coal;
4529 c->tx_max_coalesced_frames = pp->txqs[0].done_pkts_coal;
4534 static void mvneta_ethtool_get_drvinfo(struct net_device *dev,
4535 struct ethtool_drvinfo *drvinfo)
4537 strlcpy(drvinfo->driver, MVNETA_DRIVER_NAME,
4538 sizeof(drvinfo->driver));
4539 strlcpy(drvinfo->version, MVNETA_DRIVER_VERSION,
4540 sizeof(drvinfo->version));
4541 strlcpy(drvinfo->bus_info, dev_name(&dev->dev),
4542 sizeof(drvinfo->bus_info));
4546 static void mvneta_ethtool_get_ringparam(struct net_device *netdev,
4547 struct ethtool_ringparam *ring)
4549 struct mvneta_port *pp = netdev_priv(netdev);
4551 ring->rx_max_pending = MVNETA_MAX_RXD;
4552 ring->tx_max_pending = MVNETA_MAX_TXD;
4553 ring->rx_pending = pp->rx_ring_size;
4554 ring->tx_pending = pp->tx_ring_size;
4557 static int mvneta_ethtool_set_ringparam(struct net_device *dev,
4558 struct ethtool_ringparam *ring)
4560 struct mvneta_port *pp = netdev_priv(dev);
4562 if ((ring->rx_pending == 0) || (ring->tx_pending == 0))
4564 pp->rx_ring_size = ring->rx_pending < MVNETA_MAX_RXD ?
4565 ring->rx_pending : MVNETA_MAX_RXD;
4567 pp->tx_ring_size = clamp_t(u16, ring->tx_pending,
4568 MVNETA_MAX_SKB_DESCS * 2, MVNETA_MAX_TXD);
4569 if (pp->tx_ring_size != ring->tx_pending)
4570 netdev_warn(dev, "TX queue size set to %u (requested %u)\n",
4571 pp->tx_ring_size, ring->tx_pending);
4573 if (netif_running(dev)) {
4575 if (mvneta_open(dev)) {
4577 "error on opening device after ring param change\n");
4585 static void mvneta_ethtool_get_pauseparam(struct net_device *dev,
4586 struct ethtool_pauseparam *pause)
4588 struct mvneta_port *pp = netdev_priv(dev);
4590 phylink_ethtool_get_pauseparam(pp->phylink, pause);
4593 static int mvneta_ethtool_set_pauseparam(struct net_device *dev,
4594 struct ethtool_pauseparam *pause)
4596 struct mvneta_port *pp = netdev_priv(dev);
4598 return phylink_ethtool_set_pauseparam(pp->phylink, pause);
4601 static void mvneta_ethtool_get_strings(struct net_device *netdev, u32 sset,
4604 if (sset == ETH_SS_STATS) {
4607 for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++)
4608 memcpy(data + i * ETH_GSTRING_LEN,
4609 mvneta_statistics[i].name, ETH_GSTRING_LEN);
4614 mvneta_ethtool_update_pcpu_stats(struct mvneta_port *pp,
4615 struct mvneta_ethtool_stats *es)
4620 for_each_possible_cpu(cpu) {
4621 struct mvneta_pcpu_stats *stats;
4622 u64 skb_alloc_error;
4632 stats = per_cpu_ptr(pp->stats, cpu);
4634 start = u64_stats_fetch_begin_irq(&stats->syncp);
4635 skb_alloc_error = stats->es.skb_alloc_error;
4636 refill_error = stats->es.refill_error;
4637 xdp_redirect = stats->es.ps.xdp_redirect;
4638 xdp_pass = stats->es.ps.xdp_pass;
4639 xdp_drop = stats->es.ps.xdp_drop;
4640 xdp_xmit = stats->es.ps.xdp_xmit;
4641 xdp_xmit_err = stats->es.ps.xdp_xmit_err;
4642 xdp_tx = stats->es.ps.xdp_tx;
4643 xdp_tx_err = stats->es.ps.xdp_tx_err;
4644 } while (u64_stats_fetch_retry_irq(&stats->syncp, start));
4646 es->skb_alloc_error += skb_alloc_error;
4647 es->refill_error += refill_error;
4648 es->ps.xdp_redirect += xdp_redirect;
4649 es->ps.xdp_pass += xdp_pass;
4650 es->ps.xdp_drop += xdp_drop;
4651 es->ps.xdp_xmit += xdp_xmit;
4652 es->ps.xdp_xmit_err += xdp_xmit_err;
4653 es->ps.xdp_tx += xdp_tx;
4654 es->ps.xdp_tx_err += xdp_tx_err;
4658 static void mvneta_ethtool_update_stats(struct mvneta_port *pp)
4660 struct mvneta_ethtool_stats stats = {};
4661 const struct mvneta_statistic *s;
4662 void __iomem *base = pp->base;
4667 mvneta_ethtool_update_pcpu_stats(pp, &stats);
4668 for (i = 0, s = mvneta_statistics;
4669 s < mvneta_statistics + ARRAY_SIZE(mvneta_statistics);
4673 val = readl_relaxed(base + s->offset);
4674 pp->ethtool_stats[i] += val;
4677 /* Docs say to read low 32-bit then high */
4678 low = readl_relaxed(base + s->offset);
4679 high = readl_relaxed(base + s->offset + 4);
4680 val = (u64)high << 32 | low;
4681 pp->ethtool_stats[i] += val;
4684 switch (s->offset) {
4685 case ETHTOOL_STAT_EEE_WAKEUP:
4686 val = phylink_get_eee_err(pp->phylink);
4687 pp->ethtool_stats[i] += val;
4689 case ETHTOOL_STAT_SKB_ALLOC_ERR:
4690 pp->ethtool_stats[i] = stats.skb_alloc_error;
4692 case ETHTOOL_STAT_REFILL_ERR:
4693 pp->ethtool_stats[i] = stats.refill_error;
4695 case ETHTOOL_XDP_REDIRECT:
4696 pp->ethtool_stats[i] = stats.ps.xdp_redirect;
4698 case ETHTOOL_XDP_PASS:
4699 pp->ethtool_stats[i] = stats.ps.xdp_pass;
4701 case ETHTOOL_XDP_DROP:
4702 pp->ethtool_stats[i] = stats.ps.xdp_drop;
4704 case ETHTOOL_XDP_TX:
4705 pp->ethtool_stats[i] = stats.ps.xdp_tx;
4707 case ETHTOOL_XDP_TX_ERR:
4708 pp->ethtool_stats[i] = stats.ps.xdp_tx_err;
4710 case ETHTOOL_XDP_XMIT:
4711 pp->ethtool_stats[i] = stats.ps.xdp_xmit;
4713 case ETHTOOL_XDP_XMIT_ERR:
4714 pp->ethtool_stats[i] = stats.ps.xdp_xmit_err;
4722 static void mvneta_ethtool_get_stats(struct net_device *dev,
4723 struct ethtool_stats *stats, u64 *data)
4725 struct mvneta_port *pp = netdev_priv(dev);
4728 mvneta_ethtool_update_stats(pp);
4730 for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++)
4731 *data++ = pp->ethtool_stats[i];
4734 static int mvneta_ethtool_get_sset_count(struct net_device *dev, int sset)
4736 if (sset == ETH_SS_STATS)
4737 return ARRAY_SIZE(mvneta_statistics);
4741 static u32 mvneta_ethtool_get_rxfh_indir_size(struct net_device *dev)
4743 return MVNETA_RSS_LU_TABLE_SIZE;
4746 static int mvneta_ethtool_get_rxnfc(struct net_device *dev,
4747 struct ethtool_rxnfc *info,
4748 u32 *rules __always_unused)
4750 switch (info->cmd) {
4751 case ETHTOOL_GRXRINGS:
4752 info->data = rxq_number;
4761 static int mvneta_config_rss(struct mvneta_port *pp)
4766 netif_tx_stop_all_queues(pp->dev);
4768 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
4770 if (!pp->neta_armada3700) {
4771 /* We have to synchronise on the napi of each CPU */
4772 for_each_online_cpu(cpu) {
4773 struct mvneta_pcpu_port *pcpu_port =
4774 per_cpu_ptr(pp->ports, cpu);
4776 napi_synchronize(&pcpu_port->napi);
4777 napi_disable(&pcpu_port->napi);
4780 napi_synchronize(&pp->napi);
4781 napi_disable(&pp->napi);
4784 pp->rxq_def = pp->indir[0];
4786 /* Update unicast mapping */
4787 mvneta_set_rx_mode(pp->dev);
4789 /* Update val of portCfg register accordingly with all RxQueue types */
4790 val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def);
4791 mvreg_write(pp, MVNETA_PORT_CONFIG, val);
4793 /* Update the elected CPU matching the new rxq_def */
4794 spin_lock(&pp->lock);
4795 mvneta_percpu_elect(pp);
4796 spin_unlock(&pp->lock);
4798 if (!pp->neta_armada3700) {
4799 /* We have to synchronise on the napi of each CPU */
4800 for_each_online_cpu(cpu) {
4801 struct mvneta_pcpu_port *pcpu_port =
4802 per_cpu_ptr(pp->ports, cpu);
4804 napi_enable(&pcpu_port->napi);
4807 napi_enable(&pp->napi);
4810 netif_tx_start_all_queues(pp->dev);
4815 static int mvneta_ethtool_set_rxfh(struct net_device *dev, const u32 *indir,
4816 const u8 *key, const u8 hfunc)
4818 struct mvneta_port *pp = netdev_priv(dev);
4820 /* Current code for Armada 3700 doesn't support RSS features yet */
4821 if (pp->neta_armada3700)
4824 /* We require at least one supported parameter to be changed
4825 * and no change in any of the unsupported parameters
4828 (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP))
4834 memcpy(pp->indir, indir, MVNETA_RSS_LU_TABLE_SIZE);
4836 return mvneta_config_rss(pp);
4839 static int mvneta_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
4842 struct mvneta_port *pp = netdev_priv(dev);
4844 /* Current code for Armada 3700 doesn't support RSS features yet */
4845 if (pp->neta_armada3700)
4849 *hfunc = ETH_RSS_HASH_TOP;
4854 memcpy(indir, pp->indir, MVNETA_RSS_LU_TABLE_SIZE);
4859 static void mvneta_ethtool_get_wol(struct net_device *dev,
4860 struct ethtool_wolinfo *wol)
4862 struct mvneta_port *pp = netdev_priv(dev);
4864 phylink_ethtool_get_wol(pp->phylink, wol);
4867 static int mvneta_ethtool_set_wol(struct net_device *dev,
4868 struct ethtool_wolinfo *wol)
4870 struct mvneta_port *pp = netdev_priv(dev);
4873 ret = phylink_ethtool_set_wol(pp->phylink, wol);
4875 device_set_wakeup_enable(&dev->dev, !!wol->wolopts);
4880 static int mvneta_ethtool_get_eee(struct net_device *dev,
4881 struct ethtool_eee *eee)
4883 struct mvneta_port *pp = netdev_priv(dev);
4886 lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0);
4888 eee->eee_enabled = pp->eee_enabled;
4889 eee->eee_active = pp->eee_active;
4890 eee->tx_lpi_enabled = pp->tx_lpi_enabled;
4891 eee->tx_lpi_timer = (lpi_ctl0) >> 8; // * scale;
4893 return phylink_ethtool_get_eee(pp->phylink, eee);
4896 static int mvneta_ethtool_set_eee(struct net_device *dev,
4897 struct ethtool_eee *eee)
4899 struct mvneta_port *pp = netdev_priv(dev);
4902 /* The Armada 37x documents do not give limits for this other than
4903 * it being an 8-bit register. */
4904 if (eee->tx_lpi_enabled && eee->tx_lpi_timer > 255)
4907 lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0);
4908 lpi_ctl0 &= ~(0xff << 8);
4909 lpi_ctl0 |= eee->tx_lpi_timer << 8;
4910 mvreg_write(pp, MVNETA_LPI_CTRL_0, lpi_ctl0);
4912 pp->eee_enabled = eee->eee_enabled;
4913 pp->tx_lpi_enabled = eee->tx_lpi_enabled;
4915 mvneta_set_eee(pp, eee->tx_lpi_enabled && eee->eee_enabled);
4917 return phylink_ethtool_set_eee(pp->phylink, eee);
4920 static const struct net_device_ops mvneta_netdev_ops = {
4921 .ndo_open = mvneta_open,
4922 .ndo_stop = mvneta_stop,
4923 .ndo_start_xmit = mvneta_tx,
4924 .ndo_set_rx_mode = mvneta_set_rx_mode,
4925 .ndo_set_mac_address = mvneta_set_mac_addr,
4926 .ndo_change_mtu = mvneta_change_mtu,
4927 .ndo_fix_features = mvneta_fix_features,
4928 .ndo_get_stats64 = mvneta_get_stats64,
4929 .ndo_do_ioctl = mvneta_ioctl,
4930 .ndo_bpf = mvneta_xdp,
4931 .ndo_xdp_xmit = mvneta_xdp_xmit,
4934 static const struct ethtool_ops mvneta_eth_tool_ops = {
4935 .supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS |
4936 ETHTOOL_COALESCE_MAX_FRAMES,
4937 .nway_reset = mvneta_ethtool_nway_reset,
4938 .get_link = ethtool_op_get_link,
4939 .set_coalesce = mvneta_ethtool_set_coalesce,
4940 .get_coalesce = mvneta_ethtool_get_coalesce,
4941 .get_drvinfo = mvneta_ethtool_get_drvinfo,
4942 .get_ringparam = mvneta_ethtool_get_ringparam,
4943 .set_ringparam = mvneta_ethtool_set_ringparam,
4944 .get_pauseparam = mvneta_ethtool_get_pauseparam,
4945 .set_pauseparam = mvneta_ethtool_set_pauseparam,
4946 .get_strings = mvneta_ethtool_get_strings,
4947 .get_ethtool_stats = mvneta_ethtool_get_stats,
4948 .get_sset_count = mvneta_ethtool_get_sset_count,
4949 .get_rxfh_indir_size = mvneta_ethtool_get_rxfh_indir_size,
4950 .get_rxnfc = mvneta_ethtool_get_rxnfc,
4951 .get_rxfh = mvneta_ethtool_get_rxfh,
4952 .set_rxfh = mvneta_ethtool_set_rxfh,
4953 .get_link_ksettings = mvneta_ethtool_get_link_ksettings,
4954 .set_link_ksettings = mvneta_ethtool_set_link_ksettings,
4955 .get_wol = mvneta_ethtool_get_wol,
4956 .set_wol = mvneta_ethtool_set_wol,
4957 .get_eee = mvneta_ethtool_get_eee,
4958 .set_eee = mvneta_ethtool_set_eee,
4962 static int mvneta_init(struct device *dev, struct mvneta_port *pp)
4967 mvneta_port_disable(pp);
4969 /* Set port default values */
4970 mvneta_defaults_set(pp);
4972 pp->txqs = devm_kcalloc(dev, txq_number, sizeof(*pp->txqs), GFP_KERNEL);
4976 /* Initialize TX descriptor rings */
4977 for (queue = 0; queue < txq_number; queue++) {
4978 struct mvneta_tx_queue *txq = &pp->txqs[queue];
4980 txq->size = pp->tx_ring_size;
4981 txq->done_pkts_coal = MVNETA_TXDONE_COAL_PKTS;
4984 pp->rxqs = devm_kcalloc(dev, rxq_number, sizeof(*pp->rxqs), GFP_KERNEL);
4988 /* Create Rx descriptor rings */
4989 for (queue = 0; queue < rxq_number; queue++) {
4990 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
4992 rxq->size = pp->rx_ring_size;
4993 rxq->pkts_coal = MVNETA_RX_COAL_PKTS;
4994 rxq->time_coal = MVNETA_RX_COAL_USEC;
4996 = devm_kmalloc_array(pp->dev->dev.parent,
4998 sizeof(*rxq->buf_virt_addr),
5000 if (!rxq->buf_virt_addr)
5007 /* platform glue : initialize decoding windows */
5008 static void mvneta_conf_mbus_windows(struct mvneta_port *pp,
5009 const struct mbus_dram_target_info *dram)
5015 for (i = 0; i < 6; i++) {
5016 mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
5017 mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
5020 mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
5027 for (i = 0; i < dram->num_cs; i++) {
5028 const struct mbus_dram_window *cs = dram->cs + i;
5030 mvreg_write(pp, MVNETA_WIN_BASE(i),
5031 (cs->base & 0xffff0000) |
5032 (cs->mbus_attr << 8) |
5033 dram->mbus_dram_target_id);
5035 mvreg_write(pp, MVNETA_WIN_SIZE(i),
5036 (cs->size - 1) & 0xffff0000);
5038 win_enable &= ~(1 << i);
5039 win_protect |= 3 << (2 * i);
5042 /* For Armada3700 open default 4GB Mbus window, leaving
5043 * arbitration of target/attribute to a different layer
5046 mvreg_write(pp, MVNETA_WIN_SIZE(0), 0xffff0000);
5047 win_enable &= ~BIT(0);
5051 mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
5052 mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect);
5055 /* Power up the port */
5056 static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode)
5058 /* MAC Cause register should be cleared */
5059 mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0);
5061 if (phy_mode != PHY_INTERFACE_MODE_QSGMII &&
5062 phy_mode != PHY_INTERFACE_MODE_SGMII &&
5063 !phy_interface_mode_is_8023z(phy_mode) &&
5064 !phy_interface_mode_is_rgmii(phy_mode))
5070 /* Device initialization routine */
5071 static int mvneta_probe(struct platform_device *pdev)
5073 struct device_node *dn = pdev->dev.of_node;
5074 struct device_node *bm_node;
5075 struct mvneta_port *pp;
5076 struct net_device *dev;
5077 struct phylink *phylink;
5079 const char *dt_mac_addr;
5080 char hw_mac_addr[ETH_ALEN];
5081 phy_interface_t phy_mode;
5082 const char *mac_from;
5087 dev = devm_alloc_etherdev_mqs(&pdev->dev, sizeof(struct mvneta_port),
5088 txq_number, rxq_number);
5092 dev->irq = irq_of_parse_and_map(dn, 0);
5096 err = of_get_phy_mode(dn, &phy_mode);
5098 dev_err(&pdev->dev, "incorrect phy-mode\n");
5102 comphy = devm_of_phy_get(&pdev->dev, dn, NULL);
5103 if (comphy == ERR_PTR(-EPROBE_DEFER)) {
5104 err = -EPROBE_DEFER;
5106 } else if (IS_ERR(comphy)) {
5110 pp = netdev_priv(dev);
5111 spin_lock_init(&pp->lock);
5113 pp->phylink_config.dev = &dev->dev;
5114 pp->phylink_config.type = PHYLINK_NETDEV;
5116 phylink = phylink_create(&pp->phylink_config, pdev->dev.fwnode,
5117 phy_mode, &mvneta_phylink_ops);
5118 if (IS_ERR(phylink)) {
5119 err = PTR_ERR(phylink);
5123 dev->tx_queue_len = MVNETA_MAX_TXD;
5124 dev->watchdog_timeo = 5 * HZ;
5125 dev->netdev_ops = &mvneta_netdev_ops;
5127 dev->ethtool_ops = &mvneta_eth_tool_ops;
5129 pp->phylink = phylink;
5130 pp->comphy = comphy;
5131 pp->phy_interface = phy_mode;
5134 pp->rxq_def = rxq_def;
5135 pp->indir[0] = rxq_def;
5137 /* Get special SoC configurations */
5138 if (of_device_is_compatible(dn, "marvell,armada-3700-neta"))
5139 pp->neta_armada3700 = true;
5141 pp->clk = devm_clk_get(&pdev->dev, "core");
5142 if (IS_ERR(pp->clk))
5143 pp->clk = devm_clk_get(&pdev->dev, NULL);
5144 if (IS_ERR(pp->clk)) {
5145 err = PTR_ERR(pp->clk);
5146 goto err_free_phylink;
5149 clk_prepare_enable(pp->clk);
5151 pp->clk_bus = devm_clk_get(&pdev->dev, "bus");
5152 if (!IS_ERR(pp->clk_bus))
5153 clk_prepare_enable(pp->clk_bus);
5155 pp->base = devm_platform_ioremap_resource(pdev, 0);
5156 if (IS_ERR(pp->base)) {
5157 err = PTR_ERR(pp->base);
5161 /* Alloc per-cpu port structure */
5162 pp->ports = alloc_percpu(struct mvneta_pcpu_port);
5168 /* Alloc per-cpu stats */
5169 pp->stats = netdev_alloc_pcpu_stats(struct mvneta_pcpu_stats);
5172 goto err_free_ports;
5175 dt_mac_addr = of_get_mac_address(dn);
5176 if (!IS_ERR(dt_mac_addr)) {
5177 mac_from = "device tree";
5178 ether_addr_copy(dev->dev_addr, dt_mac_addr);
5180 mvneta_get_mac_addr(pp, hw_mac_addr);
5181 if (is_valid_ether_addr(hw_mac_addr)) {
5182 mac_from = "hardware";
5183 memcpy(dev->dev_addr, hw_mac_addr, ETH_ALEN);
5185 mac_from = "random";
5186 eth_hw_addr_random(dev);
5190 if (!of_property_read_u32(dn, "tx-csum-limit", &tx_csum_limit)) {
5191 if (tx_csum_limit < 0 ||
5192 tx_csum_limit > MVNETA_TX_CSUM_MAX_SIZE) {
5193 tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE;
5194 dev_info(&pdev->dev,
5195 "Wrong TX csum limit in DT, set to %dB\n",
5196 MVNETA_TX_CSUM_DEF_SIZE);
5198 } else if (of_device_is_compatible(dn, "marvell,armada-370-neta")) {
5199 tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE;
5201 tx_csum_limit = MVNETA_TX_CSUM_MAX_SIZE;
5204 pp->tx_csum_limit = tx_csum_limit;
5206 pp->dram_target_info = mv_mbus_dram_info();
5207 /* Armada3700 requires setting default configuration of Mbus
5208 * windows, however without using filled mbus_dram_target_info
5211 if (pp->dram_target_info || pp->neta_armada3700)
5212 mvneta_conf_mbus_windows(pp, pp->dram_target_info);
5214 pp->tx_ring_size = MVNETA_MAX_TXD;
5215 pp->rx_ring_size = MVNETA_MAX_RXD;
5218 SET_NETDEV_DEV(dev, &pdev->dev);
5220 pp->id = global_port_id++;
5222 /* Obtain access to BM resources if enabled and already initialized */
5223 bm_node = of_parse_phandle(dn, "buffer-manager", 0);
5225 pp->bm_priv = mvneta_bm_get(bm_node);
5227 err = mvneta_bm_port_init(pdev, pp);
5229 dev_info(&pdev->dev,
5230 "use SW buffer management\n");
5231 mvneta_bm_put(pp->bm_priv);
5235 /* Set RX packet offset correction for platforms, whose
5236 * NET_SKB_PAD, exceeds 64B. It should be 64B for 64-bit
5237 * platforms and 0B for 32-bit ones.
5239 pp->rx_offset_correction = max(0,
5241 MVNETA_RX_PKT_OFFSET_CORRECTION);
5243 of_node_put(bm_node);
5245 /* sw buffer management */
5247 pp->rx_offset_correction = MVNETA_SKB_HEADROOM;
5249 err = mvneta_init(&pdev->dev, pp);
5253 err = mvneta_port_power_up(pp, pp->phy_interface);
5255 dev_err(&pdev->dev, "can't power up port\n");
5259 /* Armada3700 network controller does not support per-cpu
5260 * operation, so only single NAPI should be initialized.
5262 if (pp->neta_armada3700) {
5263 netif_napi_add(dev, &pp->napi, mvneta_poll, NAPI_POLL_WEIGHT);
5265 for_each_present_cpu(cpu) {
5266 struct mvneta_pcpu_port *port =
5267 per_cpu_ptr(pp->ports, cpu);
5269 netif_napi_add(dev, &port->napi, mvneta_poll,
5275 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
5276 NETIF_F_TSO | NETIF_F_RXCSUM;
5277 dev->hw_features |= dev->features;
5278 dev->vlan_features |= dev->features;
5279 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
5280 dev->gso_max_segs = MVNETA_MAX_TSO_SEGS;
5282 /* MTU range: 68 - 9676 */
5283 dev->min_mtu = ETH_MIN_MTU;
5284 /* 9676 == 9700 - 20 and rounding to 8 */
5285 dev->max_mtu = 9676;
5287 err = register_netdev(dev);
5289 dev_err(&pdev->dev, "failed to register\n");
5293 netdev_info(dev, "Using %s mac address %pM\n", mac_from,
5296 platform_set_drvdata(pdev, pp->dev);
5302 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id);
5303 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short,
5305 mvneta_bm_put(pp->bm_priv);
5307 free_percpu(pp->stats);
5309 free_percpu(pp->ports);
5311 clk_disable_unprepare(pp->clk_bus);
5312 clk_disable_unprepare(pp->clk);
5315 phylink_destroy(pp->phylink);
5317 irq_dispose_mapping(dev->irq);
5321 /* Device removal routine */
5322 static int mvneta_remove(struct platform_device *pdev)
5324 struct net_device *dev = platform_get_drvdata(pdev);
5325 struct mvneta_port *pp = netdev_priv(dev);
5327 unregister_netdev(dev);
5328 clk_disable_unprepare(pp->clk_bus);
5329 clk_disable_unprepare(pp->clk);
5330 free_percpu(pp->ports);
5331 free_percpu(pp->stats);
5332 irq_dispose_mapping(dev->irq);
5333 phylink_destroy(pp->phylink);
5336 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id);
5337 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short,
5339 mvneta_bm_put(pp->bm_priv);
5345 #ifdef CONFIG_PM_SLEEP
5346 static int mvneta_suspend(struct device *device)
5349 struct net_device *dev = dev_get_drvdata(device);
5350 struct mvneta_port *pp = netdev_priv(dev);
5352 if (!netif_running(dev))
5355 if (!pp->neta_armada3700) {
5356 spin_lock(&pp->lock);
5357 pp->is_stopped = true;
5358 spin_unlock(&pp->lock);
5360 cpuhp_state_remove_instance_nocalls(online_hpstate,
5362 cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD,
5367 mvneta_stop_dev(pp);
5370 for (queue = 0; queue < rxq_number; queue++) {
5371 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
5373 mvneta_rxq_drop_pkts(pp, rxq);
5376 for (queue = 0; queue < txq_number; queue++) {
5377 struct mvneta_tx_queue *txq = &pp->txqs[queue];
5379 mvneta_txq_hw_deinit(pp, txq);
5383 netif_device_detach(dev);
5384 clk_disable_unprepare(pp->clk_bus);
5385 clk_disable_unprepare(pp->clk);
5390 static int mvneta_resume(struct device *device)
5392 struct platform_device *pdev = to_platform_device(device);
5393 struct net_device *dev = dev_get_drvdata(device);
5394 struct mvneta_port *pp = netdev_priv(dev);
5397 clk_prepare_enable(pp->clk);
5398 if (!IS_ERR(pp->clk_bus))
5399 clk_prepare_enable(pp->clk_bus);
5400 if (pp->dram_target_info || pp->neta_armada3700)
5401 mvneta_conf_mbus_windows(pp, pp->dram_target_info);
5403 err = mvneta_bm_port_init(pdev, pp);
5405 dev_info(&pdev->dev, "use SW buffer management\n");
5406 pp->rx_offset_correction = MVNETA_SKB_HEADROOM;
5410 mvneta_defaults_set(pp);
5411 err = mvneta_port_power_up(pp, pp->phy_interface);
5413 dev_err(device, "can't power up port\n");
5417 netif_device_attach(dev);
5419 if (!netif_running(dev))
5422 for (queue = 0; queue < rxq_number; queue++) {
5423 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
5425 rxq->next_desc_to_proc = 0;
5426 mvneta_rxq_hw_init(pp, rxq);
5429 for (queue = 0; queue < txq_number; queue++) {
5430 struct mvneta_tx_queue *txq = &pp->txqs[queue];
5432 txq->next_desc_to_proc = 0;
5433 mvneta_txq_hw_init(pp, txq);
5436 if (!pp->neta_armada3700) {
5437 spin_lock(&pp->lock);
5438 pp->is_stopped = false;
5439 spin_unlock(&pp->lock);
5440 cpuhp_state_add_instance_nocalls(online_hpstate,
5442 cpuhp_state_add_instance_nocalls(CPUHP_NET_MVNETA_DEAD,
5447 mvneta_start_dev(pp);
5449 mvneta_set_rx_mode(dev);
5455 static SIMPLE_DEV_PM_OPS(mvneta_pm_ops, mvneta_suspend, mvneta_resume);
5457 static const struct of_device_id mvneta_match[] = {
5458 { .compatible = "marvell,armada-370-neta" },
5459 { .compatible = "marvell,armada-xp-neta" },
5460 { .compatible = "marvell,armada-3700-neta" },
5463 MODULE_DEVICE_TABLE(of, mvneta_match);
5465 static struct platform_driver mvneta_driver = {
5466 .probe = mvneta_probe,
5467 .remove = mvneta_remove,
5469 .name = MVNETA_DRIVER_NAME,
5470 .of_match_table = mvneta_match,
5471 .pm = &mvneta_pm_ops,
5475 static int __init mvneta_driver_init(void)
5479 ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, "net/mvneta:online",
5481 mvneta_cpu_down_prepare);
5484 online_hpstate = ret;
5485 ret = cpuhp_setup_state_multi(CPUHP_NET_MVNETA_DEAD, "net/mvneta:dead",
5486 NULL, mvneta_cpu_dead);
5490 ret = platform_driver_register(&mvneta_driver);
5496 cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD);
5498 cpuhp_remove_multi_state(online_hpstate);
5502 module_init(mvneta_driver_init);
5504 static void __exit mvneta_driver_exit(void)
5506 platform_driver_unregister(&mvneta_driver);
5507 cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD);
5508 cpuhp_remove_multi_state(online_hpstate);
5510 module_exit(mvneta_driver_exit);
5512 MODULE_DESCRIPTION("Marvell NETA Ethernet Driver - www.marvell.com");
5513 MODULE_AUTHOR("Rami Rosen <rosenr@marvell.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
5514 MODULE_LICENSE("GPL");
5516 module_param(rxq_number, int, 0444);
5517 module_param(txq_number, int, 0444);
5519 module_param(rxq_def, int, 0444);
5520 module_param(rx_copybreak, int, 0644);