2 * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs.
4 * Copyright (C) 2012 Marvell
6 * Rami Rosen <rosenr@marvell.com>
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
14 #include <linux/clk.h>
15 #include <linux/cpu.h>
16 #include <linux/etherdevice.h>
17 #include <linux/if_vlan.h>
18 #include <linux/inetdevice.h>
19 #include <linux/interrupt.h>
21 #include <linux/kernel.h>
22 #include <linux/mbus.h>
23 #include <linux/module.h>
24 #include <linux/netdevice.h>
26 #include <linux/of_address.h>
27 #include <linux/of_irq.h>
28 #include <linux/of_mdio.h>
29 #include <linux/of_net.h>
30 #include <linux/phy.h>
31 #include <linux/phylink.h>
32 #include <linux/platform_device.h>
33 #include <linux/skbuff.h>
35 #include "mvneta_bm.h"
41 #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2))
42 #define MVNETA_RXQ_HW_BUF_ALLOC BIT(0)
43 #define MVNETA_RXQ_SHORT_POOL_ID_SHIFT 4
44 #define MVNETA_RXQ_SHORT_POOL_ID_MASK 0x30
45 #define MVNETA_RXQ_LONG_POOL_ID_SHIFT 6
46 #define MVNETA_RXQ_LONG_POOL_ID_MASK 0xc0
47 #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8)
48 #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8)
49 #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2))
50 #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16)
51 #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2))
52 #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2))
53 #define MVNETA_RXQ_BUF_SIZE_SHIFT 19
54 #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19)
55 #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2))
56 #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff
57 #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2))
58 #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16
59 #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255
60 #define MVNETA_PORT_POOL_BUFFER_SZ_REG(pool) (0x1700 + ((pool) << 2))
61 #define MVNETA_PORT_POOL_BUFFER_SZ_SHIFT 3
62 #define MVNETA_PORT_POOL_BUFFER_SZ_MASK 0xfff8
63 #define MVNETA_PORT_RX_RESET 0x1cc0
64 #define MVNETA_PORT_RX_DMA_RESET BIT(0)
65 #define MVNETA_PHY_ADDR 0x2000
66 #define MVNETA_PHY_ADDR_MASK 0x1f
67 #define MVNETA_MBUS_RETRY 0x2010
68 #define MVNETA_UNIT_INTR_CAUSE 0x2080
69 #define MVNETA_UNIT_CONTROL 0x20B0
70 #define MVNETA_PHY_POLLING_ENABLE BIT(1)
71 #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3))
72 #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3))
73 #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2))
74 #define MVNETA_BASE_ADDR_ENABLE 0x2290
75 #define MVNETA_ACCESS_PROTECT_ENABLE 0x2294
76 #define MVNETA_PORT_CONFIG 0x2400
77 #define MVNETA_UNI_PROMISC_MODE BIT(0)
78 #define MVNETA_DEF_RXQ(q) ((q) << 1)
79 #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4)
80 #define MVNETA_TX_UNSET_ERR_SUM BIT(12)
81 #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16)
82 #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19)
83 #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22)
84 #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25)
85 #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \
86 MVNETA_DEF_RXQ_ARP(q) | \
87 MVNETA_DEF_RXQ_TCP(q) | \
88 MVNETA_DEF_RXQ_UDP(q) | \
89 MVNETA_DEF_RXQ_BPDU(q) | \
90 MVNETA_TX_UNSET_ERR_SUM | \
91 MVNETA_RX_CSUM_WITH_PSEUDO_HDR)
92 #define MVNETA_PORT_CONFIG_EXTEND 0x2404
93 #define MVNETA_MAC_ADDR_LOW 0x2414
94 #define MVNETA_MAC_ADDR_HIGH 0x2418
95 #define MVNETA_SDMA_CONFIG 0x241c
96 #define MVNETA_SDMA_BRST_SIZE_16 4
97 #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1)
98 #define MVNETA_RX_NO_DATA_SWAP BIT(4)
99 #define MVNETA_TX_NO_DATA_SWAP BIT(5)
100 #define MVNETA_DESC_SWAP BIT(6)
101 #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22)
102 #define MVNETA_PORT_STATUS 0x2444
103 #define MVNETA_TX_IN_PRGRS BIT(1)
104 #define MVNETA_TX_FIFO_EMPTY BIT(8)
105 #define MVNETA_RX_MIN_FRAME_SIZE 0x247c
106 #define MVNETA_SERDES_CFG 0x24A0
107 #define MVNETA_SGMII_SERDES_PROTO 0x0cc7
108 #define MVNETA_QSGMII_SERDES_PROTO 0x0667
109 #define MVNETA_TYPE_PRIO 0x24bc
110 #define MVNETA_FORCE_UNI BIT(21)
111 #define MVNETA_TXQ_CMD_1 0x24e4
112 #define MVNETA_TXQ_CMD 0x2448
113 #define MVNETA_TXQ_DISABLE_SHIFT 8
114 #define MVNETA_TXQ_ENABLE_MASK 0x000000ff
115 #define MVNETA_RX_DISCARD_FRAME_COUNT 0x2484
116 #define MVNETA_OVERRUN_FRAME_COUNT 0x2488
117 #define MVNETA_GMAC_CLOCK_DIVIDER 0x24f4
118 #define MVNETA_GMAC_1MS_CLOCK_ENABLE BIT(31)
119 #define MVNETA_ACC_MODE 0x2500
120 #define MVNETA_BM_ADDRESS 0x2504
121 #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2))
122 #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff
123 #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00
124 #define MVNETA_CPU_RXQ_ACCESS(rxq) BIT(rxq)
125 #define MVNETA_CPU_TXQ_ACCESS(txq) BIT(txq + 8)
126 #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2))
128 /* Exception Interrupt Port/Queue Cause register
130 * Their behavior depend of the mapping done using the PCPX2Q
131 * registers. For a given CPU if the bit associated to a queue is not
132 * set, then for the register a read from this CPU will always return
133 * 0 and a write won't do anything
136 #define MVNETA_INTR_NEW_CAUSE 0x25a0
137 #define MVNETA_INTR_NEW_MASK 0x25a4
139 /* bits 0..7 = TXQ SENT, one bit per queue.
140 * bits 8..15 = RXQ OCCUP, one bit per queue.
141 * bits 16..23 = RXQ FREE, one bit per queue.
142 * bit 29 = OLD_REG_SUM, see old reg ?
143 * bit 30 = TX_ERR_SUM, one bit for 4 ports
144 * bit 31 = MISC_SUM, one bit for 4 ports
146 #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0)
147 #define MVNETA_TX_INTR_MASK_ALL (0xff << 0)
148 #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8)
149 #define MVNETA_RX_INTR_MASK_ALL (0xff << 8)
150 #define MVNETA_MISCINTR_INTR_MASK BIT(31)
152 #define MVNETA_INTR_OLD_CAUSE 0x25a8
153 #define MVNETA_INTR_OLD_MASK 0x25ac
155 /* Data Path Port/Queue Cause Register */
156 #define MVNETA_INTR_MISC_CAUSE 0x25b0
157 #define MVNETA_INTR_MISC_MASK 0x25b4
159 #define MVNETA_CAUSE_PHY_STATUS_CHANGE BIT(0)
160 #define MVNETA_CAUSE_LINK_CHANGE BIT(1)
161 #define MVNETA_CAUSE_PTP BIT(4)
163 #define MVNETA_CAUSE_INTERNAL_ADDR_ERR BIT(7)
164 #define MVNETA_CAUSE_RX_OVERRUN BIT(8)
165 #define MVNETA_CAUSE_RX_CRC_ERROR BIT(9)
166 #define MVNETA_CAUSE_RX_LARGE_PKT BIT(10)
167 #define MVNETA_CAUSE_TX_UNDERUN BIT(11)
168 #define MVNETA_CAUSE_PRBS_ERR BIT(12)
169 #define MVNETA_CAUSE_PSC_SYNC_CHANGE BIT(13)
170 #define MVNETA_CAUSE_SERDES_SYNC_ERR BIT(14)
172 #define MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT 16
173 #define MVNETA_CAUSE_BMU_ALLOC_ERR_ALL_MASK (0xF << MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT)
174 #define MVNETA_CAUSE_BMU_ALLOC_ERR_MASK(pool) (1 << (MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT + (pool)))
176 #define MVNETA_CAUSE_TXQ_ERROR_SHIFT 24
177 #define MVNETA_CAUSE_TXQ_ERROR_ALL_MASK (0xFF << MVNETA_CAUSE_TXQ_ERROR_SHIFT)
178 #define MVNETA_CAUSE_TXQ_ERROR_MASK(q) (1 << (MVNETA_CAUSE_TXQ_ERROR_SHIFT + (q)))
180 #define MVNETA_INTR_ENABLE 0x25b8
181 #define MVNETA_TXQ_INTR_ENABLE_ALL_MASK 0x0000ff00
182 #define MVNETA_RXQ_INTR_ENABLE_ALL_MASK 0x000000ff
184 #define MVNETA_RXQ_CMD 0x2680
185 #define MVNETA_RXQ_DISABLE_SHIFT 8
186 #define MVNETA_RXQ_ENABLE_MASK 0x000000ff
187 #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4))
188 #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4))
189 #define MVNETA_GMAC_CTRL_0 0x2c00
190 #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2
191 #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc
192 #define MVNETA_GMAC0_PORT_1000BASE_X BIT(1)
193 #define MVNETA_GMAC0_PORT_ENABLE BIT(0)
194 #define MVNETA_GMAC_CTRL_2 0x2c08
195 #define MVNETA_GMAC2_INBAND_AN_ENABLE BIT(0)
196 #define MVNETA_GMAC2_PCS_ENABLE BIT(3)
197 #define MVNETA_GMAC2_PORT_RGMII BIT(4)
198 #define MVNETA_GMAC2_PORT_RESET BIT(6)
199 #define MVNETA_GMAC_STATUS 0x2c10
200 #define MVNETA_GMAC_LINK_UP BIT(0)
201 #define MVNETA_GMAC_SPEED_1000 BIT(1)
202 #define MVNETA_GMAC_SPEED_100 BIT(2)
203 #define MVNETA_GMAC_FULL_DUPLEX BIT(3)
204 #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4)
205 #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5)
206 #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6)
207 #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7)
208 #define MVNETA_GMAC_AN_COMPLETE BIT(11)
209 #define MVNETA_GMAC_SYNC_OK BIT(14)
210 #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c
211 #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0)
212 #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1)
213 #define MVNETA_GMAC_INBAND_AN_ENABLE BIT(2)
214 #define MVNETA_GMAC_AN_BYPASS_ENABLE BIT(3)
215 #define MVNETA_GMAC_INBAND_RESTART_AN BIT(4)
216 #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5)
217 #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6)
218 #define MVNETA_GMAC_AN_SPEED_EN BIT(7)
219 #define MVNETA_GMAC_CONFIG_FLOW_CTRL BIT(8)
220 #define MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL BIT(9)
221 #define MVNETA_GMAC_AN_FLOW_CTRL_EN BIT(11)
222 #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12)
223 #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13)
224 #define MVNETA_MIB_COUNTERS_BASE 0x3000
225 #define MVNETA_MIB_LATE_COLLISION 0x7c
226 #define MVNETA_DA_FILT_SPEC_MCAST 0x3400
227 #define MVNETA_DA_FILT_OTH_MCAST 0x3500
228 #define MVNETA_DA_FILT_UCAST_BASE 0x3600
229 #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2))
230 #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2))
231 #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000
232 #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16)
233 #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2))
234 #define MVNETA_TXQ_DEC_SENT_SHIFT 16
235 #define MVNETA_TXQ_DEC_SENT_MASK 0xff
236 #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2))
237 #define MVNETA_TXQ_SENT_DESC_SHIFT 16
238 #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000
239 #define MVNETA_PORT_TX_RESET 0x3cf0
240 #define MVNETA_PORT_TX_DMA_RESET BIT(0)
241 #define MVNETA_TX_MTU 0x3e0c
242 #define MVNETA_TX_TOKEN_SIZE 0x3e14
243 #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff
244 #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2))
245 #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff
247 #define MVNETA_LPI_CTRL_0 0x2cc0
248 #define MVNETA_LPI_CTRL_1 0x2cc4
249 #define MVNETA_LPI_REQUEST_ENABLE BIT(0)
250 #define MVNETA_LPI_CTRL_2 0x2cc8
251 #define MVNETA_LPI_STATUS 0x2ccc
253 #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
255 /* Descriptor ring Macros */
256 #define MVNETA_QUEUE_NEXT_DESC(q, index) \
257 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
259 /* Various constants */
262 #define MVNETA_TXDONE_COAL_PKTS 0 /* interrupt per packet */
263 #define MVNETA_RX_COAL_PKTS 32
264 #define MVNETA_RX_COAL_USEC 100
266 /* The two bytes Marvell header. Either contains a special value used
267 * by Marvell switches when a specific hardware mode is enabled (not
268 * supported by this driver) or is filled automatically by zeroes on
269 * the RX side. Those two bytes being at the front of the Ethernet
270 * header, they allow to have the IP header aligned on a 4 bytes
271 * boundary automatically: the hardware skips those two bytes on its
274 #define MVNETA_MH_SIZE 2
276 #define MVNETA_VLAN_TAG_LEN 4
278 #define MVNETA_TX_CSUM_DEF_SIZE 1600
279 #define MVNETA_TX_CSUM_MAX_SIZE 9800
280 #define MVNETA_ACC_MODE_EXT1 1
281 #define MVNETA_ACC_MODE_EXT2 2
283 #define MVNETA_MAX_DECODE_WIN 6
285 /* Timeout constants */
286 #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000
287 #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000
288 #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000
290 #define MVNETA_TX_MTU_MAX 0x3ffff
292 /* The RSS lookup table actually has 256 entries but we do not use
295 #define MVNETA_RSS_LU_TABLE_SIZE 1
297 /* Max number of Rx descriptors */
298 #define MVNETA_MAX_RXD 128
300 /* Max number of Tx descriptors */
301 #define MVNETA_MAX_TXD 532
303 /* Max number of allowed TCP segments for software TSO */
304 #define MVNETA_MAX_TSO_SEGS 100
306 #define MVNETA_MAX_SKB_DESCS (MVNETA_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
308 /* descriptor aligned size */
309 #define MVNETA_DESC_ALIGNED_SIZE 32
311 /* Number of bytes to be taken into account by HW when putting incoming data
312 * to the buffers. It is needed in case NET_SKB_PAD exceeds maximum packet
313 * offset supported in MVNETA_RXQ_CONFIG_REG(q) registers.
315 #define MVNETA_RX_PKT_OFFSET_CORRECTION 64
317 #define MVNETA_RX_PKT_SIZE(mtu) \
318 ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \
319 ETH_HLEN + ETH_FCS_LEN, \
322 #define IS_TSO_HEADER(txq, addr) \
323 ((addr >= txq->tso_hdrs_phys) && \
324 (addr < txq->tso_hdrs_phys + txq->size * TSO_HEADER_SIZE))
326 #define MVNETA_RX_GET_BM_POOL_ID(rxd) \
327 (((rxd)->status & MVNETA_RXD_BM_POOL_MASK) >> MVNETA_RXD_BM_POOL_SHIFT)
330 ETHTOOL_STAT_EEE_WAKEUP,
334 struct mvneta_statistic {
335 unsigned short offset;
337 const char name[ETH_GSTRING_LEN];
344 static const struct mvneta_statistic mvneta_statistics[] = {
345 { 0x3000, T_REG_64, "good_octets_received", },
346 { 0x3010, T_REG_32, "good_frames_received", },
347 { 0x3008, T_REG_32, "bad_octets_received", },
348 { 0x3014, T_REG_32, "bad_frames_received", },
349 { 0x3018, T_REG_32, "broadcast_frames_received", },
350 { 0x301c, T_REG_32, "multicast_frames_received", },
351 { 0x3050, T_REG_32, "unrec_mac_control_received", },
352 { 0x3058, T_REG_32, "good_fc_received", },
353 { 0x305c, T_REG_32, "bad_fc_received", },
354 { 0x3060, T_REG_32, "undersize_received", },
355 { 0x3064, T_REG_32, "fragments_received", },
356 { 0x3068, T_REG_32, "oversize_received", },
357 { 0x306c, T_REG_32, "jabber_received", },
358 { 0x3070, T_REG_32, "mac_receive_error", },
359 { 0x3074, T_REG_32, "bad_crc_event", },
360 { 0x3078, T_REG_32, "collision", },
361 { 0x307c, T_REG_32, "late_collision", },
362 { 0x2484, T_REG_32, "rx_discard", },
363 { 0x2488, T_REG_32, "rx_overrun", },
364 { 0x3020, T_REG_32, "frames_64_octets", },
365 { 0x3024, T_REG_32, "frames_65_to_127_octets", },
366 { 0x3028, T_REG_32, "frames_128_to_255_octets", },
367 { 0x302c, T_REG_32, "frames_256_to_511_octets", },
368 { 0x3030, T_REG_32, "frames_512_to_1023_octets", },
369 { 0x3034, T_REG_32, "frames_1024_to_max_octets", },
370 { 0x3038, T_REG_64, "good_octets_sent", },
371 { 0x3040, T_REG_32, "good_frames_sent", },
372 { 0x3044, T_REG_32, "excessive_collision", },
373 { 0x3048, T_REG_32, "multicast_frames_sent", },
374 { 0x304c, T_REG_32, "broadcast_frames_sent", },
375 { 0x3054, T_REG_32, "fc_sent", },
376 { 0x300c, T_REG_32, "internal_mac_transmit_err", },
377 { ETHTOOL_STAT_EEE_WAKEUP, T_SW, "eee_wakeup_errors", },
380 struct mvneta_pcpu_stats {
381 struct u64_stats_sync syncp;
388 struct mvneta_pcpu_port {
389 /* Pointer to the shared port */
390 struct mvneta_port *pp;
392 /* Pointer to the CPU-local NAPI struct */
393 struct napi_struct napi;
395 /* Cause of the previous interrupt */
401 struct mvneta_pcpu_port __percpu *ports;
402 struct mvneta_pcpu_stats __percpu *stats;
405 unsigned int frag_size;
407 struct mvneta_rx_queue *rxqs;
408 struct mvneta_tx_queue *txqs;
409 struct net_device *dev;
410 struct hlist_node node_online;
411 struct hlist_node node_dead;
413 /* Protect the access to the percpu interrupt registers,
414 * ensuring that the configuration remains coherent.
420 struct napi_struct napi;
430 phy_interface_t phy_interface;
431 struct device_node *dn;
432 unsigned int tx_csum_limit;
433 struct phylink *phylink;
435 struct mvneta_bm *bm_priv;
436 struct mvneta_bm_pool *pool_long;
437 struct mvneta_bm_pool *pool_short;
444 u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)];
446 u32 indir[MVNETA_RSS_LU_TABLE_SIZE];
448 /* Flags for special SoC configurations */
449 bool neta_armada3700;
450 u16 rx_offset_correction;
451 const struct mbus_dram_target_info *dram_target_info;
454 /* The mvneta_tx_desc and mvneta_rx_desc structures describe the
455 * layout of the transmit and reception DMA descriptors, and their
456 * layout is therefore defined by the hardware design
459 #define MVNETA_TX_L3_OFF_SHIFT 0
460 #define MVNETA_TX_IP_HLEN_SHIFT 8
461 #define MVNETA_TX_L4_UDP BIT(16)
462 #define MVNETA_TX_L3_IP6 BIT(17)
463 #define MVNETA_TXD_IP_CSUM BIT(18)
464 #define MVNETA_TXD_Z_PAD BIT(19)
465 #define MVNETA_TXD_L_DESC BIT(20)
466 #define MVNETA_TXD_F_DESC BIT(21)
467 #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \
468 MVNETA_TXD_L_DESC | \
470 #define MVNETA_TX_L4_CSUM_FULL BIT(30)
471 #define MVNETA_TX_L4_CSUM_NOT BIT(31)
473 #define MVNETA_RXD_ERR_CRC 0x0
474 #define MVNETA_RXD_BM_POOL_SHIFT 13
475 #define MVNETA_RXD_BM_POOL_MASK (BIT(13) | BIT(14))
476 #define MVNETA_RXD_ERR_SUMMARY BIT(16)
477 #define MVNETA_RXD_ERR_OVERRUN BIT(17)
478 #define MVNETA_RXD_ERR_LEN BIT(18)
479 #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18))
480 #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18))
481 #define MVNETA_RXD_L3_IP4 BIT(25)
482 #define MVNETA_RXD_FIRST_LAST_DESC (BIT(26) | BIT(27))
483 #define MVNETA_RXD_L4_CSUM_OK BIT(30)
485 #if defined(__LITTLE_ENDIAN)
486 struct mvneta_tx_desc {
487 u32 command; /* Options used by HW for packet transmitting.*/
488 u16 reserverd1; /* csum_l4 (for future use) */
489 u16 data_size; /* Data size of transmitted packet in bytes */
490 u32 buf_phys_addr; /* Physical addr of transmitted buffer */
491 u32 reserved2; /* hw_cmd - (for future use, PMT) */
492 u32 reserved3[4]; /* Reserved - (for future use) */
495 struct mvneta_rx_desc {
496 u32 status; /* Info about received packet */
497 u16 reserved1; /* pnc_info - (for future use, PnC) */
498 u16 data_size; /* Size of received packet in bytes */
500 u32 buf_phys_addr; /* Physical address of the buffer */
501 u32 reserved2; /* pnc_flow_id (for future use, PnC) */
503 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
504 u16 reserved3; /* prefetch_cmd, for future use */
505 u16 reserved4; /* csum_l4 - (for future use, PnC) */
507 u32 reserved5; /* pnc_extra PnC (for future use, PnC) */
508 u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */
511 struct mvneta_tx_desc {
512 u16 data_size; /* Data size of transmitted packet in bytes */
513 u16 reserverd1; /* csum_l4 (for future use) */
514 u32 command; /* Options used by HW for packet transmitting.*/
515 u32 reserved2; /* hw_cmd - (for future use, PMT) */
516 u32 buf_phys_addr; /* Physical addr of transmitted buffer */
517 u32 reserved3[4]; /* Reserved - (for future use) */
520 struct mvneta_rx_desc {
521 u16 data_size; /* Size of received packet in bytes */
522 u16 reserved1; /* pnc_info - (for future use, PnC) */
523 u32 status; /* Info about received packet */
525 u32 reserved2; /* pnc_flow_id (for future use, PnC) */
526 u32 buf_phys_addr; /* Physical address of the buffer */
528 u16 reserved4; /* csum_l4 - (for future use, PnC) */
529 u16 reserved3; /* prefetch_cmd, for future use */
530 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
532 u32 reserved5; /* pnc_extra PnC (for future use, PnC) */
533 u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */
537 struct mvneta_tx_queue {
538 /* Number of this TX queue, in the range 0-7 */
541 /* Number of TX DMA descriptors in the descriptor ring */
544 /* Number of currently used TX DMA descriptor in the
549 int tx_stop_threshold;
550 int tx_wake_threshold;
552 /* Array of transmitted skb */
553 struct sk_buff **tx_skb;
555 /* Index of last TX DMA descriptor that was inserted */
558 /* Index of the TX DMA descriptor to be cleaned up */
563 /* Virtual address of the TX DMA descriptors array */
564 struct mvneta_tx_desc *descs;
566 /* DMA address of the TX DMA descriptors array */
567 dma_addr_t descs_phys;
569 /* Index of the last TX DMA descriptor */
572 /* Index of the next TX DMA descriptor to process */
573 int next_desc_to_proc;
575 /* DMA buffers for TSO headers */
578 /* DMA address of TSO headers */
579 dma_addr_t tso_hdrs_phys;
581 /* Affinity mask for CPUs*/
582 cpumask_t affinity_mask;
585 struct mvneta_rx_queue {
586 /* rx queue number, in the range 0-7 */
589 /* num of rx descriptors in the rx descriptor ring */
592 /* counter of times when mvneta_refill() failed */
598 /* Virtual address of the RX buffer */
599 void **buf_virt_addr;
601 /* Virtual address of the RX DMA descriptors array */
602 struct mvneta_rx_desc *descs;
604 /* DMA address of the RX DMA descriptors array */
605 dma_addr_t descs_phys;
607 /* Index of the last RX DMA descriptor */
610 /* Index of the next RX DMA descriptor to process */
611 int next_desc_to_proc;
614 static enum cpuhp_state online_hpstate;
615 /* The hardware supports eight (8) rx queues, but we are only allowing
616 * the first one to be used. Therefore, let's just allocate one queue.
618 static int rxq_number = 8;
619 static int txq_number = 8;
623 static int rx_copybreak __read_mostly = 256;
625 /* HW BM need that each port be identify by a unique ID */
626 static int global_port_id;
628 #define MVNETA_DRIVER_NAME "mvneta"
629 #define MVNETA_DRIVER_VERSION "1.0"
631 /* Utility/helper methods */
633 /* Write helper method */
634 static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data)
636 writel(data, pp->base + offset);
639 /* Read helper method */
640 static u32 mvreg_read(struct mvneta_port *pp, u32 offset)
642 return readl(pp->base + offset);
645 /* Increment txq get counter */
646 static void mvneta_txq_inc_get(struct mvneta_tx_queue *txq)
648 txq->txq_get_index++;
649 if (txq->txq_get_index == txq->size)
650 txq->txq_get_index = 0;
653 /* Increment txq put counter */
654 static void mvneta_txq_inc_put(struct mvneta_tx_queue *txq)
656 txq->txq_put_index++;
657 if (txq->txq_put_index == txq->size)
658 txq->txq_put_index = 0;
662 /* Clear all MIB counters */
663 static void mvneta_mib_counters_clear(struct mvneta_port *pp)
668 /* Perform dummy reads from MIB counters */
669 for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4)
670 dummy = mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i));
671 dummy = mvreg_read(pp, MVNETA_RX_DISCARD_FRAME_COUNT);
672 dummy = mvreg_read(pp, MVNETA_OVERRUN_FRAME_COUNT);
675 /* Get System Network Statistics */
677 mvneta_get_stats64(struct net_device *dev,
678 struct rtnl_link_stats64 *stats)
680 struct mvneta_port *pp = netdev_priv(dev);
684 for_each_possible_cpu(cpu) {
685 struct mvneta_pcpu_stats *cpu_stats;
691 cpu_stats = per_cpu_ptr(pp->stats, cpu);
693 start = u64_stats_fetch_begin_irq(&cpu_stats->syncp);
694 rx_packets = cpu_stats->rx_packets;
695 rx_bytes = cpu_stats->rx_bytes;
696 tx_packets = cpu_stats->tx_packets;
697 tx_bytes = cpu_stats->tx_bytes;
698 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start));
700 stats->rx_packets += rx_packets;
701 stats->rx_bytes += rx_bytes;
702 stats->tx_packets += tx_packets;
703 stats->tx_bytes += tx_bytes;
706 stats->rx_errors = dev->stats.rx_errors;
707 stats->rx_dropped = dev->stats.rx_dropped;
709 stats->tx_dropped = dev->stats.tx_dropped;
712 /* Rx descriptors helper methods */
714 /* Checks whether the RX descriptor having this status is both the first
715 * and the last descriptor for the RX packet. Each RX packet is currently
716 * received through a single RX descriptor, so not having each RX
717 * descriptor with its first and last bits set is an error
719 static int mvneta_rxq_desc_is_first_last(u32 status)
721 return (status & MVNETA_RXD_FIRST_LAST_DESC) ==
722 MVNETA_RXD_FIRST_LAST_DESC;
725 /* Add number of descriptors ready to receive new packets */
726 static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp,
727 struct mvneta_rx_queue *rxq,
730 /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can
733 while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) {
734 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
735 (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX <<
736 MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
737 ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX;
740 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
741 (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
744 /* Get number of RX descriptors occupied by received packets */
745 static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp,
746 struct mvneta_rx_queue *rxq)
750 val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id));
751 return val & MVNETA_RXQ_OCCUPIED_ALL_MASK;
754 /* Update num of rx desc called upon return from rx path or
755 * from mvneta_rxq_drop_pkts().
757 static void mvneta_rxq_desc_num_update(struct mvneta_port *pp,
758 struct mvneta_rx_queue *rxq,
759 int rx_done, int rx_filled)
763 if ((rx_done <= 0xff) && (rx_filled <= 0xff)) {
765 (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT);
766 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
770 /* Only 255 descriptors can be added at once */
771 while ((rx_done > 0) || (rx_filled > 0)) {
772 if (rx_done <= 0xff) {
779 if (rx_filled <= 0xff) {
780 val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
783 val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
786 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
790 /* Get pointer to next RX descriptor to be processed by SW */
791 static struct mvneta_rx_desc *
792 mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq)
794 int rx_desc = rxq->next_desc_to_proc;
796 rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc);
797 prefetch(rxq->descs + rxq->next_desc_to_proc);
798 return rxq->descs + rx_desc;
801 /* Change maximum receive size of the port. */
802 static void mvneta_max_rx_size_set(struct mvneta_port *pp, int max_rx_size)
806 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
807 val &= ~MVNETA_GMAC_MAX_RX_SIZE_MASK;
808 val |= ((max_rx_size - MVNETA_MH_SIZE) / 2) <<
809 MVNETA_GMAC_MAX_RX_SIZE_SHIFT;
810 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
814 /* Set rx queue offset */
815 static void mvneta_rxq_offset_set(struct mvneta_port *pp,
816 struct mvneta_rx_queue *rxq,
821 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
822 val &= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK;
825 val |= MVNETA_RXQ_PKT_OFFSET_MASK(offset >> 3);
826 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
830 /* Tx descriptors helper methods */
832 /* Update HW with number of TX descriptors to be sent */
833 static void mvneta_txq_pend_desc_add(struct mvneta_port *pp,
834 struct mvneta_tx_queue *txq,
839 pend_desc += txq->pending;
841 /* Only 255 Tx descriptors can be added at once */
843 val = min(pend_desc, 255);
844 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
846 } while (pend_desc > 0);
850 /* Get pointer to next TX descriptor to be processed (send) by HW */
851 static struct mvneta_tx_desc *
852 mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq)
854 int tx_desc = txq->next_desc_to_proc;
856 txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc);
857 return txq->descs + tx_desc;
860 /* Release the last allocated TX descriptor. Useful to handle DMA
861 * mapping failures in the TX path.
863 static void mvneta_txq_desc_put(struct mvneta_tx_queue *txq)
865 if (txq->next_desc_to_proc == 0)
866 txq->next_desc_to_proc = txq->last_desc - 1;
868 txq->next_desc_to_proc--;
871 /* Set rxq buf size */
872 static void mvneta_rxq_buf_size_set(struct mvneta_port *pp,
873 struct mvneta_rx_queue *rxq,
878 val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id));
880 val &= ~MVNETA_RXQ_BUF_SIZE_MASK;
881 val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT);
883 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val);
886 /* Disable buffer management (BM) */
887 static void mvneta_rxq_bm_disable(struct mvneta_port *pp,
888 struct mvneta_rx_queue *rxq)
892 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
893 val &= ~MVNETA_RXQ_HW_BUF_ALLOC;
894 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
897 /* Enable buffer management (BM) */
898 static void mvneta_rxq_bm_enable(struct mvneta_port *pp,
899 struct mvneta_rx_queue *rxq)
903 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
904 val |= MVNETA_RXQ_HW_BUF_ALLOC;
905 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
908 /* Notify HW about port's assignment of pool for bigger packets */
909 static void mvneta_rxq_long_pool_set(struct mvneta_port *pp,
910 struct mvneta_rx_queue *rxq)
914 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
915 val &= ~MVNETA_RXQ_LONG_POOL_ID_MASK;
916 val |= (pp->pool_long->id << MVNETA_RXQ_LONG_POOL_ID_SHIFT);
918 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
921 /* Notify HW about port's assignment of pool for smaller packets */
922 static void mvneta_rxq_short_pool_set(struct mvneta_port *pp,
923 struct mvneta_rx_queue *rxq)
927 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
928 val &= ~MVNETA_RXQ_SHORT_POOL_ID_MASK;
929 val |= (pp->pool_short->id << MVNETA_RXQ_SHORT_POOL_ID_SHIFT);
931 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
934 /* Set port's receive buffer size for assigned BM pool */
935 static inline void mvneta_bm_pool_bufsize_set(struct mvneta_port *pp,
941 if (!IS_ALIGNED(buf_size, 8)) {
942 dev_warn(pp->dev->dev.parent,
943 "illegal buf_size value %d, round to %d\n",
944 buf_size, ALIGN(buf_size, 8));
945 buf_size = ALIGN(buf_size, 8);
948 val = mvreg_read(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id));
949 val |= buf_size & MVNETA_PORT_POOL_BUFFER_SZ_MASK;
950 mvreg_write(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id), val);
953 /* Configure MBUS window in order to enable access BM internal SRAM */
954 static int mvneta_mbus_io_win_set(struct mvneta_port *pp, u32 base, u32 wsize,
957 u32 win_enable, win_protect;
960 win_enable = mvreg_read(pp, MVNETA_BASE_ADDR_ENABLE);
962 if (pp->bm_win_id < 0) {
963 /* Find first not occupied window */
964 for (i = 0; i < MVNETA_MAX_DECODE_WIN; i++) {
965 if (win_enable & (1 << i)) {
970 if (i == MVNETA_MAX_DECODE_WIN)
976 mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
977 mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
980 mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
982 mvreg_write(pp, MVNETA_WIN_BASE(i), (base & 0xffff0000) |
983 (attr << 8) | target);
985 mvreg_write(pp, MVNETA_WIN_SIZE(i), (wsize - 1) & 0xffff0000);
987 win_protect = mvreg_read(pp, MVNETA_ACCESS_PROTECT_ENABLE);
988 win_protect |= 3 << (2 * i);
989 mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect);
991 win_enable &= ~(1 << i);
992 mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
997 static int mvneta_bm_port_mbus_init(struct mvneta_port *pp)
1003 /* Get BM window information */
1004 err = mvebu_mbus_get_io_win_info(pp->bm_priv->bppi_phys_addr, &wsize,
1011 /* Open NETA -> BM window */
1012 err = mvneta_mbus_io_win_set(pp, pp->bm_priv->bppi_phys_addr, wsize,
1015 netdev_info(pp->dev, "fail to configure mbus window to BM\n");
1021 /* Assign and initialize pools for port. In case of fail
1022 * buffer manager will remain disabled for current port.
1024 static int mvneta_bm_port_init(struct platform_device *pdev,
1025 struct mvneta_port *pp)
1027 struct device_node *dn = pdev->dev.of_node;
1028 u32 long_pool_id, short_pool_id;
1030 if (!pp->neta_armada3700) {
1033 ret = mvneta_bm_port_mbus_init(pp);
1038 if (of_property_read_u32(dn, "bm,pool-long", &long_pool_id)) {
1039 netdev_info(pp->dev, "missing long pool id\n");
1043 /* Create port's long pool depending on mtu */
1044 pp->pool_long = mvneta_bm_pool_use(pp->bm_priv, long_pool_id,
1045 MVNETA_BM_LONG, pp->id,
1046 MVNETA_RX_PKT_SIZE(pp->dev->mtu));
1047 if (!pp->pool_long) {
1048 netdev_info(pp->dev, "fail to obtain long pool for port\n");
1052 pp->pool_long->port_map |= 1 << pp->id;
1054 mvneta_bm_pool_bufsize_set(pp, pp->pool_long->buf_size,
1057 /* If short pool id is not defined, assume using single pool */
1058 if (of_property_read_u32(dn, "bm,pool-short", &short_pool_id))
1059 short_pool_id = long_pool_id;
1061 /* Create port's short pool */
1062 pp->pool_short = mvneta_bm_pool_use(pp->bm_priv, short_pool_id,
1063 MVNETA_BM_SHORT, pp->id,
1064 MVNETA_BM_SHORT_PKT_SIZE);
1065 if (!pp->pool_short) {
1066 netdev_info(pp->dev, "fail to obtain short pool for port\n");
1067 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id);
1071 if (short_pool_id != long_pool_id) {
1072 pp->pool_short->port_map |= 1 << pp->id;
1073 mvneta_bm_pool_bufsize_set(pp, pp->pool_short->buf_size,
1074 pp->pool_short->id);
1080 /* Update settings of a pool for bigger packets */
1081 static void mvneta_bm_update_mtu(struct mvneta_port *pp, int mtu)
1083 struct mvneta_bm_pool *bm_pool = pp->pool_long;
1084 struct hwbm_pool *hwbm_pool = &bm_pool->hwbm_pool;
1087 /* Release all buffers from long pool */
1088 mvneta_bm_bufs_free(pp->bm_priv, bm_pool, 1 << pp->id);
1089 if (hwbm_pool->buf_num) {
1090 WARN(1, "cannot free all buffers in pool %d\n",
1095 bm_pool->pkt_size = MVNETA_RX_PKT_SIZE(mtu);
1096 bm_pool->buf_size = MVNETA_RX_BUF_SIZE(bm_pool->pkt_size);
1097 hwbm_pool->frag_size = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +
1098 SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(bm_pool->pkt_size));
1100 /* Fill entire long pool */
1101 num = hwbm_pool_add(hwbm_pool, hwbm_pool->size, GFP_ATOMIC);
1102 if (num != hwbm_pool->size) {
1103 WARN(1, "pool %d: %d of %d allocated\n",
1104 bm_pool->id, num, hwbm_pool->size);
1107 mvneta_bm_pool_bufsize_set(pp, bm_pool->buf_size, bm_pool->id);
1112 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id);
1113 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, 1 << pp->id);
1116 mvreg_write(pp, MVNETA_ACC_MODE, MVNETA_ACC_MODE_EXT1);
1117 netdev_info(pp->dev, "fail to update MTU, fall back to software BM\n");
1120 /* Start the Ethernet port RX and TX activity */
1121 static void mvneta_port_up(struct mvneta_port *pp)
1126 /* Enable all initialized TXs. */
1128 for (queue = 0; queue < txq_number; queue++) {
1129 struct mvneta_tx_queue *txq = &pp->txqs[queue];
1131 q_map |= (1 << queue);
1133 mvreg_write(pp, MVNETA_TXQ_CMD, q_map);
1136 /* Enable all initialized RXQs. */
1137 for (queue = 0; queue < rxq_number; queue++) {
1138 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
1141 q_map |= (1 << queue);
1143 mvreg_write(pp, MVNETA_RXQ_CMD, q_map);
1146 /* Stop the Ethernet port activity */
1147 static void mvneta_port_down(struct mvneta_port *pp)
1152 /* Stop Rx port activity. Check port Rx activity. */
1153 val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK;
1155 /* Issue stop command for active channels only */
1157 mvreg_write(pp, MVNETA_RXQ_CMD,
1158 val << MVNETA_RXQ_DISABLE_SHIFT);
1160 /* Wait for all Rx activity to terminate. */
1163 if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) {
1164 netdev_warn(pp->dev,
1165 "TIMEOUT for RX stopped ! rx_queue_cmd: 0x%08x\n",
1171 val = mvreg_read(pp, MVNETA_RXQ_CMD);
1172 } while (val & MVNETA_RXQ_ENABLE_MASK);
1174 /* Stop Tx port activity. Check port Tx activity. Issue stop
1175 * command for active channels only
1177 val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK;
1180 mvreg_write(pp, MVNETA_TXQ_CMD,
1181 (val << MVNETA_TXQ_DISABLE_SHIFT));
1183 /* Wait for all Tx activity to terminate. */
1186 if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) {
1187 netdev_warn(pp->dev,
1188 "TIMEOUT for TX stopped status=0x%08x\n",
1194 /* Check TX Command reg that all Txqs are stopped */
1195 val = mvreg_read(pp, MVNETA_TXQ_CMD);
1197 } while (val & MVNETA_TXQ_ENABLE_MASK);
1199 /* Double check to verify that TX FIFO is empty */
1202 if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) {
1203 netdev_warn(pp->dev,
1204 "TX FIFO empty timeout status=0x%08x\n",
1210 val = mvreg_read(pp, MVNETA_PORT_STATUS);
1211 } while (!(val & MVNETA_TX_FIFO_EMPTY) &&
1212 (val & MVNETA_TX_IN_PRGRS));
1217 /* Enable the port by setting the port enable bit of the MAC control register */
1218 static void mvneta_port_enable(struct mvneta_port *pp)
1223 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
1224 val |= MVNETA_GMAC0_PORT_ENABLE;
1225 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
1228 /* Disable the port and wait for about 200 usec before retuning */
1229 static void mvneta_port_disable(struct mvneta_port *pp)
1233 /* Reset the Enable bit in the Serial Control Register */
1234 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
1235 val &= ~MVNETA_GMAC0_PORT_ENABLE;
1236 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
1241 /* Multicast tables methods */
1243 /* Set all entries in Unicast MAC Table; queue==-1 means reject all */
1244 static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue)
1252 val = 0x1 | (queue << 1);
1253 val |= (val << 24) | (val << 16) | (val << 8);
1256 for (offset = 0; offset <= 0xc; offset += 4)
1257 mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val);
1260 /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */
1261 static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue)
1269 val = 0x1 | (queue << 1);
1270 val |= (val << 24) | (val << 16) | (val << 8);
1273 for (offset = 0; offset <= 0xfc; offset += 4)
1274 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val);
1278 /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */
1279 static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue)
1285 memset(pp->mcast_count, 0, sizeof(pp->mcast_count));
1288 memset(pp->mcast_count, 1, sizeof(pp->mcast_count));
1289 val = 0x1 | (queue << 1);
1290 val |= (val << 24) | (val << 16) | (val << 8);
1293 for (offset = 0; offset <= 0xfc; offset += 4)
1294 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val);
1297 static void mvneta_percpu_unmask_interrupt(void *arg)
1299 struct mvneta_port *pp = arg;
1301 /* All the queue are unmasked, but actually only the ones
1302 * mapped to this CPU will be unmasked
1304 mvreg_write(pp, MVNETA_INTR_NEW_MASK,
1305 MVNETA_RX_INTR_MASK_ALL |
1306 MVNETA_TX_INTR_MASK_ALL |
1307 MVNETA_MISCINTR_INTR_MASK);
1310 static void mvneta_percpu_mask_interrupt(void *arg)
1312 struct mvneta_port *pp = arg;
1314 /* All the queue are masked, but actually only the ones
1315 * mapped to this CPU will be masked
1317 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
1318 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
1319 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
1322 static void mvneta_percpu_clear_intr_cause(void *arg)
1324 struct mvneta_port *pp = arg;
1326 /* All the queue are cleared, but actually only the ones
1327 * mapped to this CPU will be cleared
1329 mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0);
1330 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
1331 mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
1334 /* This method sets defaults to the NETA port:
1335 * Clears interrupt Cause and Mask registers.
1336 * Clears all MAC tables.
1337 * Sets defaults to all registers.
1338 * Resets RX and TX descriptor rings.
1340 * This method can be called after mvneta_port_down() to return the port
1341 * settings to defaults.
1343 static void mvneta_defaults_set(struct mvneta_port *pp)
1348 int max_cpu = num_present_cpus();
1350 /* Clear all Cause registers */
1351 on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true);
1353 /* Mask all interrupts */
1354 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
1355 mvreg_write(pp, MVNETA_INTR_ENABLE, 0);
1357 /* Enable MBUS Retry bit16 */
1358 mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20);
1360 /* Set CPU queue access map. CPUs are assigned to the RX and
1361 * TX queues modulo their number. If there is only one TX
1362 * queue then it is assigned to the CPU associated to the
1365 for_each_present_cpu(cpu) {
1366 int rxq_map = 0, txq_map = 0;
1368 if (!pp->neta_armada3700) {
1369 for (rxq = 0; rxq < rxq_number; rxq++)
1370 if ((rxq % max_cpu) == cpu)
1371 rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq);
1373 for (txq = 0; txq < txq_number; txq++)
1374 if ((txq % max_cpu) == cpu)
1375 txq_map |= MVNETA_CPU_TXQ_ACCESS(txq);
1377 /* With only one TX queue we configure a special case
1378 * which will allow to get all the irq on a single
1381 if (txq_number == 1)
1382 txq_map = (cpu == pp->rxq_def) ?
1383 MVNETA_CPU_TXQ_ACCESS(1) : 0;
1386 txq_map = MVNETA_CPU_TXQ_ACCESS_ALL_MASK;
1387 rxq_map = MVNETA_CPU_RXQ_ACCESS_ALL_MASK;
1390 mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map);
1393 /* Reset RX and TX DMAs */
1394 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
1395 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
1397 /* Disable Legacy WRR, Disable EJP, Release from reset */
1398 mvreg_write(pp, MVNETA_TXQ_CMD_1, 0);
1399 for (queue = 0; queue < txq_number; queue++) {
1400 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0);
1401 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0);
1404 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
1405 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
1407 /* Set Port Acceleration Mode */
1409 /* HW buffer management + legacy parser */
1410 val = MVNETA_ACC_MODE_EXT2;
1412 /* SW buffer management + legacy parser */
1413 val = MVNETA_ACC_MODE_EXT1;
1414 mvreg_write(pp, MVNETA_ACC_MODE, val);
1417 mvreg_write(pp, MVNETA_BM_ADDRESS, pp->bm_priv->bppi_phys_addr);
1419 /* Update val of portCfg register accordingly with all RxQueue types */
1420 val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def);
1421 mvreg_write(pp, MVNETA_PORT_CONFIG, val);
1424 mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val);
1425 mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64);
1427 /* Build PORT_SDMA_CONFIG_REG */
1430 /* Default burst size */
1431 val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
1432 val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
1433 val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP;
1435 #if defined(__BIG_ENDIAN)
1436 val |= MVNETA_DESC_SWAP;
1439 /* Assign port SDMA configuration */
1440 mvreg_write(pp, MVNETA_SDMA_CONFIG, val);
1442 /* Disable PHY polling in hardware, since we're using the
1443 * kernel phylib to do this.
1445 val = mvreg_read(pp, MVNETA_UNIT_CONTROL);
1446 val &= ~MVNETA_PHY_POLLING_ENABLE;
1447 mvreg_write(pp, MVNETA_UNIT_CONTROL, val);
1449 mvneta_set_ucast_table(pp, -1);
1450 mvneta_set_special_mcast_table(pp, -1);
1451 mvneta_set_other_mcast_table(pp, -1);
1453 /* Set port interrupt enable register - default enable all */
1454 mvreg_write(pp, MVNETA_INTR_ENABLE,
1455 (MVNETA_RXQ_INTR_ENABLE_ALL_MASK
1456 | MVNETA_TXQ_INTR_ENABLE_ALL_MASK));
1458 mvneta_mib_counters_clear(pp);
1461 /* Set max sizes for tx queues */
1462 static void mvneta_txq_max_tx_size_set(struct mvneta_port *pp, int max_tx_size)
1468 mtu = max_tx_size * 8;
1469 if (mtu > MVNETA_TX_MTU_MAX)
1470 mtu = MVNETA_TX_MTU_MAX;
1473 val = mvreg_read(pp, MVNETA_TX_MTU);
1474 val &= ~MVNETA_TX_MTU_MAX;
1476 mvreg_write(pp, MVNETA_TX_MTU, val);
1478 /* TX token size and all TXQs token size must be larger that MTU */
1479 val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE);
1481 size = val & MVNETA_TX_TOKEN_SIZE_MAX;
1484 val &= ~MVNETA_TX_TOKEN_SIZE_MAX;
1486 mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val);
1488 for (queue = 0; queue < txq_number; queue++) {
1489 val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue));
1491 size = val & MVNETA_TXQ_TOKEN_SIZE_MAX;
1494 val &= ~MVNETA_TXQ_TOKEN_SIZE_MAX;
1496 mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val);
1501 /* Set unicast address */
1502 static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble,
1505 unsigned int unicast_reg;
1506 unsigned int tbl_offset;
1507 unsigned int reg_offset;
1509 /* Locate the Unicast table entry */
1510 last_nibble = (0xf & last_nibble);
1512 /* offset from unicast tbl base */
1513 tbl_offset = (last_nibble / 4) * 4;
1515 /* offset within the above reg */
1516 reg_offset = last_nibble % 4;
1518 unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset));
1521 /* Clear accepts frame bit at specified unicast DA tbl entry */
1522 unicast_reg &= ~(0xff << (8 * reg_offset));
1524 unicast_reg &= ~(0xff << (8 * reg_offset));
1525 unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
1528 mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg);
1531 /* Set mac address */
1532 static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr,
1539 mac_l = (addr[4] << 8) | (addr[5]);
1540 mac_h = (addr[0] << 24) | (addr[1] << 16) |
1541 (addr[2] << 8) | (addr[3] << 0);
1543 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l);
1544 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h);
1547 /* Accept frames of this address */
1548 mvneta_set_ucast_addr(pp, addr[5], queue);
1551 /* Set the number of packets that will be received before RX interrupt
1552 * will be generated by HW.
1554 static void mvneta_rx_pkts_coal_set(struct mvneta_port *pp,
1555 struct mvneta_rx_queue *rxq, u32 value)
1557 mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id),
1558 value | MVNETA_RXQ_NON_OCCUPIED(0));
1561 /* Set the time delay in usec before RX interrupt will be generated by
1564 static void mvneta_rx_time_coal_set(struct mvneta_port *pp,
1565 struct mvneta_rx_queue *rxq, u32 value)
1568 unsigned long clk_rate;
1570 clk_rate = clk_get_rate(pp->clk);
1571 val = (clk_rate / 1000000) * value;
1573 mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val);
1576 /* Set threshold for TX_DONE pkts coalescing */
1577 static void mvneta_tx_done_pkts_coal_set(struct mvneta_port *pp,
1578 struct mvneta_tx_queue *txq, u32 value)
1582 val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id));
1584 val &= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK;
1585 val |= MVNETA_TXQ_SENT_THRESH_MASK(value);
1587 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val);
1590 /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
1591 static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc,
1592 u32 phys_addr, void *virt_addr,
1593 struct mvneta_rx_queue *rxq)
1597 rx_desc->buf_phys_addr = phys_addr;
1598 i = rx_desc - rxq->descs;
1599 rxq->buf_virt_addr[i] = virt_addr;
1602 /* Decrement sent descriptors counter */
1603 static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp,
1604 struct mvneta_tx_queue *txq,
1609 /* Only 255 TX descriptors can be updated at once */
1610 while (sent_desc > 0xff) {
1611 val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT;
1612 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
1613 sent_desc = sent_desc - 0xff;
1616 val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT;
1617 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
1620 /* Get number of TX descriptors already sent by HW */
1621 static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp,
1622 struct mvneta_tx_queue *txq)
1627 val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id));
1628 sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >>
1629 MVNETA_TXQ_SENT_DESC_SHIFT;
1634 /* Get number of sent descriptors and decrement counter.
1635 * The number of sent descriptors is returned.
1637 static int mvneta_txq_sent_desc_proc(struct mvneta_port *pp,
1638 struct mvneta_tx_queue *txq)
1642 /* Get number of sent descriptors */
1643 sent_desc = mvneta_txq_sent_desc_num_get(pp, txq);
1645 /* Decrement sent descriptors counter */
1647 mvneta_txq_sent_desc_dec(pp, txq, sent_desc);
1652 /* Set TXQ descriptors fields relevant for CSUM calculation */
1653 static u32 mvneta_txq_desc_csum(int l3_offs, int l3_proto,
1654 int ip_hdr_len, int l4_proto)
1658 /* Fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk,
1659 * G_L4_chk, L4_type; required only for checksum
1662 command = l3_offs << MVNETA_TX_L3_OFF_SHIFT;
1663 command |= ip_hdr_len << MVNETA_TX_IP_HLEN_SHIFT;
1665 if (l3_proto == htons(ETH_P_IP))
1666 command |= MVNETA_TXD_IP_CSUM;
1668 command |= MVNETA_TX_L3_IP6;
1670 if (l4_proto == IPPROTO_TCP)
1671 command |= MVNETA_TX_L4_CSUM_FULL;
1672 else if (l4_proto == IPPROTO_UDP)
1673 command |= MVNETA_TX_L4_UDP | MVNETA_TX_L4_CSUM_FULL;
1675 command |= MVNETA_TX_L4_CSUM_NOT;
1681 /* Display more error info */
1682 static void mvneta_rx_error(struct mvneta_port *pp,
1683 struct mvneta_rx_desc *rx_desc)
1685 u32 status = rx_desc->status;
1687 if (!mvneta_rxq_desc_is_first_last(status)) {
1689 "bad rx status %08x (buffer oversize), size=%d\n",
1690 status, rx_desc->data_size);
1694 switch (status & MVNETA_RXD_ERR_CODE_MASK) {
1695 case MVNETA_RXD_ERR_CRC:
1696 netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n",
1697 status, rx_desc->data_size);
1699 case MVNETA_RXD_ERR_OVERRUN:
1700 netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n",
1701 status, rx_desc->data_size);
1703 case MVNETA_RXD_ERR_LEN:
1704 netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n",
1705 status, rx_desc->data_size);
1707 case MVNETA_RXD_ERR_RESOURCE:
1708 netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n",
1709 status, rx_desc->data_size);
1714 /* Handle RX checksum offload based on the descriptor's status */
1715 static void mvneta_rx_csum(struct mvneta_port *pp, u32 status,
1716 struct sk_buff *skb)
1718 if ((status & MVNETA_RXD_L3_IP4) &&
1719 (status & MVNETA_RXD_L4_CSUM_OK)) {
1721 skb->ip_summed = CHECKSUM_UNNECESSARY;
1725 skb->ip_summed = CHECKSUM_NONE;
1728 /* Return tx queue pointer (find last set bit) according to <cause> returned
1729 * form tx_done reg. <cause> must not be null. The return value is always a
1730 * valid queue for matching the first one found in <cause>.
1732 static struct mvneta_tx_queue *mvneta_tx_done_policy(struct mvneta_port *pp,
1735 int queue = fls(cause) - 1;
1737 return &pp->txqs[queue];
1740 /* Free tx queue skbuffs */
1741 static void mvneta_txq_bufs_free(struct mvneta_port *pp,
1742 struct mvneta_tx_queue *txq, int num,
1743 struct netdev_queue *nq)
1745 unsigned int bytes_compl = 0, pkts_compl = 0;
1748 for (i = 0; i < num; i++) {
1749 struct mvneta_tx_desc *tx_desc = txq->descs +
1751 struct sk_buff *skb = txq->tx_skb[txq->txq_get_index];
1754 bytes_compl += skb->len;
1758 mvneta_txq_inc_get(txq);
1760 if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr))
1761 dma_unmap_single(pp->dev->dev.parent,
1762 tx_desc->buf_phys_addr,
1763 tx_desc->data_size, DMA_TO_DEVICE);
1766 dev_kfree_skb_any(skb);
1769 netdev_tx_completed_queue(nq, pkts_compl, bytes_compl);
1772 /* Handle end of transmission */
1773 static void mvneta_txq_done(struct mvneta_port *pp,
1774 struct mvneta_tx_queue *txq)
1776 struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id);
1779 tx_done = mvneta_txq_sent_desc_proc(pp, txq);
1783 mvneta_txq_bufs_free(pp, txq, tx_done, nq);
1785 txq->count -= tx_done;
1787 if (netif_tx_queue_stopped(nq)) {
1788 if (txq->count <= txq->tx_wake_threshold)
1789 netif_tx_wake_queue(nq);
1793 void *mvneta_frag_alloc(unsigned int frag_size)
1795 if (likely(frag_size <= PAGE_SIZE))
1796 return netdev_alloc_frag(frag_size);
1798 return kmalloc(frag_size, GFP_ATOMIC);
1800 EXPORT_SYMBOL_GPL(mvneta_frag_alloc);
1802 void mvneta_frag_free(unsigned int frag_size, void *data)
1804 if (likely(frag_size <= PAGE_SIZE))
1805 skb_free_frag(data);
1809 EXPORT_SYMBOL_GPL(mvneta_frag_free);
1811 /* Refill processing for SW buffer management */
1812 static int mvneta_rx_refill(struct mvneta_port *pp,
1813 struct mvneta_rx_desc *rx_desc,
1814 struct mvneta_rx_queue *rxq)
1817 dma_addr_t phys_addr;
1820 data = mvneta_frag_alloc(pp->frag_size);
1824 phys_addr = dma_map_single(pp->dev->dev.parent, data,
1825 MVNETA_RX_BUF_SIZE(pp->pkt_size),
1827 if (unlikely(dma_mapping_error(pp->dev->dev.parent, phys_addr))) {
1828 mvneta_frag_free(pp->frag_size, data);
1832 phys_addr += pp->rx_offset_correction;
1833 mvneta_rx_desc_fill(rx_desc, phys_addr, data, rxq);
1837 /* Handle tx checksum */
1838 static u32 mvneta_skb_tx_csum(struct mvneta_port *pp, struct sk_buff *skb)
1840 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1842 __be16 l3_proto = vlan_get_protocol(skb);
1845 if (l3_proto == htons(ETH_P_IP)) {
1846 struct iphdr *ip4h = ip_hdr(skb);
1848 /* Calculate IPv4 checksum and L4 checksum */
1849 ip_hdr_len = ip4h->ihl;
1850 l4_proto = ip4h->protocol;
1851 } else if (l3_proto == htons(ETH_P_IPV6)) {
1852 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1854 /* Read l4_protocol from one of IPv6 extra headers */
1855 if (skb_network_header_len(skb) > 0)
1856 ip_hdr_len = (skb_network_header_len(skb) >> 2);
1857 l4_proto = ip6h->nexthdr;
1859 return MVNETA_TX_L4_CSUM_NOT;
1861 return mvneta_txq_desc_csum(skb_network_offset(skb),
1862 l3_proto, ip_hdr_len, l4_proto);
1865 return MVNETA_TX_L4_CSUM_NOT;
1868 /* Drop packets received by the RXQ and free buffers */
1869 static void mvneta_rxq_drop_pkts(struct mvneta_port *pp,
1870 struct mvneta_rx_queue *rxq)
1874 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
1876 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
1879 for (i = 0; i < rx_done; i++) {
1880 struct mvneta_rx_desc *rx_desc =
1881 mvneta_rxq_next_desc_get(rxq);
1882 u8 pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc);
1883 struct mvneta_bm_pool *bm_pool;
1885 bm_pool = &pp->bm_priv->bm_pools[pool_id];
1886 /* Return dropped buffer to the pool */
1887 mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool,
1888 rx_desc->buf_phys_addr);
1893 for (i = 0; i < rxq->size; i++) {
1894 struct mvneta_rx_desc *rx_desc = rxq->descs + i;
1895 void *data = rxq->buf_virt_addr[i];
1897 dma_unmap_single(pp->dev->dev.parent, rx_desc->buf_phys_addr,
1898 MVNETA_RX_BUF_SIZE(pp->pkt_size), DMA_FROM_DEVICE);
1899 mvneta_frag_free(pp->frag_size, data);
1903 /* Main rx processing when using software buffer management */
1904 static int mvneta_rx_swbm(struct mvneta_port *pp, int rx_todo,
1905 struct mvneta_rx_queue *rxq)
1907 struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports);
1908 struct net_device *dev = pp->dev;
1913 /* Get number of received packets */
1914 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
1916 if (rx_todo > rx_done)
1921 /* Fairness NAPI loop */
1922 while (rx_done < rx_todo) {
1923 struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq);
1924 struct sk_buff *skb;
1925 unsigned char *data;
1926 dma_addr_t phys_addr;
1927 u32 rx_status, frag_size;
1928 int rx_bytes, err, index;
1931 rx_status = rx_desc->status;
1932 rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE);
1933 index = rx_desc - rxq->descs;
1934 data = rxq->buf_virt_addr[index];
1935 phys_addr = rx_desc->buf_phys_addr;
1937 if (!mvneta_rxq_desc_is_first_last(rx_status) ||
1938 (rx_status & MVNETA_RXD_ERR_SUMMARY)) {
1939 mvneta_rx_error(pp, rx_desc);
1941 dev->stats.rx_errors++;
1942 /* leave the descriptor untouched */
1946 if (rx_bytes <= rx_copybreak) {
1947 /* better copy a small frame and not unmap the DMA region */
1948 skb = netdev_alloc_skb_ip_align(dev, rx_bytes);
1950 goto err_drop_frame;
1952 dma_sync_single_range_for_cpu(dev->dev.parent,
1954 MVNETA_MH_SIZE + NET_SKB_PAD,
1957 skb_put_data(skb, data + MVNETA_MH_SIZE + NET_SKB_PAD,
1960 skb->protocol = eth_type_trans(skb, dev);
1961 mvneta_rx_csum(pp, rx_status, skb);
1962 napi_gro_receive(&port->napi, skb);
1965 rcvd_bytes += rx_bytes;
1967 /* leave the descriptor and buffer untouched */
1971 /* Refill processing */
1972 err = mvneta_rx_refill(pp, rx_desc, rxq);
1974 netdev_err(dev, "Linux processing - Can't refill\n");
1976 goto err_drop_frame;
1979 frag_size = pp->frag_size;
1981 skb = build_skb(data, frag_size > PAGE_SIZE ? 0 : frag_size);
1983 /* After refill old buffer has to be unmapped regardless
1984 * the skb is successfully built or not.
1986 dma_unmap_single(dev->dev.parent, phys_addr,
1987 MVNETA_RX_BUF_SIZE(pp->pkt_size),
1991 goto err_drop_frame;
1994 rcvd_bytes += rx_bytes;
1996 /* Linux processing */
1997 skb_reserve(skb, MVNETA_MH_SIZE + NET_SKB_PAD);
1998 skb_put(skb, rx_bytes);
2000 skb->protocol = eth_type_trans(skb, dev);
2002 mvneta_rx_csum(pp, rx_status, skb);
2004 napi_gro_receive(&port->napi, skb);
2008 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
2010 u64_stats_update_begin(&stats->syncp);
2011 stats->rx_packets += rcvd_pkts;
2012 stats->rx_bytes += rcvd_bytes;
2013 u64_stats_update_end(&stats->syncp);
2016 /* Update rxq management counters */
2017 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
2022 /* Main rx processing when using hardware buffer management */
2023 static int mvneta_rx_hwbm(struct mvneta_port *pp, int rx_todo,
2024 struct mvneta_rx_queue *rxq)
2026 struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports);
2027 struct net_device *dev = pp->dev;
2032 /* Get number of received packets */
2033 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
2035 if (rx_todo > rx_done)
2040 /* Fairness NAPI loop */
2041 while (rx_done < rx_todo) {
2042 struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq);
2043 struct mvneta_bm_pool *bm_pool = NULL;
2044 struct sk_buff *skb;
2045 unsigned char *data;
2046 dma_addr_t phys_addr;
2047 u32 rx_status, frag_size;
2052 rx_status = rx_desc->status;
2053 rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE);
2054 data = (u8 *)(uintptr_t)rx_desc->buf_cookie;
2055 phys_addr = rx_desc->buf_phys_addr;
2056 pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc);
2057 bm_pool = &pp->bm_priv->bm_pools[pool_id];
2059 if (!mvneta_rxq_desc_is_first_last(rx_status) ||
2060 (rx_status & MVNETA_RXD_ERR_SUMMARY)) {
2061 err_drop_frame_ret_pool:
2062 /* Return the buffer to the pool */
2063 mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool,
2064 rx_desc->buf_phys_addr);
2066 dev->stats.rx_errors++;
2067 mvneta_rx_error(pp, rx_desc);
2068 /* leave the descriptor untouched */
2072 if (rx_bytes <= rx_copybreak) {
2073 /* better copy a small frame and not unmap the DMA region */
2074 skb = netdev_alloc_skb_ip_align(dev, rx_bytes);
2076 goto err_drop_frame_ret_pool;
2078 dma_sync_single_range_for_cpu(dev->dev.parent,
2079 rx_desc->buf_phys_addr,
2080 MVNETA_MH_SIZE + NET_SKB_PAD,
2083 skb_put_data(skb, data + MVNETA_MH_SIZE + NET_SKB_PAD,
2086 skb->protocol = eth_type_trans(skb, dev);
2087 mvneta_rx_csum(pp, rx_status, skb);
2088 napi_gro_receive(&port->napi, skb);
2091 rcvd_bytes += rx_bytes;
2093 /* Return the buffer to the pool */
2094 mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool,
2095 rx_desc->buf_phys_addr);
2097 /* leave the descriptor and buffer untouched */
2101 /* Refill processing */
2102 err = hwbm_pool_refill(&bm_pool->hwbm_pool, GFP_ATOMIC);
2104 netdev_err(dev, "Linux processing - Can't refill\n");
2106 goto err_drop_frame_ret_pool;
2109 frag_size = bm_pool->hwbm_pool.frag_size;
2111 skb = build_skb(data, frag_size > PAGE_SIZE ? 0 : frag_size);
2113 /* After refill old buffer has to be unmapped regardless
2114 * the skb is successfully built or not.
2116 dma_unmap_single(&pp->bm_priv->pdev->dev, phys_addr,
2117 bm_pool->buf_size, DMA_FROM_DEVICE);
2119 goto err_drop_frame;
2122 rcvd_bytes += rx_bytes;
2124 /* Linux processing */
2125 skb_reserve(skb, MVNETA_MH_SIZE + NET_SKB_PAD);
2126 skb_put(skb, rx_bytes);
2128 skb->protocol = eth_type_trans(skb, dev);
2130 mvneta_rx_csum(pp, rx_status, skb);
2132 napi_gro_receive(&port->napi, skb);
2136 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
2138 u64_stats_update_begin(&stats->syncp);
2139 stats->rx_packets += rcvd_pkts;
2140 stats->rx_bytes += rcvd_bytes;
2141 u64_stats_update_end(&stats->syncp);
2144 /* Update rxq management counters */
2145 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
2151 mvneta_tso_put_hdr(struct sk_buff *skb,
2152 struct mvneta_port *pp, struct mvneta_tx_queue *txq)
2154 struct mvneta_tx_desc *tx_desc;
2155 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2157 txq->tx_skb[txq->txq_put_index] = NULL;
2158 tx_desc = mvneta_txq_next_desc_get(txq);
2159 tx_desc->data_size = hdr_len;
2160 tx_desc->command = mvneta_skb_tx_csum(pp, skb);
2161 tx_desc->command |= MVNETA_TXD_F_DESC;
2162 tx_desc->buf_phys_addr = txq->tso_hdrs_phys +
2163 txq->txq_put_index * TSO_HEADER_SIZE;
2164 mvneta_txq_inc_put(txq);
2168 mvneta_tso_put_data(struct net_device *dev, struct mvneta_tx_queue *txq,
2169 struct sk_buff *skb, char *data, int size,
2170 bool last_tcp, bool is_last)
2172 struct mvneta_tx_desc *tx_desc;
2174 tx_desc = mvneta_txq_next_desc_get(txq);
2175 tx_desc->data_size = size;
2176 tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, data,
2177 size, DMA_TO_DEVICE);
2178 if (unlikely(dma_mapping_error(dev->dev.parent,
2179 tx_desc->buf_phys_addr))) {
2180 mvneta_txq_desc_put(txq);
2184 tx_desc->command = 0;
2185 txq->tx_skb[txq->txq_put_index] = NULL;
2188 /* last descriptor in the TCP packet */
2189 tx_desc->command = MVNETA_TXD_L_DESC;
2191 /* last descriptor in SKB */
2193 txq->tx_skb[txq->txq_put_index] = skb;
2195 mvneta_txq_inc_put(txq);
2199 static int mvneta_tx_tso(struct sk_buff *skb, struct net_device *dev,
2200 struct mvneta_tx_queue *txq)
2202 int total_len, data_left;
2204 struct mvneta_port *pp = netdev_priv(dev);
2206 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2209 /* Count needed descriptors */
2210 if ((txq->count + tso_count_descs(skb)) >= txq->size)
2213 if (skb_headlen(skb) < (skb_transport_offset(skb) + tcp_hdrlen(skb))) {
2214 pr_info("*** Is this even possible???!?!?\n");
2218 /* Initialize the TSO handler, and prepare the first payload */
2219 tso_start(skb, &tso);
2221 total_len = skb->len - hdr_len;
2222 while (total_len > 0) {
2225 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
2226 total_len -= data_left;
2229 /* prepare packet headers: MAC + IP + TCP */
2230 hdr = txq->tso_hdrs + txq->txq_put_index * TSO_HEADER_SIZE;
2231 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
2233 mvneta_tso_put_hdr(skb, pp, txq);
2235 while (data_left > 0) {
2239 size = min_t(int, tso.size, data_left);
2241 if (mvneta_tso_put_data(dev, txq, skb,
2248 tso_build_data(skb, &tso, size);
2255 /* Release all used data descriptors; header descriptors must not
2258 for (i = desc_count - 1; i >= 0; i--) {
2259 struct mvneta_tx_desc *tx_desc = txq->descs + i;
2260 if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr))
2261 dma_unmap_single(pp->dev->dev.parent,
2262 tx_desc->buf_phys_addr,
2265 mvneta_txq_desc_put(txq);
2270 /* Handle tx fragmentation processing */
2271 static int mvneta_tx_frag_process(struct mvneta_port *pp, struct sk_buff *skb,
2272 struct mvneta_tx_queue *txq)
2274 struct mvneta_tx_desc *tx_desc;
2275 int i, nr_frags = skb_shinfo(skb)->nr_frags;
2277 for (i = 0; i < nr_frags; i++) {
2278 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2279 void *addr = page_address(frag->page.p) + frag->page_offset;
2281 tx_desc = mvneta_txq_next_desc_get(txq);
2282 tx_desc->data_size = frag->size;
2284 tx_desc->buf_phys_addr =
2285 dma_map_single(pp->dev->dev.parent, addr,
2286 tx_desc->data_size, DMA_TO_DEVICE);
2288 if (dma_mapping_error(pp->dev->dev.parent,
2289 tx_desc->buf_phys_addr)) {
2290 mvneta_txq_desc_put(txq);
2294 if (i == nr_frags - 1) {
2295 /* Last descriptor */
2296 tx_desc->command = MVNETA_TXD_L_DESC | MVNETA_TXD_Z_PAD;
2297 txq->tx_skb[txq->txq_put_index] = skb;
2299 /* Descriptor in the middle: Not First, Not Last */
2300 tx_desc->command = 0;
2301 txq->tx_skb[txq->txq_put_index] = NULL;
2303 mvneta_txq_inc_put(txq);
2309 /* Release all descriptors that were used to map fragments of
2310 * this packet, as well as the corresponding DMA mappings
2312 for (i = i - 1; i >= 0; i--) {
2313 tx_desc = txq->descs + i;
2314 dma_unmap_single(pp->dev->dev.parent,
2315 tx_desc->buf_phys_addr,
2318 mvneta_txq_desc_put(txq);
2324 /* Main tx processing */
2325 static int mvneta_tx(struct sk_buff *skb, struct net_device *dev)
2327 struct mvneta_port *pp = netdev_priv(dev);
2328 u16 txq_id = skb_get_queue_mapping(skb);
2329 struct mvneta_tx_queue *txq = &pp->txqs[txq_id];
2330 struct mvneta_tx_desc *tx_desc;
2335 if (!netif_running(dev))
2338 if (skb_is_gso(skb)) {
2339 frags = mvneta_tx_tso(skb, dev, txq);
2343 frags = skb_shinfo(skb)->nr_frags + 1;
2345 /* Get a descriptor for the first part of the packet */
2346 tx_desc = mvneta_txq_next_desc_get(txq);
2348 tx_cmd = mvneta_skb_tx_csum(pp, skb);
2350 tx_desc->data_size = skb_headlen(skb);
2352 tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, skb->data,
2355 if (unlikely(dma_mapping_error(dev->dev.parent,
2356 tx_desc->buf_phys_addr))) {
2357 mvneta_txq_desc_put(txq);
2363 /* First and Last descriptor */
2364 tx_cmd |= MVNETA_TXD_FLZ_DESC;
2365 tx_desc->command = tx_cmd;
2366 txq->tx_skb[txq->txq_put_index] = skb;
2367 mvneta_txq_inc_put(txq);
2369 /* First but not Last */
2370 tx_cmd |= MVNETA_TXD_F_DESC;
2371 txq->tx_skb[txq->txq_put_index] = NULL;
2372 mvneta_txq_inc_put(txq);
2373 tx_desc->command = tx_cmd;
2374 /* Continue with other skb fragments */
2375 if (mvneta_tx_frag_process(pp, skb, txq)) {
2376 dma_unmap_single(dev->dev.parent,
2377 tx_desc->buf_phys_addr,
2380 mvneta_txq_desc_put(txq);
2388 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
2389 struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id);
2391 netdev_tx_sent_queue(nq, len);
2393 txq->count += frags;
2394 if (txq->count >= txq->tx_stop_threshold)
2395 netif_tx_stop_queue(nq);
2397 if (!skb->xmit_more || netif_xmit_stopped(nq) ||
2398 txq->pending + frags > MVNETA_TXQ_DEC_SENT_MASK)
2399 mvneta_txq_pend_desc_add(pp, txq, frags);
2401 txq->pending += frags;
2403 u64_stats_update_begin(&stats->syncp);
2404 stats->tx_packets++;
2405 stats->tx_bytes += len;
2406 u64_stats_update_end(&stats->syncp);
2408 dev->stats.tx_dropped++;
2409 dev_kfree_skb_any(skb);
2412 return NETDEV_TX_OK;
2416 /* Free tx resources, when resetting a port */
2417 static void mvneta_txq_done_force(struct mvneta_port *pp,
2418 struct mvneta_tx_queue *txq)
2421 struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id);
2422 int tx_done = txq->count;
2424 mvneta_txq_bufs_free(pp, txq, tx_done, nq);
2428 txq->txq_put_index = 0;
2429 txq->txq_get_index = 0;
2432 /* Handle tx done - called in softirq context. The <cause_tx_done> argument
2433 * must be a valid cause according to MVNETA_TXQ_INTR_MASK_ALL.
2435 static void mvneta_tx_done_gbe(struct mvneta_port *pp, u32 cause_tx_done)
2437 struct mvneta_tx_queue *txq;
2438 struct netdev_queue *nq;
2440 while (cause_tx_done) {
2441 txq = mvneta_tx_done_policy(pp, cause_tx_done);
2443 nq = netdev_get_tx_queue(pp->dev, txq->id);
2444 __netif_tx_lock(nq, smp_processor_id());
2447 mvneta_txq_done(pp, txq);
2449 __netif_tx_unlock(nq);
2450 cause_tx_done &= ~((1 << txq->id));
2454 /* Compute crc8 of the specified address, using a unique algorithm ,
2455 * according to hw spec, different than generic crc8 algorithm
2457 static int mvneta_addr_crc(unsigned char *addr)
2462 for (i = 0; i < ETH_ALEN; i++) {
2465 crc = (crc ^ addr[i]) << 8;
2466 for (j = 7; j >= 0; j--) {
2467 if (crc & (0x100 << j))
2475 /* This method controls the net device special MAC multicast support.
2476 * The Special Multicast Table for MAC addresses supports MAC of the form
2477 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
2478 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
2479 * Table entries in the DA-Filter table. This method set the Special
2480 * Multicast Table appropriate entry.
2482 static void mvneta_set_special_mcast_addr(struct mvneta_port *pp,
2483 unsigned char last_byte,
2486 unsigned int smc_table_reg;
2487 unsigned int tbl_offset;
2488 unsigned int reg_offset;
2490 /* Register offset from SMC table base */
2491 tbl_offset = (last_byte / 4);
2492 /* Entry offset within the above reg */
2493 reg_offset = last_byte % 4;
2495 smc_table_reg = mvreg_read(pp, (MVNETA_DA_FILT_SPEC_MCAST
2499 smc_table_reg &= ~(0xff << (8 * reg_offset));
2501 smc_table_reg &= ~(0xff << (8 * reg_offset));
2502 smc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
2505 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4,
2509 /* This method controls the network device Other MAC multicast support.
2510 * The Other Multicast Table is used for multicast of another type.
2511 * A CRC-8 is used as an index to the Other Multicast Table entries
2512 * in the DA-Filter table.
2513 * The method gets the CRC-8 value from the calling routine and
2514 * sets the Other Multicast Table appropriate entry according to the
2517 static void mvneta_set_other_mcast_addr(struct mvneta_port *pp,
2521 unsigned int omc_table_reg;
2522 unsigned int tbl_offset;
2523 unsigned int reg_offset;
2525 tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */
2526 reg_offset = crc8 % 4; /* Entry offset within the above reg */
2528 omc_table_reg = mvreg_read(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset);
2531 /* Clear accepts frame bit at specified Other DA table entry */
2532 omc_table_reg &= ~(0xff << (8 * reg_offset));
2534 omc_table_reg &= ~(0xff << (8 * reg_offset));
2535 omc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
2538 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg);
2541 /* The network device supports multicast using two tables:
2542 * 1) Special Multicast Table for MAC addresses of the form
2543 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
2544 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
2545 * Table entries in the DA-Filter table.
2546 * 2) Other Multicast Table for multicast of another type. A CRC-8 value
2547 * is used as an index to the Other Multicast Table entries in the
2550 static int mvneta_mcast_addr_set(struct mvneta_port *pp, unsigned char *p_addr,
2553 unsigned char crc_result = 0;
2555 if (memcmp(p_addr, "\x01\x00\x5e\x00\x00", 5) == 0) {
2556 mvneta_set_special_mcast_addr(pp, p_addr[5], queue);
2560 crc_result = mvneta_addr_crc(p_addr);
2562 if (pp->mcast_count[crc_result] == 0) {
2563 netdev_info(pp->dev, "No valid Mcast for crc8=0x%02x\n",
2568 pp->mcast_count[crc_result]--;
2569 if (pp->mcast_count[crc_result] != 0) {
2570 netdev_info(pp->dev,
2571 "After delete there are %d valid Mcast for crc8=0x%02x\n",
2572 pp->mcast_count[crc_result], crc_result);
2576 pp->mcast_count[crc_result]++;
2578 mvneta_set_other_mcast_addr(pp, crc_result, queue);
2583 /* Configure Fitering mode of Ethernet port */
2584 static void mvneta_rx_unicast_promisc_set(struct mvneta_port *pp,
2587 u32 port_cfg_reg, val;
2589 port_cfg_reg = mvreg_read(pp, MVNETA_PORT_CONFIG);
2591 val = mvreg_read(pp, MVNETA_TYPE_PRIO);
2593 /* Set / Clear UPM bit in port configuration register */
2595 /* Accept all Unicast addresses */
2596 port_cfg_reg |= MVNETA_UNI_PROMISC_MODE;
2597 val |= MVNETA_FORCE_UNI;
2598 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff);
2599 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff);
2601 /* Reject all Unicast addresses */
2602 port_cfg_reg &= ~MVNETA_UNI_PROMISC_MODE;
2603 val &= ~MVNETA_FORCE_UNI;
2606 mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg);
2607 mvreg_write(pp, MVNETA_TYPE_PRIO, val);
2610 /* register unicast and multicast addresses */
2611 static void mvneta_set_rx_mode(struct net_device *dev)
2613 struct mvneta_port *pp = netdev_priv(dev);
2614 struct netdev_hw_addr *ha;
2616 if (dev->flags & IFF_PROMISC) {
2617 /* Accept all: Multicast + Unicast */
2618 mvneta_rx_unicast_promisc_set(pp, 1);
2619 mvneta_set_ucast_table(pp, pp->rxq_def);
2620 mvneta_set_special_mcast_table(pp, pp->rxq_def);
2621 mvneta_set_other_mcast_table(pp, pp->rxq_def);
2623 /* Accept single Unicast */
2624 mvneta_rx_unicast_promisc_set(pp, 0);
2625 mvneta_set_ucast_table(pp, -1);
2626 mvneta_mac_addr_set(pp, dev->dev_addr, pp->rxq_def);
2628 if (dev->flags & IFF_ALLMULTI) {
2629 /* Accept all multicast */
2630 mvneta_set_special_mcast_table(pp, pp->rxq_def);
2631 mvneta_set_other_mcast_table(pp, pp->rxq_def);
2633 /* Accept only initialized multicast */
2634 mvneta_set_special_mcast_table(pp, -1);
2635 mvneta_set_other_mcast_table(pp, -1);
2637 if (!netdev_mc_empty(dev)) {
2638 netdev_for_each_mc_addr(ha, dev) {
2639 mvneta_mcast_addr_set(pp, ha->addr,
2647 /* Interrupt handling - the callback for request_irq() */
2648 static irqreturn_t mvneta_isr(int irq, void *dev_id)
2650 struct mvneta_port *pp = (struct mvneta_port *)dev_id;
2652 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
2653 napi_schedule(&pp->napi);
2658 /* Interrupt handling - the callback for request_percpu_irq() */
2659 static irqreturn_t mvneta_percpu_isr(int irq, void *dev_id)
2661 struct mvneta_pcpu_port *port = (struct mvneta_pcpu_port *)dev_id;
2663 disable_percpu_irq(port->pp->dev->irq);
2664 napi_schedule(&port->napi);
2669 static void mvneta_link_change(struct mvneta_port *pp)
2671 u32 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS);
2673 phylink_mac_change(pp->phylink, !!(gmac_stat & MVNETA_GMAC_LINK_UP));
2677 * Bits 0 - 7 of the causeRxTx register indicate that are transmitted
2678 * packets on the corresponding TXQ (Bit 0 is for TX queue 1).
2679 * Bits 8 -15 of the cause Rx Tx register indicate that are received
2680 * packets on the corresponding RXQ (Bit 8 is for RX queue 0).
2681 * Each CPU has its own causeRxTx register
2683 static int mvneta_poll(struct napi_struct *napi, int budget)
2688 struct mvneta_port *pp = netdev_priv(napi->dev);
2689 struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports);
2691 if (!netif_running(pp->dev)) {
2692 napi_complete(napi);
2696 /* Read cause register */
2697 cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE);
2698 if (cause_rx_tx & MVNETA_MISCINTR_INTR_MASK) {
2699 u32 cause_misc = mvreg_read(pp, MVNETA_INTR_MISC_CAUSE);
2701 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
2703 if (cause_misc & (MVNETA_CAUSE_PHY_STATUS_CHANGE |
2704 MVNETA_CAUSE_LINK_CHANGE))
2705 mvneta_link_change(pp);
2708 /* Release Tx descriptors */
2709 if (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL) {
2710 mvneta_tx_done_gbe(pp, (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL));
2711 cause_rx_tx &= ~MVNETA_TX_INTR_MASK_ALL;
2714 /* For the case where the last mvneta_poll did not process all
2717 rx_queue = fls(((cause_rx_tx >> 8) & 0xff));
2719 cause_rx_tx |= pp->neta_armada3700 ? pp->cause_rx_tx :
2723 rx_queue = rx_queue - 1;
2725 rx_done = mvneta_rx_hwbm(pp, budget, &pp->rxqs[rx_queue]);
2727 rx_done = mvneta_rx_swbm(pp, budget, &pp->rxqs[rx_queue]);
2730 if (rx_done < budget) {
2732 napi_complete_done(napi, rx_done);
2734 if (pp->neta_armada3700) {
2735 unsigned long flags;
2737 local_irq_save(flags);
2738 mvreg_write(pp, MVNETA_INTR_NEW_MASK,
2739 MVNETA_RX_INTR_MASK(rxq_number) |
2740 MVNETA_TX_INTR_MASK(txq_number) |
2741 MVNETA_MISCINTR_INTR_MASK);
2742 local_irq_restore(flags);
2744 enable_percpu_irq(pp->dev->irq, 0);
2748 if (pp->neta_armada3700)
2749 pp->cause_rx_tx = cause_rx_tx;
2751 port->cause_rx_tx = cause_rx_tx;
2756 /* Handle rxq fill: allocates rxq skbs; called when initializing a port */
2757 static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq,
2762 for (i = 0; i < num; i++) {
2763 memset(rxq->descs + i, 0, sizeof(struct mvneta_rx_desc));
2764 if (mvneta_rx_refill(pp, rxq->descs + i, rxq) != 0) {
2765 netdev_err(pp->dev, "%s:rxq %d, %d of %d buffs filled\n",
2766 __func__, rxq->id, i, num);
2771 /* Add this number of RX descriptors as non occupied (ready to
2774 mvneta_rxq_non_occup_desc_add(pp, rxq, i);
2779 /* Free all packets pending transmit from all TXQs and reset TX port */
2780 static void mvneta_tx_reset(struct mvneta_port *pp)
2784 /* free the skb's in the tx ring */
2785 for (queue = 0; queue < txq_number; queue++)
2786 mvneta_txq_done_force(pp, &pp->txqs[queue]);
2788 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
2789 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
2792 static void mvneta_rx_reset(struct mvneta_port *pp)
2794 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
2795 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
2798 /* Rx/Tx queue initialization/cleanup methods */
2800 static int mvneta_rxq_sw_init(struct mvneta_port *pp,
2801 struct mvneta_rx_queue *rxq)
2803 rxq->size = pp->rx_ring_size;
2805 /* Allocate memory for RX descriptors */
2806 rxq->descs = dma_alloc_coherent(pp->dev->dev.parent,
2807 rxq->size * MVNETA_DESC_ALIGNED_SIZE,
2808 &rxq->descs_phys, GFP_KERNEL);
2812 rxq->last_desc = rxq->size - 1;
2817 static void mvneta_rxq_hw_init(struct mvneta_port *pp,
2818 struct mvneta_rx_queue *rxq)
2820 /* Set Rx descriptors queue starting address */
2821 mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys);
2822 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size);
2825 mvneta_rxq_offset_set(pp, rxq, NET_SKB_PAD - pp->rx_offset_correction);
2827 /* Set coalescing pkts and time */
2828 mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal);
2829 mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal);
2832 /* Fill RXQ with buffers from RX pool */
2833 mvneta_rxq_buf_size_set(pp, rxq,
2834 MVNETA_RX_BUF_SIZE(pp->pkt_size));
2835 mvneta_rxq_bm_disable(pp, rxq);
2836 mvneta_rxq_fill(pp, rxq, rxq->size);
2838 mvneta_rxq_bm_enable(pp, rxq);
2839 mvneta_rxq_long_pool_set(pp, rxq);
2840 mvneta_rxq_short_pool_set(pp, rxq);
2841 mvneta_rxq_non_occup_desc_add(pp, rxq, rxq->size);
2845 /* Create a specified RX queue */
2846 static int mvneta_rxq_init(struct mvneta_port *pp,
2847 struct mvneta_rx_queue *rxq)
2852 ret = mvneta_rxq_sw_init(pp, rxq);
2856 mvneta_rxq_hw_init(pp, rxq);
2861 /* Cleanup Rx queue */
2862 static void mvneta_rxq_deinit(struct mvneta_port *pp,
2863 struct mvneta_rx_queue *rxq)
2865 mvneta_rxq_drop_pkts(pp, rxq);
2868 dma_free_coherent(pp->dev->dev.parent,
2869 rxq->size * MVNETA_DESC_ALIGNED_SIZE,
2875 rxq->next_desc_to_proc = 0;
2876 rxq->descs_phys = 0;
2879 static int mvneta_txq_sw_init(struct mvneta_port *pp,
2880 struct mvneta_tx_queue *txq)
2884 txq->size = pp->tx_ring_size;
2886 /* A queue must always have room for at least one skb.
2887 * Therefore, stop the queue when the free entries reaches
2888 * the maximum number of descriptors per skb.
2890 txq->tx_stop_threshold = txq->size - MVNETA_MAX_SKB_DESCS;
2891 txq->tx_wake_threshold = txq->tx_stop_threshold / 2;
2893 /* Allocate memory for TX descriptors */
2894 txq->descs = dma_alloc_coherent(pp->dev->dev.parent,
2895 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2896 &txq->descs_phys, GFP_KERNEL);
2900 txq->last_desc = txq->size - 1;
2902 txq->tx_skb = kmalloc_array(txq->size, sizeof(*txq->tx_skb),
2905 dma_free_coherent(pp->dev->dev.parent,
2906 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2907 txq->descs, txq->descs_phys);
2911 /* Allocate DMA buffers for TSO MAC/IP/TCP headers */
2912 txq->tso_hdrs = dma_alloc_coherent(pp->dev->dev.parent,
2913 txq->size * TSO_HEADER_SIZE,
2914 &txq->tso_hdrs_phys, GFP_KERNEL);
2915 if (!txq->tso_hdrs) {
2917 dma_free_coherent(pp->dev->dev.parent,
2918 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2919 txq->descs, txq->descs_phys);
2923 /* Setup XPS mapping */
2925 cpu = txq->id % num_present_cpus();
2927 cpu = pp->rxq_def % num_present_cpus();
2928 cpumask_set_cpu(cpu, &txq->affinity_mask);
2929 netif_set_xps_queue(pp->dev, &txq->affinity_mask, txq->id);
2934 static void mvneta_txq_hw_init(struct mvneta_port *pp,
2935 struct mvneta_tx_queue *txq)
2937 /* Set maximum bandwidth for enabled TXQs */
2938 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff);
2939 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff);
2941 /* Set Tx descriptors queue starting address */
2942 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys);
2943 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size);
2945 mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal);
2948 /* Create and initialize a tx queue */
2949 static int mvneta_txq_init(struct mvneta_port *pp,
2950 struct mvneta_tx_queue *txq)
2954 ret = mvneta_txq_sw_init(pp, txq);
2958 mvneta_txq_hw_init(pp, txq);
2963 /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/
2964 static void mvneta_txq_sw_deinit(struct mvneta_port *pp,
2965 struct mvneta_tx_queue *txq)
2967 struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id);
2972 dma_free_coherent(pp->dev->dev.parent,
2973 txq->size * TSO_HEADER_SIZE,
2974 txq->tso_hdrs, txq->tso_hdrs_phys);
2976 dma_free_coherent(pp->dev->dev.parent,
2977 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2978 txq->descs, txq->descs_phys);
2980 netdev_tx_reset_queue(nq);
2984 txq->next_desc_to_proc = 0;
2985 txq->descs_phys = 0;
2988 static void mvneta_txq_hw_deinit(struct mvneta_port *pp,
2989 struct mvneta_tx_queue *txq)
2991 /* Set minimum bandwidth for disabled TXQs */
2992 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0);
2993 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0);
2995 /* Set Tx descriptors queue starting address and size */
2996 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0);
2997 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0);
3000 static void mvneta_txq_deinit(struct mvneta_port *pp,
3001 struct mvneta_tx_queue *txq)
3003 mvneta_txq_sw_deinit(pp, txq);
3004 mvneta_txq_hw_deinit(pp, txq);
3007 /* Cleanup all Tx queues */
3008 static void mvneta_cleanup_txqs(struct mvneta_port *pp)
3012 for (queue = 0; queue < txq_number; queue++)
3013 mvneta_txq_deinit(pp, &pp->txqs[queue]);
3016 /* Cleanup all Rx queues */
3017 static void mvneta_cleanup_rxqs(struct mvneta_port *pp)
3021 for (queue = 0; queue < rxq_number; queue++)
3022 mvneta_rxq_deinit(pp, &pp->rxqs[queue]);
3026 /* Init all Rx queues */
3027 static int mvneta_setup_rxqs(struct mvneta_port *pp)
3031 for (queue = 0; queue < rxq_number; queue++) {
3032 int err = mvneta_rxq_init(pp, &pp->rxqs[queue]);
3035 netdev_err(pp->dev, "%s: can't create rxq=%d\n",
3037 mvneta_cleanup_rxqs(pp);
3045 /* Init all tx queues */
3046 static int mvneta_setup_txqs(struct mvneta_port *pp)
3050 for (queue = 0; queue < txq_number; queue++) {
3051 int err = mvneta_txq_init(pp, &pp->txqs[queue]);
3053 netdev_err(pp->dev, "%s: can't create txq=%d\n",
3055 mvneta_cleanup_txqs(pp);
3063 static void mvneta_start_dev(struct mvneta_port *pp)
3067 mvneta_max_rx_size_set(pp, pp->pkt_size);
3068 mvneta_txq_max_tx_size_set(pp, pp->pkt_size);
3070 /* start the Rx/Tx activity */
3071 mvneta_port_enable(pp);
3073 if (!pp->neta_armada3700) {
3074 /* Enable polling on the port */
3075 for_each_online_cpu(cpu) {
3076 struct mvneta_pcpu_port *port =
3077 per_cpu_ptr(pp->ports, cpu);
3079 napi_enable(&port->napi);
3082 napi_enable(&pp->napi);
3085 /* Unmask interrupts. It has to be done from each CPU */
3086 on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true);
3088 mvreg_write(pp, MVNETA_INTR_MISC_MASK,
3089 MVNETA_CAUSE_PHY_STATUS_CHANGE |
3090 MVNETA_CAUSE_LINK_CHANGE);
3092 phylink_start(pp->phylink);
3093 netif_tx_start_all_queues(pp->dev);
3096 static void mvneta_stop_dev(struct mvneta_port *pp)
3100 phylink_stop(pp->phylink);
3102 if (!pp->neta_armada3700) {
3103 for_each_online_cpu(cpu) {
3104 struct mvneta_pcpu_port *port =
3105 per_cpu_ptr(pp->ports, cpu);
3107 napi_disable(&port->napi);
3110 napi_disable(&pp->napi);
3113 netif_carrier_off(pp->dev);
3115 mvneta_port_down(pp);
3116 netif_tx_stop_all_queues(pp->dev);
3118 /* Stop the port activity */
3119 mvneta_port_disable(pp);
3121 /* Clear all ethernet port interrupts */
3122 on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true);
3124 /* Mask all ethernet port interrupts */
3125 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
3127 mvneta_tx_reset(pp);
3128 mvneta_rx_reset(pp);
3131 static void mvneta_percpu_enable(void *arg)
3133 struct mvneta_port *pp = arg;
3135 enable_percpu_irq(pp->dev->irq, IRQ_TYPE_NONE);
3138 static void mvneta_percpu_disable(void *arg)
3140 struct mvneta_port *pp = arg;
3142 disable_percpu_irq(pp->dev->irq);
3145 /* Change the device mtu */
3146 static int mvneta_change_mtu(struct net_device *dev, int mtu)
3148 struct mvneta_port *pp = netdev_priv(dev);
3151 if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu), 8)) {
3152 netdev_info(dev, "Illegal MTU value %d, rounding to %d\n",
3153 mtu, ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8));
3154 mtu = ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8);
3159 if (!netif_running(dev)) {
3161 mvneta_bm_update_mtu(pp, mtu);
3163 netdev_update_features(dev);
3167 /* The interface is running, so we have to force a
3168 * reallocation of the queues
3170 mvneta_stop_dev(pp);
3171 on_each_cpu(mvneta_percpu_disable, pp, true);
3173 mvneta_cleanup_txqs(pp);
3174 mvneta_cleanup_rxqs(pp);
3177 mvneta_bm_update_mtu(pp, mtu);
3179 pp->pkt_size = MVNETA_RX_PKT_SIZE(dev->mtu);
3180 pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) +
3181 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3183 ret = mvneta_setup_rxqs(pp);
3185 netdev_err(dev, "unable to setup rxqs after MTU change\n");
3189 ret = mvneta_setup_txqs(pp);
3191 netdev_err(dev, "unable to setup txqs after MTU change\n");
3195 on_each_cpu(mvneta_percpu_enable, pp, true);
3196 mvneta_start_dev(pp);
3199 netdev_update_features(dev);
3204 static netdev_features_t mvneta_fix_features(struct net_device *dev,
3205 netdev_features_t features)
3207 struct mvneta_port *pp = netdev_priv(dev);
3209 if (pp->tx_csum_limit && dev->mtu > pp->tx_csum_limit) {
3210 features &= ~(NETIF_F_IP_CSUM | NETIF_F_TSO);
3212 "Disable IP checksum for MTU greater than %dB\n",
3219 /* Get mac address */
3220 static void mvneta_get_mac_addr(struct mvneta_port *pp, unsigned char *addr)
3222 u32 mac_addr_l, mac_addr_h;
3224 mac_addr_l = mvreg_read(pp, MVNETA_MAC_ADDR_LOW);
3225 mac_addr_h = mvreg_read(pp, MVNETA_MAC_ADDR_HIGH);
3226 addr[0] = (mac_addr_h >> 24) & 0xFF;
3227 addr[1] = (mac_addr_h >> 16) & 0xFF;
3228 addr[2] = (mac_addr_h >> 8) & 0xFF;
3229 addr[3] = mac_addr_h & 0xFF;
3230 addr[4] = (mac_addr_l >> 8) & 0xFF;
3231 addr[5] = mac_addr_l & 0xFF;
3234 /* Handle setting mac address */
3235 static int mvneta_set_mac_addr(struct net_device *dev, void *addr)
3237 struct mvneta_port *pp = netdev_priv(dev);
3238 struct sockaddr *sockaddr = addr;
3241 ret = eth_prepare_mac_addr_change(dev, addr);
3244 /* Remove previous address table entry */
3245 mvneta_mac_addr_set(pp, dev->dev_addr, -1);
3247 /* Set new addr in hw */
3248 mvneta_mac_addr_set(pp, sockaddr->sa_data, pp->rxq_def);
3250 eth_commit_mac_addr_change(dev, addr);
3254 static void mvneta_validate(struct net_device *ndev, unsigned long *supported,
3255 struct phylink_link_state *state)
3257 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
3259 /* We only support QSGMII, SGMII, 802.3z and RGMII modes */
3260 if (state->interface != PHY_INTERFACE_MODE_NA &&
3261 state->interface != PHY_INTERFACE_MODE_QSGMII &&
3262 state->interface != PHY_INTERFACE_MODE_SGMII &&
3263 !phy_interface_mode_is_8023z(state->interface) &&
3264 !phy_interface_mode_is_rgmii(state->interface)) {
3265 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
3269 /* Allow all the expected bits */
3270 phylink_set(mask, Autoneg);
3271 phylink_set_port_modes(mask);
3273 /* Asymmetric pause is unsupported */
3274 phylink_set(mask, Pause);
3275 /* Half-duplex at speeds higher than 100Mbit is unsupported */
3276 phylink_set(mask, 1000baseT_Full);
3277 phylink_set(mask, 1000baseX_Full);
3279 if (!phy_interface_mode_is_8023z(state->interface)) {
3280 /* 10M and 100M are only supported in non-802.3z mode */
3281 phylink_set(mask, 10baseT_Half);
3282 phylink_set(mask, 10baseT_Full);
3283 phylink_set(mask, 100baseT_Half);
3284 phylink_set(mask, 100baseT_Full);
3287 bitmap_and(supported, supported, mask,
3288 __ETHTOOL_LINK_MODE_MASK_NBITS);
3289 bitmap_and(state->advertising, state->advertising, mask,
3290 __ETHTOOL_LINK_MODE_MASK_NBITS);
3293 static int mvneta_mac_link_state(struct net_device *ndev,
3294 struct phylink_link_state *state)
3296 struct mvneta_port *pp = netdev_priv(ndev);
3299 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS);
3301 if (gmac_stat & MVNETA_GMAC_SPEED_1000)
3302 state->speed = SPEED_1000;
3303 else if (gmac_stat & MVNETA_GMAC_SPEED_100)
3304 state->speed = SPEED_100;
3306 state->speed = SPEED_10;
3308 state->an_complete = !!(gmac_stat & MVNETA_GMAC_AN_COMPLETE);
3309 state->link = !!(gmac_stat & MVNETA_GMAC_LINK_UP);
3310 state->duplex = !!(gmac_stat & MVNETA_GMAC_FULL_DUPLEX);
3313 if (gmac_stat & MVNETA_GMAC_RX_FLOW_CTRL_ENABLE)
3314 state->pause |= MLO_PAUSE_RX;
3315 if (gmac_stat & MVNETA_GMAC_TX_FLOW_CTRL_ENABLE)
3316 state->pause |= MLO_PAUSE_TX;
3321 static void mvneta_mac_an_restart(struct net_device *ndev)
3323 struct mvneta_port *pp = netdev_priv(ndev);
3324 u32 gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
3326 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
3327 gmac_an | MVNETA_GMAC_INBAND_RESTART_AN);
3328 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
3329 gmac_an & ~MVNETA_GMAC_INBAND_RESTART_AN);
3332 static void mvneta_mac_config(struct net_device *ndev, unsigned int mode,
3333 const struct phylink_link_state *state)
3335 struct mvneta_port *pp = netdev_priv(ndev);
3336 u32 new_ctrl0, gmac_ctrl0 = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
3337 u32 new_ctrl2, gmac_ctrl2 = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
3338 u32 new_clk, gmac_clk = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER);
3339 u32 new_an, gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
3341 new_ctrl0 = gmac_ctrl0 & ~MVNETA_GMAC0_PORT_1000BASE_X;
3342 new_ctrl2 = gmac_ctrl2 & ~(MVNETA_GMAC2_INBAND_AN_ENABLE |
3343 MVNETA_GMAC2_PORT_RESET);
3344 new_clk = gmac_clk & ~MVNETA_GMAC_1MS_CLOCK_ENABLE;
3345 new_an = gmac_an & ~(MVNETA_GMAC_INBAND_AN_ENABLE |
3346 MVNETA_GMAC_INBAND_RESTART_AN |
3347 MVNETA_GMAC_CONFIG_MII_SPEED |
3348 MVNETA_GMAC_CONFIG_GMII_SPEED |
3349 MVNETA_GMAC_AN_SPEED_EN |
3350 MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL |
3351 MVNETA_GMAC_CONFIG_FLOW_CTRL |
3352 MVNETA_GMAC_AN_FLOW_CTRL_EN |
3353 MVNETA_GMAC_CONFIG_FULL_DUPLEX |
3354 MVNETA_GMAC_AN_DUPLEX_EN);
3356 /* Even though it might look weird, when we're configured in
3357 * SGMII or QSGMII mode, the RGMII bit needs to be set.
3359 new_ctrl2 |= MVNETA_GMAC2_PORT_RGMII;
3361 if (state->interface == PHY_INTERFACE_MODE_QSGMII ||
3362 state->interface == PHY_INTERFACE_MODE_SGMII ||
3363 phy_interface_mode_is_8023z(state->interface))
3364 new_ctrl2 |= MVNETA_GMAC2_PCS_ENABLE;
3366 if (phylink_test(state->advertising, Pause))
3367 new_an |= MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL;
3368 if (state->pause & MLO_PAUSE_TXRX_MASK)
3369 new_an |= MVNETA_GMAC_CONFIG_FLOW_CTRL;
3371 if (!phylink_autoneg_inband(mode)) {
3372 /* Phy or fixed speed */
3374 new_an |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
3376 if (state->speed == SPEED_1000)
3377 new_an |= MVNETA_GMAC_CONFIG_GMII_SPEED;
3378 else if (state->speed == SPEED_100)
3379 new_an |= MVNETA_GMAC_CONFIG_MII_SPEED;
3380 } else if (state->interface == PHY_INTERFACE_MODE_SGMII) {
3381 /* SGMII mode receives the state from the PHY */
3382 new_ctrl2 |= MVNETA_GMAC2_INBAND_AN_ENABLE;
3383 new_clk |= MVNETA_GMAC_1MS_CLOCK_ENABLE;
3384 new_an = (new_an & ~(MVNETA_GMAC_FORCE_LINK_DOWN |
3385 MVNETA_GMAC_FORCE_LINK_PASS)) |
3386 MVNETA_GMAC_INBAND_AN_ENABLE |
3387 MVNETA_GMAC_AN_SPEED_EN |
3388 MVNETA_GMAC_AN_DUPLEX_EN;
3390 /* 802.3z negotiation - only 1000base-X */
3391 new_ctrl0 |= MVNETA_GMAC0_PORT_1000BASE_X;
3392 new_clk |= MVNETA_GMAC_1MS_CLOCK_ENABLE;
3393 new_an = (new_an & ~(MVNETA_GMAC_FORCE_LINK_DOWN |
3394 MVNETA_GMAC_FORCE_LINK_PASS)) |
3395 MVNETA_GMAC_INBAND_AN_ENABLE |
3396 MVNETA_GMAC_CONFIG_GMII_SPEED |
3397 /* The MAC only supports FD mode */
3398 MVNETA_GMAC_CONFIG_FULL_DUPLEX;
3400 if (state->pause & MLO_PAUSE_AN && state->an_enabled)
3401 new_an |= MVNETA_GMAC_AN_FLOW_CTRL_EN;
3404 /* Armada 370 documentation says we can only change the port mode
3405 * and in-band enable when the link is down, so force it down
3406 * while making these changes. We also do this for GMAC_CTRL2 */
3407 if ((new_ctrl0 ^ gmac_ctrl0) & MVNETA_GMAC0_PORT_1000BASE_X ||
3408 (new_ctrl2 ^ gmac_ctrl2) & MVNETA_GMAC2_INBAND_AN_ENABLE ||
3409 (new_an ^ gmac_an) & MVNETA_GMAC_INBAND_AN_ENABLE) {
3410 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
3411 (gmac_an & ~MVNETA_GMAC_FORCE_LINK_PASS) |
3412 MVNETA_GMAC_FORCE_LINK_DOWN);
3415 if (new_ctrl0 != gmac_ctrl0)
3416 mvreg_write(pp, MVNETA_GMAC_CTRL_0, new_ctrl0);
3417 if (new_ctrl2 != gmac_ctrl2)
3418 mvreg_write(pp, MVNETA_GMAC_CTRL_2, new_ctrl2);
3419 if (new_clk != gmac_clk)
3420 mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, new_clk);
3421 if (new_an != gmac_an)
3422 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, new_an);
3424 if (gmac_ctrl2 & MVNETA_GMAC2_PORT_RESET) {
3425 while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) &
3426 MVNETA_GMAC2_PORT_RESET) != 0)
3431 static void mvneta_set_eee(struct mvneta_port *pp, bool enable)
3435 lpi_ctl1 = mvreg_read(pp, MVNETA_LPI_CTRL_1);
3437 lpi_ctl1 |= MVNETA_LPI_REQUEST_ENABLE;
3439 lpi_ctl1 &= ~MVNETA_LPI_REQUEST_ENABLE;
3440 mvreg_write(pp, MVNETA_LPI_CTRL_1, lpi_ctl1);
3443 static void mvneta_mac_link_down(struct net_device *ndev, unsigned int mode,
3444 phy_interface_t interface)
3446 struct mvneta_port *pp = netdev_priv(ndev);
3449 mvneta_port_down(pp);
3451 if (!phylink_autoneg_inband(mode)) {
3452 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
3453 val &= ~MVNETA_GMAC_FORCE_LINK_PASS;
3454 val |= MVNETA_GMAC_FORCE_LINK_DOWN;
3455 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
3458 pp->eee_active = false;
3459 mvneta_set_eee(pp, false);
3462 static void mvneta_mac_link_up(struct net_device *ndev, unsigned int mode,
3463 phy_interface_t interface,
3464 struct phy_device *phy)
3466 struct mvneta_port *pp = netdev_priv(ndev);
3469 if (!phylink_autoneg_inband(mode)) {
3470 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
3471 val &= ~MVNETA_GMAC_FORCE_LINK_DOWN;
3472 val |= MVNETA_GMAC_FORCE_LINK_PASS;
3473 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
3478 if (phy && pp->eee_enabled) {
3479 pp->eee_active = phy_init_eee(phy, 0) >= 0;
3480 mvneta_set_eee(pp, pp->eee_active && pp->tx_lpi_enabled);
3484 static const struct phylink_mac_ops mvneta_phylink_ops = {
3485 .validate = mvneta_validate,
3486 .mac_link_state = mvneta_mac_link_state,
3487 .mac_an_restart = mvneta_mac_an_restart,
3488 .mac_config = mvneta_mac_config,
3489 .mac_link_down = mvneta_mac_link_down,
3490 .mac_link_up = mvneta_mac_link_up,
3493 static int mvneta_mdio_probe(struct mvneta_port *pp)
3495 struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL };
3496 int err = phylink_of_phy_connect(pp->phylink, pp->dn, 0);
3499 netdev_err(pp->dev, "could not attach PHY: %d\n", err);
3501 phylink_ethtool_get_wol(pp->phylink, &wol);
3502 device_set_wakeup_capable(&pp->dev->dev, !!wol.supported);
3507 static void mvneta_mdio_remove(struct mvneta_port *pp)
3509 phylink_disconnect_phy(pp->phylink);
3512 /* Electing a CPU must be done in an atomic way: it should be done
3513 * after or before the removal/insertion of a CPU and this function is
3516 static void mvneta_percpu_elect(struct mvneta_port *pp)
3518 int elected_cpu = 0, max_cpu, cpu, i = 0;
3520 /* Use the cpu associated to the rxq when it is online, in all
3521 * the other cases, use the cpu 0 which can't be offline.
3523 if (cpu_online(pp->rxq_def))
3524 elected_cpu = pp->rxq_def;
3526 max_cpu = num_present_cpus();
3528 for_each_online_cpu(cpu) {
3529 int rxq_map = 0, txq_map = 0;
3532 for (rxq = 0; rxq < rxq_number; rxq++)
3533 if ((rxq % max_cpu) == cpu)
3534 rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq);
3536 if (cpu == elected_cpu)
3537 /* Map the default receive queue queue to the
3540 rxq_map |= MVNETA_CPU_RXQ_ACCESS(pp->rxq_def);
3542 /* We update the TX queue map only if we have one
3543 * queue. In this case we associate the TX queue to
3544 * the CPU bound to the default RX queue
3546 if (txq_number == 1)
3547 txq_map = (cpu == elected_cpu) ?
3548 MVNETA_CPU_TXQ_ACCESS(1) : 0;
3550 txq_map = mvreg_read(pp, MVNETA_CPU_MAP(cpu)) &
3551 MVNETA_CPU_TXQ_ACCESS_ALL_MASK;
3553 mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map);
3555 /* Update the interrupt mask on each CPU according the
3558 smp_call_function_single(cpu, mvneta_percpu_unmask_interrupt,
3565 static int mvneta_cpu_online(unsigned int cpu, struct hlist_node *node)
3568 struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port,
3570 struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu);
3573 spin_lock(&pp->lock);
3575 * Configuring the driver for a new CPU while the driver is
3576 * stopping is racy, so just avoid it.
3578 if (pp->is_stopped) {
3579 spin_unlock(&pp->lock);
3582 netif_tx_stop_all_queues(pp->dev);
3585 * We have to synchronise on tha napi of each CPU except the one
3586 * just being woken up
3588 for_each_online_cpu(other_cpu) {
3589 if (other_cpu != cpu) {
3590 struct mvneta_pcpu_port *other_port =
3591 per_cpu_ptr(pp->ports, other_cpu);
3593 napi_synchronize(&other_port->napi);
3597 /* Mask all ethernet port interrupts */
3598 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
3599 napi_enable(&port->napi);
3602 * Enable per-CPU interrupts on the CPU that is
3605 mvneta_percpu_enable(pp);
3608 * Enable per-CPU interrupt on the one CPU we care
3611 mvneta_percpu_elect(pp);
3613 /* Unmask all ethernet port interrupts */
3614 on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true);
3615 mvreg_write(pp, MVNETA_INTR_MISC_MASK,
3616 MVNETA_CAUSE_PHY_STATUS_CHANGE |
3617 MVNETA_CAUSE_LINK_CHANGE);
3618 netif_tx_start_all_queues(pp->dev);
3619 spin_unlock(&pp->lock);
3623 static int mvneta_cpu_down_prepare(unsigned int cpu, struct hlist_node *node)
3625 struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port,
3627 struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu);
3630 * Thanks to this lock we are sure that any pending cpu election is
3633 spin_lock(&pp->lock);
3634 /* Mask all ethernet port interrupts */
3635 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
3636 spin_unlock(&pp->lock);
3638 napi_synchronize(&port->napi);
3639 napi_disable(&port->napi);
3640 /* Disable per-CPU interrupts on the CPU that is brought down. */
3641 mvneta_percpu_disable(pp);
3645 static int mvneta_cpu_dead(unsigned int cpu, struct hlist_node *node)
3647 struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port,
3650 /* Check if a new CPU must be elected now this on is down */
3651 spin_lock(&pp->lock);
3652 mvneta_percpu_elect(pp);
3653 spin_unlock(&pp->lock);
3654 /* Unmask all ethernet port interrupts */
3655 on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true);
3656 mvreg_write(pp, MVNETA_INTR_MISC_MASK,
3657 MVNETA_CAUSE_PHY_STATUS_CHANGE |
3658 MVNETA_CAUSE_LINK_CHANGE);
3659 netif_tx_start_all_queues(pp->dev);
3663 static int mvneta_open(struct net_device *dev)
3665 struct mvneta_port *pp = netdev_priv(dev);
3668 pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu);
3669 pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) +
3670 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3672 ret = mvneta_setup_rxqs(pp);
3676 ret = mvneta_setup_txqs(pp);
3678 goto err_cleanup_rxqs;
3680 /* Connect to port interrupt line */
3681 if (pp->neta_armada3700)
3682 ret = request_irq(pp->dev->irq, mvneta_isr, 0,
3685 ret = request_percpu_irq(pp->dev->irq, mvneta_percpu_isr,
3686 dev->name, pp->ports);
3688 netdev_err(pp->dev, "cannot request irq %d\n", pp->dev->irq);
3689 goto err_cleanup_txqs;
3692 if (!pp->neta_armada3700) {
3693 /* Enable per-CPU interrupt on all the CPU to handle our RX
3696 on_each_cpu(mvneta_percpu_enable, pp, true);
3698 pp->is_stopped = false;
3699 /* Register a CPU notifier to handle the case where our CPU
3700 * might be taken offline.
3702 ret = cpuhp_state_add_instance_nocalls(online_hpstate,
3707 ret = cpuhp_state_add_instance_nocalls(CPUHP_NET_MVNETA_DEAD,
3710 goto err_free_online_hp;
3713 /* In default link is down */
3714 netif_carrier_off(pp->dev);
3716 ret = mvneta_mdio_probe(pp);
3718 netdev_err(dev, "cannot probe MDIO bus\n");
3719 goto err_free_dead_hp;
3722 mvneta_start_dev(pp);
3727 if (!pp->neta_armada3700)
3728 cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD,
3731 if (!pp->neta_armada3700)
3732 cpuhp_state_remove_instance_nocalls(online_hpstate,
3735 if (pp->neta_armada3700) {
3736 free_irq(pp->dev->irq, pp);
3738 on_each_cpu(mvneta_percpu_disable, pp, true);
3739 free_percpu_irq(pp->dev->irq, pp->ports);
3742 mvneta_cleanup_txqs(pp);
3744 mvneta_cleanup_rxqs(pp);
3748 /* Stop the port, free port interrupt line */
3749 static int mvneta_stop(struct net_device *dev)
3751 struct mvneta_port *pp = netdev_priv(dev);
3753 if (!pp->neta_armada3700) {
3754 /* Inform that we are stopping so we don't want to setup the
3755 * driver for new CPUs in the notifiers. The code of the
3756 * notifier for CPU online is protected by the same spinlock,
3757 * so when we get the lock, the notifer work is done.
3759 spin_lock(&pp->lock);
3760 pp->is_stopped = true;
3761 spin_unlock(&pp->lock);
3763 mvneta_stop_dev(pp);
3764 mvneta_mdio_remove(pp);
3766 cpuhp_state_remove_instance_nocalls(online_hpstate,
3768 cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD,
3770 on_each_cpu(mvneta_percpu_disable, pp, true);
3771 free_percpu_irq(dev->irq, pp->ports);
3773 mvneta_stop_dev(pp);
3774 mvneta_mdio_remove(pp);
3775 free_irq(dev->irq, pp);
3778 mvneta_cleanup_rxqs(pp);
3779 mvneta_cleanup_txqs(pp);
3784 static int mvneta_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3786 struct mvneta_port *pp = netdev_priv(dev);
3788 return phylink_mii_ioctl(pp->phylink, ifr, cmd);
3791 /* Ethtool methods */
3793 /* Set link ksettings (phy address, speed) for ethtools */
3795 mvneta_ethtool_set_link_ksettings(struct net_device *ndev,
3796 const struct ethtool_link_ksettings *cmd)
3798 struct mvneta_port *pp = netdev_priv(ndev);
3800 return phylink_ethtool_ksettings_set(pp->phylink, cmd);
3803 /* Get link ksettings for ethtools */
3805 mvneta_ethtool_get_link_ksettings(struct net_device *ndev,
3806 struct ethtool_link_ksettings *cmd)
3808 struct mvneta_port *pp = netdev_priv(ndev);
3810 return phylink_ethtool_ksettings_get(pp->phylink, cmd);
3813 static int mvneta_ethtool_nway_reset(struct net_device *dev)
3815 struct mvneta_port *pp = netdev_priv(dev);
3817 return phylink_ethtool_nway_reset(pp->phylink);
3820 /* Set interrupt coalescing for ethtools */
3821 static int mvneta_ethtool_set_coalesce(struct net_device *dev,
3822 struct ethtool_coalesce *c)
3824 struct mvneta_port *pp = netdev_priv(dev);
3827 for (queue = 0; queue < rxq_number; queue++) {
3828 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
3829 rxq->time_coal = c->rx_coalesce_usecs;
3830 rxq->pkts_coal = c->rx_max_coalesced_frames;
3831 mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal);
3832 mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal);
3835 for (queue = 0; queue < txq_number; queue++) {
3836 struct mvneta_tx_queue *txq = &pp->txqs[queue];
3837 txq->done_pkts_coal = c->tx_max_coalesced_frames;
3838 mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal);
3844 /* get coalescing for ethtools */
3845 static int mvneta_ethtool_get_coalesce(struct net_device *dev,
3846 struct ethtool_coalesce *c)
3848 struct mvneta_port *pp = netdev_priv(dev);
3850 c->rx_coalesce_usecs = pp->rxqs[0].time_coal;
3851 c->rx_max_coalesced_frames = pp->rxqs[0].pkts_coal;
3853 c->tx_max_coalesced_frames = pp->txqs[0].done_pkts_coal;
3858 static void mvneta_ethtool_get_drvinfo(struct net_device *dev,
3859 struct ethtool_drvinfo *drvinfo)
3861 strlcpy(drvinfo->driver, MVNETA_DRIVER_NAME,
3862 sizeof(drvinfo->driver));
3863 strlcpy(drvinfo->version, MVNETA_DRIVER_VERSION,
3864 sizeof(drvinfo->version));
3865 strlcpy(drvinfo->bus_info, dev_name(&dev->dev),
3866 sizeof(drvinfo->bus_info));
3870 static void mvneta_ethtool_get_ringparam(struct net_device *netdev,
3871 struct ethtool_ringparam *ring)
3873 struct mvneta_port *pp = netdev_priv(netdev);
3875 ring->rx_max_pending = MVNETA_MAX_RXD;
3876 ring->tx_max_pending = MVNETA_MAX_TXD;
3877 ring->rx_pending = pp->rx_ring_size;
3878 ring->tx_pending = pp->tx_ring_size;
3881 static int mvneta_ethtool_set_ringparam(struct net_device *dev,
3882 struct ethtool_ringparam *ring)
3884 struct mvneta_port *pp = netdev_priv(dev);
3886 if ((ring->rx_pending == 0) || (ring->tx_pending == 0))
3888 pp->rx_ring_size = ring->rx_pending < MVNETA_MAX_RXD ?
3889 ring->rx_pending : MVNETA_MAX_RXD;
3891 pp->tx_ring_size = clamp_t(u16, ring->tx_pending,
3892 MVNETA_MAX_SKB_DESCS * 2, MVNETA_MAX_TXD);
3893 if (pp->tx_ring_size != ring->tx_pending)
3894 netdev_warn(dev, "TX queue size set to %u (requested %u)\n",
3895 pp->tx_ring_size, ring->tx_pending);
3897 if (netif_running(dev)) {
3899 if (mvneta_open(dev)) {
3901 "error on opening device after ring param change\n");
3909 static void mvneta_ethtool_get_pauseparam(struct net_device *dev,
3910 struct ethtool_pauseparam *pause)
3912 struct mvneta_port *pp = netdev_priv(dev);
3914 phylink_ethtool_get_pauseparam(pp->phylink, pause);
3917 static int mvneta_ethtool_set_pauseparam(struct net_device *dev,
3918 struct ethtool_pauseparam *pause)
3920 struct mvneta_port *pp = netdev_priv(dev);
3922 return phylink_ethtool_set_pauseparam(pp->phylink, pause);
3925 static void mvneta_ethtool_get_strings(struct net_device *netdev, u32 sset,
3928 if (sset == ETH_SS_STATS) {
3931 for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++)
3932 memcpy(data + i * ETH_GSTRING_LEN,
3933 mvneta_statistics[i].name, ETH_GSTRING_LEN);
3937 static void mvneta_ethtool_update_stats(struct mvneta_port *pp)
3939 const struct mvneta_statistic *s;
3940 void __iomem *base = pp->base;
3945 for (i = 0, s = mvneta_statistics;
3946 s < mvneta_statistics + ARRAY_SIZE(mvneta_statistics);
3952 val = readl_relaxed(base + s->offset);
3955 /* Docs say to read low 32-bit then high */
3956 low = readl_relaxed(base + s->offset);
3957 high = readl_relaxed(base + s->offset + 4);
3958 val = (u64)high << 32 | low;
3961 switch (s->offset) {
3962 case ETHTOOL_STAT_EEE_WAKEUP:
3963 val = phylink_get_eee_err(pp->phylink);
3969 pp->ethtool_stats[i] += val;
3973 static void mvneta_ethtool_get_stats(struct net_device *dev,
3974 struct ethtool_stats *stats, u64 *data)
3976 struct mvneta_port *pp = netdev_priv(dev);
3979 mvneta_ethtool_update_stats(pp);
3981 for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++)
3982 *data++ = pp->ethtool_stats[i];
3985 static int mvneta_ethtool_get_sset_count(struct net_device *dev, int sset)
3987 if (sset == ETH_SS_STATS)
3988 return ARRAY_SIZE(mvneta_statistics);
3992 static u32 mvneta_ethtool_get_rxfh_indir_size(struct net_device *dev)
3994 return MVNETA_RSS_LU_TABLE_SIZE;
3997 static int mvneta_ethtool_get_rxnfc(struct net_device *dev,
3998 struct ethtool_rxnfc *info,
3999 u32 *rules __always_unused)
4001 switch (info->cmd) {
4002 case ETHTOOL_GRXRINGS:
4003 info->data = rxq_number;
4012 static int mvneta_config_rss(struct mvneta_port *pp)
4017 netif_tx_stop_all_queues(pp->dev);
4019 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
4021 /* We have to synchronise on the napi of each CPU */
4022 for_each_online_cpu(cpu) {
4023 struct mvneta_pcpu_port *pcpu_port =
4024 per_cpu_ptr(pp->ports, cpu);
4026 napi_synchronize(&pcpu_port->napi);
4027 napi_disable(&pcpu_port->napi);
4030 pp->rxq_def = pp->indir[0];
4032 /* Update unicast mapping */
4033 mvneta_set_rx_mode(pp->dev);
4035 /* Update val of portCfg register accordingly with all RxQueue types */
4036 val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def);
4037 mvreg_write(pp, MVNETA_PORT_CONFIG, val);
4039 /* Update the elected CPU matching the new rxq_def */
4040 spin_lock(&pp->lock);
4041 mvneta_percpu_elect(pp);
4042 spin_unlock(&pp->lock);
4044 /* We have to synchronise on the napi of each CPU */
4045 for_each_online_cpu(cpu) {
4046 struct mvneta_pcpu_port *pcpu_port =
4047 per_cpu_ptr(pp->ports, cpu);
4049 napi_enable(&pcpu_port->napi);
4052 netif_tx_start_all_queues(pp->dev);
4057 static int mvneta_ethtool_set_rxfh(struct net_device *dev, const u32 *indir,
4058 const u8 *key, const u8 hfunc)
4060 struct mvneta_port *pp = netdev_priv(dev);
4062 /* Current code for Armada 3700 doesn't support RSS features yet */
4063 if (pp->neta_armada3700)
4066 /* We require at least one supported parameter to be changed
4067 * and no change in any of the unsupported parameters
4070 (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP))
4076 memcpy(pp->indir, indir, MVNETA_RSS_LU_TABLE_SIZE);
4078 return mvneta_config_rss(pp);
4081 static int mvneta_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
4084 struct mvneta_port *pp = netdev_priv(dev);
4086 /* Current code for Armada 3700 doesn't support RSS features yet */
4087 if (pp->neta_armada3700)
4091 *hfunc = ETH_RSS_HASH_TOP;
4096 memcpy(indir, pp->indir, MVNETA_RSS_LU_TABLE_SIZE);
4101 static void mvneta_ethtool_get_wol(struct net_device *dev,
4102 struct ethtool_wolinfo *wol)
4104 struct mvneta_port *pp = netdev_priv(dev);
4106 phylink_ethtool_get_wol(pp->phylink, wol);
4109 static int mvneta_ethtool_set_wol(struct net_device *dev,
4110 struct ethtool_wolinfo *wol)
4112 struct mvneta_port *pp = netdev_priv(dev);
4115 ret = phylink_ethtool_set_wol(pp->phylink, wol);
4117 device_set_wakeup_enable(&dev->dev, !!wol->wolopts);
4122 static int mvneta_ethtool_get_eee(struct net_device *dev,
4123 struct ethtool_eee *eee)
4125 struct mvneta_port *pp = netdev_priv(dev);
4128 lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0);
4130 eee->eee_enabled = pp->eee_enabled;
4131 eee->eee_active = pp->eee_active;
4132 eee->tx_lpi_enabled = pp->tx_lpi_enabled;
4133 eee->tx_lpi_timer = (lpi_ctl0) >> 8; // * scale;
4135 return phylink_ethtool_get_eee(pp->phylink, eee);
4138 static int mvneta_ethtool_set_eee(struct net_device *dev,
4139 struct ethtool_eee *eee)
4141 struct mvneta_port *pp = netdev_priv(dev);
4144 /* The Armada 37x documents do not give limits for this other than
4145 * it being an 8-bit register. */
4146 if (eee->tx_lpi_enabled &&
4147 (eee->tx_lpi_timer < 0 || eee->tx_lpi_timer > 255))
4150 lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0);
4151 lpi_ctl0 &= ~(0xff << 8);
4152 lpi_ctl0 |= eee->tx_lpi_timer << 8;
4153 mvreg_write(pp, MVNETA_LPI_CTRL_0, lpi_ctl0);
4155 pp->eee_enabled = eee->eee_enabled;
4156 pp->tx_lpi_enabled = eee->tx_lpi_enabled;
4158 mvneta_set_eee(pp, eee->tx_lpi_enabled && eee->eee_enabled);
4160 return phylink_ethtool_set_eee(pp->phylink, eee);
4163 static const struct net_device_ops mvneta_netdev_ops = {
4164 .ndo_open = mvneta_open,
4165 .ndo_stop = mvneta_stop,
4166 .ndo_start_xmit = mvneta_tx,
4167 .ndo_set_rx_mode = mvneta_set_rx_mode,
4168 .ndo_set_mac_address = mvneta_set_mac_addr,
4169 .ndo_change_mtu = mvneta_change_mtu,
4170 .ndo_fix_features = mvneta_fix_features,
4171 .ndo_get_stats64 = mvneta_get_stats64,
4172 .ndo_do_ioctl = mvneta_ioctl,
4175 static const struct ethtool_ops mvneta_eth_tool_ops = {
4176 .nway_reset = mvneta_ethtool_nway_reset,
4177 .get_link = ethtool_op_get_link,
4178 .set_coalesce = mvneta_ethtool_set_coalesce,
4179 .get_coalesce = mvneta_ethtool_get_coalesce,
4180 .get_drvinfo = mvneta_ethtool_get_drvinfo,
4181 .get_ringparam = mvneta_ethtool_get_ringparam,
4182 .set_ringparam = mvneta_ethtool_set_ringparam,
4183 .get_pauseparam = mvneta_ethtool_get_pauseparam,
4184 .set_pauseparam = mvneta_ethtool_set_pauseparam,
4185 .get_strings = mvneta_ethtool_get_strings,
4186 .get_ethtool_stats = mvneta_ethtool_get_stats,
4187 .get_sset_count = mvneta_ethtool_get_sset_count,
4188 .get_rxfh_indir_size = mvneta_ethtool_get_rxfh_indir_size,
4189 .get_rxnfc = mvneta_ethtool_get_rxnfc,
4190 .get_rxfh = mvneta_ethtool_get_rxfh,
4191 .set_rxfh = mvneta_ethtool_set_rxfh,
4192 .get_link_ksettings = mvneta_ethtool_get_link_ksettings,
4193 .set_link_ksettings = mvneta_ethtool_set_link_ksettings,
4194 .get_wol = mvneta_ethtool_get_wol,
4195 .set_wol = mvneta_ethtool_set_wol,
4196 .get_eee = mvneta_ethtool_get_eee,
4197 .set_eee = mvneta_ethtool_set_eee,
4201 static int mvneta_init(struct device *dev, struct mvneta_port *pp)
4206 mvneta_port_disable(pp);
4208 /* Set port default values */
4209 mvneta_defaults_set(pp);
4211 pp->txqs = devm_kcalloc(dev, txq_number, sizeof(*pp->txqs), GFP_KERNEL);
4215 /* Initialize TX descriptor rings */
4216 for (queue = 0; queue < txq_number; queue++) {
4217 struct mvneta_tx_queue *txq = &pp->txqs[queue];
4219 txq->size = pp->tx_ring_size;
4220 txq->done_pkts_coal = MVNETA_TXDONE_COAL_PKTS;
4223 pp->rxqs = devm_kcalloc(dev, rxq_number, sizeof(*pp->rxqs), GFP_KERNEL);
4227 /* Create Rx descriptor rings */
4228 for (queue = 0; queue < rxq_number; queue++) {
4229 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
4231 rxq->size = pp->rx_ring_size;
4232 rxq->pkts_coal = MVNETA_RX_COAL_PKTS;
4233 rxq->time_coal = MVNETA_RX_COAL_USEC;
4235 = devm_kmalloc_array(pp->dev->dev.parent,
4237 sizeof(*rxq->buf_virt_addr),
4239 if (!rxq->buf_virt_addr)
4246 /* platform glue : initialize decoding windows */
4247 static void mvneta_conf_mbus_windows(struct mvneta_port *pp,
4248 const struct mbus_dram_target_info *dram)
4254 for (i = 0; i < 6; i++) {
4255 mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
4256 mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
4259 mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
4266 for (i = 0; i < dram->num_cs; i++) {
4267 const struct mbus_dram_window *cs = dram->cs + i;
4269 mvreg_write(pp, MVNETA_WIN_BASE(i),
4270 (cs->base & 0xffff0000) |
4271 (cs->mbus_attr << 8) |
4272 dram->mbus_dram_target_id);
4274 mvreg_write(pp, MVNETA_WIN_SIZE(i),
4275 (cs->size - 1) & 0xffff0000);
4277 win_enable &= ~(1 << i);
4278 win_protect |= 3 << (2 * i);
4281 /* For Armada3700 open default 4GB Mbus window, leaving
4282 * arbitration of target/attribute to a different layer
4285 mvreg_write(pp, MVNETA_WIN_SIZE(0), 0xffff0000);
4286 win_enable &= ~BIT(0);
4290 mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
4291 mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect);
4294 /* Power up the port */
4295 static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode)
4297 /* MAC Cause register should be cleared */
4298 mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0);
4300 if (phy_mode == PHY_INTERFACE_MODE_QSGMII)
4301 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO);
4302 else if (phy_mode == PHY_INTERFACE_MODE_SGMII ||
4303 phy_mode == PHY_INTERFACE_MODE_1000BASEX)
4304 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO);
4305 else if (!phy_interface_mode_is_rgmii(phy_mode))
4311 /* Device initialization routine */
4312 static int mvneta_probe(struct platform_device *pdev)
4314 struct resource *res;
4315 struct device_node *dn = pdev->dev.of_node;
4316 struct device_node *bm_node;
4317 struct mvneta_port *pp;
4318 struct net_device *dev;
4319 struct phylink *phylink;
4320 const char *dt_mac_addr;
4321 char hw_mac_addr[ETH_ALEN];
4322 const char *mac_from;
4328 dev = alloc_etherdev_mqs(sizeof(struct mvneta_port), txq_number, rxq_number);
4332 dev->irq = irq_of_parse_and_map(dn, 0);
4333 if (dev->irq == 0) {
4335 goto err_free_netdev;
4338 phy_mode = of_get_phy_mode(dn);
4340 dev_err(&pdev->dev, "incorrect phy-mode\n");
4345 phylink = phylink_create(dev, pdev->dev.fwnode, phy_mode,
4346 &mvneta_phylink_ops);
4347 if (IS_ERR(phylink)) {
4348 err = PTR_ERR(phylink);
4352 dev->tx_queue_len = MVNETA_MAX_TXD;
4353 dev->watchdog_timeo = 5 * HZ;
4354 dev->netdev_ops = &mvneta_netdev_ops;
4356 dev->ethtool_ops = &mvneta_eth_tool_ops;
4358 pp = netdev_priv(dev);
4359 spin_lock_init(&pp->lock);
4360 pp->phylink = phylink;
4361 pp->phy_interface = phy_mode;
4364 pp->rxq_def = rxq_def;
4366 /* Set RX packet offset correction for platforms, whose
4367 * NET_SKB_PAD, exceeds 64B. It should be 64B for 64-bit
4368 * platforms and 0B for 32-bit ones.
4370 pp->rx_offset_correction =
4371 max(0, NET_SKB_PAD - MVNETA_RX_PKT_OFFSET_CORRECTION);
4373 pp->indir[0] = rxq_def;
4375 /* Get special SoC configurations */
4376 if (of_device_is_compatible(dn, "marvell,armada-3700-neta"))
4377 pp->neta_armada3700 = true;
4379 pp->clk = devm_clk_get(&pdev->dev, "core");
4380 if (IS_ERR(pp->clk))
4381 pp->clk = devm_clk_get(&pdev->dev, NULL);
4382 if (IS_ERR(pp->clk)) {
4383 err = PTR_ERR(pp->clk);
4384 goto err_free_phylink;
4387 clk_prepare_enable(pp->clk);
4389 pp->clk_bus = devm_clk_get(&pdev->dev, "bus");
4390 if (!IS_ERR(pp->clk_bus))
4391 clk_prepare_enable(pp->clk_bus);
4393 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4394 pp->base = devm_ioremap_resource(&pdev->dev, res);
4395 if (IS_ERR(pp->base)) {
4396 err = PTR_ERR(pp->base);
4400 /* Alloc per-cpu port structure */
4401 pp->ports = alloc_percpu(struct mvneta_pcpu_port);
4407 /* Alloc per-cpu stats */
4408 pp->stats = netdev_alloc_pcpu_stats(struct mvneta_pcpu_stats);
4411 goto err_free_ports;
4414 dt_mac_addr = of_get_mac_address(dn);
4416 mac_from = "device tree";
4417 memcpy(dev->dev_addr, dt_mac_addr, ETH_ALEN);
4419 mvneta_get_mac_addr(pp, hw_mac_addr);
4420 if (is_valid_ether_addr(hw_mac_addr)) {
4421 mac_from = "hardware";
4422 memcpy(dev->dev_addr, hw_mac_addr, ETH_ALEN);
4424 mac_from = "random";
4425 eth_hw_addr_random(dev);
4429 if (!of_property_read_u32(dn, "tx-csum-limit", &tx_csum_limit)) {
4430 if (tx_csum_limit < 0 ||
4431 tx_csum_limit > MVNETA_TX_CSUM_MAX_SIZE) {
4432 tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE;
4433 dev_info(&pdev->dev,
4434 "Wrong TX csum limit in DT, set to %dB\n",
4435 MVNETA_TX_CSUM_DEF_SIZE);
4437 } else if (of_device_is_compatible(dn, "marvell,armada-370-neta")) {
4438 tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE;
4440 tx_csum_limit = MVNETA_TX_CSUM_MAX_SIZE;
4443 pp->tx_csum_limit = tx_csum_limit;
4445 pp->dram_target_info = mv_mbus_dram_info();
4446 /* Armada3700 requires setting default configuration of Mbus
4447 * windows, however without using filled mbus_dram_target_info
4450 if (pp->dram_target_info || pp->neta_armada3700)
4451 mvneta_conf_mbus_windows(pp, pp->dram_target_info);
4453 pp->tx_ring_size = MVNETA_MAX_TXD;
4454 pp->rx_ring_size = MVNETA_MAX_RXD;
4457 SET_NETDEV_DEV(dev, &pdev->dev);
4459 pp->id = global_port_id++;
4461 /* Obtain access to BM resources if enabled and already initialized */
4462 bm_node = of_parse_phandle(dn, "buffer-manager", 0);
4463 if (bm_node && bm_node->data) {
4464 pp->bm_priv = bm_node->data;
4465 err = mvneta_bm_port_init(pdev, pp);
4467 dev_info(&pdev->dev, "use SW buffer management\n");
4471 of_node_put(bm_node);
4473 err = mvneta_init(&pdev->dev, pp);
4477 err = mvneta_port_power_up(pp, phy_mode);
4479 dev_err(&pdev->dev, "can't power up port\n");
4483 /* Armada3700 network controller does not support per-cpu
4484 * operation, so only single NAPI should be initialized.
4486 if (pp->neta_armada3700) {
4487 netif_napi_add(dev, &pp->napi, mvneta_poll, NAPI_POLL_WEIGHT);
4489 for_each_present_cpu(cpu) {
4490 struct mvneta_pcpu_port *port =
4491 per_cpu_ptr(pp->ports, cpu);
4493 netif_napi_add(dev, &port->napi, mvneta_poll,
4499 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_TSO;
4500 dev->hw_features |= dev->features;
4501 dev->vlan_features |= dev->features;
4502 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
4503 dev->gso_max_segs = MVNETA_MAX_TSO_SEGS;
4505 /* MTU range: 68 - 9676 */
4506 dev->min_mtu = ETH_MIN_MTU;
4507 /* 9676 == 9700 - 20 and rounding to 8 */
4508 dev->max_mtu = 9676;
4510 err = register_netdev(dev);
4512 dev_err(&pdev->dev, "failed to register\n");
4513 goto err_free_stats;
4516 netdev_info(dev, "Using %s mac address %pM\n", mac_from,
4519 platform_set_drvdata(pdev, pp->dev);
4524 unregister_netdev(dev);
4526 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id);
4527 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short,
4531 free_percpu(pp->stats);
4533 free_percpu(pp->ports);
4535 clk_disable_unprepare(pp->clk_bus);
4536 clk_disable_unprepare(pp->clk);
4539 phylink_destroy(pp->phylink);
4541 irq_dispose_mapping(dev->irq);
4547 /* Device removal routine */
4548 static int mvneta_remove(struct platform_device *pdev)
4550 struct net_device *dev = platform_get_drvdata(pdev);
4551 struct mvneta_port *pp = netdev_priv(dev);
4553 unregister_netdev(dev);
4554 clk_disable_unprepare(pp->clk_bus);
4555 clk_disable_unprepare(pp->clk);
4556 free_percpu(pp->ports);
4557 free_percpu(pp->stats);
4558 irq_dispose_mapping(dev->irq);
4559 phylink_destroy(pp->phylink);
4563 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id);
4564 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short,
4571 #ifdef CONFIG_PM_SLEEP
4572 static int mvneta_suspend(struct device *device)
4575 struct net_device *dev = dev_get_drvdata(device);
4576 struct mvneta_port *pp = netdev_priv(dev);
4578 if (!netif_running(dev))
4581 if (!pp->neta_armada3700) {
4582 spin_lock(&pp->lock);
4583 pp->is_stopped = true;
4584 spin_unlock(&pp->lock);
4586 cpuhp_state_remove_instance_nocalls(online_hpstate,
4588 cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD,
4593 mvneta_stop_dev(pp);
4596 for (queue = 0; queue < rxq_number; queue++) {
4597 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
4599 mvneta_rxq_drop_pkts(pp, rxq);
4602 for (queue = 0; queue < txq_number; queue++) {
4603 struct mvneta_tx_queue *txq = &pp->txqs[queue];
4605 mvneta_txq_hw_deinit(pp, txq);
4609 netif_device_detach(dev);
4610 clk_disable_unprepare(pp->clk_bus);
4611 clk_disable_unprepare(pp->clk);
4616 static int mvneta_resume(struct device *device)
4618 struct platform_device *pdev = to_platform_device(device);
4619 struct net_device *dev = dev_get_drvdata(device);
4620 struct mvneta_port *pp = netdev_priv(dev);
4623 clk_prepare_enable(pp->clk);
4624 if (!IS_ERR(pp->clk_bus))
4625 clk_prepare_enable(pp->clk_bus);
4626 if (pp->dram_target_info || pp->neta_armada3700)
4627 mvneta_conf_mbus_windows(pp, pp->dram_target_info);
4629 err = mvneta_bm_port_init(pdev, pp);
4631 dev_info(&pdev->dev, "use SW buffer management\n");
4635 mvneta_defaults_set(pp);
4636 err = mvneta_port_power_up(pp, pp->phy_interface);
4638 dev_err(device, "can't power up port\n");
4642 netif_device_attach(dev);
4644 if (!netif_running(dev))
4647 for (queue = 0; queue < rxq_number; queue++) {
4648 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
4650 rxq->next_desc_to_proc = 0;
4651 mvneta_rxq_hw_init(pp, rxq);
4654 for (queue = 0; queue < txq_number; queue++) {
4655 struct mvneta_tx_queue *txq = &pp->txqs[queue];
4657 txq->next_desc_to_proc = 0;
4658 mvneta_txq_hw_init(pp, txq);
4661 if (!pp->neta_armada3700) {
4662 spin_lock(&pp->lock);
4663 pp->is_stopped = false;
4664 spin_unlock(&pp->lock);
4665 cpuhp_state_add_instance_nocalls(online_hpstate,
4667 cpuhp_state_add_instance_nocalls(CPUHP_NET_MVNETA_DEAD,
4672 mvneta_start_dev(pp);
4674 mvneta_set_rx_mode(dev);
4680 static SIMPLE_DEV_PM_OPS(mvneta_pm_ops, mvneta_suspend, mvneta_resume);
4682 static const struct of_device_id mvneta_match[] = {
4683 { .compatible = "marvell,armada-370-neta" },
4684 { .compatible = "marvell,armada-xp-neta" },
4685 { .compatible = "marvell,armada-3700-neta" },
4688 MODULE_DEVICE_TABLE(of, mvneta_match);
4690 static struct platform_driver mvneta_driver = {
4691 .probe = mvneta_probe,
4692 .remove = mvneta_remove,
4694 .name = MVNETA_DRIVER_NAME,
4695 .of_match_table = mvneta_match,
4696 .pm = &mvneta_pm_ops,
4700 static int __init mvneta_driver_init(void)
4704 ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, "net/mvmeta:online",
4706 mvneta_cpu_down_prepare);
4709 online_hpstate = ret;
4710 ret = cpuhp_setup_state_multi(CPUHP_NET_MVNETA_DEAD, "net/mvneta:dead",
4711 NULL, mvneta_cpu_dead);
4715 ret = platform_driver_register(&mvneta_driver);
4721 cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD);
4723 cpuhp_remove_multi_state(online_hpstate);
4727 module_init(mvneta_driver_init);
4729 static void __exit mvneta_driver_exit(void)
4731 platform_driver_unregister(&mvneta_driver);
4732 cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD);
4733 cpuhp_remove_multi_state(online_hpstate);
4735 module_exit(mvneta_driver_exit);
4737 MODULE_DESCRIPTION("Marvell NETA Ethernet Driver - www.marvell.com");
4738 MODULE_AUTHOR("Rami Rosen <rosenr@marvell.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
4739 MODULE_LICENSE("GPL");
4741 module_param(rxq_number, int, 0444);
4742 module_param(txq_number, int, 0444);
4744 module_param(rxq_def, int, 0444);
4745 module_param(rx_copybreak, int, 0644);