drivers/net/ethernet/jme.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
   4  *
   5  * Copyright 2008 JMicron Technology Corporation
   6  * https://www.jmicron.com/
   7  * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
   8  *
   9  * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
  10  */
  11
  12 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  13
  14 #include <linux/module.h>
  15 #include <linux/kernel.h>
  16 #include <linux/pci.h>
  17 #include <linux/netdevice.h>
  18 #include <linux/etherdevice.h>
  19 #include <linux/ethtool.h>
  20 #include <linux/mii.h>
  21 #include <linux/crc32.h>
  22 #include <linux/delay.h>
  23 #include <linux/spinlock.h>
  24 #include <linux/in.h>
  25 #include <linux/ip.h>
  26 #include <linux/ipv6.h>
  27 #include <linux/tcp.h>
  28 #include <linux/udp.h>
  29 #include <linux/if_vlan.h>
  30 #include <linux/slab.h>
  31 #include <net/ip6_checksum.h>
  32 #include "jme.h"
  33
  34 static int force_pseudohp = -1;
  35 static int no_pseudohp = -1;
  36 static int no_extplug = -1;
  37 module_param(force_pseudohp, int, 0);
  38 MODULE_PARM_DESC(force_pseudohp,
  39         "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
  40 module_param(no_pseudohp, int, 0);
  41 MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
  42 module_param(no_extplug, int, 0);
  43 MODULE_PARM_DESC(no_extplug,
  44         "Do not use external plug signal for pseudo hot-plug.");
  45
  46 static int
  47 jme_mdio_read(struct net_device *netdev, int phy, int reg)
  48 {
  49         struct jme_adapter *jme = netdev_priv(netdev);
  50         int i, val, again = (reg == MII_BMSR) ? 1 : 0;
  51
  52 read_again:
  53         jwrite32(jme, JME_SMI, SMI_OP_REQ |
  54                                 smi_phy_addr(phy) |
  55                                 smi_reg_addr(reg));
  56
  57         wmb();
  58         for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
  59                 udelay(20);
  60                 val = jread32(jme, JME_SMI);
  61                 if ((val & SMI_OP_REQ) == 0)
  62                         break;
  63         }
  64
  65         if (i == 0) {
  66                 pr_err("phy(%d) read timeout : %d\n", phy, reg);
  67                 return 0;
  68         }
  69
  70         if (again--)
  71                 goto read_again;
  72
  73         return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
  74 }
  75
  76 static void
  77 jme_mdio_write(struct net_device *netdev,
  78                                 int phy, int reg, int val)
  79 {
  80         struct jme_adapter *jme = netdev_priv(netdev);
  81         int i;
  82
  83         jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
  84                 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
  85                 smi_phy_addr(phy) | smi_reg_addr(reg));
  86
  87         wmb();
  88         for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
  89                 udelay(20);
  90                 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
  91                         break;
  92         }
  93
  94         if (i == 0)
  95                 pr_err("phy(%d) write timeout : %d\n", phy, reg);
  96 }
  97
  98 static inline void
  99 jme_reset_phy_processor(struct jme_adapter *jme)
 100 {
 101         u32 val;
 102
 103         jme_mdio_write(jme->dev,
 104                         jme->mii_if.phy_id,
 105                         MII_ADVERTISE, ADVERTISE_ALL |
 106                         ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
 107
 108         if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
 109                 jme_mdio_write(jme->dev,
 110                                 jme->mii_if.phy_id,
 111                                 MII_CTRL1000,
 112                                 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
 113
 114         val = jme_mdio_read(jme->dev,
 115                                 jme->mii_if.phy_id,
 116                                 MII_BMCR);
 117
 118         jme_mdio_write(jme->dev,
 119                         jme->mii_if.phy_id,
 120                         MII_BMCR, val | BMCR_RESET);
 121 }
 122
 123 static void
 124 jme_setup_wakeup_frame(struct jme_adapter *jme,
 125                        const u32 *mask, u32 crc, int fnr)
 126 {
 127         int i;
 128
 129         /*
 130          * Setup CRC pattern
 131          */
 132         jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
 133         wmb();
 134         jwrite32(jme, JME_WFODP, crc);
 135         wmb();
 136
 137         /*
 138          * Setup Mask
 139          */
 140         for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
 141                 jwrite32(jme, JME_WFOI,
 142                                 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
 143                                 (fnr & WFOI_FRAME_SEL));
 144                 wmb();
 145                 jwrite32(jme, JME_WFODP, mask[i]);
 146                 wmb();
 147         }
 148 }
 149
 150 static inline void
 151 jme_mac_rxclk_off(struct jme_adapter *jme)
 152 {
 153         jme->reg_gpreg1 |= GPREG1_RXCLKOFF;
 154         jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
 155 }
 156
 157 static inline void
 158 jme_mac_rxclk_on(struct jme_adapter *jme)
 159 {
 160         jme->reg_gpreg1 &= ~GPREG1_RXCLKOFF;
 161         jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
 162 }
 163
 164 static inline void
 165 jme_mac_txclk_off(struct jme_adapter *jme)
 166 {
 167         jme->reg_ghc &= ~(GHC_TO_CLK_SRC | GHC_TXMAC_CLK_SRC);
 168         jwrite32f(jme, JME_GHC, jme->reg_ghc);
 169 }
 170
 171 static inline void
 172 jme_mac_txclk_on(struct jme_adapter *jme)
 173 {
 174         u32 speed = jme->reg_ghc & GHC_SPEED;
 175         if (speed == GHC_SPEED_1000M)
 176                 jme->reg_ghc |= GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
 177         else
 178                 jme->reg_ghc |= GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
 179         jwrite32f(jme, JME_GHC, jme->reg_ghc);
 180 }
 181
 182 static inline void
 183 jme_reset_ghc_speed(struct jme_adapter *jme)
 184 {
 185         jme->reg_ghc &= ~(GHC_SPEED | GHC_DPX);
 186         jwrite32f(jme, JME_GHC, jme->reg_ghc);
 187 }
 188
 189 static inline void
 190 jme_reset_250A2_workaround(struct jme_adapter *jme)
 191 {
 192         jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
 193                              GPREG1_RSSPATCH);
 194         jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
 195 }
 196
 197 static inline void
 198 jme_assert_ghc_reset(struct jme_adapter *jme)
 199 {
 200         jme->reg_ghc |= GHC_SWRST;
 201         jwrite32f(jme, JME_GHC, jme->reg_ghc);
 202 }
 203
 204 static inline void
 205 jme_clear_ghc_reset(struct jme_adapter *jme)
 206 {
 207         jme->reg_ghc &= ~GHC_SWRST;
 208         jwrite32f(jme, JME_GHC, jme->reg_ghc);
 209 }
 210
 211 static void
 212 jme_reset_mac_processor(struct jme_adapter *jme)
 213 {
 214         static const u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
 215         u32 crc = 0xCDCDCDCD;
 216         u32 gpreg0;
 217         int i;
 218
 219         jme_reset_ghc_speed(jme);
 220         jme_reset_250A2_workaround(jme);
 221
 222         jme_mac_rxclk_on(jme);
 223         jme_mac_txclk_on(jme);
 224         udelay(1);
 225         jme_assert_ghc_reset(jme);
 226         udelay(1);
 227         jme_mac_rxclk_off(jme);
 228         jme_mac_txclk_off(jme);
 229         udelay(1);
 230         jme_clear_ghc_reset(jme);
 231         udelay(1);
 232         jme_mac_rxclk_on(jme);
 233         jme_mac_txclk_on(jme);
 234         udelay(1);
 235         jme_mac_rxclk_off(jme);
 236         jme_mac_txclk_off(jme);
 237
 238         jwrite32(jme, JME_RXDBA_LO, 0x00000000);
 239         jwrite32(jme, JME_RXDBA_HI, 0x00000000);
 240         jwrite32(jme, JME_RXQDC, 0x00000000);
 241         jwrite32(jme, JME_RXNDA, 0x00000000);
 242         jwrite32(jme, JME_TXDBA_LO, 0x00000000);
 243         jwrite32(jme, JME_TXDBA_HI, 0x00000000);
 244         jwrite32(jme, JME_TXQDC, 0x00000000);
 245         jwrite32(jme, JME_TXNDA, 0x00000000);
 246
 247         jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
 248         jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
 249         for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
 250                 jme_setup_wakeup_frame(jme, mask, crc, i);
 251         if (jme->fpgaver)
 252                 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
 253         else
 254                 gpreg0 = GPREG0_DEFAULT;
 255         jwrite32(jme, JME_GPREG0, gpreg0);
 256 }
 257
 258 static inline void
 259 jme_clear_pm_enable_wol(struct jme_adapter *jme)
 260 {
 261         jwrite32(jme, JME_PMCS, PMCS_STMASK | jme->reg_pmcs);
 262 }
 263
 264 static inline void
 265 jme_clear_pm_disable_wol(struct jme_adapter *jme)
 266 {
 267         jwrite32(jme, JME_PMCS, PMCS_STMASK);
 268 }
 269
 270 static int
 271 jme_reload_eeprom(struct jme_adapter *jme)
 272 {
 273         u32 val;
 274         int i;
 275
 276         val = jread32(jme, JME_SMBCSR);
 277
 278         if (val & SMBCSR_EEPROMD) {
 279                 val |= SMBCSR_CNACK;
 280                 jwrite32(jme, JME_SMBCSR, val);
 281                 val |= SMBCSR_RELOAD;
 282                 jwrite32(jme, JME_SMBCSR, val);
 283                 mdelay(12);
 284
 285                 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
 286                         mdelay(1);
 287                         if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
 288                                 break;
 289                 }
 290
 291                 if (i == 0) {
 292                         pr_err("eeprom reload timeout\n");
 293                         return -EIO;
 294                 }
 295         }
 296
 297         return 0;
 298 }
 299
 300 static void
 301 jme_load_macaddr(struct net_device *netdev)
 302 {
 303         struct jme_adapter *jme = netdev_priv(netdev);
 304         unsigned char macaddr[ETH_ALEN];
 305         u32 val;
 306
 307         spin_lock_bh(&jme->macaddr_lock);
 308         val = jread32(jme, JME_RXUMA_LO);
 309         macaddr[0] = (val >>  0) & 0xFF;
 310         macaddr[1] = (val >>  8) & 0xFF;
 311         macaddr[2] = (val >> 16) & 0xFF;
 312         macaddr[3] = (val >> 24) & 0xFF;
 313         val = jread32(jme, JME_RXUMA_HI);
 314         macaddr[4] = (val >>  0) & 0xFF;
 315         macaddr[5] = (val >>  8) & 0xFF;
 316         memcpy(netdev->dev_addr, macaddr, ETH_ALEN);
 317         spin_unlock_bh(&jme->macaddr_lock);
 318 }
 319
 320 static inline void
 321 jme_set_rx_pcc(struct jme_adapter *jme, int p)
 322 {
 323         switch (p) {
 324         case PCC_OFF:
 325                 jwrite32(jme, JME_PCCRX0,
 326                         ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
 327                         ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
 328                 break;
 329         case PCC_P1:
 330                 jwrite32(jme, JME_PCCRX0,
 331                         ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
 332                         ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
 333                 break;
 334         case PCC_P2:
 335                 jwrite32(jme, JME_PCCRX0,
 336                         ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
 337                         ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
 338                 break;
 339         case PCC_P3:
 340                 jwrite32(jme, JME_PCCRX0,
 341                         ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
 342                         ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
 343                 break;
 344         default:
 345                 break;
 346         }
 347         wmb();
 348
 349         if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
 350                 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
 351 }
 352
 353 static void
 354 jme_start_irq(struct jme_adapter *jme)
 355 {
 356         register struct dynpcc_info *dpi = &(jme->dpi);
 357
 358         jme_set_rx_pcc(jme, PCC_P1);
 359         dpi->cur                = PCC_P1;
 360         dpi->attempt            = PCC_P1;
 361         dpi->cnt                = 0;
 362
 363         jwrite32(jme, JME_PCCTX,
 364                         ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
 365                         ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
 366                         PCCTXQ0_EN
 367                 );
 368
 369         /*
 370          * Enable Interrupts
 371          */
 372         jwrite32(jme, JME_IENS, INTR_ENABLE);
 373 }
 374
 375 static inline void
 376 jme_stop_irq(struct jme_adapter *jme)
 377 {
 378         /*
 379          * Disable Interrupts
 380          */
 381         jwrite32f(jme, JME_IENC, INTR_ENABLE);
 382 }
 383
 384 static u32
 385 jme_linkstat_from_phy(struct jme_adapter *jme)
 386 {
 387         u32 phylink, bmsr;
 388
 389         phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
 390         bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
 391         if (bmsr & BMSR_ANCOMP)
 392                 phylink |= PHY_LINK_AUTONEG_COMPLETE;
 393
 394         return phylink;
 395 }
 396
 397 static inline void
 398 jme_set_phyfifo_5level(struct jme_adapter *jme)
 399 {
 400         jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
 401 }
 402
 403 static inline void
 404 jme_set_phyfifo_8level(struct jme_adapter *jme)
 405 {
 406         jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
 407 }
 408
 409 static int
 410 jme_check_link(struct net_device *netdev, int testonly)
 411 {
 412         struct jme_adapter *jme = netdev_priv(netdev);
 413         u32 phylink, cnt = JME_SPDRSV_TIMEOUT, bmcr;
 414         char linkmsg[64];
 415         int rc = 0;
 416
 417         linkmsg[0] = '\0';
 418
 419         if (jme->fpgaver)
 420                 phylink = jme_linkstat_from_phy(jme);
 421         else
 422                 phylink = jread32(jme, JME_PHY_LINK);
 423
 424         if (phylink & PHY_LINK_UP) {
 425                 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
 426                         /*
 427                          * If we did not enable AN
 428                          * Speed/Duplex Info should be obtained from SMI
 429                          */
 430                         phylink = PHY_LINK_UP;
 431
 432                         bmcr = jme_mdio_read(jme->dev,
 433                                                 jme->mii_if.phy_id,
 434                                                 MII_BMCR);
 435
 436                         phylink |= ((bmcr & BMCR_SPEED1000) &&
 437                                         (bmcr & BMCR_SPEED100) == 0) ?
 438                                         PHY_LINK_SPEED_1000M :
 439                                         (bmcr & BMCR_SPEED100) ?
 440                                         PHY_LINK_SPEED_100M :
 441                                         PHY_LINK_SPEED_10M;
 442
 443                         phylink |= (bmcr & BMCR_FULLDPLX) ?
 444                                          PHY_LINK_DUPLEX : 0;
 445
 446                         strcat(linkmsg, "Forced: ");
 447                 } else {
 448                         /*
 449                          * Keep polling for speed/duplex resolve complete
 450                          */
 451                         while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
 452                                 --cnt) {
 453
 454                                 udelay(1);
 455
 456                                 if (jme->fpgaver)
 457                                         phylink = jme_linkstat_from_phy(jme);
 458                                 else
 459                                         phylink = jread32(jme, JME_PHY_LINK);
 460                         }
 461                         if (!cnt)
 462                                 pr_err("Waiting speed resolve timeout\n");
 463
 464                         strcat(linkmsg, "ANed: ");
 465                 }
 466
 467                 if (jme->phylink == phylink) {
 468                         rc = 1;
 469                         goto out;
 470                 }
 471                 if (testonly)
 472                         goto out;
 473
 474                 jme->phylink = phylink;
 475
 476                 /*
 477                  * The speed/duplex setting of jme->reg_ghc already cleared
 478                  * by jme_reset_mac_processor()
 479                  */
 480                 switch (phylink & PHY_LINK_SPEED_MASK) {
 481                 case PHY_LINK_SPEED_10M:
 482                         jme->reg_ghc |= GHC_SPEED_10M;
 483                         strcat(linkmsg, "10 Mbps, ");
 484                         break;
 485                 case PHY_LINK_SPEED_100M:
 486                         jme->reg_ghc |= GHC_SPEED_100M;
 487                         strcat(linkmsg, "100 Mbps, ");
 488                         break;
 489                 case PHY_LINK_SPEED_1000M:
 490                         jme->reg_ghc |= GHC_SPEED_1000M;
 491                         strcat(linkmsg, "1000 Mbps, ");
 492                         break;
 493                 default:
 494                         break;
 495                 }
 496
 497                 if (phylink & PHY_LINK_DUPLEX) {
 498                         jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
 499                         jwrite32(jme, JME_TXTRHD, TXTRHD_FULLDUPLEX);
 500                         jme->reg_ghc |= GHC_DPX;
 501                 } else {
 502                         jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
 503                                                 TXMCS_BACKOFF |
 504                                                 TXMCS_CARRIERSENSE |
 505                                                 TXMCS_COLLISION);
 506                         jwrite32(jme, JME_TXTRHD, TXTRHD_HALFDUPLEX);
 507                 }
 508
 509                 jwrite32(jme, JME_GHC, jme->reg_ghc);
 510
 511                 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
 512                         jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
 513                                              GPREG1_RSSPATCH);
 514                         if (!(phylink & PHY_LINK_DUPLEX))
 515                                 jme->reg_gpreg1 |= GPREG1_HALFMODEPATCH;
 516                         switch (phylink & PHY_LINK_SPEED_MASK) {
 517                         case PHY_LINK_SPEED_10M:
 518                                 jme_set_phyfifo_8level(jme);
 519                                 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
 520                                 break;
 521                         case PHY_LINK_SPEED_100M:
 522                                 jme_set_phyfifo_5level(jme);
 523                                 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
 524                                 break;
 525                         case PHY_LINK_SPEED_1000M:
 526                                 jme_set_phyfifo_8level(jme);
 527                                 break;
 528                         default:
 529                                 break;
 530                         }
 531                 }
 532                 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
 533
 534                 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
 535                                         "Full-Duplex, " :
 536                                         "Half-Duplex, ");
 537                 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
 538                                         "MDI-X" :
 539                                         "MDI");
 540                 netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg);
 541                 netif_carrier_on(netdev);
 542         } else {
 543                 if (testonly)
 544                         goto out;
 545
 546                 netif_info(jme, link, jme->dev, "Link is down\n");
 547                 jme->phylink = 0;
 548                 netif_carrier_off(netdev);
 549         }
 550
 551 out:
 552         return rc;
 553 }
 554
 555 static int
 556 jme_setup_tx_resources(struct jme_adapter *jme)
 557 {
 558         struct jme_ring *txring = &(jme->txring[0]);
 559
 560         txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
 561                                    TX_RING_ALLOC_SIZE(jme->tx_ring_size),
 562                                    &(txring->dmaalloc),
 563                                    GFP_ATOMIC);
 564
 565         if (!txring->alloc)
 566                 goto err_set_null;
 567
 568         /*
 569          * 16 Bytes align
 570          */
 571         txring->desc            = (void *)ALIGN((unsigned long)(txring->alloc),
 572                                                 RING_DESC_ALIGN);
 573         txring->dma             = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
 574         txring->next_to_use     = 0;
 575         atomic_set(&txring->next_to_clean, 0);
 576         atomic_set(&txring->nr_free, jme->tx_ring_size);
 577
 578         txring->bufinf          = kcalloc(jme->tx_ring_size,
 579                                                 sizeof(struct jme_buffer_info),
 580                                                 GFP_ATOMIC);
 581         if (unlikely(!(txring->bufinf)))
 582                 goto err_free_txring;
 583
 584         return 0;
 585
 586 err_free_txring:
 587         dma_free_coherent(&(jme->pdev->dev),
 588                           TX_RING_ALLOC_SIZE(jme->tx_ring_size),
 589                           txring->alloc,
 590                           txring->dmaalloc);
 591
 592 err_set_null:
 593         txring->desc = NULL;
 594         txring->dmaalloc = 0;
 595         txring->dma = 0;
 596         txring->bufinf = NULL;
 597
 598         return -ENOMEM;
 599 }
 600
 601 static void
 602 jme_free_tx_resources(struct jme_adapter *jme)
 603 {
 604         int i;
 605         struct jme_ring *txring = &(jme->txring[0]);
 606         struct jme_buffer_info *txbi;
 607
 608         if (txring->alloc) {
 609                 if (txring->bufinf) {
 610                         for (i = 0 ; i < jme->tx_ring_size ; ++i) {
 611                                 txbi = txring->bufinf + i;
 612                                 if (txbi->skb) {
 613                                         dev_kfree_skb(txbi->skb);
 614                                         txbi->skb = NULL;
 615                                 }
 616                                 txbi->mapping           = 0;
 617                                 txbi->len               = 0;
 618                                 txbi->nr_desc           = 0;
 619                                 txbi->start_xmit        = 0;
 620                         }
 621                         kfree(txring->bufinf);
 622                 }
 623
 624                 dma_free_coherent(&(jme->pdev->dev),
 625                                   TX_RING_ALLOC_SIZE(jme->tx_ring_size),
 626                                   txring->alloc,
 627                                   txring->dmaalloc);
 628
 629                 txring->alloc           = NULL;
 630                 txring->desc            = NULL;
 631                 txring->dmaalloc        = 0;
 632                 txring->dma             = 0;
 633                 txring->bufinf          = NULL;
 634         }
 635         txring->next_to_use     = 0;
 636         atomic_set(&txring->next_to_clean, 0);
 637         atomic_set(&txring->nr_free, 0);
 638 }
 639
 640 static inline void
 641 jme_enable_tx_engine(struct jme_adapter *jme)
 642 {
 643         /*
 644          * Select Queue 0
 645          */
 646         jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
 647         wmb();
 648
 649         /*
 650          * Setup TX Queue 0 DMA Bass Address
 651          */
 652         jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
 653         jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
 654         jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
 655
 656         /*
 657          * Setup TX Descptor Count
 658          */
 659         jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
 660
 661         /*
 662          * Enable TX Engine
 663          */
 664         wmb();
 665         jwrite32f(jme, JME_TXCS, jme->reg_txcs |
 666                                 TXCS_SELECT_QUEUE0 |
 667                                 TXCS_ENABLE);
 668
 669         /*
 670          * Start clock for TX MAC Processor
 671          */
 672         jme_mac_txclk_on(jme);
 673 }
 674
 675 static inline void
 676 jme_disable_tx_engine(struct jme_adapter *jme)
 677 {
 678         int i;
 679         u32 val;
 680
 681         /*
 682          * Disable TX Engine
 683          */
 684         jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
 685         wmb();
 686
 687         val = jread32(jme, JME_TXCS);
 688         for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
 689                 mdelay(1);
 690                 val = jread32(jme, JME_TXCS);
 691                 rmb();
 692         }
 693
 694         if (!i)
 695                 pr_err("Disable TX engine timeout\n");
 696
 697         /*
 698          * Stop clock for TX MAC Processor
 699          */
 700         jme_mac_txclk_off(jme);
 701 }
 702
 703 static void
 704 jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
 705 {
 706         struct jme_ring *rxring = &(jme->rxring[0]);
 707         register struct rxdesc *rxdesc = rxring->desc;
 708         struct jme_buffer_info *rxbi = rxring->bufinf;
 709         rxdesc += i;
 710         rxbi += i;
 711
 712         rxdesc->dw[0] = 0;
 713         rxdesc->dw[1] = 0;
 714         rxdesc->desc1.bufaddrh  = cpu_to_le32((__u64)rxbi->mapping >> 32);
 715         rxdesc->desc1.bufaddrl  = cpu_to_le32(
 716                                         (__u64)rxbi->mapping & 0xFFFFFFFFUL);
 717         rxdesc->desc1.datalen   = cpu_to_le16(rxbi->len);
 718         if (jme->dev->features & NETIF_F_HIGHDMA)
 719                 rxdesc->desc1.flags = RXFLAG_64BIT;
 720         wmb();
 721         rxdesc->desc1.flags     |= RXFLAG_OWN | RXFLAG_INT;
 722 }
 723
 724 static int
 725 jme_make_new_rx_buf(struct jme_adapter *jme, int i)
 726 {
 727         struct jme_ring *rxring = &(jme->rxring[0]);
 728         struct jme_buffer_info *rxbi = rxring->bufinf + i;
 729         struct sk_buff *skb;
 730         dma_addr_t mapping;
 731
 732         skb = netdev_alloc_skb(jme->dev,
 733                 jme->dev->mtu + RX_EXTRA_LEN);
 734         if (unlikely(!skb))
 735                 return -ENOMEM;
 736
 737         mapping = pci_map_page(jme->pdev, virt_to_page(skb->data),
 738                                offset_in_page(skb->data), skb_tailroom(skb),
 739                                PCI_DMA_FROMDEVICE);
 740         if (unlikely(pci_dma_mapping_error(jme->pdev, mapping))) {
 741                 dev_kfree_skb(skb);
 742                 return -ENOMEM;
 743         }
 744
 745         if (likely(rxbi->mapping))
 746                 pci_unmap_page(jme->pdev, rxbi->mapping,
 747                                rxbi->len, PCI_DMA_FROMDEVICE);
 748
 749         rxbi->skb = skb;
 750         rxbi->len = skb_tailroom(skb);
 751         rxbi->mapping = mapping;
 752         return 0;
 753 }
 754
 755 static void
 756 jme_free_rx_buf(struct jme_adapter *jme, int i)
 757 {
 758         struct jme_ring *rxring = &(jme->rxring[0]);
 759         struct jme_buffer_info *rxbi = rxring->bufinf;
 760         rxbi += i;
 761
 762         if (rxbi->skb) {
 763                 pci_unmap_page(jme->pdev,
 764                                  rxbi->mapping,
 765                                  rxbi->len,
 766                                  PCI_DMA_FROMDEVICE);
 767                 dev_kfree_skb(rxbi->skb);
 768                 rxbi->skb = NULL;
 769                 rxbi->mapping = 0;
 770                 rxbi->len = 0;
 771         }
 772 }
 773
 774 static void
 775 jme_free_rx_resources(struct jme_adapter *jme)
 776 {
 777         int i;
 778         struct jme_ring *rxring = &(jme->rxring[0]);
 779
 780         if (rxring->alloc) {
 781                 if (rxring->bufinf) {
 782                         for (i = 0 ; i < jme->rx_ring_size ; ++i)
 783                                 jme_free_rx_buf(jme, i);
 784                         kfree(rxring->bufinf);
 785                 }
 786
 787                 dma_free_coherent(&(jme->pdev->dev),
 788                                   RX_RING_ALLOC_SIZE(jme->rx_ring_size),
 789                                   rxring->alloc,
 790                                   rxring->dmaalloc);
 791                 rxring->alloc    = NULL;
 792                 rxring->desc     = NULL;
 793                 rxring->dmaalloc = 0;
 794                 rxring->dma      = 0;
 795                 rxring->bufinf   = NULL;
 796         }
 797         rxring->next_to_use   = 0;
 798         atomic_set(&rxring->next_to_clean, 0);
 799 }
 800
 801 static int
 802 jme_setup_rx_resources(struct jme_adapter *jme)
 803 {
 804         int i;
 805         struct jme_ring *rxring = &(jme->rxring[0]);
 806
 807         rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
 808                                    RX_RING_ALLOC_SIZE(jme->rx_ring_size),
 809                                    &(rxring->dmaalloc),
 810                                    GFP_ATOMIC);
 811         if (!rxring->alloc)
 812                 goto err_set_null;
 813
 814         /*
 815          * 16 Bytes align
 816          */
 817         rxring->desc            = (void *)ALIGN((unsigned long)(rxring->alloc),
 818                                                 RING_DESC_ALIGN);
 819         rxring->dma             = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
 820         rxring->next_to_use     = 0;
 821         atomic_set(&rxring->next_to_clean, 0);
 822
 823         rxring->bufinf          = kcalloc(jme->rx_ring_size,
 824                                                 sizeof(struct jme_buffer_info),
 825                                                 GFP_ATOMIC);
 826         if (unlikely(!(rxring->bufinf)))
 827                 goto err_free_rxring;
 828
 829         /*
 830          * Initiallize Receive Descriptors
 831          */
 832         for (i = 0 ; i < jme->rx_ring_size ; ++i) {
 833                 if (unlikely(jme_make_new_rx_buf(jme, i))) {
 834                         jme_free_rx_resources(jme);
 835                         return -ENOMEM;
 836                 }
 837
 838                 jme_set_clean_rxdesc(jme, i);
 839         }
 840
 841         return 0;
 842
 843 err_free_rxring:
 844         dma_free_coherent(&(jme->pdev->dev),
 845                           RX_RING_ALLOC_SIZE(jme->rx_ring_size),
 846                           rxring->alloc,
 847                           rxring->dmaalloc);
 848 err_set_null:
 849         rxring->desc = NULL;
 850         rxring->dmaalloc = 0;
 851         rxring->dma = 0;
 852         rxring->bufinf = NULL;
 853
 854         return -ENOMEM;
 855 }
 856
 857 static inline void
 858 jme_enable_rx_engine(struct jme_adapter *jme)
 859 {
 860         /*
 861          * Select Queue 0
 862          */
 863         jwrite32(jme, JME_RXCS, jme->reg_rxcs |
 864                                 RXCS_QUEUESEL_Q0);
 865         wmb();
 866
 867         /*
 868          * Setup RX DMA Bass Address
 869          */
 870         jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
 871         jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
 872         jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
 873
 874         /*
 875          * Setup RX Descriptor Count
 876          */
 877         jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
 878
 879         /*
 880          * Setup Unicast Filter
 881          */
 882         jme_set_unicastaddr(jme->dev);
 883         jme_set_multi(jme->dev);
 884
 885         /*
 886          * Enable RX Engine
 887          */
 888         wmb();
 889         jwrite32f(jme, JME_RXCS, jme->reg_rxcs |
 890                                 RXCS_QUEUESEL_Q0 |
 891                                 RXCS_ENABLE |
 892                                 RXCS_QST);
 893
 894         /*
 895          * Start clock for RX MAC Processor
 896          */
 897         jme_mac_rxclk_on(jme);
 898 }
 899
 900 static inline void
 901 jme_restart_rx_engine(struct jme_adapter *jme)
 902 {
 903         /*
 904          * Start RX Engine
 905          */
 906         jwrite32(jme, JME_RXCS, jme->reg_rxcs |
 907                                 RXCS_QUEUESEL_Q0 |
 908                                 RXCS_ENABLE |
 909                                 RXCS_QST);
 910 }
 911
 912 static inline void
 913 jme_disable_rx_engine(struct jme_adapter *jme)
 914 {
 915         int i;
 916         u32 val;
 917
 918         /*
 919          * Disable RX Engine
 920          */
 921         jwrite32(jme, JME_RXCS, jme->reg_rxcs);
 922         wmb();
 923
 924         val = jread32(jme, JME_RXCS);
 925         for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
 926                 mdelay(1);
 927                 val = jread32(jme, JME_RXCS);
 928                 rmb();
 929         }
 930
 931         if (!i)
 932                 pr_err("Disable RX engine timeout\n");
 933
 934         /*
 935          * Stop clock for RX MAC Processor
 936          */
 937         jme_mac_rxclk_off(jme);
 938 }
 939
 940 static u16
 941 jme_udpsum(struct sk_buff *skb)
 942 {
 943         u16 csum = 0xFFFFu;
 944
 945         if (skb->len < (ETH_HLEN + sizeof(struct iphdr)))
 946                 return csum;
 947         if (skb->protocol != htons(ETH_P_IP))
 948                 return csum;
 949         skb_set_network_header(skb, ETH_HLEN);
 950         if ((ip_hdr(skb)->protocol != IPPROTO_UDP) ||
 951             (skb->len < (ETH_HLEN +
 952                         (ip_hdr(skb)->ihl << 2) +
 953                         sizeof(struct udphdr)))) {
 954                 skb_reset_network_header(skb);
 955                 return csum;
 956         }
 957         skb_set_transport_header(skb,
 958                         ETH_HLEN + (ip_hdr(skb)->ihl << 2));
 959         csum = udp_hdr(skb)->check;
 960         skb_reset_transport_header(skb);
 961         skb_reset_network_header(skb);
 962
 963         return csum;
 964 }
 965
 966 static int
 967 jme_rxsum_ok(struct jme_adapter *jme, u16 flags, struct sk_buff *skb)
 968 {
 969         if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
 970                 return false;
 971
 972         if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
 973                         == RXWBFLAG_TCPON)) {
 974                 if (flags & RXWBFLAG_IPV4)
 975                         netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
 976                 return false;
 977         }
 978
 979         if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
 980                         == RXWBFLAG_UDPON) && jme_udpsum(skb)) {
 981                 if (flags & RXWBFLAG_IPV4)
 982                         netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n");
 983                 return false;
 984         }
 985
 986         if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
 987                         == RXWBFLAG_IPV4)) {
 988                 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n");
 989                 return false;
 990         }
 991
 992         return true;
 993 }
 994
 995 static void
 996 jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
 997 {
 998         struct jme_ring *rxring = &(jme->rxring[0]);
 999         struct rxdesc *rxdesc = rxring->desc;
1000         struct jme_buffer_info *rxbi = rxring->bufinf;
1001         struct sk_buff *skb;
1002         int framesize;
1003
1004         rxdesc += idx;
1005         rxbi += idx;
1006
1007         skb = rxbi->skb;
1008         pci_dma_sync_single_for_cpu(jme->pdev,
1009                                         rxbi->mapping,
1010                                         rxbi->len,
1011                                         PCI_DMA_FROMDEVICE);
1012
1013         if (unlikely(jme_make_new_rx_buf(jme, idx))) {
1014                 pci_dma_sync_single_for_device(jme->pdev,
1015                                                 rxbi->mapping,
1016                                                 rxbi->len,
1017                                                 PCI_DMA_FROMDEVICE);
1018
1019                 ++(NET_STAT(jme).rx_dropped);
1020         } else {
1021                 framesize = le16_to_cpu(rxdesc->descwb.framesize)
1022                                 - RX_PREPAD_SIZE;
1023
1024                 skb_reserve(skb, RX_PREPAD_SIZE);
1025                 skb_put(skb, framesize);
1026                 skb->protocol = eth_type_trans(skb, jme->dev);
1027
1028                 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags), skb))
1029                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1030                 else
1031                         skb_checksum_none_assert(skb);
1032
1033                 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
1034                         u16 vid = le16_to_cpu(rxdesc->descwb.vlan);
1035
1036                         __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
1037                         NET_STAT(jme).rx_bytes += 4;
1038                 }
1039                 jme->jme_rx(skb);
1040
1041                 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
1042                     cpu_to_le16(RXWBFLAG_DEST_MUL))
1043                         ++(NET_STAT(jme).multicast);
1044
1045                 NET_STAT(jme).rx_bytes += framesize;
1046                 ++(NET_STAT(jme).rx_packets);
1047         }
1048
1049         jme_set_clean_rxdesc(jme, idx);
1050
1051 }
1052
1053 static int
1054 jme_process_receive(struct jme_adapter *jme, int limit)
1055 {
1056         struct jme_ring *rxring = &(jme->rxring[0]);
1057         struct rxdesc *rxdesc;
1058         int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
1059
1060         if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
1061                 goto out_inc;
1062
1063         if (unlikely(atomic_read(&jme->link_changing) != 1))
1064                 goto out_inc;
1065
1066         if (unlikely(!netif_carrier_ok(jme->dev)))
1067                 goto out_inc;
1068
1069         i = atomic_read(&rxring->next_to_clean);
1070         while (limit > 0) {
1071                 rxdesc = rxring->desc;
1072                 rxdesc += i;
1073
1074                 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
1075                 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
1076                         goto out;
1077                 --limit;
1078
1079                 rmb();
1080                 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
1081
1082                 if (unlikely(desccnt > 1 ||
1083                 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
1084
1085                         if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
1086                                 ++(NET_STAT(jme).rx_crc_errors);
1087                         else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
1088                                 ++(NET_STAT(jme).rx_fifo_errors);
1089                         else
1090                                 ++(NET_STAT(jme).rx_errors);
1091
1092                         if (desccnt > 1)
1093                                 limit -= desccnt - 1;
1094
1095                         for (j = i, ccnt = desccnt ; ccnt-- ; ) {
1096                                 jme_set_clean_rxdesc(jme, j);
1097                                 j = (j + 1) & (mask);
1098                         }
1099
1100                 } else {
1101                         jme_alloc_and_feed_skb(jme, i);
1102                 }
1103
1104                 i = (i + desccnt) & (mask);
1105         }
1106
1107 out:
1108         atomic_set(&rxring->next_to_clean, i);
1109
1110 out_inc:
1111         atomic_inc(&jme->rx_cleaning);
1112
1113         return limit > 0 ? limit : 0;
1114
1115 }
1116
1117 static void
1118 jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1119 {
1120         if (likely(atmp == dpi->cur)) {
1121                 dpi->cnt = 0;
1122                 return;
1123         }
1124
1125         if (dpi->attempt == atmp) {
1126                 ++(dpi->cnt);
1127         } else {
1128                 dpi->attempt = atmp;
1129                 dpi->cnt = 0;
1130         }
1131
1132 }
1133
1134 static void
1135 jme_dynamic_pcc(struct jme_adapter *jme)
1136 {
1137         register struct dynpcc_info *dpi = &(jme->dpi);
1138
1139         if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1140                 jme_attempt_pcc(dpi, PCC_P3);
1141         else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1142                  dpi->intr_cnt > PCC_INTR_THRESHOLD)
1143                 jme_attempt_pcc(dpi, PCC_P2);
1144         else
1145                 jme_attempt_pcc(dpi, PCC_P1);
1146
1147         if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1148                 if (dpi->attempt < dpi->cur)
1149                         tasklet_schedule(&jme->rxclean_task);
1150                 jme_set_rx_pcc(jme, dpi->attempt);
1151                 dpi->cur = dpi->attempt;
1152                 dpi->cnt = 0;
1153         }
1154 }
1155
1156 static void
1157 jme_start_pcc_timer(struct jme_adapter *jme)
1158 {
1159         struct dynpcc_info *dpi = &(jme->dpi);
1160         dpi->last_bytes         = NET_STAT(jme).rx_bytes;
1161         dpi->last_pkts          = NET_STAT(jme).rx_packets;
1162         dpi->intr_cnt           = 0;
1163         jwrite32(jme, JME_TMCSR,
1164                 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1165 }
1166
1167 static inline void
1168 jme_stop_pcc_timer(struct jme_adapter *jme)
1169 {
1170         jwrite32(jme, JME_TMCSR, 0);
1171 }
1172
1173 static void
1174 jme_shutdown_nic(struct jme_adapter *jme)
1175 {
1176         u32 phylink;
1177
1178         phylink = jme_linkstat_from_phy(jme);
1179
1180         if (!(phylink & PHY_LINK_UP)) {
1181                 /*
1182                  * Disable all interrupt before issue timer
1183                  */
1184                 jme_stop_irq(jme);
1185                 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1186         }
1187 }
1188
1189 static void
1190 jme_pcc_tasklet(struct tasklet_struct *t)
1191 {
1192         struct jme_adapter *jme = from_tasklet(jme, t, pcc_task);
1193         struct net_device *netdev = jme->dev;
1194
1195         if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1196                 jme_shutdown_nic(jme);
1197                 return;
1198         }
1199
1200         if (unlikely(!netif_carrier_ok(netdev) ||
1201                 (atomic_read(&jme->link_changing) != 1)
1202         )) {
1203                 jme_stop_pcc_timer(jme);
1204                 return;
1205         }
1206
1207         if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
1208                 jme_dynamic_pcc(jme);
1209
1210         jme_start_pcc_timer(jme);
1211 }
1212
1213 static inline void
1214 jme_polling_mode(struct jme_adapter *jme)
1215 {
1216         jme_set_rx_pcc(jme, PCC_OFF);
1217 }
1218
1219 static inline void
1220 jme_interrupt_mode(struct jme_adapter *jme)
1221 {
1222         jme_set_rx_pcc(jme, PCC_P1);
1223 }
1224
1225 static inline int
1226 jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1227 {
1228         u32 apmc;
1229         apmc = jread32(jme, JME_APMC);
1230         return apmc & JME_APMC_PSEUDO_HP_EN;
1231 }
1232
1233 static void
1234 jme_start_shutdown_timer(struct jme_adapter *jme)
1235 {
1236         u32 apmc;
1237
1238         apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1239         apmc &= ~JME_APMC_EPIEN_CTRL;
1240         if (!no_extplug) {
1241                 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1242                 wmb();
1243         }
1244         jwrite32f(jme, JME_APMC, apmc);
1245
1246         jwrite32f(jme, JME_TIMER2, 0);
1247         set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1248         jwrite32(jme, JME_TMCSR,
1249                 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1250 }
1251
1252 static void
1253 jme_stop_shutdown_timer(struct jme_adapter *jme)
1254 {
1255         u32 apmc;
1256
1257         jwrite32f(jme, JME_TMCSR, 0);
1258         jwrite32f(jme, JME_TIMER2, 0);
1259         clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1260
1261         apmc = jread32(jme, JME_APMC);
1262         apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1263         jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1264         wmb();
1265         jwrite32f(jme, JME_APMC, apmc);
1266 }
1267
1268 static void jme_link_change_work(struct work_struct *work)
1269 {
1270         struct jme_adapter *jme = container_of(work, struct jme_adapter, linkch_task);
1271         struct net_device *netdev = jme->dev;
1272         int rc;
1273
1274         while (!atomic_dec_and_test(&jme->link_changing)) {
1275                 atomic_inc(&jme->link_changing);
1276                 netif_info(jme, intr, jme->dev, "Get link change lock failed\n");
1277                 while (atomic_read(&jme->link_changing) != 1)
1278                         netif_info(jme, intr, jme->dev, "Waiting link change lock\n");
1279         }
1280
1281         if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1282                 goto out;
1283
1284         jme->old_mtu = netdev->mtu;
1285         netif_stop_queue(netdev);
1286         if (jme_pseudo_hotplug_enabled(jme))
1287                 jme_stop_shutdown_timer(jme);
1288
1289         jme_stop_pcc_timer(jme);
1290         tasklet_disable(&jme->txclean_task);
1291         tasklet_disable(&jme->rxclean_task);
1292         tasklet_disable(&jme->rxempty_task);
1293
1294         if (netif_carrier_ok(netdev)) {
1295                 jme_disable_rx_engine(jme);
1296                 jme_disable_tx_engine(jme);
1297                 jme_reset_mac_processor(jme);
1298                 jme_free_rx_resources(jme);
1299                 jme_free_tx_resources(jme);
1300
1301                 if (test_bit(JME_FLAG_POLL, &jme->flags))
1302                         jme_polling_mode(jme);
1303
1304                 netif_carrier_off(netdev);
1305         }
1306
1307         jme_check_link(netdev, 0);
1308         if (netif_carrier_ok(netdev)) {
1309                 rc = jme_setup_rx_resources(jme);
1310                 if (rc) {
1311                         pr_err("Allocating resources for RX error, Device STOPPED!\n");
1312                         goto out_enable_tasklet;
1313                 }
1314
1315                 rc = jme_setup_tx_resources(jme);
1316                 if (rc) {
1317                         pr_err("Allocating resources for TX error, Device STOPPED!\n");
1318                         goto err_out_free_rx_resources;
1319                 }
1320
1321                 jme_enable_rx_engine(jme);
1322                 jme_enable_tx_engine(jme);
1323
1324                 netif_start_queue(netdev);
1325
1326                 if (test_bit(JME_FLAG_POLL, &jme->flags))
1327                         jme_interrupt_mode(jme);
1328
1329                 jme_start_pcc_timer(jme);
1330         } else if (jme_pseudo_hotplug_enabled(jme)) {
1331                 jme_start_shutdown_timer(jme);
1332         }
1333
1334         goto out_enable_tasklet;
1335
1336 err_out_free_rx_resources:
1337         jme_free_rx_resources(jme);
1338 out_enable_tasklet:
1339         tasklet_enable(&jme->txclean_task);
1340         tasklet_enable(&jme->rxclean_task);
1341         tasklet_enable(&jme->rxempty_task);
1342 out:
1343         atomic_inc(&jme->link_changing);
1344 }
1345
1346 static void
1347 jme_rx_clean_tasklet(struct tasklet_struct *t)
1348 {
1349         struct jme_adapter *jme = from_tasklet(jme, t, rxclean_task);
1350         struct dynpcc_info *dpi = &(jme->dpi);
1351
1352         jme_process_receive(jme, jme->rx_ring_size);
1353         ++(dpi->intr_cnt);
1354
1355 }
1356
1357 static int
1358 jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
1359 {
1360         struct jme_adapter *jme = jme_napi_priv(holder);
1361         int rest;
1362
1363         rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1364
1365         while (atomic_read(&jme->rx_empty) > 0) {
1366                 atomic_dec(&jme->rx_empty);
1367                 ++(NET_STAT(jme).rx_dropped);
1368                 jme_restart_rx_engine(jme);
1369         }
1370         atomic_inc(&jme->rx_empty);
1371
1372         if (rest) {
1373                 JME_RX_COMPLETE(netdev, holder);
1374                 jme_interrupt_mode(jme);
1375         }
1376
1377         JME_NAPI_WEIGHT_SET(budget, rest);
1378         return JME_NAPI_WEIGHT_VAL(budget) - rest;
1379 }
1380
1381 static void
1382 jme_rx_empty_tasklet(struct tasklet_struct *t)
1383 {
1384         struct jme_adapter *jme = from_tasklet(jme, t, rxempty_task);
1385
1386         if (unlikely(atomic_read(&jme->link_changing) != 1))
1387                 return;
1388
1389         if (unlikely(!netif_carrier_ok(jme->dev)))
1390                 return;
1391
1392         netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
1393
1394         jme_rx_clean_tasklet(&jme->rxclean_task);
1395
1396         while (atomic_read(&jme->rx_empty) > 0) {
1397                 atomic_dec(&jme->rx_empty);
1398                 ++(NET_STAT(jme).rx_dropped);
1399                 jme_restart_rx_engine(jme);
1400         }
1401         atomic_inc(&jme->rx_empty);
1402 }
1403
1404 static void
1405 jme_wake_queue_if_stopped(struct jme_adapter *jme)
1406 {
1407         struct jme_ring *txring = &(jme->txring[0]);
1408
1409         smp_wmb();
1410         if (unlikely(netif_queue_stopped(jme->dev) &&
1411         atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1412                 netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n");
1413                 netif_wake_queue(jme->dev);
1414         }
1415
1416 }
1417
1418 static void jme_tx_clean_tasklet(struct tasklet_struct *t)
1419 {
1420         struct jme_adapter *jme = from_tasklet(jme, t, txclean_task);
1421         struct jme_ring *txring = &(jme->txring[0]);
1422         struct txdesc *txdesc = txring->desc;
1423         struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1424         int i, j, cnt = 0, max, err, mask;
1425
1426         tx_dbg(jme, "Into txclean\n");
1427
1428         if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1429                 goto out;
1430
1431         if (unlikely(atomic_read(&jme->link_changing) != 1))
1432                 goto out;
1433
1434         if (unlikely(!netif_carrier_ok(jme->dev)))
1435                 goto out;
1436
1437         max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1438         mask = jme->tx_ring_mask;
1439
1440         for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
1441
1442                 ctxbi = txbi + i;
1443
1444                 if (likely(ctxbi->skb &&
1445                 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1446
1447                         tx_dbg(jme, "txclean: %d+%d@%lu\n",
1448                                i, ctxbi->nr_desc, jiffies);
1449
1450                         err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1451
1452                         for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
1453                                 ttxbi = txbi + ((i + j) & (mask));
1454                                 txdesc[(i + j) & (mask)].dw[0] = 0;
1455
1456                                 pci_unmap_page(jme->pdev,
1457                                                  ttxbi->mapping,
1458                                                  ttxbi->len,
1459                                                  PCI_DMA_TODEVICE);
1460
1461                                 ttxbi->mapping = 0;
1462                                 ttxbi->len = 0;
1463                         }
1464
1465                         dev_kfree_skb(ctxbi->skb);
1466
1467                         cnt += ctxbi->nr_desc;
1468
1469                         if (unlikely(err)) {
1470                                 ++(NET_STAT(jme).tx_carrier_errors);
1471                         } else {
1472                                 ++(NET_STAT(jme).tx_packets);
1473                                 NET_STAT(jme).tx_bytes += ctxbi->len;
1474                         }
1475
1476                         ctxbi->skb = NULL;
1477                         ctxbi->len = 0;
1478                         ctxbi->start_xmit = 0;
1479
1480                 } else {
1481                         break;
1482                 }
1483
1484                 i = (i + ctxbi->nr_desc) & mask;
1485
1486                 ctxbi->nr_desc = 0;
1487         }
1488
1489         tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies);
1490         atomic_set(&txring->next_to_clean, i);
1491         atomic_add(cnt, &txring->nr_free);
1492
1493         jme_wake_queue_if_stopped(jme);
1494
1495 out:
1496         atomic_inc(&jme->tx_cleaning);
1497 }
1498
1499 static void
1500 jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
1501 {
1502         /*
1503          * Disable interrupt
1504          */
1505         jwrite32f(jme, JME_IENC, INTR_ENABLE);
1506
1507         if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1508                 /*
1509                  * Link change event is critical
1510                  * all other events are ignored
1511                  */
1512                 jwrite32(jme, JME_IEVE, intrstat);
1513                 schedule_work(&jme->linkch_task);
1514                 goto out_reenable;
1515         }
1516
1517         if (intrstat & INTR_TMINTR) {
1518                 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1519                 tasklet_schedule(&jme->pcc_task);
1520         }
1521
1522         if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
1523                 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1524                 tasklet_schedule(&jme->txclean_task);
1525         }
1526
1527         if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1528                 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1529                                                      INTR_PCCRX0 |
1530                                                      INTR_RX0EMP)) |
1531                                         INTR_RX0);
1532         }
1533
1534         if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1535                 if (intrstat & INTR_RX0EMP)
1536                         atomic_inc(&jme->rx_empty);
1537
1538                 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1539                         if (likely(JME_RX_SCHEDULE_PREP(jme))) {
1540                                 jme_polling_mode(jme);
1541                                 JME_RX_SCHEDULE(jme);
1542                         }
1543                 }
1544         } else {
1545                 if (intrstat & INTR_RX0EMP) {
1546                         atomic_inc(&jme->rx_empty);
1547                         tasklet_hi_schedule(&jme->rxempty_task);
1548                 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1549                         tasklet_hi_schedule(&jme->rxclean_task);
1550                 }
1551         }
1552
1553 out_reenable:
1554         /*
1555          * Re-enable interrupt
1556          */
1557         jwrite32f(jme, JME_IENS, INTR_ENABLE);
1558 }
1559
1560 static irqreturn_t
1561 jme_intr(int irq, void *dev_id)
1562 {
1563         struct net_device *netdev = dev_id;
1564         struct jme_adapter *jme = netdev_priv(netdev);
1565         u32 intrstat;
1566
1567         intrstat = jread32(jme, JME_IEVE);
1568
1569         /*
1570          * Check if it's really an interrupt for us
1571          */
1572         if (unlikely((intrstat & INTR_ENABLE) == 0))
1573                 return IRQ_NONE;
1574
1575         /*
1576          * Check if the device still exist
1577          */
1578         if (unlikely(intrstat == ~((typeof(intrstat))0)))
1579                 return IRQ_NONE;
1580
1581         jme_intr_msi(jme, intrstat);
1582
1583         return IRQ_HANDLED;
1584 }
1585
1586 static irqreturn_t
1587 jme_msi(int irq, void *dev_id)
1588 {
1589         struct net_device *netdev = dev_id;
1590         struct jme_adapter *jme = netdev_priv(netdev);
1591         u32 intrstat;
1592
1593         intrstat = jread32(jme, JME_IEVE);
1594
1595         jme_intr_msi(jme, intrstat);
1596
1597         return IRQ_HANDLED;
1598 }
1599
1600 static void
1601 jme_reset_link(struct jme_adapter *jme)
1602 {
1603         jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1604 }
1605
1606 static void
1607 jme_restart_an(struct jme_adapter *jme)
1608 {
1609         u32 bmcr;
1610
1611         spin_lock_bh(&jme->phy_lock);
1612         bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1613         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1614         jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1615         spin_unlock_bh(&jme->phy_lock);
1616 }
1617
1618 static int
1619 jme_request_irq(struct jme_adapter *jme)
1620 {
1621         int rc;
1622         struct net_device *netdev = jme->dev;
1623         irq_handler_t handler = jme_intr;
1624         int irq_flags = IRQF_SHARED;
1625
1626         if (!pci_enable_msi(jme->pdev)) {
1627                 set_bit(JME_FLAG_MSI, &jme->flags);
1628                 handler = jme_msi;
1629                 irq_flags = 0;
1630         }
1631
1632         rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1633                           netdev);
1634         if (rc) {
1635                 netdev_err(netdev,
1636                            "Unable to request %s interrupt (return: %d)\n",
1637                            test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1638                            rc);
1639
1640                 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1641                         pci_disable_msi(jme->pdev);
1642                         clear_bit(JME_FLAG_MSI, &jme->flags);
1643                 }
1644         } else {
1645                 netdev->irq = jme->pdev->irq;
1646         }
1647
1648         return rc;
1649 }
1650
1651 static void
1652 jme_free_irq(struct jme_adapter *jme)
1653 {
1654         free_irq(jme->pdev->irq, jme->dev);
1655         if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1656                 pci_disable_msi(jme->pdev);
1657                 clear_bit(JME_FLAG_MSI, &jme->flags);
1658                 jme->dev->irq = jme->pdev->irq;
1659         }
1660 }
1661
1662 static inline void
1663 jme_new_phy_on(struct jme_adapter *jme)
1664 {
1665         u32 reg;
1666
1667         reg = jread32(jme, JME_PHY_PWR);
1668         reg &= ~(PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1669                  PHY_PWR_DWN2 | PHY_PWR_CLKSEL);
1670         jwrite32(jme, JME_PHY_PWR, reg);
1671
1672         pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1673         reg &= ~PE1_GPREG0_PBG;
1674         reg |= PE1_GPREG0_ENBG;
1675         pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1676 }
1677
1678 static inline void
1679 jme_new_phy_off(struct jme_adapter *jme)
1680 {
1681         u32 reg;
1682
1683         reg = jread32(jme, JME_PHY_PWR);
1684         reg |= PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1685                PHY_PWR_DWN2 | PHY_PWR_CLKSEL;
1686         jwrite32(jme, JME_PHY_PWR, reg);
1687
1688         pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1689         reg &= ~PE1_GPREG0_PBG;
1690         reg |= PE1_GPREG0_PDD3COLD;
1691         pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1692 }
1693
1694 static inline void
1695 jme_phy_on(struct jme_adapter *jme)
1696 {
1697         u32 bmcr;
1698
1699         bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1700         bmcr &= ~BMCR_PDOWN;
1701         jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1702
1703         if (new_phy_power_ctrl(jme->chip_main_rev))
1704                 jme_new_phy_on(jme);
1705 }
1706
1707 static inline void
1708 jme_phy_off(struct jme_adapter *jme)
1709 {
1710         u32 bmcr;
1711
1712         bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1713         bmcr |= BMCR_PDOWN;
1714         jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1715
1716         if (new_phy_power_ctrl(jme->chip_main_rev))
1717                 jme_new_phy_off(jme);
1718 }
1719
1720 static int
1721 jme_phy_specreg_read(struct jme_adapter *jme, u32 specreg)
1722 {
1723         u32 phy_addr;
1724
1725         phy_addr = JM_PHY_SPEC_REG_READ | specreg;
1726         jme_mdio_write(jme->dev, jme->mii_if.phy_id, JM_PHY_SPEC_ADDR_REG,
1727                         phy_addr);
1728         return jme_mdio_read(jme->dev, jme->mii_if.phy_id,
1729                         JM_PHY_SPEC_DATA_REG);
1730 }
1731
1732 static void
1733 jme_phy_specreg_write(struct jme_adapter *jme, u32 ext_reg, u32 phy_data)
1734 {
1735         u32 phy_addr;
1736
1737         phy_addr = JM_PHY_SPEC_REG_WRITE | ext_reg;
1738         jme_mdio_write(jme->dev, jme->mii_if.phy_id, JM_PHY_SPEC_DATA_REG,
1739                         phy_data);
1740         jme_mdio_write(jme->dev, jme->mii_if.phy_id, JM_PHY_SPEC_ADDR_REG,
1741                         phy_addr);
1742 }
1743
1744 static int
1745 jme_phy_calibration(struct jme_adapter *jme)
1746 {
1747         u32 ctrl1000, phy_data;
1748
1749         jme_phy_off(jme);
1750         jme_phy_on(jme);
1751         /*  Enabel PHY test mode 1 */
1752         ctrl1000 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_CTRL1000);
1753         ctrl1000 &= ~PHY_GAD_TEST_MODE_MSK;
1754         ctrl1000 |= PHY_GAD_TEST_MODE_1;
1755         jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_CTRL1000, ctrl1000);
1756
1757         phy_data = jme_phy_specreg_read(jme, JM_PHY_EXT_COMM_2_REG);
1758         phy_data &= ~JM_PHY_EXT_COMM_2_CALI_MODE_0;
1759         phy_data |= JM_PHY_EXT_COMM_2_CALI_LATCH |
1760                         JM_PHY_EXT_COMM_2_CALI_ENABLE;
1761         jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_2_REG, phy_data);
1762         msleep(20);
1763         phy_data = jme_phy_specreg_read(jme, JM_PHY_EXT_COMM_2_REG);
1764         phy_data &= ~(JM_PHY_EXT_COMM_2_CALI_ENABLE |
1765                         JM_PHY_EXT_COMM_2_CALI_MODE_0 |
1766                         JM_PHY_EXT_COMM_2_CALI_LATCH);
1767         jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_2_REG, phy_data);
1768
1769         /*  Disable PHY test mode */
1770         ctrl1000 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_CTRL1000);
1771         ctrl1000 &= ~PHY_GAD_TEST_MODE_MSK;
1772         jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_CTRL1000, ctrl1000);
1773         return 0;
1774 }
1775
1776 static int
1777 jme_phy_setEA(struct jme_adapter *jme)
1778 {
1779         u32 phy_comm0 = 0, phy_comm1 = 0;
1780         u8 nic_ctrl;
1781
1782         pci_read_config_byte(jme->pdev, PCI_PRIV_SHARE_NICCTRL, &nic_ctrl);
1783         if ((nic_ctrl & 0x3) == JME_FLAG_PHYEA_ENABLE)
1784                 return 0;
1785
1786         switch (jme->pdev->device) {
1787         case PCI_DEVICE_ID_JMICRON_JMC250:
1788                 if (((jme->chip_main_rev == 5) &&
1789                         ((jme->chip_sub_rev == 0) || (jme->chip_sub_rev == 1) ||
1790                         (jme->chip_sub_rev == 3))) ||
1791                         (jme->chip_main_rev >= 6)) {
1792                         phy_comm0 = 0x008A;
1793                         phy_comm1 = 0x4109;
1794                 }
1795                 if ((jme->chip_main_rev == 3) &&
1796                         ((jme->chip_sub_rev == 1) || (jme->chip_sub_rev == 2)))
1797                         phy_comm0 = 0xE088;
1798                 break;
1799         case PCI_DEVICE_ID_JMICRON_JMC260:
1800                 if (((jme->chip_main_rev == 5) &&
1801                         ((jme->chip_sub_rev == 0) || (jme->chip_sub_rev == 1) ||
1802                         (jme->chip_sub_rev == 3))) ||
1803                         (jme->chip_main_rev >= 6)) {
1804                         phy_comm0 = 0x008A;
1805                         phy_comm1 = 0x4109;
1806                 }
1807                 if ((jme->chip_main_rev == 3) &&
1808                         ((jme->chip_sub_rev == 1) || (jme->chip_sub_rev == 2)))
1809                         phy_comm0 = 0xE088;
1810                 if ((jme->chip_main_rev == 2) && (jme->chip_sub_rev == 0))
1811                         phy_comm0 = 0x608A;
1812                 if ((jme->chip_main_rev == 2) && (jme->chip_sub_rev == 2))
1813                         phy_comm0 = 0x408A;
1814                 break;
1815         default:
1816                 return -ENODEV;
1817         }
1818         if (phy_comm0)
1819                 jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_0_REG, phy_comm0);
1820         if (phy_comm1)
1821                 jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_1_REG, phy_comm1);
1822
1823         return 0;
1824 }
1825
1826 static int
1827 jme_open(struct net_device *netdev)
1828 {
1829         struct jme_adapter *jme = netdev_priv(netdev);
1830         int rc;
1831
1832         jme_clear_pm_disable_wol(jme);
1833         JME_NAPI_ENABLE(jme);
1834
1835         tasklet_setup(&jme->txclean_task, jme_tx_clean_tasklet);
1836         tasklet_setup(&jme->rxclean_task, jme_rx_clean_tasklet);
1837         tasklet_setup(&jme->rxempty_task, jme_rx_empty_tasklet);
1838
1839         rc = jme_request_irq(jme);
1840         if (rc)
1841                 goto err_out;
1842
1843         jme_start_irq(jme);
1844
1845         jme_phy_on(jme);
1846         if (test_bit(JME_FLAG_SSET, &jme->flags))
1847                 jme_set_link_ksettings(netdev, &jme->old_cmd);
1848         else
1849                 jme_reset_phy_processor(jme);
1850         jme_phy_calibration(jme);
1851         jme_phy_setEA(jme);
1852         jme_reset_link(jme);
1853
1854         return 0;
1855
1856 err_out:
1857         netif_stop_queue(netdev);
1858         netif_carrier_off(netdev);
1859         return rc;
1860 }
1861
1862 static void
1863 jme_set_100m_half(struct jme_adapter *jme)
1864 {
1865         u32 bmcr, tmp;
1866
1867         jme_phy_on(jme);
1868         bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1869         tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1870                        BMCR_SPEED1000 | BMCR_FULLDPLX);
1871         tmp |= BMCR_SPEED100;
1872
1873         if (bmcr != tmp)
1874                 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1875
1876         if (jme->fpgaver)
1877                 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1878         else
1879                 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1880 }
1881
1882 #define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1883 static void
1884 jme_wait_link(struct jme_adapter *jme)
1885 {
1886         u32 phylink, to = JME_WAIT_LINK_TIME;
1887
1888         msleep(1000);
1889         phylink = jme_linkstat_from_phy(jme);
1890         while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
1891                 usleep_range(10000, 11000);
1892                 phylink = jme_linkstat_from_phy(jme);
1893         }
1894 }
1895
1896 static void
1897 jme_powersave_phy(struct jme_adapter *jme)
1898 {
1899         if (jme->reg_pmcs && device_may_wakeup(&jme->pdev->dev)) {
1900                 jme_set_100m_half(jme);
1901                 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
1902                         jme_wait_link(jme);
1903                 jme_clear_pm_enable_wol(jme);
1904         } else {
1905                 jme_phy_off(jme);
1906         }
1907 }
1908
1909 static int
1910 jme_close(struct net_device *netdev)
1911 {
1912         struct jme_adapter *jme = netdev_priv(netdev);
1913
1914         netif_stop_queue(netdev);
1915         netif_carrier_off(netdev);
1916
1917         jme_stop_irq(jme);
1918         jme_free_irq(jme);
1919
1920         JME_NAPI_DISABLE(jme);
1921
1922         cancel_work_sync(&jme->linkch_task);
1923         tasklet_kill(&jme->txclean_task);
1924         tasklet_kill(&jme->rxclean_task);
1925         tasklet_kill(&jme->rxempty_task);
1926
1927         jme_disable_rx_engine(jme);
1928         jme_disable_tx_engine(jme);
1929         jme_reset_mac_processor(jme);
1930         jme_free_rx_resources(jme);
1931         jme_free_tx_resources(jme);
1932         jme->phylink = 0;
1933         jme_phy_off(jme);
1934
1935         return 0;
1936 }
1937
1938 static int
1939 jme_alloc_txdesc(struct jme_adapter *jme,
1940                         struct sk_buff *skb)
1941 {
1942         struct jme_ring *txring = &(jme->txring[0]);
1943         int idx, nr_alloc, mask = jme->tx_ring_mask;
1944
1945         idx = txring->next_to_use;
1946         nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1947
1948         if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1949                 return -1;
1950
1951         atomic_sub(nr_alloc, &txring->nr_free);
1952
1953         txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1954
1955         return idx;
1956 }
1957
1958 static int
1959 jme_fill_tx_map(struct pci_dev *pdev,
1960                 struct txdesc *txdesc,
1961                 struct jme_buffer_info *txbi,
1962                 struct page *page,
1963                 u32 page_offset,
1964                 u32 len,
1965                 bool hidma)
1966 {
1967         dma_addr_t dmaaddr;
1968
1969         dmaaddr = pci_map_page(pdev,
1970                                 page,
1971                                 page_offset,
1972                                 len,
1973                                 PCI_DMA_TODEVICE);
1974
1975         if (unlikely(pci_dma_mapping_error(pdev, dmaaddr)))
1976                 return -EINVAL;
1977
1978         pci_dma_sync_single_for_device(pdev,
1979                                        dmaaddr,
1980                                        len,
1981                                        PCI_DMA_TODEVICE);
1982
1983         txdesc->dw[0] = 0;
1984         txdesc->dw[1] = 0;
1985         txdesc->desc2.flags     = TXFLAG_OWN;
1986         txdesc->desc2.flags     |= (hidma) ? TXFLAG_64BIT : 0;
1987         txdesc->desc2.datalen   = cpu_to_le16(len);
1988         txdesc->desc2.bufaddrh  = cpu_to_le32((__u64)dmaaddr >> 32);
1989         txdesc->desc2.bufaddrl  = cpu_to_le32(
1990                                         (__u64)dmaaddr & 0xFFFFFFFFUL);
1991
1992         txbi->mapping = dmaaddr;
1993         txbi->len = len;
1994         return 0;
1995 }
1996
1997 static void jme_drop_tx_map(struct jme_adapter *jme, int startidx, int count)
1998 {
1999         struct jme_ring *txring = &(jme->txring[0]);
2000         struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
2001         int mask = jme->tx_ring_mask;
2002         int j;
2003
2004         for (j = 0 ; j < count ; j++) {
2005                 ctxbi = txbi + ((startidx + j + 2) & (mask));
2006                 pci_unmap_page(jme->pdev,
2007                                 ctxbi->mapping,
2008                                 ctxbi->len,
2009                                 PCI_DMA_TODEVICE);
2010
2011                 ctxbi->mapping = 0;
2012                 ctxbi->len = 0;
2013         }
2014 }
2015
2016 static int
2017 jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
2018 {
2019         struct jme_ring *txring = &(jme->txring[0]);
2020         struct txdesc *txdesc = txring->desc, *ctxdesc;
2021         struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
2022         bool hidma = jme->dev->features & NETIF_F_HIGHDMA;
2023         int i, nr_frags = skb_shinfo(skb)->nr_frags;
2024         int mask = jme->tx_ring_mask;
2025         u32 len;
2026         int ret = 0;
2027
2028         for (i = 0 ; i < nr_frags ; ++i) {
2029                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2030
2031                 ctxdesc = txdesc + ((idx + i + 2) & (mask));
2032                 ctxbi = txbi + ((idx + i + 2) & (mask));
2033
2034                 ret = jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi,
2035                                       skb_frag_page(frag), skb_frag_off(frag),
2036                                       skb_frag_size(frag), hidma);
2037                 if (ret) {
2038                         jme_drop_tx_map(jme, idx, i);
2039                         goto out;
2040                 }
2041         }
2042
2043         len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
2044         ctxdesc = txdesc + ((idx + 1) & (mask));
2045         ctxbi = txbi + ((idx + 1) & (mask));
2046         ret = jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
2047                         offset_in_page(skb->data), len, hidma);
2048         if (ret)
2049                 jme_drop_tx_map(jme, idx, i);
2050
2051 out:
2052         return ret;
2053
2054 }
2055
2056
2057 static int
2058 jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
2059 {
2060         *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
2061         if (*mss) {
2062                 *flags |= TXFLAG_LSEN;
2063
2064                 if (skb->protocol == htons(ETH_P_IP)) {
2065                         struct iphdr *iph = ip_hdr(skb);
2066
2067                         iph->check = 0;
2068                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2069                                                                 iph->daddr, 0,
2070                                                                 IPPROTO_TCP,
2071                                                                 0);
2072                 } else {
2073                         tcp_v6_gso_csum_prep(skb);
2074                 }
2075
2076                 return 0;
2077         }
2078
2079         return 1;
2080 }
2081
2082 static void
2083 jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
2084 {
2085         if (skb->ip_summed == CHECKSUM_PARTIAL) {
2086                 u8 ip_proto;
2087
2088                 switch (skb->protocol) {
2089                 case htons(ETH_P_IP):
2090                         ip_proto = ip_hdr(skb)->protocol;
2091                         break;
2092                 case htons(ETH_P_IPV6):
2093                         ip_proto = ipv6_hdr(skb)->nexthdr;
2094                         break;
2095                 default:
2096                         ip_proto = 0;
2097                         break;
2098                 }
2099
2100                 switch (ip_proto) {
2101                 case IPPROTO_TCP:
2102                         *flags |= TXFLAG_TCPCS;
2103                         break;
2104                 case IPPROTO_UDP:
2105                         *flags |= TXFLAG_UDPCS;
2106                         break;
2107                 default:
2108                         netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n");
2109                         break;
2110                 }
2111         }
2112 }
2113
2114 static inline void
2115 jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
2116 {
2117         if (skb_vlan_tag_present(skb)) {
2118                 *flags |= TXFLAG_TAGON;
2119                 *vlan = cpu_to_le16(skb_vlan_tag_get(skb));
2120         }
2121 }
2122
2123 static int
2124 jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
2125 {
2126         struct jme_ring *txring = &(jme->txring[0]);
2127         struct txdesc *txdesc;
2128         struct jme_buffer_info *txbi;
2129         u8 flags;
2130         int ret = 0;
2131
2132         txdesc = (struct txdesc *)txring->desc + idx;
2133         txbi = txring->bufinf + idx;
2134
2135         txdesc->dw[0] = 0;
2136         txdesc->dw[1] = 0;
2137         txdesc->dw[2] = 0;
2138         txdesc->dw[3] = 0;
2139         txdesc->desc1.pktsize = cpu_to_le16(skb->len);
2140         /*
2141          * Set OWN bit at final.
2142          * When kernel transmit faster than NIC.
2143          * And NIC trying to send this descriptor before we tell
2144          * it to start sending this TX queue.
2145          * Other fields are already filled correctly.
2146          */
2147         wmb();
2148         flags = TXFLAG_OWN | TXFLAG_INT;
2149         /*
2150          * Set checksum flags while not tso
2151          */
2152         if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
2153                 jme_tx_csum(jme, skb, &flags);
2154         jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
2155         ret = jme_map_tx_skb(jme, skb, idx);
2156         if (ret)
2157                 return ret;
2158
2159         txdesc->desc1.flags = flags;
2160         /*
2161          * Set tx buffer info after telling NIC to send
2162          * For better tx_clean timing
2163          */
2164         wmb();
2165         txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
2166         txbi->skb = skb;
2167         txbi->len = skb->len;
2168         txbi->start_xmit = jiffies;
2169         if (!txbi->start_xmit)
2170                 txbi->start_xmit = (0UL-1);
2171
2172         return 0;
2173 }
2174
2175 static void
2176 jme_stop_queue_if_full(struct jme_adapter *jme)
2177 {
2178         struct jme_ring *txring = &(jme->txring[0]);
2179         struct jme_buffer_info *txbi = txring->bufinf;
2180         int idx = atomic_read(&txring->next_to_clean);
2181
2182         txbi += idx;
2183
2184         smp_wmb();
2185         if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
2186                 netif_stop_queue(jme->dev);
2187                 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n");
2188                 smp_wmb();
2189                 if (atomic_read(&txring->nr_free)
2190                         >= (jme->tx_wake_threshold)) {
2191                         netif_wake_queue(jme->dev);
2192                         netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n");
2193                 }
2194         }
2195
2196         if (unlikely(txbi->start_xmit &&
2197                         (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
2198                         txbi->skb)) {
2199                 netif_stop_queue(jme->dev);
2200                 netif_info(jme, tx_queued, jme->dev,
2201                            "TX Queue Stopped %d@%lu\n", idx, jiffies);
2202         }
2203 }
2204
2205 /*
2206  * This function is already protected by netif_tx_lock()
2207  */
2208
2209 static netdev_tx_t
2210 jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
2211 {
2212         struct jme_adapter *jme = netdev_priv(netdev);
2213         int idx;
2214
2215         if (unlikely(skb_is_gso(skb) && skb_cow_head(skb, 0))) {
2216                 dev_kfree_skb_any(skb);
2217                 ++(NET_STAT(jme).tx_dropped);
2218                 return NETDEV_TX_OK;
2219         }
2220
2221         idx = jme_alloc_txdesc(jme, skb);
2222
2223         if (unlikely(idx < 0)) {
2224                 netif_stop_queue(netdev);
2225                 netif_err(jme, tx_err, jme->dev,
2226                           "BUG! Tx ring full when queue awake!\n");
2227
2228                 return NETDEV_TX_BUSY;
2229         }
2230
2231         if (jme_fill_tx_desc(jme, skb, idx))
2232                 return NETDEV_TX_OK;
2233
2234         jwrite32(jme, JME_TXCS, jme->reg_txcs |
2235                                 TXCS_SELECT_QUEUE0 |
2236                                 TXCS_QUEUE0S |
2237                                 TXCS_ENABLE);
2238
2239         tx_dbg(jme, "xmit: %d+%d@%lu\n",
2240                idx, skb_shinfo(skb)->nr_frags + 2, jiffies);
2241         jme_stop_queue_if_full(jme);
2242
2243         return NETDEV_TX_OK;
2244 }
2245
2246 static void
2247 jme_set_unicastaddr(struct net_device *netdev)
2248 {
2249         struct jme_adapter *jme = netdev_priv(netdev);
2250         u32 val;
2251
2252         val = (netdev->dev_addr[3] & 0xff) << 24 |
2253               (netdev->dev_addr[2] & 0xff) << 16 |
2254               (netdev->dev_addr[1] & 0xff) <<  8 |
2255               (netdev->dev_addr[0] & 0xff);
2256         jwrite32(jme, JME_RXUMA_LO, val);
2257         val = (netdev->dev_addr[5] & 0xff) << 8 |
2258               (netdev->dev_addr[4] & 0xff);
2259         jwrite32(jme, JME_RXUMA_HI, val);
2260 }
2261
2262 static int
2263 jme_set_macaddr(struct net_device *netdev, void *p)
2264 {
2265         struct jme_adapter *jme = netdev_priv(netdev);
2266         struct sockaddr *addr = p;
2267
2268         if (netif_running(netdev))
2269                 return -EBUSY;
2270
2271         spin_lock_bh(&jme->macaddr_lock);
2272         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2273         jme_set_unicastaddr(netdev);
2274         spin_unlock_bh(&jme->macaddr_lock);
2275
2276         return 0;
2277 }
2278
2279 static void
2280 jme_set_multi(struct net_device *netdev)
2281 {
2282         struct jme_adapter *jme = netdev_priv(netdev);
2283         u32 mc_hash[2] = {};
2284
2285         spin_lock_bh(&jme->rxmcs_lock);
2286
2287         jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
2288
2289         if (netdev->flags & IFF_PROMISC) {
2290                 jme->reg_rxmcs |= RXMCS_ALLFRAME;
2291         } else if (netdev->flags & IFF_ALLMULTI) {
2292                 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
2293         } else if (netdev->flags & IFF_MULTICAST) {
2294                 struct netdev_hw_addr *ha;
2295                 int bit_nr;
2296
2297                 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
2298                 netdev_for_each_mc_addr(ha, netdev) {
2299                         bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F;
2300                         mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2301                 }
2302
2303                 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2304                 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
2305         }
2306
2307         wmb();
2308         jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2309
2310         spin_unlock_bh(&jme->rxmcs_lock);
2311 }
2312
2313 static int
2314 jme_change_mtu(struct net_device *netdev, int new_mtu)
2315 {
2316         struct jme_adapter *jme = netdev_priv(netdev);
2317
2318         netdev->mtu = new_mtu;
2319         netdev_update_features(netdev);
2320
2321         jme_restart_rx_engine(jme);
2322         jme_reset_link(jme);
2323
2324         return 0;
2325 }
2326
2327 static void
2328 jme_tx_timeout(struct net_device *netdev, unsigned int txqueue)
2329 {
2330         struct jme_adapter *jme = netdev_priv(netdev);
2331
2332         jme->phylink = 0;
2333         jme_reset_phy_processor(jme);
2334         if (test_bit(JME_FLAG_SSET, &jme->flags))
2335                 jme_set_link_ksettings(netdev, &jme->old_cmd);
2336
2337         /*
2338          * Force to Reset the link again
2339          */
2340         jme_reset_link(jme);
2341 }
2342
2343 static void
2344 jme_get_drvinfo(struct net_device *netdev,
2345                      struct ethtool_drvinfo *info)
2346 {
2347         struct jme_adapter *jme = netdev_priv(netdev);
2348
2349         strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
2350         strlcpy(info->version, DRV_VERSION, sizeof(info->version));
2351         strlcpy(info->bus_info, pci_name(jme->pdev), sizeof(info->bus_info));
2352 }
2353
2354 static int
2355 jme_get_regs_len(struct net_device *netdev)
2356 {
2357         return JME_REG_LEN;
2358 }
2359
2360 static void
2361 mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
2362 {
2363         int i;
2364
2365         for (i = 0 ; i < len ; i += 4)
2366                 p[i >> 2] = jread32(jme, reg + i);
2367 }
2368
2369 static void
2370 mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
2371 {
2372         int i;
2373         u16 *p16 = (u16 *)p;
2374
2375         for (i = 0 ; i < reg_nr ; ++i)
2376                 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2377 }
2378
2379 static void
2380 jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2381 {
2382         struct jme_adapter *jme = netdev_priv(netdev);
2383         u32 *p32 = (u32 *)p;
2384
2385         memset(p, 0xFF, JME_REG_LEN);
2386
2387         regs->version = 1;
2388         mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2389
2390         p32 += 0x100 >> 2;
2391         mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2392
2393         p32 += 0x100 >> 2;
2394         mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2395
2396         p32 += 0x100 >> 2;
2397         mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2398
2399         p32 += 0x100 >> 2;
2400         mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2401 }
2402
2403 static int
2404 jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2405 {
2406         struct jme_adapter *jme = netdev_priv(netdev);
2407
2408         ecmd->tx_coalesce_usecs = PCC_TX_TO;
2409         ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2410
2411         if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2412                 ecmd->use_adaptive_rx_coalesce = false;
2413                 ecmd->rx_coalesce_usecs = 0;
2414                 ecmd->rx_max_coalesced_frames = 0;
2415                 return 0;
2416         }
2417
2418         ecmd->use_adaptive_rx_coalesce = true;
2419
2420         switch (jme->dpi.cur) {
2421         case PCC_P1:
2422                 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2423                 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2424                 break;
2425         case PCC_P2:
2426                 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2427                 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2428                 break;
2429         case PCC_P3:
2430                 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2431                 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2432                 break;
2433         default:
2434                 break;
2435         }
2436
2437         return 0;
2438 }
2439
2440 static int
2441 jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2442 {
2443         struct jme_adapter *jme = netdev_priv(netdev);
2444         struct dynpcc_info *dpi = &(jme->dpi);
2445
2446         if (netif_running(netdev))
2447                 return -EBUSY;
2448
2449         if (ecmd->use_adaptive_rx_coalesce &&
2450             test_bit(JME_FLAG_POLL, &jme->flags)) {
2451                 clear_bit(JME_FLAG_POLL, &jme->flags);
2452                 jme->jme_rx = netif_rx;
2453                 dpi->cur                = PCC_P1;
2454                 dpi->attempt            = PCC_P1;
2455                 dpi->cnt                = 0;
2456                 jme_set_rx_pcc(jme, PCC_P1);
2457                 jme_interrupt_mode(jme);
2458         } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2459                    !(test_bit(JME_FLAG_POLL, &jme->flags))) {
2460                 set_bit(JME_FLAG_POLL, &jme->flags);
2461                 jme->jme_rx = netif_receive_skb;
2462                 jme_interrupt_mode(jme);
2463         }
2464
2465         return 0;
2466 }
2467
2468 static void
2469 jme_get_pauseparam(struct net_device *netdev,
2470                         struct ethtool_pauseparam *ecmd)
2471 {
2472         struct jme_adapter *jme = netdev_priv(netdev);
2473         u32 val;
2474
2475         ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2476         ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2477
2478         spin_lock_bh(&jme->phy_lock);
2479         val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2480         spin_unlock_bh(&jme->phy_lock);
2481
2482         ecmd->autoneg =
2483                 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
2484 }
2485
2486 static int
2487 jme_set_pauseparam(struct net_device *netdev,
2488                         struct ethtool_pauseparam *ecmd)
2489 {
2490         struct jme_adapter *jme = netdev_priv(netdev);
2491         u32 val;
2492
2493         if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
2494                 (ecmd->tx_pause != 0)) {
2495
2496                 if (ecmd->tx_pause)
2497                         jme->reg_txpfc |= TXPFC_PF_EN;
2498                 else
2499                         jme->reg_txpfc &= ~TXPFC_PF_EN;
2500
2501                 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2502         }
2503
2504         spin_lock_bh(&jme->rxmcs_lock);
2505         if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
2506                 (ecmd->rx_pause != 0)) {
2507
2508                 if (ecmd->rx_pause)
2509                         jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2510                 else
2511                         jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2512
2513                 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2514         }
2515         spin_unlock_bh(&jme->rxmcs_lock);
2516
2517         spin_lock_bh(&jme->phy_lock);
2518         val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2519         if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
2520                 (ecmd->autoneg != 0)) {
2521
2522                 if (ecmd->autoneg)
2523                         val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2524                 else
2525                         val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2526
2527                 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2528                                 MII_ADVERTISE, val);
2529         }
2530         spin_unlock_bh(&jme->phy_lock);
2531
2532         return 0;
2533 }
2534
2535 static void
2536 jme_get_wol(struct net_device *netdev,
2537                 struct ethtool_wolinfo *wol)
2538 {
2539         struct jme_adapter *jme = netdev_priv(netdev);
2540
2541         wol->supported = WAKE_MAGIC | WAKE_PHY;
2542
2543         wol->wolopts = 0;
2544
2545         if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2546                 wol->wolopts |= WAKE_PHY;
2547
2548         if (jme->reg_pmcs & PMCS_MFEN)
2549                 wol->wolopts |= WAKE_MAGIC;
2550
2551 }
2552
2553 static int
2554 jme_set_wol(struct net_device *netdev,
2555                 struct ethtool_wolinfo *wol)
2556 {
2557         struct jme_adapter *jme = netdev_priv(netdev);
2558
2559         if (wol->wolopts & (WAKE_MAGICSECURE |
2560                                 WAKE_UCAST |
2561                                 WAKE_MCAST |
2562                                 WAKE_BCAST |
2563                                 WAKE_ARP))
2564                 return -EOPNOTSUPP;
2565
2566         jme->reg_pmcs = 0;
2567
2568         if (wol->wolopts & WAKE_PHY)
2569                 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2570
2571         if (wol->wolopts & WAKE_MAGIC)
2572                 jme->reg_pmcs |= PMCS_MFEN;
2573
2574         return 0;
2575 }
2576
2577 static int
2578 jme_get_link_ksettings(struct net_device *netdev,
2579                        struct ethtool_link_ksettings *cmd)
2580 {
2581         struct jme_adapter *jme = netdev_priv(netdev);
2582
2583         spin_lock_bh(&jme->phy_lock);
2584         mii_ethtool_get_link_ksettings(&jme->mii_if, cmd);
2585         spin_unlock_bh(&jme->phy_lock);
2586         return 0;
2587 }
2588
2589 static int
2590 jme_set_link_ksettings(struct net_device *netdev,
2591                        const struct ethtool_link_ksettings *cmd)
2592 {
2593         struct jme_adapter *jme = netdev_priv(netdev);
2594         int rc, fdc = 0;
2595
2596         if (cmd->base.speed == SPEED_1000 &&
2597             cmd->base.autoneg != AUTONEG_ENABLE)
2598                 return -EINVAL;
2599
2600         /*
2601          * Check If user changed duplex only while force_media.
2602          * Hardware would not generate link change interrupt.
2603          */
2604         if (jme->mii_if.force_media &&
2605             cmd->base.autoneg != AUTONEG_ENABLE &&
2606             (jme->mii_if.full_duplex != cmd->base.duplex))
2607                 fdc = 1;
2608
2609         spin_lock_bh(&jme->phy_lock);
2610         rc = mii_ethtool_set_link_ksettings(&jme->mii_if, cmd);
2611         spin_unlock_bh(&jme->phy_lock);
2612
2613         if (!rc) {
2614                 if (fdc)
2615                         jme_reset_link(jme);
2616                 jme->old_cmd = *cmd;
2617                 set_bit(JME_FLAG_SSET, &jme->flags);
2618         }
2619
2620         return rc;
2621 }
2622
2623 static int
2624 jme_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
2625 {
2626         int rc;
2627         struct jme_adapter *jme = netdev_priv(netdev);
2628         struct mii_ioctl_data *mii_data = if_mii(rq);
2629         unsigned int duplex_chg;
2630
2631         if (cmd == SIOCSMIIREG) {
2632                 u16 val = mii_data->val_in;
2633                 if (!(val & (BMCR_RESET|BMCR_ANENABLE)) &&
2634                     (val & BMCR_SPEED1000))
2635                         return -EINVAL;
2636         }
2637
2638         spin_lock_bh(&jme->phy_lock);
2639         rc = generic_mii_ioctl(&jme->mii_if, mii_data, cmd, &duplex_chg);
2640         spin_unlock_bh(&jme->phy_lock);
2641
2642         if (!rc && (cmd == SIOCSMIIREG)) {
2643                 if (duplex_chg)
2644                         jme_reset_link(jme);
2645                 jme_get_link_ksettings(netdev, &jme->old_cmd);
2646                 set_bit(JME_FLAG_SSET, &jme->flags);
2647         }
2648
2649         return rc;
2650 }
2651
2652 static u32
2653 jme_get_link(struct net_device *netdev)
2654 {
2655         struct jme_adapter *jme = netdev_priv(netdev);
2656         return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2657 }
2658
2659 static u32
2660 jme_get_msglevel(struct net_device *netdev)
2661 {
2662         struct jme_adapter *jme = netdev_priv(netdev);
2663         return jme->msg_enable;
2664 }
2665
2666 static void
2667 jme_set_msglevel(struct net_device *netdev, u32 value)
2668 {
2669         struct jme_adapter *jme = netdev_priv(netdev);
2670         jme->msg_enable = value;
2671 }
2672
2673 static netdev_features_t
2674 jme_fix_features(struct net_device *netdev, netdev_features_t features)
2675 {
2676         if (netdev->mtu > 1900)
2677                 features &= ~(NETIF_F_ALL_TSO | NETIF_F_CSUM_MASK);
2678         return features;
2679 }
2680
2681 static int
2682 jme_set_features(struct net_device *netdev, netdev_features_t features)
2683 {
2684         struct jme_adapter *jme = netdev_priv(netdev);
2685
2686         spin_lock_bh(&jme->rxmcs_lock);
2687         if (features & NETIF_F_RXCSUM)
2688                 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2689         else
2690                 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2691         jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2692         spin_unlock_bh(&jme->rxmcs_lock);
2693
2694         return 0;
2695 }
2696
2697 #ifdef CONFIG_NET_POLL_CONTROLLER
2698 static void jme_netpoll(struct net_device *dev)
2699 {
2700         unsigned long flags;
2701
2702         local_irq_save(flags);
2703         jme_intr(dev->irq, dev);
2704         local_irq_restore(flags);
2705 }
2706 #endif
2707
2708 static int
2709 jme_nway_reset(struct net_device *netdev)
2710 {
2711         struct jme_adapter *jme = netdev_priv(netdev);
2712         jme_restart_an(jme);
2713         return 0;
2714 }
2715
2716 static u8
2717 jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2718 {
2719         u32 val;
2720         int to;
2721
2722         val = jread32(jme, JME_SMBCSR);
2723         to = JME_SMB_BUSY_TIMEOUT;
2724         while ((val & SMBCSR_BUSY) && --to) {
2725                 msleep(1);
2726                 val = jread32(jme, JME_SMBCSR);
2727         }
2728         if (!to) {
2729                 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2730                 return 0xFF;
2731         }
2732
2733         jwrite32(jme, JME_SMBINTF,
2734                 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2735                 SMBINTF_HWRWN_READ |
2736                 SMBINTF_HWCMD);
2737
2738         val = jread32(jme, JME_SMBINTF);
2739         to = JME_SMB_BUSY_TIMEOUT;
2740         while ((val & SMBINTF_HWCMD) && --to) {
2741                 msleep(1);
2742                 val = jread32(jme, JME_SMBINTF);
2743         }
2744         if (!to) {
2745                 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2746                 return 0xFF;
2747         }
2748
2749         return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2750 }
2751
2752 static void
2753 jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2754 {
2755         u32 val;
2756         int to;
2757
2758         val = jread32(jme, JME_SMBCSR);
2759         to = JME_SMB_BUSY_TIMEOUT;
2760         while ((val & SMBCSR_BUSY) && --to) {
2761                 msleep(1);
2762                 val = jread32(jme, JME_SMBCSR);
2763         }
2764         if (!to) {
2765                 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2766                 return;
2767         }
2768
2769         jwrite32(jme, JME_SMBINTF,
2770                 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2771                 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2772                 SMBINTF_HWRWN_WRITE |
2773                 SMBINTF_HWCMD);
2774
2775         val = jread32(jme, JME_SMBINTF);
2776         to = JME_SMB_BUSY_TIMEOUT;
2777         while ((val & SMBINTF_HWCMD) && --to) {
2778                 msleep(1);
2779                 val = jread32(jme, JME_SMBINTF);
2780         }
2781         if (!to) {
2782                 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2783                 return;
2784         }
2785
2786         mdelay(2);
2787 }
2788
2789 static int
2790 jme_get_eeprom_len(struct net_device *netdev)
2791 {
2792         struct jme_adapter *jme = netdev_priv(netdev);
2793         u32 val;
2794         val = jread32(jme, JME_SMBCSR);
2795         return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
2796 }
2797
2798 static int
2799 jme_get_eeprom(struct net_device *netdev,
2800                 struct ethtool_eeprom *eeprom, u8 *data)
2801 {
2802         struct jme_adapter *jme = netdev_priv(netdev);
2803         int i, offset = eeprom->offset, len = eeprom->len;
2804
2805         /*
2806          * ethtool will check the boundary for us
2807          */
2808         eeprom->magic = JME_EEPROM_MAGIC;
2809         for (i = 0 ; i < len ; ++i)
2810                 data[i] = jme_smb_read(jme, i + offset);
2811
2812         return 0;
2813 }
2814
2815 static int
2816 jme_set_eeprom(struct net_device *netdev,
2817                 struct ethtool_eeprom *eeprom, u8 *data)
2818 {
2819         struct jme_adapter *jme = netdev_priv(netdev);
2820         int i, offset = eeprom->offset, len = eeprom->len;
2821
2822         if (eeprom->magic != JME_EEPROM_MAGIC)
2823                 return -EINVAL;
2824
2825         /*
2826          * ethtool will check the boundary for us
2827          */
2828         for (i = 0 ; i < len ; ++i)
2829                 jme_smb_write(jme, i + offset, data[i]);
2830
2831         return 0;
2832 }
2833
2834 static const struct ethtool_ops jme_ethtool_ops = {
2835         .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
2836                                      ETHTOOL_COALESCE_MAX_FRAMES |
2837                                      ETHTOOL_COALESCE_USE_ADAPTIVE_RX,
2838         .get_drvinfo            = jme_get_drvinfo,
2839         .get_regs_len           = jme_get_regs_len,
2840         .get_regs               = jme_get_regs,
2841         .get_coalesce           = jme_get_coalesce,
2842         .set_coalesce           = jme_set_coalesce,
2843         .get_pauseparam         = jme_get_pauseparam,
2844         .set_pauseparam         = jme_set_pauseparam,
2845         .get_wol                = jme_get_wol,
2846         .set_wol                = jme_set_wol,
2847         .get_link               = jme_get_link,
2848         .get_msglevel           = jme_get_msglevel,
2849         .set_msglevel           = jme_set_msglevel,
2850         .nway_reset             = jme_nway_reset,
2851         .get_eeprom_len         = jme_get_eeprom_len,
2852         .get_eeprom             = jme_get_eeprom,
2853         .set_eeprom             = jme_set_eeprom,
2854         .get_link_ksettings     = jme_get_link_ksettings,
2855         .set_link_ksettings     = jme_set_link_ksettings,
2856 };
2857
2858 static int
2859 jme_pci_dma64(struct pci_dev *pdev)
2860 {
2861         if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2862             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))
2863                 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
2864                         return 1;
2865
2866         if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2867             !pci_set_dma_mask(pdev, DMA_BIT_MASK(40)))
2868                 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
2869                         return 1;
2870
2871         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
2872                 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
2873                         return 0;
2874
2875         return -1;
2876 }
2877
2878 static inline void
2879 jme_phy_init(struct jme_adapter *jme)
2880 {
2881         u16 reg26;
2882
2883         reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2884         jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2885 }
2886
2887 static inline void
2888 jme_check_hw_ver(struct jme_adapter *jme)
2889 {
2890         u32 chipmode;
2891
2892         chipmode = jread32(jme, JME_CHIPMODE);
2893
2894         jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
2895         jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
2896         jme->chip_main_rev = jme->chiprev & 0xF;
2897         jme->chip_sub_rev = (jme->chiprev >> 4) & 0xF;
2898 }
2899
2900 static const struct net_device_ops jme_netdev_ops = {
2901         .ndo_open               = jme_open,
2902         .ndo_stop               = jme_close,
2903         .ndo_validate_addr      = eth_validate_addr,
2904         .ndo_do_ioctl           = jme_ioctl,
2905         .ndo_start_xmit         = jme_start_xmit,
2906         .ndo_set_mac_address    = jme_set_macaddr,
2907         .ndo_set_rx_mode        = jme_set_multi,
2908         .ndo_change_mtu         = jme_change_mtu,
2909         .ndo_tx_timeout         = jme_tx_timeout,
2910         .ndo_fix_features       = jme_fix_features,
2911         .ndo_set_features       = jme_set_features,
2912 #ifdef CONFIG_NET_POLL_CONTROLLER
2913         .ndo_poll_controller    = jme_netpoll,
2914 #endif
2915 };
2916
2917 static int
2918 jme_init_one(struct pci_dev *pdev,
2919              const struct pci_device_id *ent)
2920 {
2921         int rc = 0, using_dac, i;
2922         struct net_device *netdev;
2923         struct jme_adapter *jme;
2924         u16 bmcr, bmsr;
2925         u32 apmc;
2926
2927         /*
2928          * set up PCI device basics
2929          */
2930         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
2931                                PCIE_LINK_STATE_CLKPM);
2932
2933         rc = pci_enable_device(pdev);
2934         if (rc) {
2935                 pr_err("Cannot enable PCI device\n");
2936                 goto err_out;
2937         }
2938
2939         using_dac = jme_pci_dma64(pdev);
2940         if (using_dac < 0) {
2941                 pr_err("Cannot set PCI DMA Mask\n");
2942                 rc = -EIO;
2943                 goto err_out_disable_pdev;
2944         }
2945
2946         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2947                 pr_err("No PCI resource region found\n");
2948                 rc = -ENOMEM;
2949                 goto err_out_disable_pdev;
2950         }
2951
2952         rc = pci_request_regions(pdev, DRV_NAME);
2953         if (rc) {
2954                 pr_err("Cannot obtain PCI resource region\n");
2955                 goto err_out_disable_pdev;
2956         }
2957
2958         pci_set_master(pdev);
2959
2960         /*
2961          * alloc and init net device
2962          */
2963         netdev = alloc_etherdev(sizeof(*jme));
2964         if (!netdev) {
2965                 rc = -ENOMEM;
2966                 goto err_out_release_regions;
2967         }
2968         netdev->netdev_ops = &jme_netdev_ops;
2969         netdev->ethtool_ops             = &jme_ethtool_ops;
2970         netdev->watchdog_timeo          = TX_TIMEOUT;
2971         netdev->hw_features             =       NETIF_F_IP_CSUM |
2972                                                 NETIF_F_IPV6_CSUM |
2973                                                 NETIF_F_SG |
2974                                                 NETIF_F_TSO |
2975                                                 NETIF_F_TSO6 |
2976                                                 NETIF_F_RXCSUM;
2977         netdev->features                =       NETIF_F_IP_CSUM |
2978                                                 NETIF_F_IPV6_CSUM |
2979                                                 NETIF_F_SG |
2980                                                 NETIF_F_TSO |
2981                                                 NETIF_F_TSO6 |
2982                                                 NETIF_F_HW_VLAN_CTAG_TX |
2983                                                 NETIF_F_HW_VLAN_CTAG_RX;
2984         if (using_dac)
2985                 netdev->features        |=      NETIF_F_HIGHDMA;
2986
2987         /* MTU range: 1280 - 9202*/
2988         netdev->min_mtu = IPV6_MIN_MTU;
2989         netdev->max_mtu = MAX_ETHERNET_JUMBO_PACKET_SIZE - ETH_HLEN;
2990
2991         SET_NETDEV_DEV(netdev, &pdev->dev);
2992         pci_set_drvdata(pdev, netdev);
2993
2994         /*
2995          * init adapter info
2996          */
2997         jme = netdev_priv(netdev);
2998         jme->pdev = pdev;
2999         jme->dev = netdev;
3000         jme->jme_rx = netif_rx;
3001         jme->old_mtu = netdev->mtu = 1500;
3002         jme->phylink = 0;
3003         jme->tx_ring_size = 1 << 10;
3004         jme->tx_ring_mask = jme->tx_ring_size - 1;
3005         jme->tx_wake_threshold = 1 << 9;
3006         jme->rx_ring_size = 1 << 9;
3007         jme->rx_ring_mask = jme->rx_ring_size - 1;
3008         jme->msg_enable = JME_DEF_MSG_ENABLE;
3009         jme->regs = ioremap(pci_resource_start(pdev, 0),
3010                              pci_resource_len(pdev, 0));
3011         if (!(jme->regs)) {
3012                 pr_err("Mapping PCI resource region error\n");
3013                 rc = -ENOMEM;
3014                 goto err_out_free_netdev;
3015         }
3016
3017         if (no_pseudohp) {
3018                 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
3019                 jwrite32(jme, JME_APMC, apmc);
3020         } else if (force_pseudohp) {
3021                 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
3022                 jwrite32(jme, JME_APMC, apmc);
3023         }
3024
3025         NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, NAPI_POLL_WEIGHT)
3026
3027         spin_lock_init(&jme->phy_lock);
3028         spin_lock_init(&jme->macaddr_lock);
3029         spin_lock_init(&jme->rxmcs_lock);
3030
3031         atomic_set(&jme->link_changing, 1);
3032         atomic_set(&jme->rx_cleaning, 1);
3033         atomic_set(&jme->tx_cleaning, 1);
3034         atomic_set(&jme->rx_empty, 1);
3035
3036         tasklet_setup(&jme->pcc_task, jme_pcc_tasklet);
3037         INIT_WORK(&jme->linkch_task, jme_link_change_work);
3038         jme->dpi.cur = PCC_P1;
3039
3040         jme->reg_ghc = 0;
3041         jme->reg_rxcs = RXCS_DEFAULT;
3042         jme->reg_rxmcs = RXMCS_DEFAULT;
3043         jme->reg_txpfc = 0;
3044         jme->reg_pmcs = PMCS_MFEN;
3045         jme->reg_gpreg1 = GPREG1_DEFAULT;
3046
3047         if (jme->reg_rxmcs & RXMCS_CHECKSUM)
3048                 netdev->features |= NETIF_F_RXCSUM;
3049
3050         /*
3051          * Get Max Read Req Size from PCI Config Space
3052          */
3053         pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
3054         jme->mrrs &= PCI_DCSR_MRRS_MASK;
3055         switch (jme->mrrs) {
3056         case MRRS_128B:
3057                 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
3058                 break;
3059         case MRRS_256B:
3060                 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
3061                 break;
3062         default:
3063                 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
3064                 break;
3065         }
3066
3067         /*
3068          * Must check before reset_mac_processor
3069          */
3070         jme_check_hw_ver(jme);
3071         jme->mii_if.dev = netdev;
3072         if (jme->fpgaver) {
3073                 jme->mii_if.phy_id = 0;
3074                 for (i = 1 ; i < 32 ; ++i) {
3075                         bmcr = jme_mdio_read(netdev, i, MII_BMCR);
3076                         bmsr = jme_mdio_read(netdev, i, MII_BMSR);
3077                         if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
3078                                 jme->mii_if.phy_id = i;
3079                                 break;
3080                         }
3081                 }
3082
3083                 if (!jme->mii_if.phy_id) {
3084                         rc = -EIO;
3085                         pr_err("Can not find phy_id\n");
3086                         goto err_out_unmap;
3087                 }
3088
3089                 jme->reg_ghc |= GHC_LINK_POLL;
3090         } else {
3091                 jme->mii_if.phy_id = 1;
3092         }
3093         if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
3094                 jme->mii_if.supports_gmii = true;
3095         else
3096                 jme->mii_if.supports_gmii = false;
3097         jme->mii_if.phy_id_mask = 0x1F;
3098         jme->mii_if.reg_num_mask = 0x1F;
3099         jme->mii_if.mdio_read = jme_mdio_read;
3100         jme->mii_if.mdio_write = jme_mdio_write;
3101
3102         jme_clear_pm_disable_wol(jme);
3103         device_init_wakeup(&pdev->dev, true);
3104
3105         jme_set_phyfifo_5level(jme);
3106         jme->pcirev = pdev->revision;
3107         if (!jme->fpgaver)
3108                 jme_phy_init(jme);
3109         jme_phy_off(jme);
3110
3111         /*
3112          * Reset MAC processor and reload EEPROM for MAC Address
3113          */
3114         jme_reset_mac_processor(jme);
3115         rc = jme_reload_eeprom(jme);
3116         if (rc) {
3117                 pr_err("Reload eeprom for reading MAC Address error\n");
3118                 goto err_out_unmap;
3119         }
3120         jme_load_macaddr(netdev);
3121
3122         /*
3123          * Tell stack that we are not ready to work until open()
3124          */
3125         netif_carrier_off(netdev);
3126
3127         rc = register_netdev(netdev);
3128         if (rc) {
3129                 pr_err("Cannot register net device\n");
3130                 goto err_out_unmap;
3131         }
3132
3133         netif_info(jme, probe, jme->dev, "%s%s chiprev:%x pcirev:%x macaddr:%pM\n",
3134                    (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
3135                    "JMC250 Gigabit Ethernet" :
3136                    (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
3137                    "JMC260 Fast Ethernet" : "Unknown",
3138                    (jme->fpgaver != 0) ? " (FPGA)" : "",
3139                    (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
3140                    jme->pcirev, netdev->dev_addr);
3141
3142         return 0;
3143
3144 err_out_unmap:
3145         iounmap(jme->regs);
3146 err_out_free_netdev:
3147         free_netdev(netdev);
3148 err_out_release_regions:
3149         pci_release_regions(pdev);
3150 err_out_disable_pdev:
3151         pci_disable_device(pdev);
3152 err_out:
3153         return rc;
3154 }
3155
3156 static void
3157 jme_remove_one(struct pci_dev *pdev)
3158 {
3159         struct net_device *netdev = pci_get_drvdata(pdev);
3160         struct jme_adapter *jme = netdev_priv(netdev);
3161
3162         unregister_netdev(netdev);
3163         iounmap(jme->regs);
3164         free_netdev(netdev);
3165         pci_release_regions(pdev);
3166         pci_disable_device(pdev);
3167
3168 }
3169
3170 static void
3171 jme_shutdown(struct pci_dev *pdev)
3172 {
3173         struct net_device *netdev = pci_get_drvdata(pdev);
3174         struct jme_adapter *jme = netdev_priv(netdev);
3175
3176         jme_powersave_phy(jme);
3177         pci_pme_active(pdev, true);
3178 }
3179
3180 #ifdef CONFIG_PM_SLEEP
3181 static int
3182 jme_suspend(struct device *dev)
3183 {
3184         struct net_device *netdev = dev_get_drvdata(dev);
3185         struct jme_adapter *jme = netdev_priv(netdev);
3186
3187         if (!netif_running(netdev))
3188                 return 0;
3189
3190         atomic_dec(&jme->link_changing);
3191
3192         netif_device_detach(netdev);
3193         netif_stop_queue(netdev);
3194         jme_stop_irq(jme);
3195
3196         tasklet_disable(&jme->txclean_task);
3197         tasklet_disable(&jme->rxclean_task);
3198         tasklet_disable(&jme->rxempty_task);
3199
3200         if (netif_carrier_ok(netdev)) {
3201                 if (test_bit(JME_FLAG_POLL, &jme->flags))
3202                         jme_polling_mode(jme);
3203
3204                 jme_stop_pcc_timer(jme);
3205                 jme_disable_rx_engine(jme);
3206                 jme_disable_tx_engine(jme);
3207                 jme_reset_mac_processor(jme);
3208                 jme_free_rx_resources(jme);
3209                 jme_free_tx_resources(jme);
3210                 netif_carrier_off(netdev);
3211                 jme->phylink = 0;
3212         }
3213
3214         tasklet_enable(&jme->txclean_task);
3215         tasklet_enable(&jme->rxclean_task);
3216         tasklet_enable(&jme->rxempty_task);
3217
3218         jme_powersave_phy(jme);
3219
3220         return 0;
3221 }
3222
3223 static int
3224 jme_resume(struct device *dev)
3225 {
3226         struct net_device *netdev = dev_get_drvdata(dev);
3227         struct jme_adapter *jme = netdev_priv(netdev);
3228
3229         if (!netif_running(netdev))
3230                 return 0;
3231
3232         jme_clear_pm_disable_wol(jme);
3233         jme_phy_on(jme);
3234         if (test_bit(JME_FLAG_SSET, &jme->flags))
3235                 jme_set_link_ksettings(netdev, &jme->old_cmd);
3236         else
3237                 jme_reset_phy_processor(jme);
3238         jme_phy_calibration(jme);
3239         jme_phy_setEA(jme);
3240         netif_device_attach(netdev);
3241
3242         atomic_inc(&jme->link_changing);
3243
3244         jme_reset_link(jme);
3245
3246         jme_start_irq(jme);
3247
3248         return 0;
3249 }
3250
3251 static SIMPLE_DEV_PM_OPS(jme_pm_ops, jme_suspend, jme_resume);
3252 #define JME_PM_OPS (&jme_pm_ops)
3253
3254 #else
3255
3256 #define JME_PM_OPS NULL
3257 #endif
3258
3259 static const struct pci_device_id jme_pci_tbl[] = {
3260         { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3261         { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
3262         { }
3263 };
3264
3265 static struct pci_driver jme_driver = {
3266         .name           = DRV_NAME,
3267         .id_table       = jme_pci_tbl,
3268         .probe          = jme_init_one,
3269         .remove         = jme_remove_one,
3270         .shutdown       = jme_shutdown,
3271         .driver.pm      = JME_PM_OPS,
3272 };
3273
3274 static int __init
3275 jme_init_module(void)
3276 {
3277         pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION);
3278         return pci_register_driver(&jme_driver);
3279 }
3280
3281 static void __exit
3282 jme_cleanup_module(void)
3283 {
3284         pci_unregister_driver(&jme_driver);
3285 }
3286
3287 module_init(jme_init_module);
3288 module_exit(jme_cleanup_module);
3289
3290 MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3291 MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3292 MODULE_LICENSE("GPL");
3293 MODULE_VERSION(DRV_VERSION);
3294 MODULE_DEVICE_TABLE(pci, jme_pci_tbl);