1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2014 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
29 #include <linux/pci.h>
30 #include <linux/delay.h>
31 #include <linux/sched.h>
34 #include "ixgbe_phy.h"
35 #include "ixgbe_x540.h"
37 #define IXGBE_X540_MAX_TX_QUEUES 128
38 #define IXGBE_X540_MAX_RX_QUEUES 128
39 #define IXGBE_X540_RAR_ENTRIES 128
40 #define IXGBE_X540_MC_TBL_SIZE 128
41 #define IXGBE_X540_VFT_TBL_SIZE 128
42 #define IXGBE_X540_RX_PB_SIZE 384
44 static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw);
45 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);
46 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);
47 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);
49 enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)
51 return ixgbe_media_type_copper;
54 s32 ixgbe_get_invariants_X540(struct ixgbe_hw *hw)
56 struct ixgbe_mac_info *mac = &hw->mac;
58 mac->mcft_size = IXGBE_X540_MC_TBL_SIZE;
59 mac->vft_size = IXGBE_X540_VFT_TBL_SIZE;
60 mac->num_rar_entries = IXGBE_X540_RAR_ENTRIES;
61 mac->rx_pb_size = IXGBE_X540_RX_PB_SIZE;
62 mac->max_rx_queues = IXGBE_X540_MAX_RX_QUEUES;
63 mac->max_tx_queues = IXGBE_X540_MAX_TX_QUEUES;
64 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
70 * ixgbe_setup_mac_link_X540 - Set the auto advertised capabilitires
71 * @hw: pointer to hardware structure
72 * @speed: new link speed
73 * @autoneg_wait_to_complete: true when waiting for completion is needed
75 s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw, ixgbe_link_speed speed,
76 bool autoneg_wait_to_complete)
78 return hw->phy.ops.setup_link_speed(hw, speed,
79 autoneg_wait_to_complete);
83 * ixgbe_reset_hw_X540 - Perform hardware reset
84 * @hw: pointer to hardware structure
86 * Resets the hardware by resetting the transmit and receive units, masks
87 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
90 s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
95 /* Call adapter stop to disable tx/rx and clear interrupts */
96 status = hw->mac.ops.stop_adapter(hw);
100 /* flush pending Tx transactions */
101 ixgbe_clear_tx_pending(hw);
104 ctrl = IXGBE_CTRL_RST;
105 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
106 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
107 IXGBE_WRITE_FLUSH(hw);
109 /* Poll for reset bit to self-clear indicating reset is complete */
110 for (i = 0; i < 10; i++) {
112 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
113 if (!(ctrl & IXGBE_CTRL_RST_MASK))
117 if (ctrl & IXGBE_CTRL_RST_MASK) {
118 status = IXGBE_ERR_RESET_FAILED;
119 hw_dbg(hw, "Reset polling failed to complete.\n");
124 * Double resets are required for recovery from certain error
125 * conditions. Between resets, it is necessary to stall to allow time
126 * for any pending HW events to complete.
128 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
129 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
133 /* Set the Rx packet buffer size. */
134 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT);
136 /* Store the permanent mac address */
137 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
140 * Store MAC address from RAR0, clear receive address registers, and
141 * clear the multicast table. Also reset num_rar_entries to 128,
142 * since we modify this value when programming the SAN MAC address.
144 hw->mac.num_rar_entries = IXGBE_X540_MAX_TX_QUEUES;
145 hw->mac.ops.init_rx_addrs(hw);
147 /* Store the permanent SAN mac address */
148 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
150 /* Add the SAN MAC address to the RAR only if it's a valid address */
151 if (is_valid_ether_addr(hw->mac.san_addr)) {
152 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
153 hw->mac.san_addr, 0, IXGBE_RAH_AV);
155 /* Save the SAN MAC RAR index */
156 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
158 /* Reserve the last RAR for the SAN MAC address */
159 hw->mac.num_rar_entries--;
162 /* Store the alternative WWNN/WWPN prefix */
163 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
164 &hw->mac.wwpn_prefix);
170 * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx
171 * @hw: pointer to hardware structure
173 * Starts the hardware using the generic start_hw function
174 * and the generation start_hw function.
175 * Then performs revision-specific operations, if any.
177 s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw)
181 ret_val = ixgbe_start_hw_generic(hw);
185 return ixgbe_start_hw_gen2(hw);
189 * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params
190 * @hw: pointer to hardware structure
192 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
193 * ixgbe_hw struct in order to set up EEPROM access.
195 s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
197 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
201 if (eeprom->type == ixgbe_eeprom_uninitialized) {
202 eeprom->semaphore_delay = 10;
203 eeprom->type = ixgbe_flash;
205 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
206 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
207 IXGBE_EEC_SIZE_SHIFT);
208 eeprom->word_size = 1 << (eeprom_size +
209 IXGBE_EEPROM_WORD_SIZE_SHIFT);
211 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n",
212 eeprom->type, eeprom->word_size);
219 * ixgbe_read_eerd_X540- Read EEPROM word using EERD
220 * @hw: pointer to hardware structure
221 * @offset: offset of word in the EEPROM to read
222 * @data: word read from the EEPROM
224 * Reads a 16 bit word from the EEPROM using the EERD register.
226 static s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)
230 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
231 return IXGBE_ERR_SWFW_SYNC;
233 status = ixgbe_read_eerd_generic(hw, offset, data);
235 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
240 * ixgbe_read_eerd_buffer_X540 - Read EEPROM word(s) using EERD
241 * @hw: pointer to hardware structure
242 * @offset: offset of word in the EEPROM to read
243 * @words: number of words
244 * @data: word(s) read from the EEPROM
246 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
248 static s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,
249 u16 offset, u16 words, u16 *data)
253 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
254 return IXGBE_ERR_SWFW_SYNC;
256 status = ixgbe_read_eerd_buffer_generic(hw, offset, words, data);
258 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
263 * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR
264 * @hw: pointer to hardware structure
265 * @offset: offset of word in the EEPROM to write
266 * @data: word write to the EEPROM
268 * Write a 16 bit word to the EEPROM using the EEWR register.
270 static s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)
274 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
275 return IXGBE_ERR_SWFW_SYNC;
277 status = ixgbe_write_eewr_generic(hw, offset, data);
279 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
284 * ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR
285 * @hw: pointer to hardware structure
286 * @offset: offset of word in the EEPROM to write
287 * @words: number of words
288 * @data: word(s) write to the EEPROM
290 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
292 static s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,
293 u16 offset, u16 words, u16 *data)
297 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
298 return IXGBE_ERR_SWFW_SYNC;
300 status = ixgbe_write_eewr_buffer_generic(hw, offset, words, data);
302 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
307 * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum
309 * This function does not use synchronization for EERD and EEWR. It can
310 * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540.
312 * @hw: pointer to hardware structure
314 static s32 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)
322 u16 checksum_last_word = IXGBE_EEPROM_CHECKSUM;
323 u16 ptr_start = IXGBE_PCIE_ANALOG_PTR;
326 * Do not use hw->eeprom.ops.read because we do not want to take
327 * the synchronization semaphores here. Instead use
328 * ixgbe_read_eerd_generic
331 /* Include 0x0-0x3F in the checksum */
332 for (i = 0; i < checksum_last_word; i++) {
333 if (ixgbe_read_eerd_generic(hw, i, &word)) {
334 hw_dbg(hw, "EEPROM read failed\n");
335 return IXGBE_ERR_EEPROM;
341 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
342 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
344 for (i = ptr_start; i < IXGBE_FW_PTR; i++) {
345 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
348 if (ixgbe_read_eerd_generic(hw, i, &pointer)) {
349 hw_dbg(hw, "EEPROM read failed\n");
353 /* Skip pointer section if the pointer is invalid. */
354 if (pointer == 0xFFFF || pointer == 0 ||
355 pointer >= hw->eeprom.word_size)
358 if (ixgbe_read_eerd_generic(hw, pointer, &length)) {
359 hw_dbg(hw, "EEPROM read failed\n");
360 return IXGBE_ERR_EEPROM;
364 /* Skip pointer section if length is invalid. */
365 if (length == 0xFFFF || length == 0 ||
366 (pointer + length) >= hw->eeprom.word_size)
369 for (j = pointer + 1; j <= pointer + length; j++) {
370 if (ixgbe_read_eerd_generic(hw, j, &word)) {
371 hw_dbg(hw, "EEPROM read failed\n");
372 return IXGBE_ERR_EEPROM;
378 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
380 return (s32)checksum;
384 * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum
385 * @hw: pointer to hardware structure
386 * @checksum_val: calculated checksum
388 * Performs checksum calculation and validates the EEPROM checksum. If the
389 * caller does not need checksum_val, the value can be NULL.
391 static s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw,
396 u16 read_checksum = 0;
398 /* Read the first word from the EEPROM. If this times out or fails, do
399 * not continue or we could be in for a very long wait while every
402 status = hw->eeprom.ops.read(hw, 0, &checksum);
404 hw_dbg(hw, "EEPROM read failed\n");
408 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
409 return IXGBE_ERR_SWFW_SYNC;
411 status = hw->eeprom.ops.calc_checksum(hw);
415 checksum = (u16)(status & 0xffff);
417 /* Do not use hw->eeprom.ops.read because we do not want to take
418 * the synchronization semaphores twice here.
420 status = ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,
425 /* Verify read checksum from EEPROM is the same as
426 * calculated checksum
428 if (read_checksum != checksum) {
429 hw_dbg(hw, "Invalid EEPROM checksum");
430 status = IXGBE_ERR_EEPROM_CHECKSUM;
433 /* If the user cares, return the calculated checksum */
435 *checksum_val = checksum;
438 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
444 * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash
445 * @hw: pointer to hardware structure
447 * After writing EEPROM to shadow RAM using EEWR register, software calculates
448 * checksum and updates the EEPROM and instructs the hardware to update
451 static s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
456 /* Read the first word from the EEPROM. If this times out or fails, do
457 * not continue or we could be in for a very long wait while every
460 status = hw->eeprom.ops.read(hw, 0, &checksum);
462 hw_dbg(hw, "EEPROM read failed\n");
466 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
467 return IXGBE_ERR_SWFW_SYNC;
469 status = hw->eeprom.ops.calc_checksum(hw);
473 checksum = (u16)(status & 0xffff);
475 /* Do not use hw->eeprom.ops.write because we do not want to
476 * take the synchronization semaphores twice here.
478 status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM, checksum);
482 status = ixgbe_update_flash_X540(hw);
485 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
490 * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device
491 * @hw: pointer to hardware structure
493 * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy
494 * EEPROM from shadow RAM to the flash device.
496 static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
501 status = ixgbe_poll_flash_update_done_X540(hw);
502 if (status == IXGBE_ERR_EEPROM) {
503 hw_dbg(hw, "Flash update time out\n");
507 flup = IXGBE_READ_REG(hw, IXGBE_EEC(hw)) | IXGBE_EEC_FLUP;
508 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), flup);
510 status = ixgbe_poll_flash_update_done_X540(hw);
512 hw_dbg(hw, "Flash update complete\n");
514 hw_dbg(hw, "Flash update time out\n");
516 if (hw->revision_id == 0) {
517 flup = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
519 if (flup & IXGBE_EEC_SEC1VAL) {
520 flup |= IXGBE_EEC_FLUP;
521 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), flup);
524 status = ixgbe_poll_flash_update_done_X540(hw);
526 hw_dbg(hw, "Flash update complete\n");
528 hw_dbg(hw, "Flash update time out\n");
535 * ixgbe_poll_flash_update_done_X540 - Poll flash update status
536 * @hw: pointer to hardware structure
538 * Polls the FLUDONE (bit 26) of the EEC Register to determine when the
539 * flash update is done.
541 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)
546 for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) {
547 reg = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
548 if (reg & IXGBE_EEC_FLUDONE)
552 return IXGBE_ERR_EEPROM;
556 * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore
557 * @hw: pointer to hardware structure
558 * @mask: Mask to specify which semaphore to acquire
560 * Acquires the SWFW semaphore thought the SW_FW_SYNC register for
561 * the specified function (CSR, PHY0, PHY1, NVM, Flash)
563 s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
567 u32 fwmask = mask << 5;
572 if (swmask == IXGBE_GSSR_EEP_SM)
573 hwmask = IXGBE_GSSR_FLASH_SM;
575 for (i = 0; i < timeout; i++) {
577 * SW NVM semaphore bit is used for access to all
578 * SW_FW_SYNC bits (not just NVM)
580 if (ixgbe_get_swfw_sync_semaphore(hw))
581 return IXGBE_ERR_SWFW_SYNC;
583 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
584 if (!(swfw_sync & (fwmask | swmask | hwmask))) {
586 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swfw_sync);
587 ixgbe_release_swfw_sync_semaphore(hw);
591 * Firmware currently using resource (fwmask),
592 * hardware currently using resource (hwmask),
593 * or other software thread currently using
596 ixgbe_release_swfw_sync_semaphore(hw);
597 usleep_range(5000, 10000);
602 * If the resource is not released by the FW/HW the SW can assume that
603 * the FW/HW malfunctions. In that case the SW should sets the
604 * SW bit(s) of the requested resource(s) while ignoring the
605 * corresponding FW/HW bits in the SW_FW_SYNC register.
608 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
609 if (swfw_sync & (fwmask | hwmask)) {
610 if (ixgbe_get_swfw_sync_semaphore(hw))
611 return IXGBE_ERR_SWFW_SYNC;
614 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swfw_sync);
615 ixgbe_release_swfw_sync_semaphore(hw);
619 usleep_range(5000, 10000);
624 * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore
625 * @hw: pointer to hardware structure
626 * @mask: Mask to specify which semaphore to release
628 * Releases the SWFW semaphore through the SW_FW_SYNC register
629 * for the specified function (CSR, PHY0, PHY1, EVM, Flash)
631 void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
636 ixgbe_get_swfw_sync_semaphore(hw);
638 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
639 swfw_sync &= ~swmask;
640 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swfw_sync);
642 ixgbe_release_swfw_sync_semaphore(hw);
643 usleep_range(5000, 10000);
647 * ixgbe_get_swfw_sync_semaphore - Get hardware semaphore
648 * @hw: pointer to hardware structure
650 * Sets the hardware semaphores so SW/FW can gain control of shared resources
652 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)
658 /* Get SMBI software semaphore between device drivers first */
659 for (i = 0; i < timeout; i++) {
660 /* If the SMBI bit is 0 when we read it, then the bit will be
661 * set and we have the semaphore
663 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
664 if (!(swsm & IXGBE_SWSM_SMBI))
666 usleep_range(50, 100);
671 "Software semaphore SMBI between device drivers not granted.\n");
672 return IXGBE_ERR_EEPROM;
675 /* Now get the semaphore between SW/FW through the REGSMP bit */
676 for (i = 0; i < timeout; i++) {
677 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
678 if (!(swsm & IXGBE_SWFW_REGSMP))
681 usleep_range(50, 100);
684 return IXGBE_ERR_EEPROM;
688 * ixgbe_release_nvm_semaphore - Release hardware semaphore
689 * @hw: pointer to hardware structure
691 * This function clears hardware semaphore bits.
693 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw)
697 /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */
699 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
700 swsm &= ~IXGBE_SWFW_REGSMP;
701 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swsm);
703 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
704 swsm &= ~IXGBE_SWSM_SMBI;
705 IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm);
707 IXGBE_WRITE_FLUSH(hw);
711 * ixgbe_blink_led_start_X540 - Blink LED based on index.
712 * @hw: pointer to hardware structure
713 * @index: led number to blink
715 * Devices that implement the version 2 interface:
718 s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index)
722 ixgbe_link_speed speed;
726 * Link should be up in order for the blink bit in the LED control
727 * register to work. Force link and speed in the MAC if link is down.
728 * This will be reversed when we stop the blinking.
730 hw->mac.ops.check_link(hw, &speed, &link_up, false);
732 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
733 macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS;
734 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
736 /* Set the LED to LINK_UP + BLINK. */
737 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
738 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
739 ledctl_reg |= IXGBE_LED_BLINK(index);
740 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
741 IXGBE_WRITE_FLUSH(hw);
747 * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index.
748 * @hw: pointer to hardware structure
749 * @index: led number to stop blinking
751 * Devices that implement the version 2 interface:
754 s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index)
759 /* Restore the LED to its default value. */
760 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
761 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
762 ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
763 ledctl_reg &= ~IXGBE_LED_BLINK(index);
764 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
766 /* Unforce link and speed in the MAC. */
767 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
768 macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS);
769 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
770 IXGBE_WRITE_FLUSH(hw);
774 static struct ixgbe_mac_operations mac_ops_X540 = {
775 .init_hw = &ixgbe_init_hw_generic,
776 .reset_hw = &ixgbe_reset_hw_X540,
777 .start_hw = &ixgbe_start_hw_X540,
778 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
779 .get_media_type = &ixgbe_get_media_type_X540,
780 .enable_rx_dma = &ixgbe_enable_rx_dma_generic,
781 .get_mac_addr = &ixgbe_get_mac_addr_generic,
782 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic,
783 .get_device_caps = &ixgbe_get_device_caps_generic,
784 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic,
785 .stop_adapter = &ixgbe_stop_adapter_generic,
786 .get_bus_info = &ixgbe_get_bus_info_generic,
787 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
788 .read_analog_reg8 = NULL,
789 .write_analog_reg8 = NULL,
790 .setup_link = &ixgbe_setup_mac_link_X540,
791 .set_rxpba = &ixgbe_set_rxpba_generic,
792 .check_link = &ixgbe_check_mac_link_generic,
793 .get_link_capabilities = &ixgbe_get_copper_link_capabilities_generic,
794 .led_on = &ixgbe_led_on_generic,
795 .led_off = &ixgbe_led_off_generic,
796 .blink_led_start = &ixgbe_blink_led_start_X540,
797 .blink_led_stop = &ixgbe_blink_led_stop_X540,
798 .set_rar = &ixgbe_set_rar_generic,
799 .clear_rar = &ixgbe_clear_rar_generic,
800 .set_vmdq = &ixgbe_set_vmdq_generic,
801 .set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic,
802 .clear_vmdq = &ixgbe_clear_vmdq_generic,
803 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
804 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
805 .enable_mc = &ixgbe_enable_mc_generic,
806 .disable_mc = &ixgbe_disable_mc_generic,
807 .clear_vfta = &ixgbe_clear_vfta_generic,
808 .set_vfta = &ixgbe_set_vfta_generic,
809 .fc_enable = &ixgbe_fc_enable_generic,
810 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic,
811 .init_uta_tables = &ixgbe_init_uta_tables_generic,
813 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing,
814 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing,
815 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540,
816 .release_swfw_sync = &ixgbe_release_swfw_sync_X540,
817 .disable_rx_buff = &ixgbe_disable_rx_buff_generic,
818 .enable_rx_buff = &ixgbe_enable_rx_buff_generic,
819 .get_thermal_sensor_data = NULL,
820 .init_thermal_sensor_thresh = NULL,
821 .prot_autoc_read = &prot_autoc_read_generic,
822 .prot_autoc_write = &prot_autoc_write_generic,
823 .enable_rx = &ixgbe_enable_rx_generic,
824 .disable_rx = &ixgbe_disable_rx_generic,
827 static struct ixgbe_eeprom_operations eeprom_ops_X540 = {
828 .init_params = &ixgbe_init_eeprom_params_X540,
829 .read = &ixgbe_read_eerd_X540,
830 .read_buffer = &ixgbe_read_eerd_buffer_X540,
831 .write = &ixgbe_write_eewr_X540,
832 .write_buffer = &ixgbe_write_eewr_buffer_X540,
833 .calc_checksum = &ixgbe_calc_eeprom_checksum_X540,
834 .validate_checksum = &ixgbe_validate_eeprom_checksum_X540,
835 .update_checksum = &ixgbe_update_eeprom_checksum_X540,
838 static struct ixgbe_phy_operations phy_ops_X540 = {
839 .identify = &ixgbe_identify_phy_generic,
840 .identify_sfp = &ixgbe_identify_sfp_module_generic,
843 .read_reg = &ixgbe_read_phy_reg_generic,
844 .write_reg = &ixgbe_write_phy_reg_generic,
845 .setup_link = &ixgbe_setup_phy_link_generic,
846 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
847 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
848 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
849 .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic,
850 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
851 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
852 .check_overtemp = &ixgbe_tn_check_overtemp,
853 .set_phy_power = &ixgbe_set_copper_phy_power,
854 .get_firmware_version = &ixgbe_get_phy_firmware_version_generic,
857 static const u32 ixgbe_mvals_X540[IXGBE_MVALS_IDX_LIMIT] = {
858 IXGBE_MVALS_INIT(X540)
861 struct ixgbe_info ixgbe_X540_info = {
862 .mac = ixgbe_mac_X540,
863 .get_invariants = &ixgbe_get_invariants_X540,
864 .mac_ops = &mac_ops_X540,
865 .eeprom_ops = &eeprom_ops_X540,
866 .phy_ops = &phy_ops_X540,
867 .mbx_ops = &mbx_ops_generic,
868 .mvals = ixgbe_mvals_X540,