1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2013 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
35 #include <linux/interrupt.h>
37 #include <linux/tcp.h>
38 #include <linux/sctp.h>
39 #include <linux/pkt_sched.h>
40 #include <linux/ipv6.h>
41 #include <linux/slab.h>
42 #include <net/checksum.h>
43 #include <net/ip6_checksum.h>
44 #include <linux/ethtool.h>
46 #include <linux/if_vlan.h>
47 #include <linux/if_macvlan.h>
48 #include <linux/if_bridge.h>
49 #include <linux/prefetch.h>
50 #include <scsi/fc/fc_fcoe.h>
53 #include "ixgbe_common.h"
54 #include "ixgbe_dcb_82599.h"
55 #include "ixgbe_sriov.h"
57 char ixgbe_driver_name[] = "ixgbe";
58 static const char ixgbe_driver_string[] =
59 "Intel(R) 10 Gigabit PCI Express Network Driver";
61 char ixgbe_default_device_descr[] =
62 "Intel(R) 10 Gigabit Network Connection";
64 static char ixgbe_default_device_descr[] =
65 "Intel(R) 10 Gigabit Network Connection";
67 #define DRV_VERSION "3.15.1-k"
68 const char ixgbe_driver_version[] = DRV_VERSION;
69 static const char ixgbe_copyright[] =
70 "Copyright (c) 1999-2013 Intel Corporation.";
72 static const struct ixgbe_info *ixgbe_info_tbl[] = {
73 [board_82598] = &ixgbe_82598_info,
74 [board_82599] = &ixgbe_82599_info,
75 [board_X540] = &ixgbe_X540_info,
78 /* ixgbe_pci_tbl - PCI Device ID Table
80 * Wildcard entries (PCI_ANY_ID) should come last
81 * Last entry must be all 0s
83 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
84 * Class, Class Mask, private data (not used) }
86 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
117 /* required last entry */
120 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
122 #ifdef CONFIG_IXGBE_DCA
123 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
125 static struct notifier_block dca_notifier = {
126 .notifier_call = ixgbe_notify_dca,
132 #ifdef CONFIG_PCI_IOV
133 static unsigned int max_vfs;
134 module_param(max_vfs, uint, 0);
135 MODULE_PARM_DESC(max_vfs,
136 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)");
137 #endif /* CONFIG_PCI_IOV */
139 static unsigned int allow_unsupported_sfp;
140 module_param(allow_unsupported_sfp, uint, 0);
141 MODULE_PARM_DESC(allow_unsupported_sfp,
142 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
144 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
145 static int debug = -1;
146 module_param(debug, int, 0);
147 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
149 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
150 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
151 MODULE_LICENSE("GPL");
152 MODULE_VERSION(DRV_VERSION);
154 static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter,
157 struct pci_dev *parent_dev;
158 struct pci_bus *parent_bus;
160 parent_bus = adapter->pdev->bus->parent;
164 parent_dev = parent_bus->self;
168 if (!pci_is_pcie(parent_dev))
171 pcie_capability_read_word(parent_dev, reg, value);
175 static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter)
177 struct ixgbe_hw *hw = &adapter->hw;
181 hw->bus.type = ixgbe_bus_type_pci_express;
183 /* Get the negotiated link width and speed from PCI config space of the
184 * parent, as this device is behind a switch
186 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status);
188 /* assume caller will handle error case */
192 hw->bus.width = ixgbe_convert_bus_width(link_status);
193 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
199 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent
200 * @hw: hw specific details
202 * This function is used by probe to determine whether a device's PCI-Express
203 * bandwidth details should be gathered from the parent bus instead of from the
204 * device. Used to ensure that various locations all have the correct device ID
207 static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw)
209 switch (hw->device_id) {
210 case IXGBE_DEV_ID_82599_SFP_SF_QP:
211 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
218 static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter,
222 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
223 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
224 struct pci_dev *pdev;
226 /* determine whether to use the the parent device
228 if (ixgbe_pcie_from_parent(&adapter->hw))
229 pdev = adapter->pdev->bus->parent->self;
231 pdev = adapter->pdev;
233 if (pcie_get_minimum_link(pdev, &speed, &width) ||
234 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) {
235 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
240 case PCIE_SPEED_2_5GT:
241 /* 8b/10b encoding reduces max throughput by 20% */
244 case PCIE_SPEED_5_0GT:
245 /* 8b/10b encoding reduces max throughput by 20% */
248 case PCIE_SPEED_8_0GT:
249 /* 128b/130b encoding reduces throughput by less than 2% */
253 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
257 e_dev_info("PCI Express bandwidth of %dGT/s available\n",
259 e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n",
260 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
261 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
262 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
265 (speed == PCIE_SPEED_2_5GT ? "20%" :
266 speed == PCIE_SPEED_5_0GT ? "20%" :
267 speed == PCIE_SPEED_8_0GT ? "<2%" :
270 if (max_gts < expected_gts) {
271 e_dev_warn("This is not sufficient for optimal performance of this card.\n");
272 e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n",
274 e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n");
278 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
280 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
281 !test_bit(__IXGBE_REMOVING, &adapter->state) &&
282 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
283 schedule_work(&adapter->service_task);
286 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
288 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
290 /* flush memory to make sure state is correct before next watchdog */
291 smp_mb__before_clear_bit();
292 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
295 struct ixgbe_reg_info {
300 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
302 /* General Registers */
303 {IXGBE_CTRL, "CTRL"},
304 {IXGBE_STATUS, "STATUS"},
305 {IXGBE_CTRL_EXT, "CTRL_EXT"},
307 /* Interrupt Registers */
308 {IXGBE_EICR, "EICR"},
311 {IXGBE_SRRCTL(0), "SRRCTL"},
312 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
313 {IXGBE_RDLEN(0), "RDLEN"},
314 {IXGBE_RDH(0), "RDH"},
315 {IXGBE_RDT(0), "RDT"},
316 {IXGBE_RXDCTL(0), "RXDCTL"},
317 {IXGBE_RDBAL(0), "RDBAL"},
318 {IXGBE_RDBAH(0), "RDBAH"},
321 {IXGBE_TDBAL(0), "TDBAL"},
322 {IXGBE_TDBAH(0), "TDBAH"},
323 {IXGBE_TDLEN(0), "TDLEN"},
324 {IXGBE_TDH(0), "TDH"},
325 {IXGBE_TDT(0), "TDT"},
326 {IXGBE_TXDCTL(0), "TXDCTL"},
328 /* List Terminator */
334 * ixgbe_regdump - register printout routine
336 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
342 switch (reginfo->ofs) {
343 case IXGBE_SRRCTL(0):
344 for (i = 0; i < 64; i++)
345 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
347 case IXGBE_DCA_RXCTRL(0):
348 for (i = 0; i < 64; i++)
349 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
352 for (i = 0; i < 64; i++)
353 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
356 for (i = 0; i < 64; i++)
357 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
360 for (i = 0; i < 64; i++)
361 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
363 case IXGBE_RXDCTL(0):
364 for (i = 0; i < 64; i++)
365 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
368 for (i = 0; i < 64; i++)
369 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
372 for (i = 0; i < 64; i++)
373 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
376 for (i = 0; i < 64; i++)
377 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
380 for (i = 0; i < 64; i++)
381 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
384 for (i = 0; i < 64; i++)
385 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
388 for (i = 0; i < 64; i++)
389 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
392 for (i = 0; i < 64; i++)
393 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
395 case IXGBE_TXDCTL(0):
396 for (i = 0; i < 64; i++)
397 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
400 pr_info("%-15s %08x\n", reginfo->name,
401 IXGBE_READ_REG(hw, reginfo->ofs));
405 for (i = 0; i < 8; i++) {
406 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
407 pr_err("%-15s", rname);
408 for (j = 0; j < 8; j++)
409 pr_cont(" %08x", regs[i*8+j]);
416 * ixgbe_dump - Print registers, tx-rings and rx-rings
418 static void ixgbe_dump(struct ixgbe_adapter *adapter)
420 struct net_device *netdev = adapter->netdev;
421 struct ixgbe_hw *hw = &adapter->hw;
422 struct ixgbe_reg_info *reginfo;
424 struct ixgbe_ring *tx_ring;
425 struct ixgbe_tx_buffer *tx_buffer;
426 union ixgbe_adv_tx_desc *tx_desc;
427 struct my_u0 { u64 a; u64 b; } *u0;
428 struct ixgbe_ring *rx_ring;
429 union ixgbe_adv_rx_desc *rx_desc;
430 struct ixgbe_rx_buffer *rx_buffer_info;
434 if (!netif_msg_hw(adapter))
437 /* Print netdevice Info */
439 dev_info(&adapter->pdev->dev, "Net device Info\n");
440 pr_info("Device Name state "
441 "trans_start last_rx\n");
442 pr_info("%-15s %016lX %016lX %016lX\n",
449 /* Print Registers */
450 dev_info(&adapter->pdev->dev, "Register Dump\n");
451 pr_info(" Register Name Value\n");
452 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
453 reginfo->name; reginfo++) {
454 ixgbe_regdump(hw, reginfo);
457 /* Print TX Ring Summary */
458 if (!netdev || !netif_running(netdev))
461 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
462 pr_info(" %s %s %s %s\n",
463 "Queue [NTU] [NTC] [bi(ntc)->dma ]",
464 "leng", "ntw", "timestamp");
465 for (n = 0; n < adapter->num_tx_queues; n++) {
466 tx_ring = adapter->tx_ring[n];
467 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
468 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
469 n, tx_ring->next_to_use, tx_ring->next_to_clean,
470 (u64)dma_unmap_addr(tx_buffer, dma),
471 dma_unmap_len(tx_buffer, len),
472 tx_buffer->next_to_watch,
473 (u64)tx_buffer->time_stamp);
477 if (!netif_msg_tx_done(adapter))
478 goto rx_ring_summary;
480 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
482 /* Transmit Descriptor Formats
484 * 82598 Advanced Transmit Descriptor
485 * +--------------------------------------------------------------+
486 * 0 | Buffer Address [63:0] |
487 * +--------------------------------------------------------------+
488 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
489 * +--------------------------------------------------------------+
490 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
492 * 82598 Advanced Transmit Descriptor (Write-Back Format)
493 * +--------------------------------------------------------------+
495 * +--------------------------------------------------------------+
496 * 8 | RSV | STA | NXTSEQ |
497 * +--------------------------------------------------------------+
500 * 82599+ Advanced Transmit Descriptor
501 * +--------------------------------------------------------------+
502 * 0 | Buffer Address [63:0] |
503 * +--------------------------------------------------------------+
504 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
505 * +--------------------------------------------------------------+
506 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
508 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
509 * +--------------------------------------------------------------+
511 * +--------------------------------------------------------------+
512 * 8 | RSV | STA | RSV |
513 * +--------------------------------------------------------------+
517 for (n = 0; n < adapter->num_tx_queues; n++) {
518 tx_ring = adapter->tx_ring[n];
519 pr_info("------------------------------------\n");
520 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
521 pr_info("------------------------------------\n");
522 pr_info("%s%s %s %s %s %s\n",
523 "T [desc] [address 63:0 ] ",
524 "[PlPOIdStDDt Ln] [bi->dma ] ",
525 "leng", "ntw", "timestamp", "bi->skb");
527 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
528 tx_desc = IXGBE_TX_DESC(tx_ring, i);
529 tx_buffer = &tx_ring->tx_buffer_info[i];
530 u0 = (struct my_u0 *)tx_desc;
531 if (dma_unmap_len(tx_buffer, len) > 0) {
532 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p",
536 (u64)dma_unmap_addr(tx_buffer, dma),
537 dma_unmap_len(tx_buffer, len),
538 tx_buffer->next_to_watch,
539 (u64)tx_buffer->time_stamp,
541 if (i == tx_ring->next_to_use &&
542 i == tx_ring->next_to_clean)
544 else if (i == tx_ring->next_to_use)
546 else if (i == tx_ring->next_to_clean)
551 if (netif_msg_pktdata(adapter) &&
553 print_hex_dump(KERN_INFO, "",
554 DUMP_PREFIX_ADDRESS, 16, 1,
555 tx_buffer->skb->data,
556 dma_unmap_len(tx_buffer, len),
562 /* Print RX Rings Summary */
564 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
565 pr_info("Queue [NTU] [NTC]\n");
566 for (n = 0; n < adapter->num_rx_queues; n++) {
567 rx_ring = adapter->rx_ring[n];
568 pr_info("%5d %5X %5X\n",
569 n, rx_ring->next_to_use, rx_ring->next_to_clean);
573 if (!netif_msg_rx_status(adapter))
576 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
578 /* Receive Descriptor Formats
580 * 82598 Advanced Receive Descriptor (Read) Format
582 * +-----------------------------------------------------+
583 * 0 | Packet Buffer Address [63:1] |A0/NSE|
584 * +----------------------------------------------+------+
585 * 8 | Header Buffer Address [63:1] | DD |
586 * +-----------------------------------------------------+
589 * 82598 Advanced Receive Descriptor (Write-Back) Format
591 * 63 48 47 32 31 30 21 20 16 15 4 3 0
592 * +------------------------------------------------------+
593 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
594 * | Packet | IP | | | | Type | Type |
595 * | Checksum | Ident | | | | | |
596 * +------------------------------------------------------+
597 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
598 * +------------------------------------------------------+
599 * 63 48 47 32 31 20 19 0
601 * 82599+ Advanced Receive Descriptor (Read) Format
603 * +-----------------------------------------------------+
604 * 0 | Packet Buffer Address [63:1] |A0/NSE|
605 * +----------------------------------------------+------+
606 * 8 | Header Buffer Address [63:1] | DD |
607 * +-----------------------------------------------------+
610 * 82599+ Advanced Receive Descriptor (Write-Back) Format
612 * 63 48 47 32 31 30 21 20 17 16 4 3 0
613 * +------------------------------------------------------+
614 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
615 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
616 * |/ Flow Dir Flt ID | | | | | |
617 * +------------------------------------------------------+
618 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
619 * +------------------------------------------------------+
620 * 63 48 47 32 31 20 19 0
623 for (n = 0; n < adapter->num_rx_queues; n++) {
624 rx_ring = adapter->rx_ring[n];
625 pr_info("------------------------------------\n");
626 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
627 pr_info("------------------------------------\n");
629 "R [desc] [ PktBuf A0] ",
630 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ",
631 "<-- Adv Rx Read format\n");
633 "RWB[desc] [PcsmIpSHl PtRs] ",
634 "[vl er S cks ln] ---------------- [bi->skb ] ",
635 "<-- Adv Rx Write-Back format\n");
637 for (i = 0; i < rx_ring->count; i++) {
638 rx_buffer_info = &rx_ring->rx_buffer_info[i];
639 rx_desc = IXGBE_RX_DESC(rx_ring, i);
640 u0 = (struct my_u0 *)rx_desc;
641 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
642 if (staterr & IXGBE_RXD_STAT_DD) {
643 /* Descriptor Done */
644 pr_info("RWB[0x%03X] %016llX "
645 "%016llX ---------------- %p", i,
648 rx_buffer_info->skb);
650 pr_info("R [0x%03X] %016llX "
651 "%016llX %016llX %p", i,
654 (u64)rx_buffer_info->dma,
655 rx_buffer_info->skb);
657 if (netif_msg_pktdata(adapter) &&
658 rx_buffer_info->dma) {
659 print_hex_dump(KERN_INFO, "",
660 DUMP_PREFIX_ADDRESS, 16, 1,
661 page_address(rx_buffer_info->page) +
662 rx_buffer_info->page_offset,
663 ixgbe_rx_bufsz(rx_ring), true);
667 if (i == rx_ring->next_to_use)
669 else if (i == rx_ring->next_to_clean)
681 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
685 /* Let firmware take over control of h/w */
686 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
687 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
688 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
691 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
695 /* Let firmware know the driver has taken over */
696 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
697 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
698 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
702 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
703 * @adapter: pointer to adapter struct
704 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
705 * @queue: queue to map the corresponding interrupt to
706 * @msix_vector: the vector to map to the corresponding queue
709 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
710 u8 queue, u8 msix_vector)
713 struct ixgbe_hw *hw = &adapter->hw;
714 switch (hw->mac.type) {
715 case ixgbe_mac_82598EB:
716 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
719 index = (((direction * 64) + queue) >> 2) & 0x1F;
720 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
721 ivar &= ~(0xFF << (8 * (queue & 0x3)));
722 ivar |= (msix_vector << (8 * (queue & 0x3)));
723 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
725 case ixgbe_mac_82599EB:
727 if (direction == -1) {
729 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
730 index = ((queue & 1) * 8);
731 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
732 ivar &= ~(0xFF << index);
733 ivar |= (msix_vector << index);
734 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
737 /* tx or rx causes */
738 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
739 index = ((16 * (queue & 1)) + (8 * direction));
740 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
741 ivar &= ~(0xFF << index);
742 ivar |= (msix_vector << index);
743 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
751 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
756 switch (adapter->hw.mac.type) {
757 case ixgbe_mac_82598EB:
758 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
759 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
761 case ixgbe_mac_82599EB:
763 mask = (qmask & 0xFFFFFFFF);
764 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
765 mask = (qmask >> 32);
766 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
773 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
774 struct ixgbe_tx_buffer *tx_buffer)
776 if (tx_buffer->skb) {
777 dev_kfree_skb_any(tx_buffer->skb);
778 if (dma_unmap_len(tx_buffer, len))
779 dma_unmap_single(ring->dev,
780 dma_unmap_addr(tx_buffer, dma),
781 dma_unmap_len(tx_buffer, len),
783 } else if (dma_unmap_len(tx_buffer, len)) {
784 dma_unmap_page(ring->dev,
785 dma_unmap_addr(tx_buffer, dma),
786 dma_unmap_len(tx_buffer, len),
789 tx_buffer->next_to_watch = NULL;
790 tx_buffer->skb = NULL;
791 dma_unmap_len_set(tx_buffer, len, 0);
792 /* tx_buffer must be completely set up in the transmit path */
795 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
797 struct ixgbe_hw *hw = &adapter->hw;
798 struct ixgbe_hw_stats *hwstats = &adapter->stats;
802 if ((hw->fc.current_mode != ixgbe_fc_full) &&
803 (hw->fc.current_mode != ixgbe_fc_rx_pause))
806 switch (hw->mac.type) {
807 case ixgbe_mac_82598EB:
808 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
811 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
813 hwstats->lxoffrxc += data;
815 /* refill credits (no tx hang) if we received xoff */
819 for (i = 0; i < adapter->num_tx_queues; i++)
820 clear_bit(__IXGBE_HANG_CHECK_ARMED,
821 &adapter->tx_ring[i]->state);
824 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
826 struct ixgbe_hw *hw = &adapter->hw;
827 struct ixgbe_hw_stats *hwstats = &adapter->stats;
831 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
833 if (adapter->ixgbe_ieee_pfc)
834 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
836 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
837 ixgbe_update_xoff_rx_lfc(adapter);
841 /* update stats for each tc, only valid with PFC enabled */
842 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
845 switch (hw->mac.type) {
846 case ixgbe_mac_82598EB:
847 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
850 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
852 hwstats->pxoffrxc[i] += pxoffrxc;
853 /* Get the TC for given UP */
854 tc = netdev_get_prio_tc_map(adapter->netdev, i);
855 xoff[tc] += pxoffrxc;
858 /* disarm tx queues that have received xoff frames */
859 for (i = 0; i < adapter->num_tx_queues; i++) {
860 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
862 tc = tx_ring->dcb_tc;
864 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
868 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
870 return ring->stats.packets;
873 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
875 struct ixgbe_adapter *adapter;
879 if (ring->l2_accel_priv)
880 adapter = ring->l2_accel_priv->real_adapter;
882 adapter = netdev_priv(ring->netdev);
885 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
886 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
889 return (head < tail) ?
890 tail - head : (tail + ring->count - head);
895 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
897 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
898 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
899 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
902 clear_check_for_tx_hang(tx_ring);
905 * Check for a hung queue, but be thorough. This verifies
906 * that a transmit has been completed since the previous
907 * check AND there is at least one packet pending. The
908 * ARMED bit is set to indicate a potential hang. The
909 * bit is cleared if a pause frame is received to remove
910 * false hang detection due to PFC or 802.3x frames. By
911 * requiring this to fail twice we avoid races with
912 * pfc clearing the ARMED bit and conditions where we
913 * run the check_tx_hang logic with a transmit completion
914 * pending but without time to complete it yet.
916 if ((tx_done_old == tx_done) && tx_pending) {
917 /* make sure it is true for two checks in a row */
918 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
921 /* update completed stats and continue */
922 tx_ring->tx_stats.tx_done_old = tx_done;
923 /* reset the countdown */
924 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
931 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
932 * @adapter: driver private struct
934 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
937 /* Do the reset outside of interrupt context */
938 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
939 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
940 e_warn(drv, "initiating reset due to tx timeout\n");
941 ixgbe_service_event_schedule(adapter);
946 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
947 * @q_vector: structure containing interrupt and ring information
948 * @tx_ring: tx ring to clean
950 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
951 struct ixgbe_ring *tx_ring)
953 struct ixgbe_adapter *adapter = q_vector->adapter;
954 struct ixgbe_tx_buffer *tx_buffer;
955 union ixgbe_adv_tx_desc *tx_desc;
956 unsigned int total_bytes = 0, total_packets = 0;
957 unsigned int budget = q_vector->tx.work_limit;
958 unsigned int i = tx_ring->next_to_clean;
960 if (test_bit(__IXGBE_DOWN, &adapter->state))
963 tx_buffer = &tx_ring->tx_buffer_info[i];
964 tx_desc = IXGBE_TX_DESC(tx_ring, i);
968 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
970 /* if next_to_watch is not set then there is no work pending */
974 /* prevent any other reads prior to eop_desc */
975 read_barrier_depends();
977 /* if DD is not set pending work has not been completed */
978 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
981 /* clear next_to_watch to prevent false hangs */
982 tx_buffer->next_to_watch = NULL;
984 /* update the statistics for this packet */
985 total_bytes += tx_buffer->bytecount;
986 total_packets += tx_buffer->gso_segs;
989 dev_kfree_skb_any(tx_buffer->skb);
991 /* unmap skb header data */
992 dma_unmap_single(tx_ring->dev,
993 dma_unmap_addr(tx_buffer, dma),
994 dma_unmap_len(tx_buffer, len),
997 /* clear tx_buffer data */
998 tx_buffer->skb = NULL;
999 dma_unmap_len_set(tx_buffer, len, 0);
1001 /* unmap remaining buffers */
1002 while (tx_desc != eop_desc) {
1007 i -= tx_ring->count;
1008 tx_buffer = tx_ring->tx_buffer_info;
1009 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1012 /* unmap any remaining paged data */
1013 if (dma_unmap_len(tx_buffer, len)) {
1014 dma_unmap_page(tx_ring->dev,
1015 dma_unmap_addr(tx_buffer, dma),
1016 dma_unmap_len(tx_buffer, len),
1018 dma_unmap_len_set(tx_buffer, len, 0);
1022 /* move us one more past the eop_desc for start of next pkt */
1027 i -= tx_ring->count;
1028 tx_buffer = tx_ring->tx_buffer_info;
1029 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1032 /* issue prefetch for next Tx descriptor */
1035 /* update budget accounting */
1037 } while (likely(budget));
1039 i += tx_ring->count;
1040 tx_ring->next_to_clean = i;
1041 u64_stats_update_begin(&tx_ring->syncp);
1042 tx_ring->stats.bytes += total_bytes;
1043 tx_ring->stats.packets += total_packets;
1044 u64_stats_update_end(&tx_ring->syncp);
1045 q_vector->tx.total_bytes += total_bytes;
1046 q_vector->tx.total_packets += total_packets;
1048 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
1049 /* schedule immediate reset if we believe we hung */
1050 struct ixgbe_hw *hw = &adapter->hw;
1051 e_err(drv, "Detected Tx Unit Hang\n"
1053 " TDH, TDT <%x>, <%x>\n"
1054 " next_to_use <%x>\n"
1055 " next_to_clean <%x>\n"
1056 "tx_buffer_info[next_to_clean]\n"
1057 " time_stamp <%lx>\n"
1059 tx_ring->queue_index,
1060 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
1061 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
1062 tx_ring->next_to_use, i,
1063 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
1065 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1068 "tx hang %d detected on queue %d, resetting adapter\n",
1069 adapter->tx_timeout_count + 1, tx_ring->queue_index);
1071 /* schedule immediate reset if we believe we hung */
1072 ixgbe_tx_timeout_reset(adapter);
1074 /* the adapter is about to reset, no point in enabling stuff */
1078 netdev_tx_completed_queue(txring_txq(tx_ring),
1079 total_packets, total_bytes);
1081 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
1082 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
1083 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
1084 /* Make sure that anybody stopping the queue after this
1085 * sees the new next_to_clean.
1088 if (__netif_subqueue_stopped(tx_ring->netdev,
1089 tx_ring->queue_index)
1090 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
1091 netif_wake_subqueue(tx_ring->netdev,
1092 tx_ring->queue_index);
1093 ++tx_ring->tx_stats.restart_queue;
1100 #ifdef CONFIG_IXGBE_DCA
1101 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
1102 struct ixgbe_ring *tx_ring,
1105 struct ixgbe_hw *hw = &adapter->hw;
1106 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
1109 switch (hw->mac.type) {
1110 case ixgbe_mac_82598EB:
1111 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
1113 case ixgbe_mac_82599EB:
1114 case ixgbe_mac_X540:
1115 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
1116 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
1119 /* for unknown hardware do not write register */
1124 * We can enable relaxed ordering for reads, but not writes when
1125 * DCA is enabled. This is due to a known issue in some chipsets
1126 * which will cause the DCA tag to be cleared.
1128 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
1129 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
1130 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1132 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
1135 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1136 struct ixgbe_ring *rx_ring,
1139 struct ixgbe_hw *hw = &adapter->hw;
1140 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
1141 u8 reg_idx = rx_ring->reg_idx;
1144 switch (hw->mac.type) {
1145 case ixgbe_mac_82599EB:
1146 case ixgbe_mac_X540:
1147 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
1154 * We can enable relaxed ordering for reads, but not writes when
1155 * DCA is enabled. This is due to a known issue in some chipsets
1156 * which will cause the DCA tag to be cleared.
1158 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
1159 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1161 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
1164 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1166 struct ixgbe_adapter *adapter = q_vector->adapter;
1167 struct ixgbe_ring *ring;
1168 int cpu = get_cpu();
1170 if (q_vector->cpu == cpu)
1173 ixgbe_for_each_ring(ring, q_vector->tx)
1174 ixgbe_update_tx_dca(adapter, ring, cpu);
1176 ixgbe_for_each_ring(ring, q_vector->rx)
1177 ixgbe_update_rx_dca(adapter, ring, cpu);
1179 q_vector->cpu = cpu;
1184 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1188 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1191 /* always use CB2 mode, difference is masked in the CB driver */
1192 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1194 for (i = 0; i < adapter->num_q_vectors; i++) {
1195 adapter->q_vector[i]->cpu = -1;
1196 ixgbe_update_dca(adapter->q_vector[i]);
1200 static int __ixgbe_notify_dca(struct device *dev, void *data)
1202 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1203 unsigned long event = *(unsigned long *)data;
1205 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
1209 case DCA_PROVIDER_ADD:
1210 /* if we're already enabled, don't do it again */
1211 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1213 if (dca_add_requester(dev) == 0) {
1214 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1215 ixgbe_setup_dca(adapter);
1218 /* Fall Through since DCA is disabled. */
1219 case DCA_PROVIDER_REMOVE:
1220 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1221 dca_remove_requester(dev);
1222 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1223 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1231 #endif /* CONFIG_IXGBE_DCA */
1232 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1233 union ixgbe_adv_rx_desc *rx_desc,
1234 struct sk_buff *skb)
1236 if (ring->netdev->features & NETIF_F_RXHASH)
1237 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
1242 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1243 * @ring: structure containing ring specific data
1244 * @rx_desc: advanced rx descriptor
1246 * Returns : true if it is FCoE pkt
1248 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
1249 union ixgbe_adv_rx_desc *rx_desc)
1251 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1253 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
1254 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1255 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1256 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1259 #endif /* IXGBE_FCOE */
1261 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1262 * @ring: structure containing ring specific data
1263 * @rx_desc: current Rx descriptor being processed
1264 * @skb: skb currently being received and modified
1266 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
1267 union ixgbe_adv_rx_desc *rx_desc,
1268 struct sk_buff *skb)
1270 skb_checksum_none_assert(skb);
1272 /* Rx csum disabled */
1273 if (!(ring->netdev->features & NETIF_F_RXCSUM))
1276 /* if IP and error */
1277 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1278 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
1279 ring->rx_stats.csum_err++;
1283 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
1286 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
1287 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1290 * 82599 errata, UDP frames with a 0 checksum can be marked as
1293 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1294 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
1297 ring->rx_stats.csum_err++;
1301 /* It must be a TCP or UDP packet with a valid checksum */
1302 skb->ip_summed = CHECKSUM_UNNECESSARY;
1305 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1307 rx_ring->next_to_use = val;
1309 /* update next to alloc since we have filled the ring */
1310 rx_ring->next_to_alloc = val;
1312 * Force memory writes to complete before letting h/w
1313 * know there are new descriptors to fetch. (Only
1314 * applicable for weak-ordered memory model archs,
1318 writel(val, rx_ring->tail);
1321 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1322 struct ixgbe_rx_buffer *bi)
1324 struct page *page = bi->page;
1325 dma_addr_t dma = bi->dma;
1327 /* since we are recycling buffers we should seldom need to alloc */
1331 /* alloc new page for storage */
1332 if (likely(!page)) {
1333 page = __skb_alloc_pages(GFP_ATOMIC | __GFP_COLD | __GFP_COMP,
1334 bi->skb, ixgbe_rx_pg_order(rx_ring));
1335 if (unlikely(!page)) {
1336 rx_ring->rx_stats.alloc_rx_page_failed++;
1342 /* map page for use */
1343 dma = dma_map_page(rx_ring->dev, page, 0,
1344 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1347 * if mapping failed free memory back to system since
1348 * there isn't much point in holding memory we can't use
1350 if (dma_mapping_error(rx_ring->dev, dma)) {
1351 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
1354 rx_ring->rx_stats.alloc_rx_page_failed++;
1359 bi->page_offset = 0;
1365 * ixgbe_alloc_rx_buffers - Replace used receive buffers
1366 * @rx_ring: ring to place buffers on
1367 * @cleaned_count: number of buffers to replace
1369 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1371 union ixgbe_adv_rx_desc *rx_desc;
1372 struct ixgbe_rx_buffer *bi;
1373 u16 i = rx_ring->next_to_use;
1379 rx_desc = IXGBE_RX_DESC(rx_ring, i);
1380 bi = &rx_ring->rx_buffer_info[i];
1381 i -= rx_ring->count;
1384 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
1388 * Refresh the desc even if buffer_addrs didn't change
1389 * because each write-back erases this info.
1391 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
1397 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
1398 bi = rx_ring->rx_buffer_info;
1399 i -= rx_ring->count;
1402 /* clear the hdr_addr for the next_to_use descriptor */
1403 rx_desc->read.hdr_addr = 0;
1406 } while (cleaned_count);
1408 i += rx_ring->count;
1410 if (rx_ring->next_to_use != i)
1411 ixgbe_release_rx_desc(rx_ring, i);
1415 * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE
1416 * @data: pointer to the start of the headers
1417 * @max_len: total length of section to find headers in
1419 * This function is meant to determine the length of headers that will
1420 * be recognized by hardware for LRO, GRO, and RSC offloads. The main
1421 * motivation of doing this is to only perform one pull for IPv4 TCP
1422 * packets so that we can do basic things like calculating the gso_size
1423 * based on the average data per packet.
1425 static unsigned int ixgbe_get_headlen(unsigned char *data,
1426 unsigned int max_len)
1429 unsigned char *network;
1432 struct vlan_hdr *vlan;
1435 struct ipv6hdr *ipv6;
1438 u8 nexthdr = 0; /* default to not TCP */
1441 /* this should never happen, but better safe than sorry */
1442 if (max_len < ETH_HLEN)
1445 /* initialize network frame pointer */
1448 /* set first protocol and move network header forward */
1449 protocol = hdr.eth->h_proto;
1450 hdr.network += ETH_HLEN;
1452 /* handle any vlan tag if present */
1453 if (protocol == __constant_htons(ETH_P_8021Q)) {
1454 if ((hdr.network - data) > (max_len - VLAN_HLEN))
1457 protocol = hdr.vlan->h_vlan_encapsulated_proto;
1458 hdr.network += VLAN_HLEN;
1461 /* handle L3 protocols */
1462 if (protocol == __constant_htons(ETH_P_IP)) {
1463 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
1466 /* access ihl as a u8 to avoid unaligned access on ia64 */
1467 hlen = (hdr.network[0] & 0x0F) << 2;
1469 /* verify hlen meets minimum size requirements */
1470 if (hlen < sizeof(struct iphdr))
1471 return hdr.network - data;
1473 /* record next protocol if header is present */
1474 if (!(hdr.ipv4->frag_off & htons(IP_OFFSET)))
1475 nexthdr = hdr.ipv4->protocol;
1476 } else if (protocol == __constant_htons(ETH_P_IPV6)) {
1477 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
1480 /* record next protocol */
1481 nexthdr = hdr.ipv6->nexthdr;
1482 hlen = sizeof(struct ipv6hdr);
1484 } else if (protocol == __constant_htons(ETH_P_FCOE)) {
1485 if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN))
1487 hlen = FCOE_HEADER_LEN;
1490 return hdr.network - data;
1493 /* relocate pointer to start of L4 header */
1494 hdr.network += hlen;
1496 /* finally sort out TCP/UDP */
1497 if (nexthdr == IPPROTO_TCP) {
1498 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
1501 /* access doff as a u8 to avoid unaligned access on ia64 */
1502 hlen = (hdr.network[12] & 0xF0) >> 2;
1504 /* verify hlen meets minimum size requirements */
1505 if (hlen < sizeof(struct tcphdr))
1506 return hdr.network - data;
1508 hdr.network += hlen;
1509 } else if (nexthdr == IPPROTO_UDP) {
1510 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
1513 hdr.network += sizeof(struct udphdr);
1517 * If everything has gone correctly hdr.network should be the
1518 * data section of the packet and will be the end of the header.
1519 * If not then it probably represents the end of the last recognized
1522 if ((hdr.network - data) < max_len)
1523 return hdr.network - data;
1528 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1529 struct sk_buff *skb)
1531 u16 hdr_len = skb_headlen(skb);
1533 /* set gso_size to avoid messing up TCP MSS */
1534 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1535 IXGBE_CB(skb)->append_cnt);
1536 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1539 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1540 struct sk_buff *skb)
1542 /* if append_cnt is 0 then frame is not RSC */
1543 if (!IXGBE_CB(skb)->append_cnt)
1546 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1547 rx_ring->rx_stats.rsc_flush++;
1549 ixgbe_set_rsc_gso_size(rx_ring, skb);
1551 /* gso_size is computed using append_cnt so always clear it last */
1552 IXGBE_CB(skb)->append_cnt = 0;
1556 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1557 * @rx_ring: rx descriptor ring packet is being transacted on
1558 * @rx_desc: pointer to the EOP Rx descriptor
1559 * @skb: pointer to current skb being populated
1561 * This function checks the ring, descriptor, and packet information in
1562 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1563 * other fields within the skb.
1565 static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1566 union ixgbe_adv_rx_desc *rx_desc,
1567 struct sk_buff *skb)
1569 struct net_device *dev = rx_ring->netdev;
1571 ixgbe_update_rsc_stats(rx_ring, skb);
1573 ixgbe_rx_hash(rx_ring, rx_desc, skb);
1575 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1577 ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb);
1579 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1580 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
1581 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1582 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
1585 skb_record_rx_queue(skb, rx_ring->queue_index);
1587 skb->protocol = eth_type_trans(skb, dev);
1590 static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1591 struct sk_buff *skb)
1593 struct ixgbe_adapter *adapter = q_vector->adapter;
1595 if (ixgbe_qv_busy_polling(q_vector))
1596 netif_receive_skb(skb);
1597 else if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1598 napi_gro_receive(&q_vector->napi, skb);
1604 * ixgbe_is_non_eop - process handling of non-EOP buffers
1605 * @rx_ring: Rx ring being processed
1606 * @rx_desc: Rx descriptor for current buffer
1607 * @skb: Current socket buffer containing buffer in progress
1609 * This function updates next to clean. If the buffer is an EOP buffer
1610 * this function exits returning false, otherwise it will place the
1611 * sk_buff in the next buffer to be chained and return true indicating
1612 * that this is in fact a non-EOP buffer.
1614 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1615 union ixgbe_adv_rx_desc *rx_desc,
1616 struct sk_buff *skb)
1618 u32 ntc = rx_ring->next_to_clean + 1;
1620 /* fetch, update, and store next to clean */
1621 ntc = (ntc < rx_ring->count) ? ntc : 0;
1622 rx_ring->next_to_clean = ntc;
1624 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1626 /* update RSC append count if present */
1627 if (ring_is_rsc_enabled(rx_ring)) {
1628 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1629 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1631 if (unlikely(rsc_enabled)) {
1632 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1634 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1635 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
1637 /* update ntc based on RSC value */
1638 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1639 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1640 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1644 /* if we are the last buffer then there is nothing else to do */
1645 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1648 /* place skb in next buffer to be received */
1649 rx_ring->rx_buffer_info[ntc].skb = skb;
1650 rx_ring->rx_stats.non_eop_descs++;
1656 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1657 * @rx_ring: rx descriptor ring packet is being transacted on
1658 * @skb: pointer to current skb being adjusted
1660 * This function is an ixgbe specific version of __pskb_pull_tail. The
1661 * main difference between this version and the original function is that
1662 * this function can make several assumptions about the state of things
1663 * that allow for significant optimizations versus the standard function.
1664 * As a result we can do things like drop a frag and maintain an accurate
1665 * truesize for the skb.
1667 static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1668 struct sk_buff *skb)
1670 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1672 unsigned int pull_len;
1675 * it is valid to use page_address instead of kmap since we are
1676 * working with pages allocated out of the lomem pool per
1677 * alloc_page(GFP_ATOMIC)
1679 va = skb_frag_address(frag);
1682 * we need the header to contain the greater of either ETH_HLEN or
1683 * 60 bytes if the skb->len is less than 60 for skb_pad.
1685 pull_len = ixgbe_get_headlen(va, IXGBE_RX_HDR_SIZE);
1687 /* align pull length to size of long to optimize memcpy performance */
1688 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1690 /* update all of the pointers */
1691 skb_frag_size_sub(frag, pull_len);
1692 frag->page_offset += pull_len;
1693 skb->data_len -= pull_len;
1694 skb->tail += pull_len;
1698 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1699 * @rx_ring: rx descriptor ring packet is being transacted on
1700 * @skb: pointer to current skb being updated
1702 * This function provides a basic DMA sync up for the first fragment of an
1703 * skb. The reason for doing this is that the first fragment cannot be
1704 * unmapped until we have reached the end of packet descriptor for a buffer
1707 static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1708 struct sk_buff *skb)
1710 /* if the page was released unmap it, else just sync our portion */
1711 if (unlikely(IXGBE_CB(skb)->page_released)) {
1712 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1713 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1714 IXGBE_CB(skb)->page_released = false;
1716 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1718 dma_sync_single_range_for_cpu(rx_ring->dev,
1721 ixgbe_rx_bufsz(rx_ring),
1724 IXGBE_CB(skb)->dma = 0;
1728 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1729 * @rx_ring: rx descriptor ring packet is being transacted on
1730 * @rx_desc: pointer to the EOP Rx descriptor
1731 * @skb: pointer to current skb being fixed
1733 * Check for corrupted packet headers caused by senders on the local L2
1734 * embedded NIC switch not setting up their Tx Descriptors right. These
1735 * should be very rare.
1737 * Also address the case where we are pulling data in on pages only
1738 * and as such no data is present in the skb header.
1740 * In addition if skb is not at least 60 bytes we need to pad it so that
1741 * it is large enough to qualify as a valid Ethernet frame.
1743 * Returns true if an error was encountered and skb was freed.
1745 static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1746 union ixgbe_adv_rx_desc *rx_desc,
1747 struct sk_buff *skb)
1749 struct net_device *netdev = rx_ring->netdev;
1751 /* verify that the packet does not have any known errors */
1752 if (unlikely(ixgbe_test_staterr(rx_desc,
1753 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1754 !(netdev->features & NETIF_F_RXALL))) {
1755 dev_kfree_skb_any(skb);
1759 /* place header in linear portion of buffer */
1760 if (skb_is_nonlinear(skb))
1761 ixgbe_pull_tail(rx_ring, skb);
1764 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1765 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1769 /* if skb_pad returns an error the skb was freed */
1770 if (unlikely(skb->len < 60)) {
1771 int pad_len = 60 - skb->len;
1773 if (skb_pad(skb, pad_len))
1775 __skb_put(skb, pad_len);
1782 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1783 * @rx_ring: rx descriptor ring to store buffers on
1784 * @old_buff: donor buffer to have page reused
1786 * Synchronizes page for reuse by the adapter
1788 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1789 struct ixgbe_rx_buffer *old_buff)
1791 struct ixgbe_rx_buffer *new_buff;
1792 u16 nta = rx_ring->next_to_alloc;
1794 new_buff = &rx_ring->rx_buffer_info[nta];
1796 /* update, and store next to alloc */
1798 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1800 /* transfer page from old buffer to new buffer */
1801 new_buff->page = old_buff->page;
1802 new_buff->dma = old_buff->dma;
1803 new_buff->page_offset = old_buff->page_offset;
1805 /* sync the buffer for use by the device */
1806 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
1807 new_buff->page_offset,
1808 ixgbe_rx_bufsz(rx_ring),
1813 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1814 * @rx_ring: rx descriptor ring to transact packets on
1815 * @rx_buffer: buffer containing page to add
1816 * @rx_desc: descriptor containing length of buffer written by hardware
1817 * @skb: sk_buff to place the data into
1819 * This function will add the data contained in rx_buffer->page to the skb.
1820 * This is done either through a direct copy if the data in the buffer is
1821 * less than the skb header size, otherwise it will just attach the page as
1822 * a frag to the skb.
1824 * The function will then update the page offset if necessary and return
1825 * true if the buffer can be reused by the adapter.
1827 static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
1828 struct ixgbe_rx_buffer *rx_buffer,
1829 union ixgbe_adv_rx_desc *rx_desc,
1830 struct sk_buff *skb)
1832 struct page *page = rx_buffer->page;
1833 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
1834 #if (PAGE_SIZE < 8192)
1835 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
1837 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1838 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1839 ixgbe_rx_bufsz(rx_ring);
1842 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1843 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1845 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1847 /* we can reuse buffer as-is, just make sure it is local */
1848 if (likely(page_to_nid(page) == numa_node_id()))
1851 /* this page cannot be reused so discard it */
1856 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1857 rx_buffer->page_offset, size, truesize);
1859 /* avoid re-using remote pages */
1860 if (unlikely(page_to_nid(page) != numa_node_id()))
1863 #if (PAGE_SIZE < 8192)
1864 /* if we are only owner of page we can reuse it */
1865 if (unlikely(page_count(page) != 1))
1868 /* flip page offset to other buffer */
1869 rx_buffer->page_offset ^= truesize;
1872 * since we are the only owner of the page and we need to
1873 * increment it, just set the value to 2 in order to avoid
1874 * an unecessary locked operation
1876 atomic_set(&page->_count, 2);
1878 /* move offset up to the next cache line */
1879 rx_buffer->page_offset += truesize;
1881 if (rx_buffer->page_offset > last_offset)
1884 /* bump ref count on page before it is given to the stack */
1891 static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
1892 union ixgbe_adv_rx_desc *rx_desc)
1894 struct ixgbe_rx_buffer *rx_buffer;
1895 struct sk_buff *skb;
1898 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
1899 page = rx_buffer->page;
1902 skb = rx_buffer->skb;
1905 void *page_addr = page_address(page) +
1906 rx_buffer->page_offset;
1908 /* prefetch first cache line of first page */
1909 prefetch(page_addr);
1910 #if L1_CACHE_BYTES < 128
1911 prefetch(page_addr + L1_CACHE_BYTES);
1914 /* allocate a skb to store the frags */
1915 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1917 if (unlikely(!skb)) {
1918 rx_ring->rx_stats.alloc_rx_buff_failed++;
1923 * we will be copying header into skb->data in
1924 * pskb_may_pull so it is in our interest to prefetch
1925 * it now to avoid a possible cache miss
1927 prefetchw(skb->data);
1930 * Delay unmapping of the first packet. It carries the
1931 * header information, HW may still access the header
1932 * after the writeback. Only unmap it when EOP is
1935 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1938 IXGBE_CB(skb)->dma = rx_buffer->dma;
1940 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
1941 ixgbe_dma_sync_frag(rx_ring, skb);
1944 /* we are reusing so sync this buffer for CPU use */
1945 dma_sync_single_range_for_cpu(rx_ring->dev,
1947 rx_buffer->page_offset,
1948 ixgbe_rx_bufsz(rx_ring),
1952 /* pull page into skb */
1953 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
1954 /* hand second half of page back to the ring */
1955 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
1956 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
1957 /* the page has been released from the ring */
1958 IXGBE_CB(skb)->page_released = true;
1960 /* we are not reusing the buffer so unmap it */
1961 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
1962 ixgbe_rx_pg_size(rx_ring),
1966 /* clear contents of buffer_info */
1967 rx_buffer->skb = NULL;
1969 rx_buffer->page = NULL;
1975 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
1976 * @q_vector: structure containing interrupt and ring information
1977 * @rx_ring: rx descriptor ring to transact packets on
1978 * @budget: Total limit on number of packets to process
1980 * This function provides a "bounce buffer" approach to Rx interrupt
1981 * processing. The advantage to this is that on systems that have
1982 * expensive overhead for IOMMU access this provides a means of avoiding
1983 * it by maintaining the mapping of the page to the syste.
1985 * Returns amount of work completed
1987 static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1988 struct ixgbe_ring *rx_ring,
1991 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1993 struct ixgbe_adapter *adapter = q_vector->adapter;
1995 unsigned int mss = 0;
1996 #endif /* IXGBE_FCOE */
1997 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
2000 union ixgbe_adv_rx_desc *rx_desc;
2001 struct sk_buff *skb;
2003 /* return some buffers to hardware, one at a time is too slow */
2004 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
2005 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2009 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
2011 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD))
2015 * This memory barrier is needed to keep us from reading
2016 * any other fields out of the rx_desc until we know the
2017 * RXD_STAT_DD bit is set
2021 /* retrieve a buffer from the ring */
2022 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
2024 /* exit if we failed to retrieve a buffer */
2030 /* place incomplete frames back on ring for completion */
2031 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
2034 /* verify the packet layout is correct */
2035 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
2038 /* probably a little skewed due to removing CRC */
2039 total_rx_bytes += skb->len;
2041 /* populate checksum, timestamp, VLAN, and protocol */
2042 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
2045 /* if ddp, not passing to ULD unless for FCP_RSP or error */
2046 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
2047 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
2048 /* include DDPed FCoE data */
2049 if (ddp_bytes > 0) {
2051 mss = rx_ring->netdev->mtu -
2052 sizeof(struct fcoe_hdr) -
2053 sizeof(struct fc_frame_header) -
2054 sizeof(struct fcoe_crc_eof);
2058 total_rx_bytes += ddp_bytes;
2059 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
2063 dev_kfree_skb_any(skb);
2068 #endif /* IXGBE_FCOE */
2069 skb_mark_napi_id(skb, &q_vector->napi);
2070 ixgbe_rx_skb(q_vector, skb);
2072 /* update budget accounting */
2074 } while (likely(total_rx_packets < budget));
2076 u64_stats_update_begin(&rx_ring->syncp);
2077 rx_ring->stats.packets += total_rx_packets;
2078 rx_ring->stats.bytes += total_rx_bytes;
2079 u64_stats_update_end(&rx_ring->syncp);
2080 q_vector->rx.total_packets += total_rx_packets;
2081 q_vector->rx.total_bytes += total_rx_bytes;
2084 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2086 return total_rx_packets;
2089 #ifdef CONFIG_NET_RX_BUSY_POLL
2090 /* must be called with local_bh_disable()d */
2091 static int ixgbe_low_latency_recv(struct napi_struct *napi)
2093 struct ixgbe_q_vector *q_vector =
2094 container_of(napi, struct ixgbe_q_vector, napi);
2095 struct ixgbe_adapter *adapter = q_vector->adapter;
2096 struct ixgbe_ring *ring;
2099 if (test_bit(__IXGBE_DOWN, &adapter->state))
2100 return LL_FLUSH_FAILED;
2102 if (!ixgbe_qv_lock_poll(q_vector))
2103 return LL_FLUSH_BUSY;
2105 ixgbe_for_each_ring(ring, q_vector->rx) {
2106 found = ixgbe_clean_rx_irq(q_vector, ring, 4);
2107 #ifdef BP_EXTENDED_STATS
2109 ring->stats.cleaned += found;
2111 ring->stats.misses++;
2117 ixgbe_qv_unlock_poll(q_vector);
2121 #endif /* CONFIG_NET_RX_BUSY_POLL */
2124 * ixgbe_configure_msix - Configure MSI-X hardware
2125 * @adapter: board private structure
2127 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
2130 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
2132 struct ixgbe_q_vector *q_vector;
2136 /* Populate MSIX to EITR Select */
2137 if (adapter->num_vfs > 32) {
2138 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2139 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2143 * Populate the IVAR table and set the ITR values to the
2144 * corresponding register.
2146 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
2147 struct ixgbe_ring *ring;
2148 q_vector = adapter->q_vector[v_idx];
2150 ixgbe_for_each_ring(ring, q_vector->rx)
2151 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
2153 ixgbe_for_each_ring(ring, q_vector->tx)
2154 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
2156 ixgbe_write_eitr(q_vector);
2159 switch (adapter->hw.mac.type) {
2160 case ixgbe_mac_82598EB:
2161 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
2164 case ixgbe_mac_82599EB:
2165 case ixgbe_mac_X540:
2166 ixgbe_set_ivar(adapter, -1, 1, v_idx);
2171 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2173 /* set up to autoclear timer, and the vectors */
2174 mask = IXGBE_EIMS_ENABLE_MASK;
2175 mask &= ~(IXGBE_EIMS_OTHER |
2176 IXGBE_EIMS_MAILBOX |
2179 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
2182 enum latency_range {
2186 latency_invalid = 255
2190 * ixgbe_update_itr - update the dynamic ITR value based on statistics
2191 * @q_vector: structure containing interrupt and ring information
2192 * @ring_container: structure containing ring performance data
2194 * Stores a new ITR value based on packets and byte
2195 * counts during the last interrupt. The advantage of per interrupt
2196 * computation is faster updates and more accurate ITR for the current
2197 * traffic pattern. Constants in this function were computed
2198 * based on theoretical maximum wire speed and thresholds were set based
2199 * on testing data as well as attempting to minimize response time
2200 * while increasing bulk throughput.
2201 * this functionality is controlled by the InterruptThrottleRate module
2202 * parameter (see ixgbe_param.c)
2204 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2205 struct ixgbe_ring_container *ring_container)
2207 int bytes = ring_container->total_bytes;
2208 int packets = ring_container->total_packets;
2211 u8 itr_setting = ring_container->itr;
2216 /* simple throttlerate management
2217 * 0-10MB/s lowest (100000 ints/s)
2218 * 10-20MB/s low (20000 ints/s)
2219 * 20-1249MB/s bulk (8000 ints/s)
2221 /* what was last interrupt timeslice? */
2222 timepassed_us = q_vector->itr >> 2;
2223 if (timepassed_us == 0)
2226 bytes_perint = bytes / timepassed_us; /* bytes/usec */
2228 switch (itr_setting) {
2229 case lowest_latency:
2230 if (bytes_perint > 10)
2231 itr_setting = low_latency;
2234 if (bytes_perint > 20)
2235 itr_setting = bulk_latency;
2236 else if (bytes_perint <= 10)
2237 itr_setting = lowest_latency;
2240 if (bytes_perint <= 20)
2241 itr_setting = low_latency;
2245 /* clear work counters since we have the values we need */
2246 ring_container->total_bytes = 0;
2247 ring_container->total_packets = 0;
2249 /* write updated itr to ring container */
2250 ring_container->itr = itr_setting;
2254 * ixgbe_write_eitr - write EITR register in hardware specific way
2255 * @q_vector: structure containing interrupt and ring information
2257 * This function is made to be called by ethtool and by the driver
2258 * when it needs to update EITR registers at runtime. Hardware
2259 * specific quirks/differences are taken care of here.
2261 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
2263 struct ixgbe_adapter *adapter = q_vector->adapter;
2264 struct ixgbe_hw *hw = &adapter->hw;
2265 int v_idx = q_vector->v_idx;
2266 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
2268 switch (adapter->hw.mac.type) {
2269 case ixgbe_mac_82598EB:
2270 /* must write high and low 16 bits to reset counter */
2271 itr_reg |= (itr_reg << 16);
2273 case ixgbe_mac_82599EB:
2274 case ixgbe_mac_X540:
2276 * set the WDIS bit to not clear the timer bits and cause an
2277 * immediate assertion of the interrupt
2279 itr_reg |= IXGBE_EITR_CNT_WDIS;
2284 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2287 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
2289 u32 new_itr = q_vector->itr;
2292 ixgbe_update_itr(q_vector, &q_vector->tx);
2293 ixgbe_update_itr(q_vector, &q_vector->rx);
2295 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
2297 switch (current_itr) {
2298 /* counts and packets in update_itr are dependent on these numbers */
2299 case lowest_latency:
2300 new_itr = IXGBE_100K_ITR;
2303 new_itr = IXGBE_20K_ITR;
2306 new_itr = IXGBE_8K_ITR;
2312 if (new_itr != q_vector->itr) {
2313 /* do an exponential smoothing */
2314 new_itr = (10 * new_itr * q_vector->itr) /
2315 ((9 * new_itr) + q_vector->itr);
2317 /* save the algorithm value here */
2318 q_vector->itr = new_itr;
2320 ixgbe_write_eitr(q_vector);
2325 * ixgbe_check_overtemp_subtask - check for over temperature
2326 * @adapter: pointer to adapter
2328 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
2330 struct ixgbe_hw *hw = &adapter->hw;
2331 u32 eicr = adapter->interrupt_event;
2333 if (test_bit(__IXGBE_DOWN, &adapter->state))
2336 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2337 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2340 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2342 switch (hw->device_id) {
2343 case IXGBE_DEV_ID_82599_T3_LOM:
2345 * Since the warning interrupt is for both ports
2346 * we don't have to check if:
2347 * - This interrupt wasn't for our port.
2348 * - We may have missed the interrupt so always have to
2349 * check if we got a LSC
2351 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
2352 !(eicr & IXGBE_EICR_LSC))
2355 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
2357 bool link_up = false;
2359 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2365 /* Check if this is not due to overtemp */
2366 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2371 if (!(eicr & IXGBE_EICR_GPI_SDP0))
2376 "Network adapter has been stopped because it has over heated. "
2377 "Restart the computer. If the problem persists, "
2378 "power off the system and replace the adapter\n");
2380 adapter->interrupt_event = 0;
2383 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2385 struct ixgbe_hw *hw = &adapter->hw;
2387 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2388 (eicr & IXGBE_EICR_GPI_SDP1)) {
2389 e_crit(probe, "Fan has stopped, replace the adapter\n");
2390 /* write to clear the interrupt */
2391 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2395 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2397 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2400 switch (adapter->hw.mac.type) {
2401 case ixgbe_mac_82599EB:
2403 * Need to check link state so complete overtemp check
2406 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
2407 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2408 adapter->interrupt_event = eicr;
2409 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2410 ixgbe_service_event_schedule(adapter);
2414 case ixgbe_mac_X540:
2415 if (!(eicr & IXGBE_EICR_TS))
2423 "Network adapter has been stopped because it has over heated. "
2424 "Restart the computer. If the problem persists, "
2425 "power off the system and replace the adapter\n");
2428 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2430 struct ixgbe_hw *hw = &adapter->hw;
2432 if (eicr & IXGBE_EICR_GPI_SDP2) {
2433 /* Clear the interrupt */
2434 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
2435 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2436 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2437 ixgbe_service_event_schedule(adapter);
2441 if (eicr & IXGBE_EICR_GPI_SDP1) {
2442 /* Clear the interrupt */
2443 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2444 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2445 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2446 ixgbe_service_event_schedule(adapter);
2451 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2453 struct ixgbe_hw *hw = &adapter->hw;
2456 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2457 adapter->link_check_timeout = jiffies;
2458 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2459 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
2460 IXGBE_WRITE_FLUSH(hw);
2461 ixgbe_service_event_schedule(adapter);
2465 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2469 struct ixgbe_hw *hw = &adapter->hw;
2471 switch (hw->mac.type) {
2472 case ixgbe_mac_82598EB:
2473 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2474 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2476 case ixgbe_mac_82599EB:
2477 case ixgbe_mac_X540:
2478 mask = (qmask & 0xFFFFFFFF);
2480 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
2481 mask = (qmask >> 32);
2483 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2488 /* skip the flush */
2491 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
2495 struct ixgbe_hw *hw = &adapter->hw;
2497 switch (hw->mac.type) {
2498 case ixgbe_mac_82598EB:
2499 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2500 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2502 case ixgbe_mac_82599EB:
2503 case ixgbe_mac_X540:
2504 mask = (qmask & 0xFFFFFFFF);
2506 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
2507 mask = (qmask >> 32);
2509 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2514 /* skip the flush */
2518 * ixgbe_irq_enable - Enable default interrupt generation settings
2519 * @adapter: board private structure
2521 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2524 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2526 /* don't reenable LSC while waiting for link */
2527 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2528 mask &= ~IXGBE_EIMS_LSC;
2530 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2531 switch (adapter->hw.mac.type) {
2532 case ixgbe_mac_82599EB:
2533 mask |= IXGBE_EIMS_GPI_SDP0;
2535 case ixgbe_mac_X540:
2536 mask |= IXGBE_EIMS_TS;
2541 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2542 mask |= IXGBE_EIMS_GPI_SDP1;
2543 switch (adapter->hw.mac.type) {
2544 case ixgbe_mac_82599EB:
2545 mask |= IXGBE_EIMS_GPI_SDP1;
2546 mask |= IXGBE_EIMS_GPI_SDP2;
2547 case ixgbe_mac_X540:
2548 mask |= IXGBE_EIMS_ECC;
2549 mask |= IXGBE_EIMS_MAILBOX;
2555 if (adapter->hw.mac.type == ixgbe_mac_X540)
2556 mask |= IXGBE_EIMS_TIMESYNC;
2558 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2559 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2560 mask |= IXGBE_EIMS_FLOW_DIR;
2562 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2564 ixgbe_irq_enable_queues(adapter, ~0);
2566 IXGBE_WRITE_FLUSH(&adapter->hw);
2569 static irqreturn_t ixgbe_msix_other(int irq, void *data)
2571 struct ixgbe_adapter *adapter = data;
2572 struct ixgbe_hw *hw = &adapter->hw;
2576 * Workaround for Silicon errata. Use clear-by-write instead
2577 * of clear-by-read. Reading with EICS will return the
2578 * interrupt causes without clearing, which later be done
2579 * with the write to EICR.
2581 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
2583 /* The lower 16bits of the EICR register are for the queue interrupts
2584 * which should be masked here in order to not accidently clear them if
2585 * the bits are high when ixgbe_msix_other is called. There is a race
2586 * condition otherwise which results in possible performance loss
2587 * especially if the ixgbe_msix_other interrupt is triggering
2588 * consistently (as it would when PPS is turned on for the X540 device)
2592 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
2594 if (eicr & IXGBE_EICR_LSC)
2595 ixgbe_check_lsc(adapter);
2597 if (eicr & IXGBE_EICR_MAILBOX)
2598 ixgbe_msg_task(adapter);
2600 switch (hw->mac.type) {
2601 case ixgbe_mac_82599EB:
2602 case ixgbe_mac_X540:
2603 if (eicr & IXGBE_EICR_ECC)
2604 e_info(link, "Received unrecoverable ECC Err, please "
2606 /* Handle Flow Director Full threshold interrupt */
2607 if (eicr & IXGBE_EICR_FLOW_DIR) {
2608 int reinit_count = 0;
2610 for (i = 0; i < adapter->num_tx_queues; i++) {
2611 struct ixgbe_ring *ring = adapter->tx_ring[i];
2612 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
2617 /* no more flow director interrupts until after init */
2618 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
2619 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2620 ixgbe_service_event_schedule(adapter);
2623 ixgbe_check_sfp_event(adapter, eicr);
2624 ixgbe_check_overtemp_event(adapter, eicr);
2630 ixgbe_check_fan_failure(adapter, eicr);
2632 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2633 ixgbe_ptp_check_pps_event(adapter, eicr);
2635 /* re-enable the original interrupt state, no lsc, no queues */
2636 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2637 ixgbe_irq_enable(adapter, false, false);
2642 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
2644 struct ixgbe_q_vector *q_vector = data;
2646 /* EIAM disabled interrupts (on this vector) for us */
2648 if (q_vector->rx.ring || q_vector->tx.ring)
2649 napi_schedule(&q_vector->napi);
2655 * ixgbe_poll - NAPI Rx polling callback
2656 * @napi: structure for representing this polling device
2657 * @budget: how many packets driver is allowed to clean
2659 * This function is used for legacy and MSI, NAPI mode
2661 int ixgbe_poll(struct napi_struct *napi, int budget)
2663 struct ixgbe_q_vector *q_vector =
2664 container_of(napi, struct ixgbe_q_vector, napi);
2665 struct ixgbe_adapter *adapter = q_vector->adapter;
2666 struct ixgbe_ring *ring;
2667 int per_ring_budget;
2668 bool clean_complete = true;
2670 #ifdef CONFIG_IXGBE_DCA
2671 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2672 ixgbe_update_dca(q_vector);
2675 ixgbe_for_each_ring(ring, q_vector->tx)
2676 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2678 if (!ixgbe_qv_lock_napi(q_vector))
2681 /* attempt to distribute budget to each queue fairly, but don't allow
2682 * the budget to go below 1 because we'll exit polling */
2683 if (q_vector->rx.count > 1)
2684 per_ring_budget = max(budget/q_vector->rx.count, 1);
2686 per_ring_budget = budget;
2688 ixgbe_for_each_ring(ring, q_vector->rx)
2689 clean_complete &= (ixgbe_clean_rx_irq(q_vector, ring,
2690 per_ring_budget) < per_ring_budget);
2692 ixgbe_qv_unlock_napi(q_vector);
2693 /* If all work not completed, return budget and keep polling */
2694 if (!clean_complete)
2697 /* all work done, exit the polling mode */
2698 napi_complete(napi);
2699 if (adapter->rx_itr_setting & 1)
2700 ixgbe_set_itr(q_vector);
2701 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2702 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2708 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2709 * @adapter: board private structure
2711 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2712 * interrupts from the kernel.
2714 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2716 struct net_device *netdev = adapter->netdev;
2720 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2721 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2722 struct msix_entry *entry = &adapter->msix_entries[vector];
2724 if (q_vector->tx.ring && q_vector->rx.ring) {
2725 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2726 "%s-%s-%d", netdev->name, "TxRx", ri++);
2728 } else if (q_vector->rx.ring) {
2729 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2730 "%s-%s-%d", netdev->name, "rx", ri++);
2731 } else if (q_vector->tx.ring) {
2732 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2733 "%s-%s-%d", netdev->name, "tx", ti++);
2735 /* skip this unused q_vector */
2738 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2739 q_vector->name, q_vector);
2741 e_err(probe, "request_irq failed for MSIX interrupt "
2742 "Error: %d\n", err);
2743 goto free_queue_irqs;
2745 /* If Flow Director is enabled, set interrupt affinity */
2746 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2747 /* assign the mask for this irq */
2748 irq_set_affinity_hint(entry->vector,
2749 &q_vector->affinity_mask);
2753 err = request_irq(adapter->msix_entries[vector].vector,
2754 ixgbe_msix_other, 0, netdev->name, adapter);
2756 e_err(probe, "request_irq for msix_other failed: %d\n", err);
2757 goto free_queue_irqs;
2765 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2767 free_irq(adapter->msix_entries[vector].vector,
2768 adapter->q_vector[vector]);
2770 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2771 pci_disable_msix(adapter->pdev);
2772 kfree(adapter->msix_entries);
2773 adapter->msix_entries = NULL;
2778 * ixgbe_intr - legacy mode Interrupt Handler
2779 * @irq: interrupt number
2780 * @data: pointer to a network interface device structure
2782 static irqreturn_t ixgbe_intr(int irq, void *data)
2784 struct ixgbe_adapter *adapter = data;
2785 struct ixgbe_hw *hw = &adapter->hw;
2786 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2790 * Workaround for silicon errata #26 on 82598. Mask the interrupt
2791 * before the read of EICR.
2793 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2795 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2796 * therefore no explicit interrupt disable is necessary */
2797 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2800 * shared interrupt alert!
2801 * make sure interrupts are enabled because the read will
2802 * have disabled interrupts due to EIAM
2803 * finish the workaround of silicon errata on 82598. Unmask
2804 * the interrupt that we masked before the EICR read.
2806 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2807 ixgbe_irq_enable(adapter, true, true);
2808 return IRQ_NONE; /* Not our interrupt */
2811 if (eicr & IXGBE_EICR_LSC)
2812 ixgbe_check_lsc(adapter);
2814 switch (hw->mac.type) {
2815 case ixgbe_mac_82599EB:
2816 ixgbe_check_sfp_event(adapter, eicr);
2818 case ixgbe_mac_X540:
2819 if (eicr & IXGBE_EICR_ECC)
2820 e_info(link, "Received unrecoverable ECC err, please "
2822 ixgbe_check_overtemp_event(adapter, eicr);
2828 ixgbe_check_fan_failure(adapter, eicr);
2829 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2830 ixgbe_ptp_check_pps_event(adapter, eicr);
2832 /* would disable interrupts here but EIAM disabled it */
2833 napi_schedule(&q_vector->napi);
2836 * re-enable link(maybe) and non-queue interrupts, no flush.
2837 * ixgbe_poll will re-enable the queue interrupts
2839 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2840 ixgbe_irq_enable(adapter, false, false);
2846 * ixgbe_request_irq - initialize interrupts
2847 * @adapter: board private structure
2849 * Attempts to configure interrupts using the best available
2850 * capabilities of the hardware and kernel.
2852 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2854 struct net_device *netdev = adapter->netdev;
2857 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2858 err = ixgbe_request_msix_irqs(adapter);
2859 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
2860 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2861 netdev->name, adapter);
2863 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2864 netdev->name, adapter);
2867 e_err(probe, "request_irq failed, Error %d\n", err);
2872 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2876 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2877 free_irq(adapter->pdev->irq, adapter);
2881 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2882 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2883 struct msix_entry *entry = &adapter->msix_entries[vector];
2885 /* free only the irqs that were actually requested */
2886 if (!q_vector->rx.ring && !q_vector->tx.ring)
2889 /* clear the affinity_mask in the IRQ descriptor */
2890 irq_set_affinity_hint(entry->vector, NULL);
2892 free_irq(entry->vector, q_vector);
2895 free_irq(adapter->msix_entries[vector++].vector, adapter);
2899 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2900 * @adapter: board private structure
2902 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2904 switch (adapter->hw.mac.type) {
2905 case ixgbe_mac_82598EB:
2906 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2908 case ixgbe_mac_82599EB:
2909 case ixgbe_mac_X540:
2910 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2911 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2912 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2917 IXGBE_WRITE_FLUSH(&adapter->hw);
2918 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2921 for (vector = 0; vector < adapter->num_q_vectors; vector++)
2922 synchronize_irq(adapter->msix_entries[vector].vector);
2924 synchronize_irq(adapter->msix_entries[vector++].vector);
2926 synchronize_irq(adapter->pdev->irq);
2931 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2934 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2936 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2938 ixgbe_write_eitr(q_vector);
2940 ixgbe_set_ivar(adapter, 0, 0, 0);
2941 ixgbe_set_ivar(adapter, 1, 0, 0);
2943 e_info(hw, "Legacy interrupt IVAR setup done\n");
2947 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2948 * @adapter: board private structure
2949 * @ring: structure containing ring specific data
2951 * Configure the Tx descriptor ring after a reset.
2953 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2954 struct ixgbe_ring *ring)
2956 struct ixgbe_hw *hw = &adapter->hw;
2957 u64 tdba = ring->dma;
2959 u32 txdctl = IXGBE_TXDCTL_ENABLE;
2960 u8 reg_idx = ring->reg_idx;
2962 /* disable queue to avoid issues while updating state */
2963 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2964 IXGBE_WRITE_FLUSH(hw);
2966 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2967 (tdba & DMA_BIT_MASK(32)));
2968 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2969 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2970 ring->count * sizeof(union ixgbe_adv_tx_desc));
2971 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2972 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2973 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2976 * set WTHRESH to encourage burst writeback, it should not be set
2977 * higher than 1 when:
2978 * - ITR is 0 as it could cause false TX hangs
2979 * - ITR is set to > 100k int/sec and BQL is enabled
2981 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2982 * to or less than the number of on chip descriptors, which is
2985 #if IS_ENABLED(CONFIG_BQL)
2986 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR))
2988 if (!ring->q_vector || (ring->q_vector->itr < 8))
2990 txdctl |= (1 << 16); /* WTHRESH = 1 */
2992 txdctl |= (8 << 16); /* WTHRESH = 8 */
2995 * Setting PTHRESH to 32 both improves performance
2996 * and avoids a TX hang with DFP enabled
2998 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2999 32; /* PTHRESH = 32 */
3001 /* reinitialize flowdirector state */
3002 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3003 ring->atr_sample_rate = adapter->atr_sample_rate;
3004 ring->atr_count = 0;
3005 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
3007 ring->atr_sample_rate = 0;
3010 /* initialize XPS */
3011 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) {
3012 struct ixgbe_q_vector *q_vector = ring->q_vector;
3015 netif_set_xps_queue(ring->netdev,
3016 &q_vector->affinity_mask,
3020 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
3023 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
3025 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3026 if (hw->mac.type == ixgbe_mac_82598EB &&
3027 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3030 /* poll to verify queue is enabled */
3032 usleep_range(1000, 2000);
3033 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
3034 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
3036 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
3039 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
3041 struct ixgbe_hw *hw = &adapter->hw;
3043 u8 tcs = netdev_get_num_tc(adapter->netdev);
3045 if (hw->mac.type == ixgbe_mac_82598EB)
3048 /* disable the arbiter while setting MTQC */
3049 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3050 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3051 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3053 /* set transmit pool layout */
3054 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3055 mtqc = IXGBE_MTQC_VT_ENA;
3057 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3059 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3060 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3061 mtqc |= IXGBE_MTQC_32VF;
3063 mtqc |= IXGBE_MTQC_64VF;
3066 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3068 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3070 mtqc = IXGBE_MTQC_64Q_1PB;
3073 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3075 /* Enable Security TX Buffer IFG for multiple pb */
3077 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3078 sectx |= IXGBE_SECTX_DCB;
3079 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
3082 /* re-enable the arbiter */
3083 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3084 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3088 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
3089 * @adapter: board private structure
3091 * Configure the Tx unit of the MAC after a reset.
3093 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
3095 struct ixgbe_hw *hw = &adapter->hw;
3099 ixgbe_setup_mtqc(adapter);
3101 if (hw->mac.type != ixgbe_mac_82598EB) {
3102 /* DMATXCTL.EN must be before Tx queues are enabled */
3103 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3104 dmatxctl |= IXGBE_DMATXCTL_TE;
3105 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3108 /* Setup the HW Tx Head and Tail descriptor pointers */
3109 for (i = 0; i < adapter->num_tx_queues; i++)
3110 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
3113 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
3114 struct ixgbe_ring *ring)
3116 struct ixgbe_hw *hw = &adapter->hw;
3117 u8 reg_idx = ring->reg_idx;
3118 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3120 srrctl |= IXGBE_SRRCTL_DROP_EN;
3122 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3125 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
3126 struct ixgbe_ring *ring)
3128 struct ixgbe_hw *hw = &adapter->hw;
3129 u8 reg_idx = ring->reg_idx;
3130 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3132 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
3134 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3137 #ifdef CONFIG_IXGBE_DCB
3138 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3140 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3144 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
3146 if (adapter->ixgbe_ieee_pfc)
3147 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
3150 * We should set the drop enable bit if:
3153 * Number of Rx queues > 1 and flow control is disabled
3155 * This allows us to avoid head of line blocking for security
3156 * and performance reasons.
3158 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
3159 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
3160 for (i = 0; i < adapter->num_rx_queues; i++)
3161 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
3163 for (i = 0; i < adapter->num_rx_queues; i++)
3164 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
3168 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
3170 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
3171 struct ixgbe_ring *rx_ring)
3173 struct ixgbe_hw *hw = &adapter->hw;
3175 u8 reg_idx = rx_ring->reg_idx;
3177 if (hw->mac.type == ixgbe_mac_82598EB) {
3178 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
3181 * if VMDq is not active we must program one srrctl register
3182 * per RSS queue since we have enabled RDRXCTL.MVMEN
3187 /* configure header buffer length, needed for RSC */
3188 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
3190 /* configure the packet buffer length */
3191 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
3193 /* configure descriptor type */
3194 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3196 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3199 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
3201 struct ixgbe_hw *hw = &adapter->hw;
3202 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
3203 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
3204 0x6A3E67EA, 0x14364D17, 0x3BED200D};
3205 u32 mrqc = 0, reta = 0;
3208 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3211 * Program table for at least 2 queues w/ SR-IOV so that VFs can
3212 * make full use of any rings they may have. We will use the
3213 * PSRTYPE register to control how many rings we use within the PF.
3215 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
3218 /* Fill out hash function seeds */
3219 for (i = 0; i < 10; i++)
3220 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
3222 /* Fill out redirection table */
3223 for (i = 0, j = 0; i < 128; i++, j++) {
3226 /* reta = 4-byte sliding window of
3227 * 0x00..(indices-1)(indices-1)00..etc. */
3228 reta = (reta << 8) | (j * 0x11);
3230 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3233 /* Disable indicating checksum in descriptor, enables RSS hash */
3234 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3235 rxcsum |= IXGBE_RXCSUM_PCSD;
3236 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3238 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3239 if (adapter->ring_feature[RING_F_RSS].mask)
3240 mrqc = IXGBE_MRQC_RSSEN;
3242 u8 tcs = netdev_get_num_tc(adapter->netdev);
3244 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3246 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3248 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3249 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3250 mrqc = IXGBE_MRQC_VMDQRSS32EN;
3252 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3255 mrqc = IXGBE_MRQC_RTRSS8TCEN;
3257 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3259 mrqc = IXGBE_MRQC_RSSEN;
3263 /* Perform hash on these packet types */
3264 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3265 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3266 IXGBE_MRQC_RSS_FIELD_IPV6 |
3267 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
3269 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
3270 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3271 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
3272 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3274 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3278 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3279 * @adapter: address of board private structure
3280 * @index: index of ring to set
3282 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
3283 struct ixgbe_ring *ring)
3285 struct ixgbe_hw *hw = &adapter->hw;
3287 u8 reg_idx = ring->reg_idx;
3289 if (!ring_is_rsc_enabled(ring))
3292 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
3293 rscctrl |= IXGBE_RSCCTL_RSCEN;
3295 * we must limit the number of descriptors so that the
3296 * total size of max desc * buf_len is not greater
3299 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
3300 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
3303 #define IXGBE_MAX_RX_DESC_POLL 10
3304 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3305 struct ixgbe_ring *ring)
3307 struct ixgbe_hw *hw = &adapter->hw;
3308 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3310 u8 reg_idx = ring->reg_idx;
3312 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3313 if (hw->mac.type == ixgbe_mac_82598EB &&
3314 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3318 usleep_range(1000, 2000);
3319 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3320 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3323 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3324 "the polling period\n", reg_idx);
3328 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3329 struct ixgbe_ring *ring)
3331 struct ixgbe_hw *hw = &adapter->hw;
3332 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3334 u8 reg_idx = ring->reg_idx;
3336 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3337 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3339 /* write value back with RXDCTL.ENABLE bit cleared */
3340 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3342 if (hw->mac.type == ixgbe_mac_82598EB &&
3343 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3346 /* the hardware may take up to 100us to really disable the rx queue */
3349 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3350 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3353 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3354 "the polling period\n", reg_idx);
3358 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3359 struct ixgbe_ring *ring)
3361 struct ixgbe_hw *hw = &adapter->hw;
3362 u64 rdba = ring->dma;
3364 u8 reg_idx = ring->reg_idx;
3366 /* disable queue to avoid issues while updating state */
3367 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3368 ixgbe_disable_rx_queue(adapter, ring);
3370 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3371 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3372 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3373 ring->count * sizeof(union ixgbe_adv_rx_desc));
3374 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3375 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
3376 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
3378 ixgbe_configure_srrctl(adapter, ring);
3379 ixgbe_configure_rscctl(adapter, ring);
3381 if (hw->mac.type == ixgbe_mac_82598EB) {
3383 * enable cache line friendly hardware writes:
3384 * PTHRESH=32 descriptors (half the internal cache),
3385 * this also removes ugly rx_no_buffer_count increment
3386 * HTHRESH=4 descriptors (to minimize latency on fetch)
3387 * WTHRESH=8 burst writeback up to two cache lines
3389 rxdctl &= ~0x3FFFFF;
3393 /* enable receive descriptor ring */
3394 rxdctl |= IXGBE_RXDCTL_ENABLE;
3395 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3397 ixgbe_rx_desc_queue_enable(adapter, ring);
3398 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
3401 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3403 struct ixgbe_hw *hw = &adapter->hw;
3404 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
3407 /* PSRTYPE must be initialized in non 82598 adapters */
3408 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3409 IXGBE_PSRTYPE_UDPHDR |
3410 IXGBE_PSRTYPE_IPV4HDR |
3411 IXGBE_PSRTYPE_L2HDR |
3412 IXGBE_PSRTYPE_IPV6HDR;
3414 if (hw->mac.type == ixgbe_mac_82598EB)
3422 for_each_set_bit(pool, &adapter->fwd_bitmask, 32)
3423 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
3426 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3428 struct ixgbe_hw *hw = &adapter->hw;
3429 u32 reg_offset, vf_shift;
3430 u32 gcr_ext, vmdctl;
3433 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3436 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3437 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3438 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
3439 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
3440 vmdctl |= IXGBE_VT_CTL_REPLEN;
3441 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
3443 vf_shift = VMDQ_P(0) % 32;
3444 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
3446 /* Enable only the PF's pool for Tx/Rx */
3447 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3448 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3449 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3450 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
3451 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
3452 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3454 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3455 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
3458 * Set up VF register offsets for selected VT Mode,
3459 * i.e. 32 or 64 VFs for SR-IOV
3461 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3462 case IXGBE_82599_VMDQ_8Q_MASK:
3463 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3465 case IXGBE_82599_VMDQ_4Q_MASK:
3466 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3469 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3473 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3476 /* Enable MAC Anti-Spoofing */
3477 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
3479 /* For VFs that have spoof checking turned off */
3480 for (i = 0; i < adapter->num_vfs; i++) {
3481 if (!adapter->vfinfo[i].spoofchk_enabled)
3482 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3486 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3488 struct ixgbe_hw *hw = &adapter->hw;
3489 struct net_device *netdev = adapter->netdev;
3490 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3491 struct ixgbe_ring *rx_ring;
3496 /* adjust max frame to be able to do baby jumbo for FCoE */
3497 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3498 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3499 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3501 #endif /* IXGBE_FCOE */
3503 /* adjust max frame to be at least the size of a standard frame */
3504 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3505 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3507 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3508 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3509 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3510 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3512 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3515 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3516 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3517 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3518 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3521 * Setup the HW Rx Head and Tail Descriptor Pointers and
3522 * the Base and Length of the Rx Descriptor Ring
3524 for (i = 0; i < adapter->num_rx_queues; i++) {
3525 rx_ring = adapter->rx_ring[i];
3526 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3527 set_ring_rsc_enabled(rx_ring);
3529 clear_ring_rsc_enabled(rx_ring);
3533 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3535 struct ixgbe_hw *hw = &adapter->hw;
3536 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3538 switch (hw->mac.type) {
3539 case ixgbe_mac_82598EB:
3541 * For VMDq support of different descriptor types or
3542 * buffer sizes through the use of multiple SRRCTL
3543 * registers, RDRXCTL.MVMEN must be set to 1
3545 * also, the manual doesn't mention it clearly but DCA hints
3546 * will only use queue 0's tags unless this bit is set. Side
3547 * effects of setting this bit are only that SRRCTL must be
3548 * fully programmed [0..15]
3550 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3552 case ixgbe_mac_82599EB:
3553 case ixgbe_mac_X540:
3554 /* Disable RSC for ACK packets */
3555 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3556 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3557 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3558 /* hardware requires some bits to be set by default */
3559 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3560 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3563 /* We should do nothing since we don't know this hardware */
3567 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3571 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3572 * @adapter: board private structure
3574 * Configure the Rx unit of the MAC after a reset.
3576 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3578 struct ixgbe_hw *hw = &adapter->hw;
3582 /* disable receives while setting up the descriptors */
3583 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3584 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3586 ixgbe_setup_psrtype(adapter);
3587 ixgbe_setup_rdrxctl(adapter);
3590 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
3591 rfctl &= ~IXGBE_RFCTL_RSC_DIS;
3592 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
3593 rfctl |= IXGBE_RFCTL_RSC_DIS;
3594 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
3596 /* Program registers for the distribution of queues */
3597 ixgbe_setup_mrqc(adapter);
3599 /* set_rx_buffer_len must be called before ring initialization */
3600 ixgbe_set_rx_buffer_len(adapter);
3603 * Setup the HW Rx Head and Tail Descriptor Pointers and
3604 * the Base and Length of the Rx Descriptor Ring
3606 for (i = 0; i < adapter->num_rx_queues; i++)
3607 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3609 /* disable drop enable for 82598 parts */
3610 if (hw->mac.type == ixgbe_mac_82598EB)
3611 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3613 /* enable all receives */
3614 rxctrl |= IXGBE_RXCTRL_RXEN;
3615 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3618 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev,
3619 __be16 proto, u16 vid)
3621 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3622 struct ixgbe_hw *hw = &adapter->hw;
3624 /* add VID to filter table */
3625 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true);
3626 set_bit(vid, adapter->active_vlans);
3631 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev,
3632 __be16 proto, u16 vid)
3634 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3635 struct ixgbe_hw *hw = &adapter->hw;
3637 /* remove VID from filter table */
3638 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false);
3639 clear_bit(vid, adapter->active_vlans);
3645 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3646 * @adapter: driver data
3648 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3650 struct ixgbe_hw *hw = &adapter->hw;
3653 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3654 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3655 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3659 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3660 * @adapter: driver data
3662 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3664 struct ixgbe_hw *hw = &adapter->hw;
3667 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3668 vlnctrl |= IXGBE_VLNCTRL_VFE;
3669 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3670 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3674 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3675 * @adapter: driver data
3677 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3679 struct ixgbe_hw *hw = &adapter->hw;
3683 switch (hw->mac.type) {
3684 case ixgbe_mac_82598EB:
3685 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3686 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3687 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3689 case ixgbe_mac_82599EB:
3690 case ixgbe_mac_X540:
3691 for (i = 0; i < adapter->num_rx_queues; i++) {
3692 struct ixgbe_ring *ring = adapter->rx_ring[i];
3694 if (ring->l2_accel_priv)
3697 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3698 vlnctrl &= ~IXGBE_RXDCTL_VME;
3699 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3708 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3709 * @adapter: driver data
3711 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3713 struct ixgbe_hw *hw = &adapter->hw;
3717 switch (hw->mac.type) {
3718 case ixgbe_mac_82598EB:
3719 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3720 vlnctrl |= IXGBE_VLNCTRL_VME;
3721 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3723 case ixgbe_mac_82599EB:
3724 case ixgbe_mac_X540:
3725 for (i = 0; i < adapter->num_rx_queues; i++) {
3726 struct ixgbe_ring *ring = adapter->rx_ring[i];
3728 if (ring->l2_accel_priv)
3731 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3732 vlnctrl |= IXGBE_RXDCTL_VME;
3733 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3741 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3745 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
3747 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3748 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
3752 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3753 * @netdev: network interface device structure
3755 * Writes unicast address list to the RAR table.
3756 * Returns: -ENOMEM on failure/insufficient address space
3757 * 0 on no addresses written
3758 * X on writing X addresses to the RAR table
3760 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3762 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3763 struct ixgbe_hw *hw = &adapter->hw;
3764 unsigned int rar_entries = hw->mac.num_rar_entries - 1;
3767 /* In SR-IOV/VMDQ modes significantly less RAR entries are available */
3768 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3769 rar_entries = IXGBE_MAX_PF_MACVLANS - 1;
3771 /* return ENOMEM indicating insufficient memory for addresses */
3772 if (netdev_uc_count(netdev) > rar_entries)
3775 if (!netdev_uc_empty(netdev)) {
3776 struct netdev_hw_addr *ha;
3777 /* return error if we do not support writing to RAR table */
3778 if (!hw->mac.ops.set_rar)
3781 netdev_for_each_uc_addr(ha, netdev) {
3784 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3785 VMDQ_P(0), IXGBE_RAH_AV);
3789 /* write the addresses in reverse order to avoid write combining */
3790 for (; rar_entries > 0 ; rar_entries--)
3791 hw->mac.ops.clear_rar(hw, rar_entries);
3797 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3798 * @netdev: network interface device structure
3800 * The set_rx_method entry point is called whenever the unicast/multicast
3801 * address list or the network interface flags are updated. This routine is
3802 * responsible for configuring the hardware for proper unicast, multicast and
3805 void ixgbe_set_rx_mode(struct net_device *netdev)
3807 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3808 struct ixgbe_hw *hw = &adapter->hw;
3809 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3812 /* Check for Promiscuous and All Multicast modes */
3814 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3816 /* set all bits that we expect to always be set */
3817 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
3818 fctrl |= IXGBE_FCTRL_BAM;
3819 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3820 fctrl |= IXGBE_FCTRL_PMCF;
3822 /* clear the bits we are changing the status of */
3823 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3825 if (netdev->flags & IFF_PROMISC) {
3826 hw->addr_ctrl.user_set_promisc = true;
3827 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3828 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3829 /* Only disable hardware filter vlans in promiscuous mode
3830 * if SR-IOV and VMDQ are disabled - otherwise ensure
3831 * that hardware VLAN filters remain enabled.
3833 if (!(adapter->flags & (IXGBE_FLAG_VMDQ_ENABLED |
3834 IXGBE_FLAG_SRIOV_ENABLED)))
3835 ixgbe_vlan_filter_disable(adapter);
3837 ixgbe_vlan_filter_enable(adapter);
3839 if (netdev->flags & IFF_ALLMULTI) {
3840 fctrl |= IXGBE_FCTRL_MPE;
3841 vmolr |= IXGBE_VMOLR_MPE;
3843 ixgbe_vlan_filter_enable(adapter);
3844 hw->addr_ctrl.user_set_promisc = false;
3848 * Write addresses to available RAR registers, if there is not
3849 * sufficient space to store all the addresses then enable
3850 * unicast promiscuous mode
3852 count = ixgbe_write_uc_addr_list(netdev);
3854 fctrl |= IXGBE_FCTRL_UPE;
3855 vmolr |= IXGBE_VMOLR_ROPE;
3858 /* Write addresses to the MTA, if the attempt fails
3859 * then we should just turn on promiscuous mode so
3860 * that we can at least receive multicast traffic
3862 hw->mac.ops.update_mc_addr_list(hw, netdev);
3863 vmolr |= IXGBE_VMOLR_ROMPE;
3865 if (adapter->num_vfs)
3866 ixgbe_restore_vf_multicasts(adapter);
3868 if (hw->mac.type != ixgbe_mac_82598EB) {
3869 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
3870 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3872 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
3875 /* This is useful for sniffing bad packets. */
3876 if (adapter->netdev->features & NETIF_F_RXALL) {
3877 /* UPE and MPE will be handled by normal PROMISC logic
3878 * in e1000e_set_rx_mode */
3879 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
3880 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
3881 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
3883 fctrl &= ~(IXGBE_FCTRL_DPF);
3884 /* NOTE: VLAN filtering is disabled by setting PROMISC */
3887 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3889 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
3890 ixgbe_vlan_strip_enable(adapter);
3892 ixgbe_vlan_strip_disable(adapter);
3895 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3899 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
3900 ixgbe_qv_init_lock(adapter->q_vector[q_idx]);
3901 napi_enable(&adapter->q_vector[q_idx]->napi);
3905 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3909 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
3910 napi_disable(&adapter->q_vector[q_idx]->napi);
3911 while (!ixgbe_qv_disable(adapter->q_vector[q_idx])) {
3912 pr_info("QV %d locked\n", q_idx);
3913 usleep_range(1000, 20000);
3918 #ifdef CONFIG_IXGBE_DCB
3920 * ixgbe_configure_dcb - Configure DCB hardware
3921 * @adapter: ixgbe adapter struct
3923 * This is called by the driver on open to configure the DCB hardware.
3924 * This is also called by the gennetlink interface when reconfiguring
3927 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3929 struct ixgbe_hw *hw = &adapter->hw;
3930 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3932 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3933 if (hw->mac.type == ixgbe_mac_82598EB)
3934 netif_set_gso_max_size(adapter->netdev, 65536);
3938 if (hw->mac.type == ixgbe_mac_82598EB)
3939 netif_set_gso_max_size(adapter->netdev, 32768);
3942 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3943 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3946 /* reconfigure the hardware */
3947 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
3948 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3950 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3952 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3953 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
3954 ixgbe_dcb_hw_ets(&adapter->hw,
3955 adapter->ixgbe_ieee_ets,
3957 ixgbe_dcb_hw_pfc_config(&adapter->hw,
3958 adapter->ixgbe_ieee_pfc->pfc_en,
3959 adapter->ixgbe_ieee_ets->prio_tc);
3962 /* Enable RSS Hash per TC */
3963 if (hw->mac.type != ixgbe_mac_82598EB) {
3965 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
3972 /* write msb to all 8 TCs in one write */
3973 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
3978 /* Additional bittime to account for IXGBE framing */
3979 #define IXGBE_ETH_FRAMING 20
3982 * ixgbe_hpbthresh - calculate high water mark for flow control
3984 * @adapter: board private structure to calculate for
3985 * @pb: packet buffer to calculate
3987 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
3989 struct ixgbe_hw *hw = &adapter->hw;
3990 struct net_device *dev = adapter->netdev;
3991 int link, tc, kb, marker;
3994 /* Calculate max LAN frame size */
3995 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
3998 /* FCoE traffic class uses FCOE jumbo frames */
3999 if ((dev->features & NETIF_F_FCOE_MTU) &&
4000 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4001 (pb == ixgbe_fcoe_get_tc(adapter)))
4002 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
4005 /* Calculate delay value for device */
4006 switch (hw->mac.type) {
4007 case ixgbe_mac_X540:
4008 dv_id = IXGBE_DV_X540(link, tc);
4011 dv_id = IXGBE_DV(link, tc);
4015 /* Loopback switch introduces additional latency */
4016 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4017 dv_id += IXGBE_B2BT(tc);
4019 /* Delay value is calculated in bit times convert to KB */
4020 kb = IXGBE_BT2KB(dv_id);
4021 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
4023 marker = rx_pba - kb;
4025 /* It is possible that the packet buffer is not large enough
4026 * to provide required headroom. In this case throw an error
4027 * to user and a do the best we can.
4030 e_warn(drv, "Packet Buffer(%i) can not provide enough"
4031 "headroom to support flow control."
4032 "Decrease MTU or number of traffic classes\n", pb);
4040 * ixgbe_lpbthresh - calculate low water mark for for flow control
4042 * @adapter: board private structure to calculate for
4043 * @pb: packet buffer to calculate
4045 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
4047 struct ixgbe_hw *hw = &adapter->hw;
4048 struct net_device *dev = adapter->netdev;
4052 /* Calculate max LAN frame size */
4053 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
4055 /* Calculate delay value for device */
4056 switch (hw->mac.type) {
4057 case ixgbe_mac_X540:
4058 dv_id = IXGBE_LOW_DV_X540(tc);
4061 dv_id = IXGBE_LOW_DV(tc);
4065 /* Delay value is calculated in bit times convert to KB */
4066 return IXGBE_BT2KB(dv_id);
4070 * ixgbe_pbthresh_setup - calculate and setup high low water marks
4072 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
4074 struct ixgbe_hw *hw = &adapter->hw;
4075 int num_tc = netdev_get_num_tc(adapter->netdev);
4081 hw->fc.low_water = ixgbe_lpbthresh(adapter);
4083 for (i = 0; i < num_tc; i++) {
4084 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
4086 /* Low water marks must not be larger than high water marks */
4087 if (hw->fc.low_water > hw->fc.high_water[i])
4088 hw->fc.low_water = 0;
4092 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
4094 struct ixgbe_hw *hw = &adapter->hw;
4096 u8 tc = netdev_get_num_tc(adapter->netdev);
4098 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4099 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
4100 hdrm = 32 << adapter->fdir_pballoc;
4104 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
4105 ixgbe_pbthresh_setup(adapter);
4108 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
4110 struct ixgbe_hw *hw = &adapter->hw;
4111 struct hlist_node *node2;
4112 struct ixgbe_fdir_filter *filter;
4114 spin_lock(&adapter->fdir_perfect_lock);
4116 if (!hlist_empty(&adapter->fdir_filter_list))
4117 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
4119 hlist_for_each_entry_safe(filter, node2,
4120 &adapter->fdir_filter_list, fdir_node) {
4121 ixgbe_fdir_write_perfect_filter_82599(hw,
4124 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
4125 IXGBE_FDIR_DROP_QUEUE :
4126 adapter->rx_ring[filter->action]->reg_idx);
4129 spin_unlock(&adapter->fdir_perfect_lock);
4132 static void ixgbe_macvlan_set_rx_mode(struct net_device *dev, unsigned int pool,
4133 struct ixgbe_adapter *adapter)
4135 struct ixgbe_hw *hw = &adapter->hw;
4138 /* No unicast promiscuous support for VMDQ devices. */
4139 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4140 vmolr |= (IXGBE_VMOLR_ROMPE | IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE);
4142 /* clear the affected bit */
4143 vmolr &= ~IXGBE_VMOLR_MPE;
4145 if (dev->flags & IFF_ALLMULTI) {
4146 vmolr |= IXGBE_VMOLR_MPE;
4148 vmolr |= IXGBE_VMOLR_ROMPE;
4149 hw->mac.ops.update_mc_addr_list(hw, dev);
4151 ixgbe_write_uc_addr_list(adapter->netdev);
4152 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4155 static void ixgbe_add_mac_filter(struct ixgbe_adapter *adapter,
4158 struct ixgbe_hw *hw = &adapter->hw;
4161 entry = hw->mac.num_rar_entries - pool;
4162 hw->mac.ops.set_rar(hw, entry, addr, VMDQ_P(pool), IXGBE_RAH_AV);
4165 static void ixgbe_fwd_psrtype(struct ixgbe_fwd_adapter *vadapter)
4167 struct ixgbe_adapter *adapter = vadapter->real_adapter;
4168 int rss_i = adapter->num_rx_queues_per_pool;
4169 struct ixgbe_hw *hw = &adapter->hw;
4170 u16 pool = vadapter->pool;
4171 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
4172 IXGBE_PSRTYPE_UDPHDR |
4173 IXGBE_PSRTYPE_IPV4HDR |
4174 IXGBE_PSRTYPE_L2HDR |
4175 IXGBE_PSRTYPE_IPV6HDR;
4177 if (hw->mac.type == ixgbe_mac_82598EB)
4185 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
4189 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4190 * @rx_ring: ring to free buffers from
4192 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4194 struct device *dev = rx_ring->dev;
4198 /* ring already cleared, nothing to do */
4199 if (!rx_ring->rx_buffer_info)
4202 /* Free all the Rx ring sk_buffs */
4203 for (i = 0; i < rx_ring->count; i++) {
4204 struct ixgbe_rx_buffer *rx_buffer;
4206 rx_buffer = &rx_ring->rx_buffer_info[i];
4207 if (rx_buffer->skb) {
4208 struct sk_buff *skb = rx_buffer->skb;
4209 if (IXGBE_CB(skb)->page_released) {
4212 ixgbe_rx_bufsz(rx_ring),
4214 IXGBE_CB(skb)->page_released = false;
4218 rx_buffer->skb = NULL;
4220 dma_unmap_page(dev, rx_buffer->dma,
4221 ixgbe_rx_pg_size(rx_ring),
4224 if (rx_buffer->page)
4225 __free_pages(rx_buffer->page,
4226 ixgbe_rx_pg_order(rx_ring));
4227 rx_buffer->page = NULL;
4230 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4231 memset(rx_ring->rx_buffer_info, 0, size);
4233 /* Zero out the descriptor ring */
4234 memset(rx_ring->desc, 0, rx_ring->size);
4236 rx_ring->next_to_alloc = 0;
4237 rx_ring->next_to_clean = 0;
4238 rx_ring->next_to_use = 0;
4241 static void ixgbe_disable_fwd_ring(struct ixgbe_fwd_adapter *vadapter,
4242 struct ixgbe_ring *rx_ring)
4244 struct ixgbe_adapter *adapter = vadapter->real_adapter;
4245 int index = rx_ring->queue_index + vadapter->rx_base_queue;
4247 /* shutdown specific queue receive and wait for dma to settle */
4248 ixgbe_disable_rx_queue(adapter, rx_ring);
4249 usleep_range(10000, 20000);
4250 ixgbe_irq_disable_queues(adapter, ((u64)1 << index));
4251 ixgbe_clean_rx_ring(rx_ring);
4252 rx_ring->l2_accel_priv = NULL;
4255 static int ixgbe_fwd_ring_down(struct net_device *vdev,
4256 struct ixgbe_fwd_adapter *accel)
4258 struct ixgbe_adapter *adapter = accel->real_adapter;
4259 unsigned int rxbase = accel->rx_base_queue;
4260 unsigned int txbase = accel->tx_base_queue;
4263 netif_tx_stop_all_queues(vdev);
4265 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4266 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4267 adapter->rx_ring[rxbase + i]->netdev = adapter->netdev;
4270 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4271 adapter->tx_ring[txbase + i]->l2_accel_priv = NULL;
4272 adapter->tx_ring[txbase + i]->netdev = adapter->netdev;
4279 static int ixgbe_fwd_ring_up(struct net_device *vdev,
4280 struct ixgbe_fwd_adapter *accel)
4282 struct ixgbe_adapter *adapter = accel->real_adapter;
4283 unsigned int rxbase, txbase, queues;
4284 int i, baseq, err = 0;
4286 if (!test_bit(accel->pool, &adapter->fwd_bitmask))
4289 baseq = accel->pool * adapter->num_rx_queues_per_pool;
4290 netdev_dbg(vdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
4291 accel->pool, adapter->num_rx_pools,
4292 baseq, baseq + adapter->num_rx_queues_per_pool,
4293 adapter->fwd_bitmask);
4295 accel->netdev = vdev;
4296 accel->rx_base_queue = rxbase = baseq;
4297 accel->tx_base_queue = txbase = baseq;
4299 for (i = 0; i < adapter->num_rx_queues_per_pool; i++)
4300 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4302 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4303 adapter->rx_ring[rxbase + i]->netdev = vdev;
4304 adapter->rx_ring[rxbase + i]->l2_accel_priv = accel;
4305 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[rxbase + i]);
4308 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4309 adapter->tx_ring[txbase + i]->netdev = vdev;
4310 adapter->tx_ring[txbase + i]->l2_accel_priv = accel;
4313 queues = min_t(unsigned int,
4314 adapter->num_rx_queues_per_pool, vdev->num_tx_queues);
4315 err = netif_set_real_num_tx_queues(vdev, queues);
4319 err = netif_set_real_num_rx_queues(vdev, queues);
4323 if (is_valid_ether_addr(vdev->dev_addr))
4324 ixgbe_add_mac_filter(adapter, vdev->dev_addr, accel->pool);
4326 ixgbe_fwd_psrtype(accel);
4327 ixgbe_macvlan_set_rx_mode(vdev, accel->pool, adapter);
4330 ixgbe_fwd_ring_down(vdev, accel);
4334 static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter)
4336 struct net_device *upper;
4337 struct list_head *iter;
4340 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
4341 if (netif_is_macvlan(upper)) {
4342 struct macvlan_dev *dfwd = netdev_priv(upper);
4343 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv;
4345 if (dfwd->fwd_priv) {
4346 err = ixgbe_fwd_ring_up(upper, vadapter);
4354 static void ixgbe_configure(struct ixgbe_adapter *adapter)
4356 struct ixgbe_hw *hw = &adapter->hw;
4358 ixgbe_configure_pb(adapter);
4359 #ifdef CONFIG_IXGBE_DCB
4360 ixgbe_configure_dcb(adapter);
4363 * We must restore virtualization before VLANs or else
4364 * the VLVF registers will not be populated
4366 ixgbe_configure_virtualization(adapter);
4368 ixgbe_set_rx_mode(adapter->netdev);
4369 ixgbe_restore_vlan(adapter);
4371 switch (hw->mac.type) {
4372 case ixgbe_mac_82599EB:
4373 case ixgbe_mac_X540:
4374 hw->mac.ops.disable_rx_buff(hw);
4380 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4381 ixgbe_init_fdir_signature_82599(&adapter->hw,
4382 adapter->fdir_pballoc);
4383 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
4384 ixgbe_init_fdir_perfect_82599(&adapter->hw,
4385 adapter->fdir_pballoc);
4386 ixgbe_fdir_filter_restore(adapter);
4389 switch (hw->mac.type) {
4390 case ixgbe_mac_82599EB:
4391 case ixgbe_mac_X540:
4392 hw->mac.ops.enable_rx_buff(hw);
4399 /* configure FCoE L2 filters, redirection table, and Rx control */
4400 ixgbe_configure_fcoe(adapter);
4402 #endif /* IXGBE_FCOE */
4403 ixgbe_configure_tx(adapter);
4404 ixgbe_configure_rx(adapter);
4405 ixgbe_configure_dfwd(adapter);
4408 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
4410 switch (hw->phy.type) {
4411 case ixgbe_phy_sfp_avago:
4412 case ixgbe_phy_sfp_ftl:
4413 case ixgbe_phy_sfp_intel:
4414 case ixgbe_phy_sfp_unknown:
4415 case ixgbe_phy_sfp_passive_tyco:
4416 case ixgbe_phy_sfp_passive_unknown:
4417 case ixgbe_phy_sfp_active_unknown:
4418 case ixgbe_phy_sfp_ftl_active:
4419 case ixgbe_phy_qsfp_passive_unknown:
4420 case ixgbe_phy_qsfp_active_unknown:
4421 case ixgbe_phy_qsfp_intel:
4422 case ixgbe_phy_qsfp_unknown:
4425 if (hw->mac.type == ixgbe_mac_82598EB)
4433 * ixgbe_sfp_link_config - set up SFP+ link
4434 * @adapter: pointer to private adapter struct
4436 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
4439 * We are assuming the worst case scenario here, and that
4440 * is that an SFP was inserted/removed after the reset
4441 * but before SFP detection was enabled. As such the best
4442 * solution is to just start searching as soon as we start
4444 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
4445 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
4447 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
4451 * ixgbe_non_sfp_link_config - set up non-SFP+ link
4452 * @hw: pointer to private hardware struct
4454 * Returns 0 on success, negative on failure
4456 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
4459 bool autoneg, link_up = false;
4460 u32 ret = IXGBE_ERR_LINK_SETUP;
4462 if (hw->mac.ops.check_link)
4463 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
4468 speed = hw->phy.autoneg_advertised;
4469 if ((!speed) && (hw->mac.ops.get_link_capabilities))
4470 ret = hw->mac.ops.get_link_capabilities(hw, &speed,
4475 if (hw->mac.ops.setup_link)
4476 ret = hw->mac.ops.setup_link(hw, speed, link_up);
4481 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
4483 struct ixgbe_hw *hw = &adapter->hw;
4486 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4487 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4489 gpie |= IXGBE_GPIE_EIAME;
4491 * use EIAM to auto-mask when MSI-X interrupt is asserted
4492 * this saves a register write for every interrupt
4494 switch (hw->mac.type) {
4495 case ixgbe_mac_82598EB:
4496 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4498 case ixgbe_mac_82599EB:
4499 case ixgbe_mac_X540:
4501 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4502 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4506 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
4507 * specifically only auto mask tx and rx interrupts */
4508 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4511 /* XXX: to interrupt immediately for EICS writes, enable this */
4512 /* gpie |= IXGBE_GPIE_EIMEN; */
4514 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
4515 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
4517 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4518 case IXGBE_82599_VMDQ_8Q_MASK:
4519 gpie |= IXGBE_GPIE_VTMODE_16;
4521 case IXGBE_82599_VMDQ_4Q_MASK:
4522 gpie |= IXGBE_GPIE_VTMODE_32;
4525 gpie |= IXGBE_GPIE_VTMODE_64;
4530 /* Enable Thermal over heat sensor interrupt */
4531 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
4532 switch (adapter->hw.mac.type) {
4533 case ixgbe_mac_82599EB:
4534 gpie |= IXGBE_SDP0_GPIEN;
4536 case ixgbe_mac_X540:
4537 gpie |= IXGBE_EIMS_TS;
4544 /* Enable fan failure interrupt */
4545 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
4546 gpie |= IXGBE_SDP1_GPIEN;
4548 if (hw->mac.type == ixgbe_mac_82599EB) {
4549 gpie |= IXGBE_SDP1_GPIEN;
4550 gpie |= IXGBE_SDP2_GPIEN;
4553 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4556 static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
4558 struct ixgbe_hw *hw = &adapter->hw;
4559 struct net_device *upper;
4560 struct list_head *iter;
4564 ixgbe_get_hw_control(adapter);
4565 ixgbe_setup_gpie(adapter);
4567 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4568 ixgbe_configure_msix(adapter);
4570 ixgbe_configure_msi_and_legacy(adapter);
4572 /* enable the optics for 82599 SFP+ fiber */
4573 if (hw->mac.ops.enable_tx_laser)
4574 hw->mac.ops.enable_tx_laser(hw);
4576 clear_bit(__IXGBE_DOWN, &adapter->state);
4577 ixgbe_napi_enable_all(adapter);
4579 if (ixgbe_is_sfp(hw)) {
4580 ixgbe_sfp_link_config(adapter);
4582 err = ixgbe_non_sfp_link_config(hw);
4584 e_err(probe, "link_config FAILED %d\n", err);
4587 /* clear any pending interrupts, may auto mask */
4588 IXGBE_READ_REG(hw, IXGBE_EICR);
4589 ixgbe_irq_enable(adapter, true, true);
4592 * If this adapter has a fan, check to see if we had a failure
4593 * before we enabled the interrupt.
4595 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4596 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4597 if (esdp & IXGBE_ESDP_SDP1)
4598 e_crit(drv, "Fan has stopped, replace the adapter\n");
4601 /* enable transmits */
4602 netif_tx_start_all_queues(adapter->netdev);
4604 /* enable any upper devices */
4605 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
4606 if (netif_is_macvlan(upper)) {
4607 struct macvlan_dev *vlan = netdev_priv(upper);
4610 netif_tx_start_all_queues(upper);
4614 /* bring the link up in the watchdog, this could race with our first
4615 * link up interrupt but shouldn't be a problem */
4616 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4617 adapter->link_check_timeout = jiffies;
4618 mod_timer(&adapter->service_timer, jiffies);
4620 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
4621 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4622 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4623 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
4626 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4628 WARN_ON(in_interrupt());
4629 /* put off any impending NetWatchDogTimeout */
4630 adapter->netdev->trans_start = jiffies;
4632 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
4633 usleep_range(1000, 2000);
4634 ixgbe_down(adapter);
4636 * If SR-IOV enabled then wait a bit before bringing the adapter
4637 * back up to give the VFs time to respond to the reset. The
4638 * two second wait is based upon the watchdog timer cycle in
4641 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4644 clear_bit(__IXGBE_RESETTING, &adapter->state);
4647 void ixgbe_up(struct ixgbe_adapter *adapter)
4649 /* hardware has been reset, we need to reload some things */
4650 ixgbe_configure(adapter);
4652 ixgbe_up_complete(adapter);
4655 void ixgbe_reset(struct ixgbe_adapter *adapter)
4657 struct ixgbe_hw *hw = &adapter->hw;
4660 /* lock SFP init bit to prevent race conditions with the watchdog */
4661 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4662 usleep_range(1000, 2000);
4664 /* clear all SFP and link config related flags while holding SFP_INIT */
4665 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4666 IXGBE_FLAG2_SFP_NEEDS_RESET);
4667 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4669 err = hw->mac.ops.init_hw(hw);
4672 case IXGBE_ERR_SFP_NOT_PRESENT:
4673 case IXGBE_ERR_SFP_NOT_SUPPORTED:
4675 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
4676 e_dev_err("master disable timed out\n");
4678 case IXGBE_ERR_EEPROM_VERSION:
4679 /* We are running on a pre-production device, log a warning */
4680 e_dev_warn("This device is a pre-production adapter/LOM. "
4681 "Please be aware there may be issues associated with "
4682 "your hardware. If you are experiencing problems "
4683 "please contact your Intel or hardware "
4684 "representative who provided you with this "
4688 e_dev_err("Hardware Error: %d\n", err);
4691 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4693 /* reprogram the RAR[0] in case user changed it. */
4694 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
4696 /* update SAN MAC vmdq pool selection */
4697 if (hw->mac.san_mac_rar_index)
4698 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
4700 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
4701 ixgbe_ptp_reset(adapter);
4705 * ixgbe_clean_tx_ring - Free Tx Buffers
4706 * @tx_ring: ring to be cleaned
4708 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
4710 struct ixgbe_tx_buffer *tx_buffer_info;
4714 /* ring already cleared, nothing to do */
4715 if (!tx_ring->tx_buffer_info)
4718 /* Free all the Tx ring sk_buffs */
4719 for (i = 0; i < tx_ring->count; i++) {
4720 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4721 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
4724 netdev_tx_reset_queue(txring_txq(tx_ring));
4726 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4727 memset(tx_ring->tx_buffer_info, 0, size);
4729 /* Zero out the descriptor ring */
4730 memset(tx_ring->desc, 0, tx_ring->size);
4732 tx_ring->next_to_use = 0;
4733 tx_ring->next_to_clean = 0;
4737 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
4738 * @adapter: board private structure
4740 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
4744 for (i = 0; i < adapter->num_rx_queues; i++)
4745 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
4749 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
4750 * @adapter: board private structure
4752 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
4756 for (i = 0; i < adapter->num_tx_queues; i++)
4757 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
4760 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4762 struct hlist_node *node2;
4763 struct ixgbe_fdir_filter *filter;
4765 spin_lock(&adapter->fdir_perfect_lock);
4767 hlist_for_each_entry_safe(filter, node2,
4768 &adapter->fdir_filter_list, fdir_node) {
4769 hlist_del(&filter->fdir_node);
4772 adapter->fdir_filter_count = 0;
4774 spin_unlock(&adapter->fdir_perfect_lock);
4777 void ixgbe_down(struct ixgbe_adapter *adapter)
4779 struct net_device *netdev = adapter->netdev;
4780 struct ixgbe_hw *hw = &adapter->hw;
4781 struct net_device *upper;
4782 struct list_head *iter;
4786 /* signal that we are down to the interrupt handler */
4787 set_bit(__IXGBE_DOWN, &adapter->state);
4789 /* disable receives */
4790 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4791 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4793 /* disable all enabled rx queues */
4794 for (i = 0; i < adapter->num_rx_queues; i++)
4795 /* this call also flushes the previous write */
4796 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4798 usleep_range(10000, 20000);
4800 netif_tx_stop_all_queues(netdev);
4802 /* call carrier off first to avoid false dev_watchdog timeouts */
4803 netif_carrier_off(netdev);
4804 netif_tx_disable(netdev);
4806 /* disable any upper devices */
4807 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
4808 if (netif_is_macvlan(upper)) {
4809 struct macvlan_dev *vlan = netdev_priv(upper);
4811 if (vlan->fwd_priv) {
4812 netif_tx_stop_all_queues(upper);
4813 netif_carrier_off(upper);
4814 netif_tx_disable(upper);
4819 ixgbe_irq_disable(adapter);
4821 ixgbe_napi_disable_all(adapter);
4823 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4824 IXGBE_FLAG2_RESET_REQUESTED);
4825 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4827 del_timer_sync(&adapter->service_timer);
4829 if (adapter->num_vfs) {
4830 /* Clear EITR Select mapping */
4831 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
4833 /* Mark all the VFs as inactive */
4834 for (i = 0 ; i < adapter->num_vfs; i++)
4835 adapter->vfinfo[i].clear_to_send = false;
4837 /* ping all the active vfs to let them know we are going down */
4838 ixgbe_ping_all_vfs(adapter);
4840 /* Disable all VFTE/VFRE TX/RX */
4841 ixgbe_disable_tx_rx(adapter);
4844 /* disable transmits in the hardware now that interrupts are off */
4845 for (i = 0; i < adapter->num_tx_queues; i++) {
4846 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4847 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
4850 /* Disable the Tx DMA engine on 82599 and X540 */
4851 switch (hw->mac.type) {
4852 case ixgbe_mac_82599EB:
4853 case ixgbe_mac_X540:
4854 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
4855 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4856 ~IXGBE_DMATXCTL_TE));
4862 if (!pci_channel_offline(adapter->pdev))
4863 ixgbe_reset(adapter);
4865 /* power down the optics for 82599 SFP+ fiber */
4866 if (hw->mac.ops.disable_tx_laser)
4867 hw->mac.ops.disable_tx_laser(hw);
4869 ixgbe_clean_all_tx_rings(adapter);
4870 ixgbe_clean_all_rx_rings(adapter);
4872 #ifdef CONFIG_IXGBE_DCA
4873 /* since we reset the hardware DCA settings were cleared */
4874 ixgbe_setup_dca(adapter);
4879 * ixgbe_tx_timeout - Respond to a Tx Hang
4880 * @netdev: network interface device structure
4882 static void ixgbe_tx_timeout(struct net_device *netdev)
4884 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4886 /* Do the reset outside of interrupt context */
4887 ixgbe_tx_timeout_reset(adapter);
4891 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4892 * @adapter: board private structure to initialize
4894 * ixgbe_sw_init initializes the Adapter private data structure.
4895 * Fields are initialized based on PCI device information and
4896 * OS network device settings (MTU size).
4898 static int ixgbe_sw_init(struct ixgbe_adapter *adapter)
4900 struct ixgbe_hw *hw = &adapter->hw;
4901 struct pci_dev *pdev = adapter->pdev;
4902 unsigned int rss, fdir;
4904 #ifdef CONFIG_IXGBE_DCB
4906 struct tc_configuration *tc;
4909 /* PCI config space info */
4911 hw->vendor_id = pdev->vendor;
4912 hw->device_id = pdev->device;
4913 hw->revision_id = pdev->revision;
4914 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4915 hw->subsystem_device_id = pdev->subsystem_device;
4917 /* Set common capability flags and settings */
4918 rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus());
4919 adapter->ring_feature[RING_F_RSS].limit = rss;
4920 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4921 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4922 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
4923 adapter->atr_sample_rate = 20;
4924 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus());
4925 adapter->ring_feature[RING_F_FDIR].limit = fdir;
4926 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
4927 #ifdef CONFIG_IXGBE_DCA
4928 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
4931 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4932 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4933 #ifdef CONFIG_IXGBE_DCB
4934 /* Default traffic class to use for FCoE */
4935 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4936 #endif /* CONFIG_IXGBE_DCB */
4937 #endif /* IXGBE_FCOE */
4939 /* Set MAC specific capability flags and exceptions */
4940 switch (hw->mac.type) {
4941 case ixgbe_mac_82598EB:
4942 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
4943 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
4945 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4946 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4948 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
4949 adapter->ring_feature[RING_F_FDIR].limit = 0;
4950 adapter->atr_sample_rate = 0;
4951 adapter->fdir_pballoc = 0;
4953 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
4954 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4955 #ifdef CONFIG_IXGBE_DCB
4956 adapter->fcoe.up = 0;
4957 #endif /* IXGBE_DCB */
4958 #endif /* IXGBE_FCOE */
4960 case ixgbe_mac_82599EB:
4961 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4962 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4964 case ixgbe_mac_X540:
4965 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
4966 if (fwsm & IXGBE_FWSM_TS_ENABLED)
4967 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4974 /* FCoE support exists, always init the FCoE lock */
4975 spin_lock_init(&adapter->fcoe.lock);
4978 /* n-tuple support exists, always init our spinlock */
4979 spin_lock_init(&adapter->fdir_perfect_lock);
4981 #ifdef CONFIG_IXGBE_DCB
4982 switch (hw->mac.type) {
4983 case ixgbe_mac_X540:
4984 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
4985 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
4988 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
4989 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
4993 /* Configure DCB traffic classes */
4994 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4995 tc = &adapter->dcb_cfg.tc_config[j];
4996 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4997 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4998 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4999 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5000 tc->dcb_pfc = pfc_disabled;
5003 /* Initialize default user to priority mapping, UPx->TC0 */
5004 tc = &adapter->dcb_cfg.tc_config[0];
5005 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
5006 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
5008 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5009 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
5010 adapter->dcb_cfg.pfc_mode_enable = false;
5011 adapter->dcb_set_bitmap = 0x00;
5012 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
5013 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
5014 sizeof(adapter->temp_dcb_cfg));
5018 /* default flow control settings */
5019 hw->fc.requested_mode = ixgbe_fc_full;
5020 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
5021 ixgbe_pbthresh_setup(adapter);
5022 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5023 hw->fc.send_xon = true;
5024 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw);
5026 #ifdef CONFIG_PCI_IOV
5028 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n");
5030 /* assign number of SR-IOV VFs */
5031 if (hw->mac.type != ixgbe_mac_82598EB) {
5033 adapter->num_vfs = 0;
5034 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n");
5036 adapter->num_vfs = max_vfs;
5039 #endif /* CONFIG_PCI_IOV */
5041 /* enable itr by default in dynamic mode */
5042 adapter->rx_itr_setting = 1;
5043 adapter->tx_itr_setting = 1;
5045 /* set default ring sizes */
5046 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5047 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5049 /* set default work limits */
5050 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
5052 /* initialize eeprom parameters */
5053 if (ixgbe_init_eeprom_params_generic(hw)) {
5054 e_dev_err("EEPROM initialization failed\n");
5058 /* PF holds first pool slot */
5059 set_bit(0, &adapter->fwd_bitmask);
5060 set_bit(__IXGBE_DOWN, &adapter->state);
5066 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
5067 * @tx_ring: tx descriptor ring (for a specific queue) to setup
5069 * Return 0 on success, negative on failure
5071 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
5073 struct device *dev = tx_ring->dev;
5074 int orig_node = dev_to_node(dev);
5078 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5080 if (tx_ring->q_vector)
5081 numa_node = tx_ring->q_vector->numa_node;
5083 tx_ring->tx_buffer_info = vzalloc_node(size, numa_node);
5084 if (!tx_ring->tx_buffer_info)
5085 tx_ring->tx_buffer_info = vzalloc(size);
5086 if (!tx_ring->tx_buffer_info)
5089 u64_stats_init(&tx_ring->syncp);
5091 /* round up to nearest 4K */
5092 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
5093 tx_ring->size = ALIGN(tx_ring->size, 4096);
5095 set_dev_node(dev, numa_node);
5096 tx_ring->desc = dma_alloc_coherent(dev,
5100 set_dev_node(dev, orig_node);
5102 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5103 &tx_ring->dma, GFP_KERNEL);
5107 tx_ring->next_to_use = 0;
5108 tx_ring->next_to_clean = 0;
5112 vfree(tx_ring->tx_buffer_info);
5113 tx_ring->tx_buffer_info = NULL;
5114 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
5119 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5120 * @adapter: board private structure
5122 * If this function returns with an error, then it's possible one or
5123 * more of the rings is populated (while the rest are not). It is the
5124 * callers duty to clean those orphaned rings.
5126 * Return 0 on success, negative on failure
5128 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5132 for (i = 0; i < adapter->num_tx_queues; i++) {
5133 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
5137 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
5143 /* rewind the index freeing the rings as we go */
5145 ixgbe_free_tx_resources(adapter->tx_ring[i]);
5150 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5151 * @rx_ring: rx descriptor ring (for a specific queue) to setup
5153 * Returns 0 on success, negative on failure
5155 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
5157 struct device *dev = rx_ring->dev;
5158 int orig_node = dev_to_node(dev);
5162 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5164 if (rx_ring->q_vector)
5165 numa_node = rx_ring->q_vector->numa_node;
5167 rx_ring->rx_buffer_info = vzalloc_node(size, numa_node);
5168 if (!rx_ring->rx_buffer_info)
5169 rx_ring->rx_buffer_info = vzalloc(size);
5170 if (!rx_ring->rx_buffer_info)
5173 u64_stats_init(&rx_ring->syncp);
5175 /* Round up to nearest 4K */
5176 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5177 rx_ring->size = ALIGN(rx_ring->size, 4096);
5179 set_dev_node(dev, numa_node);
5180 rx_ring->desc = dma_alloc_coherent(dev,
5184 set_dev_node(dev, orig_node);
5186 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5187 &rx_ring->dma, GFP_KERNEL);
5191 rx_ring->next_to_clean = 0;
5192 rx_ring->next_to_use = 0;
5196 vfree(rx_ring->rx_buffer_info);
5197 rx_ring->rx_buffer_info = NULL;
5198 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5203 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5204 * @adapter: board private structure
5206 * If this function returns with an error, then it's possible one or
5207 * more of the rings is populated (while the rest are not). It is the
5208 * callers duty to clean those orphaned rings.
5210 * Return 0 on success, negative on failure
5212 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5216 for (i = 0; i < adapter->num_rx_queues; i++) {
5217 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5221 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5226 err = ixgbe_setup_fcoe_ddp_resources(adapter);
5231 /* rewind the index freeing the rings as we go */
5233 ixgbe_free_rx_resources(adapter->rx_ring[i]);
5238 * ixgbe_free_tx_resources - Free Tx Resources per Queue
5239 * @tx_ring: Tx descriptor ring for a specific queue
5241 * Free all transmit software resources
5243 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5245 ixgbe_clean_tx_ring(tx_ring);
5247 vfree(tx_ring->tx_buffer_info);
5248 tx_ring->tx_buffer_info = NULL;
5250 /* if not set, then don't free */
5254 dma_free_coherent(tx_ring->dev, tx_ring->size,
5255 tx_ring->desc, tx_ring->dma);
5257 tx_ring->desc = NULL;
5261 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5262 * @adapter: board private structure
5264 * Free all transmit software resources
5266 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5270 for (i = 0; i < adapter->num_tx_queues; i++)
5271 if (adapter->tx_ring[i]->desc)
5272 ixgbe_free_tx_resources(adapter->tx_ring[i]);
5276 * ixgbe_free_rx_resources - Free Rx Resources
5277 * @rx_ring: ring to clean the resources from
5279 * Free all receive software resources
5281 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5283 ixgbe_clean_rx_ring(rx_ring);
5285 vfree(rx_ring->rx_buffer_info);
5286 rx_ring->rx_buffer_info = NULL;
5288 /* if not set, then don't free */
5292 dma_free_coherent(rx_ring->dev, rx_ring->size,
5293 rx_ring->desc, rx_ring->dma);
5295 rx_ring->desc = NULL;
5299 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5300 * @adapter: board private structure
5302 * Free all receive software resources
5304 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5309 ixgbe_free_fcoe_ddp_resources(adapter);
5312 for (i = 0; i < adapter->num_rx_queues; i++)
5313 if (adapter->rx_ring[i]->desc)
5314 ixgbe_free_rx_resources(adapter->rx_ring[i]);
5318 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5319 * @netdev: network interface device structure
5320 * @new_mtu: new value for maximum frame size
5322 * Returns 0 on success, negative on failure
5324 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5326 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5327 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5329 /* MTU < 68 is an error and causes problems on some kernels */
5330 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5334 * For 82599EB we cannot allow legacy VFs to enable their receive
5335 * paths when MTU greater than 1500 is configured. So display a
5336 * warning that legacy VFs will be disabled.
5338 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
5339 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
5340 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)))
5341 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
5343 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5345 /* must set new MTU before calling down or up */
5346 netdev->mtu = new_mtu;
5348 if (netif_running(netdev))
5349 ixgbe_reinit_locked(adapter);
5355 * ixgbe_open - Called when a network interface is made active
5356 * @netdev: network interface device structure
5358 * Returns 0 on success, negative value on failure
5360 * The open entry point is called when a network interface is made
5361 * active by the system (IFF_UP). At this point all resources needed
5362 * for transmit and receive operations are allocated, the interrupt
5363 * handler is registered with the OS, the watchdog timer is started,
5364 * and the stack is notified that the interface is ready.
5366 static int ixgbe_open(struct net_device *netdev)
5368 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5371 /* disallow open during test */
5372 if (test_bit(__IXGBE_TESTING, &adapter->state))
5375 netif_carrier_off(netdev);
5377 /* allocate transmit descriptors */
5378 err = ixgbe_setup_all_tx_resources(adapter);
5382 /* allocate receive descriptors */
5383 err = ixgbe_setup_all_rx_resources(adapter);
5387 ixgbe_configure(adapter);
5389 err = ixgbe_request_irq(adapter);
5393 /* Notify the stack of the actual queue counts. */
5394 if (adapter->num_rx_pools > 1)
5395 queues = adapter->num_rx_queues_per_pool;
5397 queues = adapter->num_tx_queues;
5399 err = netif_set_real_num_tx_queues(netdev, queues);
5401 goto err_set_queues;
5403 if (adapter->num_rx_pools > 1 &&
5404 adapter->num_rx_queues > IXGBE_MAX_L2A_QUEUES)
5405 queues = IXGBE_MAX_L2A_QUEUES;
5407 queues = adapter->num_rx_queues;
5408 err = netif_set_real_num_rx_queues(netdev, queues);
5410 goto err_set_queues;
5412 ixgbe_ptp_init(adapter);
5414 ixgbe_up_complete(adapter);
5419 ixgbe_free_irq(adapter);
5421 ixgbe_free_all_rx_resources(adapter);
5423 ixgbe_free_all_tx_resources(adapter);
5425 ixgbe_reset(adapter);
5431 * ixgbe_close - Disables a network interface
5432 * @netdev: network interface device structure
5434 * Returns 0, this is not allowed to fail
5436 * The close entry point is called when an interface is de-activated
5437 * by the OS. The hardware is still under the drivers control, but
5438 * needs to be disabled. A global MAC reset is issued to stop the
5439 * hardware, and all transmit and receive resources are freed.
5441 static int ixgbe_close(struct net_device *netdev)
5443 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5445 ixgbe_ptp_stop(adapter);
5447 ixgbe_down(adapter);
5448 ixgbe_free_irq(adapter);
5450 ixgbe_fdir_filter_exit(adapter);
5452 ixgbe_free_all_tx_resources(adapter);
5453 ixgbe_free_all_rx_resources(adapter);
5455 ixgbe_release_hw_control(adapter);
5461 static int ixgbe_resume(struct pci_dev *pdev)
5463 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5464 struct net_device *netdev = adapter->netdev;
5467 pci_set_power_state(pdev, PCI_D0);
5468 pci_restore_state(pdev);
5470 * pci_restore_state clears dev->state_saved so call
5471 * pci_save_state to restore it.
5473 pci_save_state(pdev);
5475 err = pci_enable_device_mem(pdev);
5477 e_dev_err("Cannot enable PCI device from suspend\n");
5480 pci_set_master(pdev);
5482 pci_wake_from_d3(pdev, false);
5484 ixgbe_reset(adapter);
5486 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5489 err = ixgbe_init_interrupt_scheme(adapter);
5490 if (!err && netif_running(netdev))
5491 err = ixgbe_open(netdev);
5498 netif_device_attach(netdev);
5502 #endif /* CONFIG_PM */
5504 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5506 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5507 struct net_device *netdev = adapter->netdev;
5508 struct ixgbe_hw *hw = &adapter->hw;
5510 u32 wufc = adapter->wol;
5515 netif_device_detach(netdev);
5518 if (netif_running(netdev)) {
5519 ixgbe_down(adapter);
5520 ixgbe_free_irq(adapter);
5521 ixgbe_free_all_tx_resources(adapter);
5522 ixgbe_free_all_rx_resources(adapter);
5526 ixgbe_clear_interrupt_scheme(adapter);
5529 retval = pci_save_state(pdev);
5534 if (hw->mac.ops.stop_link_on_d3)
5535 hw->mac.ops.stop_link_on_d3(hw);
5538 ixgbe_set_rx_mode(netdev);
5540 /* enable the optics for 82599 SFP+ fiber as we can WoL */
5541 if (hw->mac.ops.enable_tx_laser)
5542 hw->mac.ops.enable_tx_laser(hw);
5544 /* turn on all-multi mode if wake on multicast is enabled */
5545 if (wufc & IXGBE_WUFC_MC) {
5546 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5547 fctrl |= IXGBE_FCTRL_MPE;
5548 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5551 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5552 ctrl |= IXGBE_CTRL_GIO_DIS;
5553 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5555 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5557 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5558 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5561 switch (hw->mac.type) {
5562 case ixgbe_mac_82598EB:
5563 pci_wake_from_d3(pdev, false);
5565 case ixgbe_mac_82599EB:
5566 case ixgbe_mac_X540:
5567 pci_wake_from_d3(pdev, !!wufc);
5573 *enable_wake = !!wufc;
5575 ixgbe_release_hw_control(adapter);
5577 pci_disable_device(pdev);
5583 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5588 retval = __ixgbe_shutdown(pdev, &wake);
5593 pci_prepare_to_sleep(pdev);
5595 pci_wake_from_d3(pdev, false);
5596 pci_set_power_state(pdev, PCI_D3hot);
5601 #endif /* CONFIG_PM */
5603 static void ixgbe_shutdown(struct pci_dev *pdev)
5607 __ixgbe_shutdown(pdev, &wake);
5609 if (system_state == SYSTEM_POWER_OFF) {
5610 pci_wake_from_d3(pdev, wake);
5611 pci_set_power_state(pdev, PCI_D3hot);
5616 * ixgbe_update_stats - Update the board statistics counters.
5617 * @adapter: board private structure
5619 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5621 struct net_device *netdev = adapter->netdev;
5622 struct ixgbe_hw *hw = &adapter->hw;
5623 struct ixgbe_hw_stats *hwstats = &adapter->stats;
5625 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5626 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5627 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5628 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
5630 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5631 test_bit(__IXGBE_RESETTING, &adapter->state))
5634 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5637 for (i = 0; i < adapter->num_rx_queues; i++) {
5638 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5639 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5641 adapter->rsc_total_count = rsc_count;
5642 adapter->rsc_total_flush = rsc_flush;
5645 for (i = 0; i < adapter->num_rx_queues; i++) {
5646 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5647 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5648 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5649 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5650 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5651 bytes += rx_ring->stats.bytes;
5652 packets += rx_ring->stats.packets;
5654 adapter->non_eop_descs = non_eop_descs;
5655 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5656 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5657 adapter->hw_csum_rx_error = hw_csum_rx_error;
5658 netdev->stats.rx_bytes = bytes;
5659 netdev->stats.rx_packets = packets;
5663 /* gather some stats to the adapter struct that are per queue */
5664 for (i = 0; i < adapter->num_tx_queues; i++) {
5665 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5666 restart_queue += tx_ring->tx_stats.restart_queue;
5667 tx_busy += tx_ring->tx_stats.tx_busy;
5668 bytes += tx_ring->stats.bytes;
5669 packets += tx_ring->stats.packets;
5671 adapter->restart_queue = restart_queue;
5672 adapter->tx_busy = tx_busy;
5673 netdev->stats.tx_bytes = bytes;
5674 netdev->stats.tx_packets = packets;
5676 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5678 /* 8 register reads */
5679 for (i = 0; i < 8; i++) {
5680 /* for packet buffers not used, the register should read 0 */
5681 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5683 hwstats->mpc[i] += mpc;
5684 total_mpc += hwstats->mpc[i];
5685 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5686 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5687 switch (hw->mac.type) {
5688 case ixgbe_mac_82598EB:
5689 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5690 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5691 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5692 hwstats->pxonrxc[i] +=
5693 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5695 case ixgbe_mac_82599EB:
5696 case ixgbe_mac_X540:
5697 hwstats->pxonrxc[i] +=
5698 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5705 /*16 register reads */
5706 for (i = 0; i < 16; i++) {
5707 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5708 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5709 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5710 (hw->mac.type == ixgbe_mac_X540)) {
5711 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5712 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5713 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5714 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5718 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5719 /* work around hardware counting issue */
5720 hwstats->gprc -= missed_rx;
5722 ixgbe_update_xoff_received(adapter);
5724 /* 82598 hardware only has a 32 bit counter in the high register */
5725 switch (hw->mac.type) {
5726 case ixgbe_mac_82598EB:
5727 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5728 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5729 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5730 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5732 case ixgbe_mac_X540:
5733 /* OS2BMC stats are X540 only*/
5734 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5735 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5736 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5737 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5738 case ixgbe_mac_82599EB:
5739 for (i = 0; i < 16; i++)
5740 adapter->hw_rx_no_dma_resources +=
5741 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5742 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5743 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5744 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5745 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5746 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5747 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5748 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5749 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5750 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5752 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5753 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5754 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5755 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5756 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5757 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5758 /* Add up per cpu counters for total ddp aloc fail */
5759 if (adapter->fcoe.ddp_pool) {
5760 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5761 struct ixgbe_fcoe_ddp_pool *ddp_pool;
5763 u64 noddp = 0, noddp_ext_buff = 0;
5764 for_each_possible_cpu(cpu) {
5765 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
5766 noddp += ddp_pool->noddp;
5767 noddp_ext_buff += ddp_pool->noddp_ext_buff;
5769 hwstats->fcoe_noddp = noddp;
5770 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
5772 #endif /* IXGBE_FCOE */
5777 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5778 hwstats->bprc += bprc;
5779 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5780 if (hw->mac.type == ixgbe_mac_82598EB)
5781 hwstats->mprc -= bprc;
5782 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5783 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5784 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5785 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5786 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5787 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5788 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5789 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5790 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5791 hwstats->lxontxc += lxon;
5792 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5793 hwstats->lxofftxc += lxoff;
5794 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5795 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5797 * 82598 errata - tx of flow control packets is included in tx counters
5799 xon_off_tot = lxon + lxoff;
5800 hwstats->gptc -= xon_off_tot;
5801 hwstats->mptc -= xon_off_tot;
5802 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5803 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5804 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5805 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5806 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5807 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5808 hwstats->ptc64 -= xon_off_tot;
5809 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5810 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5811 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5812 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5813 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5814 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5816 /* Fill out the OS statistics structure */
5817 netdev->stats.multicast = hwstats->mprc;
5820 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5821 netdev->stats.rx_dropped = 0;
5822 netdev->stats.rx_length_errors = hwstats->rlec;
5823 netdev->stats.rx_crc_errors = hwstats->crcerrs;
5824 netdev->stats.rx_missed_errors = total_mpc;
5828 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5829 * @adapter: pointer to the device adapter structure
5831 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
5833 struct ixgbe_hw *hw = &adapter->hw;
5836 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5839 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
5841 /* if interface is down do nothing */
5842 if (test_bit(__IXGBE_DOWN, &adapter->state))
5845 /* do nothing if we are not using signature filters */
5846 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5849 adapter->fdir_overflow++;
5851 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5852 for (i = 0; i < adapter->num_tx_queues; i++)
5853 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5854 &(adapter->tx_ring[i]->state));
5855 /* re-enable flow director interrupts */
5856 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
5858 e_err(probe, "failed to finish FDIR re-initialization, "
5859 "ignored adding FDIR ATR filters\n");
5864 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5865 * @adapter: pointer to the device adapter structure
5867 * This function serves two purposes. First it strobes the interrupt lines
5868 * in order to make certain interrupts are occurring. Secondly it sets the
5869 * bits needed to check for TX hangs. As a result we should immediately
5870 * determine if a hang has occurred.
5872 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
5874 struct ixgbe_hw *hw = &adapter->hw;
5878 /* If we're down, removing or resetting, just bail */
5879 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5880 test_bit(__IXGBE_REMOVING, &adapter->state) ||
5881 test_bit(__IXGBE_RESETTING, &adapter->state))
5884 /* Force detection of hung controller */
5885 if (netif_carrier_ok(adapter->netdev)) {
5886 for (i = 0; i < adapter->num_tx_queues; i++)
5887 set_check_for_tx_hang(adapter->tx_ring[i]);
5890 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5892 * for legacy and MSI interrupts don't set any bits
5893 * that are enabled for EIAM, because this operation
5894 * would set *both* EIMS and EICS for any bit in EIAM
5896 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5897 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5899 /* get one bit for every active tx/rx interrupt vector */
5900 for (i = 0; i < adapter->num_q_vectors; i++) {
5901 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5902 if (qv->rx.ring || qv->tx.ring)
5903 eics |= ((u64)1 << i);
5907 /* Cause software interrupt to ensure rings are cleaned */
5908 ixgbe_irq_rearm_queues(adapter, eics);
5913 * ixgbe_watchdog_update_link - update the link status
5914 * @adapter: pointer to the device adapter structure
5915 * @link_speed: pointer to a u32 to store the link_speed
5917 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
5919 struct ixgbe_hw *hw = &adapter->hw;
5920 u32 link_speed = adapter->link_speed;
5921 bool link_up = adapter->link_up;
5922 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
5924 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5927 if (hw->mac.ops.check_link) {
5928 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5930 /* always assume link is up, if no check link function */
5931 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5935 if (adapter->ixgbe_ieee_pfc)
5936 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
5938 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
5939 hw->mac.ops.fc_enable(hw);
5940 ixgbe_set_rx_drop_en(adapter);
5944 time_after(jiffies, (adapter->link_check_timeout +
5945 IXGBE_TRY_LINK_TIMEOUT))) {
5946 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5947 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5948 IXGBE_WRITE_FLUSH(hw);
5951 adapter->link_up = link_up;
5952 adapter->link_speed = link_speed;
5955 static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
5957 #ifdef CONFIG_IXGBE_DCB
5958 struct net_device *netdev = adapter->netdev;
5959 struct dcb_app app = {
5960 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
5965 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
5966 up = dcb_ieee_getapp_mask(netdev, &app);
5968 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
5973 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5974 * print link up message
5975 * @adapter: pointer to the device adapter structure
5977 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
5979 struct net_device *netdev = adapter->netdev;
5980 struct ixgbe_hw *hw = &adapter->hw;
5981 u32 link_speed = adapter->link_speed;
5982 bool flow_rx, flow_tx;
5984 /* only continue if link was previously down */
5985 if (netif_carrier_ok(netdev))
5988 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
5990 switch (hw->mac.type) {
5991 case ixgbe_mac_82598EB: {
5992 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5993 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5994 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5995 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5998 case ixgbe_mac_X540:
5999 case ixgbe_mac_82599EB: {
6000 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6001 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6002 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6003 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6012 adapter->last_rx_ptp_check = jiffies;
6014 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
6015 ixgbe_ptp_start_cyclecounter(adapter);
6017 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
6018 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
6020 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6022 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
6025 ((flow_rx && flow_tx) ? "RX/TX" :
6027 (flow_tx ? "TX" : "None"))));
6029 netif_carrier_on(netdev);
6030 ixgbe_check_vf_rate_limit(adapter);
6032 /* update the default user priority for VFs */
6033 ixgbe_update_default_up(adapter);
6035 /* ping all the active vfs to let them know link has changed */
6036 ixgbe_ping_all_vfs(adapter);
6040 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6041 * print link down message
6042 * @adapter: pointer to the adapter structure
6044 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
6046 struct net_device *netdev = adapter->netdev;
6047 struct ixgbe_hw *hw = &adapter->hw;
6049 adapter->link_up = false;
6050 adapter->link_speed = 0;
6052 /* only continue if link was up previously */
6053 if (!netif_carrier_ok(netdev))
6056 /* poll for SFP+ cable when link is down */
6057 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6058 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
6060 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
6061 ixgbe_ptp_start_cyclecounter(adapter);
6063 e_info(drv, "NIC Link is Down\n");
6064 netif_carrier_off(netdev);
6066 /* ping all the active vfs to let them know link has changed */
6067 ixgbe_ping_all_vfs(adapter);
6071 * ixgbe_watchdog_flush_tx - flush queues on link down
6072 * @adapter: pointer to the device adapter structure
6074 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6077 int some_tx_pending = 0;
6079 if (!netif_carrier_ok(adapter->netdev)) {
6080 for (i = 0; i < adapter->num_tx_queues; i++) {
6081 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6082 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
6083 some_tx_pending = 1;
6088 if (some_tx_pending) {
6089 /* We've lost link, so the controller stops DMA,
6090 * but we've got queued Tx work that's never going
6091 * to get done, so reset controller to flush Tx.
6092 * (Do the reset outside of interrupt context).
6094 e_warn(drv, "initiating reset to clear Tx work after link loss\n");
6095 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
6100 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6104 /* Do not perform spoof check for 82598 or if not in IOV mode */
6105 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
6106 adapter->num_vfs == 0)
6109 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6112 * ssvpc register is cleared on read, if zero then no
6113 * spoofed packets in the last interval.
6118 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
6122 * ixgbe_watchdog_subtask - check and bring link up
6123 * @adapter: pointer to the device adapter structure
6125 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6127 /* if interface is down, removing or resetting, do nothing */
6128 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6129 test_bit(__IXGBE_REMOVING, &adapter->state) ||
6130 test_bit(__IXGBE_RESETTING, &adapter->state))
6133 ixgbe_watchdog_update_link(adapter);
6135 if (adapter->link_up)
6136 ixgbe_watchdog_link_is_up(adapter);
6138 ixgbe_watchdog_link_is_down(adapter);
6140 ixgbe_spoof_check(adapter);
6141 ixgbe_update_stats(adapter);
6143 ixgbe_watchdog_flush_tx(adapter);
6147 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
6148 * @adapter: the ixgbe adapter structure
6150 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
6152 struct ixgbe_hw *hw = &adapter->hw;
6155 /* not searching for SFP so there is nothing to do here */
6156 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6157 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6160 /* someone else is in init, wait until next service event */
6161 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6164 err = hw->phy.ops.identify_sfp(hw);
6165 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6168 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6169 /* If no cable is present, then we need to reset
6170 * the next time we find a good cable. */
6171 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
6178 /* exit if reset not needed */
6179 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6182 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
6185 * A module may be identified correctly, but the EEPROM may not have
6186 * support for that module. setup_sfp() will fail in that case, so
6187 * we should not allow that module to load.
6189 if (hw->mac.type == ixgbe_mac_82598EB)
6190 err = hw->phy.ops.reset(hw);
6192 err = hw->mac.ops.setup_sfp(hw);
6194 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6197 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6198 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6201 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6203 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6204 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6205 e_dev_err("failed to initialize because an unsupported "
6206 "SFP+ module type was detected.\n");
6207 e_dev_err("Reload the driver after installing a "
6208 "supported module.\n");
6209 unregister_netdev(adapter->netdev);
6214 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
6215 * @adapter: the ixgbe adapter structure
6217 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6219 struct ixgbe_hw *hw = &adapter->hw;
6221 bool autoneg = false;
6223 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6226 /* someone else is in init, wait until next service event */
6227 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6230 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6232 speed = hw->phy.autoneg_advertised;
6233 if ((!speed) && (hw->mac.ops.get_link_capabilities)) {
6234 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg);
6236 /* setup the highest link when no autoneg */
6238 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
6239 speed = IXGBE_LINK_SPEED_10GB_FULL;
6243 if (hw->mac.ops.setup_link)
6244 hw->mac.ops.setup_link(hw, speed, true);
6246 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6247 adapter->link_check_timeout = jiffies;
6248 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6251 #ifdef CONFIG_PCI_IOV
6252 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
6255 struct ixgbe_hw *hw = &adapter->hw;
6256 struct net_device *netdev = adapter->netdev;
6260 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
6261 if (gpc) /* If incrementing then no need for the check below */
6264 * Check to see if a bad DMA write target from an errant or
6265 * malicious VF has caused a PCIe error. If so then we can
6266 * issue a VFLR to the offending VF(s) and then resume without
6267 * requesting a full slot reset.
6270 for (vf = 0; vf < adapter->num_vfs; vf++) {
6271 ciaa = (vf << 16) | 0x80000000;
6272 /* 32 bit read so align, we really want status at offset 6 */
6273 ciaa |= PCI_COMMAND;
6274 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6275 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
6277 /* disable debug mode asap after reading data */
6278 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6279 /* Get the upper 16 bits which will be the PCI status reg */
6281 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
6282 netdev_err(netdev, "VF %d Hung DMA\n", vf);
6284 ciaa = (vf << 16) | 0x80000000;
6286 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6287 ciad = 0x00008000; /* VFLR */
6288 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
6290 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6297 * ixgbe_service_timer - Timer Call-back
6298 * @data: pointer to adapter cast into an unsigned long
6300 static void ixgbe_service_timer(unsigned long data)
6302 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6303 unsigned long next_event_offset;
6306 /* poll faster when waiting for link */
6307 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6308 next_event_offset = HZ / 10;
6310 next_event_offset = HZ * 2;
6312 #ifdef CONFIG_PCI_IOV
6314 * don't bother with SR-IOV VF DMA hang check if there are
6315 * no VFs or the link is down
6317 if (!adapter->num_vfs ||
6318 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6319 goto normal_timer_service;
6321 /* If we have VFs allocated then we must check for DMA hangs */
6322 ixgbe_check_for_bad_vf(adapter);
6323 next_event_offset = HZ / 50;
6324 adapter->timer_event_accumulator++;
6326 if (adapter->timer_event_accumulator >= 100)
6327 adapter->timer_event_accumulator = 0;
6331 normal_timer_service:
6333 /* Reset the timer */
6334 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6337 ixgbe_service_event_schedule(adapter);
6340 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6342 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6345 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6347 /* If we're already down, removing or resetting, just bail */
6348 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6349 test_bit(__IXGBE_REMOVING, &adapter->state) ||
6350 test_bit(__IXGBE_RESETTING, &adapter->state))
6353 ixgbe_dump(adapter);
6354 netdev_err(adapter->netdev, "Reset adapter\n");
6355 adapter->tx_timeout_count++;
6357 ixgbe_reinit_locked(adapter);
6361 * ixgbe_service_task - manages and runs subtasks
6362 * @work: pointer to work_struct containing our data
6364 static void ixgbe_service_task(struct work_struct *work)
6366 struct ixgbe_adapter *adapter = container_of(work,
6367 struct ixgbe_adapter,
6369 ixgbe_reset_subtask(adapter);
6370 ixgbe_sfp_detection_subtask(adapter);
6371 ixgbe_sfp_link_config_subtask(adapter);
6372 ixgbe_check_overtemp_subtask(adapter);
6373 ixgbe_watchdog_subtask(adapter);
6374 ixgbe_fdir_reinit_subtask(adapter);
6375 ixgbe_check_hang_subtask(adapter);
6377 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) {
6378 ixgbe_ptp_overflow_check(adapter);
6379 ixgbe_ptp_rx_hang(adapter);
6382 ixgbe_service_event_complete(adapter);
6385 static int ixgbe_tso(struct ixgbe_ring *tx_ring,
6386 struct ixgbe_tx_buffer *first,
6389 struct sk_buff *skb = first->skb;
6390 u32 vlan_macip_lens, type_tucmd;
6391 u32 mss_l4len_idx, l4len;
6393 if (skb->ip_summed != CHECKSUM_PARTIAL)
6396 if (!skb_is_gso(skb))
6399 if (skb_header_cloned(skb)) {
6400 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6405 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6406 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6408 if (first->protocol == __constant_htons(ETH_P_IP)) {
6409 struct iphdr *iph = ip_hdr(skb);
6412 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6416 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6417 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6418 IXGBE_TX_FLAGS_CSUM |
6419 IXGBE_TX_FLAGS_IPV4;
6420 } else if (skb_is_gso_v6(skb)) {
6421 ipv6_hdr(skb)->payload_len = 0;
6422 tcp_hdr(skb)->check =
6423 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6424 &ipv6_hdr(skb)->daddr,
6426 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6427 IXGBE_TX_FLAGS_CSUM;
6430 /* compute header lengths */
6431 l4len = tcp_hdrlen(skb);
6432 *hdr_len = skb_transport_offset(skb) + l4len;
6434 /* update gso size and bytecount with header size */
6435 first->gso_segs = skb_shinfo(skb)->gso_segs;
6436 first->bytecount += (first->gso_segs - 1) * *hdr_len;
6438 /* mss_l4len_id: use 0 as index for TSO */
6439 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6440 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
6442 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6443 vlan_macip_lens = skb_network_header_len(skb);
6444 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6445 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6447 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
6453 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6454 struct ixgbe_tx_buffer *first)
6456 struct sk_buff *skb = first->skb;
6457 u32 vlan_macip_lens = 0;
6458 u32 mss_l4len_idx = 0;
6461 if (skb->ip_summed != CHECKSUM_PARTIAL) {
6462 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6463 !(first->tx_flags & IXGBE_TX_FLAGS_CC))
6467 switch (first->protocol) {
6468 case __constant_htons(ETH_P_IP):
6469 vlan_macip_lens |= skb_network_header_len(skb);
6470 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6471 l4_hdr = ip_hdr(skb)->protocol;
6473 case __constant_htons(ETH_P_IPV6):
6474 vlan_macip_lens |= skb_network_header_len(skb);
6475 l4_hdr = ipv6_hdr(skb)->nexthdr;
6478 if (unlikely(net_ratelimit())) {
6479 dev_warn(tx_ring->dev,
6480 "partial checksum but proto=%x!\n",
6488 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6489 mss_l4len_idx = tcp_hdrlen(skb) <<
6490 IXGBE_ADVTXD_L4LEN_SHIFT;
6493 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6494 mss_l4len_idx = sizeof(struct sctphdr) <<
6495 IXGBE_ADVTXD_L4LEN_SHIFT;
6498 mss_l4len_idx = sizeof(struct udphdr) <<
6499 IXGBE_ADVTXD_L4LEN_SHIFT;
6502 if (unlikely(net_ratelimit())) {
6503 dev_warn(tx_ring->dev,
6504 "partial checksum but l4 proto=%x!\n",
6510 /* update TX checksum flag */
6511 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
6514 /* vlan_macip_lens: MACLEN, VLAN tag */
6515 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6516 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6518 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6519 type_tucmd, mss_l4len_idx);
6522 #define IXGBE_SET_FLAG(_input, _flag, _result) \
6523 ((_flag <= _result) ? \
6524 ((u32)(_input & _flag) * (_result / _flag)) : \
6525 ((u32)(_input & _flag) / (_flag / _result)))
6527 static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
6529 /* set type for advanced descriptor with frame checksum insertion */
6530 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
6531 IXGBE_ADVTXD_DCMD_DEXT |
6532 IXGBE_ADVTXD_DCMD_IFCS;
6534 /* set HW vlan bit if vlan is present */
6535 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN,
6536 IXGBE_ADVTXD_DCMD_VLE);
6538 /* set segmentation enable bits for TSO/FSO */
6539 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO,
6540 IXGBE_ADVTXD_DCMD_TSE);
6542 /* set timestamp bit if present */
6543 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP,
6544 IXGBE_ADVTXD_MAC_TSTAMP);
6546 /* insert frame checksum */
6547 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS);
6552 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
6553 u32 tx_flags, unsigned int paylen)
6555 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
6557 /* enable L4 checksum for TSO and TX checksum offload */
6558 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6559 IXGBE_TX_FLAGS_CSUM,
6560 IXGBE_ADVTXD_POPTS_TXSM);
6562 /* enble IPv4 checksum for TSO */
6563 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6564 IXGBE_TX_FLAGS_IPV4,
6565 IXGBE_ADVTXD_POPTS_IXSM);
6568 * Check Context must be set if Tx switch is enabled, which it
6569 * always is for case where virtual functions are running
6571 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6575 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6578 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6581 static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
6582 struct ixgbe_tx_buffer *first,
6585 struct sk_buff *skb = first->skb;
6586 struct ixgbe_tx_buffer *tx_buffer;
6587 union ixgbe_adv_tx_desc *tx_desc;
6588 struct skb_frag_struct *frag;
6590 unsigned int data_len, size;
6591 u32 tx_flags = first->tx_flags;
6592 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags);
6593 u16 i = tx_ring->next_to_use;
6595 tx_desc = IXGBE_TX_DESC(tx_ring, i);
6597 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
6599 size = skb_headlen(skb);
6600 data_len = skb->data_len;
6603 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6604 if (data_len < sizeof(struct fcoe_crc_eof)) {
6605 size -= sizeof(struct fcoe_crc_eof) - data_len;
6608 data_len -= sizeof(struct fcoe_crc_eof);
6613 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
6617 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
6618 if (dma_mapping_error(tx_ring->dev, dma))
6621 /* record length, and DMA address */
6622 dma_unmap_len_set(tx_buffer, len, size);
6623 dma_unmap_addr_set(tx_buffer, dma, dma);
6625 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6627 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
6628 tx_desc->read.cmd_type_len =
6629 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD);
6633 if (i == tx_ring->count) {
6634 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6637 tx_desc->read.olinfo_status = 0;
6639 dma += IXGBE_MAX_DATA_PER_TXD;
6640 size -= IXGBE_MAX_DATA_PER_TXD;
6642 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6645 if (likely(!data_len))
6648 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
6652 if (i == tx_ring->count) {
6653 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6656 tx_desc->read.olinfo_status = 0;
6659 size = min_t(unsigned int, data_len, skb_frag_size(frag));
6661 size = skb_frag_size(frag);
6665 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
6668 tx_buffer = &tx_ring->tx_buffer_info[i];
6671 /* write last descriptor with RS and EOP bits */
6672 cmd_type |= size | IXGBE_TXD_CMD;
6673 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
6675 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
6677 /* set the timestamp */
6678 first->time_stamp = jiffies;
6681 * Force memory writes to complete before letting h/w know there
6682 * are new descriptors to fetch. (Only applicable for weak-ordered
6683 * memory model archs, such as IA-64).
6685 * We also need this memory barrier to make certain all of the
6686 * status bits have been updated before next_to_watch is written.
6690 /* set next_to_watch value indicating a packet is present */
6691 first->next_to_watch = tx_desc;
6694 if (i == tx_ring->count)
6697 tx_ring->next_to_use = i;
6699 /* notify HW of packet */
6700 writel(i, tx_ring->tail);
6704 dev_err(tx_ring->dev, "TX DMA map failed\n");
6706 /* clear dma mappings for failed tx_buffer_info map */
6708 tx_buffer = &tx_ring->tx_buffer_info[i];
6709 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
6710 if (tx_buffer == first)
6717 tx_ring->next_to_use = i;
6720 static void ixgbe_atr(struct ixgbe_ring *ring,
6721 struct ixgbe_tx_buffer *first)
6723 struct ixgbe_q_vector *q_vector = ring->q_vector;
6724 union ixgbe_atr_hash_dword input = { .dword = 0 };
6725 union ixgbe_atr_hash_dword common = { .dword = 0 };
6727 unsigned char *network;
6729 struct ipv6hdr *ipv6;
6734 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6738 /* do nothing if sampling is disabled */
6739 if (!ring->atr_sample_rate)
6744 /* snag network header to get L4 type and address */
6745 hdr.network = skb_network_header(first->skb);
6747 /* Currently only IPv4/IPv6 with TCP is supported */
6748 if ((first->protocol != __constant_htons(ETH_P_IPV6) ||
6749 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6750 (first->protocol != __constant_htons(ETH_P_IP) ||
6751 hdr.ipv4->protocol != IPPROTO_TCP))
6754 th = tcp_hdr(first->skb);
6756 /* skip this packet since it is invalid or the socket is closing */
6760 /* sample on all syn packets or once every atr sample count */
6761 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6764 /* reset sample count */
6765 ring->atr_count = 0;
6767 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6770 * src and dst are inverted, think how the receiver sees them
6772 * The input is broken into two sections, a non-compressed section
6773 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6774 * is XORed together and stored in the compressed dword.
6776 input.formatted.vlan_id = vlan_id;
6779 * since src port and flex bytes occupy the same word XOR them together
6780 * and write the value to source port portion of compressed dword
6782 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
6783 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6785 common.port.src ^= th->dest ^ first->protocol;
6786 common.port.dst ^= th->source;
6788 if (first->protocol == __constant_htons(ETH_P_IP)) {
6789 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6790 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6792 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6793 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6794 hdr.ipv6->saddr.s6_addr32[1] ^
6795 hdr.ipv6->saddr.s6_addr32[2] ^
6796 hdr.ipv6->saddr.s6_addr32[3] ^
6797 hdr.ipv6->daddr.s6_addr32[0] ^
6798 hdr.ipv6->daddr.s6_addr32[1] ^
6799 hdr.ipv6->daddr.s6_addr32[2] ^
6800 hdr.ipv6->daddr.s6_addr32[3];
6803 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6804 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6805 input, common, ring->queue_index);
6808 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6810 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6811 /* Herbert's original patch had:
6812 * smp_mb__after_netif_stop_queue();
6813 * but since that doesn't exist yet, just open code it. */
6816 /* We need to check again in a case another CPU has just
6817 * made room available. */
6818 if (likely(ixgbe_desc_unused(tx_ring) < size))
6821 /* A reprieve! - use start_queue because it doesn't call schedule */
6822 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6823 ++tx_ring->tx_stats.restart_queue;
6827 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6829 if (likely(ixgbe_desc_unused(tx_ring) >= size))
6831 return __ixgbe_maybe_stop_tx(tx_ring, size);
6834 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb,
6837 struct ixgbe_fwd_adapter *fwd_adapter = accel_priv;
6839 struct ixgbe_adapter *adapter;
6840 struct ixgbe_ring_feature *f;
6845 return skb->queue_mapping + fwd_adapter->tx_base_queue;
6850 * only execute the code below if protocol is FCoE
6851 * or FIP and we have FCoE enabled on the adapter
6853 switch (vlan_get_protocol(skb)) {
6854 case __constant_htons(ETH_P_FCOE):
6855 case __constant_htons(ETH_P_FIP):
6856 adapter = netdev_priv(dev);
6858 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
6861 return __netdev_pick_tx(dev, skb);
6864 f = &adapter->ring_feature[RING_F_FCOE];
6866 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6869 while (txq >= f->indices)
6872 return txq + f->offset;
6874 return __netdev_pick_tx(dev, skb);
6878 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6879 struct ixgbe_adapter *adapter,
6880 struct ixgbe_ring *tx_ring)
6882 struct ixgbe_tx_buffer *first;
6886 u16 count = TXD_USE_COUNT(skb_headlen(skb));
6887 __be16 protocol = skb->protocol;
6891 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
6892 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
6893 * + 2 desc gap to keep tail from touching head,
6894 * + 1 desc for context descriptor,
6895 * otherwise try next time
6897 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6898 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6900 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6901 tx_ring->tx_stats.tx_busy++;
6902 return NETDEV_TX_BUSY;
6905 /* record the location of the first descriptor for this packet */
6906 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6908 first->bytecount = skb->len;
6909 first->gso_segs = 1;
6911 /* if we have a HW VLAN tag being added default to the HW one */
6912 if (vlan_tx_tag_present(skb)) {
6913 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6914 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6915 /* else if it is a SW VLAN check the next protocol and store the tag */
6916 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6917 struct vlan_hdr *vhdr, _vhdr;
6918 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6922 protocol = vhdr->h_vlan_encapsulated_proto;
6923 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
6924 IXGBE_TX_FLAGS_VLAN_SHIFT;
6925 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6928 skb_tx_timestamp(skb);
6930 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
6931 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
6932 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
6934 /* schedule check for Tx timestamp */
6935 adapter->ptp_tx_skb = skb_get(skb);
6936 adapter->ptp_tx_start = jiffies;
6937 schedule_work(&adapter->ptp_tx_work);
6940 #ifdef CONFIG_PCI_IOV
6942 * Use the l2switch_enable flag - would be false if the DMA
6943 * Tx switch had been disabled.
6945 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6946 tx_flags |= IXGBE_TX_FLAGS_CC;
6949 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
6950 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
6951 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
6952 (skb->priority != TC_PRIO_CONTROL))) {
6953 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6954 tx_flags |= (skb->priority & 0x7) <<
6955 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
6956 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6957 struct vlan_ethhdr *vhdr;
6958 if (skb_header_cloned(skb) &&
6959 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6961 vhdr = (struct vlan_ethhdr *)skb->data;
6962 vhdr->h_vlan_TCI = htons(tx_flags >>
6963 IXGBE_TX_FLAGS_VLAN_SHIFT);
6965 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6969 /* record initial flags and protocol */
6970 first->tx_flags = tx_flags;
6971 first->protocol = protocol;
6974 /* setup tx offload for FCoE */
6975 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
6976 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
6977 tso = ixgbe_fso(tx_ring, first, &hdr_len);
6984 #endif /* IXGBE_FCOE */
6985 tso = ixgbe_tso(tx_ring, first, &hdr_len);
6989 ixgbe_tx_csum(tx_ring, first);
6991 /* add the ATR filter if ATR is on */
6992 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6993 ixgbe_atr(tx_ring, first);
6997 #endif /* IXGBE_FCOE */
6998 ixgbe_tx_map(tx_ring, first, hdr_len);
7000 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
7002 return NETDEV_TX_OK;
7005 dev_kfree_skb_any(first->skb);
7008 return NETDEV_TX_OK;
7011 static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb,
7012 struct net_device *netdev,
7013 struct ixgbe_ring *ring)
7015 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7016 struct ixgbe_ring *tx_ring;
7019 * The minimum packet size for olinfo paylen is 17 so pad the skb
7020 * in order to meet this minimum size requirement.
7022 if (unlikely(skb->len < 17)) {
7023 if (skb_pad(skb, 17 - skb->len))
7024 return NETDEV_TX_OK;
7026 skb_set_tail_pointer(skb, 17);
7029 tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping];
7031 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
7034 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
7035 struct net_device *netdev)
7037 return __ixgbe_xmit_frame(skb, netdev, NULL);
7041 * ixgbe_set_mac - Change the Ethernet Address of the NIC
7042 * @netdev: network interface device structure
7043 * @p: pointer to an address structure
7045 * Returns 0 on success, negative on failure
7047 static int ixgbe_set_mac(struct net_device *netdev, void *p)
7049 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7050 struct ixgbe_hw *hw = &adapter->hw;
7051 struct sockaddr *addr = p;
7053 if (!is_valid_ether_addr(addr->sa_data))
7054 return -EADDRNOTAVAIL;
7056 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
7057 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
7059 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
7065 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
7067 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7068 struct ixgbe_hw *hw = &adapter->hw;
7072 if (prtad != hw->phy.mdio.prtad)
7074 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
7080 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
7081 u16 addr, u16 value)
7083 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7084 struct ixgbe_hw *hw = &adapter->hw;
7086 if (prtad != hw->phy.mdio.prtad)
7088 return hw->phy.ops.write_reg(hw, addr, devad, value);
7091 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
7093 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7097 return ixgbe_ptp_hwtstamp_ioctl(adapter, req, cmd);
7099 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
7104 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
7106 * @netdev: network interface device structure
7108 * Returns non-zero on failure
7110 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
7113 struct ixgbe_adapter *adapter = netdev_priv(dev);
7114 struct ixgbe_hw *hw = &adapter->hw;
7116 if (is_valid_ether_addr(hw->mac.san_addr)) {
7118 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
7121 /* update SAN MAC vmdq pool selection */
7122 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
7128 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
7130 * @netdev: network interface device structure
7132 * Returns non-zero on failure
7134 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
7137 struct ixgbe_adapter *adapter = netdev_priv(dev);
7138 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7140 if (is_valid_ether_addr(mac->san_addr)) {
7142 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7148 #ifdef CONFIG_NET_POLL_CONTROLLER
7150 * Polling 'interrupt' - used by things like netconsole to send skbs
7151 * without having to re-enable interrupts. It's not called while
7152 * the interrupt routine is executing.
7154 static void ixgbe_netpoll(struct net_device *netdev)
7156 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7159 /* if interface is down do nothing */
7160 if (test_bit(__IXGBE_DOWN, &adapter->state))
7163 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
7164 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
7165 for (i = 0; i < adapter->num_q_vectors; i++)
7166 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
7168 ixgbe_intr(adapter->pdev->irq, netdev);
7170 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
7174 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7175 struct rtnl_link_stats64 *stats)
7177 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7181 for (i = 0; i < adapter->num_rx_queues; i++) {
7182 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
7188 start = u64_stats_fetch_begin_bh(&ring->syncp);
7189 packets = ring->stats.packets;
7190 bytes = ring->stats.bytes;
7191 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7192 stats->rx_packets += packets;
7193 stats->rx_bytes += bytes;
7197 for (i = 0; i < adapter->num_tx_queues; i++) {
7198 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7204 start = u64_stats_fetch_begin_bh(&ring->syncp);
7205 packets = ring->stats.packets;
7206 bytes = ring->stats.bytes;
7207 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7208 stats->tx_packets += packets;
7209 stats->tx_bytes += bytes;
7213 /* following stats updated by ixgbe_watchdog_task() */
7214 stats->multicast = netdev->stats.multicast;
7215 stats->rx_errors = netdev->stats.rx_errors;
7216 stats->rx_length_errors = netdev->stats.rx_length_errors;
7217 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
7218 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7222 #ifdef CONFIG_IXGBE_DCB
7224 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7225 * @adapter: pointer to ixgbe_adapter
7226 * @tc: number of traffic classes currently enabled
7228 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7229 * 802.1Q priority maps to a packet buffer that exists.
7231 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
7233 struct ixgbe_hw *hw = &adapter->hw;
7237 /* 82598 have a static priority to TC mapping that can not
7238 * be changed so no validation is needed.
7240 if (hw->mac.type == ixgbe_mac_82598EB)
7243 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
7246 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
7247 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
7249 /* If up2tc is out of bounds default to zero */
7251 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7255 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7261 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
7262 * @adapter: Pointer to adapter struct
7264 * Populate the netdev user priority to tc map
7266 static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
7268 struct net_device *dev = adapter->netdev;
7269 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
7270 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
7273 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
7276 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
7277 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
7279 tc = ets->prio_tc[prio];
7281 netdev_set_prio_tc_map(dev, prio, tc);
7285 #endif /* CONFIG_IXGBE_DCB */
7287 * ixgbe_setup_tc - configure net_device for multiple traffic classes
7289 * @netdev: net device to configure
7290 * @tc: number of traffic classes to enable
7292 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7294 struct ixgbe_adapter *adapter = netdev_priv(dev);
7295 struct ixgbe_hw *hw = &adapter->hw;
7298 /* Hardware supports up to 8 traffic classes */
7299 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
7300 (hw->mac.type == ixgbe_mac_82598EB &&
7301 tc < MAX_TRAFFIC_CLASS))
7304 pools = (find_first_zero_bit(&adapter->fwd_bitmask, 32) > 1);
7305 if (tc && pools && adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS)
7308 /* Hardware has to reinitialize queues and interrupts to
7309 * match packet buffer alignment. Unfortunately, the
7310 * hardware is not flexible enough to do this dynamically.
7312 if (netif_running(dev))
7314 ixgbe_clear_interrupt_scheme(adapter);
7316 #ifdef CONFIG_IXGBE_DCB
7318 netdev_set_num_tc(dev, tc);
7319 ixgbe_set_prio_tc_map(adapter);
7321 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
7323 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
7324 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
7325 adapter->hw.fc.requested_mode = ixgbe_fc_none;
7328 netdev_reset_tc(dev);
7330 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7331 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
7333 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
7335 adapter->temp_dcb_cfg.pfc_mode_enable = false;
7336 adapter->dcb_cfg.pfc_mode_enable = false;
7339 ixgbe_validate_rtr(adapter, tc);
7341 #endif /* CONFIG_IXGBE_DCB */
7342 ixgbe_init_interrupt_scheme(adapter);
7344 if (netif_running(dev))
7345 return ixgbe_open(dev);
7350 #ifdef CONFIG_PCI_IOV
7351 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter)
7353 struct net_device *netdev = adapter->netdev;
7356 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev));
7361 void ixgbe_do_reset(struct net_device *netdev)
7363 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7365 if (netif_running(netdev))
7366 ixgbe_reinit_locked(adapter);
7368 ixgbe_reset(adapter);
7371 static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
7372 netdev_features_t features)
7374 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7376 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7377 if (!(features & NETIF_F_RXCSUM))
7378 features &= ~NETIF_F_LRO;
7380 /* Turn off LRO if not RSC capable */
7381 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
7382 features &= ~NETIF_F_LRO;
7387 static int ixgbe_set_features(struct net_device *netdev,
7388 netdev_features_t features)
7390 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7391 netdev_features_t changed = netdev->features ^ features;
7392 bool need_reset = false;
7394 /* Make sure RSC matches LRO, reset if change */
7395 if (!(features & NETIF_F_LRO)) {
7396 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7398 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
7399 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
7400 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
7401 if (adapter->rx_itr_setting == 1 ||
7402 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
7403 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
7405 } else if ((changed ^ features) & NETIF_F_LRO) {
7406 e_info(probe, "rx-usecs set too low, "
7412 * Check if Flow Director n-tuple support was enabled or disabled. If
7413 * the state changed, we need to reset.
7415 switch (features & NETIF_F_NTUPLE) {
7416 case NETIF_F_NTUPLE:
7417 /* turn off ATR, enable perfect filters and reset */
7418 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
7421 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7422 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7425 /* turn off perfect filters, enable ATR and reset */
7426 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7429 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7431 /* We cannot enable ATR if SR-IOV is enabled */
7432 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7435 /* We cannot enable ATR if we have 2 or more traffic classes */
7436 if (netdev_get_num_tc(netdev) > 1)
7439 /* We cannot enable ATR if RSS is disabled */
7440 if (adapter->ring_feature[RING_F_RSS].limit <= 1)
7443 /* A sample rate of 0 indicates ATR disabled */
7444 if (!adapter->atr_sample_rate)
7447 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7451 if (features & NETIF_F_HW_VLAN_CTAG_RX)
7452 ixgbe_vlan_strip_enable(adapter);
7454 ixgbe_vlan_strip_disable(adapter);
7456 if (changed & NETIF_F_RXALL)
7459 netdev->features = features;
7461 ixgbe_do_reset(netdev);
7466 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
7467 struct net_device *dev,
7468 const unsigned char *addr,
7471 struct ixgbe_adapter *adapter = netdev_priv(dev);
7474 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7475 return ndo_dflt_fdb_add(ndm, tb, dev, addr, flags);
7477 /* Hardware does not support aging addresses so if a
7478 * ndm_state is given only allow permanent addresses
7480 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
7481 pr_info("%s: FDB only supports static addresses\n",
7486 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
7487 u32 rar_uc_entries = IXGBE_MAX_PF_MACVLANS;
7489 if (netdev_uc_count(dev) < rar_uc_entries)
7490 err = dev_uc_add_excl(dev, addr);
7493 } else if (is_multicast_ether_addr(addr)) {
7494 err = dev_mc_add_excl(dev, addr);
7499 /* Only return duplicate errors if NLM_F_EXCL is set */
7500 if (err == -EEXIST && !(flags & NLM_F_EXCL))
7506 static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
7507 struct nlmsghdr *nlh)
7509 struct ixgbe_adapter *adapter = netdev_priv(dev);
7510 struct nlattr *attr, *br_spec;
7513 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7516 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
7518 nla_for_each_nested(attr, br_spec, rem) {
7522 if (nla_type(attr) != IFLA_BRIDGE_MODE)
7525 mode = nla_get_u16(attr);
7526 if (mode == BRIDGE_MODE_VEPA) {
7528 adapter->flags2 &= ~IXGBE_FLAG2_BRIDGE_MODE_VEB;
7529 } else if (mode == BRIDGE_MODE_VEB) {
7530 reg = IXGBE_PFDTXGSWC_VT_LBEN;
7531 adapter->flags2 |= IXGBE_FLAG2_BRIDGE_MODE_VEB;
7535 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, reg);
7537 e_info(drv, "enabling bridge mode: %s\n",
7538 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
7544 static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
7545 struct net_device *dev,
7548 struct ixgbe_adapter *adapter = netdev_priv(dev);
7551 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7554 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
7555 mode = BRIDGE_MODE_VEB;
7557 mode = BRIDGE_MODE_VEPA;
7559 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, mode);
7562 static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev)
7564 struct ixgbe_fwd_adapter *fwd_adapter = NULL;
7565 struct ixgbe_adapter *adapter = netdev_priv(pdev);
7570 if (vdev->num_rx_queues != vdev->num_tx_queues) {
7571 netdev_info(pdev, "%s: Only supports a single queue count for TX and RX\n",
7573 return ERR_PTR(-EINVAL);
7576 /* Check for hardware restriction on number of rx/tx queues */
7577 if (vdev->num_tx_queues > IXGBE_MAX_L2A_QUEUES ||
7578 vdev->num_tx_queues == IXGBE_BAD_L2A_QUEUE) {
7580 "%s: Supports RX/TX Queue counts 1,2, and 4\n",
7582 return ERR_PTR(-EINVAL);
7585 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
7586 adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS - 1) ||
7587 (adapter->num_rx_pools > IXGBE_MAX_MACVLANS))
7588 return ERR_PTR(-EBUSY);
7590 fwd_adapter = kcalloc(1, sizeof(struct ixgbe_fwd_adapter), GFP_KERNEL);
7592 return ERR_PTR(-ENOMEM);
7594 pool = find_first_zero_bit(&adapter->fwd_bitmask, 32);
7595 adapter->num_rx_pools++;
7596 set_bit(pool, &adapter->fwd_bitmask);
7597 limit = find_last_bit(&adapter->fwd_bitmask, 32);
7599 /* Enable VMDq flag so device will be set in VM mode */
7600 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | IXGBE_FLAG_SRIOV_ENABLED;
7601 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
7602 adapter->ring_feature[RING_F_RSS].limit = vdev->num_tx_queues;
7604 /* Force reinit of ring allocation with VMDQ enabled */
7605 err = ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
7608 fwd_adapter->pool = pool;
7609 fwd_adapter->real_adapter = adapter;
7610 err = ixgbe_fwd_ring_up(vdev, fwd_adapter);
7613 netif_tx_start_all_queues(vdev);
7616 /* unwind counter and free adapter struct */
7618 "%s: dfwd hardware acceleration failed\n", vdev->name);
7619 clear_bit(pool, &adapter->fwd_bitmask);
7620 adapter->num_rx_pools--;
7622 return ERR_PTR(err);
7625 static void ixgbe_fwd_del(struct net_device *pdev, void *priv)
7627 struct ixgbe_fwd_adapter *fwd_adapter = priv;
7628 struct ixgbe_adapter *adapter = fwd_adapter->real_adapter;
7631 clear_bit(fwd_adapter->pool, &adapter->fwd_bitmask);
7632 adapter->num_rx_pools--;
7634 limit = find_last_bit(&adapter->fwd_bitmask, 32);
7635 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
7636 ixgbe_fwd_ring_down(fwd_adapter->netdev, fwd_adapter);
7637 ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
7638 netdev_dbg(pdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
7639 fwd_adapter->pool, adapter->num_rx_pools,
7640 fwd_adapter->rx_base_queue,
7641 fwd_adapter->rx_base_queue + adapter->num_rx_queues_per_pool,
7642 adapter->fwd_bitmask);
7646 static const struct net_device_ops ixgbe_netdev_ops = {
7647 .ndo_open = ixgbe_open,
7648 .ndo_stop = ixgbe_close,
7649 .ndo_start_xmit = ixgbe_xmit_frame,
7650 .ndo_select_queue = ixgbe_select_queue,
7651 .ndo_set_rx_mode = ixgbe_set_rx_mode,
7652 .ndo_validate_addr = eth_validate_addr,
7653 .ndo_set_mac_address = ixgbe_set_mac,
7654 .ndo_change_mtu = ixgbe_change_mtu,
7655 .ndo_tx_timeout = ixgbe_tx_timeout,
7656 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7657 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
7658 .ndo_do_ioctl = ixgbe_ioctl,
7659 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7660 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7661 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
7662 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
7663 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
7664 .ndo_get_stats64 = ixgbe_get_stats64,
7665 #ifdef CONFIG_IXGBE_DCB
7666 .ndo_setup_tc = ixgbe_setup_tc,
7668 #ifdef CONFIG_NET_POLL_CONTROLLER
7669 .ndo_poll_controller = ixgbe_netpoll,
7671 #ifdef CONFIG_NET_RX_BUSY_POLL
7672 .ndo_busy_poll = ixgbe_low_latency_recv,
7675 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
7676 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
7677 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
7678 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7679 .ndo_fcoe_disable = ixgbe_fcoe_disable,
7680 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
7681 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
7682 #endif /* IXGBE_FCOE */
7683 .ndo_set_features = ixgbe_set_features,
7684 .ndo_fix_features = ixgbe_fix_features,
7685 .ndo_fdb_add = ixgbe_ndo_fdb_add,
7686 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
7687 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
7688 .ndo_dfwd_add_station = ixgbe_fwd_add,
7689 .ndo_dfwd_del_station = ixgbe_fwd_del,
7693 * ixgbe_enumerate_functions - Get the number of ports this device has
7694 * @adapter: adapter structure
7696 * This function enumerates the phsyical functions co-located on a single slot,
7697 * in order to determine how many ports a device has. This is most useful in
7698 * determining the required GT/s of PCIe bandwidth necessary for optimal
7701 static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter)
7703 struct list_head *entry;
7706 /* Some cards can not use the generic count PCIe functions method,
7707 * because they are behind a parent switch, so we hardcode these with
7708 * the correct number of functions.
7710 if (ixgbe_pcie_from_parent(&adapter->hw)) {
7713 list_for_each(entry, &adapter->pdev->bus_list) {
7714 struct pci_dev *pdev =
7715 list_entry(entry, struct pci_dev, bus_list);
7716 /* don't count virtual functions */
7717 if (!pdev->is_virtfn)
7726 * ixgbe_wol_supported - Check whether device supports WoL
7727 * @hw: hw specific details
7728 * @device_id: the device ID
7729 * @subdev_id: the subsystem device ID
7731 * This function is used by probe and ethtool to determine
7732 * which devices have WoL support
7735 int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
7738 struct ixgbe_hw *hw = &adapter->hw;
7739 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7740 int is_wol_supported = 0;
7742 switch (device_id) {
7743 case IXGBE_DEV_ID_82599_SFP:
7744 /* Only these subdevices could supports WOL */
7745 switch (subdevice_id) {
7746 case IXGBE_SUBDEV_ID_82599_560FLR:
7747 /* only support first port */
7748 if (hw->bus.func != 0)
7750 case IXGBE_SUBDEV_ID_82599_SP_560FLR:
7751 case IXGBE_SUBDEV_ID_82599_SFP:
7752 case IXGBE_SUBDEV_ID_82599_RNDC:
7753 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
7754 case IXGBE_SUBDEV_ID_82599_LOM_SFP:
7755 is_wol_supported = 1;
7759 case IXGBE_DEV_ID_82599EN_SFP:
7760 /* Only this subdevice supports WOL */
7761 switch (subdevice_id) {
7762 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1:
7763 is_wol_supported = 1;
7767 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7768 /* All except this subdevice support WOL */
7769 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7770 is_wol_supported = 1;
7772 case IXGBE_DEV_ID_82599_KX4:
7773 is_wol_supported = 1;
7775 case IXGBE_DEV_ID_X540T:
7776 case IXGBE_DEV_ID_X540T1:
7777 /* check eeprom to see if enabled wol */
7778 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7779 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7780 (hw->bus.func == 0))) {
7781 is_wol_supported = 1;
7786 return is_wol_supported;
7790 * ixgbe_probe - Device Initialization Routine
7791 * @pdev: PCI device information struct
7792 * @ent: entry in ixgbe_pci_tbl
7794 * Returns 0 on success, negative on failure
7796 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7797 * The OS initialization, configuring of the adapter private structure,
7798 * and a hardware reset occur.
7800 static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
7802 struct net_device *netdev;
7803 struct ixgbe_adapter *adapter = NULL;
7804 struct ixgbe_hw *hw;
7805 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
7806 static int cards_found;
7807 int i, err, pci_using_dac, expected_gts;
7808 unsigned int indices = MAX_TX_QUEUES;
7809 u8 part_str[IXGBE_PBANUM_LENGTH];
7815 /* Catch broken hardware that put the wrong VF device ID in
7816 * the PCIe SR-IOV capability.
7818 if (pdev->is_virtfn) {
7819 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7820 pci_name(pdev), pdev->vendor, pdev->device);
7824 err = pci_enable_device_mem(pdev);
7828 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
7831 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
7834 "No usable DMA configuration, aborting\n");
7840 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7841 IORESOURCE_MEM), ixgbe_driver_name);
7844 "pci_request_selected_regions failed 0x%x\n", err);
7848 pci_enable_pcie_error_reporting(pdev);
7850 pci_set_master(pdev);
7851 pci_save_state(pdev);
7853 if (ii->mac == ixgbe_mac_82598EB) {
7854 #ifdef CONFIG_IXGBE_DCB
7855 /* 8 TC w/ 4 queues per TC */
7856 indices = 4 * MAX_TRAFFIC_CLASS;
7858 indices = IXGBE_MAX_RSS_INDICES;
7862 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
7865 goto err_alloc_etherdev;
7868 SET_NETDEV_DEV(netdev, &pdev->dev);
7870 adapter = netdev_priv(netdev);
7871 pci_set_drvdata(pdev, adapter);
7873 adapter->netdev = netdev;
7874 adapter->pdev = pdev;
7877 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
7879 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7880 pci_resource_len(pdev, 0));
7886 netdev->netdev_ops = &ixgbe_netdev_ops;
7887 ixgbe_set_ethtool_ops(netdev);
7888 netdev->watchdog_timeo = 5 * HZ;
7889 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
7891 adapter->bd_number = cards_found;
7894 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
7895 hw->mac.type = ii->mac;
7898 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7899 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7900 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7901 if (!(eec & (1 << 8)))
7902 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7905 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
7906 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
7907 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7908 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7909 hw->phy.mdio.mmds = 0;
7910 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7911 hw->phy.mdio.dev = netdev;
7912 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7913 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
7915 ii->get_invariants(hw);
7917 /* setup the private structure */
7918 err = ixgbe_sw_init(adapter);
7922 /* Cache if MNG FW is up so we don't have to read the REG later */
7923 if (hw->mac.ops.mng_fw_enabled)
7924 hw->mng_fw_enabled = hw->mac.ops.mng_fw_enabled(hw);
7926 /* Make it possible the adapter to be woken up via WOL */
7927 switch (adapter->hw.mac.type) {
7928 case ixgbe_mac_82599EB:
7929 case ixgbe_mac_X540:
7930 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7937 * If there is a fan on this device and it has failed log the
7940 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7941 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7942 if (esdp & IXGBE_ESDP_SDP1)
7943 e_crit(probe, "Fan has stopped, replace the adapter\n");
7946 if (allow_unsupported_sfp)
7947 hw->allow_unsupported_sfp = allow_unsupported_sfp;
7949 /* reset_hw fills in the perm_addr as well */
7950 hw->phy.reset_if_overtemp = true;
7951 err = hw->mac.ops.reset_hw(hw);
7952 hw->phy.reset_if_overtemp = false;
7953 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7954 hw->mac.type == ixgbe_mac_82598EB) {
7956 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7957 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n");
7958 e_dev_err("Reload the driver after installing a supported module.\n");
7961 e_dev_err("HW Init failed: %d\n", err);
7965 #ifdef CONFIG_PCI_IOV
7966 /* SR-IOV not supported on the 82598 */
7967 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7970 ixgbe_init_mbx_params_pf(hw);
7971 memcpy(&hw->mbx.ops, ii->mbx_ops, sizeof(hw->mbx.ops));
7972 ixgbe_enable_sriov(adapter);
7973 pci_sriov_set_totalvfs(pdev, 63);
7977 netdev->features = NETIF_F_SG |
7980 NETIF_F_HW_VLAN_CTAG_TX |
7981 NETIF_F_HW_VLAN_CTAG_RX |
7982 NETIF_F_HW_VLAN_CTAG_FILTER |
7988 netdev->hw_features = netdev->features | NETIF_F_HW_L2FW_DOFFLOAD;
7990 switch (adapter->hw.mac.type) {
7991 case ixgbe_mac_82599EB:
7992 case ixgbe_mac_X540:
7993 netdev->features |= NETIF_F_SCTP_CSUM;
7994 netdev->hw_features |= NETIF_F_SCTP_CSUM |
8001 netdev->hw_features |= NETIF_F_RXALL;
8003 netdev->vlan_features |= NETIF_F_TSO;
8004 netdev->vlan_features |= NETIF_F_TSO6;
8005 netdev->vlan_features |= NETIF_F_IP_CSUM;
8006 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
8007 netdev->vlan_features |= NETIF_F_SG;
8009 netdev->priv_flags |= IFF_UNICAST_FLT;
8010 netdev->priv_flags |= IFF_SUPP_NOFCS;
8012 #ifdef CONFIG_IXGBE_DCB
8013 netdev->dcbnl_ops = &dcbnl_ops;
8017 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
8018 unsigned int fcoe_l;
8020 if (hw->mac.ops.get_device_caps) {
8021 hw->mac.ops.get_device_caps(hw, &device_caps);
8022 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
8023 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
8027 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus());
8028 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l;
8030 netdev->features |= NETIF_F_FSO |
8033 netdev->vlan_features |= NETIF_F_FSO |
8037 #endif /* IXGBE_FCOE */
8038 if (pci_using_dac) {
8039 netdev->features |= NETIF_F_HIGHDMA;
8040 netdev->vlan_features |= NETIF_F_HIGHDMA;
8043 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
8044 netdev->hw_features |= NETIF_F_LRO;
8045 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
8046 netdev->features |= NETIF_F_LRO;
8048 /* make sure the EEPROM is good */
8049 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
8050 e_dev_err("The EEPROM Checksum Is Not Valid\n");
8055 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
8057 if (!is_valid_ether_addr(netdev->dev_addr)) {
8058 e_dev_err("invalid MAC address\n");
8063 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
8064 (unsigned long) adapter);
8066 INIT_WORK(&adapter->service_task, ixgbe_service_task);
8067 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
8069 err = ixgbe_init_interrupt_scheme(adapter);
8073 /* WOL not supported for all devices */
8075 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
8076 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device,
8077 pdev->subsystem_device);
8078 if (hw->wol_enabled)
8079 adapter->wol = IXGBE_WUFC_MAG;
8081 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
8083 /* save off EEPROM version number */
8084 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
8085 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
8087 /* pick up the PCI bus settings for reporting later */
8088 hw->mac.ops.get_bus_info(hw);
8089 if (ixgbe_pcie_from_parent(hw))
8090 ixgbe_get_parent_bus_info(adapter);
8092 /* calculate the expected PCIe bandwidth required for optimal
8093 * performance. Note that some older parts will never have enough
8094 * bandwidth due to being older generation PCIe parts. We clamp these
8095 * parts to ensure no warning is displayed if it can't be fixed.
8097 switch (hw->mac.type) {
8098 case ixgbe_mac_82598EB:
8099 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16);
8102 expected_gts = ixgbe_enumerate_functions(adapter) * 10;
8105 ixgbe_check_minimum_link(adapter, expected_gts);
8107 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
8109 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
8110 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
8111 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
8112 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
8115 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
8116 hw->mac.type, hw->phy.type, part_str);
8118 e_dev_info("%pM\n", netdev->dev_addr);
8120 /* reset the hardware with the new settings */
8121 err = hw->mac.ops.start_hw(hw);
8122 if (err == IXGBE_ERR_EEPROM_VERSION) {
8123 /* We are running on a pre-production device, log a warning */
8124 e_dev_warn("This device is a pre-production adapter/LOM. "
8125 "Please be aware there may be issues associated "
8126 "with your hardware. If you are experiencing "
8127 "problems please contact your Intel or hardware "
8128 "representative who provided you with this "
8131 strcpy(netdev->name, "eth%d");
8132 err = register_netdev(netdev);
8136 /* power down the optics for 82599 SFP+ fiber */
8137 if (hw->mac.ops.disable_tx_laser)
8138 hw->mac.ops.disable_tx_laser(hw);
8140 /* carrier off reporting is important to ethtool even BEFORE open */
8141 netif_carrier_off(netdev);
8143 #ifdef CONFIG_IXGBE_DCA
8144 if (dca_add_requester(&pdev->dev) == 0) {
8145 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
8146 ixgbe_setup_dca(adapter);
8149 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
8150 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
8151 for (i = 0; i < adapter->num_vfs; i++)
8152 ixgbe_vf_configuration(pdev, (i | 0x10000000));
8155 /* firmware requires driver version to be 0xFFFFFFFF
8156 * since os does not support feature
8158 if (hw->mac.ops.set_fw_drv_ver)
8159 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
8162 /* add san mac addr to netdev */
8163 ixgbe_add_sanmac_netdev(netdev);
8165 e_dev_info("%s\n", ixgbe_default_device_descr);
8168 #ifdef CONFIG_IXGBE_HWMON
8169 if (ixgbe_sysfs_init(adapter))
8170 e_err(probe, "failed to allocate sysfs resources\n");
8171 #endif /* CONFIG_IXGBE_HWMON */
8173 ixgbe_dbg_adapter_init(adapter);
8175 /* Need link setup for MNG FW, else wait for IXGBE_UP */
8176 if (hw->mng_fw_enabled && hw->mac.ops.setup_link)
8177 hw->mac.ops.setup_link(hw,
8178 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL,
8184 ixgbe_release_hw_control(adapter);
8185 ixgbe_clear_interrupt_scheme(adapter);
8187 ixgbe_disable_sriov(adapter);
8188 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
8189 iounmap(hw->hw_addr);
8191 free_netdev(netdev);
8193 pci_release_selected_regions(pdev,
8194 pci_select_bars(pdev, IORESOURCE_MEM));
8197 pci_disable_device(pdev);
8202 * ixgbe_remove - Device Removal Routine
8203 * @pdev: PCI device information struct
8205 * ixgbe_remove is called by the PCI subsystem to alert the driver
8206 * that it should release a PCI device. The could be caused by a
8207 * Hot-Plug event, or because the driver is going to be removed from
8210 static void ixgbe_remove(struct pci_dev *pdev)
8212 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8213 struct net_device *netdev = adapter->netdev;
8215 ixgbe_dbg_adapter_exit(adapter);
8217 set_bit(__IXGBE_REMOVING, &adapter->state);
8218 cancel_work_sync(&adapter->service_task);
8221 #ifdef CONFIG_IXGBE_DCA
8222 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
8223 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
8224 dca_remove_requester(&pdev->dev);
8225 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
8229 #ifdef CONFIG_IXGBE_HWMON
8230 ixgbe_sysfs_exit(adapter);
8231 #endif /* CONFIG_IXGBE_HWMON */
8233 /* remove the added san mac */
8234 ixgbe_del_sanmac_netdev(netdev);
8236 if (netdev->reg_state == NETREG_REGISTERED)
8237 unregister_netdev(netdev);
8239 #ifdef CONFIG_PCI_IOV
8241 * Only disable SR-IOV on unload if the user specified the now
8242 * deprecated max_vfs module parameter.
8245 ixgbe_disable_sriov(adapter);
8247 ixgbe_clear_interrupt_scheme(adapter);
8249 ixgbe_release_hw_control(adapter);
8252 kfree(adapter->ixgbe_ieee_pfc);
8253 kfree(adapter->ixgbe_ieee_ets);
8256 iounmap(adapter->hw.hw_addr);
8257 pci_release_selected_regions(pdev, pci_select_bars(pdev,
8260 e_dev_info("complete\n");
8262 free_netdev(netdev);
8264 pci_disable_pcie_error_reporting(pdev);
8266 pci_disable_device(pdev);
8270 * ixgbe_io_error_detected - called when PCI error is detected
8271 * @pdev: Pointer to PCI device
8272 * @state: The current pci connection state
8274 * This function is called after a PCI bus error affecting
8275 * this device has been detected.
8277 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
8278 pci_channel_state_t state)
8280 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8281 struct net_device *netdev = adapter->netdev;
8283 #ifdef CONFIG_PCI_IOV
8284 struct pci_dev *bdev, *vfdev;
8285 u32 dw0, dw1, dw2, dw3;
8287 u16 req_id, pf_func;
8289 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
8290 adapter->num_vfs == 0)
8291 goto skip_bad_vf_detection;
8293 bdev = pdev->bus->self;
8294 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
8295 bdev = bdev->bus->self;
8298 goto skip_bad_vf_detection;
8300 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
8302 goto skip_bad_vf_detection;
8304 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0);
8305 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1);
8306 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2);
8307 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3);
8310 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
8311 if (!(req_id & 0x0080))
8312 goto skip_bad_vf_detection;
8314 pf_func = req_id & 0x01;
8315 if ((pf_func & 1) == (pdev->devfn & 1)) {
8316 unsigned int device_id;
8318 vf = (req_id & 0x7F) >> 1;
8319 e_dev_err("VF %d has caused a PCIe error\n", vf);
8320 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
8321 "%8.8x\tdw3: %8.8x\n",
8322 dw0, dw1, dw2, dw3);
8323 switch (adapter->hw.mac.type) {
8324 case ixgbe_mac_82599EB:
8325 device_id = IXGBE_82599_VF_DEVICE_ID;
8327 case ixgbe_mac_X540:
8328 device_id = IXGBE_X540_VF_DEVICE_ID;
8335 /* Find the pci device of the offending VF */
8336 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
8338 if (vfdev->devfn == (req_id & 0xFF))
8340 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
8344 * There's a slim chance the VF could have been hot plugged,
8345 * so if it is no longer present we don't need to issue the
8346 * VFLR. Just clean up the AER in that case.
8349 e_dev_err("Issuing VFLR to VF %d\n", vf);
8350 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
8351 /* Free device reference count */
8355 pci_cleanup_aer_uncorrect_error_status(pdev);
8359 * Even though the error may have occurred on the other port
8360 * we still need to increment the vf error reference count for
8361 * both ports because the I/O resume function will be called
8364 adapter->vferr_refcount++;
8366 return PCI_ERS_RESULT_RECOVERED;
8368 skip_bad_vf_detection:
8369 #endif /* CONFIG_PCI_IOV */
8370 netif_device_detach(netdev);
8372 if (state == pci_channel_io_perm_failure)
8373 return PCI_ERS_RESULT_DISCONNECT;
8375 if (netif_running(netdev))
8376 ixgbe_down(adapter);
8377 pci_disable_device(pdev);
8379 /* Request a slot reset. */
8380 return PCI_ERS_RESULT_NEED_RESET;
8384 * ixgbe_io_slot_reset - called after the pci bus has been reset.
8385 * @pdev: Pointer to PCI device
8387 * Restart the card from scratch, as if from a cold-boot.
8389 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
8391 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8392 pci_ers_result_t result;
8395 if (pci_enable_device_mem(pdev)) {
8396 e_err(probe, "Cannot re-enable PCI device after reset.\n");
8397 result = PCI_ERS_RESULT_DISCONNECT;
8399 pci_set_master(pdev);
8400 pci_restore_state(pdev);
8401 pci_save_state(pdev);
8403 pci_wake_from_d3(pdev, false);
8405 ixgbe_reset(adapter);
8406 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
8407 result = PCI_ERS_RESULT_RECOVERED;
8410 err = pci_cleanup_aer_uncorrect_error_status(pdev);
8412 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
8413 "failed 0x%0x\n", err);
8414 /* non-fatal, continue */
8421 * ixgbe_io_resume - called when traffic can start flowing again.
8422 * @pdev: Pointer to PCI device
8424 * This callback is called when the error recovery driver tells us that
8425 * its OK to resume normal operation.
8427 static void ixgbe_io_resume(struct pci_dev *pdev)
8429 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8430 struct net_device *netdev = adapter->netdev;
8432 #ifdef CONFIG_PCI_IOV
8433 if (adapter->vferr_refcount) {
8434 e_info(drv, "Resuming after VF err\n");
8435 adapter->vferr_refcount--;
8440 if (netif_running(netdev))
8443 netif_device_attach(netdev);
8446 static const struct pci_error_handlers ixgbe_err_handler = {
8447 .error_detected = ixgbe_io_error_detected,
8448 .slot_reset = ixgbe_io_slot_reset,
8449 .resume = ixgbe_io_resume,
8452 static struct pci_driver ixgbe_driver = {
8453 .name = ixgbe_driver_name,
8454 .id_table = ixgbe_pci_tbl,
8455 .probe = ixgbe_probe,
8456 .remove = ixgbe_remove,
8458 .suspend = ixgbe_suspend,
8459 .resume = ixgbe_resume,
8461 .shutdown = ixgbe_shutdown,
8462 .sriov_configure = ixgbe_pci_sriov_configure,
8463 .err_handler = &ixgbe_err_handler
8467 * ixgbe_init_module - Driver Registration Routine
8469 * ixgbe_init_module is the first routine called when the driver is
8470 * loaded. All it does is register with the PCI subsystem.
8472 static int __init ixgbe_init_module(void)
8475 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
8476 pr_info("%s\n", ixgbe_copyright);
8480 ret = pci_register_driver(&ixgbe_driver);
8486 #ifdef CONFIG_IXGBE_DCA
8487 dca_register_notify(&dca_notifier);
8493 module_init(ixgbe_init_module);
8496 * ixgbe_exit_module - Driver Exit Cleanup Routine
8498 * ixgbe_exit_module is called just before the driver is removed
8501 static void __exit ixgbe_exit_module(void)
8503 #ifdef CONFIG_IXGBE_DCA
8504 dca_unregister_notify(&dca_notifier);
8506 pci_unregister_driver(&ixgbe_driver);
8510 rcu_barrier(); /* Wait for completion of call_rcu()'s */
8513 #ifdef CONFIG_IXGBE_DCA
8514 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
8519 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
8520 __ixgbe_notify_dca);
8522 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
8525 #endif /* CONFIG_IXGBE_DCA */
8527 module_exit(ixgbe_exit_module);