1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018 Intel Corporation */
4 #include <linux/module.h>
5 #include <linux/types.h>
6 #include <linux/if_vlan.h>
11 #include <linux/pm_runtime.h>
12 #include <net/pkt_sched.h>
20 #define DRV_SUMMARY "Intel(R) 2.5G Ethernet Linux Driver"
22 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
24 static int debug = -1;
26 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
27 MODULE_DESCRIPTION(DRV_SUMMARY);
28 MODULE_LICENSE("GPL v2");
29 module_param(debug, int, 0);
30 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
32 char igc_driver_name[] = "igc";
33 static const char igc_driver_string[] = DRV_SUMMARY;
34 static const char igc_copyright[] =
35 "Copyright(c) 2018 Intel Corporation.";
37 static const struct igc_info *igc_info_tbl[] = {
38 [board_base] = &igc_base_info,
41 static const struct pci_device_id igc_pci_tbl[] = {
42 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_LM), board_base },
43 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_V), board_base },
44 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_I), board_base },
45 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I220_V), board_base },
46 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_K), board_base },
47 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_K2), board_base },
48 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_LMVP), board_base },
49 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_IT), board_base },
50 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I226_LM), board_base },
51 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I226_V), board_base },
52 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I226_IT), board_base },
53 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I221_V), board_base },
54 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I226_BLANK_NVM), board_base },
55 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_BLANK_NVM), board_base },
56 /* required last entry */
60 MODULE_DEVICE_TABLE(pci, igc_pci_tbl);
69 void igc_reset(struct igc_adapter *adapter)
71 struct net_device *dev = adapter->netdev;
72 struct igc_hw *hw = &adapter->hw;
73 struct igc_fc_info *fc = &hw->fc;
76 /* Repartition PBA for greater than 9k MTU if required */
79 /* flow control settings
80 * The high water mark must be low enough to fit one full frame
81 * after transmitting the pause frame. As such we must have enough
82 * space to allow for us to complete our current transmit and then
83 * receive the frame that is in progress from the link partner.
85 * - the full Rx FIFO size minus one full Tx plus one full Rx frame
87 hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE);
89 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
90 fc->low_water = fc->high_water - 16;
91 fc->pause_time = 0xFFFF;
93 fc->current_mode = fc->requested_mode;
95 hw->mac.ops.reset_hw(hw);
97 if (hw->mac.ops.init_hw(hw))
98 netdev_err(dev, "Error on hardware initialization\n");
100 /* Re-establish EEE setting */
101 igc_set_eee_i225(hw, true, true, true);
103 if (!netif_running(adapter->netdev))
104 igc_power_down_phy_copper_base(&adapter->hw);
106 /* Re-enable PTP, where applicable. */
107 igc_ptp_reset(adapter);
109 /* Re-enable TSN offloading, where applicable. */
110 igc_tsn_offload_apply(adapter);
112 igc_get_phy_info(hw);
116 * igc_power_up_link - Power up the phy link
117 * @adapter: address of board private structure
119 static void igc_power_up_link(struct igc_adapter *adapter)
121 igc_reset_phy(&adapter->hw);
123 igc_power_up_phy_copper(&adapter->hw);
125 igc_setup_link(&adapter->hw);
129 * igc_release_hw_control - release control of the h/w to f/w
130 * @adapter: address of board private structure
132 * igc_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
133 * For ASF and Pass Through versions of f/w this means that the
134 * driver is no longer loaded.
136 static void igc_release_hw_control(struct igc_adapter *adapter)
138 struct igc_hw *hw = &adapter->hw;
141 /* Let firmware take over control of h/w */
142 ctrl_ext = rd32(IGC_CTRL_EXT);
144 ctrl_ext & ~IGC_CTRL_EXT_DRV_LOAD);
148 * igc_get_hw_control - get control of the h/w from f/w
149 * @adapter: address of board private structure
151 * igc_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
152 * For ASF and Pass Through versions of f/w this means that
153 * the driver is loaded.
155 static void igc_get_hw_control(struct igc_adapter *adapter)
157 struct igc_hw *hw = &adapter->hw;
160 /* Let firmware know the driver has taken over */
161 ctrl_ext = rd32(IGC_CTRL_EXT);
163 ctrl_ext | IGC_CTRL_EXT_DRV_LOAD);
167 * igc_clean_tx_ring - Free Tx Buffers
168 * @tx_ring: ring to be cleaned
170 static void igc_clean_tx_ring(struct igc_ring *tx_ring)
172 u16 i = tx_ring->next_to_clean;
173 struct igc_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i];
175 while (i != tx_ring->next_to_use) {
176 union igc_adv_tx_desc *eop_desc, *tx_desc;
178 /* Free all the Tx ring sk_buffs */
179 dev_kfree_skb_any(tx_buffer->skb);
181 /* unmap skb header data */
182 dma_unmap_single(tx_ring->dev,
183 dma_unmap_addr(tx_buffer, dma),
184 dma_unmap_len(tx_buffer, len),
187 /* check for eop_desc to determine the end of the packet */
188 eop_desc = tx_buffer->next_to_watch;
189 tx_desc = IGC_TX_DESC(tx_ring, i);
191 /* unmap remaining buffers */
192 while (tx_desc != eop_desc) {
196 if (unlikely(i == tx_ring->count)) {
198 tx_buffer = tx_ring->tx_buffer_info;
199 tx_desc = IGC_TX_DESC(tx_ring, 0);
202 /* unmap any remaining paged data */
203 if (dma_unmap_len(tx_buffer, len))
204 dma_unmap_page(tx_ring->dev,
205 dma_unmap_addr(tx_buffer, dma),
206 dma_unmap_len(tx_buffer, len),
210 /* move us one more past the eop_desc for start of next pkt */
213 if (unlikely(i == tx_ring->count)) {
215 tx_buffer = tx_ring->tx_buffer_info;
219 /* reset BQL for queue */
220 netdev_tx_reset_queue(txring_txq(tx_ring));
222 /* reset next_to_use and next_to_clean */
223 tx_ring->next_to_use = 0;
224 tx_ring->next_to_clean = 0;
228 * igc_free_tx_resources - Free Tx Resources per Queue
229 * @tx_ring: Tx descriptor ring for a specific queue
231 * Free all transmit software resources
233 void igc_free_tx_resources(struct igc_ring *tx_ring)
235 igc_clean_tx_ring(tx_ring);
237 vfree(tx_ring->tx_buffer_info);
238 tx_ring->tx_buffer_info = NULL;
240 /* if not set, then don't free */
244 dma_free_coherent(tx_ring->dev, tx_ring->size,
245 tx_ring->desc, tx_ring->dma);
247 tx_ring->desc = NULL;
251 * igc_free_all_tx_resources - Free Tx Resources for All Queues
252 * @adapter: board private structure
254 * Free all transmit software resources
256 static void igc_free_all_tx_resources(struct igc_adapter *adapter)
260 for (i = 0; i < adapter->num_tx_queues; i++)
261 igc_free_tx_resources(adapter->tx_ring[i]);
265 * igc_clean_all_tx_rings - Free Tx Buffers for all queues
266 * @adapter: board private structure
268 static void igc_clean_all_tx_rings(struct igc_adapter *adapter)
272 for (i = 0; i < adapter->num_tx_queues; i++)
273 if (adapter->tx_ring[i])
274 igc_clean_tx_ring(adapter->tx_ring[i]);
278 * igc_setup_tx_resources - allocate Tx resources (Descriptors)
279 * @tx_ring: tx descriptor ring (for a specific queue) to setup
281 * Return 0 on success, negative on failure
283 int igc_setup_tx_resources(struct igc_ring *tx_ring)
285 struct net_device *ndev = tx_ring->netdev;
286 struct device *dev = tx_ring->dev;
289 size = sizeof(struct igc_tx_buffer) * tx_ring->count;
290 tx_ring->tx_buffer_info = vzalloc(size);
291 if (!tx_ring->tx_buffer_info)
294 /* round up to nearest 4K */
295 tx_ring->size = tx_ring->count * sizeof(union igc_adv_tx_desc);
296 tx_ring->size = ALIGN(tx_ring->size, 4096);
298 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
299 &tx_ring->dma, GFP_KERNEL);
304 tx_ring->next_to_use = 0;
305 tx_ring->next_to_clean = 0;
310 vfree(tx_ring->tx_buffer_info);
311 netdev_err(ndev, "Unable to allocate memory for Tx descriptor ring\n");
316 * igc_setup_all_tx_resources - wrapper to allocate Tx resources for all queues
317 * @adapter: board private structure
319 * Return 0 on success, negative on failure
321 static int igc_setup_all_tx_resources(struct igc_adapter *adapter)
323 struct net_device *dev = adapter->netdev;
326 for (i = 0; i < adapter->num_tx_queues; i++) {
327 err = igc_setup_tx_resources(adapter->tx_ring[i]);
329 netdev_err(dev, "Error on Tx queue %u setup\n", i);
330 for (i--; i >= 0; i--)
331 igc_free_tx_resources(adapter->tx_ring[i]);
340 * igc_clean_rx_ring - Free Rx Buffers per Queue
341 * @rx_ring: ring to free buffers from
343 static void igc_clean_rx_ring(struct igc_ring *rx_ring)
345 u16 i = rx_ring->next_to_clean;
347 dev_kfree_skb(rx_ring->skb);
350 /* Free all the Rx ring sk_buffs */
351 while (i != rx_ring->next_to_alloc) {
352 struct igc_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
354 /* Invalidate cache lines that may have been written to by
355 * device so that we avoid corrupting memory.
357 dma_sync_single_range_for_cpu(rx_ring->dev,
359 buffer_info->page_offset,
360 igc_rx_bufsz(rx_ring),
363 /* free resources associated with mapping */
364 dma_unmap_page_attrs(rx_ring->dev,
366 igc_rx_pg_size(rx_ring),
369 __page_frag_cache_drain(buffer_info->page,
370 buffer_info->pagecnt_bias);
373 if (i == rx_ring->count)
377 rx_ring->next_to_alloc = 0;
378 rx_ring->next_to_clean = 0;
379 rx_ring->next_to_use = 0;
383 * igc_clean_all_rx_rings - Free Rx Buffers for all queues
384 * @adapter: board private structure
386 static void igc_clean_all_rx_rings(struct igc_adapter *adapter)
390 for (i = 0; i < adapter->num_rx_queues; i++)
391 if (adapter->rx_ring[i])
392 igc_clean_rx_ring(adapter->rx_ring[i]);
396 * igc_free_rx_resources - Free Rx Resources
397 * @rx_ring: ring to clean the resources from
399 * Free all receive software resources
401 void igc_free_rx_resources(struct igc_ring *rx_ring)
403 igc_clean_rx_ring(rx_ring);
405 vfree(rx_ring->rx_buffer_info);
406 rx_ring->rx_buffer_info = NULL;
408 /* if not set, then don't free */
412 dma_free_coherent(rx_ring->dev, rx_ring->size,
413 rx_ring->desc, rx_ring->dma);
415 rx_ring->desc = NULL;
419 * igc_free_all_rx_resources - Free Rx Resources for All Queues
420 * @adapter: board private structure
422 * Free all receive software resources
424 static void igc_free_all_rx_resources(struct igc_adapter *adapter)
428 for (i = 0; i < adapter->num_rx_queues; i++)
429 igc_free_rx_resources(adapter->rx_ring[i]);
433 * igc_setup_rx_resources - allocate Rx resources (Descriptors)
434 * @rx_ring: rx descriptor ring (for a specific queue) to setup
436 * Returns 0 on success, negative on failure
438 int igc_setup_rx_resources(struct igc_ring *rx_ring)
440 struct net_device *ndev = rx_ring->netdev;
441 struct device *dev = rx_ring->dev;
444 size = sizeof(struct igc_rx_buffer) * rx_ring->count;
445 rx_ring->rx_buffer_info = vzalloc(size);
446 if (!rx_ring->rx_buffer_info)
449 desc_len = sizeof(union igc_adv_rx_desc);
451 /* Round up to nearest 4K */
452 rx_ring->size = rx_ring->count * desc_len;
453 rx_ring->size = ALIGN(rx_ring->size, 4096);
455 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
456 &rx_ring->dma, GFP_KERNEL);
461 rx_ring->next_to_alloc = 0;
462 rx_ring->next_to_clean = 0;
463 rx_ring->next_to_use = 0;
468 vfree(rx_ring->rx_buffer_info);
469 rx_ring->rx_buffer_info = NULL;
470 netdev_err(ndev, "Unable to allocate memory for Rx descriptor ring\n");
475 * igc_setup_all_rx_resources - wrapper to allocate Rx resources
476 * (Descriptors) for all queues
477 * @adapter: board private structure
479 * Return 0 on success, negative on failure
481 static int igc_setup_all_rx_resources(struct igc_adapter *adapter)
483 struct net_device *dev = adapter->netdev;
486 for (i = 0; i < adapter->num_rx_queues; i++) {
487 err = igc_setup_rx_resources(adapter->rx_ring[i]);
489 netdev_err(dev, "Error on Rx queue %u setup\n", i);
490 for (i--; i >= 0; i--)
491 igc_free_rx_resources(adapter->rx_ring[i]);
500 * igc_configure_rx_ring - Configure a receive ring after Reset
501 * @adapter: board private structure
502 * @ring: receive ring to be configured
504 * Configure the Rx unit of the MAC after a reset.
506 static void igc_configure_rx_ring(struct igc_adapter *adapter,
507 struct igc_ring *ring)
509 struct igc_hw *hw = &adapter->hw;
510 union igc_adv_rx_desc *rx_desc;
511 int reg_idx = ring->reg_idx;
512 u32 srrctl = 0, rxdctl = 0;
513 u64 rdba = ring->dma;
515 /* disable the queue */
516 wr32(IGC_RXDCTL(reg_idx), 0);
518 /* Set DMA base address registers */
519 wr32(IGC_RDBAL(reg_idx),
520 rdba & 0x00000000ffffffffULL);
521 wr32(IGC_RDBAH(reg_idx), rdba >> 32);
522 wr32(IGC_RDLEN(reg_idx),
523 ring->count * sizeof(union igc_adv_rx_desc));
525 /* initialize head and tail */
526 ring->tail = adapter->io_addr + IGC_RDT(reg_idx);
527 wr32(IGC_RDH(reg_idx), 0);
528 writel(0, ring->tail);
530 /* reset next-to- use/clean to place SW in sync with hardware */
531 ring->next_to_clean = 0;
532 ring->next_to_use = 0;
534 /* set descriptor configuration */
535 srrctl = IGC_RX_HDR_LEN << IGC_SRRCTL_BSIZEHDRSIZE_SHIFT;
536 if (ring_uses_large_buffer(ring))
537 srrctl |= IGC_RXBUFFER_3072 >> IGC_SRRCTL_BSIZEPKT_SHIFT;
539 srrctl |= IGC_RXBUFFER_2048 >> IGC_SRRCTL_BSIZEPKT_SHIFT;
540 srrctl |= IGC_SRRCTL_DESCTYPE_ADV_ONEBUF;
542 wr32(IGC_SRRCTL(reg_idx), srrctl);
544 rxdctl |= IGC_RX_PTHRESH;
545 rxdctl |= IGC_RX_HTHRESH << 8;
546 rxdctl |= IGC_RX_WTHRESH << 16;
548 /* initialize rx_buffer_info */
549 memset(ring->rx_buffer_info, 0,
550 sizeof(struct igc_rx_buffer) * ring->count);
552 /* initialize Rx descriptor 0 */
553 rx_desc = IGC_RX_DESC(ring, 0);
554 rx_desc->wb.upper.length = 0;
556 /* enable receive descriptor fetching */
557 rxdctl |= IGC_RXDCTL_QUEUE_ENABLE;
559 wr32(IGC_RXDCTL(reg_idx), rxdctl);
563 * igc_configure_rx - Configure receive Unit after Reset
564 * @adapter: board private structure
566 * Configure the Rx unit of the MAC after a reset.
568 static void igc_configure_rx(struct igc_adapter *adapter)
572 /* Setup the HW Rx Head and Tail Descriptor Pointers and
573 * the Base and Length of the Rx Descriptor Ring
575 for (i = 0; i < adapter->num_rx_queues; i++)
576 igc_configure_rx_ring(adapter, adapter->rx_ring[i]);
580 * igc_configure_tx_ring - Configure transmit ring after Reset
581 * @adapter: board private structure
582 * @ring: tx ring to configure
584 * Configure a transmit ring after a reset.
586 static void igc_configure_tx_ring(struct igc_adapter *adapter,
587 struct igc_ring *ring)
589 struct igc_hw *hw = &adapter->hw;
590 int reg_idx = ring->reg_idx;
591 u64 tdba = ring->dma;
594 /* disable the queue */
595 wr32(IGC_TXDCTL(reg_idx), 0);
599 wr32(IGC_TDLEN(reg_idx),
600 ring->count * sizeof(union igc_adv_tx_desc));
601 wr32(IGC_TDBAL(reg_idx),
602 tdba & 0x00000000ffffffffULL);
603 wr32(IGC_TDBAH(reg_idx), tdba >> 32);
605 ring->tail = adapter->io_addr + IGC_TDT(reg_idx);
606 wr32(IGC_TDH(reg_idx), 0);
607 writel(0, ring->tail);
609 txdctl |= IGC_TX_PTHRESH;
610 txdctl |= IGC_TX_HTHRESH << 8;
611 txdctl |= IGC_TX_WTHRESH << 16;
613 txdctl |= IGC_TXDCTL_QUEUE_ENABLE;
614 wr32(IGC_TXDCTL(reg_idx), txdctl);
618 * igc_configure_tx - Configure transmit Unit after Reset
619 * @adapter: board private structure
621 * Configure the Tx unit of the MAC after a reset.
623 static void igc_configure_tx(struct igc_adapter *adapter)
627 for (i = 0; i < adapter->num_tx_queues; i++)
628 igc_configure_tx_ring(adapter, adapter->tx_ring[i]);
632 * igc_setup_mrqc - configure the multiple receive queue control registers
633 * @adapter: Board private structure
635 static void igc_setup_mrqc(struct igc_adapter *adapter)
637 struct igc_hw *hw = &adapter->hw;
638 u32 j, num_rx_queues;
642 netdev_rss_key_fill(rss_key, sizeof(rss_key));
643 for (j = 0; j < 10; j++)
644 wr32(IGC_RSSRK(j), rss_key[j]);
646 num_rx_queues = adapter->rss_queues;
648 if (adapter->rss_indir_tbl_init != num_rx_queues) {
649 for (j = 0; j < IGC_RETA_SIZE; j++)
650 adapter->rss_indir_tbl[j] =
651 (j * num_rx_queues) / IGC_RETA_SIZE;
652 adapter->rss_indir_tbl_init = num_rx_queues;
654 igc_write_rss_indir_tbl(adapter);
656 /* Disable raw packet checksumming so that RSS hash is placed in
657 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
658 * offloads as they are enabled by default
660 rxcsum = rd32(IGC_RXCSUM);
661 rxcsum |= IGC_RXCSUM_PCSD;
663 /* Enable Receive Checksum Offload for SCTP */
664 rxcsum |= IGC_RXCSUM_CRCOFL;
666 /* Don't need to set TUOFL or IPOFL, they default to 1 */
667 wr32(IGC_RXCSUM, rxcsum);
669 /* Generate RSS hash based on packet types, TCP/UDP
670 * port numbers and/or IPv4/v6 src and dst addresses
672 mrqc = IGC_MRQC_RSS_FIELD_IPV4 |
673 IGC_MRQC_RSS_FIELD_IPV4_TCP |
674 IGC_MRQC_RSS_FIELD_IPV6 |
675 IGC_MRQC_RSS_FIELD_IPV6_TCP |
676 IGC_MRQC_RSS_FIELD_IPV6_TCP_EX;
678 if (adapter->flags & IGC_FLAG_RSS_FIELD_IPV4_UDP)
679 mrqc |= IGC_MRQC_RSS_FIELD_IPV4_UDP;
680 if (adapter->flags & IGC_FLAG_RSS_FIELD_IPV6_UDP)
681 mrqc |= IGC_MRQC_RSS_FIELD_IPV6_UDP;
683 mrqc |= IGC_MRQC_ENABLE_RSS_MQ;
685 wr32(IGC_MRQC, mrqc);
689 * igc_setup_rctl - configure the receive control registers
690 * @adapter: Board private structure
692 static void igc_setup_rctl(struct igc_adapter *adapter)
694 struct igc_hw *hw = &adapter->hw;
697 rctl = rd32(IGC_RCTL);
699 rctl &= ~(3 << IGC_RCTL_MO_SHIFT);
700 rctl &= ~(IGC_RCTL_LBM_TCVR | IGC_RCTL_LBM_MAC);
702 rctl |= IGC_RCTL_EN | IGC_RCTL_BAM | IGC_RCTL_RDMTS_HALF |
703 (hw->mac.mc_filter_type << IGC_RCTL_MO_SHIFT);
705 /* enable stripping of CRC. Newer features require
706 * that the HW strips the CRC.
708 rctl |= IGC_RCTL_SECRC;
710 /* disable store bad packets and clear size bits. */
711 rctl &= ~(IGC_RCTL_SBP | IGC_RCTL_SZ_256);
713 /* enable LPE to allow for reception of jumbo frames */
714 rctl |= IGC_RCTL_LPE;
716 /* disable queue 0 to prevent tail write w/o re-config */
717 wr32(IGC_RXDCTL(0), 0);
719 /* This is useful for sniffing bad packets. */
720 if (adapter->netdev->features & NETIF_F_RXALL) {
721 /* UPE and MPE will be handled by normal PROMISC logic
724 rctl |= (IGC_RCTL_SBP | /* Receive bad packets */
725 IGC_RCTL_BAM | /* RX All Bcast Pkts */
726 IGC_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
728 rctl &= ~(IGC_RCTL_DPF | /* Allow filtered pause */
729 IGC_RCTL_CFIEN); /* Disable VLAN CFIEN Filter */
732 wr32(IGC_RCTL, rctl);
736 * igc_setup_tctl - configure the transmit control registers
737 * @adapter: Board private structure
739 static void igc_setup_tctl(struct igc_adapter *adapter)
741 struct igc_hw *hw = &adapter->hw;
744 /* disable queue 0 which icould be enabled by default */
745 wr32(IGC_TXDCTL(0), 0);
747 /* Program the Transmit Control Register */
748 tctl = rd32(IGC_TCTL);
749 tctl &= ~IGC_TCTL_CT;
750 tctl |= IGC_TCTL_PSP | IGC_TCTL_RTLC |
751 (IGC_COLLISION_THRESHOLD << IGC_CT_SHIFT);
753 /* Enable transmits */
756 wr32(IGC_TCTL, tctl);
760 * igc_set_mac_filter_hw() - Set MAC address filter in hardware
761 * @adapter: Pointer to adapter where the filter should be set
762 * @index: Filter index
763 * @type: MAC address filter type (source or destination)
765 * @queue: If non-negative, queue assignment feature is enabled and frames
766 * matching the filter are enqueued onto 'queue'. Otherwise, queue
767 * assignment is disabled.
769 static void igc_set_mac_filter_hw(struct igc_adapter *adapter, int index,
770 enum igc_mac_filter_type type,
771 const u8 *addr, int queue)
773 struct net_device *dev = adapter->netdev;
774 struct igc_hw *hw = &adapter->hw;
777 if (WARN_ON(index >= hw->mac.rar_entry_count))
780 ral = le32_to_cpup((__le32 *)(addr));
781 rah = le16_to_cpup((__le16 *)(addr + 4));
783 if (type == IGC_MAC_FILTER_TYPE_SRC) {
784 rah &= ~IGC_RAH_ASEL_MASK;
785 rah |= IGC_RAH_ASEL_SRC_ADDR;
789 rah &= ~IGC_RAH_QSEL_MASK;
790 rah |= (queue << IGC_RAH_QSEL_SHIFT);
791 rah |= IGC_RAH_QSEL_ENABLE;
796 wr32(IGC_RAL(index), ral);
797 wr32(IGC_RAH(index), rah);
799 netdev_dbg(dev, "MAC address filter set in HW: index %d", index);
803 * igc_clear_mac_filter_hw() - Clear MAC address filter in hardware
804 * @adapter: Pointer to adapter where the filter should be cleared
805 * @index: Filter index
807 static void igc_clear_mac_filter_hw(struct igc_adapter *adapter, int index)
809 struct net_device *dev = adapter->netdev;
810 struct igc_hw *hw = &adapter->hw;
812 if (WARN_ON(index >= hw->mac.rar_entry_count))
815 wr32(IGC_RAL(index), 0);
816 wr32(IGC_RAH(index), 0);
818 netdev_dbg(dev, "MAC address filter cleared in HW: index %d", index);
821 /* Set default MAC address for the PF in the first RAR entry */
822 static void igc_set_default_mac_filter(struct igc_adapter *adapter)
824 struct net_device *dev = adapter->netdev;
825 u8 *addr = adapter->hw.mac.addr;
827 netdev_dbg(dev, "Set default MAC address filter: address %pM", addr);
829 igc_set_mac_filter_hw(adapter, 0, IGC_MAC_FILTER_TYPE_DST, addr, -1);
833 * igc_set_mac - Change the Ethernet Address of the NIC
834 * @netdev: network interface device structure
835 * @p: pointer to an address structure
837 * Returns 0 on success, negative on failure
839 static int igc_set_mac(struct net_device *netdev, void *p)
841 struct igc_adapter *adapter = netdev_priv(netdev);
842 struct igc_hw *hw = &adapter->hw;
843 struct sockaddr *addr = p;
845 if (!is_valid_ether_addr(addr->sa_data))
846 return -EADDRNOTAVAIL;
848 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
849 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
851 /* set the correct pool for the new PF MAC address in entry 0 */
852 igc_set_default_mac_filter(adapter);
858 * igc_write_mc_addr_list - write multicast addresses to MTA
859 * @netdev: network interface device structure
861 * Writes multicast address list to the MTA hash table.
862 * Returns: -ENOMEM on failure
863 * 0 on no addresses written
864 * X on writing X addresses to MTA
866 static int igc_write_mc_addr_list(struct net_device *netdev)
868 struct igc_adapter *adapter = netdev_priv(netdev);
869 struct igc_hw *hw = &adapter->hw;
870 struct netdev_hw_addr *ha;
874 if (netdev_mc_empty(netdev)) {
875 /* nothing to program, so clear mc list */
876 igc_update_mc_addr_list(hw, NULL, 0);
880 mta_list = kcalloc(netdev_mc_count(netdev), 6, GFP_ATOMIC);
884 /* The shared function expects a packed array of only addresses. */
886 netdev_for_each_mc_addr(ha, netdev)
887 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
889 igc_update_mc_addr_list(hw, mta_list, i);
892 return netdev_mc_count(netdev);
895 static __le32 igc_tx_launchtime(struct igc_adapter *adapter, ktime_t txtime)
897 ktime_t cycle_time = adapter->cycle_time;
898 ktime_t base_time = adapter->base_time;
901 /* FIXME: when using ETF together with taprio, we may have a
902 * case where 'delta' is larger than the cycle_time, this may
903 * cause problems if we don't read the current value of
904 * IGC_BASET, as the value writen into the launchtime
905 * descriptor field may be misinterpreted.
907 div_s64_rem(ktime_sub_ns(txtime, base_time), cycle_time, &launchtime);
909 return cpu_to_le32(launchtime);
912 static void igc_tx_ctxtdesc(struct igc_ring *tx_ring,
913 struct igc_tx_buffer *first,
914 u32 vlan_macip_lens, u32 type_tucmd,
917 struct igc_adv_tx_context_desc *context_desc;
918 u16 i = tx_ring->next_to_use;
920 context_desc = IGC_TX_CTXTDESC(tx_ring, i);
923 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
925 /* set bits to identify this as an advanced context descriptor */
926 type_tucmd |= IGC_TXD_CMD_DEXT | IGC_ADVTXD_DTYP_CTXT;
928 /* For i225, context index must be unique per ring. */
929 if (test_bit(IGC_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
930 mss_l4len_idx |= tx_ring->reg_idx << 4;
932 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
933 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
934 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
936 /* We assume there is always a valid Tx time available. Invalid times
937 * should have been handled by the upper layers.
939 if (tx_ring->launchtime_enable) {
940 struct igc_adapter *adapter = netdev_priv(tx_ring->netdev);
941 ktime_t txtime = first->skb->tstamp;
943 first->skb->tstamp = ktime_set(0, 0);
944 context_desc->launch_time = igc_tx_launchtime(adapter,
947 context_desc->launch_time = 0;
951 static inline bool igc_ipv6_csum_is_sctp(struct sk_buff *skb)
953 unsigned int offset = 0;
955 ipv6_find_hdr(skb, &offset, IPPROTO_SCTP, NULL, NULL);
957 return offset == skb_checksum_start_offset(skb);
960 static void igc_tx_csum(struct igc_ring *tx_ring, struct igc_tx_buffer *first)
962 struct sk_buff *skb = first->skb;
963 u32 vlan_macip_lens = 0;
966 if (skb->ip_summed != CHECKSUM_PARTIAL) {
968 if (!(first->tx_flags & IGC_TX_FLAGS_VLAN) &&
969 !tx_ring->launchtime_enable)
974 switch (skb->csum_offset) {
975 case offsetof(struct tcphdr, check):
976 type_tucmd = IGC_ADVTXD_TUCMD_L4T_TCP;
978 case offsetof(struct udphdr, check):
980 case offsetof(struct sctphdr, checksum):
981 /* validate that this is actually an SCTP request */
982 if ((first->protocol == htons(ETH_P_IP) &&
983 (ip_hdr(skb)->protocol == IPPROTO_SCTP)) ||
984 (first->protocol == htons(ETH_P_IPV6) &&
985 igc_ipv6_csum_is_sctp(skb))) {
986 type_tucmd = IGC_ADVTXD_TUCMD_L4T_SCTP;
991 skb_checksum_help(skb);
995 /* update TX checksum flag */
996 first->tx_flags |= IGC_TX_FLAGS_CSUM;
997 vlan_macip_lens = skb_checksum_start_offset(skb) -
998 skb_network_offset(skb);
1000 vlan_macip_lens |= skb_network_offset(skb) << IGC_ADVTXD_MACLEN_SHIFT;
1001 vlan_macip_lens |= first->tx_flags & IGC_TX_FLAGS_VLAN_MASK;
1003 igc_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, type_tucmd, 0);
1006 static int __igc_maybe_stop_tx(struct igc_ring *tx_ring, const u16 size)
1008 struct net_device *netdev = tx_ring->netdev;
1010 netif_stop_subqueue(netdev, tx_ring->queue_index);
1012 /* memory barriier comment */
1015 /* We need to check again in a case another CPU has just
1016 * made room available.
1018 if (igc_desc_unused(tx_ring) < size)
1022 netif_wake_subqueue(netdev, tx_ring->queue_index);
1024 u64_stats_update_begin(&tx_ring->tx_syncp2);
1025 tx_ring->tx_stats.restart_queue2++;
1026 u64_stats_update_end(&tx_ring->tx_syncp2);
1031 static inline int igc_maybe_stop_tx(struct igc_ring *tx_ring, const u16 size)
1033 if (igc_desc_unused(tx_ring) >= size)
1035 return __igc_maybe_stop_tx(tx_ring, size);
1038 #define IGC_SET_FLAG(_input, _flag, _result) \
1039 (((_flag) <= (_result)) ? \
1040 ((u32)((_input) & (_flag)) * ((_result) / (_flag))) : \
1041 ((u32)((_input) & (_flag)) / ((_flag) / (_result))))
1043 static u32 igc_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
1045 /* set type for advanced descriptor with frame checksum insertion */
1046 u32 cmd_type = IGC_ADVTXD_DTYP_DATA |
1047 IGC_ADVTXD_DCMD_DEXT |
1048 IGC_ADVTXD_DCMD_IFCS;
1050 /* set segmentation bits for TSO */
1051 cmd_type |= IGC_SET_FLAG(tx_flags, IGC_TX_FLAGS_TSO,
1052 (IGC_ADVTXD_DCMD_TSE));
1054 /* set timestamp bit if present */
1055 cmd_type |= IGC_SET_FLAG(tx_flags, IGC_TX_FLAGS_TSTAMP,
1056 (IGC_ADVTXD_MAC_TSTAMP));
1061 static void igc_tx_olinfo_status(struct igc_ring *tx_ring,
1062 union igc_adv_tx_desc *tx_desc,
1063 u32 tx_flags, unsigned int paylen)
1065 u32 olinfo_status = paylen << IGC_ADVTXD_PAYLEN_SHIFT;
1067 /* insert L4 checksum */
1068 olinfo_status |= (tx_flags & IGC_TX_FLAGS_CSUM) *
1069 ((IGC_TXD_POPTS_TXSM << 8) /
1072 /* insert IPv4 checksum */
1073 olinfo_status |= (tx_flags & IGC_TX_FLAGS_IPV4) *
1074 (((IGC_TXD_POPTS_IXSM << 8)) /
1077 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
1080 static int igc_tx_map(struct igc_ring *tx_ring,
1081 struct igc_tx_buffer *first,
1084 struct sk_buff *skb = first->skb;
1085 struct igc_tx_buffer *tx_buffer;
1086 union igc_adv_tx_desc *tx_desc;
1087 u32 tx_flags = first->tx_flags;
1089 u16 i = tx_ring->next_to_use;
1090 unsigned int data_len, size;
1092 u32 cmd_type = igc_tx_cmd_type(skb, tx_flags);
1094 tx_desc = IGC_TX_DESC(tx_ring, i);
1096 igc_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
1098 size = skb_headlen(skb);
1099 data_len = skb->data_len;
1101 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
1105 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
1106 if (dma_mapping_error(tx_ring->dev, dma))
1109 /* record length, and DMA address */
1110 dma_unmap_len_set(tx_buffer, len, size);
1111 dma_unmap_addr_set(tx_buffer, dma, dma);
1113 tx_desc->read.buffer_addr = cpu_to_le64(dma);
1115 while (unlikely(size > IGC_MAX_DATA_PER_TXD)) {
1116 tx_desc->read.cmd_type_len =
1117 cpu_to_le32(cmd_type ^ IGC_MAX_DATA_PER_TXD);
1121 if (i == tx_ring->count) {
1122 tx_desc = IGC_TX_DESC(tx_ring, 0);
1125 tx_desc->read.olinfo_status = 0;
1127 dma += IGC_MAX_DATA_PER_TXD;
1128 size -= IGC_MAX_DATA_PER_TXD;
1130 tx_desc->read.buffer_addr = cpu_to_le64(dma);
1133 if (likely(!data_len))
1136 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
1140 if (i == tx_ring->count) {
1141 tx_desc = IGC_TX_DESC(tx_ring, 0);
1144 tx_desc->read.olinfo_status = 0;
1146 size = skb_frag_size(frag);
1149 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
1150 size, DMA_TO_DEVICE);
1152 tx_buffer = &tx_ring->tx_buffer_info[i];
1155 /* write last descriptor with RS and EOP bits */
1156 cmd_type |= size | IGC_TXD_DCMD;
1157 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
1159 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
1161 /* set the timestamp */
1162 first->time_stamp = jiffies;
1164 skb_tx_timestamp(skb);
1166 /* Force memory writes to complete before letting h/w know there
1167 * are new descriptors to fetch. (Only applicable for weak-ordered
1168 * memory model archs, such as IA-64).
1170 * We also need this memory barrier to make certain all of the
1171 * status bits have been updated before next_to_watch is written.
1175 /* set next_to_watch value indicating a packet is present */
1176 first->next_to_watch = tx_desc;
1179 if (i == tx_ring->count)
1182 tx_ring->next_to_use = i;
1184 /* Make sure there is space in the ring for the next send. */
1185 igc_maybe_stop_tx(tx_ring, DESC_NEEDED);
1187 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) {
1188 writel(i, tx_ring->tail);
1193 netdev_err(tx_ring->netdev, "TX DMA map failed\n");
1194 tx_buffer = &tx_ring->tx_buffer_info[i];
1196 /* clear dma mappings for failed tx_buffer_info map */
1197 while (tx_buffer != first) {
1198 if (dma_unmap_len(tx_buffer, len))
1199 dma_unmap_page(tx_ring->dev,
1200 dma_unmap_addr(tx_buffer, dma),
1201 dma_unmap_len(tx_buffer, len),
1203 dma_unmap_len_set(tx_buffer, len, 0);
1206 i += tx_ring->count;
1207 tx_buffer = &tx_ring->tx_buffer_info[i];
1210 if (dma_unmap_len(tx_buffer, len))
1211 dma_unmap_single(tx_ring->dev,
1212 dma_unmap_addr(tx_buffer, dma),
1213 dma_unmap_len(tx_buffer, len),
1215 dma_unmap_len_set(tx_buffer, len, 0);
1217 dev_kfree_skb_any(tx_buffer->skb);
1218 tx_buffer->skb = NULL;
1220 tx_ring->next_to_use = i;
1225 static int igc_tso(struct igc_ring *tx_ring,
1226 struct igc_tx_buffer *first,
1229 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx;
1230 struct sk_buff *skb = first->skb;
1241 u32 paylen, l4_offset;
1244 if (skb->ip_summed != CHECKSUM_PARTIAL)
1247 if (!skb_is_gso(skb))
1250 err = skb_cow_head(skb, 0);
1254 ip.hdr = skb_network_header(skb);
1255 l4.hdr = skb_checksum_start(skb);
1257 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
1258 type_tucmd = IGC_ADVTXD_TUCMD_L4T_TCP;
1260 /* initialize outer IP header fields */
1261 if (ip.v4->version == 4) {
1262 unsigned char *csum_start = skb_checksum_start(skb);
1263 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4);
1265 /* IP header will have to cancel out any data that
1266 * is not a part of the outer IP header
1268 ip.v4->check = csum_fold(csum_partial(trans_start,
1269 csum_start - trans_start,
1271 type_tucmd |= IGC_ADVTXD_TUCMD_IPV4;
1274 first->tx_flags |= IGC_TX_FLAGS_TSO |
1278 ip.v6->payload_len = 0;
1279 first->tx_flags |= IGC_TX_FLAGS_TSO |
1283 /* determine offset of inner transport header */
1284 l4_offset = l4.hdr - skb->data;
1286 /* remove payload length from inner checksum */
1287 paylen = skb->len - l4_offset;
1288 if (type_tucmd & IGC_ADVTXD_TUCMD_L4T_TCP) {
1289 /* compute length of segmentation header */
1290 *hdr_len = (l4.tcp->doff * 4) + l4_offset;
1291 csum_replace_by_diff(&l4.tcp->check,
1292 (__force __wsum)htonl(paylen));
1294 /* compute length of segmentation header */
1295 *hdr_len = sizeof(*l4.udp) + l4_offset;
1296 csum_replace_by_diff(&l4.udp->check,
1297 (__force __wsum)htonl(paylen));
1300 /* update gso size and bytecount with header size */
1301 first->gso_segs = skb_shinfo(skb)->gso_segs;
1302 first->bytecount += (first->gso_segs - 1) * *hdr_len;
1305 mss_l4len_idx = (*hdr_len - l4_offset) << IGC_ADVTXD_L4LEN_SHIFT;
1306 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IGC_ADVTXD_MSS_SHIFT;
1308 /* VLAN MACLEN IPLEN */
1309 vlan_macip_lens = l4.hdr - ip.hdr;
1310 vlan_macip_lens |= (ip.hdr - skb->data) << IGC_ADVTXD_MACLEN_SHIFT;
1311 vlan_macip_lens |= first->tx_flags & IGC_TX_FLAGS_VLAN_MASK;
1313 igc_tx_ctxtdesc(tx_ring, first, vlan_macip_lens,
1314 type_tucmd, mss_l4len_idx);
1319 static netdev_tx_t igc_xmit_frame_ring(struct sk_buff *skb,
1320 struct igc_ring *tx_ring)
1322 u16 count = TXD_USE_COUNT(skb_headlen(skb));
1323 __be16 protocol = vlan_get_protocol(skb);
1324 struct igc_tx_buffer *first;
1330 /* need: 1 descriptor per page * PAGE_SIZE/IGC_MAX_DATA_PER_TXD,
1331 * + 1 desc for skb_headlen/IGC_MAX_DATA_PER_TXD,
1332 * + 2 desc gap to keep tail from touching head,
1333 * + 1 desc for context descriptor,
1334 * otherwise try next time
1336 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
1337 count += TXD_USE_COUNT(skb_frag_size(
1338 &skb_shinfo(skb)->frags[f]));
1340 if (igc_maybe_stop_tx(tx_ring, count + 3)) {
1341 /* this is a hard error */
1342 return NETDEV_TX_BUSY;
1345 /* record the location of the first descriptor for this packet */
1346 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
1348 first->bytecount = skb->len;
1349 first->gso_segs = 1;
1351 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
1352 struct igc_adapter *adapter = netdev_priv(tx_ring->netdev);
1354 /* FIXME: add support for retrieving timestamps from
1355 * the other timer registers before skipping the
1356 * timestamping request.
1358 if (adapter->tstamp_config.tx_type == HWTSTAMP_TX_ON &&
1359 !test_and_set_bit_lock(__IGC_PTP_TX_IN_PROGRESS,
1361 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1362 tx_flags |= IGC_TX_FLAGS_TSTAMP;
1364 adapter->ptp_tx_skb = skb_get(skb);
1365 adapter->ptp_tx_start = jiffies;
1367 adapter->tx_hwtstamp_skipped++;
1371 /* record initial flags and protocol */
1372 first->tx_flags = tx_flags;
1373 first->protocol = protocol;
1375 tso = igc_tso(tx_ring, first, &hdr_len);
1379 igc_tx_csum(tx_ring, first);
1381 igc_tx_map(tx_ring, first, hdr_len);
1383 return NETDEV_TX_OK;
1386 dev_kfree_skb_any(first->skb);
1389 return NETDEV_TX_OK;
1392 static inline struct igc_ring *igc_tx_queue_mapping(struct igc_adapter *adapter,
1393 struct sk_buff *skb)
1395 unsigned int r_idx = skb->queue_mapping;
1397 if (r_idx >= adapter->num_tx_queues)
1398 r_idx = r_idx % adapter->num_tx_queues;
1400 return adapter->tx_ring[r_idx];
1403 static netdev_tx_t igc_xmit_frame(struct sk_buff *skb,
1404 struct net_device *netdev)
1406 struct igc_adapter *adapter = netdev_priv(netdev);
1408 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
1409 * in order to meet this minimum size requirement.
1411 if (skb->len < 17) {
1412 if (skb_padto(skb, 17))
1413 return NETDEV_TX_OK;
1417 return igc_xmit_frame_ring(skb, igc_tx_queue_mapping(adapter, skb));
1420 static void igc_rx_checksum(struct igc_ring *ring,
1421 union igc_adv_rx_desc *rx_desc,
1422 struct sk_buff *skb)
1424 skb_checksum_none_assert(skb);
1426 /* Ignore Checksum bit is set */
1427 if (igc_test_staterr(rx_desc, IGC_RXD_STAT_IXSM))
1430 /* Rx checksum disabled via ethtool */
1431 if (!(ring->netdev->features & NETIF_F_RXCSUM))
1434 /* TCP/UDP checksum error bit is set */
1435 if (igc_test_staterr(rx_desc,
1436 IGC_RXDEXT_STATERR_L4E |
1437 IGC_RXDEXT_STATERR_IPE)) {
1438 /* work around errata with sctp packets where the TCPE aka
1439 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
1440 * packets (aka let the stack check the crc32c)
1442 if (!(skb->len == 60 &&
1443 test_bit(IGC_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
1444 u64_stats_update_begin(&ring->rx_syncp);
1445 ring->rx_stats.csum_err++;
1446 u64_stats_update_end(&ring->rx_syncp);
1448 /* let the stack verify checksum errors */
1451 /* It must be a TCP or UDP packet with a valid checksum */
1452 if (igc_test_staterr(rx_desc, IGC_RXD_STAT_TCPCS |
1453 IGC_RXD_STAT_UDPCS))
1454 skb->ip_summed = CHECKSUM_UNNECESSARY;
1456 netdev_dbg(ring->netdev, "cksum success: bits %08X\n",
1457 le32_to_cpu(rx_desc->wb.upper.status_error));
1460 static inline void igc_rx_hash(struct igc_ring *ring,
1461 union igc_adv_rx_desc *rx_desc,
1462 struct sk_buff *skb)
1464 if (ring->netdev->features & NETIF_F_RXHASH)
1466 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
1471 * igc_process_skb_fields - Populate skb header fields from Rx descriptor
1472 * @rx_ring: rx descriptor ring packet is being transacted on
1473 * @rx_desc: pointer to the EOP Rx descriptor
1474 * @skb: pointer to current skb being populated
1476 * This function checks the ring, descriptor, and packet information in order
1477 * to populate the hash, checksum, VLAN, protocol, and other fields within the
1480 static void igc_process_skb_fields(struct igc_ring *rx_ring,
1481 union igc_adv_rx_desc *rx_desc,
1482 struct sk_buff *skb)
1484 igc_rx_hash(rx_ring, rx_desc, skb);
1486 igc_rx_checksum(rx_ring, rx_desc, skb);
1488 skb_record_rx_queue(skb, rx_ring->queue_index);
1490 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1493 static struct igc_rx_buffer *igc_get_rx_buffer(struct igc_ring *rx_ring,
1494 const unsigned int size)
1496 struct igc_rx_buffer *rx_buffer;
1498 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
1499 prefetchw(rx_buffer->page);
1501 /* we are reusing so sync this buffer for CPU use */
1502 dma_sync_single_range_for_cpu(rx_ring->dev,
1504 rx_buffer->page_offset,
1508 rx_buffer->pagecnt_bias--;
1514 * igc_add_rx_frag - Add contents of Rx buffer to sk_buff
1515 * @rx_ring: rx descriptor ring to transact packets on
1516 * @rx_buffer: buffer containing page to add
1517 * @skb: sk_buff to place the data into
1518 * @size: size of buffer to be added
1520 * This function will add the data contained in rx_buffer->page to the skb.
1522 static void igc_add_rx_frag(struct igc_ring *rx_ring,
1523 struct igc_rx_buffer *rx_buffer,
1524 struct sk_buff *skb,
1527 #if (PAGE_SIZE < 8192)
1528 unsigned int truesize = igc_rx_pg_size(rx_ring) / 2;
1530 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page,
1531 rx_buffer->page_offset, size, truesize);
1532 rx_buffer->page_offset ^= truesize;
1534 unsigned int truesize = ring_uses_build_skb(rx_ring) ?
1535 SKB_DATA_ALIGN(IGC_SKB_PAD + size) :
1536 SKB_DATA_ALIGN(size);
1537 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page,
1538 rx_buffer->page_offset, size, truesize);
1539 rx_buffer->page_offset += truesize;
1543 static struct sk_buff *igc_build_skb(struct igc_ring *rx_ring,
1544 struct igc_rx_buffer *rx_buffer,
1545 union igc_adv_rx_desc *rx_desc,
1548 void *va = page_address(rx_buffer->page) + rx_buffer->page_offset;
1549 #if (PAGE_SIZE < 8192)
1550 unsigned int truesize = igc_rx_pg_size(rx_ring) / 2;
1552 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +
1553 SKB_DATA_ALIGN(IGC_SKB_PAD + size);
1555 struct sk_buff *skb;
1557 /* prefetch first cache line of first page */
1560 /* build an skb around the page buffer */
1561 skb = build_skb(va - IGC_SKB_PAD, truesize);
1565 /* update pointers within the skb to store the data */
1566 skb_reserve(skb, IGC_SKB_PAD);
1567 __skb_put(skb, size);
1569 /* update buffer offset */
1570 #if (PAGE_SIZE < 8192)
1571 rx_buffer->page_offset ^= truesize;
1573 rx_buffer->page_offset += truesize;
1579 static struct sk_buff *igc_construct_skb(struct igc_ring *rx_ring,
1580 struct igc_rx_buffer *rx_buffer,
1581 union igc_adv_rx_desc *rx_desc,
1584 void *va = page_address(rx_buffer->page) + rx_buffer->page_offset;
1585 #if (PAGE_SIZE < 8192)
1586 unsigned int truesize = igc_rx_pg_size(rx_ring) / 2;
1588 unsigned int truesize = SKB_DATA_ALIGN(size);
1590 unsigned int headlen;
1591 struct sk_buff *skb;
1593 /* prefetch first cache line of first page */
1596 /* allocate a skb to store the frags */
1597 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGC_RX_HDR_LEN);
1601 if (unlikely(igc_test_staterr(rx_desc, IGC_RXDADV_STAT_TSIP))) {
1602 igc_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
1603 va += IGC_TS_HDR_LEN;
1604 size -= IGC_TS_HDR_LEN;
1607 /* Determine available headroom for copy */
1609 if (headlen > IGC_RX_HDR_LEN)
1610 headlen = eth_get_headlen(skb->dev, va, IGC_RX_HDR_LEN);
1612 /* align pull length to size of long to optimize memcpy performance */
1613 memcpy(__skb_put(skb, headlen), va, ALIGN(headlen, sizeof(long)));
1615 /* update all of the pointers */
1618 skb_add_rx_frag(skb, 0, rx_buffer->page,
1619 (va + headlen) - page_address(rx_buffer->page),
1621 #if (PAGE_SIZE < 8192)
1622 rx_buffer->page_offset ^= truesize;
1624 rx_buffer->page_offset += truesize;
1627 rx_buffer->pagecnt_bias++;
1634 * igc_reuse_rx_page - page flip buffer and store it back on the ring
1635 * @rx_ring: rx descriptor ring to store buffers on
1636 * @old_buff: donor buffer to have page reused
1638 * Synchronizes page for reuse by the adapter
1640 static void igc_reuse_rx_page(struct igc_ring *rx_ring,
1641 struct igc_rx_buffer *old_buff)
1643 u16 nta = rx_ring->next_to_alloc;
1644 struct igc_rx_buffer *new_buff;
1646 new_buff = &rx_ring->rx_buffer_info[nta];
1648 /* update, and store next to alloc */
1650 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1652 /* Transfer page from old buffer to new buffer.
1653 * Move each member individually to avoid possible store
1654 * forwarding stalls.
1656 new_buff->dma = old_buff->dma;
1657 new_buff->page = old_buff->page;
1658 new_buff->page_offset = old_buff->page_offset;
1659 new_buff->pagecnt_bias = old_buff->pagecnt_bias;
1662 static inline bool igc_page_is_reserved(struct page *page)
1664 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page);
1667 static bool igc_can_reuse_rx_page(struct igc_rx_buffer *rx_buffer)
1669 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias;
1670 struct page *page = rx_buffer->page;
1672 /* avoid re-using remote pages */
1673 if (unlikely(igc_page_is_reserved(page)))
1676 #if (PAGE_SIZE < 8192)
1677 /* if we are only owner of page we can reuse it */
1678 if (unlikely((page_ref_count(page) - pagecnt_bias) > 1))
1681 #define IGC_LAST_OFFSET \
1682 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IGC_RXBUFFER_2048)
1684 if (rx_buffer->page_offset > IGC_LAST_OFFSET)
1688 /* If we have drained the page fragment pool we need to update
1689 * the pagecnt_bias and page count so that we fully restock the
1690 * number of references the driver holds.
1692 if (unlikely(!pagecnt_bias)) {
1693 page_ref_add(page, USHRT_MAX);
1694 rx_buffer->pagecnt_bias = USHRT_MAX;
1701 * igc_is_non_eop - process handling of non-EOP buffers
1702 * @rx_ring: Rx ring being processed
1703 * @rx_desc: Rx descriptor for current buffer
1705 * This function updates next to clean. If the buffer is an EOP buffer
1706 * this function exits returning false, otherwise it will place the
1707 * sk_buff in the next buffer to be chained and return true indicating
1708 * that this is in fact a non-EOP buffer.
1710 static bool igc_is_non_eop(struct igc_ring *rx_ring,
1711 union igc_adv_rx_desc *rx_desc)
1713 u32 ntc = rx_ring->next_to_clean + 1;
1715 /* fetch, update, and store next to clean */
1716 ntc = (ntc < rx_ring->count) ? ntc : 0;
1717 rx_ring->next_to_clean = ntc;
1719 prefetch(IGC_RX_DESC(rx_ring, ntc));
1721 if (likely(igc_test_staterr(rx_desc, IGC_RXD_STAT_EOP)))
1728 * igc_cleanup_headers - Correct corrupted or empty headers
1729 * @rx_ring: rx descriptor ring packet is being transacted on
1730 * @rx_desc: pointer to the EOP Rx descriptor
1731 * @skb: pointer to current skb being fixed
1733 * Address the case where we are pulling data in on pages only
1734 * and as such no data is present in the skb header.
1736 * In addition if skb is not at least 60 bytes we need to pad it so that
1737 * it is large enough to qualify as a valid Ethernet frame.
1739 * Returns true if an error was encountered and skb was freed.
1741 static bool igc_cleanup_headers(struct igc_ring *rx_ring,
1742 union igc_adv_rx_desc *rx_desc,
1743 struct sk_buff *skb)
1745 if (unlikely(igc_test_staterr(rx_desc, IGC_RXDEXT_STATERR_RXE))) {
1746 struct net_device *netdev = rx_ring->netdev;
1748 if (!(netdev->features & NETIF_F_RXALL)) {
1749 dev_kfree_skb_any(skb);
1754 /* if eth_skb_pad returns an error the skb was freed */
1755 if (eth_skb_pad(skb))
1761 static void igc_put_rx_buffer(struct igc_ring *rx_ring,
1762 struct igc_rx_buffer *rx_buffer)
1764 if (igc_can_reuse_rx_page(rx_buffer)) {
1765 /* hand second half of page back to the ring */
1766 igc_reuse_rx_page(rx_ring, rx_buffer);
1768 /* We are not reusing the buffer so unmap it and free
1769 * any references we are holding to it
1771 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma,
1772 igc_rx_pg_size(rx_ring), DMA_FROM_DEVICE,
1774 __page_frag_cache_drain(rx_buffer->page,
1775 rx_buffer->pagecnt_bias);
1778 /* clear contents of rx_buffer */
1779 rx_buffer->page = NULL;
1782 static inline unsigned int igc_rx_offset(struct igc_ring *rx_ring)
1784 return ring_uses_build_skb(rx_ring) ? IGC_SKB_PAD : 0;
1787 static bool igc_alloc_mapped_page(struct igc_ring *rx_ring,
1788 struct igc_rx_buffer *bi)
1790 struct page *page = bi->page;
1793 /* since we are recycling buffers we should seldom need to alloc */
1797 /* alloc new page for storage */
1798 page = dev_alloc_pages(igc_rx_pg_order(rx_ring));
1799 if (unlikely(!page)) {
1800 rx_ring->rx_stats.alloc_failed++;
1804 /* map page for use */
1805 dma = dma_map_page_attrs(rx_ring->dev, page, 0,
1806 igc_rx_pg_size(rx_ring),
1810 /* if mapping failed free memory back to system since
1811 * there isn't much point in holding memory we can't use
1813 if (dma_mapping_error(rx_ring->dev, dma)) {
1816 rx_ring->rx_stats.alloc_failed++;
1822 bi->page_offset = igc_rx_offset(rx_ring);
1823 bi->pagecnt_bias = 1;
1829 * igc_alloc_rx_buffers - Replace used receive buffers; packet split
1830 * @rx_ring: rx descriptor ring
1831 * @cleaned_count: number of buffers to clean
1833 static void igc_alloc_rx_buffers(struct igc_ring *rx_ring, u16 cleaned_count)
1835 union igc_adv_rx_desc *rx_desc;
1836 u16 i = rx_ring->next_to_use;
1837 struct igc_rx_buffer *bi;
1844 rx_desc = IGC_RX_DESC(rx_ring, i);
1845 bi = &rx_ring->rx_buffer_info[i];
1846 i -= rx_ring->count;
1848 bufsz = igc_rx_bufsz(rx_ring);
1851 if (!igc_alloc_mapped_page(rx_ring, bi))
1854 /* sync the buffer for use by the device */
1855 dma_sync_single_range_for_device(rx_ring->dev, bi->dma,
1856 bi->page_offset, bufsz,
1859 /* Refresh the desc even if buffer_addrs didn't change
1860 * because each write-back erases this info.
1862 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
1868 rx_desc = IGC_RX_DESC(rx_ring, 0);
1869 bi = rx_ring->rx_buffer_info;
1870 i -= rx_ring->count;
1873 /* clear the length for the next_to_use descriptor */
1874 rx_desc->wb.upper.length = 0;
1877 } while (cleaned_count);
1879 i += rx_ring->count;
1881 if (rx_ring->next_to_use != i) {
1882 /* record the next descriptor to use */
1883 rx_ring->next_to_use = i;
1885 /* update next to alloc since we have filled the ring */
1886 rx_ring->next_to_alloc = i;
1888 /* Force memory writes to complete before letting h/w
1889 * know there are new descriptors to fetch. (Only
1890 * applicable for weak-ordered memory model archs,
1894 writel(i, rx_ring->tail);
1898 static int igc_clean_rx_irq(struct igc_q_vector *q_vector, const int budget)
1900 unsigned int total_bytes = 0, total_packets = 0;
1901 struct igc_ring *rx_ring = q_vector->rx.ring;
1902 struct sk_buff *skb = rx_ring->skb;
1903 u16 cleaned_count = igc_desc_unused(rx_ring);
1905 while (likely(total_packets < budget)) {
1906 union igc_adv_rx_desc *rx_desc;
1907 struct igc_rx_buffer *rx_buffer;
1910 /* return some buffers to hardware, one at a time is too slow */
1911 if (cleaned_count >= IGC_RX_BUFFER_WRITE) {
1912 igc_alloc_rx_buffers(rx_ring, cleaned_count);
1916 rx_desc = IGC_RX_DESC(rx_ring, rx_ring->next_to_clean);
1917 size = le16_to_cpu(rx_desc->wb.upper.length);
1921 /* This memory barrier is needed to keep us from reading
1922 * any other fields out of the rx_desc until we know the
1923 * descriptor has been written back
1927 rx_buffer = igc_get_rx_buffer(rx_ring, size);
1929 /* retrieve a buffer from the ring */
1931 igc_add_rx_frag(rx_ring, rx_buffer, skb, size);
1932 else if (ring_uses_build_skb(rx_ring))
1933 skb = igc_build_skb(rx_ring, rx_buffer, rx_desc, size);
1935 skb = igc_construct_skb(rx_ring, rx_buffer,
1938 /* exit if we failed to retrieve a buffer */
1940 rx_ring->rx_stats.alloc_failed++;
1941 rx_buffer->pagecnt_bias++;
1945 igc_put_rx_buffer(rx_ring, rx_buffer);
1948 /* fetch next buffer in frame if non-eop */
1949 if (igc_is_non_eop(rx_ring, rx_desc))
1952 /* verify the packet layout is correct */
1953 if (igc_cleanup_headers(rx_ring, rx_desc, skb)) {
1958 /* probably a little skewed due to removing CRC */
1959 total_bytes += skb->len;
1961 /* populate checksum, VLAN, and protocol */
1962 igc_process_skb_fields(rx_ring, rx_desc, skb);
1964 napi_gro_receive(&q_vector->napi, skb);
1966 /* reset skb pointer */
1969 /* update budget accounting */
1973 /* place incomplete frames back on ring for completion */
1976 u64_stats_update_begin(&rx_ring->rx_syncp);
1977 rx_ring->rx_stats.packets += total_packets;
1978 rx_ring->rx_stats.bytes += total_bytes;
1979 u64_stats_update_end(&rx_ring->rx_syncp);
1980 q_vector->rx.total_packets += total_packets;
1981 q_vector->rx.total_bytes += total_bytes;
1984 igc_alloc_rx_buffers(rx_ring, cleaned_count);
1986 return total_packets;
1990 * igc_clean_tx_irq - Reclaim resources after transmit completes
1991 * @q_vector: pointer to q_vector containing needed info
1992 * @napi_budget: Used to determine if we are in netpoll
1994 * returns true if ring is completely cleaned
1996 static bool igc_clean_tx_irq(struct igc_q_vector *q_vector, int napi_budget)
1998 struct igc_adapter *adapter = q_vector->adapter;
1999 unsigned int total_bytes = 0, total_packets = 0;
2000 unsigned int budget = q_vector->tx.work_limit;
2001 struct igc_ring *tx_ring = q_vector->tx.ring;
2002 unsigned int i = tx_ring->next_to_clean;
2003 struct igc_tx_buffer *tx_buffer;
2004 union igc_adv_tx_desc *tx_desc;
2006 if (test_bit(__IGC_DOWN, &adapter->state))
2009 tx_buffer = &tx_ring->tx_buffer_info[i];
2010 tx_desc = IGC_TX_DESC(tx_ring, i);
2011 i -= tx_ring->count;
2014 union igc_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
2016 /* if next_to_watch is not set then there is no work pending */
2020 /* prevent any other reads prior to eop_desc */
2023 /* if DD is not set pending work has not been completed */
2024 if (!(eop_desc->wb.status & cpu_to_le32(IGC_TXD_STAT_DD)))
2027 /* clear next_to_watch to prevent false hangs */
2028 tx_buffer->next_to_watch = NULL;
2030 /* update the statistics for this packet */
2031 total_bytes += tx_buffer->bytecount;
2032 total_packets += tx_buffer->gso_segs;
2035 napi_consume_skb(tx_buffer->skb, napi_budget);
2037 /* unmap skb header data */
2038 dma_unmap_single(tx_ring->dev,
2039 dma_unmap_addr(tx_buffer, dma),
2040 dma_unmap_len(tx_buffer, len),
2043 /* clear tx_buffer data */
2044 dma_unmap_len_set(tx_buffer, len, 0);
2046 /* clear last DMA location and unmap remaining buffers */
2047 while (tx_desc != eop_desc) {
2052 i -= tx_ring->count;
2053 tx_buffer = tx_ring->tx_buffer_info;
2054 tx_desc = IGC_TX_DESC(tx_ring, 0);
2057 /* unmap any remaining paged data */
2058 if (dma_unmap_len(tx_buffer, len)) {
2059 dma_unmap_page(tx_ring->dev,
2060 dma_unmap_addr(tx_buffer, dma),
2061 dma_unmap_len(tx_buffer, len),
2063 dma_unmap_len_set(tx_buffer, len, 0);
2067 /* move us one more past the eop_desc for start of next pkt */
2072 i -= tx_ring->count;
2073 tx_buffer = tx_ring->tx_buffer_info;
2074 tx_desc = IGC_TX_DESC(tx_ring, 0);
2077 /* issue prefetch for next Tx descriptor */
2080 /* update budget accounting */
2082 } while (likely(budget));
2084 netdev_tx_completed_queue(txring_txq(tx_ring),
2085 total_packets, total_bytes);
2087 i += tx_ring->count;
2088 tx_ring->next_to_clean = i;
2089 u64_stats_update_begin(&tx_ring->tx_syncp);
2090 tx_ring->tx_stats.bytes += total_bytes;
2091 tx_ring->tx_stats.packets += total_packets;
2092 u64_stats_update_end(&tx_ring->tx_syncp);
2093 q_vector->tx.total_bytes += total_bytes;
2094 q_vector->tx.total_packets += total_packets;
2096 if (test_bit(IGC_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
2097 struct igc_hw *hw = &adapter->hw;
2099 /* Detect a transmit hang in hardware, this serializes the
2100 * check with the clearing of time_stamp and movement of i
2102 clear_bit(IGC_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
2103 if (tx_buffer->next_to_watch &&
2104 time_after(jiffies, tx_buffer->time_stamp +
2105 (adapter->tx_timeout_factor * HZ)) &&
2106 !(rd32(IGC_STATUS) & IGC_STATUS_TXOFF)) {
2107 /* detected Tx unit hang */
2108 netdev_err(tx_ring->netdev,
2109 "Detected Tx Unit Hang\n"
2113 " next_to_use <%x>\n"
2114 " next_to_clean <%x>\n"
2115 "buffer_info[next_to_clean]\n"
2116 " time_stamp <%lx>\n"
2117 " next_to_watch <%p>\n"
2119 " desc.status <%x>\n",
2120 tx_ring->queue_index,
2121 rd32(IGC_TDH(tx_ring->reg_idx)),
2122 readl(tx_ring->tail),
2123 tx_ring->next_to_use,
2124 tx_ring->next_to_clean,
2125 tx_buffer->time_stamp,
2126 tx_buffer->next_to_watch,
2128 tx_buffer->next_to_watch->wb.status);
2129 netif_stop_subqueue(tx_ring->netdev,
2130 tx_ring->queue_index);
2132 /* we are about to reset, no point in enabling stuff */
2137 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
2138 if (unlikely(total_packets &&
2139 netif_carrier_ok(tx_ring->netdev) &&
2140 igc_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
2141 /* Make sure that anybody stopping the queue after this
2142 * sees the new next_to_clean.
2145 if (__netif_subqueue_stopped(tx_ring->netdev,
2146 tx_ring->queue_index) &&
2147 !(test_bit(__IGC_DOWN, &adapter->state))) {
2148 netif_wake_subqueue(tx_ring->netdev,
2149 tx_ring->queue_index);
2151 u64_stats_update_begin(&tx_ring->tx_syncp);
2152 tx_ring->tx_stats.restart_queue++;
2153 u64_stats_update_end(&tx_ring->tx_syncp);
2160 static int igc_find_mac_filter(struct igc_adapter *adapter,
2161 enum igc_mac_filter_type type, const u8 *addr)
2163 struct igc_hw *hw = &adapter->hw;
2164 int max_entries = hw->mac.rar_entry_count;
2168 for (i = 0; i < max_entries; i++) {
2169 ral = rd32(IGC_RAL(i));
2170 rah = rd32(IGC_RAH(i));
2172 if (!(rah & IGC_RAH_AV))
2174 if (!!(rah & IGC_RAH_ASEL_SRC_ADDR) != type)
2176 if ((rah & IGC_RAH_RAH_MASK) !=
2177 le16_to_cpup((__le16 *)(addr + 4)))
2179 if (ral != le32_to_cpup((__le32 *)(addr)))
2188 static int igc_get_avail_mac_filter_slot(struct igc_adapter *adapter)
2190 struct igc_hw *hw = &adapter->hw;
2191 int max_entries = hw->mac.rar_entry_count;
2195 for (i = 0; i < max_entries; i++) {
2196 rah = rd32(IGC_RAH(i));
2198 if (!(rah & IGC_RAH_AV))
2206 * igc_add_mac_filter() - Add MAC address filter
2207 * @adapter: Pointer to adapter where the filter should be added
2208 * @type: MAC address filter type (source or destination)
2209 * @addr: MAC address
2210 * @queue: If non-negative, queue assignment feature is enabled and frames
2211 * matching the filter are enqueued onto 'queue'. Otherwise, queue
2212 * assignment is disabled.
2214 * Return: 0 in case of success, negative errno code otherwise.
2216 static int igc_add_mac_filter(struct igc_adapter *adapter,
2217 enum igc_mac_filter_type type, const u8 *addr,
2220 struct net_device *dev = adapter->netdev;
2223 index = igc_find_mac_filter(adapter, type, addr);
2227 index = igc_get_avail_mac_filter_slot(adapter);
2231 netdev_dbg(dev, "Add MAC address filter: index %d type %s address %pM queue %d\n",
2232 index, type == IGC_MAC_FILTER_TYPE_DST ? "dst" : "src",
2236 igc_set_mac_filter_hw(adapter, index, type, addr, queue);
2241 * igc_del_mac_filter() - Delete MAC address filter
2242 * @adapter: Pointer to adapter where the filter should be deleted from
2243 * @type: MAC address filter type (source or destination)
2244 * @addr: MAC address
2246 static void igc_del_mac_filter(struct igc_adapter *adapter,
2247 enum igc_mac_filter_type type, const u8 *addr)
2249 struct net_device *dev = adapter->netdev;
2252 index = igc_find_mac_filter(adapter, type, addr);
2257 /* If this is the default filter, we don't actually delete it.
2258 * We just reset to its default value i.e. disable queue
2261 netdev_dbg(dev, "Disable default MAC filter queue assignment");
2263 igc_set_mac_filter_hw(adapter, 0, type, addr, -1);
2265 netdev_dbg(dev, "Delete MAC address filter: index %d type %s address %pM\n",
2267 type == IGC_MAC_FILTER_TYPE_DST ? "dst" : "src",
2270 igc_clear_mac_filter_hw(adapter, index);
2275 * igc_add_vlan_prio_filter() - Add VLAN priority filter
2276 * @adapter: Pointer to adapter where the filter should be added
2277 * @prio: VLAN priority value
2278 * @queue: Queue number which matching frames are assigned to
2280 * Return: 0 in case of success, negative errno code otherwise.
2282 static int igc_add_vlan_prio_filter(struct igc_adapter *adapter, int prio,
2285 struct net_device *dev = adapter->netdev;
2286 struct igc_hw *hw = &adapter->hw;
2289 vlanpqf = rd32(IGC_VLANPQF);
2291 if (vlanpqf & IGC_VLANPQF_VALID(prio)) {
2292 netdev_dbg(dev, "VLAN priority filter already in use\n");
2296 vlanpqf |= IGC_VLANPQF_QSEL(prio, queue);
2297 vlanpqf |= IGC_VLANPQF_VALID(prio);
2299 wr32(IGC_VLANPQF, vlanpqf);
2301 netdev_dbg(dev, "Add VLAN priority filter: prio %d queue %d\n",
2307 * igc_del_vlan_prio_filter() - Delete VLAN priority filter
2308 * @adapter: Pointer to adapter where the filter should be deleted from
2309 * @prio: VLAN priority value
2311 static void igc_del_vlan_prio_filter(struct igc_adapter *adapter, int prio)
2313 struct igc_hw *hw = &adapter->hw;
2316 vlanpqf = rd32(IGC_VLANPQF);
2318 vlanpqf &= ~IGC_VLANPQF_VALID(prio);
2319 vlanpqf &= ~IGC_VLANPQF_QSEL(prio, IGC_VLANPQF_QUEUE_MASK);
2321 wr32(IGC_VLANPQF, vlanpqf);
2323 netdev_dbg(adapter->netdev, "Delete VLAN priority filter: prio %d\n",
2327 static int igc_get_avail_etype_filter_slot(struct igc_adapter *adapter)
2329 struct igc_hw *hw = &adapter->hw;
2332 for (i = 0; i < MAX_ETYPE_FILTER; i++) {
2333 u32 etqf = rd32(IGC_ETQF(i));
2335 if (!(etqf & IGC_ETQF_FILTER_ENABLE))
2343 * igc_add_etype_filter() - Add ethertype filter
2344 * @adapter: Pointer to adapter where the filter should be added
2345 * @etype: Ethertype value
2346 * @queue: If non-negative, queue assignment feature is enabled and frames
2347 * matching the filter are enqueued onto 'queue'. Otherwise, queue
2348 * assignment is disabled.
2350 * Return: 0 in case of success, negative errno code otherwise.
2352 static int igc_add_etype_filter(struct igc_adapter *adapter, u16 etype,
2355 struct igc_hw *hw = &adapter->hw;
2359 index = igc_get_avail_etype_filter_slot(adapter);
2363 etqf = rd32(IGC_ETQF(index));
2365 etqf &= ~IGC_ETQF_ETYPE_MASK;
2369 etqf &= ~IGC_ETQF_QUEUE_MASK;
2370 etqf |= (queue << IGC_ETQF_QUEUE_SHIFT);
2371 etqf |= IGC_ETQF_QUEUE_ENABLE;
2374 etqf |= IGC_ETQF_FILTER_ENABLE;
2376 wr32(IGC_ETQF(index), etqf);
2378 netdev_dbg(adapter->netdev, "Add ethertype filter: etype %04x queue %d\n",
2383 static int igc_find_etype_filter(struct igc_adapter *adapter, u16 etype)
2385 struct igc_hw *hw = &adapter->hw;
2388 for (i = 0; i < MAX_ETYPE_FILTER; i++) {
2389 u32 etqf = rd32(IGC_ETQF(i));
2391 if ((etqf & IGC_ETQF_ETYPE_MASK) == etype)
2399 * igc_del_etype_filter() - Delete ethertype filter
2400 * @adapter: Pointer to adapter where the filter should be deleted from
2401 * @etype: Ethertype value
2403 static void igc_del_etype_filter(struct igc_adapter *adapter, u16 etype)
2405 struct igc_hw *hw = &adapter->hw;
2408 index = igc_find_etype_filter(adapter, etype);
2412 wr32(IGC_ETQF(index), 0);
2414 netdev_dbg(adapter->netdev, "Delete ethertype filter: etype %04x\n",
2418 static int igc_enable_nfc_rule(struct igc_adapter *adapter,
2419 const struct igc_nfc_rule *rule)
2423 if (rule->filter.match_flags & IGC_FILTER_FLAG_ETHER_TYPE) {
2424 err = igc_add_etype_filter(adapter, rule->filter.etype,
2430 if (rule->filter.match_flags & IGC_FILTER_FLAG_SRC_MAC_ADDR) {
2431 err = igc_add_mac_filter(adapter, IGC_MAC_FILTER_TYPE_SRC,
2432 rule->filter.src_addr, rule->action);
2437 if (rule->filter.match_flags & IGC_FILTER_FLAG_DST_MAC_ADDR) {
2438 err = igc_add_mac_filter(adapter, IGC_MAC_FILTER_TYPE_DST,
2439 rule->filter.dst_addr, rule->action);
2444 if (rule->filter.match_flags & IGC_FILTER_FLAG_VLAN_TCI) {
2445 int prio = (rule->filter.vlan_tci & VLAN_PRIO_MASK) >>
2448 err = igc_add_vlan_prio_filter(adapter, prio, rule->action);
2456 static void igc_disable_nfc_rule(struct igc_adapter *adapter,
2457 const struct igc_nfc_rule *rule)
2459 if (rule->filter.match_flags & IGC_FILTER_FLAG_ETHER_TYPE)
2460 igc_del_etype_filter(adapter, rule->filter.etype);
2462 if (rule->filter.match_flags & IGC_FILTER_FLAG_VLAN_TCI) {
2463 int prio = (rule->filter.vlan_tci & VLAN_PRIO_MASK) >>
2466 igc_del_vlan_prio_filter(adapter, prio);
2469 if (rule->filter.match_flags & IGC_FILTER_FLAG_SRC_MAC_ADDR)
2470 igc_del_mac_filter(adapter, IGC_MAC_FILTER_TYPE_SRC,
2471 rule->filter.src_addr);
2473 if (rule->filter.match_flags & IGC_FILTER_FLAG_DST_MAC_ADDR)
2474 igc_del_mac_filter(adapter, IGC_MAC_FILTER_TYPE_DST,
2475 rule->filter.dst_addr);
2479 * igc_get_nfc_rule() - Get NFC rule
2480 * @adapter: Pointer to adapter
2481 * @location: Rule location
2483 * Context: Expects adapter->nfc_rule_lock to be held by caller.
2485 * Return: Pointer to NFC rule at @location. If not found, NULL.
2487 struct igc_nfc_rule *igc_get_nfc_rule(struct igc_adapter *adapter,
2490 struct igc_nfc_rule *rule;
2492 list_for_each_entry(rule, &adapter->nfc_rule_list, list) {
2493 if (rule->location == location)
2495 if (rule->location > location)
2503 * igc_del_nfc_rule() - Delete NFC rule
2504 * @adapter: Pointer to adapter
2505 * @rule: Pointer to rule to be deleted
2507 * Disable NFC rule in hardware and delete it from adapter.
2509 * Context: Expects adapter->nfc_rule_lock to be held by caller.
2511 void igc_del_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule)
2513 igc_disable_nfc_rule(adapter, rule);
2515 list_del(&rule->list);
2516 adapter->nfc_rule_count--;
2521 static void igc_flush_nfc_rules(struct igc_adapter *adapter)
2523 struct igc_nfc_rule *rule, *tmp;
2525 mutex_lock(&adapter->nfc_rule_lock);
2527 list_for_each_entry_safe(rule, tmp, &adapter->nfc_rule_list, list)
2528 igc_del_nfc_rule(adapter, rule);
2530 mutex_unlock(&adapter->nfc_rule_lock);
2534 * igc_add_nfc_rule() - Add NFC rule
2535 * @adapter: Pointer to adapter
2536 * @rule: Pointer to rule to be added
2538 * Enable NFC rule in hardware and add it to adapter.
2540 * Context: Expects adapter->nfc_rule_lock to be held by caller.
2542 * Return: 0 on success, negative errno on failure.
2544 int igc_add_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule)
2546 struct igc_nfc_rule *pred, *cur;
2549 err = igc_enable_nfc_rule(adapter, rule);
2554 list_for_each_entry(cur, &adapter->nfc_rule_list, list) {
2555 if (cur->location >= rule->location)
2560 list_add(&rule->list, pred ? &pred->list : &adapter->nfc_rule_list);
2561 adapter->nfc_rule_count++;
2565 static void igc_restore_nfc_rules(struct igc_adapter *adapter)
2567 struct igc_nfc_rule *rule;
2569 mutex_lock(&adapter->nfc_rule_lock);
2571 list_for_each_entry_reverse(rule, &adapter->nfc_rule_list, list)
2572 igc_enable_nfc_rule(adapter, rule);
2574 mutex_unlock(&adapter->nfc_rule_lock);
2577 static int igc_uc_sync(struct net_device *netdev, const unsigned char *addr)
2579 struct igc_adapter *adapter = netdev_priv(netdev);
2581 return igc_add_mac_filter(adapter, IGC_MAC_FILTER_TYPE_DST, addr, -1);
2584 static int igc_uc_unsync(struct net_device *netdev, const unsigned char *addr)
2586 struct igc_adapter *adapter = netdev_priv(netdev);
2588 igc_del_mac_filter(adapter, IGC_MAC_FILTER_TYPE_DST, addr);
2593 * igc_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
2594 * @netdev: network interface device structure
2596 * The set_rx_mode entry point is called whenever the unicast or multicast
2597 * address lists or the network interface flags are updated. This routine is
2598 * responsible for configuring the hardware for proper unicast, multicast,
2599 * promiscuous mode, and all-multi behavior.
2601 static void igc_set_rx_mode(struct net_device *netdev)
2603 struct igc_adapter *adapter = netdev_priv(netdev);
2604 struct igc_hw *hw = &adapter->hw;
2605 u32 rctl = 0, rlpml = MAX_JUMBO_FRAME_SIZE;
2608 /* Check for Promiscuous and All Multicast modes */
2609 if (netdev->flags & IFF_PROMISC) {
2610 rctl |= IGC_RCTL_UPE | IGC_RCTL_MPE;
2612 if (netdev->flags & IFF_ALLMULTI) {
2613 rctl |= IGC_RCTL_MPE;
2615 /* Write addresses to the MTA, if the attempt fails
2616 * then we should just turn on promiscuous mode so
2617 * that we can at least receive multicast traffic
2619 count = igc_write_mc_addr_list(netdev);
2621 rctl |= IGC_RCTL_MPE;
2625 /* Write addresses to available RAR registers, if there is not
2626 * sufficient space to store all the addresses then enable
2627 * unicast promiscuous mode
2629 if (__dev_uc_sync(netdev, igc_uc_sync, igc_uc_unsync))
2630 rctl |= IGC_RCTL_UPE;
2632 /* update state of unicast and multicast */
2633 rctl |= rd32(IGC_RCTL) & ~(IGC_RCTL_UPE | IGC_RCTL_MPE);
2634 wr32(IGC_RCTL, rctl);
2636 #if (PAGE_SIZE < 8192)
2637 if (adapter->max_frame_size <= IGC_MAX_FRAME_BUILD_SKB)
2638 rlpml = IGC_MAX_FRAME_BUILD_SKB;
2640 wr32(IGC_RLPML, rlpml);
2644 * igc_configure - configure the hardware for RX and TX
2645 * @adapter: private board structure
2647 static void igc_configure(struct igc_adapter *adapter)
2649 struct net_device *netdev = adapter->netdev;
2652 igc_get_hw_control(adapter);
2653 igc_set_rx_mode(netdev);
2655 igc_setup_tctl(adapter);
2656 igc_setup_mrqc(adapter);
2657 igc_setup_rctl(adapter);
2659 igc_set_default_mac_filter(adapter);
2660 igc_restore_nfc_rules(adapter);
2662 igc_configure_tx(adapter);
2663 igc_configure_rx(adapter);
2665 igc_rx_fifo_flush_base(&adapter->hw);
2667 /* call igc_desc_unused which always leaves
2668 * at least 1 descriptor unused to make sure
2669 * next_to_use != next_to_clean
2671 for (i = 0; i < adapter->num_rx_queues; i++) {
2672 struct igc_ring *ring = adapter->rx_ring[i];
2674 igc_alloc_rx_buffers(ring, igc_desc_unused(ring));
2679 * igc_write_ivar - configure ivar for given MSI-X vector
2680 * @hw: pointer to the HW structure
2681 * @msix_vector: vector number we are allocating to a given ring
2682 * @index: row index of IVAR register to write within IVAR table
2683 * @offset: column offset of in IVAR, should be multiple of 8
2685 * The IVAR table consists of 2 columns,
2686 * each containing an cause allocation for an Rx and Tx ring, and a
2687 * variable number of rows depending on the number of queues supported.
2689 static void igc_write_ivar(struct igc_hw *hw, int msix_vector,
2690 int index, int offset)
2692 u32 ivar = array_rd32(IGC_IVAR0, index);
2694 /* clear any bits that are currently set */
2695 ivar &= ~((u32)0xFF << offset);
2697 /* write vector and valid bit */
2698 ivar |= (msix_vector | IGC_IVAR_VALID) << offset;
2700 array_wr32(IGC_IVAR0, index, ivar);
2703 static void igc_assign_vector(struct igc_q_vector *q_vector, int msix_vector)
2705 struct igc_adapter *adapter = q_vector->adapter;
2706 struct igc_hw *hw = &adapter->hw;
2707 int rx_queue = IGC_N0_QUEUE;
2708 int tx_queue = IGC_N0_QUEUE;
2710 if (q_vector->rx.ring)
2711 rx_queue = q_vector->rx.ring->reg_idx;
2712 if (q_vector->tx.ring)
2713 tx_queue = q_vector->tx.ring->reg_idx;
2715 switch (hw->mac.type) {
2717 if (rx_queue > IGC_N0_QUEUE)
2718 igc_write_ivar(hw, msix_vector,
2720 (rx_queue & 0x1) << 4);
2721 if (tx_queue > IGC_N0_QUEUE)
2722 igc_write_ivar(hw, msix_vector,
2724 ((tx_queue & 0x1) << 4) + 8);
2725 q_vector->eims_value = BIT(msix_vector);
2728 WARN_ONCE(hw->mac.type != igc_i225, "Wrong MAC type\n");
2732 /* add q_vector eims value to global eims_enable_mask */
2733 adapter->eims_enable_mask |= q_vector->eims_value;
2735 /* configure q_vector to set itr on first interrupt */
2736 q_vector->set_itr = 1;
2740 * igc_configure_msix - Configure MSI-X hardware
2741 * @adapter: Pointer to adapter structure
2743 * igc_configure_msix sets up the hardware to properly
2744 * generate MSI-X interrupts.
2746 static void igc_configure_msix(struct igc_adapter *adapter)
2748 struct igc_hw *hw = &adapter->hw;
2752 adapter->eims_enable_mask = 0;
2754 /* set vector for other causes, i.e. link changes */
2755 switch (hw->mac.type) {
2757 /* Turn on MSI-X capability first, or our settings
2758 * won't stick. And it will take days to debug.
2760 wr32(IGC_GPIE, IGC_GPIE_MSIX_MODE |
2761 IGC_GPIE_PBA | IGC_GPIE_EIAME |
2764 /* enable msix_other interrupt */
2765 adapter->eims_other = BIT(vector);
2766 tmp = (vector++ | IGC_IVAR_VALID) << 8;
2768 wr32(IGC_IVAR_MISC, tmp);
2771 /* do nothing, since nothing else supports MSI-X */
2773 } /* switch (hw->mac.type) */
2775 adapter->eims_enable_mask |= adapter->eims_other;
2777 for (i = 0; i < adapter->num_q_vectors; i++)
2778 igc_assign_vector(adapter->q_vector[i], vector++);
2784 * igc_irq_enable - Enable default interrupt generation settings
2785 * @adapter: board private structure
2787 static void igc_irq_enable(struct igc_adapter *adapter)
2789 struct igc_hw *hw = &adapter->hw;
2791 if (adapter->msix_entries) {
2792 u32 ims = IGC_IMS_LSC | IGC_IMS_DOUTSYNC | IGC_IMS_DRSTA;
2793 u32 regval = rd32(IGC_EIAC);
2795 wr32(IGC_EIAC, regval | adapter->eims_enable_mask);
2796 regval = rd32(IGC_EIAM);
2797 wr32(IGC_EIAM, regval | adapter->eims_enable_mask);
2798 wr32(IGC_EIMS, adapter->eims_enable_mask);
2801 wr32(IGC_IMS, IMS_ENABLE_MASK | IGC_IMS_DRSTA);
2802 wr32(IGC_IAM, IMS_ENABLE_MASK | IGC_IMS_DRSTA);
2807 * igc_irq_disable - Mask off interrupt generation on the NIC
2808 * @adapter: board private structure
2810 static void igc_irq_disable(struct igc_adapter *adapter)
2812 struct igc_hw *hw = &adapter->hw;
2814 if (adapter->msix_entries) {
2815 u32 regval = rd32(IGC_EIAM);
2817 wr32(IGC_EIAM, regval & ~adapter->eims_enable_mask);
2818 wr32(IGC_EIMC, adapter->eims_enable_mask);
2819 regval = rd32(IGC_EIAC);
2820 wr32(IGC_EIAC, regval & ~adapter->eims_enable_mask);
2827 if (adapter->msix_entries) {
2830 synchronize_irq(adapter->msix_entries[vector++].vector);
2832 for (i = 0; i < adapter->num_q_vectors; i++)
2833 synchronize_irq(adapter->msix_entries[vector++].vector);
2835 synchronize_irq(adapter->pdev->irq);
2839 void igc_set_flag_queue_pairs(struct igc_adapter *adapter,
2840 const u32 max_rss_queues)
2842 /* Determine if we need to pair queues. */
2843 /* If rss_queues > half of max_rss_queues, pair the queues in
2844 * order to conserve interrupts due to limited supply.
2846 if (adapter->rss_queues > (max_rss_queues / 2))
2847 adapter->flags |= IGC_FLAG_QUEUE_PAIRS;
2849 adapter->flags &= ~IGC_FLAG_QUEUE_PAIRS;
2852 unsigned int igc_get_max_rss_queues(struct igc_adapter *adapter)
2854 return IGC_MAX_RX_QUEUES;
2857 static void igc_init_queue_configuration(struct igc_adapter *adapter)
2861 max_rss_queues = igc_get_max_rss_queues(adapter);
2862 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2864 igc_set_flag_queue_pairs(adapter, max_rss_queues);
2868 * igc_reset_q_vector - Reset config for interrupt vector
2869 * @adapter: board private structure to initialize
2870 * @v_idx: Index of vector to be reset
2872 * If NAPI is enabled it will delete any references to the
2873 * NAPI struct. This is preparation for igc_free_q_vector.
2875 static void igc_reset_q_vector(struct igc_adapter *adapter, int v_idx)
2877 struct igc_q_vector *q_vector = adapter->q_vector[v_idx];
2879 /* if we're coming from igc_set_interrupt_capability, the vectors are
2885 if (q_vector->tx.ring)
2886 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
2888 if (q_vector->rx.ring)
2889 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL;
2891 netif_napi_del(&q_vector->napi);
2895 * igc_free_q_vector - Free memory allocated for specific interrupt vector
2896 * @adapter: board private structure to initialize
2897 * @v_idx: Index of vector to be freed
2899 * This function frees the memory allocated to the q_vector.
2901 static void igc_free_q_vector(struct igc_adapter *adapter, int v_idx)
2903 struct igc_q_vector *q_vector = adapter->q_vector[v_idx];
2905 adapter->q_vector[v_idx] = NULL;
2907 /* igc_get_stats64() might access the rings on this vector,
2908 * we must wait a grace period before freeing it.
2911 kfree_rcu(q_vector, rcu);
2915 * igc_free_q_vectors - Free memory allocated for interrupt vectors
2916 * @adapter: board private structure to initialize
2918 * This function frees the memory allocated to the q_vectors. In addition if
2919 * NAPI is enabled it will delete any references to the NAPI struct prior
2920 * to freeing the q_vector.
2922 static void igc_free_q_vectors(struct igc_adapter *adapter)
2924 int v_idx = adapter->num_q_vectors;
2926 adapter->num_tx_queues = 0;
2927 adapter->num_rx_queues = 0;
2928 adapter->num_q_vectors = 0;
2931 igc_reset_q_vector(adapter, v_idx);
2932 igc_free_q_vector(adapter, v_idx);
2937 * igc_update_itr - update the dynamic ITR value based on statistics
2938 * @q_vector: pointer to q_vector
2939 * @ring_container: ring info to update the itr for
2941 * Stores a new ITR value based on packets and byte
2942 * counts during the last interrupt. The advantage of per interrupt
2943 * computation is faster updates and more accurate ITR for the current
2944 * traffic pattern. Constants in this function were computed
2945 * based on theoretical maximum wire speed and thresholds were set based
2946 * on testing data as well as attempting to minimize response time
2947 * while increasing bulk throughput.
2948 * NOTE: These calculations are only valid when operating in a single-
2949 * queue environment.
2951 static void igc_update_itr(struct igc_q_vector *q_vector,
2952 struct igc_ring_container *ring_container)
2954 unsigned int packets = ring_container->total_packets;
2955 unsigned int bytes = ring_container->total_bytes;
2956 u8 itrval = ring_container->itr;
2958 /* no packets, exit with status unchanged */
2963 case lowest_latency:
2964 /* handle TSO and jumbo frames */
2965 if (bytes / packets > 8000)
2966 itrval = bulk_latency;
2967 else if ((packets < 5) && (bytes > 512))
2968 itrval = low_latency;
2970 case low_latency: /* 50 usec aka 20000 ints/s */
2971 if (bytes > 10000) {
2972 /* this if handles the TSO accounting */
2973 if (bytes / packets > 8000)
2974 itrval = bulk_latency;
2975 else if ((packets < 10) || ((bytes / packets) > 1200))
2976 itrval = bulk_latency;
2977 else if ((packets > 35))
2978 itrval = lowest_latency;
2979 } else if (bytes / packets > 2000) {
2980 itrval = bulk_latency;
2981 } else if (packets <= 2 && bytes < 512) {
2982 itrval = lowest_latency;
2985 case bulk_latency: /* 250 usec aka 4000 ints/s */
2986 if (bytes > 25000) {
2988 itrval = low_latency;
2989 } else if (bytes < 1500) {
2990 itrval = low_latency;
2995 /* clear work counters since we have the values we need */
2996 ring_container->total_bytes = 0;
2997 ring_container->total_packets = 0;
2999 /* write updated itr to ring container */
3000 ring_container->itr = itrval;
3003 static void igc_set_itr(struct igc_q_vector *q_vector)
3005 struct igc_adapter *adapter = q_vector->adapter;
3006 u32 new_itr = q_vector->itr_val;
3009 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
3010 switch (adapter->link_speed) {
3014 new_itr = IGC_4K_ITR;
3020 igc_update_itr(q_vector, &q_vector->tx);
3021 igc_update_itr(q_vector, &q_vector->rx);
3023 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
3025 /* conservative mode (itr 3) eliminates the lowest_latency setting */
3026 if (current_itr == lowest_latency &&
3027 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
3028 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
3029 current_itr = low_latency;
3031 switch (current_itr) {
3032 /* counts and packets in update_itr are dependent on these numbers */
3033 case lowest_latency:
3034 new_itr = IGC_70K_ITR; /* 70,000 ints/sec */
3037 new_itr = IGC_20K_ITR; /* 20,000 ints/sec */
3040 new_itr = IGC_4K_ITR; /* 4,000 ints/sec */
3047 if (new_itr != q_vector->itr_val) {
3048 /* this attempts to bias the interrupt rate towards Bulk
3049 * by adding intermediate steps when interrupt rate is
3052 new_itr = new_itr > q_vector->itr_val ?
3053 max((new_itr * q_vector->itr_val) /
3054 (new_itr + (q_vector->itr_val >> 2)),
3056 /* Don't write the value here; it resets the adapter's
3057 * internal timer, and causes us to delay far longer than
3058 * we should between interrupts. Instead, we write the ITR
3059 * value at the beginning of the next interrupt so the timing
3060 * ends up being correct.
3062 q_vector->itr_val = new_itr;
3063 q_vector->set_itr = 1;
3067 static void igc_reset_interrupt_capability(struct igc_adapter *adapter)
3069 int v_idx = adapter->num_q_vectors;
3071 if (adapter->msix_entries) {
3072 pci_disable_msix(adapter->pdev);
3073 kfree(adapter->msix_entries);
3074 adapter->msix_entries = NULL;
3075 } else if (adapter->flags & IGC_FLAG_HAS_MSI) {
3076 pci_disable_msi(adapter->pdev);
3080 igc_reset_q_vector(adapter, v_idx);
3084 * igc_set_interrupt_capability - set MSI or MSI-X if supported
3085 * @adapter: Pointer to adapter structure
3086 * @msix: boolean value for MSI-X capability
3088 * Attempt to configure interrupts using the best available
3089 * capabilities of the hardware and kernel.
3091 static void igc_set_interrupt_capability(struct igc_adapter *adapter,
3099 adapter->flags |= IGC_FLAG_HAS_MSIX;
3101 /* Number of supported queues. */
3102 adapter->num_rx_queues = adapter->rss_queues;
3104 adapter->num_tx_queues = adapter->rss_queues;
3106 /* start with one vector for every Rx queue */
3107 numvecs = adapter->num_rx_queues;
3109 /* if Tx handler is separate add 1 for every Tx queue */
3110 if (!(adapter->flags & IGC_FLAG_QUEUE_PAIRS))
3111 numvecs += adapter->num_tx_queues;
3113 /* store the number of vectors reserved for queues */
3114 adapter->num_q_vectors = numvecs;
3116 /* add 1 vector for link status interrupts */
3119 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
3122 if (!adapter->msix_entries)
3125 /* populate entry values */
3126 for (i = 0; i < numvecs; i++)
3127 adapter->msix_entries[i].entry = i;
3129 err = pci_enable_msix_range(adapter->pdev,
3130 adapter->msix_entries,
3136 kfree(adapter->msix_entries);
3137 adapter->msix_entries = NULL;
3139 igc_reset_interrupt_capability(adapter);
3142 adapter->flags &= ~IGC_FLAG_HAS_MSIX;
3144 adapter->rss_queues = 1;
3145 adapter->flags |= IGC_FLAG_QUEUE_PAIRS;
3146 adapter->num_rx_queues = 1;
3147 adapter->num_tx_queues = 1;
3148 adapter->num_q_vectors = 1;
3149 if (!pci_enable_msi(adapter->pdev))
3150 adapter->flags |= IGC_FLAG_HAS_MSI;
3154 * igc_update_ring_itr - update the dynamic ITR value based on packet size
3155 * @q_vector: pointer to q_vector
3157 * Stores a new ITR value based on strictly on packet size. This
3158 * algorithm is less sophisticated than that used in igc_update_itr,
3159 * due to the difficulty of synchronizing statistics across multiple
3160 * receive rings. The divisors and thresholds used by this function
3161 * were determined based on theoretical maximum wire speed and testing
3162 * data, in order to minimize response time while increasing bulk
3164 * NOTE: This function is called only when operating in a multiqueue
3165 * receive environment.
3167 static void igc_update_ring_itr(struct igc_q_vector *q_vector)
3169 struct igc_adapter *adapter = q_vector->adapter;
3170 int new_val = q_vector->itr_val;
3171 int avg_wire_size = 0;
3172 unsigned int packets;
3174 /* For non-gigabit speeds, just fix the interrupt rate at 4000
3175 * ints/sec - ITR timer value of 120 ticks.
3177 switch (adapter->link_speed) {
3180 new_val = IGC_4K_ITR;
3186 packets = q_vector->rx.total_packets;
3188 avg_wire_size = q_vector->rx.total_bytes / packets;
3190 packets = q_vector->tx.total_packets;
3192 avg_wire_size = max_t(u32, avg_wire_size,
3193 q_vector->tx.total_bytes / packets);
3195 /* if avg_wire_size isn't set no work was done */
3199 /* Add 24 bytes to size to account for CRC, preamble, and gap */
3200 avg_wire_size += 24;
3202 /* Don't starve jumbo frames */
3203 avg_wire_size = min(avg_wire_size, 3000);
3205 /* Give a little boost to mid-size frames */
3206 if (avg_wire_size > 300 && avg_wire_size < 1200)
3207 new_val = avg_wire_size / 3;
3209 new_val = avg_wire_size / 2;
3211 /* conservative mode (itr 3) eliminates the lowest_latency setting */
3212 if (new_val < IGC_20K_ITR &&
3213 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
3214 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
3215 new_val = IGC_20K_ITR;
3218 if (new_val != q_vector->itr_val) {
3219 q_vector->itr_val = new_val;
3220 q_vector->set_itr = 1;
3223 q_vector->rx.total_bytes = 0;
3224 q_vector->rx.total_packets = 0;
3225 q_vector->tx.total_bytes = 0;
3226 q_vector->tx.total_packets = 0;
3229 static void igc_ring_irq_enable(struct igc_q_vector *q_vector)
3231 struct igc_adapter *adapter = q_vector->adapter;
3232 struct igc_hw *hw = &adapter->hw;
3234 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
3235 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
3236 if (adapter->num_q_vectors == 1)
3237 igc_set_itr(q_vector);
3239 igc_update_ring_itr(q_vector);
3242 if (!test_bit(__IGC_DOWN, &adapter->state)) {
3243 if (adapter->msix_entries)
3244 wr32(IGC_EIMS, q_vector->eims_value);
3246 igc_irq_enable(adapter);
3250 static void igc_add_ring(struct igc_ring *ring,
3251 struct igc_ring_container *head)
3258 * igc_cache_ring_register - Descriptor ring to register mapping
3259 * @adapter: board private structure to initialize
3261 * Once we know the feature-set enabled for the device, we'll cache
3262 * the register offset the descriptor ring is assigned to.
3264 static void igc_cache_ring_register(struct igc_adapter *adapter)
3268 switch (adapter->hw.mac.type) {
3271 for (; i < adapter->num_rx_queues; i++)
3272 adapter->rx_ring[i]->reg_idx = i;
3273 for (; j < adapter->num_tx_queues; j++)
3274 adapter->tx_ring[j]->reg_idx = j;
3280 * igc_poll - NAPI Rx polling callback
3281 * @napi: napi polling structure
3282 * @budget: count of how many packets we should handle
3284 static int igc_poll(struct napi_struct *napi, int budget)
3286 struct igc_q_vector *q_vector = container_of(napi,
3287 struct igc_q_vector,
3289 bool clean_complete = true;
3292 if (q_vector->tx.ring)
3293 clean_complete = igc_clean_tx_irq(q_vector, budget);
3295 if (q_vector->rx.ring) {
3296 int cleaned = igc_clean_rx_irq(q_vector, budget);
3298 work_done += cleaned;
3299 if (cleaned >= budget)
3300 clean_complete = false;
3303 /* If all work not completed, return budget and keep polling */
3304 if (!clean_complete)
3307 /* Exit the polling mode, but don't re-enable interrupts if stack might
3308 * poll us due to busy-polling
3310 if (likely(napi_complete_done(napi, work_done)))
3311 igc_ring_irq_enable(q_vector);
3313 return min(work_done, budget - 1);
3317 * igc_alloc_q_vector - Allocate memory for a single interrupt vector
3318 * @adapter: board private structure to initialize
3319 * @v_count: q_vectors allocated on adapter, used for ring interleaving
3320 * @v_idx: index of vector in adapter struct
3321 * @txr_count: total number of Tx rings to allocate
3322 * @txr_idx: index of first Tx ring to allocate
3323 * @rxr_count: total number of Rx rings to allocate
3324 * @rxr_idx: index of first Rx ring to allocate
3326 * We allocate one q_vector. If allocation fails we return -ENOMEM.
3328 static int igc_alloc_q_vector(struct igc_adapter *adapter,
3329 unsigned int v_count, unsigned int v_idx,
3330 unsigned int txr_count, unsigned int txr_idx,
3331 unsigned int rxr_count, unsigned int rxr_idx)
3333 struct igc_q_vector *q_vector;
3334 struct igc_ring *ring;
3337 /* igc only supports 1 Tx and/or 1 Rx queue per vector */
3338 if (txr_count > 1 || rxr_count > 1)
3341 ring_count = txr_count + rxr_count;
3343 /* allocate q_vector and rings */
3344 q_vector = adapter->q_vector[v_idx];
3346 q_vector = kzalloc(struct_size(q_vector, ring, ring_count),
3349 memset(q_vector, 0, struct_size(q_vector, ring, ring_count));
3353 /* initialize NAPI */
3354 netif_napi_add(adapter->netdev, &q_vector->napi,
3357 /* tie q_vector and adapter together */
3358 adapter->q_vector[v_idx] = q_vector;
3359 q_vector->adapter = adapter;
3361 /* initialize work limits */
3362 q_vector->tx.work_limit = adapter->tx_work_limit;
3364 /* initialize ITR configuration */
3365 q_vector->itr_register = adapter->io_addr + IGC_EITR(0);
3366 q_vector->itr_val = IGC_START_ITR;
3368 /* initialize pointer to rings */
3369 ring = q_vector->ring;
3371 /* initialize ITR */
3373 /* rx or rx/tx vector */
3374 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
3375 q_vector->itr_val = adapter->rx_itr_setting;
3377 /* tx only vector */
3378 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
3379 q_vector->itr_val = adapter->tx_itr_setting;
3383 /* assign generic ring traits */
3384 ring->dev = &adapter->pdev->dev;
3385 ring->netdev = adapter->netdev;
3387 /* configure backlink on ring */
3388 ring->q_vector = q_vector;
3390 /* update q_vector Tx values */
3391 igc_add_ring(ring, &q_vector->tx);
3393 /* apply Tx specific ring traits */
3394 ring->count = adapter->tx_ring_count;
3395 ring->queue_index = txr_idx;
3397 /* assign ring to adapter */
3398 adapter->tx_ring[txr_idx] = ring;
3400 /* push pointer to next ring */
3405 /* assign generic ring traits */
3406 ring->dev = &adapter->pdev->dev;
3407 ring->netdev = adapter->netdev;
3409 /* configure backlink on ring */
3410 ring->q_vector = q_vector;
3412 /* update q_vector Rx values */
3413 igc_add_ring(ring, &q_vector->rx);
3415 /* apply Rx specific ring traits */
3416 ring->count = adapter->rx_ring_count;
3417 ring->queue_index = rxr_idx;
3419 /* assign ring to adapter */
3420 adapter->rx_ring[rxr_idx] = ring;
3427 * igc_alloc_q_vectors - Allocate memory for interrupt vectors
3428 * @adapter: board private structure to initialize
3430 * We allocate one q_vector per queue interrupt. If allocation fails we
3433 static int igc_alloc_q_vectors(struct igc_adapter *adapter)
3435 int rxr_remaining = adapter->num_rx_queues;
3436 int txr_remaining = adapter->num_tx_queues;
3437 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
3438 int q_vectors = adapter->num_q_vectors;
3441 if (q_vectors >= (rxr_remaining + txr_remaining)) {
3442 for (; rxr_remaining; v_idx++) {
3443 err = igc_alloc_q_vector(adapter, q_vectors, v_idx,
3449 /* update counts and index */
3455 for (; v_idx < q_vectors; v_idx++) {
3456 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
3457 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
3459 err = igc_alloc_q_vector(adapter, q_vectors, v_idx,
3460 tqpv, txr_idx, rqpv, rxr_idx);
3465 /* update counts and index */
3466 rxr_remaining -= rqpv;
3467 txr_remaining -= tqpv;
3475 adapter->num_tx_queues = 0;
3476 adapter->num_rx_queues = 0;
3477 adapter->num_q_vectors = 0;
3480 igc_free_q_vector(adapter, v_idx);
3486 * igc_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
3487 * @adapter: Pointer to adapter structure
3488 * @msix: boolean for MSI-X capability
3490 * This function initializes the interrupts and allocates all of the queues.
3492 static int igc_init_interrupt_scheme(struct igc_adapter *adapter, bool msix)
3494 struct net_device *dev = adapter->netdev;
3497 igc_set_interrupt_capability(adapter, msix);
3499 err = igc_alloc_q_vectors(adapter);
3501 netdev_err(dev, "Unable to allocate memory for vectors\n");
3502 goto err_alloc_q_vectors;
3505 igc_cache_ring_register(adapter);
3509 err_alloc_q_vectors:
3510 igc_reset_interrupt_capability(adapter);
3515 * igc_sw_init - Initialize general software structures (struct igc_adapter)
3516 * @adapter: board private structure to initialize
3518 * igc_sw_init initializes the Adapter private data structure.
3519 * Fields are initialized based on PCI device information and
3520 * OS network device settings (MTU size).
3522 static int igc_sw_init(struct igc_adapter *adapter)
3524 struct net_device *netdev = adapter->netdev;
3525 struct pci_dev *pdev = adapter->pdev;
3526 struct igc_hw *hw = &adapter->hw;
3528 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
3530 /* set default ring sizes */
3531 adapter->tx_ring_count = IGC_DEFAULT_TXD;
3532 adapter->rx_ring_count = IGC_DEFAULT_RXD;
3534 /* set default ITR values */
3535 adapter->rx_itr_setting = IGC_DEFAULT_ITR;
3536 adapter->tx_itr_setting = IGC_DEFAULT_ITR;
3538 /* set default work limits */
3539 adapter->tx_work_limit = IGC_DEFAULT_TX_WORK;
3541 /* adjust max frame to be at least the size of a standard frame */
3542 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
3544 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
3546 mutex_init(&adapter->nfc_rule_lock);
3547 INIT_LIST_HEAD(&adapter->nfc_rule_list);
3548 adapter->nfc_rule_count = 0;
3550 spin_lock_init(&adapter->stats64_lock);
3551 /* Assume MSI-X interrupts, will be checked during IRQ allocation */
3552 adapter->flags |= IGC_FLAG_HAS_MSIX;
3554 igc_init_queue_configuration(adapter);
3556 /* This call may decrease the number of queues */
3557 if (igc_init_interrupt_scheme(adapter, true)) {
3558 netdev_err(netdev, "Unable to allocate memory for queues\n");
3562 /* Explicitly disable IRQ since the NIC can be in any state. */
3563 igc_irq_disable(adapter);
3565 set_bit(__IGC_DOWN, &adapter->state);
3571 * igc_up - Open the interface and prepare it to handle traffic
3572 * @adapter: board private structure
3574 void igc_up(struct igc_adapter *adapter)
3576 struct igc_hw *hw = &adapter->hw;
3579 /* hardware has been reset, we need to reload some things */
3580 igc_configure(adapter);
3582 clear_bit(__IGC_DOWN, &adapter->state);
3584 for (i = 0; i < adapter->num_q_vectors; i++)
3585 napi_enable(&adapter->q_vector[i]->napi);
3587 if (adapter->msix_entries)
3588 igc_configure_msix(adapter);
3590 igc_assign_vector(adapter->q_vector[0], 0);
3592 /* Clear any pending interrupts. */
3594 igc_irq_enable(adapter);
3596 netif_tx_start_all_queues(adapter->netdev);
3598 /* start the watchdog. */
3599 hw->mac.get_link_status = 1;
3600 schedule_work(&adapter->watchdog_task);
3604 * igc_update_stats - Update the board statistics counters
3605 * @adapter: board private structure
3607 void igc_update_stats(struct igc_adapter *adapter)
3609 struct rtnl_link_stats64 *net_stats = &adapter->stats64;
3610 struct pci_dev *pdev = adapter->pdev;
3611 struct igc_hw *hw = &adapter->hw;
3612 u64 _bytes, _packets;
3618 /* Prevent stats update while adapter is being reset, or if the pci
3619 * connection is down.
3621 if (adapter->link_speed == 0)
3623 if (pci_channel_offline(pdev))
3630 for (i = 0; i < adapter->num_rx_queues; i++) {
3631 struct igc_ring *ring = adapter->rx_ring[i];
3632 u32 rqdpc = rd32(IGC_RQDPC(i));
3634 if (hw->mac.type >= igc_i225)
3635 wr32(IGC_RQDPC(i), 0);
3638 ring->rx_stats.drops += rqdpc;
3639 net_stats->rx_fifo_errors += rqdpc;
3643 start = u64_stats_fetch_begin_irq(&ring->rx_syncp);
3644 _bytes = ring->rx_stats.bytes;
3645 _packets = ring->rx_stats.packets;
3646 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start));
3648 packets += _packets;
3651 net_stats->rx_bytes = bytes;
3652 net_stats->rx_packets = packets;
3656 for (i = 0; i < adapter->num_tx_queues; i++) {
3657 struct igc_ring *ring = adapter->tx_ring[i];
3660 start = u64_stats_fetch_begin_irq(&ring->tx_syncp);
3661 _bytes = ring->tx_stats.bytes;
3662 _packets = ring->tx_stats.packets;
3663 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start));
3665 packets += _packets;
3667 net_stats->tx_bytes = bytes;
3668 net_stats->tx_packets = packets;
3671 /* read stats registers */
3672 adapter->stats.crcerrs += rd32(IGC_CRCERRS);
3673 adapter->stats.gprc += rd32(IGC_GPRC);
3674 adapter->stats.gorc += rd32(IGC_GORCL);
3675 rd32(IGC_GORCH); /* clear GORCL */
3676 adapter->stats.bprc += rd32(IGC_BPRC);
3677 adapter->stats.mprc += rd32(IGC_MPRC);
3678 adapter->stats.roc += rd32(IGC_ROC);
3680 adapter->stats.prc64 += rd32(IGC_PRC64);
3681 adapter->stats.prc127 += rd32(IGC_PRC127);
3682 adapter->stats.prc255 += rd32(IGC_PRC255);
3683 adapter->stats.prc511 += rd32(IGC_PRC511);
3684 adapter->stats.prc1023 += rd32(IGC_PRC1023);
3685 adapter->stats.prc1522 += rd32(IGC_PRC1522);
3686 adapter->stats.tlpic += rd32(IGC_TLPIC);
3687 adapter->stats.rlpic += rd32(IGC_RLPIC);
3689 mpc = rd32(IGC_MPC);
3690 adapter->stats.mpc += mpc;
3691 net_stats->rx_fifo_errors += mpc;
3692 adapter->stats.scc += rd32(IGC_SCC);
3693 adapter->stats.ecol += rd32(IGC_ECOL);
3694 adapter->stats.mcc += rd32(IGC_MCC);
3695 adapter->stats.latecol += rd32(IGC_LATECOL);
3696 adapter->stats.dc += rd32(IGC_DC);
3697 adapter->stats.rlec += rd32(IGC_RLEC);
3698 adapter->stats.xonrxc += rd32(IGC_XONRXC);
3699 adapter->stats.xontxc += rd32(IGC_XONTXC);
3700 adapter->stats.xoffrxc += rd32(IGC_XOFFRXC);
3701 adapter->stats.xofftxc += rd32(IGC_XOFFTXC);
3702 adapter->stats.fcruc += rd32(IGC_FCRUC);
3703 adapter->stats.gptc += rd32(IGC_GPTC);
3704 adapter->stats.gotc += rd32(IGC_GOTCL);
3705 rd32(IGC_GOTCH); /* clear GOTCL */
3706 adapter->stats.rnbc += rd32(IGC_RNBC);
3707 adapter->stats.ruc += rd32(IGC_RUC);
3708 adapter->stats.rfc += rd32(IGC_RFC);
3709 adapter->stats.rjc += rd32(IGC_RJC);
3710 adapter->stats.tor += rd32(IGC_TORH);
3711 adapter->stats.tot += rd32(IGC_TOTH);
3712 adapter->stats.tpr += rd32(IGC_TPR);
3714 adapter->stats.ptc64 += rd32(IGC_PTC64);
3715 adapter->stats.ptc127 += rd32(IGC_PTC127);
3716 adapter->stats.ptc255 += rd32(IGC_PTC255);
3717 adapter->stats.ptc511 += rd32(IGC_PTC511);
3718 adapter->stats.ptc1023 += rd32(IGC_PTC1023);
3719 adapter->stats.ptc1522 += rd32(IGC_PTC1522);
3721 adapter->stats.mptc += rd32(IGC_MPTC);
3722 adapter->stats.bptc += rd32(IGC_BPTC);
3724 adapter->stats.tpt += rd32(IGC_TPT);
3725 adapter->stats.colc += rd32(IGC_COLC);
3726 adapter->stats.colc += rd32(IGC_RERC);
3728 adapter->stats.algnerrc += rd32(IGC_ALGNERRC);
3730 adapter->stats.tsctc += rd32(IGC_TSCTC);
3732 adapter->stats.iac += rd32(IGC_IAC);
3734 /* Fill out the OS statistics structure */
3735 net_stats->multicast = adapter->stats.mprc;
3736 net_stats->collisions = adapter->stats.colc;
3740 /* RLEC on some newer hardware can be incorrect so build
3741 * our own version based on RUC and ROC
3743 net_stats->rx_errors = adapter->stats.rxerrc +
3744 adapter->stats.crcerrs + adapter->stats.algnerrc +
3745 adapter->stats.ruc + adapter->stats.roc +
3746 adapter->stats.cexterr;
3747 net_stats->rx_length_errors = adapter->stats.ruc +
3749 net_stats->rx_crc_errors = adapter->stats.crcerrs;
3750 net_stats->rx_frame_errors = adapter->stats.algnerrc;
3751 net_stats->rx_missed_errors = adapter->stats.mpc;
3754 net_stats->tx_errors = adapter->stats.ecol +
3755 adapter->stats.latecol;
3756 net_stats->tx_aborted_errors = adapter->stats.ecol;
3757 net_stats->tx_window_errors = adapter->stats.latecol;
3758 net_stats->tx_carrier_errors = adapter->stats.tncrs;
3760 /* Tx Dropped needs to be maintained elsewhere */
3762 /* Management Stats */
3763 adapter->stats.mgptc += rd32(IGC_MGTPTC);
3764 adapter->stats.mgprc += rd32(IGC_MGTPRC);
3765 adapter->stats.mgpdc += rd32(IGC_MGTPDC);
3769 * igc_down - Close the interface
3770 * @adapter: board private structure
3772 void igc_down(struct igc_adapter *adapter)
3774 struct net_device *netdev = adapter->netdev;
3775 struct igc_hw *hw = &adapter->hw;
3779 set_bit(__IGC_DOWN, &adapter->state);
3781 igc_ptp_suspend(adapter);
3783 /* disable receives in the hardware */
3784 rctl = rd32(IGC_RCTL);
3785 wr32(IGC_RCTL, rctl & ~IGC_RCTL_EN);
3786 /* flush and sleep below */
3788 /* set trans_start so we don't get spurious watchdogs during reset */
3789 netif_trans_update(netdev);
3791 netif_carrier_off(netdev);
3792 netif_tx_stop_all_queues(netdev);
3794 /* disable transmits in the hardware */
3795 tctl = rd32(IGC_TCTL);
3796 tctl &= ~IGC_TCTL_EN;
3797 wr32(IGC_TCTL, tctl);
3798 /* flush both disables and wait for them to finish */
3800 usleep_range(10000, 20000);
3802 igc_irq_disable(adapter);
3804 adapter->flags &= ~IGC_FLAG_NEED_LINK_UPDATE;
3806 for (i = 0; i < adapter->num_q_vectors; i++) {
3807 if (adapter->q_vector[i]) {
3808 napi_synchronize(&adapter->q_vector[i]->napi);
3809 napi_disable(&adapter->q_vector[i]->napi);
3813 del_timer_sync(&adapter->watchdog_timer);
3814 del_timer_sync(&adapter->phy_info_timer);
3816 /* record the stats before reset*/
3817 spin_lock(&adapter->stats64_lock);
3818 igc_update_stats(adapter);
3819 spin_unlock(&adapter->stats64_lock);
3821 adapter->link_speed = 0;
3822 adapter->link_duplex = 0;
3824 if (!pci_channel_offline(adapter->pdev))
3827 /* clear VLAN promisc flag so VFTA will be updated if necessary */
3828 adapter->flags &= ~IGC_FLAG_VLAN_PROMISC;
3830 igc_clean_all_tx_rings(adapter);
3831 igc_clean_all_rx_rings(adapter);
3834 void igc_reinit_locked(struct igc_adapter *adapter)
3836 while (test_and_set_bit(__IGC_RESETTING, &adapter->state))
3837 usleep_range(1000, 2000);
3840 clear_bit(__IGC_RESETTING, &adapter->state);
3843 static void igc_reset_task(struct work_struct *work)
3845 struct igc_adapter *adapter;
3847 adapter = container_of(work, struct igc_adapter, reset_task);
3849 igc_rings_dump(adapter);
3850 igc_regs_dump(adapter);
3851 netdev_err(adapter->netdev, "Reset adapter\n");
3852 igc_reinit_locked(adapter);
3856 * igc_change_mtu - Change the Maximum Transfer Unit
3857 * @netdev: network interface device structure
3858 * @new_mtu: new value for maximum frame size
3860 * Returns 0 on success, negative on failure
3862 static int igc_change_mtu(struct net_device *netdev, int new_mtu)
3864 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
3865 struct igc_adapter *adapter = netdev_priv(netdev);
3867 /* adjust max frame to be at least the size of a standard frame */
3868 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3869 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
3871 while (test_and_set_bit(__IGC_RESETTING, &adapter->state))
3872 usleep_range(1000, 2000);
3874 /* igc_down has a dependency on max_frame_size */
3875 adapter->max_frame_size = max_frame;
3877 if (netif_running(netdev))
3880 netdev_dbg(netdev, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
3881 netdev->mtu = new_mtu;
3883 if (netif_running(netdev))
3888 clear_bit(__IGC_RESETTING, &adapter->state);
3894 * igc_get_stats - Get System Network Statistics
3895 * @netdev: network interface device structure
3897 * Returns the address of the device statistics structure.
3898 * The statistics are updated here and also from the timer callback.
3900 static struct net_device_stats *igc_get_stats(struct net_device *netdev)
3902 struct igc_adapter *adapter = netdev_priv(netdev);
3904 if (!test_bit(__IGC_RESETTING, &adapter->state))
3905 igc_update_stats(adapter);
3907 /* only return the current stats */
3908 return &netdev->stats;
3911 static netdev_features_t igc_fix_features(struct net_device *netdev,
3912 netdev_features_t features)
3914 /* Since there is no support for separate Rx/Tx vlan accel
3915 * enable/disable make sure Tx flag is always in same state as Rx.
3917 if (features & NETIF_F_HW_VLAN_CTAG_RX)
3918 features |= NETIF_F_HW_VLAN_CTAG_TX;
3920 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
3925 static int igc_set_features(struct net_device *netdev,
3926 netdev_features_t features)
3928 netdev_features_t changed = netdev->features ^ features;
3929 struct igc_adapter *adapter = netdev_priv(netdev);
3931 /* Add VLAN support */
3932 if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE)))
3935 if (!(features & NETIF_F_NTUPLE))
3936 igc_flush_nfc_rules(adapter);
3938 netdev->features = features;
3940 if (netif_running(netdev))
3941 igc_reinit_locked(adapter);
3948 static netdev_features_t
3949 igc_features_check(struct sk_buff *skb, struct net_device *dev,
3950 netdev_features_t features)
3952 unsigned int network_hdr_len, mac_hdr_len;
3954 /* Make certain the headers can be described by a context descriptor */
3955 mac_hdr_len = skb_network_header(skb) - skb->data;
3956 if (unlikely(mac_hdr_len > IGC_MAX_MAC_HDR_LEN))
3957 return features & ~(NETIF_F_HW_CSUM |
3959 NETIF_F_HW_VLAN_CTAG_TX |
3963 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb);
3964 if (unlikely(network_hdr_len > IGC_MAX_NETWORK_HDR_LEN))
3965 return features & ~(NETIF_F_HW_CSUM |
3970 /* We can only support IPv4 TSO in tunnels if we can mangle the
3971 * inner IP ID field, so strip TSO if MANGLEID is not supported.
3973 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID))
3974 features &= ~NETIF_F_TSO;
3979 static void igc_tsync_interrupt(struct igc_adapter *adapter)
3981 struct igc_hw *hw = &adapter->hw;
3982 u32 tsicr = rd32(IGC_TSICR);
3985 if (tsicr & IGC_TSICR_TXTS) {
3986 /* retrieve hardware timestamp */
3987 schedule_work(&adapter->ptp_tx_work);
3988 ack |= IGC_TSICR_TXTS;
3991 /* acknowledge the interrupts */
3992 wr32(IGC_TSICR, ack);
3996 * igc_msix_other - msix other interrupt handler
3997 * @irq: interrupt number
3998 * @data: pointer to a q_vector
4000 static irqreturn_t igc_msix_other(int irq, void *data)
4002 struct igc_adapter *adapter = data;
4003 struct igc_hw *hw = &adapter->hw;
4004 u32 icr = rd32(IGC_ICR);
4006 /* reading ICR causes bit 31 of EICR to be cleared */
4007 if (icr & IGC_ICR_DRSTA)
4008 schedule_work(&adapter->reset_task);
4010 if (icr & IGC_ICR_DOUTSYNC) {
4011 /* HW is reporting DMA is out of sync */
4012 adapter->stats.doosync++;
4015 if (icr & IGC_ICR_LSC) {
4016 hw->mac.get_link_status = 1;
4017 /* guard against interrupt when we're going down */
4018 if (!test_bit(__IGC_DOWN, &adapter->state))
4019 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4022 if (icr & IGC_ICR_TS)
4023 igc_tsync_interrupt(adapter);
4025 wr32(IGC_EIMS, adapter->eims_other);
4030 static void igc_write_itr(struct igc_q_vector *q_vector)
4032 u32 itr_val = q_vector->itr_val & IGC_QVECTOR_MASK;
4034 if (!q_vector->set_itr)
4038 itr_val = IGC_ITR_VAL_MASK;
4040 itr_val |= IGC_EITR_CNT_IGNR;
4042 writel(itr_val, q_vector->itr_register);
4043 q_vector->set_itr = 0;
4046 static irqreturn_t igc_msix_ring(int irq, void *data)
4048 struct igc_q_vector *q_vector = data;
4050 /* Write the ITR value calculated from the previous interrupt. */
4051 igc_write_itr(q_vector);
4053 napi_schedule(&q_vector->napi);
4059 * igc_request_msix - Initialize MSI-X interrupts
4060 * @adapter: Pointer to adapter structure
4062 * igc_request_msix allocates MSI-X vectors and requests interrupts from the
4065 static int igc_request_msix(struct igc_adapter *adapter)
4067 int i = 0, err = 0, vector = 0, free_vector = 0;
4068 struct net_device *netdev = adapter->netdev;
4070 err = request_irq(adapter->msix_entries[vector].vector,
4071 &igc_msix_other, 0, netdev->name, adapter);
4075 for (i = 0; i < adapter->num_q_vectors; i++) {
4076 struct igc_q_vector *q_vector = adapter->q_vector[i];
4080 q_vector->itr_register = adapter->io_addr + IGC_EITR(vector);
4082 if (q_vector->rx.ring && q_vector->tx.ring)
4083 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
4084 q_vector->rx.ring->queue_index);
4085 else if (q_vector->tx.ring)
4086 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
4087 q_vector->tx.ring->queue_index);
4088 else if (q_vector->rx.ring)
4089 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
4090 q_vector->rx.ring->queue_index);
4092 sprintf(q_vector->name, "%s-unused", netdev->name);
4094 err = request_irq(adapter->msix_entries[vector].vector,
4095 igc_msix_ring, 0, q_vector->name,
4101 igc_configure_msix(adapter);
4105 /* free already assigned IRQs */
4106 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
4109 for (i = 0; i < vector; i++) {
4110 free_irq(adapter->msix_entries[free_vector++].vector,
4111 adapter->q_vector[i]);
4118 * igc_clear_interrupt_scheme - reset the device to a state of no interrupts
4119 * @adapter: Pointer to adapter structure
4121 * This function resets the device so that it has 0 rx queues, tx queues, and
4122 * MSI-X interrupts allocated.
4124 static void igc_clear_interrupt_scheme(struct igc_adapter *adapter)
4126 igc_free_q_vectors(adapter);
4127 igc_reset_interrupt_capability(adapter);
4130 /* Need to wait a few seconds after link up to get diagnostic information from
4133 static void igc_update_phy_info(struct timer_list *t)
4135 struct igc_adapter *adapter = from_timer(adapter, t, phy_info_timer);
4137 igc_get_phy_info(&adapter->hw);
4141 * igc_has_link - check shared code for link and determine up/down
4142 * @adapter: pointer to driver private info
4144 bool igc_has_link(struct igc_adapter *adapter)
4146 struct igc_hw *hw = &adapter->hw;
4147 bool link_active = false;
4149 /* get_link_status is set on LSC (link status) interrupt or
4150 * rx sequence error interrupt. get_link_status will stay
4151 * false until the igc_check_for_link establishes link
4152 * for copper adapters ONLY
4154 switch (hw->phy.media_type) {
4155 case igc_media_type_copper:
4156 if (!hw->mac.get_link_status)
4158 hw->mac.ops.check_for_link(hw);
4159 link_active = !hw->mac.get_link_status;
4162 case igc_media_type_unknown:
4166 if (hw->mac.type == igc_i225 &&
4167 hw->phy.id == I225_I_PHY_ID) {
4168 if (!netif_carrier_ok(adapter->netdev)) {
4169 adapter->flags &= ~IGC_FLAG_NEED_LINK_UPDATE;
4170 } else if (!(adapter->flags & IGC_FLAG_NEED_LINK_UPDATE)) {
4171 adapter->flags |= IGC_FLAG_NEED_LINK_UPDATE;
4172 adapter->link_check_timeout = jiffies;
4180 * igc_watchdog - Timer Call-back
4181 * @t: timer for the watchdog
4183 static void igc_watchdog(struct timer_list *t)
4185 struct igc_adapter *adapter = from_timer(adapter, t, watchdog_timer);
4186 /* Do the rest outside of interrupt context */
4187 schedule_work(&adapter->watchdog_task);
4190 static void igc_watchdog_task(struct work_struct *work)
4192 struct igc_adapter *adapter = container_of(work,
4195 struct net_device *netdev = adapter->netdev;
4196 struct igc_hw *hw = &adapter->hw;
4197 struct igc_phy_info *phy = &hw->phy;
4198 u16 phy_data, retry_count = 20;
4202 link = igc_has_link(adapter);
4204 if (adapter->flags & IGC_FLAG_NEED_LINK_UPDATE) {
4205 if (time_after(jiffies, (adapter->link_check_timeout + HZ)))
4206 adapter->flags &= ~IGC_FLAG_NEED_LINK_UPDATE;
4212 /* Cancel scheduled suspend requests. */
4213 pm_runtime_resume(netdev->dev.parent);
4215 if (!netif_carrier_ok(netdev)) {
4218 hw->mac.ops.get_speed_and_duplex(hw,
4219 &adapter->link_speed,
4220 &adapter->link_duplex);
4222 ctrl = rd32(IGC_CTRL);
4223 /* Link status message must follow this format */
4225 "NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
4226 adapter->link_speed,
4227 adapter->link_duplex == FULL_DUPLEX ?
4229 (ctrl & IGC_CTRL_TFCE) &&
4230 (ctrl & IGC_CTRL_RFCE) ? "RX/TX" :
4231 (ctrl & IGC_CTRL_RFCE) ? "RX" :
4232 (ctrl & IGC_CTRL_TFCE) ? "TX" : "None");
4234 /* disable EEE if enabled */
4235 if ((adapter->flags & IGC_FLAG_EEE) &&
4236 adapter->link_duplex == HALF_DUPLEX) {
4238 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex\n");
4239 adapter->hw.dev_spec._base.eee_enable = false;
4240 adapter->flags &= ~IGC_FLAG_EEE;
4243 /* check if SmartSpeed worked */
4244 igc_check_downshift(hw);
4245 if (phy->speed_downgraded)
4246 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
4248 /* adjust timeout factor according to speed/duplex */
4249 adapter->tx_timeout_factor = 1;
4250 switch (adapter->link_speed) {
4252 adapter->tx_timeout_factor = 14;
4255 /* maybe add some timeout factor ? */
4259 if (adapter->link_speed != SPEED_1000)
4262 /* wait for Remote receiver status OK */
4264 if (!igc_read_phy_reg(hw, PHY_1000T_STATUS,
4266 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) &&
4270 goto retry_read_status;
4271 } else if (!retry_count) {
4272 netdev_err(netdev, "exceed max 2 second\n");
4275 netdev_err(netdev, "read 1000Base-T Status Reg\n");
4278 netif_carrier_on(netdev);
4280 /* link state has changed, schedule phy info update */
4281 if (!test_bit(__IGC_DOWN, &adapter->state))
4282 mod_timer(&adapter->phy_info_timer,
4283 round_jiffies(jiffies + 2 * HZ));
4286 if (netif_carrier_ok(netdev)) {
4287 adapter->link_speed = 0;
4288 adapter->link_duplex = 0;
4290 /* Links status message must follow this format */
4291 netdev_info(netdev, "NIC Link is Down\n");
4292 netif_carrier_off(netdev);
4294 /* link state has changed, schedule phy info update */
4295 if (!test_bit(__IGC_DOWN, &adapter->state))
4296 mod_timer(&adapter->phy_info_timer,
4297 round_jiffies(jiffies + 2 * HZ));
4299 /* link is down, time to check for alternate media */
4300 if (adapter->flags & IGC_FLAG_MAS_ENABLE) {
4301 if (adapter->flags & IGC_FLAG_MEDIA_RESET) {
4302 schedule_work(&adapter->reset_task);
4303 /* return immediately */
4307 pm_schedule_suspend(netdev->dev.parent,
4310 /* also check for alternate media here */
4311 } else if (!netif_carrier_ok(netdev) &&
4312 (adapter->flags & IGC_FLAG_MAS_ENABLE)) {
4313 if (adapter->flags & IGC_FLAG_MEDIA_RESET) {
4314 schedule_work(&adapter->reset_task);
4315 /* return immediately */
4321 spin_lock(&adapter->stats64_lock);
4322 igc_update_stats(adapter);
4323 spin_unlock(&adapter->stats64_lock);
4325 for (i = 0; i < adapter->num_tx_queues; i++) {
4326 struct igc_ring *tx_ring = adapter->tx_ring[i];
4328 if (!netif_carrier_ok(netdev)) {
4329 /* We've lost link, so the controller stops DMA,
4330 * but we've got queued Tx work that's never going
4331 * to get done, so reset controller to flush Tx.
4332 * (Do the reset outside of interrupt context).
4334 if (igc_desc_unused(tx_ring) + 1 < tx_ring->count) {
4335 adapter->tx_timeout_count++;
4336 schedule_work(&adapter->reset_task);
4337 /* return immediately since reset is imminent */
4342 /* Force detection of hung controller every watchdog period */
4343 set_bit(IGC_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
4346 /* Cause software interrupt to ensure Rx ring is cleaned */
4347 if (adapter->flags & IGC_FLAG_HAS_MSIX) {
4350 for (i = 0; i < adapter->num_q_vectors; i++)
4351 eics |= adapter->q_vector[i]->eims_value;
4352 wr32(IGC_EICS, eics);
4354 wr32(IGC_ICS, IGC_ICS_RXDMT0);
4357 igc_ptp_tx_hang(adapter);
4359 /* Reset the timer */
4360 if (!test_bit(__IGC_DOWN, &adapter->state)) {
4361 if (adapter->flags & IGC_FLAG_NEED_LINK_UPDATE)
4362 mod_timer(&adapter->watchdog_timer,
4363 round_jiffies(jiffies + HZ));
4365 mod_timer(&adapter->watchdog_timer,
4366 round_jiffies(jiffies + 2 * HZ));
4371 * igc_intr_msi - Interrupt Handler
4372 * @irq: interrupt number
4373 * @data: pointer to a network interface device structure
4375 static irqreturn_t igc_intr_msi(int irq, void *data)
4377 struct igc_adapter *adapter = data;
4378 struct igc_q_vector *q_vector = adapter->q_vector[0];
4379 struct igc_hw *hw = &adapter->hw;
4380 /* read ICR disables interrupts using IAM */
4381 u32 icr = rd32(IGC_ICR);
4383 igc_write_itr(q_vector);
4385 if (icr & IGC_ICR_DRSTA)
4386 schedule_work(&adapter->reset_task);
4388 if (icr & IGC_ICR_DOUTSYNC) {
4389 /* HW is reporting DMA is out of sync */
4390 adapter->stats.doosync++;
4393 if (icr & (IGC_ICR_RXSEQ | IGC_ICR_LSC)) {
4394 hw->mac.get_link_status = 1;
4395 if (!test_bit(__IGC_DOWN, &adapter->state))
4396 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4399 napi_schedule(&q_vector->napi);
4405 * igc_intr - Legacy Interrupt Handler
4406 * @irq: interrupt number
4407 * @data: pointer to a network interface device structure
4409 static irqreturn_t igc_intr(int irq, void *data)
4411 struct igc_adapter *adapter = data;
4412 struct igc_q_vector *q_vector = adapter->q_vector[0];
4413 struct igc_hw *hw = &adapter->hw;
4414 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
4415 * need for the IMC write
4417 u32 icr = rd32(IGC_ICR);
4419 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
4420 * not set, then the adapter didn't send an interrupt
4422 if (!(icr & IGC_ICR_INT_ASSERTED))
4425 igc_write_itr(q_vector);
4427 if (icr & IGC_ICR_DRSTA)
4428 schedule_work(&adapter->reset_task);
4430 if (icr & IGC_ICR_DOUTSYNC) {
4431 /* HW is reporting DMA is out of sync */
4432 adapter->stats.doosync++;
4435 if (icr & (IGC_ICR_RXSEQ | IGC_ICR_LSC)) {
4436 hw->mac.get_link_status = 1;
4437 /* guard against interrupt when we're going down */
4438 if (!test_bit(__IGC_DOWN, &adapter->state))
4439 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4442 napi_schedule(&q_vector->napi);
4447 static void igc_free_irq(struct igc_adapter *adapter)
4449 if (adapter->msix_entries) {
4452 free_irq(adapter->msix_entries[vector++].vector, adapter);
4454 for (i = 0; i < adapter->num_q_vectors; i++)
4455 free_irq(adapter->msix_entries[vector++].vector,
4456 adapter->q_vector[i]);
4458 free_irq(adapter->pdev->irq, adapter);
4463 * igc_request_irq - initialize interrupts
4464 * @adapter: Pointer to adapter structure
4466 * Attempts to configure interrupts using the best available
4467 * capabilities of the hardware and kernel.
4469 static int igc_request_irq(struct igc_adapter *adapter)
4471 struct net_device *netdev = adapter->netdev;
4472 struct pci_dev *pdev = adapter->pdev;
4475 if (adapter->flags & IGC_FLAG_HAS_MSIX) {
4476 err = igc_request_msix(adapter);
4479 /* fall back to MSI */
4480 igc_free_all_tx_resources(adapter);
4481 igc_free_all_rx_resources(adapter);
4483 igc_clear_interrupt_scheme(adapter);
4484 err = igc_init_interrupt_scheme(adapter, false);
4487 igc_setup_all_tx_resources(adapter);
4488 igc_setup_all_rx_resources(adapter);
4489 igc_configure(adapter);
4492 igc_assign_vector(adapter->q_vector[0], 0);
4494 if (adapter->flags & IGC_FLAG_HAS_MSI) {
4495 err = request_irq(pdev->irq, &igc_intr_msi, 0,
4496 netdev->name, adapter);
4500 /* fall back to legacy interrupts */
4501 igc_reset_interrupt_capability(adapter);
4502 adapter->flags &= ~IGC_FLAG_HAS_MSI;
4505 err = request_irq(pdev->irq, &igc_intr, IRQF_SHARED,
4506 netdev->name, adapter);
4509 netdev_err(netdev, "Error %d getting interrupt\n", err);
4516 * __igc_open - Called when a network interface is made active
4517 * @netdev: network interface device structure
4518 * @resuming: boolean indicating if the device is resuming
4520 * Returns 0 on success, negative value on failure
4522 * The open entry point is called when a network interface is made
4523 * active by the system (IFF_UP). At this point all resources needed
4524 * for transmit and receive operations are allocated, the interrupt
4525 * handler is registered with the OS, the watchdog timer is started,
4526 * and the stack is notified that the interface is ready.
4528 static int __igc_open(struct net_device *netdev, bool resuming)
4530 struct igc_adapter *adapter = netdev_priv(netdev);
4531 struct pci_dev *pdev = adapter->pdev;
4532 struct igc_hw *hw = &adapter->hw;
4536 /* disallow open during test */
4538 if (test_bit(__IGC_TESTING, &adapter->state)) {
4544 pm_runtime_get_sync(&pdev->dev);
4546 netif_carrier_off(netdev);
4548 /* allocate transmit descriptors */
4549 err = igc_setup_all_tx_resources(adapter);
4553 /* allocate receive descriptors */
4554 err = igc_setup_all_rx_resources(adapter);
4558 igc_power_up_link(adapter);
4560 igc_configure(adapter);
4562 err = igc_request_irq(adapter);
4566 /* Notify the stack of the actual queue counts. */
4567 err = netif_set_real_num_tx_queues(netdev, adapter->num_tx_queues);
4569 goto err_set_queues;
4571 err = netif_set_real_num_rx_queues(netdev, adapter->num_rx_queues);
4573 goto err_set_queues;
4575 clear_bit(__IGC_DOWN, &adapter->state);
4577 for (i = 0; i < adapter->num_q_vectors; i++)
4578 napi_enable(&adapter->q_vector[i]->napi);
4580 /* Clear any pending interrupts. */
4582 igc_irq_enable(adapter);
4585 pm_runtime_put(&pdev->dev);
4587 netif_tx_start_all_queues(netdev);
4589 /* start the watchdog. */
4590 hw->mac.get_link_status = 1;
4591 schedule_work(&adapter->watchdog_task);
4596 igc_free_irq(adapter);
4598 igc_release_hw_control(adapter);
4599 igc_power_down_phy_copper_base(&adapter->hw);
4600 igc_free_all_rx_resources(adapter);
4602 igc_free_all_tx_resources(adapter);
4606 pm_runtime_put(&pdev->dev);
4611 int igc_open(struct net_device *netdev)
4613 return __igc_open(netdev, false);
4617 * __igc_close - Disables a network interface
4618 * @netdev: network interface device structure
4619 * @suspending: boolean indicating the device is suspending
4621 * Returns 0, this is not allowed to fail
4623 * The close entry point is called when an interface is de-activated
4624 * by the OS. The hardware is still under the driver's control, but
4625 * needs to be disabled. A global MAC reset is issued to stop the
4626 * hardware, and all transmit and receive resources are freed.
4628 static int __igc_close(struct net_device *netdev, bool suspending)
4630 struct igc_adapter *adapter = netdev_priv(netdev);
4631 struct pci_dev *pdev = adapter->pdev;
4633 WARN_ON(test_bit(__IGC_RESETTING, &adapter->state));
4636 pm_runtime_get_sync(&pdev->dev);
4640 igc_release_hw_control(adapter);
4642 igc_free_irq(adapter);
4644 igc_free_all_tx_resources(adapter);
4645 igc_free_all_rx_resources(adapter);
4648 pm_runtime_put_sync(&pdev->dev);
4653 int igc_close(struct net_device *netdev)
4655 if (netif_device_present(netdev) || netdev->dismantle)
4656 return __igc_close(netdev, false);
4661 * igc_ioctl - Access the hwtstamp interface
4662 * @netdev: network interface device structure
4663 * @ifr: interface request data
4664 * @cmd: ioctl command
4666 static int igc_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4670 return igc_ptp_get_ts_config(netdev, ifr);
4672 return igc_ptp_set_ts_config(netdev, ifr);
4678 static int igc_save_launchtime_params(struct igc_adapter *adapter, int queue,
4681 struct igc_ring *ring;
4684 if (queue < 0 || queue >= adapter->num_tx_queues)
4687 ring = adapter->tx_ring[queue];
4688 ring->launchtime_enable = enable;
4690 if (adapter->base_time)
4693 adapter->cycle_time = NSEC_PER_SEC;
4695 for (i = 0; i < adapter->num_tx_queues; i++) {
4696 ring = adapter->tx_ring[i];
4697 ring->start_time = 0;
4698 ring->end_time = NSEC_PER_SEC;
4704 static bool is_base_time_past(ktime_t base_time, const struct timespec64 *now)
4706 struct timespec64 b;
4708 b = ktime_to_timespec64(base_time);
4710 return timespec64_compare(now, &b) > 0;
4713 static bool validate_schedule(struct igc_adapter *adapter,
4714 const struct tc_taprio_qopt_offload *qopt)
4716 int queue_uses[IGC_MAX_TX_QUEUES] = { };
4717 struct timespec64 now;
4720 if (qopt->cycle_time_extension)
4723 igc_ptp_read(adapter, &now);
4725 /* If we program the controller's BASET registers with a time
4726 * in the future, it will hold all the packets until that
4727 * time, causing a lot of TX Hangs, so to avoid that, we
4728 * reject schedules that would start in the future.
4730 if (!is_base_time_past(qopt->base_time, &now))
4733 for (n = 0; n < qopt->num_entries; n++) {
4734 const struct tc_taprio_sched_entry *e;
4737 e = &qopt->entries[n];
4739 /* i225 only supports "global" frame preemption
4742 if (e->command != TC_TAPRIO_CMD_SET_GATES)
4745 for (i = 0; i < IGC_MAX_TX_QUEUES; i++) {
4746 if (e->gate_mask & BIT(i))
4749 if (queue_uses[i] > 1)
4757 static int igc_tsn_enable_launchtime(struct igc_adapter *adapter,
4758 struct tc_etf_qopt_offload *qopt)
4760 struct igc_hw *hw = &adapter->hw;
4763 if (hw->mac.type != igc_i225)
4766 err = igc_save_launchtime_params(adapter, qopt->queue, qopt->enable);
4770 return igc_tsn_offload_apply(adapter);
4773 static int igc_save_qbv_schedule(struct igc_adapter *adapter,
4774 struct tc_taprio_qopt_offload *qopt)
4776 u32 start_time = 0, end_time = 0;
4779 if (!qopt->enable) {
4780 adapter->base_time = 0;
4784 if (adapter->base_time)
4787 if (!validate_schedule(adapter, qopt))
4790 adapter->cycle_time = qopt->cycle_time;
4791 adapter->base_time = qopt->base_time;
4793 /* FIXME: be a little smarter about cases when the gate for a
4794 * queue stays open for more than one entry.
4796 for (n = 0; n < qopt->num_entries; n++) {
4797 struct tc_taprio_sched_entry *e = &qopt->entries[n];
4800 end_time += e->interval;
4802 for (i = 0; i < IGC_MAX_TX_QUEUES; i++) {
4803 struct igc_ring *ring = adapter->tx_ring[i];
4805 if (!(e->gate_mask & BIT(i)))
4808 ring->start_time = start_time;
4809 ring->end_time = end_time;
4812 start_time += e->interval;
4818 static int igc_tsn_enable_qbv_scheduling(struct igc_adapter *adapter,
4819 struct tc_taprio_qopt_offload *qopt)
4821 struct igc_hw *hw = &adapter->hw;
4824 if (hw->mac.type != igc_i225)
4827 err = igc_save_qbv_schedule(adapter, qopt);
4831 return igc_tsn_offload_apply(adapter);
4834 static int igc_setup_tc(struct net_device *dev, enum tc_setup_type type,
4837 struct igc_adapter *adapter = netdev_priv(dev);
4840 case TC_SETUP_QDISC_TAPRIO:
4841 return igc_tsn_enable_qbv_scheduling(adapter, type_data);
4843 case TC_SETUP_QDISC_ETF:
4844 return igc_tsn_enable_launchtime(adapter, type_data);
4851 static const struct net_device_ops igc_netdev_ops = {
4852 .ndo_open = igc_open,
4853 .ndo_stop = igc_close,
4854 .ndo_start_xmit = igc_xmit_frame,
4855 .ndo_set_rx_mode = igc_set_rx_mode,
4856 .ndo_set_mac_address = igc_set_mac,
4857 .ndo_change_mtu = igc_change_mtu,
4858 .ndo_get_stats = igc_get_stats,
4859 .ndo_fix_features = igc_fix_features,
4860 .ndo_set_features = igc_set_features,
4861 .ndo_features_check = igc_features_check,
4862 .ndo_do_ioctl = igc_ioctl,
4863 .ndo_setup_tc = igc_setup_tc,
4866 /* PCIe configuration access */
4867 void igc_read_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value)
4869 struct igc_adapter *adapter = hw->back;
4871 pci_read_config_word(adapter->pdev, reg, value);
4874 void igc_write_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value)
4876 struct igc_adapter *adapter = hw->back;
4878 pci_write_config_word(adapter->pdev, reg, *value);
4881 s32 igc_read_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value)
4883 struct igc_adapter *adapter = hw->back;
4885 if (!pci_is_pcie(adapter->pdev))
4886 return -IGC_ERR_CONFIG;
4888 pcie_capability_read_word(adapter->pdev, reg, value);
4893 s32 igc_write_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value)
4895 struct igc_adapter *adapter = hw->back;
4897 if (!pci_is_pcie(adapter->pdev))
4898 return -IGC_ERR_CONFIG;
4900 pcie_capability_write_word(adapter->pdev, reg, *value);
4905 u32 igc_rd32(struct igc_hw *hw, u32 reg)
4907 struct igc_adapter *igc = container_of(hw, struct igc_adapter, hw);
4908 u8 __iomem *hw_addr = READ_ONCE(hw->hw_addr);
4911 value = readl(&hw_addr[reg]);
4913 /* reads should not return all F's */
4914 if (!(~value) && (!reg || !(~readl(hw_addr)))) {
4915 struct net_device *netdev = igc->netdev;
4918 netif_device_detach(netdev);
4919 netdev_err(netdev, "PCIe link lost, device now detached\n");
4920 WARN(pci_device_is_present(igc->pdev),
4921 "igc: Failed to read reg 0x%x!\n", reg);
4927 int igc_set_spd_dplx(struct igc_adapter *adapter, u32 spd, u8 dplx)
4929 struct igc_mac_info *mac = &adapter->hw.mac;
4933 /* Make sure dplx is at most 1 bit and lsb of speed is not set
4934 * for the switch() below to work
4936 if ((spd & 1) || (dplx & ~1))
4939 switch (spd + dplx) {
4940 case SPEED_10 + DUPLEX_HALF:
4941 mac->forced_speed_duplex = ADVERTISE_10_HALF;
4943 case SPEED_10 + DUPLEX_FULL:
4944 mac->forced_speed_duplex = ADVERTISE_10_FULL;
4946 case SPEED_100 + DUPLEX_HALF:
4947 mac->forced_speed_duplex = ADVERTISE_100_HALF;
4949 case SPEED_100 + DUPLEX_FULL:
4950 mac->forced_speed_duplex = ADVERTISE_100_FULL;
4952 case SPEED_1000 + DUPLEX_FULL:
4954 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
4956 case SPEED_1000 + DUPLEX_HALF: /* not supported */
4958 case SPEED_2500 + DUPLEX_FULL:
4960 adapter->hw.phy.autoneg_advertised = ADVERTISE_2500_FULL;
4962 case SPEED_2500 + DUPLEX_HALF: /* not supported */
4967 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
4968 adapter->hw.phy.mdix = AUTO_ALL_MODES;
4973 netdev_err(adapter->netdev, "Unsupported Speed/Duplex configuration\n");
4978 * igc_probe - Device Initialization Routine
4979 * @pdev: PCI device information struct
4980 * @ent: entry in igc_pci_tbl
4982 * Returns 0 on success, negative on failure
4984 * igc_probe initializes an adapter identified by a pci_dev structure.
4985 * The OS initialization, configuring the adapter private structure,
4986 * and a hardware reset occur.
4988 static int igc_probe(struct pci_dev *pdev,
4989 const struct pci_device_id *ent)
4991 struct igc_adapter *adapter;
4992 struct net_device *netdev;
4994 const struct igc_info *ei = igc_info_tbl[ent->driver_data];
4995 int err, pci_using_dac;
4997 err = pci_enable_device_mem(pdev);
5002 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
5006 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
5009 "No usable DMA configuration, aborting\n");
5014 err = pci_request_mem_regions(pdev, igc_driver_name);
5018 pci_enable_pcie_error_reporting(pdev);
5020 pci_set_master(pdev);
5023 netdev = alloc_etherdev_mq(sizeof(struct igc_adapter),
5027 goto err_alloc_etherdev;
5029 SET_NETDEV_DEV(netdev, &pdev->dev);
5031 pci_set_drvdata(pdev, netdev);
5032 adapter = netdev_priv(netdev);
5033 adapter->netdev = netdev;
5034 adapter->pdev = pdev;
5037 adapter->port_num = hw->bus.func;
5038 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
5040 err = pci_save_state(pdev);
5045 adapter->io_addr = ioremap(pci_resource_start(pdev, 0),
5046 pci_resource_len(pdev, 0));
5047 if (!adapter->io_addr)
5050 /* hw->hw_addr can be zeroed, so use adapter->io_addr for unmap */
5051 hw->hw_addr = adapter->io_addr;
5053 netdev->netdev_ops = &igc_netdev_ops;
5054 igc_ethtool_set_ops(netdev);
5055 netdev->watchdog_timeo = 5 * HZ;
5057 netdev->mem_start = pci_resource_start(pdev, 0);
5058 netdev->mem_end = pci_resource_end(pdev, 0);
5060 /* PCI config space info */
5061 hw->vendor_id = pdev->vendor;
5062 hw->device_id = pdev->device;
5063 hw->revision_id = pdev->revision;
5064 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5065 hw->subsystem_device_id = pdev->subsystem_device;
5067 /* Copy the default MAC and PHY function pointers */
5068 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
5069 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
5071 /* Initialize skew-specific constants */
5072 err = ei->get_invariants(hw);
5076 /* Add supported features to the features list*/
5077 netdev->features |= NETIF_F_SG;
5078 netdev->features |= NETIF_F_TSO;
5079 netdev->features |= NETIF_F_TSO6;
5080 netdev->features |= NETIF_F_TSO_ECN;
5081 netdev->features |= NETIF_F_RXCSUM;
5082 netdev->features |= NETIF_F_HW_CSUM;
5083 netdev->features |= NETIF_F_SCTP_CRC;
5084 netdev->features |= NETIF_F_HW_TC;
5086 #define IGC_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \
5087 NETIF_F_GSO_GRE_CSUM | \
5088 NETIF_F_GSO_IPXIP4 | \
5089 NETIF_F_GSO_IPXIP6 | \
5090 NETIF_F_GSO_UDP_TUNNEL | \
5091 NETIF_F_GSO_UDP_TUNNEL_CSUM)
5093 netdev->gso_partial_features = IGC_GSO_PARTIAL_FEATURES;
5094 netdev->features |= NETIF_F_GSO_PARTIAL | IGC_GSO_PARTIAL_FEATURES;
5096 /* setup the private structure */
5097 err = igc_sw_init(adapter);
5101 /* copy netdev features into list of user selectable features */
5102 netdev->hw_features |= NETIF_F_NTUPLE;
5103 netdev->hw_features |= netdev->features;
5106 netdev->features |= NETIF_F_HIGHDMA;
5108 /* MTU range: 68 - 9216 */
5109 netdev->min_mtu = ETH_MIN_MTU;
5110 netdev->max_mtu = MAX_STD_JUMBO_FRAME_SIZE;
5112 /* before reading the NVM, reset the controller to put the device in a
5113 * known good starting state
5115 hw->mac.ops.reset_hw(hw);
5117 if (igc_get_flash_presence_i225(hw)) {
5118 if (hw->nvm.ops.validate(hw) < 0) {
5119 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
5125 if (eth_platform_get_mac_address(&pdev->dev, hw->mac.addr)) {
5126 /* copy the MAC address out of the NVM */
5127 if (hw->mac.ops.read_mac_addr(hw))
5128 dev_err(&pdev->dev, "NVM Read Error\n");
5131 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
5133 if (!is_valid_ether_addr(netdev->dev_addr)) {
5134 dev_err(&pdev->dev, "Invalid MAC Address\n");
5139 /* configure RXPBSIZE and TXPBSIZE */
5140 wr32(IGC_RXPBS, I225_RXPBSIZE_DEFAULT);
5141 wr32(IGC_TXPBS, I225_TXPBSIZE_DEFAULT);
5143 timer_setup(&adapter->watchdog_timer, igc_watchdog, 0);
5144 timer_setup(&adapter->phy_info_timer, igc_update_phy_info, 0);
5146 INIT_WORK(&adapter->reset_task, igc_reset_task);
5147 INIT_WORK(&adapter->watchdog_task, igc_watchdog_task);
5149 /* Initialize link properties that are user-changeable */
5150 adapter->fc_autoneg = true;
5151 hw->mac.autoneg = true;
5152 hw->phy.autoneg_advertised = 0xaf;
5154 hw->fc.requested_mode = igc_fc_default;
5155 hw->fc.current_mode = igc_fc_default;
5157 /* By default, support wake on port A */
5158 adapter->flags |= IGC_FLAG_WOL_SUPPORTED;
5160 /* initialize the wol settings based on the eeprom settings */
5161 if (adapter->flags & IGC_FLAG_WOL_SUPPORTED)
5162 adapter->wol |= IGC_WUFC_MAG;
5164 device_set_wakeup_enable(&adapter->pdev->dev,
5165 adapter->flags & IGC_FLAG_WOL_SUPPORTED);
5167 igc_ptp_init(adapter);
5169 /* reset the hardware with the new settings */
5172 /* let the f/w know that the h/w is now under the control of the
5175 igc_get_hw_control(adapter);
5177 strncpy(netdev->name, "eth%d", IFNAMSIZ);
5178 err = register_netdev(netdev);
5182 /* carrier off reporting is important to ethtool even BEFORE open */
5183 netif_carrier_off(netdev);
5185 /* Check if Media Autosense is enabled */
5188 /* print pcie link status and MAC address */
5189 pcie_print_link_status(pdev);
5190 netdev_info(netdev, "MAC: %pM\n", netdev->dev_addr);
5192 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
5193 /* Disable EEE for internal PHY devices */
5194 hw->dev_spec._base.eee_enable = false;
5195 adapter->flags &= ~IGC_FLAG_EEE;
5196 igc_set_eee_i225(hw, false, false, false);
5198 pm_runtime_put_noidle(&pdev->dev);
5203 igc_release_hw_control(adapter);
5205 if (!igc_check_reset_block(hw))
5208 igc_clear_interrupt_scheme(adapter);
5209 iounmap(adapter->io_addr);
5211 free_netdev(netdev);
5213 pci_release_mem_regions(pdev);
5216 pci_disable_device(pdev);
5221 * igc_remove - Device Removal Routine
5222 * @pdev: PCI device information struct
5224 * igc_remove is called by the PCI subsystem to alert the driver
5225 * that it should release a PCI device. This could be caused by a
5226 * Hot-Plug event, or because the driver is going to be removed from
5229 static void igc_remove(struct pci_dev *pdev)
5231 struct net_device *netdev = pci_get_drvdata(pdev);
5232 struct igc_adapter *adapter = netdev_priv(netdev);
5234 pm_runtime_get_noresume(&pdev->dev);
5236 igc_flush_nfc_rules(adapter);
5238 igc_ptp_stop(adapter);
5240 set_bit(__IGC_DOWN, &adapter->state);
5242 del_timer_sync(&adapter->watchdog_timer);
5243 del_timer_sync(&adapter->phy_info_timer);
5245 cancel_work_sync(&adapter->reset_task);
5246 cancel_work_sync(&adapter->watchdog_task);
5248 /* Release control of h/w to f/w. If f/w is AMT enabled, this
5249 * would have already happened in close and is redundant.
5251 igc_release_hw_control(adapter);
5252 unregister_netdev(netdev);
5254 igc_clear_interrupt_scheme(adapter);
5255 pci_iounmap(pdev, adapter->io_addr);
5256 pci_release_mem_regions(pdev);
5258 free_netdev(netdev);
5260 pci_disable_pcie_error_reporting(pdev);
5262 pci_disable_device(pdev);
5265 static int __igc_shutdown(struct pci_dev *pdev, bool *enable_wake,
5268 struct net_device *netdev = pci_get_drvdata(pdev);
5269 struct igc_adapter *adapter = netdev_priv(netdev);
5270 u32 wufc = runtime ? IGC_WUFC_LNKC : adapter->wol;
5271 struct igc_hw *hw = &adapter->hw;
5272 u32 ctrl, rctl, status;
5276 netif_device_detach(netdev);
5278 if (netif_running(netdev))
5279 __igc_close(netdev, true);
5281 igc_ptp_suspend(adapter);
5283 igc_clear_interrupt_scheme(adapter);
5286 status = rd32(IGC_STATUS);
5287 if (status & IGC_STATUS_LU)
5288 wufc &= ~IGC_WUFC_LNKC;
5291 igc_setup_rctl(adapter);
5292 igc_set_rx_mode(netdev);
5294 /* turn on all-multi mode if wake on multicast is enabled */
5295 if (wufc & IGC_WUFC_MC) {
5296 rctl = rd32(IGC_RCTL);
5297 rctl |= IGC_RCTL_MPE;
5298 wr32(IGC_RCTL, rctl);
5301 ctrl = rd32(IGC_CTRL);
5302 ctrl |= IGC_CTRL_ADVD3WUC;
5303 wr32(IGC_CTRL, ctrl);
5305 /* Allow time for pending master requests to run */
5306 igc_disable_pcie_master(hw);
5308 wr32(IGC_WUC, IGC_WUC_PME_EN);
5309 wr32(IGC_WUFC, wufc);
5315 wake = wufc || adapter->en_mng_pt;
5317 igc_power_down_phy_copper_base(&adapter->hw);
5319 igc_power_up_link(adapter);
5322 *enable_wake = wake;
5324 /* Release control of h/w to f/w. If f/w is AMT enabled, this
5325 * would have already happened in close and is redundant.
5327 igc_release_hw_control(adapter);
5329 pci_disable_device(pdev);
5335 static int __maybe_unused igc_runtime_suspend(struct device *dev)
5337 return __igc_shutdown(to_pci_dev(dev), NULL, 1);
5340 static void igc_deliver_wake_packet(struct net_device *netdev)
5342 struct igc_adapter *adapter = netdev_priv(netdev);
5343 struct igc_hw *hw = &adapter->hw;
5344 struct sk_buff *skb;
5347 wupl = rd32(IGC_WUPL) & IGC_WUPL_MASK;
5349 /* WUPM stores only the first 128 bytes of the wake packet.
5350 * Read the packet only if we have the whole thing.
5352 if (wupl == 0 || wupl > IGC_WUPM_BYTES)
5355 skb = netdev_alloc_skb_ip_align(netdev, IGC_WUPM_BYTES);
5361 /* Ensure reads are 32-bit aligned */
5362 wupl = roundup(wupl, 4);
5364 memcpy_fromio(skb->data, hw->hw_addr + IGC_WUPM_REG(0), wupl);
5366 skb->protocol = eth_type_trans(skb, netdev);
5370 static int __maybe_unused igc_resume(struct device *dev)
5372 struct pci_dev *pdev = to_pci_dev(dev);
5373 struct net_device *netdev = pci_get_drvdata(pdev);
5374 struct igc_adapter *adapter = netdev_priv(netdev);
5375 struct igc_hw *hw = &adapter->hw;
5378 pci_set_power_state(pdev, PCI_D0);
5379 pci_restore_state(pdev);
5380 pci_save_state(pdev);
5382 if (!pci_device_is_present(pdev))
5384 err = pci_enable_device_mem(pdev);
5386 netdev_err(netdev, "Cannot enable PCI device from suspend\n");
5389 pci_set_master(pdev);
5391 pci_enable_wake(pdev, PCI_D3hot, 0);
5392 pci_enable_wake(pdev, PCI_D3cold, 0);
5394 if (igc_init_interrupt_scheme(adapter, true)) {
5395 netdev_err(netdev, "Unable to allocate memory for queues\n");
5401 /* let the f/w know that the h/w is now under the control of the
5404 igc_get_hw_control(adapter);
5406 val = rd32(IGC_WUS);
5407 if (val & WAKE_PKT_WUS)
5408 igc_deliver_wake_packet(netdev);
5413 if (!err && netif_running(netdev))
5414 err = __igc_open(netdev, true);
5417 netif_device_attach(netdev);
5423 static int __maybe_unused igc_runtime_resume(struct device *dev)
5425 return igc_resume(dev);
5428 static int __maybe_unused igc_suspend(struct device *dev)
5430 return __igc_shutdown(to_pci_dev(dev), NULL, 0);
5433 static int __maybe_unused igc_runtime_idle(struct device *dev)
5435 struct net_device *netdev = dev_get_drvdata(dev);
5436 struct igc_adapter *adapter = netdev_priv(netdev);
5438 if (!igc_has_link(adapter))
5439 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
5443 #endif /* CONFIG_PM */
5445 static void igc_shutdown(struct pci_dev *pdev)
5449 __igc_shutdown(pdev, &wake, 0);
5451 if (system_state == SYSTEM_POWER_OFF) {
5452 pci_wake_from_d3(pdev, wake);
5453 pci_set_power_state(pdev, PCI_D3hot);
5458 * igc_io_error_detected - called when PCI error is detected
5459 * @pdev: Pointer to PCI device
5460 * @state: The current PCI connection state
5462 * This function is called after a PCI bus error affecting
5463 * this device has been detected.
5465 static pci_ers_result_t igc_io_error_detected(struct pci_dev *pdev,
5466 pci_channel_state_t state)
5468 struct net_device *netdev = pci_get_drvdata(pdev);
5469 struct igc_adapter *adapter = netdev_priv(netdev);
5471 netif_device_detach(netdev);
5473 if (state == pci_channel_io_perm_failure)
5474 return PCI_ERS_RESULT_DISCONNECT;
5476 if (netif_running(netdev))
5478 pci_disable_device(pdev);
5480 /* Request a slot reset. */
5481 return PCI_ERS_RESULT_NEED_RESET;
5485 * igc_io_slot_reset - called after the PCI bus has been reset.
5486 * @pdev: Pointer to PCI device
5488 * Restart the card from scratch, as if from a cold-boot. Implementation
5489 * resembles the first-half of the igc_resume routine.
5491 static pci_ers_result_t igc_io_slot_reset(struct pci_dev *pdev)
5493 struct net_device *netdev = pci_get_drvdata(pdev);
5494 struct igc_adapter *adapter = netdev_priv(netdev);
5495 struct igc_hw *hw = &adapter->hw;
5496 pci_ers_result_t result;
5498 if (pci_enable_device_mem(pdev)) {
5499 netdev_err(netdev, "Could not re-enable PCI device after reset\n");
5500 result = PCI_ERS_RESULT_DISCONNECT;
5502 pci_set_master(pdev);
5503 pci_restore_state(pdev);
5504 pci_save_state(pdev);
5506 pci_enable_wake(pdev, PCI_D3hot, 0);
5507 pci_enable_wake(pdev, PCI_D3cold, 0);
5509 /* In case of PCI error, adapter loses its HW address
5510 * so we should re-assign it here.
5512 hw->hw_addr = adapter->io_addr;
5516 result = PCI_ERS_RESULT_RECOVERED;
5523 * igc_io_resume - called when traffic can start to flow again.
5524 * @pdev: Pointer to PCI device
5526 * This callback is called when the error recovery driver tells us that
5527 * its OK to resume normal operation. Implementation resembles the
5528 * second-half of the igc_resume routine.
5530 static void igc_io_resume(struct pci_dev *pdev)
5532 struct net_device *netdev = pci_get_drvdata(pdev);
5533 struct igc_adapter *adapter = netdev_priv(netdev);
5536 if (netif_running(netdev)) {
5537 if (igc_open(netdev)) {
5538 netdev_err(netdev, "igc_open failed after reset\n");
5543 netif_device_attach(netdev);
5545 /* let the f/w know that the h/w is now under the control of the
5548 igc_get_hw_control(adapter);
5552 static const struct pci_error_handlers igc_err_handler = {
5553 .error_detected = igc_io_error_detected,
5554 .slot_reset = igc_io_slot_reset,
5555 .resume = igc_io_resume,
5559 static const struct dev_pm_ops igc_pm_ops = {
5560 SET_SYSTEM_SLEEP_PM_OPS(igc_suspend, igc_resume)
5561 SET_RUNTIME_PM_OPS(igc_runtime_suspend, igc_runtime_resume,
5566 static struct pci_driver igc_driver = {
5567 .name = igc_driver_name,
5568 .id_table = igc_pci_tbl,
5570 .remove = igc_remove,
5572 .driver.pm = &igc_pm_ops,
5574 .shutdown = igc_shutdown,
5575 .err_handler = &igc_err_handler,
5579 * igc_reinit_queues - return error
5580 * @adapter: pointer to adapter structure
5582 int igc_reinit_queues(struct igc_adapter *adapter)
5584 struct net_device *netdev = adapter->netdev;
5587 if (netif_running(netdev))
5590 igc_reset_interrupt_capability(adapter);
5592 if (igc_init_interrupt_scheme(adapter, true)) {
5593 netdev_err(netdev, "Unable to allocate memory for queues\n");
5597 if (netif_running(netdev))
5598 err = igc_open(netdev);
5604 * igc_get_hw_dev - return device
5605 * @hw: pointer to hardware structure
5607 * used by hardware layer to print debugging information
5609 struct net_device *igc_get_hw_dev(struct igc_hw *hw)
5611 struct igc_adapter *adapter = hw->back;
5613 return adapter->netdev;
5617 * igc_init_module - Driver Registration Routine
5619 * igc_init_module is the first routine called when the driver is
5620 * loaded. All it does is register with the PCI subsystem.
5622 static int __init igc_init_module(void)
5626 pr_info("%s\n", igc_driver_string);
5627 pr_info("%s\n", igc_copyright);
5629 ret = pci_register_driver(&igc_driver);
5633 module_init(igc_init_module);
5636 * igc_exit_module - Driver Exit Cleanup Routine
5638 * igc_exit_module is called just before the driver is removed
5641 static void __exit igc_exit_module(void)
5643 pci_unregister_driver(&igc_driver);
5646 module_exit(igc_exit_module);