1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018 Intel Corporation */
4 #include <linux/delay.h>
9 * igc_acquire_nvm_i225 - Acquire exclusive access to EEPROM
10 * @hw: pointer to the HW structure
12 * Acquire the necessary semaphores for exclusive access to the EEPROM.
13 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
14 * Return successful if access grant bit set, else clear the request for
15 * EEPROM access and return -IGC_ERR_NVM (-1).
17 static s32 igc_acquire_nvm_i225(struct igc_hw *hw)
19 return igc_acquire_swfw_sync_i225(hw, IGC_SWFW_EEP_SM);
23 * igc_release_nvm_i225 - Release exclusive access to EEPROM
24 * @hw: pointer to the HW structure
26 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
27 * then release the semaphores acquired.
29 static void igc_release_nvm_i225(struct igc_hw *hw)
31 igc_release_swfw_sync_i225(hw, IGC_SWFW_EEP_SM);
35 * igc_get_hw_semaphore_i225 - Acquire hardware semaphore
36 * @hw: pointer to the HW structure
38 * Acquire the HW semaphore to access the PHY or NVM
40 static s32 igc_get_hw_semaphore_i225(struct igc_hw *hw)
42 s32 timeout = hw->nvm.word_size + 1;
46 /* Get the SW semaphore */
48 swsm = rd32(IGC_SWSM);
49 if (!(swsm & IGC_SWSM_SMBI))
52 usleep_range(500, 600);
57 /* In rare circumstances, the SW semaphore may already be held
58 * unintentionally. Clear the semaphore once before giving up.
60 if (hw->dev_spec._base.clear_semaphore_once) {
61 hw->dev_spec._base.clear_semaphore_once = false;
62 igc_put_hw_semaphore(hw);
63 for (i = 0; i < timeout; i++) {
64 swsm = rd32(IGC_SWSM);
65 if (!(swsm & IGC_SWSM_SMBI))
68 usleep_range(500, 600);
72 /* If we do not have the semaphore here, we have to give up. */
74 hw_dbg("Driver can't access device - SMBI bit is set.\n");
79 /* Get the FW semaphore. */
80 for (i = 0; i < timeout; i++) {
81 swsm = rd32(IGC_SWSM);
82 wr32(IGC_SWSM, swsm | IGC_SWSM_SWESMBI);
84 /* Semaphore acquired if bit latched */
85 if (rd32(IGC_SWSM) & IGC_SWSM_SWESMBI)
88 usleep_range(500, 600);
92 /* Release semaphores */
93 igc_put_hw_semaphore(hw);
94 hw_dbg("Driver can't access the NVM\n");
102 * igc_acquire_swfw_sync_i225 - Acquire SW/FW semaphore
103 * @hw: pointer to the HW structure
104 * @mask: specifies which semaphore to acquire
106 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
107 * will also specify which port we're acquiring the lock for.
109 s32 igc_acquire_swfw_sync_i225(struct igc_hw *hw, u16 mask)
111 s32 i = 0, timeout = 200;
112 u32 fwmask = mask << 16;
117 while (i < timeout) {
118 if (igc_get_hw_semaphore_i225(hw)) {
119 ret_val = -IGC_ERR_SWFW_SYNC;
123 swfw_sync = rd32(IGC_SW_FW_SYNC);
124 if (!(swfw_sync & (fwmask | swmask)))
127 /* Firmware currently using resource (fwmask) */
128 igc_put_hw_semaphore(hw);
134 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
135 ret_val = -IGC_ERR_SWFW_SYNC;
140 wr32(IGC_SW_FW_SYNC, swfw_sync);
142 igc_put_hw_semaphore(hw);
148 * igc_release_swfw_sync_i225 - Release SW/FW semaphore
149 * @hw: pointer to the HW structure
150 * @mask: specifies which semaphore to acquire
152 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
153 * will also specify which port we're releasing the lock for.
155 void igc_release_swfw_sync_i225(struct igc_hw *hw, u16 mask)
159 while (igc_get_hw_semaphore_i225(hw))
162 swfw_sync = rd32(IGC_SW_FW_SYNC);
164 wr32(IGC_SW_FW_SYNC, swfw_sync);
166 igc_put_hw_semaphore(hw);
170 * igc_read_nvm_srrd_i225 - Reads Shadow Ram using EERD register
171 * @hw: pointer to the HW structure
172 * @offset: offset of word in the Shadow Ram to read
173 * @words: number of words to read
174 * @data: word read from the Shadow Ram
176 * Reads a 16 bit word from the Shadow Ram using the EERD register.
177 * Uses necessary synchronization semaphores.
179 static s32 igc_read_nvm_srrd_i225(struct igc_hw *hw, u16 offset, u16 words,
185 /* We cannot hold synchronization semaphores for too long,
186 * because of forceful takeover procedure. However it is more efficient
187 * to read in bursts than synchronizing access for each word.
189 for (i = 0; i < words; i += IGC_EERD_EEWR_MAX_COUNT) {
190 count = (words - i) / IGC_EERD_EEWR_MAX_COUNT > 0 ?
191 IGC_EERD_EEWR_MAX_COUNT : (words - i);
193 status = hw->nvm.ops.acquire(hw);
197 status = igc_read_nvm_eerd(hw, offset, count, data + i);
198 hw->nvm.ops.release(hw);
207 * igc_write_nvm_srwr - Write to Shadow Ram using EEWR
208 * @hw: pointer to the HW structure
209 * @offset: offset within the Shadow Ram to be written to
210 * @words: number of words to write
211 * @data: 16 bit word(s) to be written to the Shadow Ram
213 * Writes data to Shadow Ram at offset using EEWR register.
215 * If igc_update_nvm_checksum is not called after this function , the
216 * Shadow Ram will most likely contain an invalid checksum.
218 static s32 igc_write_nvm_srwr(struct igc_hw *hw, u16 offset, u16 words,
221 struct igc_nvm_info *nvm = &hw->nvm;
222 s32 ret_val = -IGC_ERR_NVM;
223 u32 attempts = 100000;
226 /* A check for invalid values: offset too large, too many words,
227 * too many words for the offset, and not enough words.
229 if (offset >= nvm->word_size || (words > (nvm->word_size - offset)) ||
231 hw_dbg("nvm parameter(s) out of bounds\n");
235 for (i = 0; i < words; i++) {
236 ret_val = -IGC_ERR_NVM;
237 eewr = ((offset + i) << IGC_NVM_RW_ADDR_SHIFT) |
238 (data[i] << IGC_NVM_RW_REG_DATA) |
239 IGC_NVM_RW_REG_START;
241 wr32(IGC_SRWR, eewr);
243 for (k = 0; k < attempts; k++) {
244 if (IGC_NVM_RW_REG_DONE &
253 hw_dbg("Shadow RAM write EEWR timed out\n");
262 * igc_write_nvm_srwr_i225 - Write to Shadow RAM using EEWR
263 * @hw: pointer to the HW structure
264 * @offset: offset within the Shadow RAM to be written to
265 * @words: number of words to write
266 * @data: 16 bit word(s) to be written to the Shadow RAM
268 * Writes data to Shadow RAM at offset using EEWR register.
270 * If igc_update_nvm_checksum is not called after this function , the
271 * data will not be committed to FLASH and also Shadow RAM will most likely
272 * contain an invalid checksum.
274 * If error code is returned, data and Shadow RAM may be inconsistent - buffer
277 static s32 igc_write_nvm_srwr_i225(struct igc_hw *hw, u16 offset, u16 words,
283 /* We cannot hold synchronization semaphores for too long,
284 * because of forceful takeover procedure. However it is more efficient
285 * to write in bursts than synchronizing access for each word.
287 for (i = 0; i < words; i += IGC_EERD_EEWR_MAX_COUNT) {
288 count = (words - i) / IGC_EERD_EEWR_MAX_COUNT > 0 ?
289 IGC_EERD_EEWR_MAX_COUNT : (words - i);
291 status = hw->nvm.ops.acquire(hw);
295 status = igc_write_nvm_srwr(hw, offset, count, data + i);
296 hw->nvm.ops.release(hw);
305 * igc_validate_nvm_checksum_i225 - Validate EEPROM checksum
306 * @hw: pointer to the HW structure
308 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
309 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
311 static s32 igc_validate_nvm_checksum_i225(struct igc_hw *hw)
313 s32 (*read_op_ptr)(struct igc_hw *hw, u16 offset, u16 count,
317 status = hw->nvm.ops.acquire(hw);
321 /* Replace the read function with semaphore grabbing with
322 * the one that skips this for a while.
323 * We have semaphore taken already here.
325 read_op_ptr = hw->nvm.ops.read;
326 hw->nvm.ops.read = igc_read_nvm_eerd;
328 status = igc_validate_nvm_checksum(hw);
330 /* Revert original read operation. */
331 hw->nvm.ops.read = read_op_ptr;
333 hw->nvm.ops.release(hw);
340 * igc_pool_flash_update_done_i225 - Pool FLUDONE status
341 * @hw: pointer to the HW structure
343 static s32 igc_pool_flash_update_done_i225(struct igc_hw *hw)
345 s32 ret_val = -IGC_ERR_NVM;
348 for (i = 0; i < IGC_FLUDONE_ATTEMPTS; i++) {
349 reg = rd32(IGC_EECD);
350 if (reg & IGC_EECD_FLUDONE_I225) {
361 * igc_update_flash_i225 - Commit EEPROM to the flash
362 * @hw: pointer to the HW structure
364 static s32 igc_update_flash_i225(struct igc_hw *hw)
369 ret_val = igc_pool_flash_update_done_i225(hw);
370 if (ret_val == -IGC_ERR_NVM) {
371 hw_dbg("Flash update time out\n");
375 flup = rd32(IGC_EECD) | IGC_EECD_FLUPD_I225;
376 wr32(IGC_EECD, flup);
378 ret_val = igc_pool_flash_update_done_i225(hw);
380 hw_dbg("Flash update time out\n");
382 hw_dbg("Flash update complete\n");
389 * igc_update_nvm_checksum_i225 - Update EEPROM checksum
390 * @hw: pointer to the HW structure
392 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
393 * up to the checksum. Then calculates the EEPROM checksum and writes the
394 * value to the EEPROM. Next commit EEPROM data onto the Flash.
396 static s32 igc_update_nvm_checksum_i225(struct igc_hw *hw)
402 /* Read the first word from the EEPROM. If this times out or fails, do
403 * not continue or we could be in for a very long wait while every
406 ret_val = igc_read_nvm_eerd(hw, 0, 1, &nvm_data);
408 hw_dbg("EEPROM read failed\n");
412 ret_val = hw->nvm.ops.acquire(hw);
416 /* Do not use hw->nvm.ops.write, hw->nvm.ops.read
417 * because we do not want to take the synchronization
418 * semaphores twice here.
421 for (i = 0; i < NVM_CHECKSUM_REG; i++) {
422 ret_val = igc_read_nvm_eerd(hw, i, 1, &nvm_data);
424 hw->nvm.ops.release(hw);
425 hw_dbg("NVM Read Error while updating checksum.\n");
428 checksum += nvm_data;
430 checksum = (u16)NVM_SUM - checksum;
431 ret_val = igc_write_nvm_srwr(hw, NVM_CHECKSUM_REG, 1,
434 hw->nvm.ops.release(hw);
435 hw_dbg("NVM Write Error while updating checksum.\n");
439 hw->nvm.ops.release(hw);
441 ret_val = igc_update_flash_i225(hw);
448 * igc_get_flash_presence_i225 - Check if flash device is detected
449 * @hw: pointer to the HW structure
451 bool igc_get_flash_presence_i225(struct igc_hw *hw)
453 bool ret_val = false;
456 eec = rd32(IGC_EECD);
457 if (eec & IGC_EECD_FLASH_DETECTED_I225)
464 * igc_init_nvm_params_i225 - Init NVM func ptrs.
465 * @hw: pointer to the HW structure
467 s32 igc_init_nvm_params_i225(struct igc_hw *hw)
469 struct igc_nvm_info *nvm = &hw->nvm;
471 nvm->ops.acquire = igc_acquire_nvm_i225;
472 nvm->ops.release = igc_release_nvm_i225;
474 /* NVM Function Pointers */
475 if (igc_get_flash_presence_i225(hw)) {
476 nvm->ops.read = igc_read_nvm_srrd_i225;
477 nvm->ops.write = igc_write_nvm_srwr_i225;
478 nvm->ops.validate = igc_validate_nvm_checksum_i225;
479 nvm->ops.update = igc_update_nvm_checksum_i225;
481 nvm->ops.read = igc_read_nvm_eerd;
482 nvm->ops.write = NULL;
483 nvm->ops.validate = NULL;
484 nvm->ops.update = NULL;
490 * igc_set_eee_i225 - Enable/disable EEE support
491 * @hw: pointer to the HW structure
492 * @adv2p5G: boolean flag enabling 2.5G EEE advertisement
493 * @adv1G: boolean flag enabling 1G EEE advertisement
494 * @adv100M: boolean flag enabling 100M EEE advertisement
496 * Enable/disable EEE based on setting in dev_spec structure.
498 s32 igc_set_eee_i225(struct igc_hw *hw, bool adv2p5G, bool adv1G,
503 ipcnfg = rd32(IGC_IPCNFG);
504 eeer = rd32(IGC_EEER);
506 /* enable or disable per user setting */
507 if (hw->dev_spec._base.eee_enable) {
508 u32 eee_su = rd32(IGC_EEE_SU);
511 ipcnfg |= IGC_IPCNFG_EEE_100M_AN;
513 ipcnfg &= ~IGC_IPCNFG_EEE_100M_AN;
516 ipcnfg |= IGC_IPCNFG_EEE_1G_AN;
518 ipcnfg &= ~IGC_IPCNFG_EEE_1G_AN;
521 ipcnfg |= IGC_IPCNFG_EEE_2_5G_AN;
523 ipcnfg &= ~IGC_IPCNFG_EEE_2_5G_AN;
525 eeer |= (IGC_EEER_TX_LPI_EN | IGC_EEER_RX_LPI_EN |
528 /* This bit should not be set in normal operation. */
529 if (eee_su & IGC_EEE_SU_LPI_CLK_STP)
530 hw_dbg("LPI Clock Stop Bit should not be set!\n");
532 ipcnfg &= ~(IGC_IPCNFG_EEE_2_5G_AN | IGC_IPCNFG_EEE_1G_AN |
533 IGC_IPCNFG_EEE_100M_AN);
534 eeer &= ~(IGC_EEER_TX_LPI_EN | IGC_EEER_RX_LPI_EN |
537 wr32(IGC_IPCNFG, ipcnfg);
538 wr32(IGC_EEER, eeer);
545 /* igc_set_ltr_i225 - Set Latency Tolerance Reporting thresholds
546 * @hw: pointer to the HW structure
547 * @link: bool indicating link status
549 * Set the LTR thresholds based on the link speed (Mbps), EEE, and DMAC
550 * settings, otherwise specify that there is no LTR requirement.
552 s32 igc_set_ltr_i225(struct igc_hw *hw, bool link)
554 u32 tw_system, ltrc, ltrv, ltr_min, ltr_max, scale_min, scale_max;
558 /* If we do not have link, LTR thresholds are zero. */
560 hw->mac.ops.get_speed_and_duplex(hw, &speed, &duplex);
562 /* Check if using copper interface with EEE enabled or if the
563 * link speed is 10 Mbps.
565 if (hw->dev_spec._base.eee_enable &&
567 /* EEE enabled, so send LTRMAX threshold. */
568 ltrc = rd32(IGC_LTRC) |
570 wr32(IGC_LTRC, ltrc);
572 /* Calculate tw_system (nsec). */
573 if (speed == SPEED_100) {
574 tw_system = ((rd32(IGC_EEE_SU) &
575 IGC_TW_SYSTEM_100_MASK) >>
576 IGC_TW_SYSTEM_100_SHIFT) * 500;
578 tw_system = (rd32(IGC_EEE_SU) &
579 IGC_TW_SYSTEM_1000_MASK) * 500;
585 /* Get the Rx packet buffer size. */
586 size = rd32(IGC_RXPBS) &
587 IGC_RXPBS_SIZE_I225_MASK;
589 /* Calculations vary based on DMAC settings. */
590 if (rd32(IGC_DMACR) & IGC_DMACR_DMAC_EN) {
591 size -= (rd32(IGC_DMACR) &
592 IGC_DMACR_DMACTHR_MASK) >>
593 IGC_DMACR_DMACTHR_SHIFT;
594 /* Convert size to bits. */
597 /* Convert size to bytes, subtract the MTU, and then
598 * convert the size to bits.
605 hw_dbg("Invalid effective Rx buffer size %d\n",
607 return -IGC_ERR_CONFIG;
610 /* Calculate the thresholds. Since speed is in Mbps, simplify
611 * the calculation by multiplying size/speed by 1000 for result
612 * to be in nsec before dividing by the scale in nsec. Set the
613 * scale such that the LTR threshold fits in the register.
615 ltr_min = (1000 * size) / speed;
616 ltr_max = ltr_min + tw_system;
617 scale_min = (ltr_min / 1024) < 1024 ? IGC_LTRMINV_SCALE_1024 :
618 IGC_LTRMINV_SCALE_32768;
619 scale_max = (ltr_max / 1024) < 1024 ? IGC_LTRMAXV_SCALE_1024 :
620 IGC_LTRMAXV_SCALE_32768;
621 ltr_min /= scale_min == IGC_LTRMINV_SCALE_1024 ? 1024 : 32768;
623 ltr_max /= scale_max == IGC_LTRMAXV_SCALE_1024 ? 1024 : 32768;
626 /* Only write the LTR thresholds if they differ from before. */
627 ltrv = rd32(IGC_LTRMINV);
628 if (ltr_min != (ltrv & IGC_LTRMINV_LTRV_MASK)) {
629 ltrv = IGC_LTRMINV_LSNP_REQ | ltr_min |
630 (scale_min << IGC_LTRMINV_SCALE_SHIFT);
631 wr32(IGC_LTRMINV, ltrv);
634 ltrv = rd32(IGC_LTRMAXV);
635 if (ltr_max != (ltrv & IGC_LTRMAXV_LTRV_MASK)) {
636 ltrv = IGC_LTRMAXV_LSNP_REQ | ltr_max |
637 (scale_max << IGC_LTRMAXV_SCALE_SHIFT);
638 wr32(IGC_LTRMAXV, ltrv);