1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018 Intel Corporation */
7 #include <linux/types.h>
8 #include <linux/if_ether.h>
9 #include <linux/netdevice.h>
12 #include "igc_defines.h"
19 #define IGC_DEV_ID_I225_LM 0x15F2
20 #define IGC_DEV_ID_I225_V 0x15F3
21 #define IGC_DEV_ID_I225_I 0x15F8
22 #define IGC_DEV_ID_I220_V 0x15F7
23 #define IGC_DEV_ID_I225_K 0x3100
24 #define IGC_DEV_ID_I225_K2 0x3101
25 #define IGC_DEV_ID_I226_K 0x3102
26 #define IGC_DEV_ID_I225_LMVP 0x5502
27 #define IGC_DEV_ID_I226_LMVP 0x5503
28 #define IGC_DEV_ID_I225_IT 0x0D9F
29 #define IGC_DEV_ID_I226_LM 0x125B
30 #define IGC_DEV_ID_I226_V 0x125C
31 #define IGC_DEV_ID_I226_IT 0x125D
32 #define IGC_DEV_ID_I221_V 0x125E
33 #define IGC_DEV_ID_I226_BLANK_NVM 0x125F
34 #define IGC_DEV_ID_I225_BLANK_NVM 0x15FD
36 /* Function pointers for the MAC. */
37 struct igc_mac_operations {
38 s32 (*check_for_link)(struct igc_hw *hw);
39 s32 (*reset_hw)(struct igc_hw *hw);
40 s32 (*init_hw)(struct igc_hw *hw);
41 s32 (*setup_physical_interface)(struct igc_hw *hw);
42 void (*rar_set)(struct igc_hw *hw, u8 *address, u32 index);
43 s32 (*read_mac_addr)(struct igc_hw *hw);
44 s32 (*get_speed_and_duplex)(struct igc_hw *hw, u16 *speed,
46 s32 (*acquire_swfw_sync)(struct igc_hw *hw, u16 mask);
47 void (*release_swfw_sync)(struct igc_hw *hw, u16 mask);
53 igc_num_macs /* List is 1-based, so subtract 1 for true count. */
57 igc_media_type_unknown = 0,
58 igc_media_type_copper = 1,
68 s32 (*get_invariants)(struct igc_hw *hw);
69 struct igc_mac_operations *mac_ops;
70 const struct igc_phy_operations *phy_ops;
71 struct igc_nvm_operations *nvm_ops;
74 extern const struct igc_info igc_base_info;
77 struct igc_mac_operations ops;
80 u8 perm_addr[ETH_ALEN];
82 enum igc_mac_type type;
89 u32 mta_shadow[MAX_MTA_REG];
92 u8 forced_speed_duplex;
94 bool asf_firmware_present;
95 bool arc_subsystem_valid;
102 struct igc_nvm_operations {
103 s32 (*acquire)(struct igc_hw *hw);
104 s32 (*read)(struct igc_hw *hw, u16 offset, u16 i, u16 *data);
105 void (*release)(struct igc_hw *hw);
106 s32 (*write)(struct igc_hw *hw, u16 offset, u16 i, u16 *data);
107 s32 (*update)(struct igc_hw *hw);
108 s32 (*validate)(struct igc_hw *hw);
111 struct igc_phy_operations {
112 s32 (*acquire)(struct igc_hw *hw);
113 s32 (*check_reset_block)(struct igc_hw *hw);
114 s32 (*force_speed_duplex)(struct igc_hw *hw);
115 s32 (*get_phy_info)(struct igc_hw *hw);
116 s32 (*read_reg)(struct igc_hw *hw, u32 address, u16 *data);
117 void (*release)(struct igc_hw *hw);
118 s32 (*reset)(struct igc_hw *hw);
119 s32 (*write_reg)(struct igc_hw *hw, u32 address, u16 data);
122 struct igc_nvm_info {
123 struct igc_nvm_operations ops;
124 enum igc_nvm_type type;
133 struct igc_phy_info {
134 struct igc_phy_operations ops;
138 u32 reset_delay_us; /* in usec */
141 enum igc_media_type media_type;
143 u16 autoneg_advertised;
149 bool speed_downgraded;
150 bool autoneg_wait_to_complete;
153 struct igc_bus_info {
163 igc_fc_default = 0xFF
167 u32 high_water; /* Flow control high-water mark */
168 u32 low_water; /* Flow control low-water mark */
169 u16 pause_time; /* Flow control pause timer */
170 bool send_xon; /* Flow control send XON */
171 bool strict_ieee; /* Strict IEEE mode */
172 enum igc_fc_mode current_mode; /* Type of flow control */
173 enum igc_fc_mode requested_mode;
176 struct igc_dev_spec_base {
177 bool clear_semaphore_once;
185 unsigned long io_base;
187 struct igc_mac_info mac;
188 struct igc_fc_info fc;
189 struct igc_nvm_info nvm;
190 struct igc_phy_info phy;
192 struct igc_bus_info bus;
195 struct igc_dev_spec_base _base;
199 u16 subsystem_vendor_id;
200 u16 subsystem_device_id;
206 /* Statistics counters collected by the MAC */
207 struct igc_hw_stats {
280 struct net_device *igc_get_hw_dev(struct igc_hw *hw);
281 #define hw_dbg(format, arg...) \
282 netdev_dbg(igc_get_hw_dev(hw), format, ##arg)
284 s32 igc_read_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value);
285 s32 igc_write_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value);
286 void igc_read_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value);
287 void igc_write_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value);
289 #endif /* _IGC_HW_H_ */