1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018 Intel Corporation */
7 #include <linux/types.h>
8 #include <linux/if_ether.h>
9 #include <linux/netdevice.h>
12 #include "igc_defines.h"
19 #define IGC_DEV_ID_I225_LM 0x15F2
20 #define IGC_DEV_ID_I225_V 0x15F3
21 #define IGC_DEV_ID_I225_I 0x15F8
22 #define IGC_DEV_ID_I220_V 0x15F7
23 #define IGC_DEV_ID_I225_K 0x3100
24 #define IGC_DEV_ID_I225_K2 0x3101
25 #define IGC_DEV_ID_I225_LMVP 0x5502
26 #define IGC_DEV_ID_I225_IT 0x0D9F
27 #define IGC_DEV_ID_I225_BLANK_NVM 0x15FD
29 /* Function pointers for the MAC. */
30 struct igc_mac_operations {
31 s32 (*check_for_link)(struct igc_hw *hw);
32 s32 (*reset_hw)(struct igc_hw *hw);
33 s32 (*init_hw)(struct igc_hw *hw);
34 s32 (*setup_physical_interface)(struct igc_hw *hw);
35 void (*rar_set)(struct igc_hw *hw, u8 *address, u32 index);
36 s32 (*read_mac_addr)(struct igc_hw *hw);
37 s32 (*get_speed_and_duplex)(struct igc_hw *hw, u16 *speed,
39 s32 (*acquire_swfw_sync)(struct igc_hw *hw, u16 mask);
40 void (*release_swfw_sync)(struct igc_hw *hw, u16 mask);
46 igc_num_macs /* List is 1-based, so subtract 1 for true count. */
56 igc_media_type_unknown = 0,
57 igc_media_type_copper = 1,
69 s32 (*get_invariants)(struct igc_hw *hw);
70 struct igc_mac_operations *mac_ops;
71 const struct igc_phy_operations *phy_ops;
72 struct igc_nvm_operations *nvm_ops;
75 extern const struct igc_info igc_base_info;
78 struct igc_mac_operations ops;
81 u8 perm_addr[ETH_ALEN];
83 enum igc_mac_type type;
90 u32 mta_shadow[MAX_MTA_REG];
93 u8 forced_speed_duplex;
95 bool asf_firmware_present;
96 bool arc_subsystem_valid;
100 bool get_link_status;
103 struct igc_nvm_operations {
104 s32 (*acquire)(struct igc_hw *hw);
105 s32 (*read)(struct igc_hw *hw, u16 offset, u16 i, u16 *data);
106 void (*release)(struct igc_hw *hw);
107 s32 (*write)(struct igc_hw *hw, u16 offset, u16 i, u16 *data);
108 s32 (*update)(struct igc_hw *hw);
109 s32 (*validate)(struct igc_hw *hw);
110 s32 (*valid_led_default)(struct igc_hw *hw, u16 *data);
113 struct igc_phy_operations {
114 s32 (*acquire)(struct igc_hw *hw);
115 s32 (*check_reset_block)(struct igc_hw *hw);
116 s32 (*force_speed_duplex)(struct igc_hw *hw);
117 s32 (*get_phy_info)(struct igc_hw *hw);
118 s32 (*read_reg)(struct igc_hw *hw, u32 address, u16 *data);
119 void (*release)(struct igc_hw *hw);
120 s32 (*reset)(struct igc_hw *hw);
121 s32 (*write_reg)(struct igc_hw *hw, u32 address, u16 data);
124 struct igc_nvm_info {
125 struct igc_nvm_operations ops;
126 enum igc_nvm_type type;
138 struct igc_phy_info {
139 struct igc_phy_operations ops;
141 enum igc_phy_type type;
145 u32 reset_delay_us; /* in usec */
148 enum igc_media_type media_type;
150 u16 autoneg_advertised;
157 bool speed_downgraded;
158 bool autoneg_wait_to_complete;
161 struct igc_bus_info {
171 igc_fc_default = 0xFF
175 u32 high_water; /* Flow control high-water mark */
176 u32 low_water; /* Flow control low-water mark */
177 u16 pause_time; /* Flow control pause timer */
178 bool send_xon; /* Flow control send XON */
179 bool strict_ieee; /* Strict IEEE mode */
180 enum igc_fc_mode current_mode; /* Type of flow control */
181 enum igc_fc_mode requested_mode;
184 struct igc_dev_spec_base {
185 bool clear_semaphore_once;
193 unsigned long io_base;
195 struct igc_mac_info mac;
196 struct igc_fc_info fc;
197 struct igc_nvm_info nvm;
198 struct igc_phy_info phy;
200 struct igc_bus_info bus;
203 struct igc_dev_spec_base _base;
207 u16 subsystem_vendor_id;
208 u16 subsystem_device_id;
214 /* Statistics counters collected by the MAC */
215 struct igc_hw_stats {
286 struct net_device *igc_get_hw_dev(struct igc_hw *hw);
287 #define hw_dbg(format, arg...) \
288 netdev_dbg(igc_get_hw_dev(hw), format, ##arg)
290 s32 igc_read_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value);
291 s32 igc_write_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value);
292 void igc_read_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value);
293 void igc_write_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value);
295 #endif /* _IGC_HW_H_ */