1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018 Intel Corporation */
7 #include <linux/kobject.h>
9 #include <linux/netdevice.h>
10 #include <linux/vmalloc.h>
11 #include <linux/ethtool.h>
12 #include <linux/sctp.h>
13 #include <linux/ptp_clock_kernel.h>
14 #include <linux/timecounter.h>
15 #include <linux/net_tstamp.h>
16 #include <linux/bitfield.h>
20 void igc_ethtool_set_ops(struct net_device *);
22 /* Transmit and receive queues */
23 #define IGC_MAX_RX_QUEUES 4
24 #define IGC_MAX_TX_QUEUES 4
26 #define MAX_Q_VECTORS 8
27 #define MAX_STD_JUMBO_FRAME_SIZE 9216
29 #define MAX_ETYPE_FILTER 8
30 #define IGC_RETA_SIZE 128
34 #define IGC_N_PEROUT 2
37 #define MAX_FLEX_FILTER 32
39 enum igc_mac_filter_type {
40 IGC_MAC_FILTER_TYPE_DST = 0,
41 IGC_MAC_FILTER_TYPE_SRC
44 struct igc_tx_queue_stats {
51 struct igc_rx_queue_stats {
59 struct igc_rx_packet_stats {
60 u64 ipv4_packets; /* IPv4 headers processed */
61 u64 ipv4e_packets; /* IPv4E headers with extensions processed */
62 u64 ipv6_packets; /* IPv6 headers processed */
63 u64 ipv6e_packets; /* IPv6E headers with extensions processed */
64 u64 tcp_packets; /* TCP headers processed */
65 u64 udp_packets; /* UDP headers processed */
66 u64 sctp_packets; /* SCTP headers processed */
67 u64 nfs_packets; /* NFS headers processe */
71 struct igc_ring_container {
72 struct igc_ring *ring; /* pointer to linked list of rings */
73 unsigned int total_bytes; /* total bytes processed this int */
74 unsigned int total_packets; /* total packets processed this int */
75 u16 work_limit; /* total work allowed per interrupt */
76 u8 count; /* total number of rings in vector */
77 u8 itr; /* current ITR setting for ring */
81 struct igc_q_vector *q_vector; /* backlink to q_vector */
82 struct net_device *netdev; /* back pointer to net_device */
83 struct device *dev; /* device for dma mapping */
84 union { /* array of buffer info structs */
85 struct igc_tx_buffer *tx_buffer_info;
86 struct igc_rx_buffer *rx_buffer_info;
88 void *desc; /* descriptor ring memory */
89 unsigned long flags; /* ring specific flags */
90 void __iomem *tail; /* pointer to ring tail register */
91 dma_addr_t dma; /* phys address of the ring */
92 unsigned int size; /* length of desc. ring in bytes */
94 u16 count; /* number of desc. in the ring */
95 u8 queue_index; /* logical index of the ring*/
96 u8 reg_idx; /* physical index of the ring */
97 bool launchtime_enable; /* true if LaunchTime is enabled */
98 ktime_t last_tx_cycle; /* end of the cycle with a launchtime transmission */
99 ktime_t last_ff_cycle; /* Last cycle with an active first flag */
106 bool cbs_enable; /* indicates if CBS is enabled */
107 s32 idleslope; /* idleSlope in kbps */
108 s32 sendslope; /* sendSlope in kbps */
109 s32 hicredit; /* hiCredit in bytes */
110 s32 locredit; /* loCredit in bytes */
112 /* everything past this point are written often */
120 struct igc_tx_queue_stats tx_stats;
121 struct u64_stats_sync tx_syncp;
122 struct u64_stats_sync tx_syncp2;
126 struct igc_rx_queue_stats rx_stats;
127 struct igc_rx_packet_stats pkt_stats;
128 struct u64_stats_sync rx_syncp;
133 struct xdp_rxq_info xdp_rxq;
134 struct xsk_buff_pool *xsk_pool;
135 } ____cacheline_internodealigned_in_smp;
137 /* Board specific private data structure */
139 struct net_device *netdev;
141 struct ethtool_eee eee;
146 unsigned int num_q_vectors;
148 struct msix_entry *msix_entries;
152 u32 tx_timeout_count;
154 struct igc_ring *tx_ring[IGC_MAX_TX_QUEUES];
158 struct igc_ring *rx_ring[IGC_MAX_RX_QUEUES];
160 struct timer_list watchdog_timer;
161 struct timer_list dma_err_timer;
162 struct timer_list phy_info_timer;
172 /* Interrupt Throttle Rate */
176 struct work_struct reset_task;
177 struct work_struct watchdog_task;
178 struct work_struct dma_err_task;
181 u8 tx_timeout_factor;
190 u32 qbv_config_change_errors;
192 /* OS defined structs */
193 struct pci_dev *pdev;
194 /* lock for statistics */
195 spinlock_t stats64_lock;
196 struct rtnl_link_stats64 stats64;
198 /* structs defined in igc_hw.h */
200 struct igc_hw_stats stats;
202 struct igc_q_vector *q_vector[MAX_Q_VECTORS];
203 u32 eims_enable_mask;
209 u32 tx_hwtstamp_timeouts;
210 u32 tx_hwtstamp_skipped;
211 u32 rx_hwtstamp_cleared;
214 u32 rss_indir_tbl_init;
216 /* Any access to elements in nfc_rule_list is protected by the
219 struct mutex nfc_rule_lock;
220 struct list_head nfc_rule_list;
221 unsigned int nfc_rule_count;
223 u8 rss_indir_tbl[IGC_RETA_SIZE];
225 unsigned long link_check_timeout;
230 struct ptp_clock *ptp_clock;
231 struct ptp_clock_info ptp_caps;
232 /* Access to ptp_tx_skb and ptp_tx_start are protected by the
235 spinlock_t ptp_tx_lock;
236 struct sk_buff *ptp_tx_skb;
237 struct hwtstamp_config tstamp_config;
238 unsigned long ptp_tx_start;
239 unsigned int ptp_flags;
240 /* System time value lock */
241 spinlock_t tmreg_lock;
242 struct cyclecounter cc;
243 struct timecounter tc;
244 struct timespec64 prev_ptp_time; /* Pre-reset PTP clock */
245 ktime_t ptp_reset_start; /* Reset time in clock mono */
246 struct system_time_snapshot snapshot;
250 struct bpf_prog *xdp_prog;
252 bool pps_sys_wrap_on;
254 struct ptp_pin_desc sdp_config[IGC_N_SDP];
256 struct timespec64 start;
257 struct timespec64 period;
258 } perout[IGC_N_PEROUT];
261 void igc_up(struct igc_adapter *adapter);
262 void igc_down(struct igc_adapter *adapter);
263 int igc_open(struct net_device *netdev);
264 int igc_close(struct net_device *netdev);
265 int igc_setup_tx_resources(struct igc_ring *ring);
266 int igc_setup_rx_resources(struct igc_ring *ring);
267 void igc_free_tx_resources(struct igc_ring *ring);
268 void igc_free_rx_resources(struct igc_ring *ring);
269 unsigned int igc_get_max_rss_queues(struct igc_adapter *adapter);
270 void igc_set_flag_queue_pairs(struct igc_adapter *adapter,
271 const u32 max_rss_queues);
272 int igc_reinit_queues(struct igc_adapter *adapter);
273 void igc_write_rss_indir_tbl(struct igc_adapter *adapter);
274 bool igc_has_link(struct igc_adapter *adapter);
275 void igc_reset(struct igc_adapter *adapter);
276 void igc_update_stats(struct igc_adapter *adapter);
277 void igc_disable_rx_ring(struct igc_ring *ring);
278 void igc_enable_rx_ring(struct igc_ring *ring);
279 void igc_disable_tx_ring(struct igc_ring *ring);
280 void igc_enable_tx_ring(struct igc_ring *ring);
281 int igc_xsk_wakeup(struct net_device *dev, u32 queue_id, u32 flags);
283 /* igc_dump declarations */
284 void igc_rings_dump(struct igc_adapter *adapter);
285 void igc_regs_dump(struct igc_adapter *adapter);
287 extern char igc_driver_name[];
289 #define IGC_REGS_LEN 740
291 /* flags controlling PTP/1588 function */
292 #define IGC_PTP_ENABLED BIT(0)
294 /* Flags definitions */
295 #define IGC_FLAG_HAS_MSI BIT(0)
296 #define IGC_FLAG_QUEUE_PAIRS BIT(3)
297 #define IGC_FLAG_DMAC BIT(4)
298 #define IGC_FLAG_PTP BIT(8)
299 #define IGC_FLAG_WOL_SUPPORTED BIT(8)
300 #define IGC_FLAG_NEED_LINK_UPDATE BIT(9)
301 #define IGC_FLAG_HAS_MSIX BIT(13)
302 #define IGC_FLAG_EEE BIT(14)
303 #define IGC_FLAG_VLAN_PROMISC BIT(15)
304 #define IGC_FLAG_RX_LEGACY BIT(16)
305 #define IGC_FLAG_TSN_QBV_ENABLED BIT(17)
306 #define IGC_FLAG_TSN_QAV_ENABLED BIT(18)
308 #define IGC_FLAG_TSN_ANY_ENABLED \
309 (IGC_FLAG_TSN_QBV_ENABLED | IGC_FLAG_TSN_QAV_ENABLED)
311 #define IGC_FLAG_RSS_FIELD_IPV4_UDP BIT(6)
312 #define IGC_FLAG_RSS_FIELD_IPV6_UDP BIT(7)
314 #define IGC_MRQC_ENABLE_RSS_MQ 0x00000002
315 #define IGC_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
316 #define IGC_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
318 /* RX-desc Write-Back format RSS Type's */
319 enum igc_rss_type_num {
320 IGC_RSS_TYPE_NO_HASH = 0,
321 IGC_RSS_TYPE_HASH_TCP_IPV4 = 1,
322 IGC_RSS_TYPE_HASH_IPV4 = 2,
323 IGC_RSS_TYPE_HASH_TCP_IPV6 = 3,
324 IGC_RSS_TYPE_HASH_IPV6_EX = 4,
325 IGC_RSS_TYPE_HASH_IPV6 = 5,
326 IGC_RSS_TYPE_HASH_TCP_IPV6_EX = 6,
327 IGC_RSS_TYPE_HASH_UDP_IPV4 = 7,
328 IGC_RSS_TYPE_HASH_UDP_IPV6 = 8,
329 IGC_RSS_TYPE_HASH_UDP_IPV6_EX = 9,
330 IGC_RSS_TYPE_MAX = 10,
332 #define IGC_RSS_TYPE_MAX_TABLE 16
333 #define IGC_RSS_TYPE_MASK GENMASK(3,0) /* 4-bits (3:0) = mask 0x0F */
335 /* igc_rss_type - Rx descriptor RSS type field */
336 static inline u32 igc_rss_type(const union igc_adv_rx_desc *rx_desc)
338 /* RSS Type 4-bits (3:0) number: 0-9 (above 9 is reserved)
339 * Accessing the same bits via u16 (wb.lower.lo_dword.hs_rss.pkt_info)
340 * is slightly slower than via u32 (wb.lower.lo_dword.data)
342 return le32_get_bits(rx_desc->wb.lower.lo_dword.data, IGC_RSS_TYPE_MASK);
345 /* Interrupt defines */
346 #define IGC_START_ITR 648 /* ~6000 ints/sec */
347 #define IGC_4K_ITR 980
348 #define IGC_20K_ITR 196
349 #define IGC_70K_ITR 56
351 #define IGC_DEFAULT_ITR 3 /* dynamic */
352 #define IGC_MAX_ITR_USECS 10000
353 #define IGC_MIN_ITR_USECS 10
354 #define NON_Q_VECTORS 1
355 #define MAX_MSIX_ENTRIES 10
357 /* TX/RX descriptor defines */
358 #define IGC_DEFAULT_TXD 256
359 #define IGC_DEFAULT_TX_WORK 128
360 #define IGC_MIN_TXD 80
361 #define IGC_MAX_TXD 4096
363 #define IGC_DEFAULT_RXD 256
364 #define IGC_MIN_RXD 80
365 #define IGC_MAX_RXD 4096
367 /* Supported Rx Buffer Sizes */
368 #define IGC_RXBUFFER_256 256
369 #define IGC_RXBUFFER_2048 2048
370 #define IGC_RXBUFFER_3072 3072
372 #define AUTO_ALL_MODES 0
373 #define IGC_RX_HDR_LEN IGC_RXBUFFER_256
375 /* Transmit and receive latency (for PTP timestamps) */
376 #define IGC_I225_TX_LATENCY_10 240
377 #define IGC_I225_TX_LATENCY_100 58
378 #define IGC_I225_TX_LATENCY_1000 80
379 #define IGC_I225_TX_LATENCY_2500 1325
380 #define IGC_I225_RX_LATENCY_10 6450
381 #define IGC_I225_RX_LATENCY_100 185
382 #define IGC_I225_RX_LATENCY_1000 300
383 #define IGC_I225_RX_LATENCY_2500 1485
385 /* RX and TX descriptor control thresholds.
386 * PTHRESH - MAC will consider prefetch if it has fewer than this number of
387 * descriptors available in its onboard memory.
388 * Setting this to 0 disables RX descriptor prefetch.
389 * HTHRESH - MAC will only prefetch if there are at least this many descriptors
390 * available in host memory.
391 * If PTHRESH is 0, this should also be 0.
392 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
393 * descriptors until either it has this many to write back, or the
396 #define IGC_RX_PTHRESH 8
397 #define IGC_RX_HTHRESH 8
398 #define IGC_TX_PTHRESH 8
399 #define IGC_TX_HTHRESH 1
400 #define IGC_RX_WTHRESH 4
401 #define IGC_TX_WTHRESH 16
403 #define IGC_RX_DMA_ATTR \
404 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
406 #define IGC_TS_HDR_LEN 16
408 #define IGC_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN)
410 #if (PAGE_SIZE < 8192)
411 #define IGC_MAX_FRAME_BUILD_SKB \
412 (SKB_WITH_OVERHEAD(IGC_RXBUFFER_2048) - IGC_SKB_PAD - IGC_TS_HDR_LEN)
414 #define IGC_MAX_FRAME_BUILD_SKB (IGC_RXBUFFER_2048 - IGC_TS_HDR_LEN)
417 /* How many Rx Buffers do we bundle into one write to the hardware ? */
418 #define IGC_RX_BUFFER_WRITE 16 /* Must be power of 2 */
421 #define IGC_TX_FLAGS_VLAN_MASK 0xffff0000
422 #define IGC_TX_FLAGS_VLAN_SHIFT 16
424 /* igc_test_staterr - tests bits within Rx descriptor status and error fields */
425 static inline __le32 igc_test_staterr(union igc_adv_rx_desc *rx_desc,
426 const u32 stat_err_bits)
428 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
439 IGC_TX_FLAGS_VLAN = 0x01,
440 IGC_TX_FLAGS_TSO = 0x02,
441 IGC_TX_FLAGS_TSTAMP = 0x04,
444 IGC_TX_FLAGS_IPV4 = 0x10,
445 IGC_TX_FLAGS_CSUM = 0x20,
452 /* The largest size we can write to the descriptor is 65535. In order to
453 * maintain a power of two alignment we have to limit ourselves to 32K.
455 #define IGC_MAX_TXD_PWR 15
456 #define IGC_MAX_DATA_PER_TXD BIT(IGC_MAX_TXD_PWR)
458 /* Tx Descriptors needed, worst case */
459 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGC_MAX_DATA_PER_TXD)
460 #define DESC_NEEDED (MAX_SKB_FRAGS + 4)
462 enum igc_tx_buffer_type {
463 IGC_TX_BUFFER_TYPE_SKB,
464 IGC_TX_BUFFER_TYPE_XDP,
465 IGC_TX_BUFFER_TYPE_XSK,
468 /* wrapper around a pointer to a socket buffer,
469 * so a DMA handle can be stored along with the buffer
471 struct igc_tx_buffer {
472 union igc_adv_tx_desc *next_to_watch;
473 unsigned long time_stamp;
474 enum igc_tx_buffer_type type;
477 struct xdp_frame *xdpf;
479 unsigned int bytecount;
483 DEFINE_DMA_UNMAP_ADDR(dma);
484 DEFINE_DMA_UNMAP_LEN(len);
488 struct igc_rx_buffer {
493 #if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536)
500 struct xdp_buff *xdp;
504 /* context wrapper around xdp_buff to provide access to descriptor metadata */
505 struct igc_xdp_buff {
507 union igc_adv_rx_desc *rx_desc;
508 ktime_t rx_ts; /* data indication bit IGC_RXDADV_STAT_TSIP */
511 struct igc_q_vector {
512 struct igc_adapter *adapter; /* backlink */
513 void __iomem *itr_register;
514 u32 eims_value; /* EIMS mask value */
519 struct igc_ring_container rx, tx;
521 struct napi_struct napi;
523 struct rcu_head rcu; /* to avoid race with update stats on free */
524 char name[IFNAMSIZ + 9];
525 struct net_device poll_dev;
527 /* for dynamic allocation of rings associated with this q_vector */
528 struct igc_ring ring[] ____cacheline_internodealigned_in_smp;
531 enum igc_filter_match_flags {
532 IGC_FILTER_FLAG_ETHER_TYPE = BIT(0),
533 IGC_FILTER_FLAG_VLAN_TCI = BIT(1),
534 IGC_FILTER_FLAG_SRC_MAC_ADDR = BIT(2),
535 IGC_FILTER_FLAG_DST_MAC_ADDR = BIT(3),
536 IGC_FILTER_FLAG_USER_DATA = BIT(4),
537 IGC_FILTER_FLAG_VLAN_ETYPE = BIT(5),
540 struct igc_nfc_filter {
545 u8 src_addr[ETH_ALEN];
546 u8 dst_addr[ETH_ALEN];
556 struct igc_nfc_rule {
557 struct list_head list;
558 struct igc_nfc_filter filter;
564 /* IGC supports a total of 32 NFC rules: 16 MAC address based, 8 VLAN priority
565 * based, 8 ethertype based and 32 Flex filter based rules.
567 #define IGC_MAX_RXNFC_RULES 64
569 struct igc_flex_filter {
580 /* igc_desc_unused - calculate if we have unused descriptors */
581 static inline u16 igc_desc_unused(const struct igc_ring *ring)
583 u16 ntc = ring->next_to_clean;
584 u16 ntu = ring->next_to_use;
586 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
589 static inline s32 igc_get_phy_info(struct igc_hw *hw)
591 if (hw->phy.ops.get_phy_info)
592 return hw->phy.ops.get_phy_info(hw);
597 static inline s32 igc_reset_phy(struct igc_hw *hw)
599 if (hw->phy.ops.reset)
600 return hw->phy.ops.reset(hw);
605 static inline struct netdev_queue *txring_txq(const struct igc_ring *tx_ring)
607 return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index);
610 enum igc_ring_flags_t {
611 IGC_RING_FLAG_RX_3K_BUFFER,
612 IGC_RING_FLAG_RX_BUILD_SKB_ENABLED,
613 IGC_RING_FLAG_RX_SCTP_CSUM,
614 IGC_RING_FLAG_RX_LB_VLAN_BSWAP,
615 IGC_RING_FLAG_TX_CTX_IDX,
616 IGC_RING_FLAG_TX_DETECT_HANG,
617 IGC_RING_FLAG_AF_XDP_ZC,
618 IGC_RING_FLAG_TX_HWTSTAMP,
621 #define ring_uses_large_buffer(ring) \
622 test_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
623 #define set_ring_uses_large_buffer(ring) \
624 set_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
625 #define clear_ring_uses_large_buffer(ring) \
626 clear_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
628 #define ring_uses_build_skb(ring) \
629 test_bit(IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags)
631 static inline unsigned int igc_rx_bufsz(struct igc_ring *ring)
633 #if (PAGE_SIZE < 8192)
634 if (ring_uses_large_buffer(ring))
635 return IGC_RXBUFFER_3072;
637 if (ring_uses_build_skb(ring))
638 return IGC_MAX_FRAME_BUILD_SKB + IGC_TS_HDR_LEN;
640 return IGC_RXBUFFER_2048;
643 static inline unsigned int igc_rx_pg_order(struct igc_ring *ring)
645 #if (PAGE_SIZE < 8192)
646 if (ring_uses_large_buffer(ring))
652 static inline s32 igc_read_phy_reg(struct igc_hw *hw, u32 offset, u16 *data)
654 if (hw->phy.ops.read_reg)
655 return hw->phy.ops.read_reg(hw, offset, data);
660 void igc_reinit_locked(struct igc_adapter *);
661 struct igc_nfc_rule *igc_get_nfc_rule(struct igc_adapter *adapter,
663 int igc_add_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule);
664 void igc_del_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule);
666 void igc_ptp_init(struct igc_adapter *adapter);
667 void igc_ptp_reset(struct igc_adapter *adapter);
668 void igc_ptp_suspend(struct igc_adapter *adapter);
669 void igc_ptp_stop(struct igc_adapter *adapter);
670 ktime_t igc_ptp_rx_pktstamp(struct igc_adapter *adapter, __le32 *buf);
671 int igc_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr);
672 int igc_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr);
673 void igc_ptp_tx_hang(struct igc_adapter *adapter);
674 void igc_ptp_read(struct igc_adapter *adapter, struct timespec64 *ts);
675 void igc_ptp_tx_tstamp_event(struct igc_adapter *adapter);
677 #define igc_rx_pg_size(_ring) (PAGE_SIZE << igc_rx_pg_order(_ring))
679 #define IGC_TXD_DCMD (IGC_ADVTXD_DCMD_EOP | IGC_ADVTXD_DCMD_RS)
681 #define IGC_RX_DESC(R, i) \
682 (&(((union igc_adv_rx_desc *)((R)->desc))[i]))
683 #define IGC_TX_DESC(R, i) \
684 (&(((union igc_adv_tx_desc *)((R)->desc))[i]))
685 #define IGC_TX_CTXTDESC(R, i) \
686 (&(((struct igc_adv_tx_context_desc *)((R)->desc))[i]))