1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018 Intel Corporation */
7 #include <linux/kobject.h>
9 #include <linux/netdevice.h>
10 #include <linux/vmalloc.h>
11 #include <linux/ethtool.h>
12 #include <linux/sctp.h>
13 #include <linux/ptp_clock_kernel.h>
14 #include <linux/timecounter.h>
15 #include <linux/net_tstamp.h>
19 void igc_ethtool_set_ops(struct net_device *);
21 /* Transmit and receive queues */
22 #define IGC_MAX_RX_QUEUES 4
23 #define IGC_MAX_TX_QUEUES 4
25 #define MAX_Q_VECTORS 8
26 #define MAX_STD_JUMBO_FRAME_SIZE 9216
28 #define MAX_ETYPE_FILTER 8
29 #define IGC_RETA_SIZE 128
31 enum igc_mac_filter_type {
32 IGC_MAC_FILTER_TYPE_DST = 0,
33 IGC_MAC_FILTER_TYPE_SRC
36 struct igc_tx_queue_stats {
43 struct igc_rx_queue_stats {
51 struct igc_rx_packet_stats {
52 u64 ipv4_packets; /* IPv4 headers processed */
53 u64 ipv4e_packets; /* IPv4E headers with extensions processed */
54 u64 ipv6_packets; /* IPv6 headers processed */
55 u64 ipv6e_packets; /* IPv6E headers with extensions processed */
56 u64 tcp_packets; /* TCP headers processed */
57 u64 udp_packets; /* UDP headers processed */
58 u64 sctp_packets; /* SCTP headers processed */
59 u64 nfs_packets; /* NFS headers processe */
63 struct igc_ring_container {
64 struct igc_ring *ring; /* pointer to linked list of rings */
65 unsigned int total_bytes; /* total bytes processed this int */
66 unsigned int total_packets; /* total packets processed this int */
67 u16 work_limit; /* total work allowed per interrupt */
68 u8 count; /* total number of rings in vector */
69 u8 itr; /* current ITR setting for ring */
73 struct igc_q_vector *q_vector; /* backlink to q_vector */
74 struct net_device *netdev; /* back pointer to net_device */
75 struct device *dev; /* device for dma mapping */
76 union { /* array of buffer info structs */
77 struct igc_tx_buffer *tx_buffer_info;
78 struct igc_rx_buffer *rx_buffer_info;
80 void *desc; /* descriptor ring memory */
81 unsigned long flags; /* ring specific flags */
82 void __iomem *tail; /* pointer to ring tail register */
83 dma_addr_t dma; /* phys address of the ring */
84 unsigned int size; /* length of desc. ring in bytes */
86 u16 count; /* number of desc. in the ring */
87 u8 queue_index; /* logical index of the ring*/
88 u8 reg_idx; /* physical index of the ring */
89 bool launchtime_enable; /* true if LaunchTime is enabled */
94 /* everything past this point are written often */
102 struct igc_tx_queue_stats tx_stats;
103 struct u64_stats_sync tx_syncp;
104 struct u64_stats_sync tx_syncp2;
108 struct igc_rx_queue_stats rx_stats;
109 struct igc_rx_packet_stats pkt_stats;
110 struct u64_stats_sync rx_syncp;
114 } ____cacheline_internodealigned_in_smp;
116 /* Board specific private data structure */
118 struct net_device *netdev;
120 struct ethtool_eee eee;
125 unsigned int num_q_vectors;
127 struct msix_entry *msix_entries;
131 u32 tx_timeout_count;
133 struct igc_ring *tx_ring[IGC_MAX_TX_QUEUES];
137 struct igc_ring *rx_ring[IGC_MAX_RX_QUEUES];
139 struct timer_list watchdog_timer;
140 struct timer_list dma_err_timer;
141 struct timer_list phy_info_timer;
151 /* Interrupt Throttle Rate */
155 struct work_struct reset_task;
156 struct work_struct watchdog_task;
157 struct work_struct dma_err_task;
160 u8 tx_timeout_factor;
169 /* OS defined structs */
170 struct pci_dev *pdev;
171 /* lock for statistics */
172 spinlock_t stats64_lock;
173 struct rtnl_link_stats64 stats64;
175 /* structs defined in igc_hw.h */
177 struct igc_hw_stats stats;
179 struct igc_q_vector *q_vector[MAX_Q_VECTORS];
180 u32 eims_enable_mask;
186 u32 tx_hwtstamp_timeouts;
187 u32 tx_hwtstamp_skipped;
188 u32 rx_hwtstamp_cleared;
191 u32 rss_indir_tbl_init;
193 /* Any access to elements in nfc_rule_list is protected by the
196 struct mutex nfc_rule_lock;
197 struct list_head nfc_rule_list;
198 unsigned int nfc_rule_count;
200 u8 rss_indir_tbl[IGC_RETA_SIZE];
202 unsigned long link_check_timeout;
207 struct ptp_clock *ptp_clock;
208 struct ptp_clock_info ptp_caps;
209 struct work_struct ptp_tx_work;
210 struct sk_buff *ptp_tx_skb;
211 struct hwtstamp_config tstamp_config;
212 unsigned long ptp_tx_start;
213 unsigned int ptp_flags;
214 /* System time value lock */
215 spinlock_t tmreg_lock;
216 struct cyclecounter cc;
217 struct timecounter tc;
220 void igc_up(struct igc_adapter *adapter);
221 void igc_down(struct igc_adapter *adapter);
222 int igc_open(struct net_device *netdev);
223 int igc_close(struct net_device *netdev);
224 int igc_setup_tx_resources(struct igc_ring *ring);
225 int igc_setup_rx_resources(struct igc_ring *ring);
226 void igc_free_tx_resources(struct igc_ring *ring);
227 void igc_free_rx_resources(struct igc_ring *ring);
228 unsigned int igc_get_max_rss_queues(struct igc_adapter *adapter);
229 void igc_set_flag_queue_pairs(struct igc_adapter *adapter,
230 const u32 max_rss_queues);
231 int igc_reinit_queues(struct igc_adapter *adapter);
232 void igc_write_rss_indir_tbl(struct igc_adapter *adapter);
233 bool igc_has_link(struct igc_adapter *adapter);
234 void igc_reset(struct igc_adapter *adapter);
235 int igc_set_spd_dplx(struct igc_adapter *adapter, u32 spd, u8 dplx);
236 void igc_update_stats(struct igc_adapter *adapter);
238 /* igc_dump declarations */
239 void igc_rings_dump(struct igc_adapter *adapter);
240 void igc_regs_dump(struct igc_adapter *adapter);
242 extern char igc_driver_name[];
244 #define IGC_REGS_LEN 740
246 /* flags controlling PTP/1588 function */
247 #define IGC_PTP_ENABLED BIT(0)
249 /* Flags definitions */
250 #define IGC_FLAG_HAS_MSI BIT(0)
251 #define IGC_FLAG_QUEUE_PAIRS BIT(3)
252 #define IGC_FLAG_DMAC BIT(4)
253 #define IGC_FLAG_PTP BIT(8)
254 #define IGC_FLAG_WOL_SUPPORTED BIT(8)
255 #define IGC_FLAG_NEED_LINK_UPDATE BIT(9)
256 #define IGC_FLAG_MEDIA_RESET BIT(10)
257 #define IGC_FLAG_MAS_ENABLE BIT(12)
258 #define IGC_FLAG_HAS_MSIX BIT(13)
259 #define IGC_FLAG_EEE BIT(14)
260 #define IGC_FLAG_VLAN_PROMISC BIT(15)
261 #define IGC_FLAG_RX_LEGACY BIT(16)
262 #define IGC_FLAG_TSN_QBV_ENABLED BIT(17)
264 #define IGC_FLAG_RSS_FIELD_IPV4_UDP BIT(6)
265 #define IGC_FLAG_RSS_FIELD_IPV6_UDP BIT(7)
267 #define IGC_MRQC_ENABLE_RSS_MQ 0x00000002
268 #define IGC_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
269 #define IGC_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
271 /* Interrupt defines */
272 #define IGC_START_ITR 648 /* ~6000 ints/sec */
273 #define IGC_4K_ITR 980
274 #define IGC_20K_ITR 196
275 #define IGC_70K_ITR 56
277 #define IGC_DEFAULT_ITR 3 /* dynamic */
278 #define IGC_MAX_ITR_USECS 10000
279 #define IGC_MIN_ITR_USECS 10
280 #define NON_Q_VECTORS 1
281 #define MAX_MSIX_ENTRIES 10
283 /* TX/RX descriptor defines */
284 #define IGC_DEFAULT_TXD 256
285 #define IGC_DEFAULT_TX_WORK 128
286 #define IGC_MIN_TXD 80
287 #define IGC_MAX_TXD 4096
289 #define IGC_DEFAULT_RXD 256
290 #define IGC_MIN_RXD 80
291 #define IGC_MAX_RXD 4096
293 /* Supported Rx Buffer Sizes */
294 #define IGC_RXBUFFER_256 256
295 #define IGC_RXBUFFER_2048 2048
296 #define IGC_RXBUFFER_3072 3072
298 #define AUTO_ALL_MODES 0
299 #define IGC_RX_HDR_LEN IGC_RXBUFFER_256
301 /* Transmit and receive latency (for PTP timestamps) */
302 #define IGC_I225_TX_LATENCY_10 240
303 #define IGC_I225_TX_LATENCY_100 58
304 #define IGC_I225_TX_LATENCY_1000 80
305 #define IGC_I225_TX_LATENCY_2500 1325
306 #define IGC_I225_RX_LATENCY_10 6450
307 #define IGC_I225_RX_LATENCY_100 185
308 #define IGC_I225_RX_LATENCY_1000 300
309 #define IGC_I225_RX_LATENCY_2500 1485
311 /* RX and TX descriptor control thresholds.
312 * PTHRESH - MAC will consider prefetch if it has fewer than this number of
313 * descriptors available in its onboard memory.
314 * Setting this to 0 disables RX descriptor prefetch.
315 * HTHRESH - MAC will only prefetch if there are at least this many descriptors
316 * available in host memory.
317 * If PTHRESH is 0, this should also be 0.
318 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
319 * descriptors until either it has this many to write back, or the
322 #define IGC_RX_PTHRESH 8
323 #define IGC_RX_HTHRESH 8
324 #define IGC_TX_PTHRESH 8
325 #define IGC_TX_HTHRESH 1
326 #define IGC_RX_WTHRESH 4
327 #define IGC_TX_WTHRESH 16
329 #define IGC_RX_DMA_ATTR \
330 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
332 #define IGC_TS_HDR_LEN 16
334 #define IGC_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN)
336 #if (PAGE_SIZE < 8192)
337 #define IGC_MAX_FRAME_BUILD_SKB \
338 (SKB_WITH_OVERHEAD(IGC_RXBUFFER_2048) - IGC_SKB_PAD - IGC_TS_HDR_LEN)
340 #define IGC_MAX_FRAME_BUILD_SKB (IGC_RXBUFFER_2048 - IGC_TS_HDR_LEN)
343 /* How many Rx Buffers do we bundle into one write to the hardware ? */
344 #define IGC_RX_BUFFER_WRITE 16 /* Must be power of 2 */
347 #define IGC_TX_FLAGS_VLAN_MASK 0xffff0000
349 /* igc_test_staterr - tests bits within Rx descriptor status and error fields */
350 static inline __le32 igc_test_staterr(union igc_adv_rx_desc *rx_desc,
351 const u32 stat_err_bits)
353 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
360 __IGC_PTP_TX_IN_PROGRESS,
365 IGC_TX_FLAGS_VLAN = 0x01,
366 IGC_TX_FLAGS_TSO = 0x02,
367 IGC_TX_FLAGS_TSTAMP = 0x04,
370 IGC_TX_FLAGS_IPV4 = 0x10,
371 IGC_TX_FLAGS_CSUM = 0x20,
378 /* The largest size we can write to the descriptor is 65535. In order to
379 * maintain a power of two alignment we have to limit ourselves to 32K.
381 #define IGC_MAX_TXD_PWR 15
382 #define IGC_MAX_DATA_PER_TXD BIT(IGC_MAX_TXD_PWR)
384 /* Tx Descriptors needed, worst case */
385 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGC_MAX_DATA_PER_TXD)
386 #define DESC_NEEDED (MAX_SKB_FRAGS + 4)
388 /* wrapper around a pointer to a socket buffer,
389 * so a DMA handle can be stored along with the buffer
391 struct igc_tx_buffer {
392 union igc_adv_tx_desc *next_to_watch;
393 unsigned long time_stamp;
395 unsigned int bytecount;
399 DEFINE_DMA_UNMAP_ADDR(dma);
400 DEFINE_DMA_UNMAP_LEN(len);
404 struct igc_rx_buffer {
407 #if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536)
415 struct igc_q_vector {
416 struct igc_adapter *adapter; /* backlink */
417 void __iomem *itr_register;
418 u32 eims_value; /* EIMS mask value */
423 struct igc_ring_container rx, tx;
425 struct napi_struct napi;
427 struct rcu_head rcu; /* to avoid race with update stats on free */
428 char name[IFNAMSIZ + 9];
429 struct net_device poll_dev;
431 /* for dynamic allocation of rings associated with this q_vector */
432 struct igc_ring ring[] ____cacheline_internodealigned_in_smp;
435 enum igc_filter_match_flags {
436 IGC_FILTER_FLAG_ETHER_TYPE = 0x1,
437 IGC_FILTER_FLAG_VLAN_TCI = 0x2,
438 IGC_FILTER_FLAG_SRC_MAC_ADDR = 0x4,
439 IGC_FILTER_FLAG_DST_MAC_ADDR = 0x8,
442 struct igc_nfc_filter {
446 u8 src_addr[ETH_ALEN];
447 u8 dst_addr[ETH_ALEN];
450 struct igc_nfc_rule {
451 struct list_head list;
452 struct igc_nfc_filter filter;
457 /* IGC supports a total of 32 NFC rules: 16 MAC address based,, 8 VLAN priority
458 * based, and 8 ethertype based.
460 #define IGC_MAX_RXNFC_RULES 32
462 /* igc_desc_unused - calculate if we have unused descriptors */
463 static inline u16 igc_desc_unused(const struct igc_ring *ring)
465 u16 ntc = ring->next_to_clean;
466 u16 ntu = ring->next_to_use;
468 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
471 static inline s32 igc_get_phy_info(struct igc_hw *hw)
473 if (hw->phy.ops.get_phy_info)
474 return hw->phy.ops.get_phy_info(hw);
479 static inline s32 igc_reset_phy(struct igc_hw *hw)
481 if (hw->phy.ops.reset)
482 return hw->phy.ops.reset(hw);
487 static inline struct netdev_queue *txring_txq(const struct igc_ring *tx_ring)
489 return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index);
492 enum igc_ring_flags_t {
493 IGC_RING_FLAG_RX_3K_BUFFER,
494 IGC_RING_FLAG_RX_BUILD_SKB_ENABLED,
495 IGC_RING_FLAG_RX_SCTP_CSUM,
496 IGC_RING_FLAG_RX_LB_VLAN_BSWAP,
497 IGC_RING_FLAG_TX_CTX_IDX,
498 IGC_RING_FLAG_TX_DETECT_HANG
501 #define ring_uses_large_buffer(ring) \
502 test_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
504 #define ring_uses_build_skb(ring) \
505 test_bit(IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags)
507 static inline unsigned int igc_rx_bufsz(struct igc_ring *ring)
509 #if (PAGE_SIZE < 8192)
510 if (ring_uses_large_buffer(ring))
511 return IGC_RXBUFFER_3072;
513 if (ring_uses_build_skb(ring))
514 return IGC_MAX_FRAME_BUILD_SKB + IGC_TS_HDR_LEN;
516 return IGC_RXBUFFER_2048;
519 static inline unsigned int igc_rx_pg_order(struct igc_ring *ring)
521 #if (PAGE_SIZE < 8192)
522 if (ring_uses_large_buffer(ring))
528 static inline s32 igc_read_phy_reg(struct igc_hw *hw, u32 offset, u16 *data)
530 if (hw->phy.ops.read_reg)
531 return hw->phy.ops.read_reg(hw, offset, data);
536 void igc_reinit_locked(struct igc_adapter *);
537 struct igc_nfc_rule *igc_get_nfc_rule(struct igc_adapter *adapter,
539 int igc_add_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule);
540 void igc_del_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule);
542 void igc_ptp_init(struct igc_adapter *adapter);
543 void igc_ptp_reset(struct igc_adapter *adapter);
544 void igc_ptp_suspend(struct igc_adapter *adapter);
545 void igc_ptp_stop(struct igc_adapter *adapter);
546 void igc_ptp_rx_pktstamp(struct igc_q_vector *q_vector, void *va,
547 struct sk_buff *skb);
548 int igc_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr);
549 int igc_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr);
550 void igc_ptp_tx_hang(struct igc_adapter *adapter);
552 #define igc_rx_pg_size(_ring) (PAGE_SIZE << igc_rx_pg_order(_ring))
554 #define IGC_TXD_DCMD (IGC_ADVTXD_DCMD_EOP | IGC_ADVTXD_DCMD_RS)
556 #define IGC_RX_DESC(R, i) \
557 (&(((union igc_adv_rx_desc *)((R)->desc))[i]))
558 #define IGC_TX_DESC(R, i) \
559 (&(((union igc_adv_tx_desc *)((R)->desc))[i]))
560 #define IGC_TX_CTXTDESC(R, i) \
561 (&(((struct igc_adv_tx_context_desc *)((R)->desc))[i]))