1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018, Intel Corporation. */
7 #define ICE_BYTES_PER_WORD 2
8 #define ICE_BYTES_PER_DWORD 4
10 #include "ice_status.h"
11 #include "ice_hw_autogen.h"
12 #include "ice_osdep.h"
13 #include "ice_controlq.h"
14 #include "ice_lan_tx_rx.h"
15 #include "ice_flex_type.h"
16 #include "ice_protocol_type.h"
18 static inline bool ice_is_tc_ena(unsigned long bitmap, u8 tc)
20 return test_bit(tc, &bitmap);
23 static inline u64 round_up_64bit(u64 a, u32 b)
25 return div64_long(((a) + (b) / 2), (b));
28 static inline u32 ice_round_to_num(u32 N, u32 R)
30 return ((((N) % (R)) < ((R) / 2)) ? (((N) / (R)) * (R)) :
31 ((((N) + (R) - 1) / (R)) * (R)));
34 /* Driver always calls main vsi_handle first */
35 #define ICE_MAIN_VSI_HANDLE 0
37 /* debug masks - set these bits in hw->debug_mask to control output */
38 #define ICE_DBG_INIT BIT_ULL(1)
39 #define ICE_DBG_FW_LOG BIT_ULL(3)
40 #define ICE_DBG_LINK BIT_ULL(4)
41 #define ICE_DBG_PHY BIT_ULL(5)
42 #define ICE_DBG_QCTX BIT_ULL(6)
43 #define ICE_DBG_NVM BIT_ULL(7)
44 #define ICE_DBG_LAN BIT_ULL(8)
45 #define ICE_DBG_FLOW BIT_ULL(9)
46 #define ICE_DBG_SW BIT_ULL(13)
47 #define ICE_DBG_SCHED BIT_ULL(14)
48 #define ICE_DBG_PKG BIT_ULL(16)
49 #define ICE_DBG_RES BIT_ULL(17)
50 #define ICE_DBG_AQ_MSG BIT_ULL(24)
51 #define ICE_DBG_AQ_DESC BIT_ULL(25)
52 #define ICE_DBG_AQ_DESC_BUF BIT_ULL(26)
53 #define ICE_DBG_AQ_CMD BIT_ULL(27)
54 #define ICE_DBG_USER BIT_ULL(31)
59 ICE_CHANGE_LOCK_RES_ID,
60 ICE_GLOBAL_CFG_LOCK_RES_ID
63 /* FW update timeout definitions are in milliseconds */
64 #define ICE_NVM_TIMEOUT 180000
65 #define ICE_CHANGE_LOCK_TIMEOUT 1000
66 #define ICE_GLOBAL_CFG_LOCK_TIMEOUT 3000
68 enum ice_aq_res_access_type {
73 struct ice_driver_ver {
90 enum ice_phy_cache_mode {
103 struct ice_phy_cache_mode_data {
105 enum ice_fec_mode curr_user_fec_req;
106 enum ice_fc_mode curr_user_fc_req;
107 u16 curr_user_speed_req;
111 enum ice_set_fc_aq_failures {
112 ICE_SET_FC_AQ_FAIL_NONE = 0,
113 ICE_SET_FC_AQ_FAIL_GET,
114 ICE_SET_FC_AQ_FAIL_SET,
115 ICE_SET_FC_AQ_FAIL_UPDATE
118 /* Various MAC types */
126 enum ice_media_type {
127 ICE_MEDIA_UNKNOWN = 0,
137 ICE_VSI_CTRL = 3, /* equates to ICE_VSI_PF with 1 queue pair */
141 struct ice_link_status {
142 /* Refer to ice_aq_phy_type for bits definition */
145 u8 topo_media_conflict;
149 u8 lse_ena; /* Link Status Event notification */
155 /* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of
156 * ice_aqc_get_phy_caps structure
158 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
161 /* Different reset sources for which a disable queue AQ call has to be made in
162 * order to clean the Tx scheduler as a part of the reset
164 enum ice_disq_rst_src {
170 /* PHY info such as phy_type, etc... */
171 struct ice_phy_info {
172 struct ice_link_status link_info;
173 struct ice_link_status link_info_old;
176 enum ice_media_type media_type;
178 /* Please refer to struct ice_aqc_get_link_status_data to get
179 * detail of enable bit in curr_user_speed_req
181 u16 curr_user_speed_req;
182 enum ice_fec_mode curr_user_fec_req;
183 enum ice_fc_mode curr_user_fc_req;
184 struct ice_aqc_set_phy_cfg_data curr_user_phy_cfg;
187 /* protocol enumeration for filters */
188 enum ice_fltr_ptype {
189 /* NONE - used for undef/error */
190 ICE_FLTR_PTYPE_NONF_NONE = 0,
191 ICE_FLTR_PTYPE_NONF_IPV4_UDP,
192 ICE_FLTR_PTYPE_NONF_IPV4_TCP,
193 ICE_FLTR_PTYPE_NONF_IPV4_SCTP,
194 ICE_FLTR_PTYPE_NONF_IPV4_OTHER,
195 ICE_FLTR_PTYPE_FRAG_IPV4,
196 ICE_FLTR_PTYPE_NONF_IPV6_UDP,
197 ICE_FLTR_PTYPE_NONF_IPV6_TCP,
198 ICE_FLTR_PTYPE_NONF_IPV6_SCTP,
199 ICE_FLTR_PTYPE_NONF_IPV6_OTHER,
204 ICE_FD_HW_SEG_NON_TUN = 0,
209 /* 2 VSI = 1 ICE_VSI_PF + 1 ICE_VSI_CTRL */
210 #define ICE_MAX_FDIR_VSI_PER_FILTER 2
212 struct ice_fd_hw_prof {
213 struct ice_flow_seg_info *fdir_seg[ICE_FD_HW_SEG_MAX];
215 u64 entry_h[ICE_MAX_FDIR_VSI_PER_FILTER][ICE_FD_HW_SEG_MAX];
216 u16 vsi_h[ICE_MAX_FDIR_VSI_PER_FILTER];
219 /* Common HW capabilities for SW use */
220 struct ice_hw_common_caps {
222 /* DCB capabilities */
223 u32 active_tc_bitmap;
227 u16 num_rxq; /* Number/Total Rx queues */
228 u16 rxq_first_id; /* First queue ID for Rx queues */
229 u16 num_txq; /* Number/Total Tx queues */
230 u16 txq_first_id; /* First queue ID for Tx queues */
233 u16 num_msix_vectors;
234 u16 msix_vector_first_id;
236 /* Max MTU for function or device */
239 /* Virtualization support */
240 u8 sr_iov_1_1; /* SR-IOV enabled */
242 /* RSS related capabilities */
243 u16 rss_table_size; /* 512 for PFs and 64 for VFs */
244 u8 rss_table_entry_width; /* RSS Entry width in bits */
248 bool nvm_update_pending_nvm;
249 bool nvm_update_pending_orom;
250 bool nvm_update_pending_netlist;
251 #define ICE_NVM_PENDING_NVM_IMAGE BIT(0)
252 #define ICE_NVM_PENDING_OROM BIT(1)
253 #define ICE_NVM_PENDING_NETLIST BIT(2)
254 bool nvm_unified_update;
255 #define ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT BIT(3)
258 /* Function specific capabilities */
259 struct ice_hw_func_caps {
260 struct ice_hw_common_caps common_cap;
261 u32 num_allocd_vfs; /* Number of allocated VFs */
262 u32 vf_base_id; /* Logical ID of the first VF */
264 u32 fd_fltr_guar; /* Number of filters guaranteed */
265 u32 fd_fltr_best_effort; /* Number of best effort filters */
268 /* Device wide capabilities */
269 struct ice_hw_dev_caps {
270 struct ice_hw_common_caps common_cap;
271 u32 num_vfs_exposed; /* Total number of VFs exposed */
272 u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */
273 u32 num_flow_director_fltr; /* Number of FD filters available */
278 struct ice_mac_info {
279 u8 lan_addr[ETH_ALEN];
280 u8 perm_addr[ETH_ALEN];
283 /* Reset types used to determine which kind of reset was requested. These
284 * defines match what the RESET_TYPE field of the GLGEN_RSTAT register.
285 * ICE_RESET_PFR does not match any RESET_TYPE field in the GLGEN_RSTAT register
286 * because its reset source is different than the other types listed.
298 struct ice_bus_info {
303 /* Flow control (FC) parameters */
305 enum ice_fc_mode current_mode; /* FC mode in effect */
306 enum ice_fc_mode req_mode; /* FC mode requested by caller */
309 /* Option ROM version information */
310 struct ice_orom_info {
311 u8 major; /* Major version of OROM */
312 u8 patch; /* Patch version of OROM */
313 u16 build; /* Build version of OROM */
316 /* NVM version information */
317 struct ice_nvm_info {
323 /* netlist version information */
324 struct ice_netlist_info {
325 u32 major; /* major high/low */
326 u32 minor; /* minor high/low */
327 u32 type; /* type high/low */
328 u32 rev; /* revision high/low */
329 u32 hash; /* SHA-1 hash word */
330 u16 cust_ver; /* customer version */
333 /* Enumeration of possible flash banks for the NVM, OROM, and Netlist modules
334 * of the flash image.
336 enum ice_flash_bank {
337 ICE_INVALID_FLASH_BANK,
342 /* information for accessing NVM, OROM, and Netlist flash banks */
343 struct ice_bank_info {
344 u32 nvm_ptr; /* Pointer to 1st NVM bank */
345 u32 nvm_size; /* Size of NVM bank */
346 u32 orom_ptr; /* Pointer to 1st OROM bank */
347 u32 orom_size; /* Size of OROM bank */
348 u32 netlist_ptr; /* Pointer to 1st Netlist bank */
349 u32 netlist_size; /* Size of Netlist bank */
350 enum ice_flash_bank nvm_bank; /* Active NVM bank */
351 enum ice_flash_bank orom_bank; /* Active OROM bank */
352 enum ice_flash_bank netlist_bank; /* Active Netlist bank */
355 /* Flash Chip Information */
356 struct ice_flash_info {
357 struct ice_orom_info orom; /* Option ROM version info */
358 struct ice_nvm_info nvm; /* NVM version information */
359 struct ice_netlist_info netlist;/* Netlist version info */
360 struct ice_bank_info banks; /* Flash Bank information */
361 u16 sr_words; /* Shadow RAM size in words */
362 u32 flash_size; /* Size of available flash in bytes */
363 u8 blank_nvm_mode; /* is NVM empty (no FW present) */
366 struct ice_link_default_override_tlv {
368 #define ICE_LINK_OVERRIDE_OPT_M 0x3F
369 #define ICE_LINK_OVERRIDE_STRICT_MODE BIT(0)
370 #define ICE_LINK_OVERRIDE_EPCT_DIS BIT(1)
371 #define ICE_LINK_OVERRIDE_PORT_DIS BIT(2)
372 #define ICE_LINK_OVERRIDE_EN BIT(3)
373 #define ICE_LINK_OVERRIDE_AUTO_LINK_DIS BIT(4)
374 #define ICE_LINK_OVERRIDE_EEE_EN BIT(5)
376 #define ICE_LINK_OVERRIDE_PHY_CFG_S 8
377 #define ICE_LINK_OVERRIDE_PHY_CFG_M (0xC3 << ICE_LINK_OVERRIDE_PHY_CFG_S)
378 #define ICE_LINK_OVERRIDE_PAUSE_M 0x3
379 #define ICE_LINK_OVERRIDE_LESM_EN BIT(6)
380 #define ICE_LINK_OVERRIDE_AUTO_FEC_EN BIT(7)
382 #define ICE_LINK_OVERRIDE_FEC_OPT_M 0xFF
388 #define ICE_NVM_VER_LEN 32
390 /* Max number of port to queue branches w.r.t topology */
391 #define ICE_MAX_TRAFFIC_CLASS 8
392 #define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS
394 #define ice_for_each_traffic_class(_i) \
395 for ((_i) = 0; (_i) < ICE_MAX_TRAFFIC_CLASS; (_i)++)
397 #define ICE_INVAL_TEID 0xFFFFFFFF
399 struct ice_sched_node {
400 struct ice_sched_node *parent;
401 struct ice_sched_node *sibling; /* next sibling in the same layer */
402 struct ice_sched_node **children;
403 struct ice_aqc_txsched_elem_data info;
404 u32 agg_id; /* aggregator group ID */
406 u8 in_use; /* suspended or in use */
407 u8 tx_sched_layer; /* Logical Layer (1-9) */
411 #define ICE_SCHED_NODE_OWNER_LAN 0
414 /* Access Macros for Tx Sched Elements data */
415 #define ICE_TXSCHED_GET_NODE_TEID(x) le32_to_cpu((x)->info.node_teid)
417 /* The aggregator type determines if identifier is for a VSI group,
418 * aggregator group, aggregator of queues, or queue group.
421 ICE_AGG_TYPE_UNKNOWN = 0,
423 ICE_AGG_TYPE_AGG, /* aggregator */
428 /* Rate limit types */
431 ICE_MIN_BW, /* for CIR profile */
432 ICE_MAX_BW, /* for EIR profile */
433 ICE_SHARED_BW /* for shared profile */
436 #define ICE_SCHED_MIN_BW 500 /* in Kbps */
437 #define ICE_SCHED_MAX_BW 100000000 /* in Kbps */
438 #define ICE_SCHED_DFLT_BW 0xFFFFFFFF /* unlimited */
439 #define ICE_SCHED_DFLT_RL_PROF_ID 0
440 #define ICE_SCHED_NO_SHARED_RL_PROF_ID 0xFFFF
441 #define ICE_SCHED_DFLT_BW_WT 4
442 #define ICE_SCHED_INVAL_PROF_ID 0xFFFF
443 #define ICE_SCHED_DFLT_BURST_SIZE (15 * 1024) /* in bytes (15k) */
445 /* Data structure for saving BW information */
453 ICE_BW_TYPE_CNT /* This must be last */
461 struct ice_bw_type_info {
462 DECLARE_BITMAP(bw_t_bitmap, ICE_BW_TYPE_CNT);
464 struct ice_bw cir_bw;
465 struct ice_bw eir_bw;
469 /* VSI queue context structure for given TC */
473 /* bw_t_info saves queue BW information */
474 struct ice_bw_type_info bw_t_info;
477 /* VSI type list entry to locate corresponding VSI/aggregator nodes */
478 struct ice_sched_vsi_info {
479 struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS];
480 struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS];
481 struct list_head list_entry;
482 u16 max_lanq[ICE_MAX_TRAFFIC_CLASS];
485 /* driver defines the policy */
486 struct ice_sched_tx_policy {
488 u8 max_num_lan_qs_per_tc[ICE_MAX_TRAFFIC_CLASS];
492 /* CEE or IEEE 802.1Qaz ETS Configuration data */
493 struct ice_dcb_ets_cfg {
497 u8 prio_table[ICE_MAX_TRAFFIC_CLASS];
498 u8 tcbwtable[ICE_MAX_TRAFFIC_CLASS];
499 u8 tsatable[ICE_MAX_TRAFFIC_CLASS];
502 /* CEE or IEEE 802.1Qaz PFC Configuration data */
503 struct ice_dcb_pfc_cfg {
510 /* CEE or IEEE 802.1Qaz Application Priority data */
511 struct ice_dcb_app_priority_table {
517 #define ICE_MAX_USER_PRIORITY 8
518 #define ICE_DCBX_MAX_APPS 32
519 #define ICE_LLDPDU_SIZE 1500
520 #define ICE_TLV_STATUS_OPER 0x1
521 #define ICE_TLV_STATUS_SYNC 0x2
522 #define ICE_TLV_STATUS_ERR 0x4
523 #define ICE_APP_PROT_ID_FCOE 0x8906
524 #define ICE_APP_PROT_ID_ISCSI 0x0cbc
525 #define ICE_APP_PROT_ID_FIP 0x8914
526 #define ICE_APP_SEL_ETHTYPE 0x1
527 #define ICE_APP_SEL_TCPIP 0x2
528 #define ICE_CEE_APP_SEL_ETHTYPE 0x0
529 #define ICE_SR_LINK_DEFAULT_OVERRIDE_PTR 0x134
530 #define ICE_CEE_APP_SEL_TCPIP 0x1
532 struct ice_dcbx_cfg {
534 u32 tlv_status; /* CEE mode TLV status */
535 struct ice_dcb_ets_cfg etscfg;
536 struct ice_dcb_ets_cfg etsrec;
537 struct ice_dcb_pfc_cfg pfc;
538 struct ice_dcb_app_priority_table app[ICE_DCBX_MAX_APPS];
540 #define ICE_DCBX_MODE_CEE 0x1
541 #define ICE_DCBX_MODE_IEEE 0x2
543 #define ICE_DCBX_APPS_NON_WILLING 0x1
546 struct ice_port_info {
547 struct ice_sched_node *root; /* Root Node per Port */
548 struct ice_hw *hw; /* back pointer to HW instance */
549 u32 last_node_teid; /* scheduler last node info */
550 u16 sw_id; /* Initial switch ID belongs to port */
553 #define ICE_SCHED_PORT_STATE_INIT 0x0
554 #define ICE_SCHED_PORT_STATE_READY 0x1
556 #define ICE_LPORT_MASK 0xff
557 u16 dflt_tx_vsi_rule_id;
559 u16 dflt_rx_vsi_rule_id;
561 struct ice_fc_info fc;
562 struct ice_mac_info mac;
563 struct ice_phy_info phy;
564 struct mutex sched_lock; /* protect access to TXSched tree */
565 struct ice_sched_node *
566 sib_head[ICE_MAX_TRAFFIC_CLASS][ICE_AQC_TOPO_MAX_LEVEL_NUM];
567 /* List contain profile ID(s) and other params per layer */
568 struct list_head rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM];
569 struct ice_dcbx_cfg local_dcbx_cfg; /* Oper/Local Cfg */
571 struct ice_dcbx_cfg remote_dcbx_cfg; /* Peer Cfg */
572 struct ice_dcbx_cfg desired_dcbx_cfg; /* CEE Desired Cfg */
573 /* LLDP/DCBX Status */
574 u8 dcbx_status:3; /* see ICE_DCBX_STATUS_DIS */
579 struct ice_switch_info {
580 struct list_head vsi_list_map_head;
581 struct ice_sw_recipe *recp_list;
584 /* FW logging configuration */
585 struct ice_fw_log_evnt {
586 u8 cfg : 4; /* New event enables to configure */
587 u8 cur : 4; /* Current/active event enables */
590 struct ice_fw_log_cfg {
591 u8 cq_en : 1; /* FW logging is enabled via the control queue */
592 u8 uart_en : 1; /* FW logging is enabled via UART for all PFs */
593 u8 actv_evnts; /* Cumulation of currently enabled log events */
595 #define ICE_FW_LOG_EVNT_INFO (ICE_AQC_FW_LOG_INFO_EN >> ICE_AQC_FW_LOG_EN_S)
596 #define ICE_FW_LOG_EVNT_INIT (ICE_AQC_FW_LOG_INIT_EN >> ICE_AQC_FW_LOG_EN_S)
597 #define ICE_FW_LOG_EVNT_FLOW (ICE_AQC_FW_LOG_FLOW_EN >> ICE_AQC_FW_LOG_EN_S)
598 #define ICE_FW_LOG_EVNT_ERR (ICE_AQC_FW_LOG_ERR_EN >> ICE_AQC_FW_LOG_EN_S)
599 struct ice_fw_log_evnt evnts[ICE_AQC_FW_LOG_ID_MAX];
602 /* Port hardware description */
606 struct ice_aqc_layer_props *layer_info;
607 struct ice_port_info *port_info;
608 u64 debug_mask; /* bitmap for debug mask */
609 enum ice_mac_type mac_type;
611 u16 fd_ctr_base; /* FD counter base index */
616 u16 subsystem_device_id;
617 u16 subsystem_vendor_id;
620 u8 pf_id; /* device profile info */
622 u16 max_burst_size; /* driver sets this value */
624 /* Tx Scheduler values */
625 u8 num_tx_sched_layers;
626 u8 num_tx_sched_phys_layers;
629 u8 sw_entry_point_layer;
630 u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM];
631 struct list_head agg_list; /* lists all aggregator */
633 struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI];
634 u8 evb_veb; /* true for VEB, false for VEPA */
635 u8 reset_ongoing; /* true if HW is in reset, false otherwise */
636 struct ice_bus_info bus;
637 struct ice_flash_info flash;
638 struct ice_hw_dev_caps dev_caps; /* device capabilities */
639 struct ice_hw_func_caps func_caps; /* function capabilities */
641 struct ice_switch_info *switch_info; /* switch filter lists */
643 /* Control Queue info */
644 struct ice_ctl_q_info adminq;
645 struct ice_ctl_q_info mailboxq;
647 u8 api_branch; /* API branch version */
648 u8 api_maj_ver; /* API major version */
649 u8 api_min_ver; /* API minor version */
650 u8 api_patch; /* API patch version */
651 u8 fw_branch; /* firmware branch version */
652 u8 fw_maj_ver; /* firmware major version */
653 u8 fw_min_ver; /* firmware minor version */
654 u8 fw_patch; /* firmware patch version */
655 u32 fw_build; /* firmware build number */
657 struct ice_fw_log_cfg fw_log;
659 /* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL
660 * register. Used for determining the ITR/INTRL granularity during
663 #define ICE_MAX_AGG_BW_200G 0x0
664 #define ICE_MAX_AGG_BW_100G 0X1
665 #define ICE_MAX_AGG_BW_50G 0x2
666 #define ICE_MAX_AGG_BW_25G 0x3
667 /* ITR granularity for different speeds */
668 #define ICE_ITR_GRAN_ABOVE_25 2
669 #define ICE_ITR_GRAN_MAX_25 4
670 /* ITR granularity in 1 us */
672 /* INTRL granularity for different speeds */
673 #define ICE_INTRL_GRAN_ABOVE_25 4
674 #define ICE_INTRL_GRAN_MAX_25 8
675 /* INTRL granularity in 1 us */
678 u8 ucast_shared; /* true if VSIs can share unicast addr */
680 /* Active package version (currently active) */
681 struct ice_pkg_ver active_pkg_ver;
683 u8 active_pkg_name[ICE_PKG_NAME_SIZE];
684 u8 active_pkg_in_nvm;
686 enum ice_aq_err pkg_dwnld_status;
688 /* Driver's package ver - (from the Metadata seg) */
689 struct ice_pkg_ver pkg_ver;
690 u8 pkg_name[ICE_PKG_NAME_SIZE];
692 /* Driver's Ice package version (from the Ice seg) */
693 struct ice_pkg_ver ice_pkg_ver;
694 u8 ice_pkg_name[ICE_PKG_NAME_SIZE];
696 /* Pointer to the ice segment */
699 /* Pointer to allocated copy of pkg memory */
704 struct mutex tnl_lock;
705 struct ice_tunnel_table tnl;
707 struct udp_tunnel_nic_shared udp_tunnel_shared;
708 struct udp_tunnel_nic_info udp_tunnel_nic;
710 /* HW block tables */
711 struct ice_blk_info blk[ICE_BLK_COUNT];
712 struct mutex fl_profs_locks[ICE_BLK_COUNT]; /* lock fltr profiles */
713 struct list_head fl_profs[ICE_BLK_COUNT];
715 /* Flow Director filter info */
716 int fdir_active_fltr;
718 struct mutex fdir_fltr_lock; /* protect Flow Director */
719 struct list_head fdir_list_head;
721 /* Book-keeping of side-band filter count per flow-type.
722 * This is used to detect and handle input set changes for
723 * respective flow-type.
725 u16 fdir_fltr_cnt[ICE_FLTR_PTYPE_MAX];
727 struct ice_fd_hw_prof **fdir_prof;
728 DECLARE_BITMAP(fdir_perfect_fltr, ICE_FLTR_PTYPE_MAX);
729 struct mutex rss_locks; /* protect RSS configuration */
730 struct list_head rss_list_head;
733 /* Statistics collected by each port, VSI, VEB, and S-channel */
734 struct ice_eth_stats {
735 u64 rx_bytes; /* gorc */
736 u64 rx_unicast; /* uprc */
737 u64 rx_multicast; /* mprc */
738 u64 rx_broadcast; /* bprc */
739 u64 rx_discards; /* rdpc */
740 u64 rx_unknown_protocol; /* rupp */
741 u64 tx_bytes; /* gotc */
742 u64 tx_unicast; /* uptc */
743 u64 tx_multicast; /* mptc */
744 u64 tx_broadcast; /* bptc */
745 u64 tx_discards; /* tdpc */
746 u64 tx_errors; /* tepc */
751 /* Statistics collected by the MAC */
752 struct ice_hw_port_stats {
753 /* eth stats collected by the port */
754 struct ice_eth_stats eth;
755 /* additional port specific stats */
756 u64 tx_dropped_link_down; /* tdold */
757 u64 crc_errors; /* crcerrs */
758 u64 illegal_bytes; /* illerrc */
759 u64 error_bytes; /* errbc */
760 u64 mac_local_faults; /* mlfc */
761 u64 mac_remote_faults; /* mrfc */
762 u64 rx_len_errors; /* rlec */
763 u64 link_xon_rx; /* lxonrxc */
764 u64 link_xoff_rx; /* lxoffrxc */
765 u64 link_xon_tx; /* lxontxc */
766 u64 link_xoff_tx; /* lxofftxc */
767 u64 priority_xon_rx[8]; /* pxonrxc[8] */
768 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
769 u64 priority_xon_tx[8]; /* pxontxc[8] */
770 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
771 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
772 u64 rx_size_64; /* prc64 */
773 u64 rx_size_127; /* prc127 */
774 u64 rx_size_255; /* prc255 */
775 u64 rx_size_511; /* prc511 */
776 u64 rx_size_1023; /* prc1023 */
777 u64 rx_size_1522; /* prc1522 */
778 u64 rx_size_big; /* prc9522 */
779 u64 rx_undersize; /* ruc */
780 u64 rx_fragments; /* rfc */
781 u64 rx_oversize; /* roc */
782 u64 rx_jabber; /* rjc */
783 u64 tx_size_64; /* ptc64 */
784 u64 tx_size_127; /* ptc127 */
785 u64 tx_size_255; /* ptc255 */
786 u64 tx_size_511; /* ptc511 */
787 u64 tx_size_1023; /* ptc1023 */
788 u64 tx_size_1522; /* ptc1522 */
789 u64 tx_size_big; /* ptc9522 */
790 /* flow director stats */
795 /* Checksum and Shadow RAM pointers */
796 #define ICE_SR_NVM_CTRL_WORD 0x00
797 #define ICE_SR_BOOT_CFG_PTR 0x132
798 #define ICE_SR_NVM_WOL_CFG 0x19
799 #define ICE_NVM_OROM_VER_OFF 0x02
800 #define ICE_SR_PBA_BLOCK_PTR 0x16
801 #define ICE_SR_NVM_DEV_STARTER_VER 0x18
802 #define ICE_SR_NVM_EETRACK_LO 0x2D
803 #define ICE_SR_NVM_EETRACK_HI 0x2E
804 #define ICE_NVM_VER_LO_SHIFT 0
805 #define ICE_NVM_VER_LO_MASK (0xff << ICE_NVM_VER_LO_SHIFT)
806 #define ICE_NVM_VER_HI_SHIFT 12
807 #define ICE_NVM_VER_HI_MASK (0xf << ICE_NVM_VER_HI_SHIFT)
808 #define ICE_OROM_VER_PATCH_SHIFT 0
809 #define ICE_OROM_VER_PATCH_MASK (0xff << ICE_OROM_VER_PATCH_SHIFT)
810 #define ICE_OROM_VER_BUILD_SHIFT 8
811 #define ICE_OROM_VER_BUILD_MASK (0xffff << ICE_OROM_VER_BUILD_SHIFT)
812 #define ICE_OROM_VER_SHIFT 24
813 #define ICE_OROM_VER_MASK (0xff << ICE_OROM_VER_SHIFT)
814 #define ICE_SR_PFA_PTR 0x40
815 #define ICE_SR_1ST_NVM_BANK_PTR 0x42
816 #define ICE_SR_NVM_BANK_SIZE 0x43
817 #define ICE_SR_1ST_OROM_BANK_PTR 0x44
818 #define ICE_SR_OROM_BANK_SIZE 0x45
819 #define ICE_SR_NETLIST_BANK_PTR 0x46
820 #define ICE_SR_NETLIST_BANK_SIZE 0x47
821 #define ICE_SR_SECTOR_SIZE_IN_WORDS 0x800
823 /* Auxiliary field, mask, and shift definition for Shadow RAM and NVM Flash */
824 #define ICE_SR_CTRL_WORD_1_S 0x06
825 #define ICE_SR_CTRL_WORD_1_M (0x03 << ICE_SR_CTRL_WORD_1_S)
826 #define ICE_SR_CTRL_WORD_VALID 0x1
827 #define ICE_SR_CTRL_WORD_OROM_BANK BIT(3)
828 #define ICE_SR_CTRL_WORD_NETLIST_BANK BIT(4)
829 #define ICE_SR_CTRL_WORD_NVM_BANK BIT(5)
831 #define ICE_SR_NVM_PTR_4KB_UNITS BIT(15)
833 /* Link override related */
834 #define ICE_SR_PFA_LINK_OVERRIDE_WORDS 10
835 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS 4
836 #define ICE_SR_PFA_LINK_OVERRIDE_OFFSET 2
837 #define ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET 1
838 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET 2
839 #define ICE_FW_API_LINK_OVERRIDE_MAJ 1
840 #define ICE_FW_API_LINK_OVERRIDE_MIN 5
841 #define ICE_FW_API_LINK_OVERRIDE_PATCH 2
843 #define ICE_SR_WORDS_IN_1KB 512
845 /* Hash redirection LUT for VSI - maximum array size */
846 #define ICE_VSIQF_HLUT_ARRAY_SIZE ((VSIQF_HLUT_MAX_INDEX + 1) * 4)
848 #endif /* _ICE_TYPE_H_ */