1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018, Intel Corporation. */
7 #include "ice_status.h"
8 #include "ice_hw_autogen.h"
10 #include "ice_controlq.h"
11 #include "ice_lan_tx_rx.h"
13 #define ICE_BYTES_PER_WORD 2
14 #define ICE_BYTES_PER_DWORD 4
16 static inline bool ice_is_tc_ena(u8 bitmap, u8 tc)
18 return test_bit(tc, (unsigned long *)&bitmap);
21 /* Driver always calls main vsi_handle first */
22 #define ICE_MAIN_VSI_HANDLE 0
24 /* debug masks - set these bits in hw->debug_mask to control output */
25 #define ICE_DBG_INIT BIT_ULL(1)
26 #define ICE_DBG_LINK BIT_ULL(4)
27 #define ICE_DBG_QCTX BIT_ULL(6)
28 #define ICE_DBG_NVM BIT_ULL(7)
29 #define ICE_DBG_LAN BIT_ULL(8)
30 #define ICE_DBG_SW BIT_ULL(13)
31 #define ICE_DBG_SCHED BIT_ULL(14)
32 #define ICE_DBG_RES BIT_ULL(17)
33 #define ICE_DBG_AQ_MSG BIT_ULL(24)
34 #define ICE_DBG_AQ_CMD BIT_ULL(27)
35 #define ICE_DBG_USER BIT_ULL(31)
40 ICE_CHANGE_LOCK_RES_ID,
41 ICE_GLOBAL_CFG_LOCK_RES_ID
44 /* FW update timeout definitions are in milliseconds */
45 #define ICE_NVM_TIMEOUT 180000
46 #define ICE_CHANGE_LOCK_TIMEOUT 1000
47 #define ICE_GLOBAL_CFG_LOCK_TIMEOUT 3000
49 enum ice_aq_res_access_type {
63 enum ice_set_fc_aq_failures {
64 ICE_SET_FC_AQ_FAIL_NONE = 0,
65 ICE_SET_FC_AQ_FAIL_GET,
66 ICE_SET_FC_AQ_FAIL_SET,
67 ICE_SET_FC_AQ_FAIL_UPDATE
70 /* Various MAC types */
78 ICE_MEDIA_UNKNOWN = 0,
90 struct ice_link_status {
91 /* Refer to ice_aq_phy_type for bits definition */
96 u8 lse_ena; /* Link Status Event notification */
101 /* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of
102 * ice_aqc_get_phy_caps structure
104 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
107 /* Different reset sources for which a disable queue AQ call has to be made in
108 * order to clean the TX scheduler as a part of the reset
110 enum ice_disq_rst_src {
116 /* PHY info such as phy_type, etc... */
117 struct ice_phy_info {
118 struct ice_link_status link_info;
119 struct ice_link_status link_info_old;
121 enum ice_media_type media_type;
125 /* Common HW capabilities for SW use */
126 struct ice_hw_common_caps {
130 u16 num_rxq; /* Number/Total RX queues */
131 u16 rxq_first_id; /* First queue ID for RX queues */
132 u16 num_txq; /* Number/Total TX queues */
133 u16 txq_first_id; /* First queue ID for TX queues */
136 u16 num_msix_vectors;
137 u16 msix_vector_first_id;
139 /* Max MTU for function or device */
142 /* Virtualization support */
143 u8 sr_iov_1_1; /* SR-IOV enabled */
145 /* RSS related capabilities */
146 u16 rss_table_size; /* 512 for PFs and 64 for VFs */
147 u8 rss_table_entry_width; /* RSS Entry width in bits */
150 /* Function specific capabilities */
151 struct ice_hw_func_caps {
152 struct ice_hw_common_caps common_cap;
153 u32 num_allocd_vfs; /* Number of allocated VFs */
154 u32 vf_base_id; /* Logical ID of the first VF */
158 /* Device wide capabilities */
159 struct ice_hw_dev_caps {
160 struct ice_hw_common_caps common_cap;
161 u32 num_vfs_exposed; /* Total number of VFs exposed */
162 u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */
166 struct ice_mac_info {
167 u8 lan_addr[ETH_ALEN];
168 u8 perm_addr[ETH_ALEN];
171 /* Reset types used to determine which kind of reset was requested. These
172 * defines match what the RESET_TYPE field of the GLGEN_RSTAT register.
173 * ICE_RESET_PFR does not match any RESET_TYPE field in the GLGEN_RSTAT register
174 * because its reset source is different than the other types listed.
186 struct ice_bus_info {
191 /* Flow control (FC) parameters */
193 enum ice_fc_mode current_mode; /* FC mode in effect */
194 enum ice_fc_mode req_mode; /* FC mode requested by caller */
197 /* NVM Information */
198 struct ice_nvm_info {
199 u32 eetrack; /* NVM data version */
200 u32 oem_ver; /* OEM version info */
201 u16 sr_words; /* Shadow RAM size in words */
202 u16 ver; /* NVM package version */
203 u8 blank_nvm_mode; /* is NVM empty (no FW present) */
206 /* Max number of port to queue branches w.r.t topology */
207 #define ICE_MAX_TRAFFIC_CLASS 8
208 #define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS
210 struct ice_sched_node {
211 struct ice_sched_node *parent;
212 struct ice_sched_node *sibling; /* next sibling in the same layer */
213 struct ice_sched_node **children;
214 struct ice_aqc_txsched_elem_data info;
215 u32 agg_id; /* aggregator group id */
217 u8 in_use; /* suspended or in use */
218 u8 tx_sched_layer; /* Logical Layer (1-9) */
222 #define ICE_SCHED_NODE_OWNER_LAN 0
225 /* Access Macros for Tx Sched Elements data */
226 #define ICE_TXSCHED_GET_NODE_TEID(x) le32_to_cpu((x)->info.node_teid)
228 /* The aggregator type determines if identifier is for a VSI group,
229 * aggregator group, aggregator of queues, or queue group.
232 ICE_AGG_TYPE_UNKNOWN = 0,
234 ICE_AGG_TYPE_AGG, /* aggregator */
239 #define ICE_SCHED_DFLT_RL_PROF_ID 0
240 #define ICE_SCHED_DFLT_BW_WT 1
242 /* vsi type list entry to locate corresponding vsi/ag nodes */
243 struct ice_sched_vsi_info {
244 struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS];
245 struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS];
246 struct list_head list_entry;
247 u16 max_lanq[ICE_MAX_TRAFFIC_CLASS];
251 /* driver defines the policy */
252 struct ice_sched_tx_policy {
254 u8 max_num_lan_qs_per_tc[ICE_MAX_TRAFFIC_CLASS];
258 struct ice_port_info {
259 struct ice_sched_node *root; /* Root Node per Port */
260 struct ice_hw *hw; /* back pointer to hw instance */
261 u32 last_node_teid; /* scheduler last node info */
262 u16 sw_id; /* Initial switch ID belongs to port */
265 #define ICE_SCHED_PORT_STATE_INIT 0x0
266 #define ICE_SCHED_PORT_STATE_READY 0x1
267 u16 dflt_tx_vsi_rule_id;
269 u16 dflt_rx_vsi_rule_id;
271 struct ice_fc_info fc;
272 struct ice_mac_info mac;
273 struct ice_phy_info phy;
274 struct mutex sched_lock; /* protect access to TXSched tree */
275 struct list_head agg_list; /* lists all aggregator */
277 #define ICE_LPORT_MASK 0xff
281 struct ice_switch_info {
282 struct list_head vsi_list_map_head;
283 struct ice_sw_recipe *recp_list;
286 /* FW logging configuration */
287 struct ice_fw_log_evnt {
288 u8 cfg : 4; /* New event enables to configure */
289 u8 cur : 4; /* Current/active event enables */
292 struct ice_fw_log_cfg {
293 u8 cq_en : 1; /* FW logging is enabled via the control queue */
294 u8 uart_en : 1; /* FW logging is enabled via UART for all PFs */
295 u8 actv_evnts; /* Cumulation of currently enabled log events */
297 #define ICE_FW_LOG_EVNT_INFO (ICE_AQC_FW_LOG_INFO_EN >> ICE_AQC_FW_LOG_EN_S)
298 #define ICE_FW_LOG_EVNT_INIT (ICE_AQC_FW_LOG_INIT_EN >> ICE_AQC_FW_LOG_EN_S)
299 #define ICE_FW_LOG_EVNT_FLOW (ICE_AQC_FW_LOG_FLOW_EN >> ICE_AQC_FW_LOG_EN_S)
300 #define ICE_FW_LOG_EVNT_ERR (ICE_AQC_FW_LOG_ERR_EN >> ICE_AQC_FW_LOG_EN_S)
301 struct ice_fw_log_evnt evnts[ICE_AQC_FW_LOG_ID_MAX];
304 /* Port hardware description */
308 struct ice_aqc_layer_props *layer_info;
309 struct ice_port_info *port_info;
310 u64 debug_mask; /* bitmap for debug mask */
311 enum ice_mac_type mac_type;
316 u16 subsystem_device_id;
317 u16 subsystem_vendor_id;
320 u8 pf_id; /* device profile info */
322 /* TX Scheduler values */
323 u16 num_tx_sched_layers;
324 u16 num_tx_sched_phys_layers;
327 u8 sw_entry_point_layer;
328 u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM];
330 struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI];
331 u8 evb_veb; /* true for VEB, false for VEPA */
332 u8 reset_ongoing; /* true if hw is in reset, false otherwise */
333 struct ice_bus_info bus;
334 struct ice_nvm_info nvm;
335 struct ice_hw_dev_caps dev_caps; /* device capabilities */
336 struct ice_hw_func_caps func_caps; /* function capabilities */
338 struct ice_switch_info *switch_info; /* switch filter lists */
340 /* Control Queue info */
341 struct ice_ctl_q_info adminq;
342 struct ice_ctl_q_info mailboxq;
344 u8 api_branch; /* API branch version */
345 u8 api_maj_ver; /* API major version */
346 u8 api_min_ver; /* API minor version */
347 u8 api_patch; /* API patch version */
348 u8 fw_branch; /* firmware branch version */
349 u8 fw_maj_ver; /* firmware major version */
350 u8 fw_min_ver; /* firmware minor version */
351 u8 fw_patch; /* firmware patch version */
352 u32 fw_build; /* firmware build number */
354 struct ice_fw_log_cfg fw_log;
356 /* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL
357 * register. Used for determining the itr/intrl granularity during
360 #define ICE_MAX_AGG_BW_200G 0x0
361 #define ICE_MAX_AGG_BW_100G 0X1
362 #define ICE_MAX_AGG_BW_50G 0x2
363 #define ICE_MAX_AGG_BW_25G 0x3
364 /* ITR granularity for different speeds */
365 #define ICE_ITR_GRAN_ABOVE_25 2
366 #define ICE_ITR_GRAN_MAX_25 4
367 /* ITR granularity in 1 us */
369 /* INTRL granularity for different speeds */
370 #define ICE_INTRL_GRAN_ABOVE_25 4
371 #define ICE_INTRL_GRAN_MAX_25 8
372 /* INTRL granularity in 1 us */
375 u8 ucast_shared; /* true if VSIs can share unicast addr */
379 /* Statistics collected by each port, VSI, VEB, and S-channel */
380 struct ice_eth_stats {
381 u64 rx_bytes; /* gorc */
382 u64 rx_unicast; /* uprc */
383 u64 rx_multicast; /* mprc */
384 u64 rx_broadcast; /* bprc */
385 u64 rx_discards; /* rdpc */
386 u64 rx_unknown_protocol; /* rupp */
387 u64 tx_bytes; /* gotc */
388 u64 tx_unicast; /* uptc */
389 u64 tx_multicast; /* mptc */
390 u64 tx_broadcast; /* bptc */
391 u64 tx_discards; /* tdpc */
392 u64 tx_errors; /* tepc */
395 /* Statistics collected by the MAC */
396 struct ice_hw_port_stats {
397 /* eth stats collected by the port */
398 struct ice_eth_stats eth;
399 /* additional port specific stats */
400 u64 tx_dropped_link_down; /* tdold */
401 u64 crc_errors; /* crcerrs */
402 u64 illegal_bytes; /* illerrc */
403 u64 error_bytes; /* errbc */
404 u64 mac_local_faults; /* mlfc */
405 u64 mac_remote_faults; /* mrfc */
406 u64 rx_len_errors; /* rlec */
407 u64 link_xon_rx; /* lxonrxc */
408 u64 link_xoff_rx; /* lxoffrxc */
409 u64 link_xon_tx; /* lxontxc */
410 u64 link_xoff_tx; /* lxofftxc */
411 u64 rx_size_64; /* prc64 */
412 u64 rx_size_127; /* prc127 */
413 u64 rx_size_255; /* prc255 */
414 u64 rx_size_511; /* prc511 */
415 u64 rx_size_1023; /* prc1023 */
416 u64 rx_size_1522; /* prc1522 */
417 u64 rx_size_big; /* prc9522 */
418 u64 rx_undersize; /* ruc */
419 u64 rx_fragments; /* rfc */
420 u64 rx_oversize; /* roc */
421 u64 rx_jabber; /* rjc */
422 u64 tx_size_64; /* ptc64 */
423 u64 tx_size_127; /* ptc127 */
424 u64 tx_size_255; /* ptc255 */
425 u64 tx_size_511; /* ptc511 */
426 u64 tx_size_1023; /* ptc1023 */
427 u64 tx_size_1522; /* ptc1522 */
428 u64 tx_size_big; /* ptc9522 */
431 /* Checksum and Shadow RAM pointers */
432 #define ICE_SR_NVM_DEV_STARTER_VER 0x18
433 #define ICE_SR_NVM_EETRACK_LO 0x2D
434 #define ICE_SR_NVM_EETRACK_HI 0x2E
435 #define ICE_NVM_VER_LO_SHIFT 0
436 #define ICE_NVM_VER_LO_MASK (0xff << ICE_NVM_VER_LO_SHIFT)
437 #define ICE_NVM_VER_HI_SHIFT 12
438 #define ICE_NVM_VER_HI_MASK (0xf << ICE_NVM_VER_HI_SHIFT)
439 #define ICE_OEM_VER_PATCH_SHIFT 0
440 #define ICE_OEM_VER_PATCH_MASK (0xff << ICE_OEM_VER_PATCH_SHIFT)
441 #define ICE_OEM_VER_BUILD_SHIFT 8
442 #define ICE_OEM_VER_BUILD_MASK (0xffff << ICE_OEM_VER_BUILD_SHIFT)
443 #define ICE_OEM_VER_SHIFT 24
444 #define ICE_OEM_VER_MASK (0xff << ICE_OEM_VER_SHIFT)
445 #define ICE_SR_SECTOR_SIZE_IN_WORDS 0x800
446 #define ICE_SR_WORDS_IN_1KB 512
448 /* Hash redirection LUT for VSI - maximum array size */
449 #define ICE_VSIQF_HLUT_ARRAY_SIZE ((VSIQF_HLUT_MAX_INDEX + 1) * 4)
451 #endif /* _ICE_TYPE_H_ */