1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (C) 2021, Intel Corporation. */
4 #include <linux/delay.h>
5 #include "ice_common.h"
6 #include "ice_ptp_hw.h"
7 #include "ice_ptp_consts.h"
8 #include "ice_cgu_regs.h"
10 static struct dpll_pin_frequency ice_cgu_pin_freq_common[] = {
11 DPLL_PIN_FREQUENCY_1PPS,
12 DPLL_PIN_FREQUENCY_10MHZ,
15 static struct dpll_pin_frequency ice_cgu_pin_freq_1_hz[] = {
16 DPLL_PIN_FREQUENCY_1PPS,
19 static struct dpll_pin_frequency ice_cgu_pin_freq_10_mhz[] = {
20 DPLL_PIN_FREQUENCY_10MHZ,
23 static const struct ice_cgu_pin_desc ice_e810t_sfp_cgu_inputs[] = {
24 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR,
25 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
26 { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR,
27 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
28 { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, 0, },
29 { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, 0, },
30 { "SMA1", ZL_REF3P, DPLL_PIN_TYPE_EXT,
31 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
32 { "SMA2/U.FL2", ZL_REF3N, DPLL_PIN_TYPE_EXT,
33 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
34 { "GNSS-1PPS", ZL_REF4P, DPLL_PIN_TYPE_GNSS,
35 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },
36 { "OCXO", ZL_REF4N, DPLL_PIN_TYPE_INT_OSCILLATOR, 0, },
39 static const struct ice_cgu_pin_desc ice_e810t_qsfp_cgu_inputs[] = {
40 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR,
41 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
42 { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR,
43 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
44 { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, },
45 { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, },
46 { "C827_1-RCLKA", ZL_REF2P, DPLL_PIN_TYPE_MUX, },
47 { "C827_1-RCLKB", ZL_REF2N, DPLL_PIN_TYPE_MUX, },
48 { "SMA1", ZL_REF3P, DPLL_PIN_TYPE_EXT,
49 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
50 { "SMA2/U.FL2", ZL_REF3N, DPLL_PIN_TYPE_EXT,
51 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
52 { "GNSS-1PPS", ZL_REF4P, DPLL_PIN_TYPE_GNSS,
53 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },
54 { "OCXO", ZL_REF4N, DPLL_PIN_TYPE_INT_OSCILLATOR, },
57 static const struct ice_cgu_pin_desc ice_e810t_sfp_cgu_outputs[] = {
58 { "REF-SMA1", ZL_OUT0, DPLL_PIN_TYPE_EXT,
59 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
60 { "REF-SMA2/U.FL2", ZL_OUT1, DPLL_PIN_TYPE_EXT,
61 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
62 { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT, },
63 { "MAC-CLK", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, },
64 { "CVL-SDP21", ZL_OUT4, DPLL_PIN_TYPE_EXT,
65 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },
66 { "CVL-SDP23", ZL_OUT5, DPLL_PIN_TYPE_EXT,
67 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },
70 static const struct ice_cgu_pin_desc ice_e810t_qsfp_cgu_outputs[] = {
71 { "REF-SMA1", ZL_OUT0, DPLL_PIN_TYPE_EXT,
72 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
73 { "REF-SMA2/U.FL2", ZL_OUT1, DPLL_PIN_TYPE_EXT,
74 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
75 { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },
76 { "PHY2-CLK", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },
77 { "MAC-CLK", ZL_OUT4, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },
78 { "CVL-SDP21", ZL_OUT5, DPLL_PIN_TYPE_EXT,
79 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },
80 { "CVL-SDP23", ZL_OUT6, DPLL_PIN_TYPE_EXT,
81 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },
84 static const struct ice_cgu_pin_desc ice_e823_si_cgu_inputs[] = {
85 { "NONE", SI_REF0P, 0, 0 },
86 { "NONE", SI_REF0N, 0, 0 },
87 { "SYNCE0_DP", SI_REF1P, DPLL_PIN_TYPE_MUX, 0 },
88 { "SYNCE0_DN", SI_REF1N, DPLL_PIN_TYPE_MUX, 0 },
89 { "EXT_CLK_SYNC", SI_REF2P, DPLL_PIN_TYPE_EXT,
90 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
91 { "NONE", SI_REF2N, 0, 0 },
92 { "EXT_PPS_OUT", SI_REF3, DPLL_PIN_TYPE_EXT,
93 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
94 { "INT_PPS_OUT", SI_REF4, DPLL_PIN_TYPE_EXT,
95 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
98 static const struct ice_cgu_pin_desc ice_e823_si_cgu_outputs[] = {
99 { "1588-TIME_SYNC", SI_OUT0, DPLL_PIN_TYPE_EXT,
100 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
101 { "PHY-CLK", SI_OUT1, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },
102 { "10MHZ-SMA2", SI_OUT2, DPLL_PIN_TYPE_EXT,
103 ARRAY_SIZE(ice_cgu_pin_freq_10_mhz), ice_cgu_pin_freq_10_mhz },
104 { "PPS-SMA1", SI_OUT3, DPLL_PIN_TYPE_EXT,
105 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
108 static const struct ice_cgu_pin_desc ice_e823_zl_cgu_inputs[] = {
109 { "NONE", ZL_REF0P, 0, 0 },
110 { "INT_PPS_OUT", ZL_REF0N, DPLL_PIN_TYPE_EXT,
111 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },
112 { "SYNCE0_DP", ZL_REF1P, DPLL_PIN_TYPE_MUX, 0 },
113 { "SYNCE0_DN", ZL_REF1N, DPLL_PIN_TYPE_MUX, 0 },
114 { "NONE", ZL_REF2P, 0, 0 },
115 { "NONE", ZL_REF2N, 0, 0 },
116 { "EXT_CLK_SYNC", ZL_REF3P, DPLL_PIN_TYPE_EXT,
117 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
118 { "NONE", ZL_REF3N, 0, 0 },
119 { "EXT_PPS_OUT", ZL_REF4P, DPLL_PIN_TYPE_EXT,
120 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },
121 { "OCXO", ZL_REF4N, DPLL_PIN_TYPE_INT_OSCILLATOR, 0 },
124 static const struct ice_cgu_pin_desc ice_e823_zl_cgu_outputs[] = {
125 { "PPS-SMA1", ZL_OUT0, DPLL_PIN_TYPE_EXT,
126 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },
127 { "10MHZ-SMA2", ZL_OUT1, DPLL_PIN_TYPE_EXT,
128 ARRAY_SIZE(ice_cgu_pin_freq_10_mhz), ice_cgu_pin_freq_10_mhz },
129 { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },
130 { "1588-TIME_REF", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },
131 { "CPK-TIME_SYNC", ZL_OUT4, DPLL_PIN_TYPE_EXT,
132 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
133 { "NONE", ZL_OUT5, 0, 0 },
136 /* Low level functions for interacting with and managing the device clock used
137 * for the Precision Time Protocol.
139 * The ice hardware represents the current time using three registers:
141 * GLTSYN_TIME_H GLTSYN_TIME_L GLTSYN_TIME_R
142 * +---------------+ +---------------+ +---------------+
143 * | 32 bits | | 32 bits | | 32 bits |
144 * +---------------+ +---------------+ +---------------+
146 * The registers are incremented every clock tick using a 40bit increment
147 * value defined over two registers:
149 * GLTSYN_INCVAL_H GLTSYN_INCVAL_L
150 * +---------------+ +---------------+
151 * | 8 bit s | | 32 bits |
152 * +---------------+ +---------------+
154 * The increment value is added to the GLSTYN_TIME_R and GLSTYN_TIME_L
155 * registers every clock source tick. Depending on the specific device
156 * configuration, the clock source frequency could be one of a number of
159 * For E810 devices, the increment frequency is 812.5 MHz
161 * For E822 devices the clock can be derived from different sources, and the
162 * increment has an effective frequency of one of the following:
170 * The hardware captures timestamps in the PHY for incoming packets, and for
171 * outgoing packets on request. To support this, the PHY maintains a timer
172 * that matches the lower 64 bits of the global source timer.
174 * In order to ensure that the PHY timers and the source timer are equivalent,
175 * shadow registers are used to prepare the desired initial values. A special
176 * sync command is issued to trigger copying from the shadow registers into
177 * the appropriate source and PHY registers simultaneously.
179 * The driver supports devices which have different PHYs with subtly different
180 * mechanisms to program and control the timers. We divide the devices into
181 * families named after the first major device, E810 and similar devices, and
182 * E822 and similar devices.
184 * - E822 based devices have additional support for fine grained Vernier
185 * calibration which requires significant setup
186 * - The layout of timestamp data in the PHY register blocks is different
187 * - The way timer synchronization commands are issued is different.
189 * To support this, very low level functions have an e810 or e822 suffix
190 * indicating what type of device they work on. Higher level abstractions for
191 * tasks that can be done on both devices do not have the suffix and will
192 * correctly look up the appropriate low level function when running.
194 * Functions which only make sense on a single device family may not have
195 * a suitable generic implementation
199 * ice_get_ptp_src_clock_index - determine source clock index
200 * @hw: pointer to HW struct
202 * Determine the source clock index currently in use, based on device
203 * capabilities reported during initialization.
205 u8 ice_get_ptp_src_clock_index(struct ice_hw *hw)
207 return hw->func_caps.ts_func_info.tmr_index_assoc;
211 * ice_ptp_read_src_incval - Read source timer increment value
212 * @hw: pointer to HW struct
214 * Read the increment value of the source timer and return it.
216 static u64 ice_ptp_read_src_incval(struct ice_hw *hw)
221 tmr_idx = ice_get_ptp_src_clock_index(hw);
223 lo = rd32(hw, GLTSYN_INCVAL_L(tmr_idx));
224 hi = rd32(hw, GLTSYN_INCVAL_H(tmr_idx));
226 return ((u64)(hi & INCVAL_HIGH_M) << 32) | lo;
230 * ice_ptp_src_cmd - Prepare source timer for a timer command
231 * @hw: pointer to HW structure
232 * @cmd: Timer command
234 * Prepare the source timer for an upcoming timer sync command.
236 void ice_ptp_src_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd)
241 tmr_idx = ice_get_ptp_src_clock_index(hw);
242 cmd_val = tmr_idx << SEL_CPK_SRC;
245 case ICE_PTP_INIT_TIME:
246 cmd_val |= GLTSYN_CMD_INIT_TIME;
248 case ICE_PTP_INIT_INCVAL:
249 cmd_val |= GLTSYN_CMD_INIT_INCVAL;
251 case ICE_PTP_ADJ_TIME:
252 cmd_val |= GLTSYN_CMD_ADJ_TIME;
254 case ICE_PTP_ADJ_TIME_AT_TIME:
255 cmd_val |= GLTSYN_CMD_ADJ_INIT_TIME;
257 case ICE_PTP_READ_TIME:
258 cmd_val |= GLTSYN_CMD_READ_TIME;
264 wr32(hw, GLTSYN_CMD, cmd_val);
268 * ice_ptp_exec_tmr_cmd - Execute all prepared timer commands
269 * @hw: pointer to HW struct
271 * Write the SYNC_EXEC_CMD bit to the GLTSYN_CMD_SYNC register, and flush the
272 * write immediately. This triggers the hardware to begin executing all of the
273 * source and PHY timer commands synchronously.
275 static void ice_ptp_exec_tmr_cmd(struct ice_hw *hw)
277 wr32(hw, GLTSYN_CMD_SYNC, SYNC_EXEC_CMD);
281 /* E822 family functions
283 * The following functions operate on the E822 family of devices.
287 * ice_fill_phy_msg_e822 - Fill message data for a PHY register access
288 * @msg: the PHY message buffer to fill in
289 * @port: the port to access
290 * @offset: the register offset
293 ice_fill_phy_msg_e822(struct ice_sbq_msg_input *msg, u8 port, u16 offset)
295 int phy_port, phy, quadtype;
297 phy_port = port % ICE_PORTS_PER_PHY_E822;
298 phy = port / ICE_PORTS_PER_PHY_E822;
299 quadtype = (port / ICE_PORTS_PER_QUAD) % ICE_QUADS_PER_PHY_E822;
302 msg->msg_addr_low = P_Q0_L(P_0_BASE + offset, phy_port);
303 msg->msg_addr_high = P_Q0_H(P_0_BASE + offset, phy_port);
305 msg->msg_addr_low = P_Q1_L(P_4_BASE + offset, phy_port);
306 msg->msg_addr_high = P_Q1_H(P_4_BASE + offset, phy_port);
310 msg->dest_dev = rmn_0;
312 msg->dest_dev = rmn_1;
314 msg->dest_dev = rmn_2;
318 * ice_is_64b_phy_reg_e822 - Check if this is a 64bit PHY register
319 * @low_addr: the low address to check
320 * @high_addr: on return, contains the high address of the 64bit register
322 * Checks if the provided low address is one of the known 64bit PHY values
323 * represented as two 32bit registers. If it is, return the appropriate high
324 * register offset to use.
326 static bool ice_is_64b_phy_reg_e822(u16 low_addr, u16 *high_addr)
329 case P_REG_PAR_PCS_TX_OFFSET_L:
330 *high_addr = P_REG_PAR_PCS_TX_OFFSET_U;
332 case P_REG_PAR_PCS_RX_OFFSET_L:
333 *high_addr = P_REG_PAR_PCS_RX_OFFSET_U;
335 case P_REG_PAR_TX_TIME_L:
336 *high_addr = P_REG_PAR_TX_TIME_U;
338 case P_REG_PAR_RX_TIME_L:
339 *high_addr = P_REG_PAR_RX_TIME_U;
341 case P_REG_TOTAL_TX_OFFSET_L:
342 *high_addr = P_REG_TOTAL_TX_OFFSET_U;
344 case P_REG_TOTAL_RX_OFFSET_L:
345 *high_addr = P_REG_TOTAL_RX_OFFSET_U;
347 case P_REG_UIX66_10G_40G_L:
348 *high_addr = P_REG_UIX66_10G_40G_U;
350 case P_REG_UIX66_25G_100G_L:
351 *high_addr = P_REG_UIX66_25G_100G_U;
353 case P_REG_TX_CAPTURE_L:
354 *high_addr = P_REG_TX_CAPTURE_U;
356 case P_REG_RX_CAPTURE_L:
357 *high_addr = P_REG_RX_CAPTURE_U;
359 case P_REG_TX_TIMER_INC_PRE_L:
360 *high_addr = P_REG_TX_TIMER_INC_PRE_U;
362 case P_REG_RX_TIMER_INC_PRE_L:
363 *high_addr = P_REG_RX_TIMER_INC_PRE_U;
371 * ice_is_40b_phy_reg_e822 - Check if this is a 40bit PHY register
372 * @low_addr: the low address to check
373 * @high_addr: on return, contains the high address of the 40bit value
375 * Checks if the provided low address is one of the known 40bit PHY values
376 * split into two registers with the lower 8 bits in the low register and the
377 * upper 32 bits in the high register. If it is, return the appropriate high
378 * register offset to use.
380 static bool ice_is_40b_phy_reg_e822(u16 low_addr, u16 *high_addr)
383 case P_REG_TIMETUS_L:
384 *high_addr = P_REG_TIMETUS_U;
386 case P_REG_PAR_RX_TUS_L:
387 *high_addr = P_REG_PAR_RX_TUS_U;
389 case P_REG_PAR_TX_TUS_L:
390 *high_addr = P_REG_PAR_TX_TUS_U;
392 case P_REG_PCS_RX_TUS_L:
393 *high_addr = P_REG_PCS_RX_TUS_U;
395 case P_REG_PCS_TX_TUS_L:
396 *high_addr = P_REG_PCS_TX_TUS_U;
398 case P_REG_DESK_PAR_RX_TUS_L:
399 *high_addr = P_REG_DESK_PAR_RX_TUS_U;
401 case P_REG_DESK_PAR_TX_TUS_L:
402 *high_addr = P_REG_DESK_PAR_TX_TUS_U;
404 case P_REG_DESK_PCS_RX_TUS_L:
405 *high_addr = P_REG_DESK_PCS_RX_TUS_U;
407 case P_REG_DESK_PCS_TX_TUS_L:
408 *high_addr = P_REG_DESK_PCS_TX_TUS_U;
416 * ice_read_phy_reg_e822 - Read a PHY register
417 * @hw: pointer to the HW struct
418 * @port: PHY port to read from
419 * @offset: PHY register offset to read
420 * @val: on return, the contents read from the PHY
422 * Read a PHY register for the given port over the device sideband queue.
425 ice_read_phy_reg_e822(struct ice_hw *hw, u8 port, u16 offset, u32 *val)
427 struct ice_sbq_msg_input msg = {0};
430 ice_fill_phy_msg_e822(&msg, port, offset);
431 msg.opcode = ice_sbq_msg_rd;
433 err = ice_sbq_rw_reg(hw, &msg);
435 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n",
446 * ice_read_64b_phy_reg_e822 - Read a 64bit value from PHY registers
447 * @hw: pointer to the HW struct
448 * @port: PHY port to read from
449 * @low_addr: offset of the lower register to read from
450 * @val: on return, the contents of the 64bit value from the PHY registers
452 * Reads the two registers associated with a 64bit value and returns it in the
453 * val pointer. The offset always specifies the lower register offset to use.
454 * The high offset is looked up. This function only operates on registers
455 * known to be two parts of a 64bit value.
458 ice_read_64b_phy_reg_e822(struct ice_hw *hw, u8 port, u16 low_addr, u64 *val)
464 /* Only operate on registers known to be split into two 32bit
467 if (!ice_is_64b_phy_reg_e822(low_addr, &high_addr)) {
468 ice_debug(hw, ICE_DBG_PTP, "Invalid 64b register addr 0x%08x\n",
473 err = ice_read_phy_reg_e822(hw, port, low_addr, &low);
475 ice_debug(hw, ICE_DBG_PTP, "Failed to read from low register 0x%08x\n, err %d",
480 err = ice_read_phy_reg_e822(hw, port, high_addr, &high);
482 ice_debug(hw, ICE_DBG_PTP, "Failed to read from high register 0x%08x\n, err %d",
487 *val = (u64)high << 32 | low;
493 * ice_write_phy_reg_e822 - Write a PHY register
494 * @hw: pointer to the HW struct
495 * @port: PHY port to write to
496 * @offset: PHY register offset to write
497 * @val: The value to write to the register
499 * Write a PHY register for the given port over the device sideband queue.
502 ice_write_phy_reg_e822(struct ice_hw *hw, u8 port, u16 offset, u32 val)
504 struct ice_sbq_msg_input msg = {0};
507 ice_fill_phy_msg_e822(&msg, port, offset);
508 msg.opcode = ice_sbq_msg_wr;
511 err = ice_sbq_rw_reg(hw, &msg);
513 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n",
522 * ice_write_40b_phy_reg_e822 - Write a 40b value to the PHY
523 * @hw: pointer to the HW struct
524 * @port: port to write to
525 * @low_addr: offset of the low register
526 * @val: 40b value to write
528 * Write the provided 40b value to the two associated registers by splitting
529 * it up into two chunks, the lower 8 bits and the upper 32 bits.
532 ice_write_40b_phy_reg_e822(struct ice_hw *hw, u8 port, u16 low_addr, u64 val)
538 /* Only operate on registers known to be split into a lower 8 bit
539 * register and an upper 32 bit register.
541 if (!ice_is_40b_phy_reg_e822(low_addr, &high_addr)) {
542 ice_debug(hw, ICE_DBG_PTP, "Invalid 40b register addr 0x%08x\n",
547 low = (u32)(val & P_REG_40B_LOW_M);
548 high = (u32)(val >> P_REG_40B_HIGH_S);
550 err = ice_write_phy_reg_e822(hw, port, low_addr, low);
552 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d",
557 err = ice_write_phy_reg_e822(hw, port, high_addr, high);
559 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d",
568 * ice_write_64b_phy_reg_e822 - Write a 64bit value to PHY registers
569 * @hw: pointer to the HW struct
570 * @port: PHY port to read from
571 * @low_addr: offset of the lower register to read from
572 * @val: the contents of the 64bit value to write to PHY
574 * Write the 64bit value to the two associated 32bit PHY registers. The offset
575 * is always specified as the lower register, and the high address is looked
576 * up. This function only operates on registers known to be two parts of
580 ice_write_64b_phy_reg_e822(struct ice_hw *hw, u8 port, u16 low_addr, u64 val)
586 /* Only operate on registers known to be split into two 32bit
589 if (!ice_is_64b_phy_reg_e822(low_addr, &high_addr)) {
590 ice_debug(hw, ICE_DBG_PTP, "Invalid 64b register addr 0x%08x\n",
595 low = lower_32_bits(val);
596 high = upper_32_bits(val);
598 err = ice_write_phy_reg_e822(hw, port, low_addr, low);
600 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d",
605 err = ice_write_phy_reg_e822(hw, port, high_addr, high);
607 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d",
616 * ice_fill_quad_msg_e822 - Fill message data for quad register access
617 * @msg: the PHY message buffer to fill in
618 * @quad: the quad to access
619 * @offset: the register offset
621 * Fill a message buffer for accessing a register in a quad shared between
625 ice_fill_quad_msg_e822(struct ice_sbq_msg_input *msg, u8 quad, u16 offset)
629 if (quad >= ICE_MAX_QUAD)
632 msg->dest_dev = rmn_0;
634 if ((quad % ICE_QUADS_PER_PHY_E822) == 0)
635 addr = Q_0_BASE + offset;
637 addr = Q_1_BASE + offset;
639 msg->msg_addr_low = lower_16_bits(addr);
640 msg->msg_addr_high = upper_16_bits(addr);
646 * ice_read_quad_reg_e822 - Read a PHY quad register
647 * @hw: pointer to the HW struct
648 * @quad: quad to read from
649 * @offset: quad register offset to read
650 * @val: on return, the contents read from the quad
652 * Read a quad register over the device sideband queue. Quad registers are
653 * shared between multiple PHYs.
656 ice_read_quad_reg_e822(struct ice_hw *hw, u8 quad, u16 offset, u32 *val)
658 struct ice_sbq_msg_input msg = {0};
661 err = ice_fill_quad_msg_e822(&msg, quad, offset);
665 msg.opcode = ice_sbq_msg_rd;
667 err = ice_sbq_rw_reg(hw, &msg);
669 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n",
680 * ice_write_quad_reg_e822 - Write a PHY quad register
681 * @hw: pointer to the HW struct
682 * @quad: quad to write to
683 * @offset: quad register offset to write
684 * @val: The value to write to the register
686 * Write a quad register over the device sideband queue. Quad registers are
687 * shared between multiple PHYs.
690 ice_write_quad_reg_e822(struct ice_hw *hw, u8 quad, u16 offset, u32 val)
692 struct ice_sbq_msg_input msg = {0};
695 err = ice_fill_quad_msg_e822(&msg, quad, offset);
699 msg.opcode = ice_sbq_msg_wr;
702 err = ice_sbq_rw_reg(hw, &msg);
704 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n",
713 * ice_read_phy_tstamp_e822 - Read a PHY timestamp out of the quad block
714 * @hw: pointer to the HW struct
715 * @quad: the quad to read from
716 * @idx: the timestamp index to read
717 * @tstamp: on return, the 40bit timestamp value
719 * Read a 40bit timestamp value out of the two associated registers in the
720 * quad memory block that is shared between the internal PHYs of the E822
724 ice_read_phy_tstamp_e822(struct ice_hw *hw, u8 quad, u8 idx, u64 *tstamp)
726 u16 lo_addr, hi_addr;
730 lo_addr = (u16)TS_L(Q_REG_TX_MEMORY_BANK_START, idx);
731 hi_addr = (u16)TS_H(Q_REG_TX_MEMORY_BANK_START, idx);
733 err = ice_read_quad_reg_e822(hw, quad, lo_addr, &lo);
735 ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, err %d\n",
740 err = ice_read_quad_reg_e822(hw, quad, hi_addr, &hi);
742 ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, err %d\n",
747 /* For E822 based internal PHYs, the timestamp is reported with the
748 * lower 8 bits in the low register, and the upper 32 bits in the high
751 *tstamp = ((u64)hi) << TS_PHY_HIGH_S | ((u64)lo & TS_PHY_LOW_M);
757 * ice_clear_phy_tstamp_e822 - Clear a timestamp from the quad block
758 * @hw: pointer to the HW struct
759 * @quad: the quad to read from
760 * @idx: the timestamp index to reset
762 * Read the timestamp out of the quad to clear its timestamp status bit from
763 * the PHY quad block that is shared between the internal PHYs of the E822
766 * Note that unlike E810, software cannot directly write to the quad memory
767 * bank registers. E822 relies on the ice_get_phy_tx_tstamp_ready() function
768 * to determine which timestamps are valid. Reading a timestamp auto-clears
771 * To directly clear the contents of the timestamp block entirely, discarding
772 * all timestamp data at once, software should instead use
773 * ice_ptp_reset_ts_memory_quad_e822().
775 * This function should only be called on an idx whose bit is set according to
776 * ice_get_phy_tx_tstamp_ready().
779 ice_clear_phy_tstamp_e822(struct ice_hw *hw, u8 quad, u8 idx)
784 err = ice_read_phy_tstamp_e822(hw, quad, idx, &unused_tstamp);
786 ice_debug(hw, ICE_DBG_PTP, "Failed to read the timestamp register for quad %u, idx %u, err %d\n",
795 * ice_ptp_reset_ts_memory_quad_e822 - Clear all timestamps from the quad block
796 * @hw: pointer to the HW struct
797 * @quad: the quad to read from
799 * Clear all timestamps from the PHY quad block that is shared between the
800 * internal PHYs on the E822 devices.
802 void ice_ptp_reset_ts_memory_quad_e822(struct ice_hw *hw, u8 quad)
804 ice_write_quad_reg_e822(hw, quad, Q_REG_TS_CTRL, Q_REG_TS_CTRL_M);
805 ice_write_quad_reg_e822(hw, quad, Q_REG_TS_CTRL, ~(u32)Q_REG_TS_CTRL_M);
809 * ice_ptp_reset_ts_memory_e822 - Clear all timestamps from all quad blocks
810 * @hw: pointer to the HW struct
812 static void ice_ptp_reset_ts_memory_e822(struct ice_hw *hw)
816 for (quad = 0; quad < ICE_MAX_QUAD; quad++)
817 ice_ptp_reset_ts_memory_quad_e822(hw, quad);
821 * ice_read_cgu_reg_e822 - Read a CGU register
822 * @hw: pointer to the HW struct
823 * @addr: Register address to read
824 * @val: storage for register value read
826 * Read the contents of a register of the Clock Generation Unit. Only
827 * applicable to E822 devices.
830 ice_read_cgu_reg_e822(struct ice_hw *hw, u32 addr, u32 *val)
832 struct ice_sbq_msg_input cgu_msg;
835 cgu_msg.opcode = ice_sbq_msg_rd;
836 cgu_msg.dest_dev = cgu;
837 cgu_msg.msg_addr_low = addr;
838 cgu_msg.msg_addr_high = 0x0;
840 err = ice_sbq_rw_reg(hw, &cgu_msg);
842 ice_debug(hw, ICE_DBG_PTP, "Failed to read CGU register 0x%04x, err %d\n",
853 * ice_write_cgu_reg_e822 - Write a CGU register
854 * @hw: pointer to the HW struct
855 * @addr: Register address to write
856 * @val: value to write into the register
858 * Write the specified value to a register of the Clock Generation Unit. Only
859 * applicable to E822 devices.
862 ice_write_cgu_reg_e822(struct ice_hw *hw, u32 addr, u32 val)
864 struct ice_sbq_msg_input cgu_msg;
867 cgu_msg.opcode = ice_sbq_msg_wr;
868 cgu_msg.dest_dev = cgu;
869 cgu_msg.msg_addr_low = addr;
870 cgu_msg.msg_addr_high = 0x0;
873 err = ice_sbq_rw_reg(hw, &cgu_msg);
875 ice_debug(hw, ICE_DBG_PTP, "Failed to write CGU register 0x%04x, err %d\n",
884 * ice_clk_freq_str - Convert time_ref_freq to string
885 * @clk_freq: Clock frequency
887 * Convert the specified TIME_REF clock frequency to a string.
889 static const char *ice_clk_freq_str(u8 clk_freq)
891 switch ((enum ice_time_ref_freq)clk_freq) {
892 case ICE_TIME_REF_FREQ_25_000:
894 case ICE_TIME_REF_FREQ_122_880:
896 case ICE_TIME_REF_FREQ_125_000:
898 case ICE_TIME_REF_FREQ_153_600:
900 case ICE_TIME_REF_FREQ_156_250:
902 case ICE_TIME_REF_FREQ_245_760:
910 * ice_clk_src_str - Convert time_ref_src to string
911 * @clk_src: Clock source
913 * Convert the specified clock source to its string name.
915 static const char *ice_clk_src_str(u8 clk_src)
917 switch ((enum ice_clk_src)clk_src) {
918 case ICE_CLK_SRC_TCX0:
920 case ICE_CLK_SRC_TIME_REF:
928 * ice_cfg_cgu_pll_e822 - Configure the Clock Generation Unit
929 * @hw: pointer to the HW struct
930 * @clk_freq: Clock frequency to program
931 * @clk_src: Clock source to select (TIME_REF, or TCX0)
933 * Configure the Clock Generation Unit with the desired clock frequency and
934 * time reference, enabling the PLL which drives the PTP hardware clock.
937 ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq clk_freq,
938 enum ice_clk_src clk_src)
940 union tspll_ro_bwm_lf bwm_lf;
941 union nac_cgu_dword19 dw19;
942 union nac_cgu_dword22 dw22;
943 union nac_cgu_dword24 dw24;
944 union nac_cgu_dword9 dw9;
947 if (clk_freq >= NUM_ICE_TIME_REF_FREQ) {
948 dev_warn(ice_hw_to_dev(hw), "Invalid TIME_REF frequency %u\n",
953 if (clk_src >= NUM_ICE_CLK_SRC) {
954 dev_warn(ice_hw_to_dev(hw), "Invalid clock source %u\n",
959 if (clk_src == ICE_CLK_SRC_TCX0 &&
960 clk_freq != ICE_TIME_REF_FREQ_25_000) {
961 dev_warn(ice_hw_to_dev(hw),
962 "TCX0 only supports 25 MHz frequency\n");
966 err = ice_read_cgu_reg_e822(hw, NAC_CGU_DWORD9, &dw9.val);
970 err = ice_read_cgu_reg_e822(hw, NAC_CGU_DWORD24, &dw24.val);
974 err = ice_read_cgu_reg_e822(hw, TSPLL_RO_BWM_LF, &bwm_lf.val);
978 /* Log the current clock configuration */
979 ice_debug(hw, ICE_DBG_PTP, "Current CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n",
980 dw24.field.ts_pll_enable ? "enabled" : "disabled",
981 ice_clk_src_str(dw24.field.time_ref_sel),
982 ice_clk_freq_str(dw9.field.time_ref_freq_sel),
983 bwm_lf.field.plllock_true_lock_cri ? "locked" : "unlocked");
985 /* Disable the PLL before changing the clock source or frequency */
986 if (dw24.field.ts_pll_enable) {
987 dw24.field.ts_pll_enable = 0;
989 err = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD24, dw24.val);
994 /* Set the frequency */
995 dw9.field.time_ref_freq_sel = clk_freq;
996 err = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD9, dw9.val);
1000 /* Configure the TS PLL feedback divisor */
1001 err = ice_read_cgu_reg_e822(hw, NAC_CGU_DWORD19, &dw19.val);
1005 dw19.field.tspll_fbdiv_intgr = e822_cgu_params[clk_freq].feedback_div;
1006 dw19.field.tspll_ndivratio = 1;
1008 err = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD19, dw19.val);
1012 /* Configure the TS PLL post divisor */
1013 err = ice_read_cgu_reg_e822(hw, NAC_CGU_DWORD22, &dw22.val);
1017 dw22.field.time1588clk_div = e822_cgu_params[clk_freq].post_pll_div;
1018 dw22.field.time1588clk_sel_div2 = 0;
1020 err = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD22, dw22.val);
1024 /* Configure the TS PLL pre divisor and clock source */
1025 err = ice_read_cgu_reg_e822(hw, NAC_CGU_DWORD24, &dw24.val);
1029 dw24.field.ref1588_ck_div = e822_cgu_params[clk_freq].refclk_pre_div;
1030 dw24.field.tspll_fbdiv_frac = e822_cgu_params[clk_freq].frac_n_div;
1031 dw24.field.time_ref_sel = clk_src;
1033 err = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD24, dw24.val);
1037 /* Finally, enable the PLL */
1038 dw24.field.ts_pll_enable = 1;
1040 err = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD24, dw24.val);
1044 /* Wait to verify if the PLL locks */
1045 usleep_range(1000, 5000);
1047 err = ice_read_cgu_reg_e822(hw, TSPLL_RO_BWM_LF, &bwm_lf.val);
1051 if (!bwm_lf.field.plllock_true_lock_cri) {
1052 dev_warn(ice_hw_to_dev(hw), "CGU PLL failed to lock\n");
1056 /* Log the current clock configuration */
1057 ice_debug(hw, ICE_DBG_PTP, "New CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n",
1058 dw24.field.ts_pll_enable ? "enabled" : "disabled",
1059 ice_clk_src_str(dw24.field.time_ref_sel),
1060 ice_clk_freq_str(dw9.field.time_ref_freq_sel),
1061 bwm_lf.field.plllock_true_lock_cri ? "locked" : "unlocked");
1067 * ice_init_cgu_e822 - Initialize CGU with settings from firmware
1068 * @hw: pointer to the HW structure
1070 * Initialize the Clock Generation Unit of the E822 device.
1072 static int ice_init_cgu_e822(struct ice_hw *hw)
1074 struct ice_ts_func_info *ts_info = &hw->func_caps.ts_func_info;
1075 union tspll_cntr_bist_settings cntr_bist;
1078 err = ice_read_cgu_reg_e822(hw, TSPLL_CNTR_BIST_SETTINGS,
1083 /* Disable sticky lock detection so lock err reported is accurate */
1084 cntr_bist.field.i_plllock_sel_0 = 0;
1085 cntr_bist.field.i_plllock_sel_1 = 0;
1087 err = ice_write_cgu_reg_e822(hw, TSPLL_CNTR_BIST_SETTINGS,
1092 /* Configure the CGU PLL using the parameters from the function
1095 err = ice_cfg_cgu_pll_e822(hw, ts_info->time_ref,
1096 (enum ice_clk_src)ts_info->clk_src);
1104 * ice_ptp_set_vernier_wl - Set the window length for vernier calibration
1105 * @hw: pointer to the HW struct
1107 * Set the window length used for the vernier port calibration process.
1109 static int ice_ptp_set_vernier_wl(struct ice_hw *hw)
1113 for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) {
1116 err = ice_write_phy_reg_e822(hw, port, P_REG_WL,
1119 ice_debug(hw, ICE_DBG_PTP, "Failed to set vernier window length for port %u, err %d\n",
1129 * ice_ptp_init_phc_e822 - Perform E822 specific PHC initialization
1130 * @hw: pointer to HW struct
1132 * Perform PHC initialization steps specific to E822 devices.
1134 static int ice_ptp_init_phc_e822(struct ice_hw *hw)
1139 /* Enable reading switch and PHY registers over the sideband queue */
1140 #define PF_SB_REM_DEV_CTL_SWITCH_READ BIT(1)
1141 #define PF_SB_REM_DEV_CTL_PHY0 BIT(2)
1142 regval = rd32(hw, PF_SB_REM_DEV_CTL);
1143 regval |= (PF_SB_REM_DEV_CTL_SWITCH_READ |
1144 PF_SB_REM_DEV_CTL_PHY0);
1145 wr32(hw, PF_SB_REM_DEV_CTL, regval);
1147 /* Initialize the Clock Generation Unit */
1148 err = ice_init_cgu_e822(hw);
1152 /* Set window length for all the ports */
1153 return ice_ptp_set_vernier_wl(hw);
1157 * ice_ptp_prep_phy_time_e822 - Prepare PHY port with initial time
1158 * @hw: pointer to the HW struct
1159 * @time: Time to initialize the PHY port clocks to
1161 * Program the PHY port registers with a new initial time value. The port
1162 * clock will be initialized once the driver issues an ICE_PTP_INIT_TIME sync
1163 * command. The time value is the upper 32 bits of the PHY timer, usually in
1164 * units of nominal nanoseconds.
1167 ice_ptp_prep_phy_time_e822(struct ice_hw *hw, u32 time)
1173 /* The time represents the upper 32 bits of the PHY timer, so we need
1174 * to shift to account for this when programming.
1176 phy_time = (u64)time << 32;
1178 for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) {
1180 err = ice_write_64b_phy_reg_e822(hw, port,
1181 P_REG_TX_TIMER_INC_PRE_L,
1187 err = ice_write_64b_phy_reg_e822(hw, port,
1188 P_REG_RX_TIMER_INC_PRE_L,
1197 ice_debug(hw, ICE_DBG_PTP, "Failed to write init time for port %u, err %d\n",
1204 * ice_ptp_prep_port_adj_e822 - Prepare a single port for time adjust
1205 * @hw: pointer to HW struct
1206 * @port: Port number to be programmed
1207 * @time: time in cycles to adjust the port Tx and Rx clocks
1209 * Program the port for an atomic adjustment by writing the Tx and Rx timer
1210 * registers. The atomic adjustment won't be completed until the driver issues
1211 * an ICE_PTP_ADJ_TIME command.
1213 * Note that time is not in units of nanoseconds. It is in clock time
1214 * including the lower sub-nanosecond portion of the port timer.
1216 * Negative adjustments are supported using 2s complement arithmetic.
1219 ice_ptp_prep_port_adj_e822(struct ice_hw *hw, u8 port, s64 time)
1224 l_time = lower_32_bits(time);
1225 u_time = upper_32_bits(time);
1228 err = ice_write_phy_reg_e822(hw, port, P_REG_TX_TIMER_INC_PRE_L,
1233 err = ice_write_phy_reg_e822(hw, port, P_REG_TX_TIMER_INC_PRE_U,
1239 err = ice_write_phy_reg_e822(hw, port, P_REG_RX_TIMER_INC_PRE_L,
1244 err = ice_write_phy_reg_e822(hw, port, P_REG_RX_TIMER_INC_PRE_U,
1252 ice_debug(hw, ICE_DBG_PTP, "Failed to write time adjust for port %u, err %d\n",
1258 * ice_ptp_prep_phy_adj_e822 - Prep PHY ports for a time adjustment
1259 * @hw: pointer to HW struct
1260 * @adj: adjustment in nanoseconds
1262 * Prepare the PHY ports for an atomic time adjustment by programming the PHY
1263 * Tx and Rx port registers. The actual adjustment is completed by issuing an
1264 * ICE_PTP_ADJ_TIME or ICE_PTP_ADJ_TIME_AT_TIME sync command.
1267 ice_ptp_prep_phy_adj_e822(struct ice_hw *hw, s32 adj)
1272 /* The port clock supports adjustment of the sub-nanosecond portion of
1273 * the clock. We shift the provided adjustment in nanoseconds to
1274 * calculate the appropriate adjustment to program into the PHY ports.
1277 cycles = (s64)adj << 32;
1279 cycles = -(((s64)-adj) << 32);
1281 for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) {
1284 err = ice_ptp_prep_port_adj_e822(hw, port, cycles);
1293 * ice_ptp_prep_phy_incval_e822 - Prepare PHY ports for time adjustment
1294 * @hw: pointer to HW struct
1295 * @incval: new increment value to prepare
1297 * Prepare each of the PHY ports for a new increment value by programming the
1298 * port's TIMETUS registers. The new increment value will be updated after
1299 * issuing an ICE_PTP_INIT_INCVAL command.
1302 ice_ptp_prep_phy_incval_e822(struct ice_hw *hw, u64 incval)
1307 for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) {
1308 err = ice_write_40b_phy_reg_e822(hw, port, P_REG_TIMETUS_L,
1317 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval for port %u, err %d\n",
1324 * ice_ptp_read_port_capture - Read a port's local time capture
1325 * @hw: pointer to HW struct
1326 * @port: Port number to read
1327 * @tx_ts: on return, the Tx port time capture
1328 * @rx_ts: on return, the Rx port time capture
1330 * Read the port's Tx and Rx local time capture values.
1332 * Note this has no equivalent for the E810 devices.
1335 ice_ptp_read_port_capture(struct ice_hw *hw, u8 port, u64 *tx_ts, u64 *rx_ts)
1340 err = ice_read_64b_phy_reg_e822(hw, port, P_REG_TX_CAPTURE_L, tx_ts);
1342 ice_debug(hw, ICE_DBG_PTP, "Failed to read REG_TX_CAPTURE, err %d\n",
1347 ice_debug(hw, ICE_DBG_PTP, "tx_init = 0x%016llx\n",
1348 (unsigned long long)*tx_ts);
1351 err = ice_read_64b_phy_reg_e822(hw, port, P_REG_RX_CAPTURE_L, rx_ts);
1353 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_CAPTURE, err %d\n",
1358 ice_debug(hw, ICE_DBG_PTP, "rx_init = 0x%016llx\n",
1359 (unsigned long long)*rx_ts);
1365 * ice_ptp_write_port_cmd_e822 - Prepare a single PHY port for a timer command
1366 * @hw: pointer to HW struct
1367 * @port: Port to which cmd has to be sent
1368 * @cmd: Command to be sent to the port
1370 * Prepare the requested port for an upcoming timer sync command.
1372 * Do not use this function directly. If you want to configure exactly one
1373 * port, use ice_ptp_one_port_cmd() instead.
1376 ice_ptp_write_port_cmd_e822(struct ice_hw *hw, u8 port, enum ice_ptp_tmr_cmd cmd)
1382 tmr_idx = ice_get_ptp_src_clock_index(hw);
1383 cmd_val = tmr_idx << SEL_PHY_SRC;
1385 case ICE_PTP_INIT_TIME:
1386 cmd_val |= PHY_CMD_INIT_TIME;
1388 case ICE_PTP_INIT_INCVAL:
1389 cmd_val |= PHY_CMD_INIT_INCVAL;
1391 case ICE_PTP_ADJ_TIME:
1392 cmd_val |= PHY_CMD_ADJ_TIME;
1394 case ICE_PTP_READ_TIME:
1395 cmd_val |= PHY_CMD_READ_TIME;
1397 case ICE_PTP_ADJ_TIME_AT_TIME:
1398 cmd_val |= PHY_CMD_ADJ_TIME_AT_TIME;
1405 /* Read, modify, write */
1406 err = ice_read_phy_reg_e822(hw, port, P_REG_TX_TMR_CMD, &val);
1408 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_TMR_CMD, err %d\n",
1413 /* Modify necessary bits only and perform write */
1414 val &= ~TS_CMD_MASK;
1417 err = ice_write_phy_reg_e822(hw, port, P_REG_TX_TMR_CMD, val);
1419 ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_TMR_CMD, err %d\n",
1425 /* Read, modify, write */
1426 err = ice_read_phy_reg_e822(hw, port, P_REG_RX_TMR_CMD, &val);
1428 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_TMR_CMD, err %d\n",
1433 /* Modify necessary bits only and perform write */
1434 val &= ~TS_CMD_MASK;
1437 err = ice_write_phy_reg_e822(hw, port, P_REG_RX_TMR_CMD, val);
1439 ice_debug(hw, ICE_DBG_PTP, "Failed to write back RX_TMR_CMD, err %d\n",
1448 * ice_ptp_one_port_cmd - Prepare one port for a timer command
1449 * @hw: pointer to the HW struct
1450 * @configured_port: the port to configure with configured_cmd
1451 * @configured_cmd: timer command to prepare on the configured_port
1453 * Prepare the configured_port for the configured_cmd, and prepare all other
1454 * ports for ICE_PTP_NOP. This causes the configured_port to execute the
1455 * desired command while all other ports perform no operation.
1458 ice_ptp_one_port_cmd(struct ice_hw *hw, u8 configured_port,
1459 enum ice_ptp_tmr_cmd configured_cmd)
1463 for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) {
1464 enum ice_ptp_tmr_cmd cmd;
1467 if (port == configured_port)
1468 cmd = configured_cmd;
1472 err = ice_ptp_write_port_cmd_e822(hw, port, cmd);
1481 * ice_ptp_port_cmd_e822 - Prepare all ports for a timer command
1482 * @hw: pointer to the HW struct
1483 * @cmd: timer command to prepare
1485 * Prepare all ports connected to this device for an upcoming timer sync
1489 ice_ptp_port_cmd_e822(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd)
1493 for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) {
1496 err = ice_ptp_write_port_cmd_e822(hw, port, cmd);
1504 /* E822 Vernier calibration functions
1506 * The following functions are used as part of the vernier calibration of
1507 * a port. This calibration increases the precision of the timestamps on the
1512 * ice_phy_get_speed_and_fec_e822 - Get link speed and FEC based on serdes mode
1513 * @hw: pointer to HW struct
1514 * @port: the port to read from
1515 * @link_out: if non-NULL, holds link speed on success
1516 * @fec_out: if non-NULL, holds FEC algorithm on success
1518 * Read the serdes data for the PHY port and extract the link speed and FEC
1522 ice_phy_get_speed_and_fec_e822(struct ice_hw *hw, u8 port,
1523 enum ice_ptp_link_spd *link_out,
1524 enum ice_ptp_fec_mode *fec_out)
1526 enum ice_ptp_link_spd link;
1527 enum ice_ptp_fec_mode fec;
1531 err = ice_read_phy_reg_e822(hw, port, P_REG_LINK_SPEED, &serdes);
1533 ice_debug(hw, ICE_DBG_PTP, "Failed to read serdes info\n");
1537 /* Determine the FEC algorithm */
1538 fec = (enum ice_ptp_fec_mode)P_REG_LINK_SPEED_FEC_MODE(serdes);
1540 serdes &= P_REG_LINK_SPEED_SERDES_M;
1542 /* Determine the link speed */
1543 if (fec == ICE_PTP_FEC_MODE_RS_FEC) {
1545 case ICE_PTP_SERDES_25G:
1546 link = ICE_PTP_LNK_SPD_25G_RS;
1548 case ICE_PTP_SERDES_50G:
1549 link = ICE_PTP_LNK_SPD_50G_RS;
1551 case ICE_PTP_SERDES_100G:
1552 link = ICE_PTP_LNK_SPD_100G_RS;
1559 case ICE_PTP_SERDES_1G:
1560 link = ICE_PTP_LNK_SPD_1G;
1562 case ICE_PTP_SERDES_10G:
1563 link = ICE_PTP_LNK_SPD_10G;
1565 case ICE_PTP_SERDES_25G:
1566 link = ICE_PTP_LNK_SPD_25G;
1568 case ICE_PTP_SERDES_40G:
1569 link = ICE_PTP_LNK_SPD_40G;
1571 case ICE_PTP_SERDES_50G:
1572 link = ICE_PTP_LNK_SPD_50G;
1588 * ice_phy_cfg_lane_e822 - Configure PHY quad for single/multi-lane timestamp
1589 * @hw: pointer to HW struct
1590 * @port: to configure the quad for
1592 static void ice_phy_cfg_lane_e822(struct ice_hw *hw, u8 port)
1594 enum ice_ptp_link_spd link_spd;
1599 err = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, NULL);
1601 ice_debug(hw, ICE_DBG_PTP, "Failed to get PHY link speed, err %d\n",
1606 quad = port / ICE_PORTS_PER_QUAD;
1608 err = ice_read_quad_reg_e822(hw, quad, Q_REG_TX_MEM_GBL_CFG, &val);
1610 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEM_GLB_CFG, err %d\n",
1615 if (link_spd >= ICE_PTP_LNK_SPD_40G)
1616 val &= ~Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M;
1618 val |= Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M;
1620 err = ice_write_quad_reg_e822(hw, quad, Q_REG_TX_MEM_GBL_CFG, val);
1622 ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_MEM_GBL_CFG, err %d\n",
1629 * ice_phy_cfg_uix_e822 - Configure Serdes UI to TU conversion for E822
1630 * @hw: pointer to the HW structure
1631 * @port: the port to configure
1633 * Program the conversion ration of Serdes clock "unit intervals" (UIs) to PHC
1634 * hardware clock time units (TUs). That is, determine the number of TUs per
1635 * serdes unit interval, and program the UIX registers with this conversion.
1637 * This conversion is used as part of the calibration process when determining
1638 * the additional error of a timestamp vs the real time of transmission or
1639 * receipt of the packet.
1641 * Hardware uses the number of TUs per 66 UIs, written to the UIX registers
1642 * for the two main serdes clock rates, 10G/40G and 25G/100G serdes clocks.
1644 * To calculate the conversion ratio, we use the following facts:
1646 * a) the clock frequency in Hz (cycles per second)
1647 * b) the number of TUs per cycle (the increment value of the clock)
1648 * c) 1 second per 1 billion nanoseconds
1649 * d) the duration of 66 UIs in nanoseconds
1651 * Given these facts, we can use the following table to work out what ratios
1652 * to multiply in order to get the number of TUs per 66 UIs:
1654 * cycles | 1 second | incval (TUs) | nanoseconds
1655 * -------+--------------+--------------+-------------
1656 * second | 1 billion ns | cycle | 66 UIs
1658 * To perform the multiplication using integers without too much loss of
1659 * precision, we can take use the following equation:
1661 * (freq * incval * 6600 LINE_UI ) / ( 100 * 1 billion)
1663 * We scale up to using 6600 UI instead of 66 in order to avoid fractional
1664 * nanosecond UIs (66 UI at 10G/40G is 6.4 ns)
1666 * The increment value has a maximum expected range of about 34 bits, while
1667 * the frequency value is about 29 bits. Multiplying these values shouldn't
1668 * overflow the 64 bits. However, we must then further multiply them again by
1669 * the Serdes unit interval duration. To avoid overflow here, we split the
1670 * overall divide by 1e11 into a divide by 256 (shift down by 8 bits) and
1671 * a divide by 390,625,000. This does lose some precision, but avoids
1672 * miscalculation due to arithmetic overflow.
1674 static int ice_phy_cfg_uix_e822(struct ice_hw *hw, u8 port)
1676 u64 cur_freq, clk_incval, tu_per_sec, uix;
1679 cur_freq = ice_e822_pll_freq(ice_e822_time_ref(hw));
1680 clk_incval = ice_ptp_read_src_incval(hw);
1682 /* Calculate TUs per second divided by 256 */
1683 tu_per_sec = (cur_freq * clk_incval) >> 8;
1685 #define LINE_UI_10G_40G 640 /* 6600 UIs is 640 nanoseconds at 10Gb/40Gb */
1686 #define LINE_UI_25G_100G 256 /* 6600 UIs is 256 nanoseconds at 25Gb/100Gb */
1688 /* Program the 10Gb/40Gb conversion ratio */
1689 uix = div_u64(tu_per_sec * LINE_UI_10G_40G, 390625000);
1691 err = ice_write_64b_phy_reg_e822(hw, port, P_REG_UIX66_10G_40G_L,
1694 ice_debug(hw, ICE_DBG_PTP, "Failed to write UIX66_10G_40G, err %d\n",
1699 /* Program the 25Gb/100Gb conversion ratio */
1700 uix = div_u64(tu_per_sec * LINE_UI_25G_100G, 390625000);
1702 err = ice_write_64b_phy_reg_e822(hw, port, P_REG_UIX66_25G_100G_L,
1705 ice_debug(hw, ICE_DBG_PTP, "Failed to write UIX66_25G_100G, err %d\n",
1714 * ice_phy_cfg_parpcs_e822 - Configure TUs per PAR/PCS clock cycle
1715 * @hw: pointer to the HW struct
1716 * @port: port to configure
1718 * Configure the number of TUs for the PAR and PCS clocks used as part of the
1719 * timestamp calibration process. This depends on the link speed, as the PHY
1720 * uses different markers depending on the speed.
1723 * - Tx/Rx PAR/PCS markers
1726 * - Tx/Rx Reed Solomon gearbox PAR/PCS markers
1729 * - Tx/Rx PAR/PCS markers
1730 * - Rx Deskew PAR/PCS markers
1732 * 50G RS and 100GB RS:
1733 * - Tx/Rx Reed Solomon gearbox PAR/PCS markers
1734 * - Rx Deskew PAR/PCS markers
1735 * - Tx PAR/PCS markers
1737 * To calculate the conversion, we use the PHC clock frequency (cycles per
1738 * second), the increment value (TUs per cycle), and the related PHY clock
1739 * frequency to calculate the TUs per unit of the PHY link clock. The
1740 * following table shows how the units convert:
1742 * cycles | TUs | second
1743 * -------+-------+--------
1744 * second | cycle | cycles
1746 * For each conversion register, look up the appropriate frequency from the
1747 * e822 PAR/PCS table and calculate the TUs per unit of that clock. Program
1748 * this to the appropriate register, preparing hardware to perform timestamp
1749 * calibration to calculate the total Tx or Rx offset to adjust the timestamp
1750 * in order to calibrate for the internal PHY delays.
1752 * Note that the increment value ranges up to ~34 bits, and the clock
1753 * frequency is ~29 bits, so multiplying them together should fit within the
1754 * 64 bit arithmetic.
1756 static int ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port)
1758 u64 cur_freq, clk_incval, tu_per_sec, phy_tus;
1759 enum ice_ptp_link_spd link_spd;
1760 enum ice_ptp_fec_mode fec_mode;
1763 err = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode);
1767 cur_freq = ice_e822_pll_freq(ice_e822_time_ref(hw));
1768 clk_incval = ice_ptp_read_src_incval(hw);
1770 /* Calculate TUs per cycle of the PHC clock */
1771 tu_per_sec = cur_freq * clk_incval;
1773 /* For each PHY conversion register, look up the appropriate link
1774 * speed frequency and determine the TUs per that clock's cycle time.
1775 * Split this into a high and low value and then program the
1776 * appropriate register. If that link speed does not use the
1777 * associated register, write zeros to clear it instead.
1780 /* P_REG_PAR_TX_TUS */
1781 if (e822_vernier[link_spd].tx_par_clk)
1782 phy_tus = div_u64(tu_per_sec,
1783 e822_vernier[link_spd].tx_par_clk);
1787 err = ice_write_40b_phy_reg_e822(hw, port, P_REG_PAR_TX_TUS_L,
1792 /* P_REG_PAR_RX_TUS */
1793 if (e822_vernier[link_spd].rx_par_clk)
1794 phy_tus = div_u64(tu_per_sec,
1795 e822_vernier[link_spd].rx_par_clk);
1799 err = ice_write_40b_phy_reg_e822(hw, port, P_REG_PAR_RX_TUS_L,
1804 /* P_REG_PCS_TX_TUS */
1805 if (e822_vernier[link_spd].tx_pcs_clk)
1806 phy_tus = div_u64(tu_per_sec,
1807 e822_vernier[link_spd].tx_pcs_clk);
1811 err = ice_write_40b_phy_reg_e822(hw, port, P_REG_PCS_TX_TUS_L,
1816 /* P_REG_PCS_RX_TUS */
1817 if (e822_vernier[link_spd].rx_pcs_clk)
1818 phy_tus = div_u64(tu_per_sec,
1819 e822_vernier[link_spd].rx_pcs_clk);
1823 err = ice_write_40b_phy_reg_e822(hw, port, P_REG_PCS_RX_TUS_L,
1828 /* P_REG_DESK_PAR_TX_TUS */
1829 if (e822_vernier[link_spd].tx_desk_rsgb_par)
1830 phy_tus = div_u64(tu_per_sec,
1831 e822_vernier[link_spd].tx_desk_rsgb_par);
1835 err = ice_write_40b_phy_reg_e822(hw, port, P_REG_DESK_PAR_TX_TUS_L,
1840 /* P_REG_DESK_PAR_RX_TUS */
1841 if (e822_vernier[link_spd].rx_desk_rsgb_par)
1842 phy_tus = div_u64(tu_per_sec,
1843 e822_vernier[link_spd].rx_desk_rsgb_par);
1847 err = ice_write_40b_phy_reg_e822(hw, port, P_REG_DESK_PAR_RX_TUS_L,
1852 /* P_REG_DESK_PCS_TX_TUS */
1853 if (e822_vernier[link_spd].tx_desk_rsgb_pcs)
1854 phy_tus = div_u64(tu_per_sec,
1855 e822_vernier[link_spd].tx_desk_rsgb_pcs);
1859 err = ice_write_40b_phy_reg_e822(hw, port, P_REG_DESK_PCS_TX_TUS_L,
1864 /* P_REG_DESK_PCS_RX_TUS */
1865 if (e822_vernier[link_spd].rx_desk_rsgb_pcs)
1866 phy_tus = div_u64(tu_per_sec,
1867 e822_vernier[link_spd].rx_desk_rsgb_pcs);
1871 return ice_write_40b_phy_reg_e822(hw, port, P_REG_DESK_PCS_RX_TUS_L,
1876 * ice_calc_fixed_tx_offset_e822 - Calculated Fixed Tx offset for a port
1877 * @hw: pointer to the HW struct
1878 * @link_spd: the Link speed to calculate for
1880 * Calculate the fixed offset due to known static latency data.
1883 ice_calc_fixed_tx_offset_e822(struct ice_hw *hw, enum ice_ptp_link_spd link_spd)
1885 u64 cur_freq, clk_incval, tu_per_sec, fixed_offset;
1887 cur_freq = ice_e822_pll_freq(ice_e822_time_ref(hw));
1888 clk_incval = ice_ptp_read_src_incval(hw);
1890 /* Calculate TUs per second */
1891 tu_per_sec = cur_freq * clk_incval;
1893 /* Calculate number of TUs to add for the fixed Tx latency. Since the
1894 * latency measurement is in 1/100th of a nanosecond, we need to
1895 * multiply by tu_per_sec and then divide by 1e11. This calculation
1896 * overflows 64 bit integer arithmetic, so break it up into two
1897 * divisions by 1e4 first then by 1e7.
1899 fixed_offset = div_u64(tu_per_sec, 10000);
1900 fixed_offset *= e822_vernier[link_spd].tx_fixed_delay;
1901 fixed_offset = div_u64(fixed_offset, 10000000);
1903 return fixed_offset;
1907 * ice_phy_cfg_tx_offset_e822 - Configure total Tx timestamp offset
1908 * @hw: pointer to the HW struct
1909 * @port: the PHY port to configure
1911 * Program the P_REG_TOTAL_TX_OFFSET register with the total number of TUs to
1912 * adjust Tx timestamps by. This is calculated by combining some known static
1913 * latency along with the Vernier offset computations done by hardware.
1915 * This function will not return successfully until the Tx offset calculations
1916 * have been completed, which requires waiting until at least one packet has
1917 * been transmitted by the device. It is safe to call this function
1918 * periodically until calibration succeeds, as it will only program the offset
1921 * To avoid overflow, when calculating the offset based on the known static
1922 * latency values, we use measurements in 1/100th of a nanosecond, and divide
1923 * the TUs per second up front. This avoids overflow while allowing
1924 * calculation of the adjustment using integer arithmetic.
1926 * Returns zero on success, -EBUSY if the hardware vernier offset
1927 * calibration has not completed, or another error code on failure.
1929 int ice_phy_cfg_tx_offset_e822(struct ice_hw *hw, u8 port)
1931 enum ice_ptp_link_spd link_spd;
1932 enum ice_ptp_fec_mode fec_mode;
1933 u64 total_offset, val;
1937 /* Nothing to do if we've already programmed the offset */
1938 err = ice_read_phy_reg_e822(hw, port, P_REG_TX_OR, ®);
1940 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_OR for port %u, err %d\n",
1948 err = ice_read_phy_reg_e822(hw, port, P_REG_TX_OV_STATUS, ®);
1950 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_OV_STATUS for port %u, err %d\n",
1955 if (!(reg & P_REG_TX_OV_STATUS_OV_M))
1958 err = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode);
1962 total_offset = ice_calc_fixed_tx_offset_e822(hw, link_spd);
1964 /* Read the first Vernier offset from the PHY register and add it to
1967 if (link_spd == ICE_PTP_LNK_SPD_1G ||
1968 link_spd == ICE_PTP_LNK_SPD_10G ||
1969 link_spd == ICE_PTP_LNK_SPD_25G ||
1970 link_spd == ICE_PTP_LNK_SPD_25G_RS ||
1971 link_spd == ICE_PTP_LNK_SPD_40G ||
1972 link_spd == ICE_PTP_LNK_SPD_50G) {
1973 err = ice_read_64b_phy_reg_e822(hw, port,
1974 P_REG_PAR_PCS_TX_OFFSET_L,
1979 total_offset += val;
1982 /* For Tx, we only need to use the second Vernier offset for
1983 * multi-lane link speeds with RS-FEC. The lanes will always be
1986 if (link_spd == ICE_PTP_LNK_SPD_50G_RS ||
1987 link_spd == ICE_PTP_LNK_SPD_100G_RS) {
1988 err = ice_read_64b_phy_reg_e822(hw, port,
1989 P_REG_PAR_TX_TIME_L,
1994 total_offset += val;
1997 /* Now that the total offset has been calculated, program it to the
1998 * PHY and indicate that the Tx offset is ready. After this,
1999 * timestamps will be enabled.
2001 err = ice_write_64b_phy_reg_e822(hw, port, P_REG_TOTAL_TX_OFFSET_L,
2006 err = ice_write_phy_reg_e822(hw, port, P_REG_TX_OR, 1);
2010 dev_info(ice_hw_to_dev(hw), "Port=%d Tx vernier offset calibration complete\n",
2017 * ice_phy_calc_pmd_adj_e822 - Calculate PMD adjustment for Rx
2018 * @hw: pointer to the HW struct
2019 * @port: the PHY port to adjust for
2020 * @link_spd: the current link speed of the PHY
2021 * @fec_mode: the current FEC mode of the PHY
2022 * @pmd_adj: on return, the amount to adjust the Rx total offset by
2024 * Calculates the adjustment to Rx timestamps due to PMD alignment in the PHY.
2025 * This varies by link speed and FEC mode. The value calculated accounts for
2026 * various delays caused when receiving a packet.
2029 ice_phy_calc_pmd_adj_e822(struct ice_hw *hw, u8 port,
2030 enum ice_ptp_link_spd link_spd,
2031 enum ice_ptp_fec_mode fec_mode, u64 *pmd_adj)
2033 u64 cur_freq, clk_incval, tu_per_sec, mult, adj;
2038 err = ice_read_phy_reg_e822(hw, port, P_REG_PMD_ALIGNMENT, &val);
2040 ice_debug(hw, ICE_DBG_PTP, "Failed to read PMD alignment, err %d\n",
2045 pmd_align = (u8)val;
2047 cur_freq = ice_e822_pll_freq(ice_e822_time_ref(hw));
2048 clk_incval = ice_ptp_read_src_incval(hw);
2050 /* Calculate TUs per second */
2051 tu_per_sec = cur_freq * clk_incval;
2053 /* The PMD alignment adjustment measurement depends on the link speed,
2054 * and whether FEC is enabled. For each link speed, the alignment
2055 * adjustment is calculated by dividing a value by the length of
2056 * a Time Unit in nanoseconds.
2058 * 1G: align == 4 ? 10 * 0.8 : (align + 6 % 10) * 0.8
2059 * 10G: align == 65 ? 0 : (align * 0.1 * 32/33)
2060 * 10G w/FEC: align * 0.1 * 32/33
2061 * 25G: align == 65 ? 0 : (align * 0.4 * 32/33)
2062 * 25G w/FEC: align * 0.4 * 32/33
2063 * 40G: align == 65 ? 0 : (align * 0.1 * 32/33)
2064 * 40G w/FEC: align * 0.1 * 32/33
2065 * 50G: align == 65 ? 0 : (align * 0.4 * 32/33)
2066 * 50G w/FEC: align * 0.8 * 32/33
2068 * For RS-FEC, if align is < 17 then we must also add 1.6 * 32/33.
2070 * To allow for calculating this value using integer arithmetic, we
2071 * instead start with the number of TUs per second, (inverse of the
2072 * length of a Time Unit in nanoseconds), multiply by a value based
2073 * on the PMD alignment register, and then divide by the right value
2074 * calculated based on the table above. To avoid integer overflow this
2075 * division is broken up into a step of dividing by 125 first.
2077 if (link_spd == ICE_PTP_LNK_SPD_1G) {
2081 mult = (pmd_align + 6) % 10;
2082 } else if (link_spd == ICE_PTP_LNK_SPD_10G ||
2083 link_spd == ICE_PTP_LNK_SPD_25G ||
2084 link_spd == ICE_PTP_LNK_SPD_40G ||
2085 link_spd == ICE_PTP_LNK_SPD_50G) {
2086 /* If Clause 74 FEC, always calculate PMD adjust */
2087 if (pmd_align != 65 || fec_mode == ICE_PTP_FEC_MODE_CLAUSE74)
2091 } else if (link_spd == ICE_PTP_LNK_SPD_25G_RS ||
2092 link_spd == ICE_PTP_LNK_SPD_50G_RS ||
2093 link_spd == ICE_PTP_LNK_SPD_100G_RS) {
2095 mult = pmd_align + 40;
2099 ice_debug(hw, ICE_DBG_PTP, "Unknown link speed %d, skipping PMD adjustment\n",
2104 /* In some cases, there's no need to adjust for the PMD alignment */
2110 /* Calculate the adjustment by multiplying TUs per second by the
2111 * appropriate multiplier and divisor. To avoid overflow, we first
2112 * divide by 125, and then handle remaining divisor based on the link
2113 * speed pmd_adj_divisor value.
2115 adj = div_u64(tu_per_sec, 125);
2117 adj = div_u64(adj, e822_vernier[link_spd].pmd_adj_divisor);
2119 /* Finally, for 25G-RS and 50G-RS, a further adjustment for the Rx
2120 * cycle count is necessary.
2122 if (link_spd == ICE_PTP_LNK_SPD_25G_RS) {
2126 err = ice_read_phy_reg_e822(hw, port, P_REG_RX_40_TO_160_CNT,
2129 ice_debug(hw, ICE_DBG_PTP, "Failed to read 25G-RS Rx cycle count, err %d\n",
2134 rx_cycle = val & P_REG_RX_40_TO_160_CNT_RXCYC_M;
2136 mult = (4 - rx_cycle) * 40;
2138 cycle_adj = div_u64(tu_per_sec, 125);
2140 cycle_adj = div_u64(cycle_adj, e822_vernier[link_spd].pmd_adj_divisor);
2144 } else if (link_spd == ICE_PTP_LNK_SPD_50G_RS) {
2148 err = ice_read_phy_reg_e822(hw, port, P_REG_RX_80_TO_160_CNT,
2151 ice_debug(hw, ICE_DBG_PTP, "Failed to read 50G-RS Rx cycle count, err %d\n",
2156 rx_cycle = val & P_REG_RX_80_TO_160_CNT_RXCYC_M;
2158 mult = rx_cycle * 40;
2160 cycle_adj = div_u64(tu_per_sec, 125);
2162 cycle_adj = div_u64(cycle_adj, e822_vernier[link_spd].pmd_adj_divisor);
2168 /* Return the calculated adjustment */
2175 * ice_calc_fixed_rx_offset_e822 - Calculated the fixed Rx offset for a port
2176 * @hw: pointer to HW struct
2177 * @link_spd: The Link speed to calculate for
2179 * Determine the fixed Rx latency for a given link speed.
2182 ice_calc_fixed_rx_offset_e822(struct ice_hw *hw, enum ice_ptp_link_spd link_spd)
2184 u64 cur_freq, clk_incval, tu_per_sec, fixed_offset;
2186 cur_freq = ice_e822_pll_freq(ice_e822_time_ref(hw));
2187 clk_incval = ice_ptp_read_src_incval(hw);
2189 /* Calculate TUs per second */
2190 tu_per_sec = cur_freq * clk_incval;
2192 /* Calculate number of TUs to add for the fixed Rx latency. Since the
2193 * latency measurement is in 1/100th of a nanosecond, we need to
2194 * multiply by tu_per_sec and then divide by 1e11. This calculation
2195 * overflows 64 bit integer arithmetic, so break it up into two
2196 * divisions by 1e4 first then by 1e7.
2198 fixed_offset = div_u64(tu_per_sec, 10000);
2199 fixed_offset *= e822_vernier[link_spd].rx_fixed_delay;
2200 fixed_offset = div_u64(fixed_offset, 10000000);
2202 return fixed_offset;
2206 * ice_phy_cfg_rx_offset_e822 - Configure total Rx timestamp offset
2207 * @hw: pointer to the HW struct
2208 * @port: the PHY port to configure
2210 * Program the P_REG_TOTAL_RX_OFFSET register with the number of Time Units to
2211 * adjust Rx timestamps by. This combines calculations from the Vernier offset
2212 * measurements taken in hardware with some data about known fixed delay as
2213 * well as adjusting for multi-lane alignment delay.
2215 * This function will not return successfully until the Rx offset calculations
2216 * have been completed, which requires waiting until at least one packet has
2217 * been received by the device. It is safe to call this function periodically
2218 * until calibration succeeds, as it will only program the offset once.
2220 * This function must be called only after the offset registers are valid,
2221 * i.e. after the Vernier calibration wait has passed, to ensure that the PHY
2222 * has measured the offset.
2224 * To avoid overflow, when calculating the offset based on the known static
2225 * latency values, we use measurements in 1/100th of a nanosecond, and divide
2226 * the TUs per second up front. This avoids overflow while allowing
2227 * calculation of the adjustment using integer arithmetic.
2229 * Returns zero on success, -EBUSY if the hardware vernier offset
2230 * calibration has not completed, or another error code on failure.
2232 int ice_phy_cfg_rx_offset_e822(struct ice_hw *hw, u8 port)
2234 enum ice_ptp_link_spd link_spd;
2235 enum ice_ptp_fec_mode fec_mode;
2236 u64 total_offset, pmd, val;
2240 /* Nothing to do if we've already programmed the offset */
2241 err = ice_read_phy_reg_e822(hw, port, P_REG_RX_OR, ®);
2243 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_OR for port %u, err %d\n",
2251 err = ice_read_phy_reg_e822(hw, port, P_REG_RX_OV_STATUS, ®);
2253 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_OV_STATUS for port %u, err %d\n",
2258 if (!(reg & P_REG_RX_OV_STATUS_OV_M))
2261 err = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode);
2265 total_offset = ice_calc_fixed_rx_offset_e822(hw, link_spd);
2267 /* Read the first Vernier offset from the PHY register and add it to
2270 err = ice_read_64b_phy_reg_e822(hw, port,
2271 P_REG_PAR_PCS_RX_OFFSET_L,
2276 total_offset += val;
2278 /* For Rx, all multi-lane link speeds include a second Vernier
2279 * calibration, because the lanes might not be aligned.
2281 if (link_spd == ICE_PTP_LNK_SPD_40G ||
2282 link_spd == ICE_PTP_LNK_SPD_50G ||
2283 link_spd == ICE_PTP_LNK_SPD_50G_RS ||
2284 link_spd == ICE_PTP_LNK_SPD_100G_RS) {
2285 err = ice_read_64b_phy_reg_e822(hw, port,
2286 P_REG_PAR_RX_TIME_L,
2291 total_offset += val;
2294 /* In addition, Rx must account for the PMD alignment */
2295 err = ice_phy_calc_pmd_adj_e822(hw, port, link_spd, fec_mode, &pmd);
2299 /* For RS-FEC, this adjustment adds delay, but for other modes, it
2302 if (fec_mode == ICE_PTP_FEC_MODE_RS_FEC)
2303 total_offset += pmd;
2305 total_offset -= pmd;
2307 /* Now that the total offset has been calculated, program it to the
2308 * PHY and indicate that the Rx offset is ready. After this,
2309 * timestamps will be enabled.
2311 err = ice_write_64b_phy_reg_e822(hw, port, P_REG_TOTAL_RX_OFFSET_L,
2316 err = ice_write_phy_reg_e822(hw, port, P_REG_RX_OR, 1);
2320 dev_info(ice_hw_to_dev(hw), "Port=%d Rx vernier offset calibration complete\n",
2327 * ice_read_phy_and_phc_time_e822 - Simultaneously capture PHC and PHY time
2328 * @hw: pointer to the HW struct
2329 * @port: the PHY port to read
2330 * @phy_time: on return, the 64bit PHY timer value
2331 * @phc_time: on return, the lower 64bits of PHC time
2333 * Issue a ICE_PTP_READ_TIME timer command to simultaneously capture the PHY
2334 * and PHC timer values.
2337 ice_read_phy_and_phc_time_e822(struct ice_hw *hw, u8 port, u64 *phy_time,
2340 u64 tx_time, rx_time;
2345 tmr_idx = ice_get_ptp_src_clock_index(hw);
2347 /* Prepare the PHC timer for a ICE_PTP_READ_TIME capture command */
2348 ice_ptp_src_cmd(hw, ICE_PTP_READ_TIME);
2350 /* Prepare the PHY timer for a ICE_PTP_READ_TIME capture command */
2351 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_READ_TIME);
2355 /* Issue the sync to start the ICE_PTP_READ_TIME capture */
2356 ice_ptp_exec_tmr_cmd(hw);
2358 /* Read the captured PHC time from the shadow time registers */
2359 zo = rd32(hw, GLTSYN_SHTIME_0(tmr_idx));
2360 lo = rd32(hw, GLTSYN_SHTIME_L(tmr_idx));
2361 *phc_time = (u64)lo << 32 | zo;
2363 /* Read the captured PHY time from the PHY shadow registers */
2364 err = ice_ptp_read_port_capture(hw, port, &tx_time, &rx_time);
2368 /* If the PHY Tx and Rx timers don't match, log a warning message.
2369 * Note that this should not happen in normal circumstances since the
2370 * driver always programs them together.
2372 if (tx_time != rx_time)
2373 dev_warn(ice_hw_to_dev(hw),
2374 "PHY port %u Tx and Rx timers do not match, tx_time 0x%016llX, rx_time 0x%016llX\n",
2375 port, (unsigned long long)tx_time,
2376 (unsigned long long)rx_time);
2378 *phy_time = tx_time;
2384 * ice_sync_phy_timer_e822 - Synchronize the PHY timer with PHC timer
2385 * @hw: pointer to the HW struct
2386 * @port: the PHY port to synchronize
2388 * Perform an adjustment to ensure that the PHY and PHC timers are in sync.
2389 * This is done by issuing a ICE_PTP_READ_TIME command which triggers a
2390 * simultaneous read of the PHY timer and PHC timer. Then we use the
2391 * difference to calculate an appropriate 2s complement addition to add
2392 * to the PHY timer in order to ensure it reads the same value as the
2393 * primary PHC timer.
2395 static int ice_sync_phy_timer_e822(struct ice_hw *hw, u8 port)
2397 u64 phc_time, phy_time, difference;
2400 if (!ice_ptp_lock(hw)) {
2401 ice_debug(hw, ICE_DBG_PTP, "Failed to acquire PTP semaphore\n");
2405 err = ice_read_phy_and_phc_time_e822(hw, port, &phy_time, &phc_time);
2409 /* Calculate the amount required to add to the port time in order for
2410 * it to match the PHC time.
2412 * Note that the port adjustment is done using 2s complement
2413 * arithmetic. This is convenient since it means that we can simply
2414 * calculate the difference between the PHC time and the port time,
2415 * and it will be interpreted correctly.
2417 difference = phc_time - phy_time;
2419 err = ice_ptp_prep_port_adj_e822(hw, port, (s64)difference);
2423 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_ADJ_TIME);
2427 /* Do not perform any action on the main timer */
2428 ice_ptp_src_cmd(hw, ICE_PTP_NOP);
2430 /* Issue the sync to activate the time adjustment */
2431 ice_ptp_exec_tmr_cmd(hw);
2433 /* Re-capture the timer values to flush the command registers and
2434 * verify that the time was properly adjusted.
2436 err = ice_read_phy_and_phc_time_e822(hw, port, &phy_time, &phc_time);
2440 dev_info(ice_hw_to_dev(hw),
2441 "Port %u PHY time synced to PHC: 0x%016llX, 0x%016llX\n",
2442 port, (unsigned long long)phy_time,
2443 (unsigned long long)phc_time);
2455 * ice_stop_phy_timer_e822 - Stop the PHY clock timer
2456 * @hw: pointer to the HW struct
2457 * @port: the PHY port to stop
2458 * @soft_reset: if true, hold the SOFT_RESET bit of P_REG_PS
2460 * Stop the clock of a PHY port. This must be done as part of the flow to
2461 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is
2462 * initialized or when link speed changes.
2465 ice_stop_phy_timer_e822(struct ice_hw *hw, u8 port, bool soft_reset)
2470 err = ice_write_phy_reg_e822(hw, port, P_REG_TX_OR, 0);
2474 err = ice_write_phy_reg_e822(hw, port, P_REG_RX_OR, 0);
2478 err = ice_read_phy_reg_e822(hw, port, P_REG_PS, &val);
2482 val &= ~P_REG_PS_START_M;
2483 err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
2487 val &= ~P_REG_PS_ENA_CLK_M;
2488 err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
2493 val |= P_REG_PS_SFT_RESET_M;
2494 err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
2499 ice_debug(hw, ICE_DBG_PTP, "Disabled clock on PHY port %u\n", port);
2505 * ice_start_phy_timer_e822 - Start the PHY clock timer
2506 * @hw: pointer to the HW struct
2507 * @port: the PHY port to start
2509 * Start the clock of a PHY port. This must be done as part of the flow to
2510 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is
2511 * initialized or when link speed changes.
2513 * Hardware will take Vernier measurements on Tx or Rx of packets.
2515 int ice_start_phy_timer_e822(struct ice_hw *hw, u8 port)
2522 tmr_idx = ice_get_ptp_src_clock_index(hw);
2524 err = ice_stop_phy_timer_e822(hw, port, false);
2528 ice_phy_cfg_lane_e822(hw, port);
2530 err = ice_phy_cfg_uix_e822(hw, port);
2534 err = ice_phy_cfg_parpcs_e822(hw, port);
2538 lo = rd32(hw, GLTSYN_INCVAL_L(tmr_idx));
2539 hi = rd32(hw, GLTSYN_INCVAL_H(tmr_idx));
2540 incval = (u64)hi << 32 | lo;
2542 err = ice_write_40b_phy_reg_e822(hw, port, P_REG_TIMETUS_L, incval);
2546 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_INIT_INCVAL);
2550 /* Do not perform any action on the main timer */
2551 ice_ptp_src_cmd(hw, ICE_PTP_NOP);
2553 ice_ptp_exec_tmr_cmd(hw);
2555 err = ice_read_phy_reg_e822(hw, port, P_REG_PS, &val);
2559 val |= P_REG_PS_SFT_RESET_M;
2560 err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
2564 val |= P_REG_PS_START_M;
2565 err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
2569 val &= ~P_REG_PS_SFT_RESET_M;
2570 err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
2574 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_INIT_INCVAL);
2578 ice_ptp_exec_tmr_cmd(hw);
2580 val |= P_REG_PS_ENA_CLK_M;
2581 err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
2585 val |= P_REG_PS_LOAD_OFFSET_M;
2586 err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
2590 ice_ptp_exec_tmr_cmd(hw);
2592 err = ice_sync_phy_timer_e822(hw, port);
2596 ice_debug(hw, ICE_DBG_PTP, "Enabled clock on PHY port %u\n", port);
2602 * ice_get_phy_tx_tstamp_ready_e822 - Read Tx memory status register
2603 * @hw: pointer to the HW struct
2604 * @quad: the timestamp quad to read from
2605 * @tstamp_ready: contents of the Tx memory status register
2607 * Read the Q_REG_TX_MEMORY_STATUS register indicating which timestamps in
2608 * the PHY are ready. A set bit means the corresponding timestamp is valid and
2609 * ready to be captured from the PHY timestamp block.
2612 ice_get_phy_tx_tstamp_ready_e822(struct ice_hw *hw, u8 quad, u64 *tstamp_ready)
2617 err = ice_read_quad_reg_e822(hw, quad, Q_REG_TX_MEMORY_STATUS_U, &hi);
2619 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS_U for quad %u, err %d\n",
2624 err = ice_read_quad_reg_e822(hw, quad, Q_REG_TX_MEMORY_STATUS_L, &lo);
2626 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS_L for quad %u, err %d\n",
2631 *tstamp_ready = (u64)hi << 32 | (u64)lo;
2638 * The following functions operate on the E810 series devices which use
2639 * a separate external PHY.
2643 * ice_read_phy_reg_e810 - Read register from external PHY on E810
2644 * @hw: pointer to the HW struct
2645 * @addr: the address to read from
2646 * @val: On return, the value read from the PHY
2648 * Read a register from the external PHY on the E810 device.
2650 static int ice_read_phy_reg_e810(struct ice_hw *hw, u32 addr, u32 *val)
2652 struct ice_sbq_msg_input msg = {0};
2655 msg.msg_addr_low = lower_16_bits(addr);
2656 msg.msg_addr_high = upper_16_bits(addr);
2657 msg.opcode = ice_sbq_msg_rd;
2658 msg.dest_dev = rmn_0;
2660 err = ice_sbq_rw_reg(hw, &msg);
2662 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n",
2673 * ice_write_phy_reg_e810 - Write register on external PHY on E810
2674 * @hw: pointer to the HW struct
2675 * @addr: the address to writem to
2676 * @val: the value to write to the PHY
2678 * Write a value to a register of the external PHY on the E810 device.
2680 static int ice_write_phy_reg_e810(struct ice_hw *hw, u32 addr, u32 val)
2682 struct ice_sbq_msg_input msg = {0};
2685 msg.msg_addr_low = lower_16_bits(addr);
2686 msg.msg_addr_high = upper_16_bits(addr);
2687 msg.opcode = ice_sbq_msg_wr;
2688 msg.dest_dev = rmn_0;
2691 err = ice_sbq_rw_reg(hw, &msg);
2693 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n",
2702 * ice_read_phy_tstamp_ll_e810 - Read a PHY timestamp registers through the FW
2703 * @hw: pointer to the HW struct
2704 * @idx: the timestamp index to read
2705 * @hi: 8 bit timestamp high value
2706 * @lo: 32 bit timestamp low value
2708 * Read a 8bit timestamp high value and 32 bit timestamp low value out of the
2709 * timestamp block of the external PHY on the E810 device using the low latency
2713 ice_read_phy_tstamp_ll_e810(struct ice_hw *hw, u8 idx, u8 *hi, u32 *lo)
2718 /* Write TS index to read to the PF register so the FW can read it */
2719 val = FIELD_PREP(TS_LL_READ_TS_IDX, idx) | TS_LL_READ_TS;
2720 wr32(hw, PF_SB_ATQBAL, val);
2722 /* Read the register repeatedly until the FW provides us the TS */
2723 for (i = TS_LL_READ_RETRIES; i > 0; i--) {
2724 val = rd32(hw, PF_SB_ATQBAL);
2726 /* When the bit is cleared, the TS is ready in the register */
2727 if (!(FIELD_GET(TS_LL_READ_TS, val))) {
2728 /* High 8 bit value of the TS is on the bits 16:23 */
2729 *hi = FIELD_GET(TS_LL_READ_TS_HIGH, val);
2731 /* Read the low 32 bit value and set the TS valid bit */
2732 *lo = rd32(hw, PF_SB_ATQBAH) | TS_VALID;
2739 /* FW failed to provide the TS in time */
2740 ice_debug(hw, ICE_DBG_PTP, "Failed to read PTP timestamp using low latency read\n");
2745 * ice_read_phy_tstamp_sbq_e810 - Read a PHY timestamp registers through the sbq
2746 * @hw: pointer to the HW struct
2747 * @lport: the lport to read from
2748 * @idx: the timestamp index to read
2749 * @hi: 8 bit timestamp high value
2750 * @lo: 32 bit timestamp low value
2752 * Read a 8bit timestamp high value and 32 bit timestamp low value out of the
2753 * timestamp block of the external PHY on the E810 device using sideband queue.
2756 ice_read_phy_tstamp_sbq_e810(struct ice_hw *hw, u8 lport, u8 idx, u8 *hi,
2759 u32 hi_addr = TS_EXT(HIGH_TX_MEMORY_BANK_START, lport, idx);
2760 u32 lo_addr = TS_EXT(LOW_TX_MEMORY_BANK_START, lport, idx);
2764 err = ice_read_phy_reg_e810(hw, lo_addr, &lo_val);
2766 ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, err %d\n",
2771 err = ice_read_phy_reg_e810(hw, hi_addr, &hi_val);
2773 ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, err %d\n",
2785 * ice_read_phy_tstamp_e810 - Read a PHY timestamp out of the external PHY
2786 * @hw: pointer to the HW struct
2787 * @lport: the lport to read from
2788 * @idx: the timestamp index to read
2789 * @tstamp: on return, the 40bit timestamp value
2791 * Read a 40bit timestamp value out of the timestamp block of the external PHY
2792 * on the E810 device.
2795 ice_read_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx, u64 *tstamp)
2801 if (hw->dev_caps.ts_dev_info.ts_ll_read)
2802 err = ice_read_phy_tstamp_ll_e810(hw, idx, &hi, &lo);
2804 err = ice_read_phy_tstamp_sbq_e810(hw, lport, idx, &hi, &lo);
2809 /* For E810 devices, the timestamp is reported with the lower 32 bits
2810 * in the low register, and the upper 8 bits in the high register.
2812 *tstamp = ((u64)hi) << TS_HIGH_S | ((u64)lo & TS_LOW_M);
2818 * ice_clear_phy_tstamp_e810 - Clear a timestamp from the external PHY
2819 * @hw: pointer to the HW struct
2820 * @lport: the lport to read from
2821 * @idx: the timestamp index to reset
2823 * Read the timestamp and then forcibly overwrite its value to clear the valid
2824 * bit from the timestamp block of the external PHY on the E810 device.
2826 * This function should only be called on an idx whose bit is set according to
2827 * ice_get_phy_tx_tstamp_ready().
2829 static int ice_clear_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx)
2831 u32 lo_addr, hi_addr;
2835 err = ice_read_phy_tstamp_e810(hw, lport, idx, &unused_tstamp);
2837 ice_debug(hw, ICE_DBG_PTP, "Failed to read the timestamp register for lport %u, idx %u, err %d\n",
2842 lo_addr = TS_EXT(LOW_TX_MEMORY_BANK_START, lport, idx);
2843 hi_addr = TS_EXT(HIGH_TX_MEMORY_BANK_START, lport, idx);
2845 err = ice_write_phy_reg_e810(hw, lo_addr, 0);
2847 ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register for lport %u, idx %u, err %d\n",
2852 err = ice_write_phy_reg_e810(hw, hi_addr, 0);
2854 ice_debug(hw, ICE_DBG_PTP, "Failed to clear high PTP timestamp register for lport %u, idx %u, err %d\n",
2863 * ice_ptp_init_phy_e810 - Enable PTP function on the external PHY
2864 * @hw: pointer to HW struct
2866 * Enable the timesync PTP functionality for the external PHY connected to
2869 int ice_ptp_init_phy_e810(struct ice_hw *hw)
2874 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
2875 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_ENA(tmr_idx),
2876 GLTSYN_ENA_TSYN_ENA_M);
2878 ice_debug(hw, ICE_DBG_PTP, "PTP failed in ena_phy_time_syn %d\n",
2885 * ice_ptp_init_phc_e810 - Perform E810 specific PHC initialization
2886 * @hw: pointer to HW struct
2888 * Perform E810-specific PTP hardware clock initialization steps.
2890 static int ice_ptp_init_phc_e810(struct ice_hw *hw)
2892 /* Ensure synchronization delay is zero */
2893 wr32(hw, GLTSYN_SYNC_DLAY, 0);
2895 /* Initialize the PHY */
2896 return ice_ptp_init_phy_e810(hw);
2900 * ice_ptp_prep_phy_time_e810 - Prepare PHY port with initial time
2901 * @hw: Board private structure
2902 * @time: Time to initialize the PHY port clock to
2904 * Program the PHY port ETH_GLTSYN_SHTIME registers in preparation setting the
2905 * initial clock time. The time will not actually be programmed until the
2906 * driver issues an ICE_PTP_INIT_TIME command.
2908 * The time value is the upper 32 bits of the PHY timer, usually in units of
2909 * nominal nanoseconds.
2911 static int ice_ptp_prep_phy_time_e810(struct ice_hw *hw, u32 time)
2916 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
2917 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHTIME_0(tmr_idx), 0);
2919 ice_debug(hw, ICE_DBG_PTP, "Failed to write SHTIME_0, err %d\n",
2924 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHTIME_L(tmr_idx), time);
2926 ice_debug(hw, ICE_DBG_PTP, "Failed to write SHTIME_L, err %d\n",
2935 * ice_ptp_prep_phy_adj_e810 - Prep PHY port for a time adjustment
2936 * @hw: pointer to HW struct
2937 * @adj: adjustment value to program
2939 * Prepare the PHY port for an atomic adjustment by programming the PHY
2940 * ETH_GLTSYN_SHADJ_L and ETH_GLTSYN_SHADJ_H registers. The actual adjustment
2941 * is completed by issuing an ICE_PTP_ADJ_TIME sync command.
2943 * The adjustment value only contains the portion used for the upper 32bits of
2944 * the PHY timer, usually in units of nominal nanoseconds. Negative
2945 * adjustments are supported using 2s complement arithmetic.
2947 static int ice_ptp_prep_phy_adj_e810(struct ice_hw *hw, s32 adj)
2952 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
2954 /* Adjustments are represented as signed 2's complement values in
2955 * nanoseconds. Sub-nanosecond adjustment is not supported.
2957 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_L(tmr_idx), 0);
2959 ice_debug(hw, ICE_DBG_PTP, "Failed to write adj to PHY SHADJ_L, err %d\n",
2964 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_H(tmr_idx), adj);
2966 ice_debug(hw, ICE_DBG_PTP, "Failed to write adj to PHY SHADJ_H, err %d\n",
2975 * ice_ptp_prep_phy_incval_e810 - Prep PHY port increment value change
2976 * @hw: pointer to HW struct
2977 * @incval: The new 40bit increment value to prepare
2979 * Prepare the PHY port for a new increment value by programming the PHY
2980 * ETH_GLTSYN_SHADJ_L and ETH_GLTSYN_SHADJ_H registers. The actual change is
2981 * completed by issuing an ICE_PTP_INIT_INCVAL command.
2983 static int ice_ptp_prep_phy_incval_e810(struct ice_hw *hw, u64 incval)
2989 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
2990 low = lower_32_bits(incval);
2991 high = upper_32_bits(incval);
2993 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_L(tmr_idx), low);
2995 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval to PHY SHADJ_L, err %d\n",
3000 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_H(tmr_idx), high);
3002 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval PHY SHADJ_H, err %d\n",
3011 * ice_ptp_port_cmd_e810 - Prepare all external PHYs for a timer command
3012 * @hw: pointer to HW struct
3013 * @cmd: Command to be sent to the port
3015 * Prepare the external PHYs connected to this device for a timer sync
3018 static int ice_ptp_port_cmd_e810(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd)
3024 case ICE_PTP_INIT_TIME:
3025 cmd_val = GLTSYN_CMD_INIT_TIME;
3027 case ICE_PTP_INIT_INCVAL:
3028 cmd_val = GLTSYN_CMD_INIT_INCVAL;
3030 case ICE_PTP_ADJ_TIME:
3031 cmd_val = GLTSYN_CMD_ADJ_TIME;
3033 case ICE_PTP_READ_TIME:
3034 cmd_val = GLTSYN_CMD_READ_TIME;
3036 case ICE_PTP_ADJ_TIME_AT_TIME:
3037 cmd_val = GLTSYN_CMD_ADJ_INIT_TIME;
3043 /* Read, modify, write */
3044 err = ice_read_phy_reg_e810(hw, ETH_GLTSYN_CMD, &val);
3046 ice_debug(hw, ICE_DBG_PTP, "Failed to read GLTSYN_CMD, err %d\n", err);
3050 /* Modify necessary bits only and perform write */
3051 val &= ~TS_CMD_MASK_E810;
3054 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_CMD, val);
3056 ice_debug(hw, ICE_DBG_PTP, "Failed to write back GLTSYN_CMD, err %d\n", err);
3064 * ice_get_phy_tx_tstamp_ready_e810 - Read Tx memory status register
3065 * @hw: pointer to the HW struct
3066 * @port: the PHY port to read
3067 * @tstamp_ready: contents of the Tx memory status register
3069 * E810 devices do not use a Tx memory status register. Instead simply
3070 * indicate that all timestamps are currently ready.
3073 ice_get_phy_tx_tstamp_ready_e810(struct ice_hw *hw, u8 port, u64 *tstamp_ready)
3075 *tstamp_ready = 0xFFFFFFFFFFFFFFFF;
3079 /* E810T SMA functions
3081 * The following functions operate specifically on E810T hardware and are used
3082 * to access the extended GPIOs available.
3086 * ice_get_pca9575_handle
3087 * @hw: pointer to the hw struct
3088 * @pca9575_handle: GPIO controller's handle
3090 * Find and return the GPIO controller's handle in the netlist.
3091 * When found - the value will be cached in the hw structure and following calls
3092 * will return cached value
3095 ice_get_pca9575_handle(struct ice_hw *hw, u16 *pca9575_handle)
3097 struct ice_aqc_get_link_topo *cmd;
3098 struct ice_aq_desc desc;
3102 /* If handle was read previously return cached value */
3103 if (hw->io_expander_handle) {
3104 *pca9575_handle = hw->io_expander_handle;
3108 /* If handle was not detected read it from the netlist */
3109 cmd = &desc.params.get_link_topo;
3110 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo);
3112 /* Set node type to GPIO controller */
3113 cmd->addr.topo_params.node_type_ctx =
3114 (ICE_AQC_LINK_TOPO_NODE_TYPE_M &
3115 ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL);
3117 #define SW_PCA9575_SFP_TOPO_IDX 2
3118 #define SW_PCA9575_QSFP_TOPO_IDX 1
3120 /* Check if the SW IO expander controlling SMA exists in the netlist. */
3121 if (hw->device_id == ICE_DEV_ID_E810C_SFP)
3122 idx = SW_PCA9575_SFP_TOPO_IDX;
3123 else if (hw->device_id == ICE_DEV_ID_E810C_QSFP)
3124 idx = SW_PCA9575_QSFP_TOPO_IDX;
3128 cmd->addr.topo_params.index = idx;
3130 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
3134 /* Verify if we found the right IO expander type */
3135 if (desc.params.get_link_topo.node_part_num !=
3136 ICE_AQC_GET_LINK_TOPO_NODE_NR_PCA9575)
3139 /* If present save the handle and return it */
3140 hw->io_expander_handle =
3141 le16_to_cpu(desc.params.get_link_topo.addr.handle);
3142 *pca9575_handle = hw->io_expander_handle;
3148 * ice_read_sma_ctrl_e810t
3149 * @hw: pointer to the hw struct
3150 * @data: pointer to data to be read from the GPIO controller
3152 * Read the SMA controller state. It is connected to pins 3-7 of Port 1 of the
3153 * PCA9575 expander, so only bits 3-7 in data are valid.
3155 int ice_read_sma_ctrl_e810t(struct ice_hw *hw, u8 *data)
3161 status = ice_get_pca9575_handle(hw, &handle);
3167 for (i = ICE_SMA_MIN_BIT_E810T; i <= ICE_SMA_MAX_BIT_E810T; i++) {
3170 status = ice_aq_get_gpio(hw, handle, i + ICE_PCA9575_P1_OFFSET,
3174 *data |= (u8)(!pin) << i;
3181 * ice_write_sma_ctrl_e810t
3182 * @hw: pointer to the hw struct
3183 * @data: data to be written to the GPIO controller
3185 * Write the data to the SMA controller. It is connected to pins 3-7 of Port 1
3186 * of the PCA9575 expander, so only bits 3-7 in data are valid.
3188 int ice_write_sma_ctrl_e810t(struct ice_hw *hw, u8 data)
3194 status = ice_get_pca9575_handle(hw, &handle);
3198 for (i = ICE_SMA_MIN_BIT_E810T; i <= ICE_SMA_MAX_BIT_E810T; i++) {
3201 pin = !(data & (1 << i));
3202 status = ice_aq_set_gpio(hw, handle, i + ICE_PCA9575_P1_OFFSET,
3212 * ice_read_pca9575_reg_e810t
3213 * @hw: pointer to the hw struct
3214 * @offset: GPIO controller register offset
3215 * @data: pointer to data to be read from the GPIO controller
3217 * Read the register from the GPIO controller
3219 int ice_read_pca9575_reg_e810t(struct ice_hw *hw, u8 offset, u8 *data)
3221 struct ice_aqc_link_topo_addr link_topo;
3226 memset(&link_topo, 0, sizeof(link_topo));
3228 err = ice_get_pca9575_handle(hw, &handle);
3232 link_topo.handle = cpu_to_le16(handle);
3233 link_topo.topo_params.node_type_ctx =
3234 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_CTX_M,
3235 ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED);
3237 addr = cpu_to_le16((u16)offset);
3239 return ice_aq_read_i2c(hw, link_topo, 0, addr, 1, data, NULL);
3242 /* Device agnostic functions
3244 * The following functions implement shared behavior common to both E822 and
3245 * E810 devices, possibly calling a device specific implementation where
3250 * ice_ptp_lock - Acquire PTP global semaphore register lock
3251 * @hw: pointer to the HW struct
3253 * Acquire the global PTP hardware semaphore lock. Returns true if the lock
3254 * was acquired, false otherwise.
3256 * The PFTSYN_SEM register sets the busy bit on read, returning the previous
3257 * value. If software sees the busy bit cleared, this means that this function
3258 * acquired the lock (and the busy bit is now set). If software sees the busy
3259 * bit set, it means that another function acquired the lock.
3261 * Software must clear the busy bit with a write to release the lock for other
3262 * functions when done.
3264 bool ice_ptp_lock(struct ice_hw *hw)
3269 #define MAX_TRIES 15
3271 for (i = 0; i < MAX_TRIES; i++) {
3272 hw_lock = rd32(hw, PFTSYN_SEM + (PFTSYN_SEM_BYTES * hw->pf_id));
3273 hw_lock = hw_lock & PFTSYN_SEM_BUSY_M;
3275 /* Somebody is holding the lock */
3276 usleep_range(5000, 6000);
3287 * ice_ptp_unlock - Release PTP global semaphore register lock
3288 * @hw: pointer to the HW struct
3290 * Release the global PTP hardware semaphore lock. This is done by writing to
3291 * the PFTSYN_SEM register.
3293 void ice_ptp_unlock(struct ice_hw *hw)
3295 wr32(hw, PFTSYN_SEM + (PFTSYN_SEM_BYTES * hw->pf_id), 0);
3299 * ice_ptp_init_phy_model - Initialize hw->phy_model based on device type
3300 * @hw: pointer to the HW structure
3302 * Determine the PHY model for the device, and initialize hw->phy_model
3303 * for use by other functions.
3305 void ice_ptp_init_phy_model(struct ice_hw *hw)
3307 if (ice_is_e810(hw))
3308 hw->phy_model = ICE_PHY_E810;
3310 hw->phy_model = ICE_PHY_E822;
3314 * ice_ptp_tmr_cmd - Prepare and trigger a timer sync command
3315 * @hw: pointer to HW struct
3316 * @cmd: the command to issue
3318 * Prepare the source timer and PHY timers and then trigger the requested
3319 * command. This causes the shadow registers previously written in preparation
3320 * for the command to be synchronously applied to both the source and PHY
3323 static int ice_ptp_tmr_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd)
3327 /* First, prepare the source timer */
3328 ice_ptp_src_cmd(hw, cmd);
3330 /* Next, prepare the ports */
3331 switch (hw->phy_model) {
3333 err = ice_ptp_port_cmd_e810(hw, cmd);
3336 err = ice_ptp_port_cmd_e822(hw, cmd);
3343 ice_debug(hw, ICE_DBG_PTP, "Failed to prepare PHY ports for timer command %u, err %d\n",
3348 /* Write the sync command register to drive both source and PHY timer
3349 * commands synchronously
3351 ice_ptp_exec_tmr_cmd(hw);
3357 * ice_ptp_init_time - Initialize device time to provided value
3358 * @hw: pointer to HW struct
3359 * @time: 64bits of time (GLTSYN_TIME_L and GLTSYN_TIME_H)
3361 * Initialize the device to the specified time provided. This requires a three
3364 * 1) write the new init time to the source timer shadow registers
3365 * 2) write the new init time to the PHY timer shadow registers
3366 * 3) issue an init_time timer command to synchronously switch both the source
3367 * and port timers to the new init time value at the next clock cycle.
3369 int ice_ptp_init_time(struct ice_hw *hw, u64 time)
3374 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
3377 wr32(hw, GLTSYN_SHTIME_L(tmr_idx), lower_32_bits(time));
3378 wr32(hw, GLTSYN_SHTIME_H(tmr_idx), upper_32_bits(time));
3379 wr32(hw, GLTSYN_SHTIME_0(tmr_idx), 0);
3382 /* Fill Rx and Tx ports and send msg to PHY */
3383 switch (hw->phy_model) {
3385 err = ice_ptp_prep_phy_time_e810(hw, time & 0xFFFFFFFF);
3388 err = ice_ptp_prep_phy_time_e822(hw, time & 0xFFFFFFFF);
3397 return ice_ptp_tmr_cmd(hw, ICE_PTP_INIT_TIME);
3401 * ice_ptp_write_incval - Program PHC with new increment value
3402 * @hw: pointer to HW struct
3403 * @incval: Source timer increment value per clock cycle
3405 * Program the PHC with a new increment value. This requires a three-step
3408 * 1) Write the increment value to the source timer shadow registers
3409 * 2) Write the increment value to the PHY timer shadow registers
3410 * 3) Issue an ICE_PTP_INIT_INCVAL timer command to synchronously switch both
3411 * the source and port timers to the new increment value at the next clock
3414 int ice_ptp_write_incval(struct ice_hw *hw, u64 incval)
3419 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
3422 wr32(hw, GLTSYN_SHADJ_L(tmr_idx), lower_32_bits(incval));
3423 wr32(hw, GLTSYN_SHADJ_H(tmr_idx), upper_32_bits(incval));
3425 switch (hw->phy_model) {
3427 err = ice_ptp_prep_phy_incval_e810(hw, incval);
3430 err = ice_ptp_prep_phy_incval_e822(hw, incval);
3439 return ice_ptp_tmr_cmd(hw, ICE_PTP_INIT_INCVAL);
3443 * ice_ptp_write_incval_locked - Program new incval while holding semaphore
3444 * @hw: pointer to HW struct
3445 * @incval: Source timer increment value per clock cycle
3447 * Program a new PHC incval while holding the PTP semaphore.
3449 int ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval)
3453 if (!ice_ptp_lock(hw))
3456 err = ice_ptp_write_incval(hw, incval);
3464 * ice_ptp_adj_clock - Adjust PHC clock time atomically
3465 * @hw: pointer to HW struct
3466 * @adj: Adjustment in nanoseconds
3468 * Perform an atomic adjustment of the PHC time by the specified number of
3469 * nanoseconds. This requires a three-step process:
3471 * 1) Write the adjustment to the source timer shadow registers
3472 * 2) Write the adjustment to the PHY timer shadow registers
3473 * 3) Issue an ICE_PTP_ADJ_TIME timer command to synchronously apply the
3474 * adjustment to both the source and port timers at the next clock cycle.
3476 int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj)
3481 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
3483 /* Write the desired clock adjustment into the GLTSYN_SHADJ register.
3484 * For an ICE_PTP_ADJ_TIME command, this set of registers represents
3485 * the value to add to the clock time. It supports subtraction by
3486 * interpreting the value as a 2's complement integer.
3488 wr32(hw, GLTSYN_SHADJ_L(tmr_idx), 0);
3489 wr32(hw, GLTSYN_SHADJ_H(tmr_idx), adj);
3491 switch (hw->phy_model) {
3493 err = ice_ptp_prep_phy_adj_e810(hw, adj);
3496 err = ice_ptp_prep_phy_adj_e822(hw, adj);
3505 return ice_ptp_tmr_cmd(hw, ICE_PTP_ADJ_TIME);
3509 * ice_read_phy_tstamp - Read a PHY timestamp from the timestamo block
3510 * @hw: pointer to the HW struct
3511 * @block: the block to read from
3512 * @idx: the timestamp index to read
3513 * @tstamp: on return, the 40bit timestamp value
3515 * Read a 40bit timestamp value out of the timestamp block. For E822 devices,
3516 * the block is the quad to read from. For E810 devices, the block is the
3517 * logical port to read from.
3519 int ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp)
3521 switch (hw->phy_model) {
3523 return ice_read_phy_tstamp_e810(hw, block, idx, tstamp);
3525 return ice_read_phy_tstamp_e822(hw, block, idx, tstamp);
3532 * ice_clear_phy_tstamp - Clear a timestamp from the timestamp block
3533 * @hw: pointer to the HW struct
3534 * @block: the block to read from
3535 * @idx: the timestamp index to reset
3537 * Clear a timestamp from the timestamp block, discarding its value without
3538 * returning it. This resets the memory status bit for the timestamp index
3539 * allowing it to be reused for another timestamp in the future.
3541 * For E822 devices, the block number is the PHY quad to clear from. For E810
3542 * devices, the block number is the logical port to clear from.
3544 * This function must only be called on a timestamp index whose valid bit is
3545 * set according to ice_get_phy_tx_tstamp_ready().
3547 int ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx)
3549 switch (hw->phy_model) {
3551 return ice_clear_phy_tstamp_e810(hw, block, idx);
3553 return ice_clear_phy_tstamp_e822(hw, block, idx);
3560 * ice_get_pf_c827_idx - find and return the C827 index for the current pf
3561 * @hw: pointer to the hw struct
3562 * @idx: index of the found C827 PHY
3565 * * negative - failure
3567 static int ice_get_pf_c827_idx(struct ice_hw *hw, u8 *idx)
3569 struct ice_aqc_get_link_topo cmd;
3570 u8 node_part_number;
3575 if (hw->mac_type != ICE_MAC_E810)
3578 if (hw->device_id != ICE_DEV_ID_E810C_QSFP) {
3583 memset(&cmd, 0, sizeof(cmd));
3585 ctx = ICE_AQC_LINK_TOPO_NODE_TYPE_PHY << ICE_AQC_LINK_TOPO_NODE_TYPE_S;
3586 ctx |= ICE_AQC_LINK_TOPO_NODE_CTX_PORT << ICE_AQC_LINK_TOPO_NODE_CTX_S;
3587 cmd.addr.topo_params.node_type_ctx = ctx;
3589 status = ice_aq_get_netlist_node(hw, &cmd, &node_part_number,
3591 if (status || node_part_number != ICE_AQC_GET_LINK_TOPO_NODE_NR_C827)
3594 if (node_handle == E810C_QSFP_C827_0_HANDLE)
3596 else if (node_handle == E810C_QSFP_C827_1_HANDLE)
3605 * ice_ptp_reset_ts_memory - Reset timestamp memory for all blocks
3606 * @hw: pointer to the HW struct
3608 void ice_ptp_reset_ts_memory(struct ice_hw *hw)
3610 switch (hw->phy_model) {
3612 ice_ptp_reset_ts_memory_e822(hw);
3621 * ice_ptp_init_phc - Initialize PTP hardware clock
3622 * @hw: pointer to the HW struct
3624 * Perform the steps required to initialize the PTP hardware clock.
3626 int ice_ptp_init_phc(struct ice_hw *hw)
3628 u8 src_idx = hw->func_caps.ts_func_info.tmr_index_owned;
3630 /* Enable source clocks */
3631 wr32(hw, GLTSYN_ENA(src_idx), GLTSYN_ENA_TSYN_ENA_M);
3633 /* Clear event err indications for auxiliary pins */
3634 (void)rd32(hw, GLTSYN_STAT(src_idx));
3636 switch (hw->phy_model) {
3638 return ice_ptp_init_phc_e810(hw);
3640 return ice_ptp_init_phc_e822(hw);
3647 * ice_get_phy_tx_tstamp_ready - Read PHY Tx memory status indication
3648 * @hw: pointer to the HW struct
3649 * @block: the timestamp block to check
3650 * @tstamp_ready: storage for the PHY Tx memory status information
3652 * Check the PHY for Tx timestamp memory status. This reports a 64 bit value
3653 * which indicates which timestamps in the block may be captured. A set bit
3654 * means the timestamp can be read. An unset bit means the timestamp is not
3655 * ready and software should avoid reading the register.
3657 int ice_get_phy_tx_tstamp_ready(struct ice_hw *hw, u8 block, u64 *tstamp_ready)
3659 switch (hw->phy_model) {
3661 return ice_get_phy_tx_tstamp_ready_e810(hw, block,
3664 return ice_get_phy_tx_tstamp_ready_e822(hw, block,
3673 * ice_cgu_get_pin_desc_e823 - get pin description array
3674 * @hw: pointer to the hw struct
3675 * @input: if request is done against input or output pin
3676 * @size: number of inputs/outputs
3678 * Return: pointer to pin description array associated to given hw.
3680 static const struct ice_cgu_pin_desc *
3681 ice_cgu_get_pin_desc_e823(struct ice_hw *hw, bool input, int *size)
3683 static const struct ice_cgu_pin_desc *t;
3685 if (hw->cgu_part_number ==
3686 ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032) {
3688 t = ice_e823_zl_cgu_inputs;
3689 *size = ARRAY_SIZE(ice_e823_zl_cgu_inputs);
3691 t = ice_e823_zl_cgu_outputs;
3692 *size = ARRAY_SIZE(ice_e823_zl_cgu_outputs);
3694 } else if (hw->cgu_part_number ==
3695 ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384) {
3697 t = ice_e823_si_cgu_inputs;
3698 *size = ARRAY_SIZE(ice_e823_si_cgu_inputs);
3700 t = ice_e823_si_cgu_outputs;
3701 *size = ARRAY_SIZE(ice_e823_si_cgu_outputs);
3712 * ice_cgu_get_pin_desc - get pin description array
3713 * @hw: pointer to the hw struct
3714 * @input: if request is done against input or output pins
3715 * @size: size of array returned by function
3717 * Return: pointer to pin description array associated to given hw.
3719 static const struct ice_cgu_pin_desc *
3720 ice_cgu_get_pin_desc(struct ice_hw *hw, bool input, int *size)
3722 const struct ice_cgu_pin_desc *t = NULL;
3724 switch (hw->device_id) {
3725 case ICE_DEV_ID_E810C_SFP:
3727 t = ice_e810t_sfp_cgu_inputs;
3728 *size = ARRAY_SIZE(ice_e810t_sfp_cgu_inputs);
3730 t = ice_e810t_sfp_cgu_outputs;
3731 *size = ARRAY_SIZE(ice_e810t_sfp_cgu_outputs);
3734 case ICE_DEV_ID_E810C_QSFP:
3736 t = ice_e810t_qsfp_cgu_inputs;
3737 *size = ARRAY_SIZE(ice_e810t_qsfp_cgu_inputs);
3739 t = ice_e810t_qsfp_cgu_outputs;
3740 *size = ARRAY_SIZE(ice_e810t_qsfp_cgu_outputs);
3743 case ICE_DEV_ID_E823L_10G_BASE_T:
3744 case ICE_DEV_ID_E823L_1GBE:
3745 case ICE_DEV_ID_E823L_BACKPLANE:
3746 case ICE_DEV_ID_E823L_QSFP:
3747 case ICE_DEV_ID_E823L_SFP:
3748 case ICE_DEV_ID_E823C_10G_BASE_T:
3749 case ICE_DEV_ID_E823C_BACKPLANE:
3750 case ICE_DEV_ID_E823C_QSFP:
3751 case ICE_DEV_ID_E823C_SFP:
3752 case ICE_DEV_ID_E823C_SGMII:
3753 t = ice_cgu_get_pin_desc_e823(hw, input, size);
3763 * ice_cgu_get_pin_type - get pin's type
3764 * @hw: pointer to the hw struct
3766 * @input: if request is done against input or output pin
3768 * Return: type of a pin.
3770 enum dpll_pin_type ice_cgu_get_pin_type(struct ice_hw *hw, u8 pin, bool input)
3772 const struct ice_cgu_pin_desc *t;
3775 t = ice_cgu_get_pin_desc(hw, input, &t_size);
3787 * ice_cgu_get_pin_freq_supp - get pin's supported frequency
3788 * @hw: pointer to the hw struct
3790 * @input: if request is done against input or output pin
3791 * @num: output number of supported frequencies
3793 * Get frequency supported number and array of supported frequencies.
3795 * Return: array of supported frequencies for given pin.
3797 struct dpll_pin_frequency *
3798 ice_cgu_get_pin_freq_supp(struct ice_hw *hw, u8 pin, bool input, u8 *num)
3800 const struct ice_cgu_pin_desc *t;
3804 t = ice_cgu_get_pin_desc(hw, input, &t_size);
3809 *num = t[pin].freq_supp_num;
3811 return t[pin].freq_supp;
3815 * ice_cgu_get_pin_name - get pin's name
3816 * @hw: pointer to the hw struct
3818 * @input: if request is done against input or output pin
3821 * * null terminated char array with name
3822 * * NULL in case of failure
3824 const char *ice_cgu_get_pin_name(struct ice_hw *hw, u8 pin, bool input)
3826 const struct ice_cgu_pin_desc *t;
3829 t = ice_cgu_get_pin_desc(hw, input, &t_size);
3841 * ice_get_cgu_state - get the state of the DPLL
3842 * @hw: pointer to the hw struct
3843 * @dpll_idx: Index of internal DPLL unit
3844 * @last_dpll_state: last known state of DPLL
3845 * @pin: pointer to a buffer for returning currently active pin
3846 * @ref_state: reference clock state
3847 * @eec_mode: eec mode of the DPLL
3848 * @phase_offset: pointer to a buffer for returning phase offset
3849 * @dpll_state: state of the DPLL (output)
3851 * This function will read the state of the DPLL(dpll_idx). Non-null
3852 * 'pin', 'ref_state', 'eec_mode' and 'phase_offset' parameters are used to
3853 * retrieve currently active pin, state, mode and phase_offset respectively.
3855 * Return: state of the DPLL
3857 int ice_get_cgu_state(struct ice_hw *hw, u8 dpll_idx,
3858 enum dpll_lock_status last_dpll_state, u8 *pin,
3859 u8 *ref_state, u8 *eec_mode, s64 *phase_offset,
3860 enum dpll_lock_status *dpll_state)
3862 u8 hw_ref_state, hw_dpll_state, hw_eec_mode, hw_config;
3863 s64 hw_phase_offset;
3866 status = ice_aq_get_cgu_dpll_status(hw, dpll_idx, &hw_ref_state,
3867 &hw_dpll_state, &hw_config,
3868 &hw_phase_offset, &hw_eec_mode);
3873 /* current ref pin in dpll_state_refsel_status_X register */
3874 *pin = hw_config & ICE_AQC_GET_CGU_DPLL_CONFIG_CLK_REF_SEL;
3876 *phase_offset = hw_phase_offset;
3878 *ref_state = hw_ref_state;
3880 *eec_mode = hw_eec_mode;
3884 /* According to ZL DPLL documentation, once state reach LOCKED_HO_ACQ
3885 * it would never return to FREERUN. This aligns to ITU-T G.781
3886 * Recommendation. We cannot report HOLDOVER as HO memory is cleared
3887 * while switching to another reference.
3888 * Only for situations where previous state was either: "LOCKED without
3889 * HO_ACQ" or "HOLDOVER" we actually back to FREERUN.
3891 if (hw_dpll_state & ICE_AQC_GET_CGU_DPLL_STATUS_STATE_LOCK) {
3892 if (hw_dpll_state & ICE_AQC_GET_CGU_DPLL_STATUS_STATE_HO_READY)
3893 *dpll_state = DPLL_LOCK_STATUS_LOCKED_HO_ACQ;
3895 *dpll_state = DPLL_LOCK_STATUS_LOCKED;
3896 } else if (last_dpll_state == DPLL_LOCK_STATUS_LOCKED_HO_ACQ ||
3897 last_dpll_state == DPLL_LOCK_STATUS_HOLDOVER) {
3898 *dpll_state = DPLL_LOCK_STATUS_HOLDOVER;
3900 *dpll_state = DPLL_LOCK_STATUS_UNLOCKED;
3907 * ice_get_cgu_rclk_pin_info - get info on available recovered clock pins
3908 * @hw: pointer to the hw struct
3909 * @base_idx: returns index of first recovered clock pin on device
3910 * @pin_num: returns number of recovered clock pins available on device
3912 * Based on hw provide caller info about recovery clock pins available on the
3916 * * 0 - success, information is valid
3917 * * negative - failure, information is not valid
3919 int ice_get_cgu_rclk_pin_info(struct ice_hw *hw, u8 *base_idx, u8 *pin_num)
3924 switch (hw->device_id) {
3925 case ICE_DEV_ID_E810C_SFP:
3926 case ICE_DEV_ID_E810C_QSFP:
3928 ret = ice_get_pf_c827_idx(hw, &phy_idx);
3931 *base_idx = E810T_CGU_INPUT_C827(phy_idx, ICE_RCLKA_PIN);
3932 *pin_num = ICE_E810_RCLK_PINS_NUM;
3935 case ICE_DEV_ID_E823L_10G_BASE_T:
3936 case ICE_DEV_ID_E823L_1GBE:
3937 case ICE_DEV_ID_E823L_BACKPLANE:
3938 case ICE_DEV_ID_E823L_QSFP:
3939 case ICE_DEV_ID_E823L_SFP:
3940 case ICE_DEV_ID_E823C_10G_BASE_T:
3941 case ICE_DEV_ID_E823C_BACKPLANE:
3942 case ICE_DEV_ID_E823C_QSFP:
3943 case ICE_DEV_ID_E823C_SFP:
3944 case ICE_DEV_ID_E823C_SGMII:
3945 *pin_num = ICE_E822_RCLK_PINS_NUM;
3947 if (hw->cgu_part_number ==
3948 ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032)
3949 *base_idx = ZL_REF1P;
3950 else if (hw->cgu_part_number ==
3951 ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384)
3952 *base_idx = SI_REF1P;
3966 * ice_cgu_get_output_pin_state_caps - get output pin state capabilities
3967 * @hw: pointer to the hw struct
3968 * @pin_id: id of a pin
3969 * @caps: capabilities to modify
3972 * * 0 - success, state capabilities were modified
3973 * * negative - failure, capabilities were not modified
3975 int ice_cgu_get_output_pin_state_caps(struct ice_hw *hw, u8 pin_id,
3976 unsigned long *caps)
3978 bool can_change = true;
3980 switch (hw->device_id) {
3981 case ICE_DEV_ID_E810C_SFP:
3982 if (pin_id == ZL_OUT2 || pin_id == ZL_OUT3)
3985 case ICE_DEV_ID_E810C_QSFP:
3986 if (pin_id == ZL_OUT2 || pin_id == ZL_OUT3 || pin_id == ZL_OUT4)
3989 case ICE_DEV_ID_E823L_10G_BASE_T:
3990 case ICE_DEV_ID_E823L_1GBE:
3991 case ICE_DEV_ID_E823L_BACKPLANE:
3992 case ICE_DEV_ID_E823L_QSFP:
3993 case ICE_DEV_ID_E823L_SFP:
3994 case ICE_DEV_ID_E823C_10G_BASE_T:
3995 case ICE_DEV_ID_E823C_BACKPLANE:
3996 case ICE_DEV_ID_E823C_QSFP:
3997 case ICE_DEV_ID_E823C_SFP:
3998 case ICE_DEV_ID_E823C_SGMII:
3999 if (hw->cgu_part_number ==
4000 ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032 &&
4003 else if (hw->cgu_part_number ==
4004 ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384 &&
4012 *caps |= DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE;
4014 *caps &= ~DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE;