1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (C) 2021, Intel Corporation. */
8 #define E810_OUT_PROP_DELAY_NS 1
10 #define UNKNOWN_INCVAL_E822 0x100000000ULL
12 static const struct ptp_pin_desc ice_pin_desc_e810t[] = {
13 /* name idx func chan */
14 { "GNSS", GNSS, PTP_PF_EXTTS, 0, { 0, } },
15 { "SMA1", SMA1, PTP_PF_NONE, 1, { 0, } },
16 { "U.FL1", UFL1, PTP_PF_NONE, 1, { 0, } },
17 { "SMA2", SMA2, PTP_PF_NONE, 2, { 0, } },
18 { "U.FL2", UFL2, PTP_PF_NONE, 2, { 0, } },
22 * ice_get_sma_config_e810t
23 * @hw: pointer to the hw struct
24 * @ptp_pins: pointer to the ptp_pin_desc struture
26 * Read the configuration of the SMA control logic and put it into the
27 * ptp_pin_desc structure
30 ice_get_sma_config_e810t(struct ice_hw *hw, struct ptp_pin_desc *ptp_pins)
35 /* Read initial pin state */
36 status = ice_read_sma_ctrl_e810t(hw, &data);
40 /* initialize with defaults */
41 for (i = 0; i < NUM_PTP_PINS_E810T; i++) {
42 snprintf(ptp_pins[i].name, sizeof(ptp_pins[i].name),
43 "%s", ice_pin_desc_e810t[i].name);
44 ptp_pins[i].index = ice_pin_desc_e810t[i].index;
45 ptp_pins[i].func = ice_pin_desc_e810t[i].func;
46 ptp_pins[i].chan = ice_pin_desc_e810t[i].chan;
50 switch (data & ICE_SMA1_MASK_E810T) {
51 case ICE_SMA1_MASK_E810T:
53 ptp_pins[SMA1].func = PTP_PF_NONE;
54 ptp_pins[UFL1].func = PTP_PF_NONE;
56 case ICE_SMA1_DIR_EN_E810T:
57 ptp_pins[SMA1].func = PTP_PF_PEROUT;
58 ptp_pins[UFL1].func = PTP_PF_NONE;
60 case ICE_SMA1_TX_EN_E810T:
61 ptp_pins[SMA1].func = PTP_PF_EXTTS;
62 ptp_pins[UFL1].func = PTP_PF_NONE;
65 ptp_pins[SMA1].func = PTP_PF_EXTTS;
66 ptp_pins[UFL1].func = PTP_PF_PEROUT;
71 switch (data & ICE_SMA2_MASK_E810T) {
72 case ICE_SMA2_MASK_E810T:
74 ptp_pins[SMA2].func = PTP_PF_NONE;
75 ptp_pins[UFL2].func = PTP_PF_NONE;
77 case (ICE_SMA2_TX_EN_E810T | ICE_SMA2_UFL2_RX_DIS_E810T):
78 ptp_pins[SMA2].func = PTP_PF_EXTTS;
79 ptp_pins[UFL2].func = PTP_PF_NONE;
81 case (ICE_SMA2_DIR_EN_E810T | ICE_SMA2_UFL2_RX_DIS_E810T):
82 ptp_pins[SMA2].func = PTP_PF_PEROUT;
83 ptp_pins[UFL2].func = PTP_PF_NONE;
85 case (ICE_SMA2_DIR_EN_E810T | ICE_SMA2_TX_EN_E810T):
86 ptp_pins[SMA2].func = PTP_PF_NONE;
87 ptp_pins[UFL2].func = PTP_PF_EXTTS;
89 case ICE_SMA2_DIR_EN_E810T:
90 ptp_pins[SMA2].func = PTP_PF_PEROUT;
91 ptp_pins[UFL2].func = PTP_PF_EXTTS;
99 * ice_ptp_set_sma_config_e810t
100 * @hw: pointer to the hw struct
101 * @ptp_pins: pointer to the ptp_pin_desc struture
103 * Set the configuration of the SMA control logic based on the configuration in
107 ice_ptp_set_sma_config_e810t(struct ice_hw *hw,
108 const struct ptp_pin_desc *ptp_pins)
113 /* SMA1 and UFL1 cannot be set to TX at the same time */
114 if (ptp_pins[SMA1].func == PTP_PF_PEROUT &&
115 ptp_pins[UFL1].func == PTP_PF_PEROUT)
118 /* SMA2 and UFL2 cannot be set to RX at the same time */
119 if (ptp_pins[SMA2].func == PTP_PF_EXTTS &&
120 ptp_pins[UFL2].func == PTP_PF_EXTTS)
123 /* Read initial pin state value */
124 status = ice_read_sma_ctrl_e810t(hw, &data);
128 /* Set the right sate based on the desired configuration */
129 data &= ~ICE_SMA1_MASK_E810T;
130 if (ptp_pins[SMA1].func == PTP_PF_NONE &&
131 ptp_pins[UFL1].func == PTP_PF_NONE) {
132 dev_info(ice_hw_to_dev(hw), "SMA1 + U.FL1 disabled");
133 data |= ICE_SMA1_MASK_E810T;
134 } else if (ptp_pins[SMA1].func == PTP_PF_EXTTS &&
135 ptp_pins[UFL1].func == PTP_PF_NONE) {
136 dev_info(ice_hw_to_dev(hw), "SMA1 RX");
137 data |= ICE_SMA1_TX_EN_E810T;
138 } else if (ptp_pins[SMA1].func == PTP_PF_NONE &&
139 ptp_pins[UFL1].func == PTP_PF_PEROUT) {
140 /* U.FL 1 TX will always enable SMA 1 RX */
141 dev_info(ice_hw_to_dev(hw), "SMA1 RX + U.FL1 TX");
142 } else if (ptp_pins[SMA1].func == PTP_PF_EXTTS &&
143 ptp_pins[UFL1].func == PTP_PF_PEROUT) {
144 dev_info(ice_hw_to_dev(hw), "SMA1 RX + U.FL1 TX");
145 } else if (ptp_pins[SMA1].func == PTP_PF_PEROUT &&
146 ptp_pins[UFL1].func == PTP_PF_NONE) {
147 dev_info(ice_hw_to_dev(hw), "SMA1 TX");
148 data |= ICE_SMA1_DIR_EN_E810T;
151 data &= ~ICE_SMA2_MASK_E810T;
152 if (ptp_pins[SMA2].func == PTP_PF_NONE &&
153 ptp_pins[UFL2].func == PTP_PF_NONE) {
154 dev_info(ice_hw_to_dev(hw), "SMA2 + U.FL2 disabled");
155 data |= ICE_SMA2_MASK_E810T;
156 } else if (ptp_pins[SMA2].func == PTP_PF_EXTTS &&
157 ptp_pins[UFL2].func == PTP_PF_NONE) {
158 dev_info(ice_hw_to_dev(hw), "SMA2 RX");
159 data |= (ICE_SMA2_TX_EN_E810T |
160 ICE_SMA2_UFL2_RX_DIS_E810T);
161 } else if (ptp_pins[SMA2].func == PTP_PF_NONE &&
162 ptp_pins[UFL2].func == PTP_PF_EXTTS) {
163 dev_info(ice_hw_to_dev(hw), "UFL2 RX");
164 data |= (ICE_SMA2_DIR_EN_E810T | ICE_SMA2_TX_EN_E810T);
165 } else if (ptp_pins[SMA2].func == PTP_PF_PEROUT &&
166 ptp_pins[UFL2].func == PTP_PF_NONE) {
167 dev_info(ice_hw_to_dev(hw), "SMA2 TX");
168 data |= (ICE_SMA2_DIR_EN_E810T |
169 ICE_SMA2_UFL2_RX_DIS_E810T);
170 } else if (ptp_pins[SMA2].func == PTP_PF_PEROUT &&
171 ptp_pins[UFL2].func == PTP_PF_EXTTS) {
172 dev_info(ice_hw_to_dev(hw), "SMA2 TX + U.FL2 RX");
173 data |= ICE_SMA2_DIR_EN_E810T;
176 return ice_write_sma_ctrl_e810t(hw, data);
180 * ice_ptp_set_sma_e810t
181 * @info: the driver's PTP info structure
182 * @pin: pin index in kernel structure
183 * @func: Pin function to be set (PTP_PF_NONE, PTP_PF_EXTTS or PTP_PF_PEROUT)
185 * Set the configuration of a single SMA pin
188 ice_ptp_set_sma_e810t(struct ptp_clock_info *info, unsigned int pin,
189 enum ptp_pin_function func)
191 struct ptp_pin_desc ptp_pins[NUM_PTP_PINS_E810T];
192 struct ice_pf *pf = ptp_info_to_pf(info);
193 struct ice_hw *hw = &pf->hw;
196 if (pin < SMA1 || func > PTP_PF_PEROUT)
199 err = ice_get_sma_config_e810t(hw, ptp_pins);
203 /* Disable the same function on the other pin sharing the channel */
204 if (pin == SMA1 && ptp_pins[UFL1].func == func)
205 ptp_pins[UFL1].func = PTP_PF_NONE;
206 if (pin == UFL1 && ptp_pins[SMA1].func == func)
207 ptp_pins[SMA1].func = PTP_PF_NONE;
209 if (pin == SMA2 && ptp_pins[UFL2].func == func)
210 ptp_pins[UFL2].func = PTP_PF_NONE;
211 if (pin == UFL2 && ptp_pins[SMA2].func == func)
212 ptp_pins[SMA2].func = PTP_PF_NONE;
214 /* Set up new pin function in the temp table */
215 ptp_pins[pin].func = func;
217 return ice_ptp_set_sma_config_e810t(hw, ptp_pins);
221 * ice_verify_pin_e810t
222 * @info: the driver's PTP info structure
224 * @func: Assigned function
225 * @chan: Assigned channel
227 * Verify if pin supports requested pin function. If the Check pins consistency.
228 * Reconfigure the SMA logic attached to the given pin to enable its
229 * desired functionality
232 ice_verify_pin_e810t(struct ptp_clock_info *info, unsigned int pin,
233 enum ptp_pin_function func, unsigned int chan)
235 /* Don't allow channel reassignment */
236 if (chan != ice_pin_desc_e810t[pin].chan)
239 /* Check if functions are properly assigned */
248 if (pin == UFL2 || pin == GNSS)
255 return ice_ptp_set_sma_e810t(info, pin, func);
259 * ice_set_tx_tstamp - Enable or disable Tx timestamping
260 * @pf: The PF pointer to search in
261 * @on: bool value for whether timestamps are enabled or disabled
263 static void ice_set_tx_tstamp(struct ice_pf *pf, bool on)
269 vsi = ice_get_main_vsi(pf);
273 /* Set the timestamp enable flag for all the Tx rings */
274 ice_for_each_txq(vsi, i) {
275 if (!vsi->tx_rings[i])
277 vsi->tx_rings[i]->ptp_tx = on;
280 /* Configure the Tx timestamp interrupt */
281 val = rd32(&pf->hw, PFINT_OICR_ENA);
283 val |= PFINT_OICR_TSYN_TX_M;
285 val &= ~PFINT_OICR_TSYN_TX_M;
286 wr32(&pf->hw, PFINT_OICR_ENA, val);
288 pf->ptp.tstamp_config.tx_type = on ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
292 * ice_set_rx_tstamp - Enable or disable Rx timestamping
293 * @pf: The PF pointer to search in
294 * @on: bool value for whether timestamps are enabled or disabled
296 static void ice_set_rx_tstamp(struct ice_pf *pf, bool on)
301 vsi = ice_get_main_vsi(pf);
305 /* Set the timestamp flag for all the Rx rings */
306 ice_for_each_rxq(vsi, i) {
307 if (!vsi->rx_rings[i])
309 vsi->rx_rings[i]->ptp_rx = on;
312 pf->ptp.tstamp_config.rx_filter = on ? HWTSTAMP_FILTER_ALL :
313 HWTSTAMP_FILTER_NONE;
317 * ice_ptp_cfg_timestamp - Configure timestamp for init/deinit
318 * @pf: Board private structure
319 * @ena: bool value to enable or disable time stamp
321 * This function will configure timestamping during PTP initialization
322 * and deinitialization
324 void ice_ptp_cfg_timestamp(struct ice_pf *pf, bool ena)
326 ice_set_tx_tstamp(pf, ena);
327 ice_set_rx_tstamp(pf, ena);
331 * ice_get_ptp_clock_index - Get the PTP clock index
332 * @pf: the PF pointer
334 * Determine the clock index of the PTP clock associated with this device. If
335 * this is the PF controlling the clock, just use the local access to the
336 * clock device pointer.
338 * Otherwise, read from the driver shared parameters to determine the clock
341 * Returns: the index of the PTP clock associated with this device, or -1 if
342 * there is no associated clock.
344 int ice_get_ptp_clock_index(struct ice_pf *pf)
346 struct device *dev = ice_pf_to_dev(pf);
347 enum ice_aqc_driver_params param_idx;
348 struct ice_hw *hw = &pf->hw;
353 /* Use the ptp_clock structure if we're the main PF */
355 return ptp_clock_index(pf->ptp.clock);
357 tmr_idx = hw->func_caps.ts_func_info.tmr_index_assoc;
359 param_idx = ICE_AQC_DRIVER_PARAM_CLK_IDX_TMR0;
361 param_idx = ICE_AQC_DRIVER_PARAM_CLK_IDX_TMR1;
363 err = ice_aq_get_driver_param(hw, param_idx, &value, NULL);
365 dev_err(dev, "Failed to read PTP clock index parameter, err %d aq_err %s\n",
366 err, ice_aq_str(hw->adminq.sq_last_status));
370 /* The PTP clock index is an integer, and will be between 0 and
371 * INT_MAX. The highest bit of the driver shared parameter is used to
372 * indicate whether or not the currently stored clock index is valid.
374 if (!(value & PTP_SHARED_CLK_IDX_VALID))
377 return value & ~PTP_SHARED_CLK_IDX_VALID;
381 * ice_set_ptp_clock_index - Set the PTP clock index
382 * @pf: the PF pointer
384 * Set the PTP clock index for this device into the shared driver parameters,
385 * so that other PFs associated with this device can read it.
387 * If the PF is unable to store the clock index, it will log an error, but
388 * will continue operating PTP.
390 static void ice_set_ptp_clock_index(struct ice_pf *pf)
392 struct device *dev = ice_pf_to_dev(pf);
393 enum ice_aqc_driver_params param_idx;
394 struct ice_hw *hw = &pf->hw;
402 tmr_idx = hw->func_caps.ts_func_info.tmr_index_assoc;
404 param_idx = ICE_AQC_DRIVER_PARAM_CLK_IDX_TMR0;
406 param_idx = ICE_AQC_DRIVER_PARAM_CLK_IDX_TMR1;
408 value = (u32)ptp_clock_index(pf->ptp.clock);
409 if (value > INT_MAX) {
410 dev_err(dev, "PTP Clock index is too large to store\n");
413 value |= PTP_SHARED_CLK_IDX_VALID;
415 err = ice_aq_set_driver_param(hw, param_idx, value, NULL);
417 dev_err(dev, "Failed to set PTP clock index parameter, err %d aq_err %s\n",
418 err, ice_aq_str(hw->adminq.sq_last_status));
423 * ice_clear_ptp_clock_index - Clear the PTP clock index
424 * @pf: the PF pointer
426 * Clear the PTP clock index for this device. Must be called when
427 * unregistering the PTP clock, in order to ensure other PFs stop reporting
428 * a clock object that no longer exists.
430 static void ice_clear_ptp_clock_index(struct ice_pf *pf)
432 struct device *dev = ice_pf_to_dev(pf);
433 enum ice_aqc_driver_params param_idx;
434 struct ice_hw *hw = &pf->hw;
438 /* Do not clear the index if we don't own the timer */
439 if (!hw->func_caps.ts_func_info.src_tmr_owned)
442 tmr_idx = hw->func_caps.ts_func_info.tmr_index_assoc;
444 param_idx = ICE_AQC_DRIVER_PARAM_CLK_IDX_TMR0;
446 param_idx = ICE_AQC_DRIVER_PARAM_CLK_IDX_TMR1;
448 err = ice_aq_set_driver_param(hw, param_idx, 0, NULL);
450 dev_dbg(dev, "Failed to clear PTP clock index parameter, err %d aq_err %s\n",
451 err, ice_aq_str(hw->adminq.sq_last_status));
456 * ice_ptp_read_src_clk_reg - Read the source clock register
457 * @pf: Board private structure
458 * @sts: Optional parameter for holding a pair of system timestamps from
459 * the system clock. Will be ignored if NULL is given.
462 ice_ptp_read_src_clk_reg(struct ice_pf *pf, struct ptp_system_timestamp *sts)
464 struct ice_hw *hw = &pf->hw;
468 tmr_idx = ice_get_ptp_src_clock_index(hw);
469 /* Read the system timestamp pre PHC read */
470 ptp_read_system_prets(sts);
472 lo = rd32(hw, GLTSYN_TIME_L(tmr_idx));
474 /* Read the system timestamp post PHC read */
475 ptp_read_system_postts(sts);
477 hi = rd32(hw, GLTSYN_TIME_H(tmr_idx));
478 lo2 = rd32(hw, GLTSYN_TIME_L(tmr_idx));
481 /* if TIME_L rolled over read TIME_L again and update
484 ptp_read_system_prets(sts);
485 lo = rd32(hw, GLTSYN_TIME_L(tmr_idx));
486 ptp_read_system_postts(sts);
487 hi = rd32(hw, GLTSYN_TIME_H(tmr_idx));
490 return ((u64)hi << 32) | lo;
494 * ice_ptp_extend_32b_ts - Convert a 32b nanoseconds timestamp to 64b
495 * @cached_phc_time: recently cached copy of PHC time
496 * @in_tstamp: Ingress/egress 32b nanoseconds timestamp value
498 * Hardware captures timestamps which contain only 32 bits of nominal
499 * nanoseconds, as opposed to the 64bit timestamps that the stack expects.
500 * Note that the captured timestamp values may be 40 bits, but the lower
501 * 8 bits are sub-nanoseconds and generally discarded.
503 * Extend the 32bit nanosecond timestamp using the following algorithm and
506 * 1) have a recently cached copy of the PHC time
507 * 2) assume that the in_tstamp was captured 2^31 nanoseconds (~2.1
508 * seconds) before or after the PHC time was captured.
509 * 3) calculate the delta between the cached time and the timestamp
510 * 4) if the delta is smaller than 2^31 nanoseconds, then the timestamp was
511 * captured after the PHC time. In this case, the full timestamp is just
512 * the cached PHC time plus the delta.
513 * 5) otherwise, if the delta is larger than 2^31 nanoseconds, then the
514 * timestamp was captured *before* the PHC time, i.e. because the PHC
515 * cache was updated after the timestamp was captured by hardware. In this
516 * case, the full timestamp is the cached time minus the inverse delta.
518 * This algorithm works even if the PHC time was updated after a Tx timestamp
519 * was requested, but before the Tx timestamp event was reported from
522 * This calculation primarily relies on keeping the cached PHC time up to
523 * date. If the timestamp was captured more than 2^31 nanoseconds after the
524 * PHC time, it is possible that the lower 32bits of PHC time have
525 * overflowed more than once, and we might generate an incorrect timestamp.
527 * This is prevented by (a) periodically updating the cached PHC time once
528 * a second, and (b) discarding any Tx timestamp packet if it has waited for
529 * a timestamp for more than one second.
531 static u64 ice_ptp_extend_32b_ts(u64 cached_phc_time, u32 in_tstamp)
533 u32 delta, phc_time_lo;
536 /* Extract the lower 32 bits of the PHC time */
537 phc_time_lo = (u32)cached_phc_time;
539 /* Calculate the delta between the lower 32bits of the cached PHC
540 * time and the in_tstamp value
542 delta = (in_tstamp - phc_time_lo);
544 /* Do not assume that the in_tstamp is always more recent than the
545 * cached PHC time. If the delta is large, it indicates that the
546 * in_tstamp was taken in the past, and should be converted
549 if (delta > (U32_MAX / 2)) {
550 /* reverse the delta calculation here */
551 delta = (phc_time_lo - in_tstamp);
552 ns = cached_phc_time - delta;
554 ns = cached_phc_time + delta;
561 * ice_ptp_extend_40b_ts - Convert a 40b timestamp to 64b nanoseconds
562 * @pf: Board private structure
563 * @in_tstamp: Ingress/egress 40b timestamp value
565 * The Tx and Rx timestamps are 40 bits wide, including 32 bits of nominal
566 * nanoseconds, 7 bits of sub-nanoseconds, and a valid bit.
568 * *--------------------------------------------------------------*
569 * | 32 bits of nanoseconds | 7 high bits of sub ns underflow | v |
570 * *--------------------------------------------------------------*
572 * The low bit is an indicator of whether the timestamp is valid. The next
573 * 7 bits are a capture of the upper 7 bits of the sub-nanosecond underflow,
574 * and the remaining 32 bits are the lower 32 bits of the PHC timer.
576 * It is assumed that the caller verifies the timestamp is valid prior to
577 * calling this function.
579 * Extract the 32bit nominal nanoseconds and extend them. Use the cached PHC
580 * time stored in the device private PTP structure as the basis for timestamp
583 * See ice_ptp_extend_32b_ts for a detailed explanation of the extension
586 static u64 ice_ptp_extend_40b_ts(struct ice_pf *pf, u64 in_tstamp)
588 const u64 mask = GENMASK_ULL(31, 0);
589 unsigned long discard_time;
591 /* Discard the hardware timestamp if the cached PHC time is too old */
592 discard_time = pf->ptp.cached_phc_jiffies + msecs_to_jiffies(2000);
593 if (time_is_before_jiffies(discard_time)) {
594 pf->ptp.tx_hwtstamp_discarded++;
598 return ice_ptp_extend_32b_ts(pf->ptp.cached_phc_time,
599 (in_tstamp >> 8) & mask);
603 * ice_ptp_tx_tstamp_work - Process Tx timestamps for a port
604 * @work: pointer to the kthread_work struct
606 * Process timestamps captured by the PHY associated with this port. To do
607 * this, loop over each index with a waiting skb.
609 * If a given index has a valid timestamp, perform the following steps:
611 * 1) copy the timestamp out of the PHY register
612 * 4) clear the timestamp valid bit in the PHY register
613 * 5) unlock the index by clearing the associated in_use bit.
614 * 2) extend the 40b timestamp value to get a 64bit timestamp
615 * 3) send that timestamp to the stack
617 * After looping, if we still have waiting SKBs, then re-queue the work. This
618 * may cause us effectively poll even when not strictly necessary. We do this
619 * because it's possible a new timestamp was requested around the same time as
620 * the interrupt. In some cases hardware might not interrupt us again when the
621 * timestamp is captured.
623 * Note that we only take the tracking lock when clearing the bit and when
624 * checking if we need to re-queue this task. The only place where bits can be
625 * set is the hard xmit routine where an SKB has a request flag set. The only
626 * places where we clear bits are this work function, or the periodic cleanup
627 * thread. If the cleanup thread clears a bit we're processing we catch it
628 * when we lock to clear the bit and then grab the SKB pointer. If a Tx thread
629 * starts a new timestamp, we might not begin processing it right away but we
630 * will notice it at the end when we re-queue the work item. If a Tx thread
631 * starts a new timestamp just after this function exits without re-queuing,
632 * the interrupt when the timestamp finishes should trigger. Avoiding holding
633 * the lock for the entire function is important in order to ensure that Tx
634 * threads do not get blocked while waiting for the lock.
636 static void ice_ptp_tx_tstamp_work(struct kthread_work *work)
638 struct ice_ptp_port *ptp_port;
639 struct ice_ptp_tx *tx;
644 tx = container_of(work, struct ice_ptp_tx, work);
648 ptp_port = container_of(tx, struct ice_ptp_port, tx);
649 pf = ptp_port_to_pf(ptp_port);
652 for_each_set_bit(idx, tx->in_use, tx->len) {
653 struct skb_shared_hwtstamps shhwtstamps = {};
654 u8 phy_idx = idx + tx->quad_offset;
655 u64 raw_tstamp, tstamp;
659 ice_trace(tx_tstamp_fw_req, tx->tstamps[idx].skb, idx);
661 err = ice_read_phy_tstamp(hw, tx->quad, phy_idx,
666 ice_trace(tx_tstamp_fw_done, tx->tstamps[idx].skb, idx);
668 /* Check if the timestamp is invalid or stale */
669 if (!(raw_tstamp & ICE_PTP_TS_VALID) ||
670 raw_tstamp == tx->tstamps[idx].cached_tstamp)
673 /* The timestamp is valid, so we'll go ahead and clear this
674 * index and then send the timestamp up to the stack.
676 spin_lock(&tx->lock);
677 tx->tstamps[idx].cached_tstamp = raw_tstamp;
678 clear_bit(idx, tx->in_use);
679 skb = tx->tstamps[idx].skb;
680 tx->tstamps[idx].skb = NULL;
681 spin_unlock(&tx->lock);
683 /* it's (unlikely but) possible we raced with the cleanup
684 * thread for discarding old timestamp requests.
689 /* Extend the timestamp using cached PHC time */
690 tstamp = ice_ptp_extend_40b_ts(pf, raw_tstamp);
692 shhwtstamps.hwtstamp = ns_to_ktime(tstamp);
693 ice_trace(tx_tstamp_complete, skb, idx);
696 skb_tstamp_tx(skb, &shhwtstamps);
697 dev_kfree_skb_any(skb);
700 /* Check if we still have work to do. If so, re-queue this task to
701 * poll for remaining timestamps.
703 spin_lock(&tx->lock);
704 if (!bitmap_empty(tx->in_use, tx->len))
705 kthread_queue_work(pf->ptp.kworker, &tx->work);
706 spin_unlock(&tx->lock);
710 * ice_ptp_alloc_tx_tracker - Initialize tracking for Tx timestamps
711 * @tx: Tx tracking structure to initialize
713 * Assumes that the length has already been initialized. Do not call directly,
714 * use the ice_ptp_init_tx_e822 or ice_ptp_init_tx_e810 instead.
717 ice_ptp_alloc_tx_tracker(struct ice_ptp_tx *tx)
719 tx->tstamps = kcalloc(tx->len, sizeof(*tx->tstamps), GFP_KERNEL);
723 tx->in_use = bitmap_zalloc(tx->len, GFP_KERNEL);
730 spin_lock_init(&tx->lock);
731 kthread_init_work(&tx->work, ice_ptp_tx_tstamp_work);
739 * ice_ptp_flush_tx_tracker - Flush any remaining timestamps from the tracker
740 * @pf: Board private structure
741 * @tx: the tracker to flush
744 ice_ptp_flush_tx_tracker(struct ice_pf *pf, struct ice_ptp_tx *tx)
748 for (idx = 0; idx < tx->len; idx++) {
749 u8 phy_idx = idx + tx->quad_offset;
751 spin_lock(&tx->lock);
752 if (tx->tstamps[idx].skb) {
753 dev_kfree_skb_any(tx->tstamps[idx].skb);
754 tx->tstamps[idx].skb = NULL;
755 pf->ptp.tx_hwtstamp_flushed++;
757 clear_bit(idx, tx->in_use);
758 spin_unlock(&tx->lock);
760 /* Clear any potential residual timestamp in the PHY block */
761 if (!pf->hw.reset_ongoing)
762 ice_clear_phy_tstamp(&pf->hw, tx->quad, phy_idx);
767 * ice_ptp_release_tx_tracker - Release allocated memory for Tx tracker
768 * @pf: Board private structure
769 * @tx: Tx tracking structure to release
771 * Free memory associated with the Tx timestamp tracker.
774 ice_ptp_release_tx_tracker(struct ice_pf *pf, struct ice_ptp_tx *tx)
778 kthread_cancel_work_sync(&tx->work);
780 ice_ptp_flush_tx_tracker(pf, tx);
785 bitmap_free(tx->in_use);
792 * ice_ptp_init_tx_e822 - Initialize tracking for Tx timestamps
793 * @pf: Board private structure
794 * @tx: the Tx tracking structure to initialize
795 * @port: the port this structure tracks
797 * Initialize the Tx timestamp tracker for this port. For generic MAC devices,
798 * the timestamp block is shared for all ports in the same quad. To avoid
799 * ports using the same timestamp index, logically break the block of
800 * registers into chunks based on the port number.
803 ice_ptp_init_tx_e822(struct ice_pf *pf, struct ice_ptp_tx *tx, u8 port)
805 tx->quad = port / ICE_PORTS_PER_QUAD;
806 tx->quad_offset = (port % ICE_PORTS_PER_QUAD) * INDEX_PER_PORT;
807 tx->len = INDEX_PER_PORT;
809 return ice_ptp_alloc_tx_tracker(tx);
813 * ice_ptp_init_tx_e810 - Initialize tracking for Tx timestamps
814 * @pf: Board private structure
815 * @tx: the Tx tracking structure to initialize
817 * Initialize the Tx timestamp tracker for this PF. For E810 devices, each
818 * port has its own block of timestamps, independent of the other ports.
821 ice_ptp_init_tx_e810(struct ice_pf *pf, struct ice_ptp_tx *tx)
823 tx->quad = pf->hw.port_info->lport;
825 tx->len = INDEX_PER_QUAD;
827 return ice_ptp_alloc_tx_tracker(tx);
831 * ice_ptp_tx_tstamp_cleanup - Cleanup old timestamp requests that got dropped
832 * @pf: pointer to the PF struct
833 * @tx: PTP Tx tracker to clean up
835 * Loop through the Tx timestamp requests and see if any of them have been
836 * waiting for a long time. Discard any SKBs that have been waiting for more
837 * than 2 seconds. This is long enough to be reasonably sure that the
838 * timestamp will never be captured. This might happen if the packet gets
839 * discarded before it reaches the PHY timestamping block.
841 static void ice_ptp_tx_tstamp_cleanup(struct ice_pf *pf, struct ice_ptp_tx *tx)
843 struct ice_hw *hw = &pf->hw;
849 for_each_set_bit(idx, tx->in_use, tx->len) {
853 /* Check if this SKB has been waiting for too long */
854 if (time_is_after_jiffies(tx->tstamps[idx].start + 2 * HZ))
857 /* Read tstamp to be able to use this register again */
858 ice_read_phy_tstamp(hw, tx->quad, idx + tx->quad_offset,
861 spin_lock(&tx->lock);
862 skb = tx->tstamps[idx].skb;
863 tx->tstamps[idx].skb = NULL;
864 clear_bit(idx, tx->in_use);
865 spin_unlock(&tx->lock);
867 /* Count the number of Tx timestamps which have timed out */
868 pf->ptp.tx_hwtstamp_timeouts++;
870 /* Free the SKB after we've cleared the bit */
871 dev_kfree_skb_any(skb);
876 * ice_ptp_update_cached_phctime - Update the cached PHC time values
877 * @pf: Board specific private structure
879 * This function updates the system time values which are cached in the PF
880 * structure and the Rx rings.
882 * This function must be called periodically to ensure that the cached value
883 * is never more than 2 seconds old. It must also be called whenever the PHC
884 * time has been changed.
887 * * 0 - OK, successfully updated
888 * * -EAGAIN - PF was busy, need to reschedule the update
890 static int ice_ptp_update_cached_phctime(struct ice_pf *pf)
892 struct device *dev = ice_pf_to_dev(pf);
893 unsigned long update_before;
897 if (test_and_set_bit(ICE_CFG_BUSY, pf->state))
900 update_before = pf->ptp.cached_phc_jiffies + msecs_to_jiffies(2000);
901 if (pf->ptp.cached_phc_time &&
902 time_is_before_jiffies(update_before)) {
903 unsigned long time_taken = jiffies - pf->ptp.cached_phc_jiffies;
905 dev_warn(dev, "%u msecs passed between update to cached PHC time\n",
906 jiffies_to_msecs(time_taken));
907 pf->ptp.late_cached_phc_updates++;
910 /* Read the current PHC time */
911 systime = ice_ptp_read_src_clk_reg(pf, NULL);
913 /* Update the cached PHC time stored in the PF structure */
914 WRITE_ONCE(pf->ptp.cached_phc_time, systime);
915 WRITE_ONCE(pf->ptp.cached_phc_jiffies, jiffies);
917 ice_for_each_vsi(pf, i) {
918 struct ice_vsi *vsi = pf->vsi[i];
924 if (vsi->type != ICE_VSI_PF)
927 ice_for_each_rxq(vsi, j) {
928 if (!vsi->rx_rings[j])
930 WRITE_ONCE(vsi->rx_rings[j]->cached_phctime, systime);
933 clear_bit(ICE_CFG_BUSY, pf->state);
939 * ice_ptp_read_time - Read the time from the device
940 * @pf: Board private structure
941 * @ts: timespec structure to hold the current time value
942 * @sts: Optional parameter for holding a pair of system timestamps from
943 * the system clock. Will be ignored if NULL is given.
945 * This function reads the source clock registers and stores them in a timespec.
946 * However, since the registers are 64 bits of nanoseconds, we must convert the
947 * result to a timespec before we can return.
950 ice_ptp_read_time(struct ice_pf *pf, struct timespec64 *ts,
951 struct ptp_system_timestamp *sts)
953 u64 time_ns = ice_ptp_read_src_clk_reg(pf, sts);
955 *ts = ns_to_timespec64(time_ns);
959 * ice_ptp_write_init - Set PHC time to provided value
960 * @pf: Board private structure
961 * @ts: timespec structure that holds the new time value
963 * Set the PHC time to the specified time provided in the timespec.
965 static int ice_ptp_write_init(struct ice_pf *pf, struct timespec64 *ts)
967 u64 ns = timespec64_to_ns(ts);
968 struct ice_hw *hw = &pf->hw;
970 return ice_ptp_init_time(hw, ns);
974 * ice_ptp_write_adj - Adjust PHC clock time atomically
975 * @pf: Board private structure
976 * @adj: Adjustment in nanoseconds
978 * Perform an atomic adjustment of the PHC time by the specified number of
981 static int ice_ptp_write_adj(struct ice_pf *pf, s32 adj)
983 struct ice_hw *hw = &pf->hw;
985 return ice_ptp_adj_clock(hw, adj);
989 * ice_base_incval - Get base timer increment value
990 * @pf: Board private structure
992 * Look up the base timer increment value for this device. The base increment
993 * value is used to define the nominal clock tick rate. This increment value
994 * is programmed during device initialization. It is also used as the basis
995 * for calculating adjustments using scaled_ppm.
997 static u64 ice_base_incval(struct ice_pf *pf)
999 struct ice_hw *hw = &pf->hw;
1002 if (ice_is_e810(hw))
1003 incval = ICE_PTP_NOMINAL_INCVAL_E810;
1004 else if (ice_e822_time_ref(hw) < NUM_ICE_TIME_REF_FREQ)
1005 incval = ice_e822_nominal_incval(ice_e822_time_ref(hw));
1007 incval = UNKNOWN_INCVAL_E822;
1009 dev_dbg(ice_pf_to_dev(pf), "PTP: using base increment value of 0x%016llx\n",
1016 * ice_ptp_reset_ts_memory_quad - Reset timestamp memory for one quad
1017 * @pf: The PF private data structure
1018 * @quad: The quad (0-4)
1020 static void ice_ptp_reset_ts_memory_quad(struct ice_pf *pf, int quad)
1022 struct ice_hw *hw = &pf->hw;
1024 ice_write_quad_reg_e822(hw, quad, Q_REG_TS_CTRL, Q_REG_TS_CTRL_M);
1025 ice_write_quad_reg_e822(hw, quad, Q_REG_TS_CTRL, ~(u32)Q_REG_TS_CTRL_M);
1029 * ice_ptp_check_tx_fifo - Check whether Tx FIFO is in an OK state
1030 * @port: PTP port for which Tx FIFO is checked
1032 static int ice_ptp_check_tx_fifo(struct ice_ptp_port *port)
1034 int quad = port->port_num / ICE_PORTS_PER_QUAD;
1035 int offs = port->port_num % ICE_PORTS_PER_QUAD;
1041 pf = ptp_port_to_pf(port);
1044 if (port->tx_fifo_busy_cnt == FIFO_OK)
1047 /* need to read FIFO state */
1048 if (offs == 0 || offs == 1)
1049 err = ice_read_quad_reg_e822(hw, quad, Q_REG_FIFO01_STATUS,
1052 err = ice_read_quad_reg_e822(hw, quad, Q_REG_FIFO23_STATUS,
1056 dev_err(ice_pf_to_dev(pf), "PTP failed to check port %d Tx FIFO, err %d\n",
1057 port->port_num, err);
1062 phy_sts = (val & Q_REG_FIFO13_M) >> Q_REG_FIFO13_S;
1064 phy_sts = (val & Q_REG_FIFO02_M) >> Q_REG_FIFO02_S;
1066 if (phy_sts & FIFO_EMPTY) {
1067 port->tx_fifo_busy_cnt = FIFO_OK;
1071 port->tx_fifo_busy_cnt++;
1073 dev_dbg(ice_pf_to_dev(pf), "Try %d, port %d FIFO not empty\n",
1074 port->tx_fifo_busy_cnt, port->port_num);
1076 if (port->tx_fifo_busy_cnt == ICE_PTP_FIFO_NUM_CHECKS) {
1077 dev_dbg(ice_pf_to_dev(pf),
1078 "Port %d Tx FIFO still not empty; resetting quad %d\n",
1079 port->port_num, quad);
1080 ice_ptp_reset_ts_memory_quad(pf, quad);
1081 port->tx_fifo_busy_cnt = FIFO_OK;
1089 * ice_ptp_check_tx_offset_valid - Check if the Tx PHY offset is valid
1090 * @port: the PTP port to check
1092 * Checks whether the Tx offset for the PHY associated with this port is
1093 * valid. Returns 0 if the offset is valid, and a non-zero error code if it is
1096 static int ice_ptp_check_tx_offset_valid(struct ice_ptp_port *port)
1098 struct ice_pf *pf = ptp_port_to_pf(port);
1099 struct device *dev = ice_pf_to_dev(pf);
1100 struct ice_hw *hw = &pf->hw;
1104 err = ice_ptp_check_tx_fifo(port);
1108 err = ice_read_phy_reg_e822(hw, port->port_num, P_REG_TX_OV_STATUS,
1111 dev_err(dev, "Failed to read TX_OV_STATUS for port %d, err %d\n",
1112 port->port_num, err);
1116 if (!(val & P_REG_TX_OV_STATUS_OV_M))
1123 * ice_ptp_check_rx_offset_valid - Check if the Rx PHY offset is valid
1124 * @port: the PTP port to check
1126 * Checks whether the Rx offset for the PHY associated with this port is
1127 * valid. Returns 0 if the offset is valid, and a non-zero error code if it is
1130 static int ice_ptp_check_rx_offset_valid(struct ice_ptp_port *port)
1132 struct ice_pf *pf = ptp_port_to_pf(port);
1133 struct device *dev = ice_pf_to_dev(pf);
1134 struct ice_hw *hw = &pf->hw;
1138 err = ice_read_phy_reg_e822(hw, port->port_num, P_REG_RX_OV_STATUS,
1141 dev_err(dev, "Failed to read RX_OV_STATUS for port %d, err %d\n",
1142 port->port_num, err);
1146 if (!(val & P_REG_RX_OV_STATUS_OV_M))
1153 * ice_ptp_check_offset_valid - Check port offset valid bit
1154 * @port: Port for which offset valid bit is checked
1156 * Returns 0 if both Tx and Rx offset are valid, and -EAGAIN if one of the
1157 * offset is not ready.
1159 static int ice_ptp_check_offset_valid(struct ice_ptp_port *port)
1163 /* always check both Tx and Rx offset validity */
1164 tx_err = ice_ptp_check_tx_offset_valid(port);
1165 rx_err = ice_ptp_check_rx_offset_valid(port);
1167 if (tx_err || rx_err)
1174 * ice_ptp_wait_for_offset_valid - Check for valid Tx and Rx offsets
1175 * @work: Pointer to the kthread_work structure for this task
1177 * Check whether both the Tx and Rx offsets are valid for enabling the vernier
1180 * Once we have valid offsets from hardware, update the total Tx and Rx
1181 * offsets, and exit bypass mode. This enables more precise timestamps using
1182 * the extra data measured during the vernier calibration process.
1184 static void ice_ptp_wait_for_offset_valid(struct kthread_work *work)
1186 struct ice_ptp_port *port;
1192 port = container_of(work, struct ice_ptp_port, ov_work.work);
1193 pf = ptp_port_to_pf(port);
1195 dev = ice_pf_to_dev(pf);
1197 if (ice_ptp_check_offset_valid(port)) {
1198 /* Offsets not ready yet, try again later */
1199 kthread_queue_delayed_work(pf->ptp.kworker,
1201 msecs_to_jiffies(100));
1205 /* Offsets are valid, so it is safe to exit bypass mode */
1206 err = ice_phy_exit_bypass_e822(hw, port->port_num);
1208 dev_warn(dev, "Failed to exit bypass mode for PHY port %u, err %d\n",
1209 port->port_num, err);
1215 * ice_ptp_port_phy_stop - Stop timestamping for a PHY port
1216 * @ptp_port: PTP port to stop
1219 ice_ptp_port_phy_stop(struct ice_ptp_port *ptp_port)
1221 struct ice_pf *pf = ptp_port_to_pf(ptp_port);
1222 u8 port = ptp_port->port_num;
1223 struct ice_hw *hw = &pf->hw;
1226 if (ice_is_e810(hw))
1229 mutex_lock(&ptp_port->ps_lock);
1231 kthread_cancel_delayed_work_sync(&ptp_port->ov_work);
1233 err = ice_stop_phy_timer_e822(hw, port, true);
1235 dev_err(ice_pf_to_dev(pf), "PTP failed to set PHY port %d down, err %d\n",
1238 mutex_unlock(&ptp_port->ps_lock);
1244 * ice_ptp_port_phy_restart - (Re)start and calibrate PHY timestamping
1245 * @ptp_port: PTP port for which the PHY start is set
1247 * Start the PHY timestamping block, and initiate Vernier timestamping
1248 * calibration. If timestamping cannot be calibrated (such as if link is down)
1249 * then disable the timestamping block instead.
1252 ice_ptp_port_phy_restart(struct ice_ptp_port *ptp_port)
1254 struct ice_pf *pf = ptp_port_to_pf(ptp_port);
1255 u8 port = ptp_port->port_num;
1256 struct ice_hw *hw = &pf->hw;
1259 if (ice_is_e810(hw))
1262 if (!ptp_port->link_up)
1263 return ice_ptp_port_phy_stop(ptp_port);
1265 mutex_lock(&ptp_port->ps_lock);
1267 kthread_cancel_delayed_work_sync(&ptp_port->ov_work);
1269 /* temporarily disable Tx timestamps while calibrating PHY offset */
1270 ptp_port->tx.calibrating = true;
1271 ptp_port->tx_fifo_busy_cnt = 0;
1273 /* Start the PHY timer in bypass mode */
1274 err = ice_start_phy_timer_e822(hw, port, true);
1278 /* Enable Tx timestamps right away */
1279 ptp_port->tx.calibrating = false;
1281 kthread_queue_delayed_work(pf->ptp.kworker, &ptp_port->ov_work, 0);
1285 dev_err(ice_pf_to_dev(pf), "PTP failed to set PHY port %d up, err %d\n",
1288 mutex_unlock(&ptp_port->ps_lock);
1294 * ice_ptp_link_change - Set or clear port registers for timestamping
1295 * @pf: Board private structure
1296 * @port: Port for which the PHY start is set
1297 * @linkup: Link is up or down
1299 int ice_ptp_link_change(struct ice_pf *pf, u8 port, bool linkup)
1301 struct ice_ptp_port *ptp_port;
1303 if (!test_bit(ICE_FLAG_PTP_SUPPORTED, pf->flags))
1306 if (port >= ICE_NUM_EXTERNAL_PORTS)
1309 ptp_port = &pf->ptp.port;
1310 if (ptp_port->port_num != port)
1313 /* Update cached link err for this port immediately */
1314 ptp_port->link_up = linkup;
1316 if (!test_bit(ICE_FLAG_PTP, pf->flags))
1317 /* PTP is not setup */
1320 return ice_ptp_port_phy_restart(ptp_port);
1324 * ice_ptp_reset_ts_memory - Reset timestamp memory for all quads
1325 * @pf: The PF private data structure
1327 static void ice_ptp_reset_ts_memory(struct ice_pf *pf)
1331 quad = pf->hw.port_info->lport / ICE_PORTS_PER_QUAD;
1332 ice_ptp_reset_ts_memory_quad(pf, quad);
1336 * ice_ptp_tx_ena_intr - Enable or disable the Tx timestamp interrupt
1337 * @pf: PF private structure
1338 * @ena: bool value to enable or disable interrupt
1339 * @threshold: Minimum number of packets at which intr is triggered
1341 * Utility function to enable or disable Tx timestamp interrupt and threshold
1343 static int ice_ptp_tx_ena_intr(struct ice_pf *pf, bool ena, u32 threshold)
1345 struct ice_hw *hw = &pf->hw;
1350 ice_ptp_reset_ts_memory(pf);
1352 for (quad = 0; quad < ICE_MAX_QUAD; quad++) {
1353 err = ice_read_quad_reg_e822(hw, quad, Q_REG_TX_MEM_GBL_CFG,
1359 val |= Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M;
1360 val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_THR_M;
1361 val |= ((threshold << Q_REG_TX_MEM_GBL_CFG_INTR_THR_S) &
1362 Q_REG_TX_MEM_GBL_CFG_INTR_THR_M);
1364 val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M;
1367 err = ice_write_quad_reg_e822(hw, quad, Q_REG_TX_MEM_GBL_CFG,
1374 dev_err(ice_pf_to_dev(pf), "PTP failed in intr ena, err %d\n",
1380 * ice_ptp_reset_phy_timestamping - Reset PHY timestamping block
1381 * @pf: Board private structure
1383 static void ice_ptp_reset_phy_timestamping(struct ice_pf *pf)
1385 ice_ptp_port_phy_restart(&pf->ptp.port);
1389 * ice_ptp_adjfine - Adjust clock increment rate
1390 * @info: the driver's PTP info structure
1391 * @scaled_ppm: Parts per million with 16-bit fractional field
1393 * Adjust the frequency of the clock by the indicated scaled ppm from the
1396 static int ice_ptp_adjfine(struct ptp_clock_info *info, long scaled_ppm)
1398 struct ice_pf *pf = ptp_info_to_pf(info);
1399 struct ice_hw *hw = &pf->hw;
1404 incval = ice_base_incval(pf);
1406 if (scaled_ppm < 0) {
1408 scaled_ppm = -scaled_ppm;
1411 diff = mul_u64_u64_div_u64(incval, (u64)scaled_ppm,
1418 err = ice_ptp_write_incval_locked(hw, incval);
1420 dev_err(ice_pf_to_dev(pf), "PTP failed to set incval, err %d\n",
1429 * ice_ptp_extts_work - Workqueue task function
1430 * @work: external timestamp work structure
1432 * Service for PTP external clock event
1434 static void ice_ptp_extts_work(struct kthread_work *work)
1436 struct ice_ptp *ptp = container_of(work, struct ice_ptp, extts_work);
1437 struct ice_pf *pf = container_of(ptp, struct ice_pf, ptp);
1438 struct ptp_clock_event event;
1439 struct ice_hw *hw = &pf->hw;
1443 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
1444 /* Event time is captured by one of the two matched registers
1445 * GLTSYN_EVNT_L: 32 LSB of sampled time event
1446 * GLTSYN_EVNT_H: 32 MSB of sampled time event
1447 * Event is defined in GLTSYN_EVNT_0 register
1449 for (chan = 0; chan < GLTSYN_EVNT_H_IDX_MAX; chan++) {
1450 /* Check if channel is enabled */
1451 if (pf->ptp.ext_ts_irq & (1 << chan)) {
1452 lo = rd32(hw, GLTSYN_EVNT_L(chan, tmr_idx));
1453 hi = rd32(hw, GLTSYN_EVNT_H(chan, tmr_idx));
1454 event.timestamp = (((u64)hi) << 32) | lo;
1455 event.type = PTP_CLOCK_EXTTS;
1459 ptp_clock_event(pf->ptp.clock, &event);
1460 pf->ptp.ext_ts_irq &= ~(1 << chan);
1466 * ice_ptp_cfg_extts - Configure EXTTS pin and channel
1467 * @pf: Board private structure
1468 * @ena: true to enable; false to disable
1469 * @chan: GPIO channel (0-3)
1470 * @gpio_pin: GPIO pin
1471 * @extts_flags: request flags from the ptp_extts_request.flags
1474 ice_ptp_cfg_extts(struct ice_pf *pf, bool ena, unsigned int chan, u32 gpio_pin,
1475 unsigned int extts_flags)
1477 u32 func, aux_reg, gpio_reg, irq_reg;
1478 struct ice_hw *hw = &pf->hw;
1481 if (chan > (unsigned int)pf->ptp.info.n_ext_ts)
1484 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
1486 irq_reg = rd32(hw, PFINT_OICR_ENA);
1489 /* Enable the interrupt */
1490 irq_reg |= PFINT_OICR_TSYN_EVNT_M;
1491 aux_reg = GLTSYN_AUX_IN_0_INT_ENA_M;
1493 #define GLTSYN_AUX_IN_0_EVNTLVL_RISING_EDGE BIT(0)
1494 #define GLTSYN_AUX_IN_0_EVNTLVL_FALLING_EDGE BIT(1)
1496 /* set event level to requested edge */
1497 if (extts_flags & PTP_FALLING_EDGE)
1498 aux_reg |= GLTSYN_AUX_IN_0_EVNTLVL_FALLING_EDGE;
1499 if (extts_flags & PTP_RISING_EDGE)
1500 aux_reg |= GLTSYN_AUX_IN_0_EVNTLVL_RISING_EDGE;
1502 /* Write GPIO CTL reg.
1503 * 0x1 is input sampled by EVENT register(channel)
1504 * + num_in_channels * tmr_idx
1506 func = 1 + chan + (tmr_idx * 3);
1507 gpio_reg = ((func << GLGEN_GPIO_CTL_PIN_FUNC_S) &
1508 GLGEN_GPIO_CTL_PIN_FUNC_M);
1509 pf->ptp.ext_ts_chan |= (1 << chan);
1511 /* clear the values we set to reset defaults */
1514 pf->ptp.ext_ts_chan &= ~(1 << chan);
1515 if (!pf->ptp.ext_ts_chan)
1516 irq_reg &= ~PFINT_OICR_TSYN_EVNT_M;
1519 wr32(hw, PFINT_OICR_ENA, irq_reg);
1520 wr32(hw, GLTSYN_AUX_IN(chan, tmr_idx), aux_reg);
1521 wr32(hw, GLGEN_GPIO_CTL(gpio_pin), gpio_reg);
1527 * ice_ptp_cfg_clkout - Configure clock to generate periodic wave
1528 * @pf: Board private structure
1529 * @chan: GPIO channel (0-3)
1530 * @config: desired periodic clk configuration. NULL will disable channel
1531 * @store: If set to true the values will be stored
1533 * Configure the internal clock generator modules to generate the clock wave of
1536 static int ice_ptp_cfg_clkout(struct ice_pf *pf, unsigned int chan,
1537 struct ice_perout_channel *config, bool store)
1539 u64 current_time, period, start_time, phase;
1540 struct ice_hw *hw = &pf->hw;
1541 u32 func, val, gpio_pin;
1544 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
1546 /* 0. Reset mode & out_en in AUX_OUT */
1547 wr32(hw, GLTSYN_AUX_OUT(chan, tmr_idx), 0);
1549 /* If we're disabling the output, clear out CLKO and TGT and keep
1552 if (!config || !config->ena) {
1553 wr32(hw, GLTSYN_CLKO(chan, tmr_idx), 0);
1554 wr32(hw, GLTSYN_TGT_L(chan, tmr_idx), 0);
1555 wr32(hw, GLTSYN_TGT_H(chan, tmr_idx), 0);
1557 val = GLGEN_GPIO_CTL_PIN_DIR_M;
1558 gpio_pin = pf->ptp.perout_channels[chan].gpio_pin;
1559 wr32(hw, GLGEN_GPIO_CTL(gpio_pin), val);
1561 /* Store the value if requested */
1563 memset(&pf->ptp.perout_channels[chan], 0,
1564 sizeof(struct ice_perout_channel));
1568 period = config->period;
1569 start_time = config->start_time;
1570 div64_u64_rem(start_time, period, &phase);
1571 gpio_pin = config->gpio_pin;
1573 /* 1. Write clkout with half of required period value */
1575 dev_err(ice_pf_to_dev(pf), "CLK Period must be an even value\n");
1581 /* For proper operation, the GLTSYN_CLKO must be larger than clock tick
1584 if (period <= MIN_PULSE || period > U32_MAX) {
1585 dev_err(ice_pf_to_dev(pf), "CLK Period must be > %d && < 2^33",
1590 wr32(hw, GLTSYN_CLKO(chan, tmr_idx), lower_32_bits(period));
1592 /* Allow time for programming before start_time is hit */
1593 current_time = ice_ptp_read_src_clk_reg(pf, NULL);
1595 /* if start time is in the past start the timer at the nearest second
1598 if (start_time < current_time)
1599 start_time = div64_u64(current_time + NSEC_PER_SEC - 1,
1600 NSEC_PER_SEC) * NSEC_PER_SEC + phase;
1602 if (ice_is_e810(hw))
1603 start_time -= E810_OUT_PROP_DELAY_NS;
1605 start_time -= ice_e822_pps_delay(ice_e822_time_ref(hw));
1607 /* 2. Write TARGET time */
1608 wr32(hw, GLTSYN_TGT_L(chan, tmr_idx), lower_32_bits(start_time));
1609 wr32(hw, GLTSYN_TGT_H(chan, tmr_idx), upper_32_bits(start_time));
1611 /* 3. Write AUX_OUT register */
1612 val = GLTSYN_AUX_OUT_0_OUT_ENA_M | GLTSYN_AUX_OUT_0_OUTMOD_M;
1613 wr32(hw, GLTSYN_AUX_OUT(chan, tmr_idx), val);
1615 /* 4. write GPIO CTL reg */
1616 func = 8 + chan + (tmr_idx * 4);
1617 val = GLGEN_GPIO_CTL_PIN_DIR_M |
1618 ((func << GLGEN_GPIO_CTL_PIN_FUNC_S) & GLGEN_GPIO_CTL_PIN_FUNC_M);
1619 wr32(hw, GLGEN_GPIO_CTL(gpio_pin), val);
1621 /* Store the value if requested */
1623 memcpy(&pf->ptp.perout_channels[chan], config,
1624 sizeof(struct ice_perout_channel));
1625 pf->ptp.perout_channels[chan].start_time = phase;
1630 dev_err(ice_pf_to_dev(pf), "PTP failed to cfg per_clk\n");
1635 * ice_ptp_disable_all_clkout - Disable all currently configured outputs
1636 * @pf: pointer to the PF structure
1638 * Disable all currently configured clock outputs. This is necessary before
1639 * certain changes to the PTP hardware clock. Use ice_ptp_enable_all_clkout to
1640 * re-enable the clocks again.
1642 static void ice_ptp_disable_all_clkout(struct ice_pf *pf)
1646 for (i = 0; i < pf->ptp.info.n_per_out; i++)
1647 if (pf->ptp.perout_channels[i].ena)
1648 ice_ptp_cfg_clkout(pf, i, NULL, false);
1652 * ice_ptp_enable_all_clkout - Enable all configured periodic clock outputs
1653 * @pf: pointer to the PF structure
1655 * Enable all currently configured clock outputs. Use this after
1656 * ice_ptp_disable_all_clkout to reconfigure the output signals according to
1657 * their configuration.
1659 static void ice_ptp_enable_all_clkout(struct ice_pf *pf)
1663 for (i = 0; i < pf->ptp.info.n_per_out; i++)
1664 if (pf->ptp.perout_channels[i].ena)
1665 ice_ptp_cfg_clkout(pf, i, &pf->ptp.perout_channels[i],
1670 * ice_ptp_gpio_enable_e810 - Enable/disable ancillary features of PHC
1671 * @info: the driver's PTP info structure
1672 * @rq: The requested feature to change
1673 * @on: Enable/disable flag
1676 ice_ptp_gpio_enable_e810(struct ptp_clock_info *info,
1677 struct ptp_clock_request *rq, int on)
1679 struct ice_pf *pf = ptp_info_to_pf(info);
1680 struct ice_perout_channel clk_cfg = {0};
1681 bool sma_pres = false;
1686 if (ice_is_feature_supported(pf, ICE_F_SMA_CTRL))
1690 case PTP_CLK_REQ_PEROUT:
1691 chan = rq->perout.index;
1693 if (chan == ice_pin_desc_e810t[SMA1].chan)
1694 clk_cfg.gpio_pin = GPIO_20;
1695 else if (chan == ice_pin_desc_e810t[SMA2].chan)
1696 clk_cfg.gpio_pin = GPIO_22;
1699 } else if (ice_is_e810t(&pf->hw)) {
1701 clk_cfg.gpio_pin = GPIO_20;
1703 clk_cfg.gpio_pin = GPIO_22;
1704 } else if (chan == PPS_CLK_GEN_CHAN) {
1705 clk_cfg.gpio_pin = PPS_PIN_INDEX;
1707 clk_cfg.gpio_pin = chan;
1710 clk_cfg.period = ((rq->perout.period.sec * NSEC_PER_SEC) +
1711 rq->perout.period.nsec);
1712 clk_cfg.start_time = ((rq->perout.start.sec * NSEC_PER_SEC) +
1713 rq->perout.start.nsec);
1716 err = ice_ptp_cfg_clkout(pf, chan, &clk_cfg, true);
1718 case PTP_CLK_REQ_EXTTS:
1719 chan = rq->extts.index;
1721 if (chan < ice_pin_desc_e810t[SMA2].chan)
1725 } else if (ice_is_e810t(&pf->hw)) {
1734 err = ice_ptp_cfg_extts(pf, !!on, chan, gpio_pin,
1745 * ice_ptp_gettimex64 - Get the time of the clock
1746 * @info: the driver's PTP info structure
1747 * @ts: timespec64 structure to hold the current time value
1748 * @sts: Optional parameter for holding a pair of system timestamps from
1749 * the system clock. Will be ignored if NULL is given.
1751 * Read the device clock and return the correct value on ns, after converting it
1752 * into a timespec struct.
1755 ice_ptp_gettimex64(struct ptp_clock_info *info, struct timespec64 *ts,
1756 struct ptp_system_timestamp *sts)
1758 struct ice_pf *pf = ptp_info_to_pf(info);
1759 struct ice_hw *hw = &pf->hw;
1761 if (!ice_ptp_lock(hw)) {
1762 dev_err(ice_pf_to_dev(pf), "PTP failed to get time\n");
1766 ice_ptp_read_time(pf, ts, sts);
1773 * ice_ptp_settime64 - Set the time of the clock
1774 * @info: the driver's PTP info structure
1775 * @ts: timespec64 structure that holds the new time value
1777 * Set the device clock to the user input value. The conversion from timespec
1778 * to ns happens in the write function.
1781 ice_ptp_settime64(struct ptp_clock_info *info, const struct timespec64 *ts)
1783 struct ice_pf *pf = ptp_info_to_pf(info);
1784 struct timespec64 ts64 = *ts;
1785 struct ice_hw *hw = &pf->hw;
1788 /* For Vernier mode, we need to recalibrate after new settime
1789 * Start with disabling timestamp block
1791 if (pf->ptp.port.link_up)
1792 ice_ptp_port_phy_stop(&pf->ptp.port);
1794 if (!ice_ptp_lock(hw)) {
1799 /* Disable periodic outputs */
1800 ice_ptp_disable_all_clkout(pf);
1802 err = ice_ptp_write_init(pf, &ts64);
1806 ice_ptp_update_cached_phctime(pf);
1808 /* Reenable periodic outputs */
1809 ice_ptp_enable_all_clkout(pf);
1811 /* Recalibrate and re-enable timestamp block */
1812 if (pf->ptp.port.link_up)
1813 ice_ptp_port_phy_restart(&pf->ptp.port);
1816 dev_err(ice_pf_to_dev(pf), "PTP failed to set time %d\n", err);
1824 * ice_ptp_adjtime_nonatomic - Do a non-atomic clock adjustment
1825 * @info: the driver's PTP info structure
1826 * @delta: Offset in nanoseconds to adjust the time by
1828 static int ice_ptp_adjtime_nonatomic(struct ptp_clock_info *info, s64 delta)
1830 struct timespec64 now, then;
1833 then = ns_to_timespec64(delta);
1834 ret = ice_ptp_gettimex64(info, &now, NULL);
1837 now = timespec64_add(now, then);
1839 return ice_ptp_settime64(info, (const struct timespec64 *)&now);
1843 * ice_ptp_adjtime - Adjust the time of the clock by the indicated delta
1844 * @info: the driver's PTP info structure
1845 * @delta: Offset in nanoseconds to adjust the time by
1847 static int ice_ptp_adjtime(struct ptp_clock_info *info, s64 delta)
1849 struct ice_pf *pf = ptp_info_to_pf(info);
1850 struct ice_hw *hw = &pf->hw;
1854 dev = ice_pf_to_dev(pf);
1856 /* Hardware only supports atomic adjustments using signed 32-bit
1857 * integers. For any adjustment outside this range, perform
1858 * a non-atomic get->adjust->set flow.
1860 if (delta > S32_MAX || delta < S32_MIN) {
1861 dev_dbg(dev, "delta = %lld, adjtime non-atomic\n", delta);
1862 return ice_ptp_adjtime_nonatomic(info, delta);
1865 if (!ice_ptp_lock(hw)) {
1866 dev_err(dev, "PTP failed to acquire semaphore in adjtime\n");
1870 /* Disable periodic outputs */
1871 ice_ptp_disable_all_clkout(pf);
1873 err = ice_ptp_write_adj(pf, delta);
1875 /* Reenable periodic outputs */
1876 ice_ptp_enable_all_clkout(pf);
1881 dev_err(dev, "PTP failed to adjust time, err %d\n", err);
1885 ice_ptp_update_cached_phctime(pf);
1890 #ifdef CONFIG_ICE_HWTS
1892 * ice_ptp_get_syncdevicetime - Get the cross time stamp info
1893 * @device: Current device time
1894 * @system: System counter value read synchronously with device time
1895 * @ctx: Context provided by timekeeping code
1897 * Read device and system (ART) clock simultaneously and return the corrected
1898 * clock values in ns.
1901 ice_ptp_get_syncdevicetime(ktime_t *device,
1902 struct system_counterval_t *system,
1905 struct ice_pf *pf = (struct ice_pf *)ctx;
1906 struct ice_hw *hw = &pf->hw;
1907 u32 hh_lock, hh_art_ctl;
1910 /* Get the HW lock */
1911 hh_lock = rd32(hw, PFHH_SEM + (PFTSYN_SEM_BYTES * hw->pf_id));
1912 if (hh_lock & PFHH_SEM_BUSY_M) {
1913 dev_err(ice_pf_to_dev(pf), "PTP failed to get hh lock\n");
1917 /* Start the ART and device clock sync sequence */
1918 hh_art_ctl = rd32(hw, GLHH_ART_CTL);
1919 hh_art_ctl = hh_art_ctl | GLHH_ART_CTL_ACTIVE_M;
1920 wr32(hw, GLHH_ART_CTL, hh_art_ctl);
1922 #define MAX_HH_LOCK_TRIES 100
1924 for (i = 0; i < MAX_HH_LOCK_TRIES; i++) {
1925 /* Wait for sync to complete */
1926 hh_art_ctl = rd32(hw, GLHH_ART_CTL);
1927 if (hh_art_ctl & GLHH_ART_CTL_ACTIVE_M) {
1931 u32 hh_ts_lo, hh_ts_hi, tmr_idx;
1934 tmr_idx = hw->func_caps.ts_func_info.tmr_index_assoc;
1936 hh_ts_lo = rd32(hw, GLHH_ART_TIME_L);
1937 hh_ts_hi = rd32(hw, GLHH_ART_TIME_H);
1938 hh_ts = ((u64)hh_ts_hi << 32) | hh_ts_lo;
1939 *system = convert_art_ns_to_tsc(hh_ts);
1940 /* Read Device source clock time */
1941 hh_ts_lo = rd32(hw, GLTSYN_HHTIME_L(tmr_idx));
1942 hh_ts_hi = rd32(hw, GLTSYN_HHTIME_H(tmr_idx));
1943 hh_ts = ((u64)hh_ts_hi << 32) | hh_ts_lo;
1944 *device = ns_to_ktime(hh_ts);
1948 /* Release HW lock */
1949 hh_lock = rd32(hw, PFHH_SEM + (PFTSYN_SEM_BYTES * hw->pf_id));
1950 hh_lock = hh_lock & ~PFHH_SEM_BUSY_M;
1951 wr32(hw, PFHH_SEM + (PFTSYN_SEM_BYTES * hw->pf_id), hh_lock);
1953 if (i == MAX_HH_LOCK_TRIES)
1960 * ice_ptp_getcrosststamp_e822 - Capture a device cross timestamp
1961 * @info: the driver's PTP info structure
1962 * @cts: The memory to fill the cross timestamp info
1964 * Capture a cross timestamp between the ART and the device PTP hardware
1965 * clock. Fill the cross timestamp information and report it back to the
1968 * This is only valid for E822 devices which have support for generating the
1969 * cross timestamp via PCIe PTM.
1971 * In order to correctly correlate the ART timestamp back to the TSC time, the
1972 * CPU must have X86_FEATURE_TSC_KNOWN_FREQ.
1975 ice_ptp_getcrosststamp_e822(struct ptp_clock_info *info,
1976 struct system_device_crosststamp *cts)
1978 struct ice_pf *pf = ptp_info_to_pf(info);
1980 return get_device_system_crosststamp(ice_ptp_get_syncdevicetime,
1983 #endif /* CONFIG_ICE_HWTS */
1986 * ice_ptp_get_ts_config - ioctl interface to read the timestamping config
1987 * @pf: Board private structure
1990 * Copy the timestamping config to user buffer
1992 int ice_ptp_get_ts_config(struct ice_pf *pf, struct ifreq *ifr)
1994 struct hwtstamp_config *config;
1996 if (!test_bit(ICE_FLAG_PTP, pf->flags))
1999 config = &pf->ptp.tstamp_config;
2001 return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ?
2006 * ice_ptp_set_timestamp_mode - Setup driver for requested timestamp mode
2007 * @pf: Board private structure
2008 * @config: hwtstamp settings requested or saved
2011 ice_ptp_set_timestamp_mode(struct ice_pf *pf, struct hwtstamp_config *config)
2013 switch (config->tx_type) {
2014 case HWTSTAMP_TX_OFF:
2015 ice_set_tx_tstamp(pf, false);
2017 case HWTSTAMP_TX_ON:
2018 ice_set_tx_tstamp(pf, true);
2024 switch (config->rx_filter) {
2025 case HWTSTAMP_FILTER_NONE:
2026 ice_set_rx_tstamp(pf, false);
2028 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
2029 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
2030 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
2031 case HWTSTAMP_FILTER_PTP_V2_EVENT:
2032 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
2033 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2034 case HWTSTAMP_FILTER_PTP_V2_SYNC:
2035 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
2036 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2037 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
2038 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
2039 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2040 case HWTSTAMP_FILTER_NTP_ALL:
2041 case HWTSTAMP_FILTER_ALL:
2042 ice_set_rx_tstamp(pf, true);
2052 * ice_ptp_set_ts_config - ioctl interface to control the timestamping
2053 * @pf: Board private structure
2056 * Get the user config and store it
2058 int ice_ptp_set_ts_config(struct ice_pf *pf, struct ifreq *ifr)
2060 struct hwtstamp_config config;
2063 if (!test_bit(ICE_FLAG_PTP, pf->flags))
2066 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
2069 err = ice_ptp_set_timestamp_mode(pf, &config);
2073 /* Return the actual configuration set */
2074 config = pf->ptp.tstamp_config;
2076 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
2081 * ice_ptp_rx_hwtstamp - Check for an Rx timestamp
2082 * @rx_ring: Ring to get the VSI info
2083 * @rx_desc: Receive descriptor
2084 * @skb: Particular skb to send timestamp with
2086 * The driver receives a notification in the receive descriptor with timestamp.
2087 * The timestamp is in ns, so we must convert the result first.
2090 ice_ptp_rx_hwtstamp(struct ice_rx_ring *rx_ring,
2091 union ice_32b_rx_flex_desc *rx_desc, struct sk_buff *skb)
2096 /* Populate timesync data into skb */
2097 if (rx_desc->wb.time_stamp_low & ICE_PTP_TS_VALID) {
2098 struct skb_shared_hwtstamps *hwtstamps;
2100 /* Use ice_ptp_extend_32b_ts directly, using the ring-specific
2101 * cached PHC value, rather than accessing the PF. This also
2102 * allows us to simply pass the upper 32bits of nanoseconds
2103 * directly. Calling ice_ptp_extend_40b_ts is unnecessary as
2104 * it would just discard these bits itself.
2106 ts_high = le32_to_cpu(rx_desc->wb.flex_ts.ts_high);
2107 ts_ns = ice_ptp_extend_32b_ts(rx_ring->cached_phctime, ts_high);
2109 hwtstamps = skb_hwtstamps(skb);
2110 memset(hwtstamps, 0, sizeof(*hwtstamps));
2111 hwtstamps->hwtstamp = ns_to_ktime(ts_ns);
2116 * ice_ptp_disable_sma_pins_e810t - Disable E810-T SMA pins
2117 * @pf: pointer to the PF structure
2118 * @info: PTP clock info structure
2120 * Disable the OS access to the SMA pins. Called to clear out the OS
2121 * indications of pin support when we fail to setup the E810-T SMA control
2125 ice_ptp_disable_sma_pins_e810t(struct ice_pf *pf, struct ptp_clock_info *info)
2127 struct device *dev = ice_pf_to_dev(pf);
2129 dev_warn(dev, "Failed to configure E810-T SMA pin control\n");
2131 info->enable = NULL;
2132 info->verify = NULL;
2135 info->n_per_out = 0;
2139 * ice_ptp_setup_sma_pins_e810t - Setup the SMA pins
2140 * @pf: pointer to the PF structure
2141 * @info: PTP clock info structure
2143 * Finish setting up the SMA pins by allocating pin_config, and setting it up
2144 * according to the current status of the SMA. On failure, disable all of the
2145 * extended SMA pin support.
2148 ice_ptp_setup_sma_pins_e810t(struct ice_pf *pf, struct ptp_clock_info *info)
2150 struct device *dev = ice_pf_to_dev(pf);
2153 /* Allocate memory for kernel pins interface */
2154 info->pin_config = devm_kcalloc(dev, info->n_pins,
2155 sizeof(*info->pin_config), GFP_KERNEL);
2156 if (!info->pin_config) {
2157 ice_ptp_disable_sma_pins_e810t(pf, info);
2161 /* Read current SMA status */
2162 err = ice_get_sma_config_e810t(&pf->hw, info->pin_config);
2164 ice_ptp_disable_sma_pins_e810t(pf, info);
2168 * ice_ptp_setup_pins_e810t - Setup PTP pins in sysfs
2169 * @pf: pointer to the PF instance
2170 * @info: PTP clock capabilities
2173 ice_ptp_setup_pins_e810t(struct ice_pf *pf, struct ptp_clock_info *info)
2175 /* Check if SMA controller is in the netlist */
2176 if (ice_is_feature_supported(pf, ICE_F_SMA_CTRL) &&
2177 !ice_is_pca9575_present(&pf->hw))
2178 ice_clear_feature_support(pf, ICE_F_SMA_CTRL);
2180 if (!ice_is_feature_supported(pf, ICE_F_SMA_CTRL)) {
2181 info->n_ext_ts = N_EXT_TS_E810_NO_SMA;
2182 info->n_per_out = N_PER_OUT_E810T_NO_SMA;
2186 info->n_per_out = N_PER_OUT_E810T;
2188 if (ice_is_feature_supported(pf, ICE_F_PTP_EXTTS)) {
2189 info->n_ext_ts = N_EXT_TS_E810;
2190 info->n_pins = NUM_PTP_PINS_E810T;
2191 info->verify = ice_verify_pin_e810t;
2194 /* Complete setup of the SMA pins */
2195 ice_ptp_setup_sma_pins_e810t(pf, info);
2199 * ice_ptp_setup_pins_e810 - Setup PTP pins in sysfs
2200 * @pf: pointer to the PF instance
2201 * @info: PTP clock capabilities
2203 static void ice_ptp_setup_pins_e810(struct ice_pf *pf, struct ptp_clock_info *info)
2205 info->n_per_out = N_PER_OUT_E810;
2207 if (!ice_is_feature_supported(pf, ICE_F_PTP_EXTTS))
2210 info->n_ext_ts = N_EXT_TS_E810;
2214 * ice_ptp_set_funcs_e822 - Set specialized functions for E822 support
2215 * @pf: Board private structure
2216 * @info: PTP info to fill
2218 * Assign functions to the PTP capabiltiies structure for E822 devices.
2219 * Functions which operate across all device families should be set directly
2220 * in ice_ptp_set_caps. Only add functions here which are distinct for E822
2224 ice_ptp_set_funcs_e822(struct ice_pf *pf, struct ptp_clock_info *info)
2226 #ifdef CONFIG_ICE_HWTS
2227 if (boot_cpu_has(X86_FEATURE_ART) &&
2228 boot_cpu_has(X86_FEATURE_TSC_KNOWN_FREQ))
2229 info->getcrosststamp = ice_ptp_getcrosststamp_e822;
2230 #endif /* CONFIG_ICE_HWTS */
2234 * ice_ptp_set_funcs_e810 - Set specialized functions for E810 support
2235 * @pf: Board private structure
2236 * @info: PTP info to fill
2238 * Assign functions to the PTP capabiltiies structure for E810 devices.
2239 * Functions which operate across all device families should be set directly
2240 * in ice_ptp_set_caps. Only add functions here which are distinct for e810
2244 ice_ptp_set_funcs_e810(struct ice_pf *pf, struct ptp_clock_info *info)
2246 info->enable = ice_ptp_gpio_enable_e810;
2248 if (ice_is_e810t(&pf->hw))
2249 ice_ptp_setup_pins_e810t(pf, info);
2251 ice_ptp_setup_pins_e810(pf, info);
2255 * ice_ptp_set_caps - Set PTP capabilities
2256 * @pf: Board private structure
2258 static void ice_ptp_set_caps(struct ice_pf *pf)
2260 struct ptp_clock_info *info = &pf->ptp.info;
2261 struct device *dev = ice_pf_to_dev(pf);
2263 snprintf(info->name, sizeof(info->name) - 1, "%s-%s-clk",
2264 dev_driver_string(dev), dev_name(dev));
2265 info->owner = THIS_MODULE;
2266 info->max_adj = 999999999;
2267 info->adjtime = ice_ptp_adjtime;
2268 info->adjfine = ice_ptp_adjfine;
2269 info->gettimex64 = ice_ptp_gettimex64;
2270 info->settime64 = ice_ptp_settime64;
2272 if (ice_is_e810(&pf->hw))
2273 ice_ptp_set_funcs_e810(pf, info);
2275 ice_ptp_set_funcs_e822(pf, info);
2279 * ice_ptp_create_clock - Create PTP clock device for userspace
2280 * @pf: Board private structure
2282 * This function creates a new PTP clock device. It only creates one if we
2283 * don't already have one. Will return error if it can't create one, but success
2284 * if we already have a device. Should be used by ice_ptp_init to create clock
2285 * initially, and prevent global resets from creating new clock devices.
2287 static long ice_ptp_create_clock(struct ice_pf *pf)
2289 struct ptp_clock_info *info;
2290 struct ptp_clock *clock;
2293 /* No need to create a clock device if we already have one */
2297 ice_ptp_set_caps(pf);
2299 info = &pf->ptp.info;
2300 dev = ice_pf_to_dev(pf);
2302 /* Attempt to register the clock before enabling the hardware. */
2303 clock = ptp_clock_register(info, dev);
2305 return PTR_ERR(clock);
2307 pf->ptp.clock = clock;
2313 * ice_ptp_request_ts - Request an available Tx timestamp index
2314 * @tx: the PTP Tx timestamp tracker to request from
2315 * @skb: the SKB to associate with this timestamp request
2317 s8 ice_ptp_request_ts(struct ice_ptp_tx *tx, struct sk_buff *skb)
2321 /* Check if this tracker is initialized */
2322 if (!tx->init || tx->calibrating)
2325 spin_lock(&tx->lock);
2326 /* Find and set the first available index */
2327 idx = find_first_zero_bit(tx->in_use, tx->len);
2328 if (idx < tx->len) {
2329 /* We got a valid index that no other thread could have set. Store
2330 * a reference to the skb and the start time to allow discarding old
2333 set_bit(idx, tx->in_use);
2334 tx->tstamps[idx].start = jiffies;
2335 tx->tstamps[idx].skb = skb_get(skb);
2336 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2337 ice_trace(tx_tstamp_request, skb, idx);
2340 spin_unlock(&tx->lock);
2342 /* return the appropriate PHY timestamp register index, -1 if no
2343 * indexes were available.
2348 return idx + tx->quad_offset;
2352 * ice_ptp_process_ts - Spawn kthread work to handle timestamps
2353 * @pf: Board private structure
2355 * Queue work required to process the PTP Tx timestamps outside of interrupt
2358 void ice_ptp_process_ts(struct ice_pf *pf)
2360 if (pf->ptp.port.tx.init)
2361 kthread_queue_work(pf->ptp.kworker, &pf->ptp.port.tx.work);
2364 static void ice_ptp_periodic_work(struct kthread_work *work)
2366 struct ice_ptp *ptp = container_of(work, struct ice_ptp, work.work);
2367 struct ice_pf *pf = container_of(ptp, struct ice_pf, ptp);
2370 if (!test_bit(ICE_FLAG_PTP, pf->flags))
2373 err = ice_ptp_update_cached_phctime(pf);
2375 ice_ptp_tx_tstamp_cleanup(pf, &pf->ptp.port.tx);
2377 /* Run twice a second or reschedule if phc update failed */
2378 kthread_queue_delayed_work(ptp->kworker, &ptp->work,
2379 msecs_to_jiffies(err ? 10 : 500));
2383 * ice_ptp_reset - Initialize PTP hardware clock support after reset
2384 * @pf: Board private structure
2386 void ice_ptp_reset(struct ice_pf *pf)
2388 struct ice_ptp *ptp = &pf->ptp;
2389 struct ice_hw *hw = &pf->hw;
2390 struct timespec64 ts;
2394 if (test_bit(ICE_PFR_REQ, pf->state))
2397 if (!hw->func_caps.ts_func_info.src_tmr_owned)
2400 err = ice_ptp_init_phc(hw);
2404 /* Acquire the global hardware lock */
2405 if (!ice_ptp_lock(hw)) {
2410 /* Write the increment time value to PHY and LAN */
2411 err = ice_ptp_write_incval(hw, ice_base_incval(pf));
2417 /* Write the initial Time value to PHY and LAN using the cached PHC
2418 * time before the reset and time difference between stopping and
2419 * starting the clock.
2421 if (ptp->cached_phc_time) {
2422 time_diff = ktime_get_real_ns() - ptp->reset_time;
2423 ts = ns_to_timespec64(ptp->cached_phc_time + time_diff);
2425 ts = ktime_to_timespec64(ktime_get_real());
2427 err = ice_ptp_write_init(pf, &ts);
2433 /* Release the global hardware lock */
2436 if (!ice_is_e810(hw)) {
2437 /* Enable quad interrupts */
2438 err = ice_ptp_tx_ena_intr(pf, true, itr);
2444 /* Restart the PHY timestamping block */
2445 ice_ptp_reset_phy_timestamping(pf);
2448 /* Init Tx structures */
2449 if (ice_is_e810(&pf->hw)) {
2450 err = ice_ptp_init_tx_e810(pf, &ptp->port.tx);
2452 kthread_init_delayed_work(&ptp->port.ov_work,
2453 ice_ptp_wait_for_offset_valid);
2454 err = ice_ptp_init_tx_e822(pf, &ptp->port.tx,
2455 ptp->port.port_num);
2460 set_bit(ICE_FLAG_PTP, pf->flags);
2462 /* Start periodic work going */
2463 kthread_queue_delayed_work(ptp->kworker, &ptp->work, 0);
2465 dev_info(ice_pf_to_dev(pf), "PTP reset successful\n");
2469 dev_err(ice_pf_to_dev(pf), "PTP reset failed %d\n", err);
2473 * ice_ptp_prepare_for_reset - Prepare PTP for reset
2474 * @pf: Board private structure
2476 void ice_ptp_prepare_for_reset(struct ice_pf *pf)
2478 struct ice_ptp *ptp = &pf->ptp;
2481 clear_bit(ICE_FLAG_PTP, pf->flags);
2483 /* Disable timestamping for both Tx and Rx */
2484 ice_ptp_cfg_timestamp(pf, false);
2486 kthread_cancel_delayed_work_sync(&ptp->work);
2487 kthread_cancel_work_sync(&ptp->extts_work);
2489 if (test_bit(ICE_PFR_REQ, pf->state))
2492 ice_ptp_release_tx_tracker(pf, &pf->ptp.port.tx);
2494 /* Disable periodic outputs */
2495 ice_ptp_disable_all_clkout(pf);
2497 src_tmr = ice_get_ptp_src_clock_index(&pf->hw);
2499 /* Disable source clock */
2500 wr32(&pf->hw, GLTSYN_ENA(src_tmr), (u32)~GLTSYN_ENA_TSYN_ENA_M);
2502 /* Acquire PHC and system timer to restore after reset */
2503 ptp->reset_time = ktime_get_real_ns();
2507 * ice_ptp_init_owner - Initialize PTP_1588_CLOCK device
2508 * @pf: Board private structure
2510 * Setup and initialize a PTP clock device that represents the device hardware
2511 * clock. Save the clock index for other functions connected to the same
2512 * hardware resource.
2514 static int ice_ptp_init_owner(struct ice_pf *pf)
2516 struct ice_hw *hw = &pf->hw;
2517 struct timespec64 ts;
2520 err = ice_ptp_init_phc(hw);
2522 dev_err(ice_pf_to_dev(pf), "Failed to initialize PHC, err %d\n",
2527 /* Acquire the global hardware lock */
2528 if (!ice_ptp_lock(hw)) {
2533 /* Write the increment time value to PHY and LAN */
2534 err = ice_ptp_write_incval(hw, ice_base_incval(pf));
2540 ts = ktime_to_timespec64(ktime_get_real());
2541 /* Write the initial Time value to PHY and LAN */
2542 err = ice_ptp_write_init(pf, &ts);
2548 /* Release the global hardware lock */
2551 if (!ice_is_e810(hw)) {
2552 /* Enable quad interrupts */
2553 err = ice_ptp_tx_ena_intr(pf, true, itr);
2558 /* Ensure we have a clock device */
2559 err = ice_ptp_create_clock(pf);
2563 /* Store the PTP clock index for other PFs */
2564 ice_set_ptp_clock_index(pf);
2569 pf->ptp.clock = NULL;
2575 * ice_ptp_init_work - Initialize PTP work threads
2576 * @pf: Board private structure
2577 * @ptp: PF PTP structure
2579 static int ice_ptp_init_work(struct ice_pf *pf, struct ice_ptp *ptp)
2581 struct kthread_worker *kworker;
2583 /* Initialize work functions */
2584 kthread_init_delayed_work(&ptp->work, ice_ptp_periodic_work);
2585 kthread_init_work(&ptp->extts_work, ice_ptp_extts_work);
2587 /* Allocate a kworker for handling work required for the ports
2588 * connected to the PTP hardware clock.
2590 kworker = kthread_create_worker(0, "ice-ptp-%s",
2591 dev_name(ice_pf_to_dev(pf)));
2592 if (IS_ERR(kworker))
2593 return PTR_ERR(kworker);
2595 ptp->kworker = kworker;
2597 /* Start periodic work going */
2598 kthread_queue_delayed_work(ptp->kworker, &ptp->work, 0);
2604 * ice_ptp_init_port - Initialize PTP port structure
2605 * @pf: Board private structure
2606 * @ptp_port: PTP port structure
2608 static int ice_ptp_init_port(struct ice_pf *pf, struct ice_ptp_port *ptp_port)
2610 mutex_init(&ptp_port->ps_lock);
2612 if (ice_is_e810(&pf->hw))
2613 return ice_ptp_init_tx_e810(pf, &ptp_port->tx);
2615 kthread_init_delayed_work(&ptp_port->ov_work,
2616 ice_ptp_wait_for_offset_valid);
2617 return ice_ptp_init_tx_e822(pf, &ptp_port->tx, ptp_port->port_num);
2621 * ice_ptp_init - Initialize PTP hardware clock support
2622 * @pf: Board private structure
2624 * Set up the device for interacting with the PTP hardware clock for all
2625 * functions, both the function that owns the clock hardware, and the
2626 * functions connected to the clock hardware.
2628 * The clock owner will allocate and register a ptp_clock with the
2629 * PTP_1588_CLOCK infrastructure. All functions allocate a kthread and work
2630 * items used for asynchronous work such as Tx timestamps and periodic work.
2632 void ice_ptp_init(struct ice_pf *pf)
2634 struct ice_ptp *ptp = &pf->ptp;
2635 struct ice_hw *hw = &pf->hw;
2638 /* If this function owns the clock hardware, it must allocate and
2639 * configure the PTP clock device to represent it.
2641 if (hw->func_caps.ts_func_info.src_tmr_owned) {
2642 err = ice_ptp_init_owner(pf);
2647 ptp->port.port_num = hw->pf_id;
2648 err = ice_ptp_init_port(pf, &ptp->port);
2652 /* Start the PHY timestamping block */
2653 ice_ptp_reset_phy_timestamping(pf);
2655 set_bit(ICE_FLAG_PTP, pf->flags);
2656 err = ice_ptp_init_work(pf, ptp);
2660 dev_info(ice_pf_to_dev(pf), "PTP init successful\n");
2664 /* If we registered a PTP clock, release it */
2665 if (pf->ptp.clock) {
2666 ptp_clock_unregister(ptp->clock);
2667 pf->ptp.clock = NULL;
2669 clear_bit(ICE_FLAG_PTP, pf->flags);
2670 dev_err(ice_pf_to_dev(pf), "PTP failed %d\n", err);
2674 * ice_ptp_release - Disable the driver/HW support and unregister the clock
2675 * @pf: Board private structure
2677 * This function handles the cleanup work required from the initialization by
2678 * clearing out the important information and unregistering the clock
2680 void ice_ptp_release(struct ice_pf *pf)
2682 if (!test_bit(ICE_FLAG_PTP, pf->flags))
2685 /* Disable timestamping for both Tx and Rx */
2686 ice_ptp_cfg_timestamp(pf, false);
2688 ice_ptp_release_tx_tracker(pf, &pf->ptp.port.tx);
2690 clear_bit(ICE_FLAG_PTP, pf->flags);
2692 kthread_cancel_delayed_work_sync(&pf->ptp.work);
2694 ice_ptp_port_phy_stop(&pf->ptp.port);
2695 mutex_destroy(&pf->ptp.port.ps_lock);
2696 if (pf->ptp.kworker) {
2697 kthread_destroy_worker(pf->ptp.kworker);
2698 pf->ptp.kworker = NULL;
2704 /* Disable periodic outputs */
2705 ice_ptp_disable_all_clkout(pf);
2707 ice_clear_ptp_clock_index(pf);
2708 ptp_clock_unregister(pf->ptp.clock);
2709 pf->ptp.clock = NULL;
2711 dev_info(ice_pf_to_dev(pf), "Removed PTP clock\n");