1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018, Intel Corporation. */
4 #include <linux/vmalloc.h>
6 #include "ice_common.h"
10 * @hw: pointer to the HW struct
11 * @module_typeid: module pointer location in words from the NVM beginning
12 * @offset: byte offset from the module beginning
13 * @length: length of the section to be read (in bytes from the offset)
14 * @data: command buffer (size [bytes] = length)
15 * @last_command: tells if this is the last command in a series
16 * @read_shadow_ram: tell if this is a shadow RAM read
17 * @cd: pointer to command details structure or NULL
19 * Read the NVM using the admin queue commands (0x0701)
22 ice_aq_read_nvm(struct ice_hw *hw, u16 module_typeid, u32 offset, u16 length,
23 void *data, bool last_command, bool read_shadow_ram,
26 struct ice_aq_desc desc;
27 struct ice_aqc_nvm *cmd;
29 cmd = &desc.params.nvm;
31 if (offset > ICE_AQC_NVM_MAX_OFFSET)
34 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_read);
36 if (!read_shadow_ram && module_typeid == ICE_AQC_NVM_START_POINT)
37 cmd->cmd_flags |= ICE_AQC_NVM_FLASH_ONLY;
39 /* If this is the last command in a series, set the proper flag. */
41 cmd->cmd_flags |= ICE_AQC_NVM_LAST_CMD;
42 cmd->module_typeid = cpu_to_le16(module_typeid);
43 cmd->offset_low = cpu_to_le16(offset & 0xFFFF);
44 cmd->offset_high = (offset >> 16) & 0xFF;
45 cmd->length = cpu_to_le16(length);
47 return ice_aq_send_cmd(hw, &desc, data, length, cd);
51 * ice_read_flat_nvm - Read portion of NVM by flat offset
52 * @hw: pointer to the HW struct
53 * @offset: offset from beginning of NVM
54 * @length: (in) number of bytes to read; (out) number of bytes actually read
55 * @data: buffer to return data in (sized to fit the specified length)
56 * @read_shadow_ram: if true, read from shadow RAM instead of NVM
58 * Reads a portion of the NVM, as a flat memory space. This function correctly
59 * breaks read requests across Shadow RAM sectors and ensures that no single
60 * read request exceeds the maximum 4KB read for a single AdminQ command.
62 * Returns a status code on failure. Note that the data pointer may be
63 * partially updated if some reads succeed before a failure.
66 ice_read_flat_nvm(struct ice_hw *hw, u32 offset, u32 *length, u8 *data,
76 /* Verify the length of the read if this is for the Shadow RAM */
77 if (read_shadow_ram && ((offset + inlen) > (hw->flash.sr_words * 2u))) {
78 ice_debug(hw, ICE_DBG_NVM, "NVM error: requested offset is beyond Shadow RAM limit\n");
83 u32 read_size, sector_offset;
85 /* ice_aq_read_nvm cannot read more than 4KB at a time.
86 * Additionally, a read from the Shadow RAM may not cross over
87 * a sector boundary. Conveniently, the sector size is also
90 sector_offset = offset % ICE_AQ_MAX_BUF_LEN;
91 read_size = min_t(u32, ICE_AQ_MAX_BUF_LEN - sector_offset,
94 last_cmd = !(bytes_read + read_size < inlen);
96 status = ice_aq_read_nvm(hw, ICE_AQC_NVM_START_POINT,
98 data + bytes_read, last_cmd,
99 read_shadow_ram, NULL);
103 bytes_read += read_size;
107 *length = bytes_read;
113 * @hw: pointer to the HW struct
114 * @module_typeid: module pointer location in words from the NVM beginning
115 * @offset: byte offset from the module beginning
116 * @length: length of the section to be written (in bytes from the offset)
117 * @data: command buffer (size [bytes] = length)
118 * @last_command: tells if this is the last command in a series
119 * @command_flags: command parameters
120 * @cd: pointer to command details structure or NULL
122 * Update the NVM using the admin queue commands (0x0703)
125 ice_aq_update_nvm(struct ice_hw *hw, u16 module_typeid, u32 offset,
126 u16 length, void *data, bool last_command, u8 command_flags,
127 struct ice_sq_cd *cd)
129 struct ice_aq_desc desc;
130 struct ice_aqc_nvm *cmd;
132 cmd = &desc.params.nvm;
134 /* In offset the highest byte must be zeroed. */
135 if (offset & 0xFF000000)
138 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_write);
140 cmd->cmd_flags |= command_flags;
142 /* If this is the last command in a series, set the proper flag. */
144 cmd->cmd_flags |= ICE_AQC_NVM_LAST_CMD;
145 cmd->module_typeid = cpu_to_le16(module_typeid);
146 cmd->offset_low = cpu_to_le16(offset & 0xFFFF);
147 cmd->offset_high = (offset >> 16) & 0xFF;
148 cmd->length = cpu_to_le16(length);
150 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
152 return ice_aq_send_cmd(hw, &desc, data, length, cd);
157 * @hw: pointer to the HW struct
158 * @module_typeid: module pointer location in words from the NVM beginning
159 * @cd: pointer to command details structure or NULL
161 * Erase the NVM sector using the admin queue commands (0x0702)
163 int ice_aq_erase_nvm(struct ice_hw *hw, u16 module_typeid, struct ice_sq_cd *cd)
165 struct ice_aq_desc desc;
166 struct ice_aqc_nvm *cmd;
168 cmd = &desc.params.nvm;
170 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_erase);
172 cmd->module_typeid = cpu_to_le16(module_typeid);
173 cmd->length = cpu_to_le16(ICE_AQC_NVM_ERASE_LEN);
175 cmd->offset_high = 0;
177 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
181 * ice_read_sr_word_aq - Reads Shadow RAM via AQ
182 * @hw: pointer to the HW structure
183 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
184 * @data: word read from the Shadow RAM
186 * Reads one 16 bit word from the Shadow RAM using ice_read_flat_nvm.
188 static int ice_read_sr_word_aq(struct ice_hw *hw, u16 offset, u16 *data)
190 u32 bytes = sizeof(u16);
194 /* Note that ice_read_flat_nvm takes into account the 4Kb AdminQ and
195 * Shadow RAM sector restrictions necessary when reading from the NVM.
197 status = ice_read_flat_nvm(hw, offset * sizeof(u16), &bytes,
198 (__force u8 *)&data_local, true);
202 *data = le16_to_cpu(data_local);
207 * ice_acquire_nvm - Generic request for acquiring the NVM ownership
208 * @hw: pointer to the HW structure
209 * @access: NVM access type (read or write)
211 * This function will request NVM ownership.
213 int ice_acquire_nvm(struct ice_hw *hw, enum ice_aq_res_access_type access)
215 if (hw->flash.blank_nvm_mode)
218 return ice_acquire_res(hw, ICE_NVM_RES_ID, access, ICE_NVM_TIMEOUT);
222 * ice_release_nvm - Generic request for releasing the NVM ownership
223 * @hw: pointer to the HW structure
225 * This function will release NVM ownership.
227 void ice_release_nvm(struct ice_hw *hw)
229 if (hw->flash.blank_nvm_mode)
232 ice_release_res(hw, ICE_NVM_RES_ID);
236 * ice_get_flash_bank_offset - Get offset into requested flash bank
237 * @hw: pointer to the HW structure
238 * @bank: whether to read from the active or inactive flash bank
239 * @module: the module to read from
241 * Based on the module, lookup the module offset from the beginning of the
244 * Returns the flash offset. Note that a value of zero is invalid and must be
245 * treated as an error.
247 static u32 ice_get_flash_bank_offset(struct ice_hw *hw, enum ice_bank_select bank, u16 module)
249 struct ice_bank_info *banks = &hw->flash.banks;
250 enum ice_flash_bank active_bank;
251 bool second_bank_active;
255 case ICE_SR_1ST_NVM_BANK_PTR:
256 offset = banks->nvm_ptr;
257 size = banks->nvm_size;
258 active_bank = banks->nvm_bank;
260 case ICE_SR_1ST_OROM_BANK_PTR:
261 offset = banks->orom_ptr;
262 size = banks->orom_size;
263 active_bank = banks->orom_bank;
265 case ICE_SR_NETLIST_BANK_PTR:
266 offset = banks->netlist_ptr;
267 size = banks->netlist_size;
268 active_bank = banks->netlist_bank;
271 ice_debug(hw, ICE_DBG_NVM, "Unexpected value for flash module: 0x%04x\n", module);
275 switch (active_bank) {
276 case ICE_1ST_FLASH_BANK:
277 second_bank_active = false;
279 case ICE_2ND_FLASH_BANK:
280 second_bank_active = true;
283 ice_debug(hw, ICE_DBG_NVM, "Unexpected value for active flash bank: %u\n",
288 /* The second flash bank is stored immediately following the first
289 * bank. Based on whether the 1st or 2nd bank is active, and whether
290 * we want the active or inactive bank, calculate the desired offset.
293 case ICE_ACTIVE_FLASH_BANK:
294 return offset + (second_bank_active ? size : 0);
295 case ICE_INACTIVE_FLASH_BANK:
296 return offset + (second_bank_active ? 0 : size);
299 ice_debug(hw, ICE_DBG_NVM, "Unexpected value for flash bank selection: %u\n", bank);
304 * ice_read_flash_module - Read a word from one of the main NVM modules
305 * @hw: pointer to the HW structure
306 * @bank: which bank of the module to read
307 * @module: the module to read
308 * @offset: the offset into the module in bytes
309 * @data: storage for the word read from the flash
310 * @length: bytes of data to read
312 * Read data from the specified flash module. The bank parameter indicates
313 * whether or not to read from the active bank or the inactive bank of that
316 * The word will be read using flat NVM access, and relies on the
317 * hw->flash.banks data being setup by ice_determine_active_flash_banks()
318 * during initialization.
321 ice_read_flash_module(struct ice_hw *hw, enum ice_bank_select bank, u16 module,
322 u32 offset, u8 *data, u32 length)
327 start = ice_get_flash_bank_offset(hw, bank, module);
329 ice_debug(hw, ICE_DBG_NVM, "Unable to calculate flash bank offset for module 0x%04x\n",
334 status = ice_acquire_nvm(hw, ICE_RES_READ);
338 status = ice_read_flat_nvm(hw, start + offset, &length, data, false);
346 * ice_read_nvm_module - Read from the active main NVM module
347 * @hw: pointer to the HW structure
348 * @bank: whether to read from active or inactive NVM module
349 * @offset: offset into the NVM module to read, in words
350 * @data: storage for returned word value
352 * Read the specified word from the active NVM module. This includes the CSS
353 * header at the start of the NVM module.
356 ice_read_nvm_module(struct ice_hw *hw, enum ice_bank_select bank, u32 offset, u16 *data)
361 status = ice_read_flash_module(hw, bank, ICE_SR_1ST_NVM_BANK_PTR, offset * sizeof(u16),
362 (__force u8 *)&data_local, sizeof(u16));
364 *data = le16_to_cpu(data_local);
370 * ice_read_nvm_sr_copy - Read a word from the Shadow RAM copy in the NVM bank
371 * @hw: pointer to the HW structure
372 * @bank: whether to read from the active or inactive NVM module
373 * @offset: offset into the Shadow RAM copy to read, in words
374 * @data: storage for returned word value
376 * Read the specified word from the copy of the Shadow RAM found in the
377 * specified NVM module.
380 ice_read_nvm_sr_copy(struct ice_hw *hw, enum ice_bank_select bank, u32 offset, u16 *data)
382 return ice_read_nvm_module(hw, bank, ICE_NVM_SR_COPY_WORD_OFFSET + offset, data);
386 * ice_read_netlist_module - Read data from the netlist module area
387 * @hw: pointer to the HW structure
388 * @bank: whether to read from the active or inactive module
389 * @offset: offset into the netlist to read from
390 * @data: storage for returned word value
392 * Read a word from the specified netlist bank.
395 ice_read_netlist_module(struct ice_hw *hw, enum ice_bank_select bank, u32 offset, u16 *data)
400 status = ice_read_flash_module(hw, bank, ICE_SR_NETLIST_BANK_PTR, offset * sizeof(u16),
401 (__force u8 *)&data_local, sizeof(u16));
403 *data = le16_to_cpu(data_local);
409 * ice_read_sr_word - Reads Shadow RAM word and acquire NVM if necessary
410 * @hw: pointer to the HW structure
411 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
412 * @data: word read from the Shadow RAM
414 * Reads one 16 bit word from the Shadow RAM using the ice_read_sr_word_aq.
416 int ice_read_sr_word(struct ice_hw *hw, u16 offset, u16 *data)
420 status = ice_acquire_nvm(hw, ICE_RES_READ);
422 status = ice_read_sr_word_aq(hw, offset, data);
430 * ice_get_pfa_module_tlv - Reads sub module TLV from NVM PFA
431 * @hw: pointer to hardware structure
432 * @module_tlv: pointer to module TLV to return
433 * @module_tlv_len: pointer to module TLV length to return
434 * @module_type: module type requested
436 * Finds the requested sub module TLV type from the Preserved Field
437 * Area (PFA) and returns the TLV pointer and length. The caller can
438 * use these to read the variable length TLV value.
441 ice_get_pfa_module_tlv(struct ice_hw *hw, u16 *module_tlv, u16 *module_tlv_len,
444 u16 pfa_len, pfa_ptr;
448 status = ice_read_sr_word(hw, ICE_SR_PFA_PTR, &pfa_ptr);
450 ice_debug(hw, ICE_DBG_INIT, "Preserved Field Array pointer.\n");
453 status = ice_read_sr_word(hw, pfa_ptr, &pfa_len);
455 ice_debug(hw, ICE_DBG_INIT, "Failed to read PFA length.\n");
458 /* Starting with first TLV after PFA length, iterate through the list
459 * of TLVs to find the requested one.
461 next_tlv = pfa_ptr + 1;
462 while (next_tlv < pfa_ptr + pfa_len) {
463 u16 tlv_sub_module_type;
467 status = ice_read_sr_word(hw, next_tlv, &tlv_sub_module_type);
469 ice_debug(hw, ICE_DBG_INIT, "Failed to read TLV type.\n");
472 /* Read TLV length */
473 status = ice_read_sr_word(hw, next_tlv + 1, &tlv_len);
475 ice_debug(hw, ICE_DBG_INIT, "Failed to read TLV length.\n");
478 if (tlv_sub_module_type == module_type) {
480 *module_tlv = next_tlv;
481 *module_tlv_len = tlv_len;
486 /* Check next TLV, i.e. current TLV pointer + length + 2 words
487 * (for current TLV's type and length)
489 next_tlv = next_tlv + tlv_len + 2;
491 /* Module does not exist */
496 * ice_read_pba_string - Reads part number string from NVM
497 * @hw: pointer to hardware structure
498 * @pba_num: stores the part number string from the NVM
499 * @pba_num_size: part number string buffer length
501 * Reads the part number string from the NVM.
503 int ice_read_pba_string(struct ice_hw *hw, u8 *pba_num, u32 pba_num_size)
505 u16 pba_tlv, pba_tlv_len;
506 u16 pba_word, pba_size;
510 status = ice_get_pfa_module_tlv(hw, &pba_tlv, &pba_tlv_len,
511 ICE_SR_PBA_BLOCK_PTR);
513 ice_debug(hw, ICE_DBG_INIT, "Failed to read PBA Block TLV.\n");
517 /* pba_size is the next word */
518 status = ice_read_sr_word(hw, (pba_tlv + 2), &pba_size);
520 ice_debug(hw, ICE_DBG_INIT, "Failed to read PBA Section size.\n");
524 if (pba_tlv_len < pba_size) {
525 ice_debug(hw, ICE_DBG_INIT, "Invalid PBA Block TLV size.\n");
529 /* Subtract one to get PBA word count (PBA Size word is included in
533 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
534 ice_debug(hw, ICE_DBG_INIT, "Buffer too small for PBA data.\n");
538 for (i = 0; i < pba_size; i++) {
539 status = ice_read_sr_word(hw, (pba_tlv + 2 + 1) + i, &pba_word);
541 ice_debug(hw, ICE_DBG_INIT, "Failed to read PBA Block word %d.\n", i);
545 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
546 pba_num[(i * 2) + 1] = pba_word & 0xFF;
548 pba_num[(pba_size * 2)] = '\0';
554 * ice_get_nvm_ver_info - Read NVM version information
555 * @hw: pointer to the HW struct
556 * @bank: whether to read from the active or inactive flash bank
557 * @nvm: pointer to NVM info structure
559 * Read the NVM EETRACK ID and map version of the main NVM image bank, filling
560 * in the NVM info structure.
563 ice_get_nvm_ver_info(struct ice_hw *hw, enum ice_bank_select bank, struct ice_nvm_info *nvm)
565 u16 eetrack_lo, eetrack_hi, ver;
568 status = ice_read_nvm_sr_copy(hw, bank, ICE_SR_NVM_DEV_STARTER_VER, &ver);
570 ice_debug(hw, ICE_DBG_NVM, "Failed to read DEV starter version.\n");
574 nvm->major = (ver & ICE_NVM_VER_HI_MASK) >> ICE_NVM_VER_HI_SHIFT;
575 nvm->minor = (ver & ICE_NVM_VER_LO_MASK) >> ICE_NVM_VER_LO_SHIFT;
577 status = ice_read_nvm_sr_copy(hw, bank, ICE_SR_NVM_EETRACK_LO, &eetrack_lo);
579 ice_debug(hw, ICE_DBG_NVM, "Failed to read EETRACK lo.\n");
582 status = ice_read_nvm_sr_copy(hw, bank, ICE_SR_NVM_EETRACK_HI, &eetrack_hi);
584 ice_debug(hw, ICE_DBG_NVM, "Failed to read EETRACK hi.\n");
588 nvm->eetrack = (eetrack_hi << 16) | eetrack_lo;
594 * ice_get_inactive_nvm_ver - Read Option ROM version from the inactive bank
595 * @hw: pointer to the HW structure
596 * @nvm: storage for Option ROM version information
598 * Reads the NVM EETRACK ID, Map version, and security revision of the
599 * inactive NVM bank. Used to access version data for a pending update that
600 * has not yet been activated.
602 int ice_get_inactive_nvm_ver(struct ice_hw *hw, struct ice_nvm_info *nvm)
604 return ice_get_nvm_ver_info(hw, ICE_INACTIVE_FLASH_BANK, nvm);
608 * ice_get_orom_civd_data - Get the combo version information from Option ROM
609 * @hw: pointer to the HW struct
610 * @bank: whether to read from the active or inactive flash module
611 * @civd: storage for the Option ROM CIVD data.
613 * Searches through the Option ROM flash contents to locate the CIVD data for
617 ice_get_orom_civd_data(struct ice_hw *hw, enum ice_bank_select bank,
618 struct ice_orom_civd_info *civd)
624 /* The CIVD section is located in the Option ROM aligned to 512 bytes.
625 * The first 4 bytes must contain the ASCII characters "$CIV".
626 * A simple modulo 256 sum of all of the bytes of the structure must
629 * The exact location is unknown and varies between images but is
630 * usually somewhere in the middle of the bank. We need to scan the
631 * Option ROM bank to locate it.
633 * It's significantly faster to read the entire Option ROM up front
634 * using the maximum page size, than to read each possible location
635 * with a separate firmware command.
637 orom_data = vzalloc(hw->flash.banks.orom_size);
641 status = ice_read_flash_module(hw, bank, ICE_SR_1ST_OROM_BANK_PTR, 0,
642 orom_data, hw->flash.banks.orom_size);
645 ice_debug(hw, ICE_DBG_NVM, "Unable to read Option ROM data\n");
649 /* Scan the memory buffer to locate the CIVD data section */
650 for (offset = 0; (offset + 512) <= hw->flash.banks.orom_size; offset += 512) {
651 struct ice_orom_civd_info *tmp;
654 tmp = (struct ice_orom_civd_info *)&orom_data[offset];
656 /* Skip forward until we find a matching signature */
657 if (memcmp("$CIV", tmp->signature, sizeof(tmp->signature)) != 0)
660 ice_debug(hw, ICE_DBG_NVM, "Found CIVD section at offset %u\n",
663 /* Verify that the simple checksum is zero */
664 for (i = 0; i < sizeof(*tmp); i++)
665 /* cppcheck-suppress objectIndex */
666 sum += ((u8 *)tmp)[i];
669 ice_debug(hw, ICE_DBG_NVM, "Found CIVD data with invalid checksum of %u\n",
671 goto err_invalid_checksum;
679 ice_debug(hw, ICE_DBG_NVM, "Unable to locate CIVD data within the Option ROM\n");
681 err_invalid_checksum:
687 * ice_get_orom_ver_info - Read Option ROM version information
688 * @hw: pointer to the HW struct
689 * @bank: whether to read from the active or inactive flash module
690 * @orom: pointer to Option ROM info structure
692 * Read Option ROM version and security revision from the Option ROM flash
696 ice_get_orom_ver_info(struct ice_hw *hw, enum ice_bank_select bank, struct ice_orom_info *orom)
698 struct ice_orom_civd_info civd;
702 status = ice_get_orom_civd_data(hw, bank, &civd);
704 ice_debug(hw, ICE_DBG_NVM, "Failed to locate valid Option ROM CIVD data\n");
708 combo_ver = le32_to_cpu(civd.combo_ver);
710 orom->major = (u8)((combo_ver & ICE_OROM_VER_MASK) >> ICE_OROM_VER_SHIFT);
711 orom->patch = (u8)(combo_ver & ICE_OROM_VER_PATCH_MASK);
712 orom->build = (u16)((combo_ver & ICE_OROM_VER_BUILD_MASK) >> ICE_OROM_VER_BUILD_SHIFT);
718 * ice_get_inactive_orom_ver - Read Option ROM version from the inactive bank
719 * @hw: pointer to the HW structure
720 * @orom: storage for Option ROM version information
722 * Reads the Option ROM version and security revision data for the inactive
723 * section of flash. Used to access version data for a pending update that has
724 * not yet been activated.
726 int ice_get_inactive_orom_ver(struct ice_hw *hw, struct ice_orom_info *orom)
728 return ice_get_orom_ver_info(hw, ICE_INACTIVE_FLASH_BANK, orom);
732 * ice_get_netlist_info
733 * @hw: pointer to the HW struct
734 * @bank: whether to read from the active or inactive flash bank
735 * @netlist: pointer to netlist version info structure
737 * Get the netlist version information from the requested bank. Reads the Link
738 * Topology section to find the Netlist ID block and extract the relevant
739 * information into the netlist version structure.
742 ice_get_netlist_info(struct ice_hw *hw, enum ice_bank_select bank,
743 struct ice_netlist_info *netlist)
745 u16 module_id, length, node_count, i;
749 status = ice_read_netlist_module(hw, bank, ICE_NETLIST_TYPE_OFFSET, &module_id);
753 if (module_id != ICE_NETLIST_LINK_TOPO_MOD_ID) {
754 ice_debug(hw, ICE_DBG_NVM, "Expected netlist module_id ID of 0x%04x, but got 0x%04x\n",
755 ICE_NETLIST_LINK_TOPO_MOD_ID, module_id);
759 status = ice_read_netlist_module(hw, bank, ICE_LINK_TOPO_MODULE_LEN, &length);
763 /* sanity check that we have at least enough words to store the netlist ID block */
764 if (length < ICE_NETLIST_ID_BLK_SIZE) {
765 ice_debug(hw, ICE_DBG_NVM, "Netlist Link Topology module too small. Expected at least %u words, but got %u words.\n",
766 ICE_NETLIST_ID_BLK_SIZE, length);
770 status = ice_read_netlist_module(hw, bank, ICE_LINK_TOPO_NODE_COUNT, &node_count);
773 node_count &= ICE_LINK_TOPO_NODE_COUNT_M;
775 id_blk = kcalloc(ICE_NETLIST_ID_BLK_SIZE, sizeof(*id_blk), GFP_KERNEL);
779 /* Read out the entire Netlist ID Block at once. */
780 status = ice_read_flash_module(hw, bank, ICE_SR_NETLIST_BANK_PTR,
781 ICE_NETLIST_ID_BLK_OFFSET(node_count) * sizeof(u16),
782 (u8 *)id_blk, ICE_NETLIST_ID_BLK_SIZE * sizeof(u16));
786 for (i = 0; i < ICE_NETLIST_ID_BLK_SIZE; i++)
787 id_blk[i] = le16_to_cpu(((__force __le16 *)id_blk)[i]);
789 netlist->major = id_blk[ICE_NETLIST_ID_BLK_MAJOR_VER_HIGH] << 16 |
790 id_blk[ICE_NETLIST_ID_BLK_MAJOR_VER_LOW];
791 netlist->minor = id_blk[ICE_NETLIST_ID_BLK_MINOR_VER_HIGH] << 16 |
792 id_blk[ICE_NETLIST_ID_BLK_MINOR_VER_LOW];
793 netlist->type = id_blk[ICE_NETLIST_ID_BLK_TYPE_HIGH] << 16 |
794 id_blk[ICE_NETLIST_ID_BLK_TYPE_LOW];
795 netlist->rev = id_blk[ICE_NETLIST_ID_BLK_REV_HIGH] << 16 |
796 id_blk[ICE_NETLIST_ID_BLK_REV_LOW];
797 netlist->cust_ver = id_blk[ICE_NETLIST_ID_BLK_CUST_VER];
798 /* Read the left most 4 bytes of SHA */
799 netlist->hash = id_blk[ICE_NETLIST_ID_BLK_SHA_HASH_WORD(15)] << 16 |
800 id_blk[ICE_NETLIST_ID_BLK_SHA_HASH_WORD(14)];
809 * ice_get_inactive_netlist_ver
810 * @hw: pointer to the HW struct
811 * @netlist: pointer to netlist version info structure
813 * Read the netlist version data from the inactive netlist bank. Used to
814 * extract version data of a pending flash update in order to display the
817 int ice_get_inactive_netlist_ver(struct ice_hw *hw, struct ice_netlist_info *netlist)
819 return ice_get_netlist_info(hw, ICE_INACTIVE_FLASH_BANK, netlist);
823 * ice_discover_flash_size - Discover the available flash size.
824 * @hw: pointer to the HW struct
826 * The device flash could be up to 16MB in size. However, it is possible that
827 * the actual size is smaller. Use bisection to determine the accessible size
830 static int ice_discover_flash_size(struct ice_hw *hw)
832 u32 min_size = 0, max_size = ICE_AQC_NVM_MAX_OFFSET + 1;
835 status = ice_acquire_nvm(hw, ICE_RES_READ);
839 while ((max_size - min_size) > 1) {
840 u32 offset = (max_size + min_size) / 2;
844 status = ice_read_flat_nvm(hw, offset, &len, &data, false);
845 if (status == -EIO &&
846 hw->adminq.sq_last_status == ICE_AQ_RC_EINVAL) {
847 ice_debug(hw, ICE_DBG_NVM, "%s: New upper bound of %u bytes\n",
851 } else if (!status) {
852 ice_debug(hw, ICE_DBG_NVM, "%s: New lower bound of %u bytes\n",
856 /* an unexpected error occurred */
857 goto err_read_flat_nvm;
861 ice_debug(hw, ICE_DBG_NVM, "Predicted flash size is %u bytes\n", max_size);
863 hw->flash.flash_size = max_size;
872 * ice_read_sr_pointer - Read the value of a Shadow RAM pointer word
873 * @hw: pointer to the HW structure
874 * @offset: the word offset of the Shadow RAM word to read
875 * @pointer: pointer value read from Shadow RAM
877 * Read the given Shadow RAM word, and convert it to a pointer value specified
878 * in bytes. This function assumes the specified offset is a valid pointer
881 * Each pointer word specifies whether it is stored in word size or 4KB
882 * sector size by using the highest bit. The reported pointer value will be in
883 * bytes, intended for flat NVM reads.
885 static int ice_read_sr_pointer(struct ice_hw *hw, u16 offset, u32 *pointer)
890 status = ice_read_sr_word(hw, offset, &value);
894 /* Determine if the pointer is in 4KB or word units */
895 if (value & ICE_SR_NVM_PTR_4KB_UNITS)
896 *pointer = (value & ~ICE_SR_NVM_PTR_4KB_UNITS) * 4 * 1024;
898 *pointer = value * 2;
904 * ice_read_sr_area_size - Read an area size from a Shadow RAM word
905 * @hw: pointer to the HW structure
906 * @offset: the word offset of the Shadow RAM to read
907 * @size: size value read from the Shadow RAM
909 * Read the given Shadow RAM word, and convert it to an area size value
910 * specified in bytes. This function assumes the specified offset is a valid
913 * Each area size word is specified in 4KB sector units. This function reports
914 * the size in bytes, intended for flat NVM reads.
916 static int ice_read_sr_area_size(struct ice_hw *hw, u16 offset, u32 *size)
921 status = ice_read_sr_word(hw, offset, &value);
925 /* Area sizes are always specified in 4KB units */
926 *size = value * 4 * 1024;
932 * ice_determine_active_flash_banks - Discover active bank for each module
933 * @hw: pointer to the HW struct
935 * Read the Shadow RAM control word and determine which banks are active for
936 * the NVM, OROM, and Netlist modules. Also read and calculate the associated
937 * pointer and size. These values are then cached into the ice_flash_info
938 * structure for later use in order to calculate the correct offset to read
939 * from the active module.
941 static int ice_determine_active_flash_banks(struct ice_hw *hw)
943 struct ice_bank_info *banks = &hw->flash.banks;
947 status = ice_read_sr_word(hw, ICE_SR_NVM_CTRL_WORD, &ctrl_word);
949 ice_debug(hw, ICE_DBG_NVM, "Failed to read the Shadow RAM control word\n");
953 /* Check that the control word indicates validity */
954 if ((ctrl_word & ICE_SR_CTRL_WORD_1_M) >> ICE_SR_CTRL_WORD_1_S != ICE_SR_CTRL_WORD_VALID) {
955 ice_debug(hw, ICE_DBG_NVM, "Shadow RAM control word is invalid\n");
959 if (!(ctrl_word & ICE_SR_CTRL_WORD_NVM_BANK))
960 banks->nvm_bank = ICE_1ST_FLASH_BANK;
962 banks->nvm_bank = ICE_2ND_FLASH_BANK;
964 if (!(ctrl_word & ICE_SR_CTRL_WORD_OROM_BANK))
965 banks->orom_bank = ICE_1ST_FLASH_BANK;
967 banks->orom_bank = ICE_2ND_FLASH_BANK;
969 if (!(ctrl_word & ICE_SR_CTRL_WORD_NETLIST_BANK))
970 banks->netlist_bank = ICE_1ST_FLASH_BANK;
972 banks->netlist_bank = ICE_2ND_FLASH_BANK;
974 status = ice_read_sr_pointer(hw, ICE_SR_1ST_NVM_BANK_PTR, &banks->nvm_ptr);
976 ice_debug(hw, ICE_DBG_NVM, "Failed to read NVM bank pointer\n");
980 status = ice_read_sr_area_size(hw, ICE_SR_NVM_BANK_SIZE, &banks->nvm_size);
982 ice_debug(hw, ICE_DBG_NVM, "Failed to read NVM bank area size\n");
986 status = ice_read_sr_pointer(hw, ICE_SR_1ST_OROM_BANK_PTR, &banks->orom_ptr);
988 ice_debug(hw, ICE_DBG_NVM, "Failed to read OROM bank pointer\n");
992 status = ice_read_sr_area_size(hw, ICE_SR_OROM_BANK_SIZE, &banks->orom_size);
994 ice_debug(hw, ICE_DBG_NVM, "Failed to read OROM bank area size\n");
998 status = ice_read_sr_pointer(hw, ICE_SR_NETLIST_BANK_PTR, &banks->netlist_ptr);
1000 ice_debug(hw, ICE_DBG_NVM, "Failed to read Netlist bank pointer\n");
1004 status = ice_read_sr_area_size(hw, ICE_SR_NETLIST_BANK_SIZE, &banks->netlist_size);
1006 ice_debug(hw, ICE_DBG_NVM, "Failed to read Netlist bank area size\n");
1014 * ice_init_nvm - initializes NVM setting
1015 * @hw: pointer to the HW struct
1017 * This function reads and populates NVM settings such as Shadow RAM size,
1018 * max_timeout, and blank_nvm_mode
1020 int ice_init_nvm(struct ice_hw *hw)
1022 struct ice_flash_info *flash = &hw->flash;
1027 /* The SR size is stored regardless of the NVM programming mode
1028 * as the blank mode may be used in the factory line.
1030 gens_stat = rd32(hw, GLNVM_GENS);
1031 sr_size = (gens_stat & GLNVM_GENS_SR_SIZE_M) >> GLNVM_GENS_SR_SIZE_S;
1033 /* Switching to words (sr_size contains power of 2) */
1034 flash->sr_words = BIT(sr_size) * ICE_SR_WORDS_IN_1KB;
1036 /* Check if we are in the normal or blank NVM programming mode */
1037 fla = rd32(hw, GLNVM_FLA);
1038 if (fla & GLNVM_FLA_LOCKED_M) { /* Normal programming mode */
1039 flash->blank_nvm_mode = false;
1041 /* Blank programming mode */
1042 flash->blank_nvm_mode = true;
1043 ice_debug(hw, ICE_DBG_NVM, "NVM init error: unsupported blank mode.\n");
1047 status = ice_discover_flash_size(hw);
1049 ice_debug(hw, ICE_DBG_NVM, "NVM init error: failed to discover flash size.\n");
1053 status = ice_determine_active_flash_banks(hw);
1055 ice_debug(hw, ICE_DBG_NVM, "Failed to determine active flash banks.\n");
1059 status = ice_get_nvm_ver_info(hw, ICE_ACTIVE_FLASH_BANK, &flash->nvm);
1061 ice_debug(hw, ICE_DBG_INIT, "Failed to read NVM info.\n");
1065 status = ice_get_orom_ver_info(hw, ICE_ACTIVE_FLASH_BANK, &flash->orom);
1067 ice_debug(hw, ICE_DBG_INIT, "Failed to read Option ROM info.\n");
1069 /* read the netlist version information */
1070 status = ice_get_netlist_info(hw, ICE_ACTIVE_FLASH_BANK, &flash->netlist);
1072 ice_debug(hw, ICE_DBG_INIT, "Failed to read netlist info.\n");
1078 * ice_nvm_validate_checksum
1079 * @hw: pointer to the HW struct
1081 * Verify NVM PFA checksum validity (0x0706)
1083 int ice_nvm_validate_checksum(struct ice_hw *hw)
1085 struct ice_aqc_nvm_checksum *cmd;
1086 struct ice_aq_desc desc;
1089 status = ice_acquire_nvm(hw, ICE_RES_READ);
1093 cmd = &desc.params.nvm_checksum;
1095 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_checksum);
1096 cmd->flags = ICE_AQC_NVM_CHECKSUM_VERIFY;
1098 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1099 ice_release_nvm(hw);
1102 if (le16_to_cpu(cmd->checksum) != ICE_AQC_NVM_CHECKSUM_CORRECT)
1109 * ice_nvm_write_activate
1110 * @hw: pointer to the HW struct
1111 * @cmd_flags: flags for write activate command
1112 * @response_flags: response indicators from firmware
1114 * Update the control word with the required banks' validity bits
1115 * and dumps the Shadow RAM to flash (0x0707)
1117 * cmd_flags controls which banks to activate, and the preservation level to
1118 * use when activating the NVM bank.
1120 * On successful return of the firmware command, the response_flags variable
1121 * is updated with the flags reported by firmware indicating certain status,
1122 * such as whether EMP reset is enabled.
1124 int ice_nvm_write_activate(struct ice_hw *hw, u8 cmd_flags, u8 *response_flags)
1126 struct ice_aqc_nvm *cmd;
1127 struct ice_aq_desc desc;
1130 cmd = &desc.params.nvm;
1131 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_write_activate);
1133 cmd->cmd_flags = cmd_flags;
1135 err = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1136 if (!err && response_flags)
1137 *response_flags = cmd->cmd_flags;
1143 * ice_aq_nvm_update_empr
1144 * @hw: pointer to the HW struct
1146 * Update empr (0x0709). This command allows SW to
1147 * request an EMPR to activate new FW.
1149 int ice_aq_nvm_update_empr(struct ice_hw *hw)
1151 struct ice_aq_desc desc;
1153 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_update_empr);
1155 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1158 /* ice_nvm_set_pkg_data
1159 * @hw: pointer to the HW struct
1160 * @del_pkg_data_flag: If is set then the current pkg_data store by FW
1162 * If bit is set to 1, then buffer should be size 0.
1163 * @data: pointer to buffer
1164 * @length: length of the buffer
1165 * @cd: pointer to command details structure or NULL
1167 * Set package data (0x070A). This command is equivalent to the reception
1168 * of a PLDM FW Update GetPackageData cmd. This command should be sent
1169 * as part of the NVM update as the first cmd in the flow.
1173 ice_nvm_set_pkg_data(struct ice_hw *hw, bool del_pkg_data_flag, u8 *data,
1174 u16 length, struct ice_sq_cd *cd)
1176 struct ice_aqc_nvm_pkg_data *cmd;
1177 struct ice_aq_desc desc;
1179 if (length != 0 && !data)
1182 cmd = &desc.params.pkg_data;
1184 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_pkg_data);
1185 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
1187 if (del_pkg_data_flag)
1188 cmd->cmd_flags |= ICE_AQC_NVM_PKG_DELETE;
1190 return ice_aq_send_cmd(hw, &desc, data, length, cd);
1193 /* ice_nvm_pass_component_tbl
1194 * @hw: pointer to the HW struct
1195 * @data: pointer to buffer
1196 * @length: length of the buffer
1197 * @transfer_flag: parameter for determining stage of the update
1198 * @comp_response: a pointer to the response from the 0x070B AQC.
1199 * @comp_response_code: a pointer to the response code from the 0x070B AQC.
1200 * @cd: pointer to command details structure or NULL
1202 * Pass component table (0x070B). This command is equivalent to the reception
1203 * of a PLDM FW Update PassComponentTable cmd. This command should be sent once
1204 * per component. It can be only sent after Set Package Data cmd and before
1205 * actual update. FW will assume these commands are going to be sent until
1206 * the TransferFlag is set to End or StartAndEnd.
1210 ice_nvm_pass_component_tbl(struct ice_hw *hw, u8 *data, u16 length,
1211 u8 transfer_flag, u8 *comp_response,
1212 u8 *comp_response_code, struct ice_sq_cd *cd)
1214 struct ice_aqc_nvm_pass_comp_tbl *cmd;
1215 struct ice_aq_desc desc;
1218 if (!data || !comp_response || !comp_response_code)
1221 cmd = &desc.params.pass_comp_tbl;
1223 ice_fill_dflt_direct_cmd_desc(&desc,
1224 ice_aqc_opc_nvm_pass_component_tbl);
1225 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
1227 cmd->transfer_flag = transfer_flag;
1228 status = ice_aq_send_cmd(hw, &desc, data, length, cd);
1231 *comp_response = cmd->component_response;
1232 *comp_response_code = cmd->component_response_code;