1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018, Intel Corporation. */
4 #include "ice_common.h"
6 #include "ice_adminq_cmd.h"
9 #define ICE_PF_RESET_WAIT_COUNT 300
12 * ice_set_mac_type - Sets MAC type
13 * @hw: pointer to the HW structure
15 * This function sets the MAC type of the adapter based on the
16 * vendor ID and device ID stored in the HW structure.
18 static enum ice_status ice_set_mac_type(struct ice_hw *hw)
20 if (hw->vendor_id != PCI_VENDOR_ID_INTEL)
21 return ICE_ERR_DEVICE_NOT_SUPPORTED;
23 switch (hw->device_id) {
24 case ICE_DEV_ID_E810C_BACKPLANE:
25 case ICE_DEV_ID_E810C_QSFP:
26 case ICE_DEV_ID_E810C_SFP:
27 case ICE_DEV_ID_E810_XXV_SFP:
28 hw->mac_type = ICE_MAC_E810;
30 case ICE_DEV_ID_E823C_10G_BASE_T:
31 case ICE_DEV_ID_E823C_BACKPLANE:
32 case ICE_DEV_ID_E823C_QSFP:
33 case ICE_DEV_ID_E823C_SFP:
34 case ICE_DEV_ID_E823C_SGMII:
35 case ICE_DEV_ID_E822C_10G_BASE_T:
36 case ICE_DEV_ID_E822C_BACKPLANE:
37 case ICE_DEV_ID_E822C_QSFP:
38 case ICE_DEV_ID_E822C_SFP:
39 case ICE_DEV_ID_E822C_SGMII:
40 case ICE_DEV_ID_E822L_10G_BASE_T:
41 case ICE_DEV_ID_E822L_BACKPLANE:
42 case ICE_DEV_ID_E822L_SFP:
43 case ICE_DEV_ID_E822L_SGMII:
44 case ICE_DEV_ID_E823L_10G_BASE_T:
45 case ICE_DEV_ID_E823L_1GBE:
46 case ICE_DEV_ID_E823L_BACKPLANE:
47 case ICE_DEV_ID_E823L_QSFP:
48 case ICE_DEV_ID_E823L_SFP:
49 hw->mac_type = ICE_MAC_GENERIC;
52 hw->mac_type = ICE_MAC_UNKNOWN;
56 ice_debug(hw, ICE_DBG_INIT, "mac_type: %d\n", hw->mac_type);
61 * ice_clear_pf_cfg - Clear PF configuration
62 * @hw: pointer to the hardware structure
64 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port
65 * configuration, flow director filters, etc.).
67 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw)
69 struct ice_aq_desc desc;
71 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg);
73 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
77 * ice_aq_manage_mac_read - manage MAC address read command
78 * @hw: pointer to the HW struct
79 * @buf: a virtual buffer to hold the manage MAC read response
80 * @buf_size: Size of the virtual buffer
81 * @cd: pointer to command details structure or NULL
83 * This function is used to return per PF station MAC address (0x0107).
84 * NOTE: Upon successful completion of this command, MAC address information
85 * is returned in user specified buffer. Please interpret user specified
86 * buffer as "manage_mac_read" response.
87 * Response such as various MAC addresses are stored in HW struct (port.mac)
88 * ice_discover_dev_caps is expected to be called before this function is
91 static enum ice_status
92 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size,
95 struct ice_aqc_manage_mac_read_resp *resp;
96 struct ice_aqc_manage_mac_read *cmd;
97 struct ice_aq_desc desc;
98 enum ice_status status;
102 cmd = &desc.params.mac_read;
104 if (buf_size < sizeof(*resp))
105 return ICE_ERR_BUF_TOO_SHORT;
107 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read);
109 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
113 resp = (struct ice_aqc_manage_mac_read_resp *)buf;
114 flags = le16_to_cpu(cmd->flags) & ICE_AQC_MAN_MAC_READ_M;
116 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) {
117 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n");
121 /* A single port can report up to two (LAN and WoL) addresses */
122 for (i = 0; i < cmd->num_addr; i++)
123 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) {
124 ether_addr_copy(hw->port_info->mac.lan_addr,
126 ether_addr_copy(hw->port_info->mac.perm_addr,
135 * ice_aq_get_phy_caps - returns PHY capabilities
136 * @pi: port information structure
137 * @qual_mods: report qualified modules
138 * @report_mode: report mode capabilities
139 * @pcaps: structure for PHY capabilities to be filled
140 * @cd: pointer to command details structure or NULL
142 * Returns the various PHY capabilities supported on the Port (0x0600)
145 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
146 struct ice_aqc_get_phy_caps_data *pcaps,
147 struct ice_sq_cd *cd)
149 struct ice_aqc_get_phy_caps *cmd;
150 u16 pcaps_size = sizeof(*pcaps);
151 struct ice_aq_desc desc;
152 enum ice_status status;
155 cmd = &desc.params.get_phy;
157 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi)
158 return ICE_ERR_PARAM;
161 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps);
164 cmd->param0 |= cpu_to_le16(ICE_AQC_GET_PHY_RQM);
166 cmd->param0 |= cpu_to_le16(report_mode);
167 status = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd);
169 ice_debug(hw, ICE_DBG_LINK, "get phy caps - report_mode = 0x%x\n",
171 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n",
172 (unsigned long long)le64_to_cpu(pcaps->phy_type_low));
173 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n",
174 (unsigned long long)le64_to_cpu(pcaps->phy_type_high));
175 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", pcaps->caps);
176 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n",
177 pcaps->low_power_ctrl_an);
178 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", pcaps->eee_cap);
179 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n",
181 ice_debug(hw, ICE_DBG_LINK, " link_fec_options = 0x%x\n",
182 pcaps->link_fec_options);
183 ice_debug(hw, ICE_DBG_LINK, " module_compliance_enforcement = 0x%x\n",
184 pcaps->module_compliance_enforcement);
185 ice_debug(hw, ICE_DBG_LINK, " extended_compliance_code = 0x%x\n",
186 pcaps->extended_compliance_code);
187 ice_debug(hw, ICE_DBG_LINK, " module_type[0] = 0x%x\n",
188 pcaps->module_type[0]);
189 ice_debug(hw, ICE_DBG_LINK, " module_type[1] = 0x%x\n",
190 pcaps->module_type[1]);
191 ice_debug(hw, ICE_DBG_LINK, " module_type[2] = 0x%x\n",
192 pcaps->module_type[2]);
194 if (!status && report_mode == ICE_AQC_REPORT_TOPO_CAP) {
195 pi->phy.phy_type_low = le64_to_cpu(pcaps->phy_type_low);
196 pi->phy.phy_type_high = le64_to_cpu(pcaps->phy_type_high);
197 memcpy(pi->phy.link_info.module_type, &pcaps->module_type,
198 sizeof(pi->phy.link_info.module_type));
205 * ice_aq_get_link_topo_handle - get link topology node return status
206 * @pi: port information structure
207 * @node_type: requested node type
208 * @cd: pointer to command details structure or NULL
210 * Get link topology node return status for specified node type (0x06E0)
212 * Node type cage can be used to determine if cage is present. If AQC
213 * returns error (ENOENT), then no cage present. If no cage present, then
214 * connection type is backplane or BASE-T.
216 static enum ice_status
217 ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type,
218 struct ice_sq_cd *cd)
220 struct ice_aqc_get_link_topo *cmd;
221 struct ice_aq_desc desc;
223 cmd = &desc.params.get_link_topo;
225 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo);
227 cmd->addr.node_type_ctx = (ICE_AQC_LINK_TOPO_NODE_CTX_PORT <<
228 ICE_AQC_LINK_TOPO_NODE_CTX_S);
231 cmd->addr.node_type_ctx |= (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type);
233 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
237 * ice_is_media_cage_present
238 * @pi: port information structure
240 * Returns true if media cage is present, else false. If no cage, then
241 * media type is backplane or BASE-T.
243 static bool ice_is_media_cage_present(struct ice_port_info *pi)
245 /* Node type cage can be used to determine if cage is present. If AQC
246 * returns error (ENOENT), then no cage present. If no cage present then
247 * connection type is backplane or BASE-T.
249 return !ice_aq_get_link_topo_handle(pi,
250 ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE,
255 * ice_get_media_type - Gets media type
256 * @pi: port information structure
258 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi)
260 struct ice_link_status *hw_link_info;
263 return ICE_MEDIA_UNKNOWN;
265 hw_link_info = &pi->phy.link_info;
266 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high)
267 /* If more than one media type is selected, report unknown */
268 return ICE_MEDIA_UNKNOWN;
270 if (hw_link_info->phy_type_low) {
271 /* 1G SGMII is a special case where some DA cable PHYs
272 * may show this as an option when it really shouldn't
273 * be since SGMII is meant to be between a MAC and a PHY
274 * in a backplane. Try to detect this case and handle it
276 if (hw_link_info->phy_type_low == ICE_PHY_TYPE_LOW_1G_SGMII &&
277 (hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] ==
278 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE ||
279 hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] ==
280 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE))
283 switch (hw_link_info->phy_type_low) {
284 case ICE_PHY_TYPE_LOW_1000BASE_SX:
285 case ICE_PHY_TYPE_LOW_1000BASE_LX:
286 case ICE_PHY_TYPE_LOW_10GBASE_SR:
287 case ICE_PHY_TYPE_LOW_10GBASE_LR:
288 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
289 case ICE_PHY_TYPE_LOW_25GBASE_SR:
290 case ICE_PHY_TYPE_LOW_25GBASE_LR:
291 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
292 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
293 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
294 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
295 case ICE_PHY_TYPE_LOW_50GBASE_SR:
296 case ICE_PHY_TYPE_LOW_50GBASE_FR:
297 case ICE_PHY_TYPE_LOW_50GBASE_LR:
298 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
299 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
300 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
301 case ICE_PHY_TYPE_LOW_100GBASE_DR:
302 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC:
303 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC:
304 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC:
305 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC:
306 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC:
307 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:
308 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC:
309 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC:
310 return ICE_MEDIA_FIBER;
311 case ICE_PHY_TYPE_LOW_100BASE_TX:
312 case ICE_PHY_TYPE_LOW_1000BASE_T:
313 case ICE_PHY_TYPE_LOW_2500BASE_T:
314 case ICE_PHY_TYPE_LOW_5GBASE_T:
315 case ICE_PHY_TYPE_LOW_10GBASE_T:
316 case ICE_PHY_TYPE_LOW_25GBASE_T:
317 return ICE_MEDIA_BASET;
318 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
319 case ICE_PHY_TYPE_LOW_25GBASE_CR:
320 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
321 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
322 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
323 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
324 case ICE_PHY_TYPE_LOW_50GBASE_CP:
325 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
326 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
327 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
329 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
330 case ICE_PHY_TYPE_LOW_40G_XLAUI:
331 case ICE_PHY_TYPE_LOW_50G_LAUI2:
332 case ICE_PHY_TYPE_LOW_50G_AUI2:
333 case ICE_PHY_TYPE_LOW_50G_AUI1:
334 case ICE_PHY_TYPE_LOW_100G_AUI4:
335 case ICE_PHY_TYPE_LOW_100G_CAUI4:
336 if (ice_is_media_cage_present(pi))
339 case ICE_PHY_TYPE_LOW_1000BASE_KX:
340 case ICE_PHY_TYPE_LOW_2500BASE_KX:
341 case ICE_PHY_TYPE_LOW_2500BASE_X:
342 case ICE_PHY_TYPE_LOW_5GBASE_KR:
343 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
344 case ICE_PHY_TYPE_LOW_25GBASE_KR:
345 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
346 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
347 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
348 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
349 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
350 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
351 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
352 return ICE_MEDIA_BACKPLANE;
355 switch (hw_link_info->phy_type_high) {
356 case ICE_PHY_TYPE_HIGH_100G_AUI2:
357 case ICE_PHY_TYPE_HIGH_100G_CAUI2:
358 if (ice_is_media_cage_present(pi))
361 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
362 return ICE_MEDIA_BACKPLANE;
363 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC:
364 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC:
365 return ICE_MEDIA_FIBER;
368 return ICE_MEDIA_UNKNOWN;
372 * ice_aq_get_link_info
373 * @pi: port information structure
374 * @ena_lse: enable/disable LinkStatusEvent reporting
375 * @link: pointer to link status structure - optional
376 * @cd: pointer to command details structure or NULL
378 * Get Link Status (0x607). Returns the link status of the adapter.
381 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
382 struct ice_link_status *link, struct ice_sq_cd *cd)
384 struct ice_aqc_get_link_status_data link_data = { 0 };
385 struct ice_aqc_get_link_status *resp;
386 struct ice_link_status *li_old, *li;
387 enum ice_media_type *hw_media_type;
388 struct ice_fc_info *hw_fc_info;
389 bool tx_pause, rx_pause;
390 struct ice_aq_desc desc;
391 enum ice_status status;
396 return ICE_ERR_PARAM;
398 li_old = &pi->phy.link_info_old;
399 hw_media_type = &pi->phy.media_type;
400 li = &pi->phy.link_info;
401 hw_fc_info = &pi->fc;
403 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status);
404 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS;
405 resp = &desc.params.get_link_status;
406 resp->cmd_flags = cpu_to_le16(cmd_flags);
407 resp->lport_num = pi->lport;
409 status = ice_aq_send_cmd(hw, &desc, &link_data, sizeof(link_data), cd);
414 /* save off old link status information */
417 /* update current link status information */
418 li->link_speed = le16_to_cpu(link_data.link_speed);
419 li->phy_type_low = le64_to_cpu(link_data.phy_type_low);
420 li->phy_type_high = le64_to_cpu(link_data.phy_type_high);
421 *hw_media_type = ice_get_media_type(pi);
422 li->link_info = link_data.link_info;
423 li->an_info = link_data.an_info;
424 li->ext_info = link_data.ext_info;
425 li->max_frame_size = le16_to_cpu(link_data.max_frame_size);
426 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK;
427 li->topo_media_conflict = link_data.topo_media_conflict;
428 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M |
429 ICE_AQ_CFG_PACING_TYPE_M);
432 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX);
433 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX);
434 if (tx_pause && rx_pause)
435 hw_fc_info->current_mode = ICE_FC_FULL;
437 hw_fc_info->current_mode = ICE_FC_TX_PAUSE;
439 hw_fc_info->current_mode = ICE_FC_RX_PAUSE;
441 hw_fc_info->current_mode = ICE_FC_NONE;
443 li->lse_ena = !!(resp->cmd_flags & cpu_to_le16(ICE_AQ_LSE_IS_ENABLED));
445 ice_debug(hw, ICE_DBG_LINK, "get link info\n");
446 ice_debug(hw, ICE_DBG_LINK, " link_speed = 0x%x\n", li->link_speed);
447 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n",
448 (unsigned long long)li->phy_type_low);
449 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n",
450 (unsigned long long)li->phy_type_high);
451 ice_debug(hw, ICE_DBG_LINK, " media_type = 0x%x\n", *hw_media_type);
452 ice_debug(hw, ICE_DBG_LINK, " link_info = 0x%x\n", li->link_info);
453 ice_debug(hw, ICE_DBG_LINK, " an_info = 0x%x\n", li->an_info);
454 ice_debug(hw, ICE_DBG_LINK, " ext_info = 0x%x\n", li->ext_info);
455 ice_debug(hw, ICE_DBG_LINK, " fec_info = 0x%x\n", li->fec_info);
456 ice_debug(hw, ICE_DBG_LINK, " lse_ena = 0x%x\n", li->lse_ena);
457 ice_debug(hw, ICE_DBG_LINK, " max_frame = 0x%x\n",
459 ice_debug(hw, ICE_DBG_LINK, " pacing = 0x%x\n", li->pacing);
461 /* save link status information */
465 /* flag cleared so calling functions don't call AQ again */
466 pi->phy.get_link_info = false;
472 * ice_fill_tx_timer_and_fc_thresh
473 * @hw: pointer to the HW struct
474 * @cmd: pointer to MAC cfg structure
476 * Add Tx timer and FC refresh threshold info to Set MAC Config AQ command
480 ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw,
481 struct ice_aqc_set_mac_cfg *cmd)
483 u16 fc_thres_val, tx_timer_val;
486 /* We read back the transmit timer and FC threshold value of
487 * LFC. Thus, we will use index =
488 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX.
490 * Also, because we are operating on transmit timer and FC
491 * threshold of LFC, we don't turn on any bit in tx_tmr_priority
493 #define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX
495 /* Retrieve the transmit timer */
496 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC));
498 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M;
499 cmd->tx_tmr_value = cpu_to_le16(tx_timer_val);
501 /* Retrieve the FC threshold */
502 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC));
503 fc_thres_val = val & PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M;
505 cmd->fc_refresh_threshold = cpu_to_le16(fc_thres_val);
510 * @hw: pointer to the HW struct
511 * @max_frame_size: Maximum Frame Size to be supported
512 * @cd: pointer to command details structure or NULL
514 * Set MAC configuration (0x0603)
517 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd)
519 struct ice_aqc_set_mac_cfg *cmd;
520 struct ice_aq_desc desc;
522 cmd = &desc.params.set_mac_cfg;
524 if (max_frame_size == 0)
525 return ICE_ERR_PARAM;
527 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg);
529 cmd->max_frame_size = cpu_to_le16(max_frame_size);
531 ice_fill_tx_timer_and_fc_thresh(hw, cmd);
533 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
537 * ice_init_fltr_mgmt_struct - initializes filter management list and locks
538 * @hw: pointer to the HW struct
540 static enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw)
542 struct ice_switch_info *sw;
543 enum ice_status status;
545 hw->switch_info = devm_kzalloc(ice_hw_to_dev(hw),
546 sizeof(*hw->switch_info), GFP_KERNEL);
547 sw = hw->switch_info;
550 return ICE_ERR_NO_MEMORY;
552 INIT_LIST_HEAD(&sw->vsi_list_map_head);
554 status = ice_init_def_sw_recp(hw);
556 devm_kfree(ice_hw_to_dev(hw), hw->switch_info);
563 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks
564 * @hw: pointer to the HW struct
566 static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw)
568 struct ice_switch_info *sw = hw->switch_info;
569 struct ice_vsi_list_map_info *v_pos_map;
570 struct ice_vsi_list_map_info *v_tmp_map;
571 struct ice_sw_recipe *recps;
574 list_for_each_entry_safe(v_pos_map, v_tmp_map, &sw->vsi_list_map_head,
576 list_del(&v_pos_map->list_entry);
577 devm_kfree(ice_hw_to_dev(hw), v_pos_map);
579 recps = hw->switch_info->recp_list;
580 for (i = 0; i < ICE_SW_LKUP_LAST; i++) {
581 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry;
583 recps[i].root_rid = i;
584 mutex_destroy(&recps[i].filt_rule_lock);
585 list_for_each_entry_safe(lst_itr, tmp_entry,
586 &recps[i].filt_rules, list_entry) {
587 list_del(&lst_itr->list_entry);
588 devm_kfree(ice_hw_to_dev(hw), lst_itr);
591 ice_rm_all_sw_replay_rule_info(hw);
592 devm_kfree(ice_hw_to_dev(hw), sw->recp_list);
593 devm_kfree(ice_hw_to_dev(hw), sw);
597 * ice_get_fw_log_cfg - get FW logging configuration
598 * @hw: pointer to the HW struct
600 static enum ice_status ice_get_fw_log_cfg(struct ice_hw *hw)
602 struct ice_aq_desc desc;
603 enum ice_status status;
607 size = sizeof(*config) * ICE_AQC_FW_LOG_ID_MAX;
608 config = devm_kzalloc(ice_hw_to_dev(hw), size, GFP_KERNEL);
610 return ICE_ERR_NO_MEMORY;
612 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging_info);
614 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
616 status = ice_aq_send_cmd(hw, &desc, config, size, NULL);
620 /* Save FW logging information into the HW structure */
621 for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) {
624 v = le16_to_cpu(config[i]);
625 m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S;
626 flgs = (v & ICE_AQC_FW_LOG_EN_M) >> ICE_AQC_FW_LOG_EN_S;
628 if (m < ICE_AQC_FW_LOG_ID_MAX)
629 hw->fw_log.evnts[m].cur = flgs;
633 devm_kfree(ice_hw_to_dev(hw), config);
639 * ice_cfg_fw_log - configure FW logging
640 * @hw: pointer to the HW struct
641 * @enable: enable certain FW logging events if true, disable all if false
643 * This function enables/disables the FW logging via Rx CQ events and a UART
644 * port based on predetermined configurations. FW logging via the Rx CQ can be
645 * enabled/disabled for individual PF's. However, FW logging via the UART can
646 * only be enabled/disabled for all PFs on the same device.
648 * To enable overall FW logging, the "cq_en" and "uart_en" enable bits in
649 * hw->fw_log need to be set accordingly, e.g. based on user-provided input,
650 * before initializing the device.
652 * When re/configuring FW logging, callers need to update the "cfg" elements of
653 * the hw->fw_log.evnts array with the desired logging event configurations for
654 * modules of interest. When disabling FW logging completely, the callers can
655 * just pass false in the "enable" parameter. On completion, the function will
656 * update the "cur" element of the hw->fw_log.evnts array with the resulting
657 * logging event configurations of the modules that are being re/configured. FW
658 * logging modules that are not part of a reconfiguration operation retain their
661 * Before resetting the device, it is recommended that the driver disables FW
662 * logging before shutting down the control queue. When disabling FW logging
663 * ("enable" = false), the latest configurations of FW logging events stored in
664 * hw->fw_log.evnts[] are not overridden to allow them to be reconfigured after
667 * When enabling FW logging to emit log messages via the Rx CQ during the
668 * device's initialization phase, a mechanism alternative to interrupt handlers
669 * needs to be used to extract FW log messages from the Rx CQ periodically and
670 * to prevent the Rx CQ from being full and stalling other types of control
671 * messages from FW to SW. Interrupts are typically disabled during the device's
672 * initialization phase.
674 static enum ice_status ice_cfg_fw_log(struct ice_hw *hw, bool enable)
676 struct ice_aqc_fw_logging *cmd;
677 enum ice_status status = 0;
678 u16 i, chgs = 0, len = 0;
679 struct ice_aq_desc desc;
684 if (!hw->fw_log.cq_en && !hw->fw_log.uart_en)
687 /* Disable FW logging only when the control queue is still responsive */
689 (!hw->fw_log.actv_evnts || !ice_check_sq_alive(hw, &hw->adminq)))
692 /* Get current FW log settings */
693 status = ice_get_fw_log_cfg(hw);
697 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging);
698 cmd = &desc.params.fw_logging;
700 /* Indicate which controls are valid */
701 if (hw->fw_log.cq_en)
702 cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_AQ_VALID;
704 if (hw->fw_log.uart_en)
705 cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_UART_VALID;
708 /* Fill in an array of entries with FW logging modules and
709 * logging events being reconfigured.
711 for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) {
714 /* Keep track of enabled event types */
715 actv_evnts |= hw->fw_log.evnts[i].cfg;
717 if (hw->fw_log.evnts[i].cfg == hw->fw_log.evnts[i].cur)
721 data = devm_kcalloc(ice_hw_to_dev(hw),
723 ICE_AQC_FW_LOG_ID_MAX,
726 return ICE_ERR_NO_MEMORY;
729 val = i << ICE_AQC_FW_LOG_ID_S;
730 val |= hw->fw_log.evnts[i].cfg << ICE_AQC_FW_LOG_EN_S;
731 data[chgs++] = cpu_to_le16(val);
734 /* Only enable FW logging if at least one module is specified.
735 * If FW logging is currently enabled but all modules are not
736 * enabled to emit log messages, disable FW logging altogether.
739 /* Leave if there is effectively no change */
743 if (hw->fw_log.cq_en)
744 cmd->log_ctrl |= ICE_AQC_FW_LOG_AQ_EN;
746 if (hw->fw_log.uart_en)
747 cmd->log_ctrl |= ICE_AQC_FW_LOG_UART_EN;
750 len = sizeof(*data) * chgs;
751 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
755 status = ice_aq_send_cmd(hw, &desc, buf, len, NULL);
757 /* Update the current configuration to reflect events enabled.
758 * hw->fw_log.cq_en and hw->fw_log.uart_en indicate if the FW
759 * logging mode is enabled for the device. They do not reflect
760 * actual modules being enabled to emit log messages. So, their
761 * values remain unchanged even when all modules are disabled.
763 u16 cnt = enable ? chgs : (u16)ICE_AQC_FW_LOG_ID_MAX;
765 hw->fw_log.actv_evnts = actv_evnts;
766 for (i = 0; i < cnt; i++) {
770 /* When disabling all FW logging events as part
771 * of device's de-initialization, the original
772 * configurations are retained, and can be used
773 * to reconfigure FW logging later if the device
776 hw->fw_log.evnts[i].cur = 0;
780 v = le16_to_cpu(data[i]);
781 m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S;
782 hw->fw_log.evnts[m].cur = hw->fw_log.evnts[m].cfg;
788 devm_kfree(ice_hw_to_dev(hw), data);
795 * @hw: pointer to the HW struct
796 * @desc: pointer to the AQ message descriptor
797 * @buf: pointer to the buffer accompanying the AQ message
799 * Formats a FW Log message and outputs it via the standard driver logs.
801 void ice_output_fw_log(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf)
803 ice_debug(hw, ICE_DBG_FW_LOG, "[ FW Log Msg Start ]\n");
804 ice_debug_array(hw, ICE_DBG_FW_LOG, 16, 1, (u8 *)buf,
805 le16_to_cpu(desc->datalen));
806 ice_debug(hw, ICE_DBG_FW_LOG, "[ FW Log Msg End ]\n");
810 * ice_get_itr_intrl_gran
811 * @hw: pointer to the HW struct
813 * Determines the ITR/INTRL granularities based on the maximum aggregate
814 * bandwidth according to the device's configuration during power-on.
816 static void ice_get_itr_intrl_gran(struct ice_hw *hw)
818 u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) &
819 GL_PWR_MODE_CTL_CAR_MAX_BW_M) >>
820 GL_PWR_MODE_CTL_CAR_MAX_BW_S;
822 switch (max_agg_bw) {
823 case ICE_MAX_AGG_BW_200G:
824 case ICE_MAX_AGG_BW_100G:
825 case ICE_MAX_AGG_BW_50G:
826 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25;
827 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25;
829 case ICE_MAX_AGG_BW_25G:
830 hw->itr_gran = ICE_ITR_GRAN_MAX_25;
831 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25;
837 * ice_init_hw - main hardware initialization routine
838 * @hw: pointer to the hardware structure
840 enum ice_status ice_init_hw(struct ice_hw *hw)
842 struct ice_aqc_get_phy_caps_data *pcaps;
843 enum ice_status status;
847 /* Set MAC type based on DeviceID */
848 status = ice_set_mac_type(hw);
852 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) &
853 PF_FUNC_RID_FUNC_NUM_M) >>
854 PF_FUNC_RID_FUNC_NUM_S;
856 status = ice_reset(hw, ICE_RESET_PFR);
860 ice_get_itr_intrl_gran(hw);
862 status = ice_create_all_ctrlq(hw);
864 goto err_unroll_cqinit;
866 /* Enable FW logging. Not fatal if this fails. */
867 status = ice_cfg_fw_log(hw, true);
869 ice_debug(hw, ICE_DBG_INIT, "Failed to enable FW logging.\n");
871 status = ice_clear_pf_cfg(hw);
873 goto err_unroll_cqinit;
875 /* Set bit to enable Flow Director filters */
876 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M);
877 INIT_LIST_HEAD(&hw->fdir_list_head);
879 ice_clear_pxe_mode(hw);
881 status = ice_init_nvm(hw);
883 goto err_unroll_cqinit;
885 status = ice_get_caps(hw);
887 goto err_unroll_cqinit;
889 hw->port_info = devm_kzalloc(ice_hw_to_dev(hw),
890 sizeof(*hw->port_info), GFP_KERNEL);
891 if (!hw->port_info) {
892 status = ICE_ERR_NO_MEMORY;
893 goto err_unroll_cqinit;
896 /* set the back pointer to HW */
897 hw->port_info->hw = hw;
899 /* Initialize port_info struct with switch configuration data */
900 status = ice_get_initial_sw_cfg(hw);
902 goto err_unroll_alloc;
906 /* Query the allocated resources for Tx scheduler */
907 status = ice_sched_query_res_alloc(hw);
909 ice_debug(hw, ICE_DBG_SCHED,
910 "Failed to get scheduler allocated resources\n");
911 goto err_unroll_alloc;
914 /* Initialize port_info struct with scheduler data */
915 status = ice_sched_init_port(hw->port_info);
917 goto err_unroll_sched;
919 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL);
921 status = ICE_ERR_NO_MEMORY;
922 goto err_unroll_sched;
925 /* Initialize port_info struct with PHY capabilities */
926 status = ice_aq_get_phy_caps(hw->port_info, false,
927 ICE_AQC_REPORT_TOPO_CAP, pcaps, NULL);
928 devm_kfree(ice_hw_to_dev(hw), pcaps);
930 goto err_unroll_sched;
932 /* Initialize port_info struct with link information */
933 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL);
935 goto err_unroll_sched;
937 /* need a valid SW entry point to build a Tx tree */
938 if (!hw->sw_entry_point_layer) {
939 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n");
940 status = ICE_ERR_CFG;
941 goto err_unroll_sched;
943 INIT_LIST_HEAD(&hw->agg_list);
944 /* Initialize max burst size */
945 if (!hw->max_burst_size)
946 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE);
948 status = ice_init_fltr_mgmt_struct(hw);
950 goto err_unroll_sched;
952 /* Get MAC information */
953 /* A single port can report up to two (LAN and WoL) addresses */
954 mac_buf = devm_kcalloc(ice_hw_to_dev(hw), 2,
955 sizeof(struct ice_aqc_manage_mac_read_resp),
957 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp);
960 status = ICE_ERR_NO_MEMORY;
961 goto err_unroll_fltr_mgmt_struct;
964 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL);
965 devm_kfree(ice_hw_to_dev(hw), mac_buf);
968 goto err_unroll_fltr_mgmt_struct;
969 /* enable jumbo frame support at MAC level */
970 status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL);
972 goto err_unroll_fltr_mgmt_struct;
973 /* Obtain counter base index which would be used by flow director */
974 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base);
976 goto err_unroll_fltr_mgmt_struct;
977 status = ice_init_hw_tbls(hw);
979 goto err_unroll_fltr_mgmt_struct;
980 mutex_init(&hw->tnl_lock);
983 err_unroll_fltr_mgmt_struct:
984 ice_cleanup_fltr_mgmt_struct(hw);
986 ice_sched_cleanup_all(hw);
988 devm_kfree(ice_hw_to_dev(hw), hw->port_info);
990 ice_destroy_all_ctrlq(hw);
995 * ice_deinit_hw - unroll initialization operations done by ice_init_hw
996 * @hw: pointer to the hardware structure
998 * This should be called only during nominal operation, not as a result of
999 * ice_init_hw() failing since ice_init_hw() will take care of unrolling
1000 * applicable initializations if it fails for any reason.
1002 void ice_deinit_hw(struct ice_hw *hw)
1004 ice_free_fd_res_cntr(hw, hw->fd_ctr_base);
1005 ice_cleanup_fltr_mgmt_struct(hw);
1007 ice_sched_cleanup_all(hw);
1008 ice_sched_clear_agg(hw);
1010 ice_free_hw_tbls(hw);
1011 mutex_destroy(&hw->tnl_lock);
1013 if (hw->port_info) {
1014 devm_kfree(ice_hw_to_dev(hw), hw->port_info);
1015 hw->port_info = NULL;
1018 /* Attempt to disable FW logging before shutting down control queues */
1019 ice_cfg_fw_log(hw, false);
1020 ice_destroy_all_ctrlq(hw);
1022 /* Clear VSI contexts if not already cleared */
1023 ice_clear_all_vsi_ctx(hw);
1027 * ice_check_reset - Check to see if a global reset is complete
1028 * @hw: pointer to the hardware structure
1030 enum ice_status ice_check_reset(struct ice_hw *hw)
1032 u32 cnt, reg = 0, grst_delay, uld_mask;
1034 /* Poll for Device Active state in case a recent CORER, GLOBR,
1035 * or EMPR has occurred. The grst delay value is in 100ms units.
1036 * Add 1sec for outstanding AQ commands that can take a long time.
1038 grst_delay = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >>
1039 GLGEN_RSTCTL_GRSTDEL_S) + 10;
1041 for (cnt = 0; cnt < grst_delay; cnt++) {
1043 reg = rd32(hw, GLGEN_RSTAT);
1044 if (!(reg & GLGEN_RSTAT_DEVSTATE_M))
1048 if (cnt == grst_delay) {
1049 ice_debug(hw, ICE_DBG_INIT,
1050 "Global reset polling failed to complete.\n");
1051 return ICE_ERR_RESET_FAILED;
1054 #define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\
1055 GLNVM_ULD_PCIER_DONE_1_M |\
1056 GLNVM_ULD_CORER_DONE_M |\
1057 GLNVM_ULD_GLOBR_DONE_M |\
1058 GLNVM_ULD_POR_DONE_M |\
1059 GLNVM_ULD_POR_DONE_1_M |\
1060 GLNVM_ULD_PCIER_DONE_2_M)
1062 uld_mask = ICE_RESET_DONE_MASK;
1064 /* Device is Active; check Global Reset processes are done */
1065 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
1066 reg = rd32(hw, GLNVM_ULD) & uld_mask;
1067 if (reg == uld_mask) {
1068 ice_debug(hw, ICE_DBG_INIT,
1069 "Global reset processes done. %d\n", cnt);
1075 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
1076 ice_debug(hw, ICE_DBG_INIT,
1077 "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n",
1079 return ICE_ERR_RESET_FAILED;
1086 * ice_pf_reset - Reset the PF
1087 * @hw: pointer to the hardware structure
1089 * If a global reset has been triggered, this function checks
1090 * for its completion and then issues the PF reset
1092 static enum ice_status ice_pf_reset(struct ice_hw *hw)
1096 /* If at function entry a global reset was already in progress, i.e.
1097 * state is not 'device active' or any of the reset done bits are not
1098 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the
1099 * global reset is done.
1101 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) ||
1102 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) {
1103 /* poll on global reset currently in progress until done */
1104 if (ice_check_reset(hw))
1105 return ICE_ERR_RESET_FAILED;
1111 reg = rd32(hw, PFGEN_CTRL);
1113 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M));
1115 /* Wait for the PFR to complete. The wait time is the global config lock
1116 * timeout plus the PFR timeout which will account for a possible reset
1117 * that is occurring during a download package operation.
1119 for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT +
1120 ICE_PF_RESET_WAIT_COUNT; cnt++) {
1121 reg = rd32(hw, PFGEN_CTRL);
1122 if (!(reg & PFGEN_CTRL_PFSWR_M))
1128 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
1129 ice_debug(hw, ICE_DBG_INIT,
1130 "PF reset polling failed to complete.\n");
1131 return ICE_ERR_RESET_FAILED;
1138 * ice_reset - Perform different types of reset
1139 * @hw: pointer to the hardware structure
1140 * @req: reset request
1142 * This function triggers a reset as specified by the req parameter.
1145 * If anything other than a PF reset is triggered, PXE mode is restored.
1146 * This has to be cleared using ice_clear_pxe_mode again, once the AQ
1147 * interface has been restored in the rebuild flow.
1149 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req)
1155 return ice_pf_reset(hw);
1156 case ICE_RESET_CORER:
1157 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n");
1158 val = GLGEN_RTRIG_CORER_M;
1160 case ICE_RESET_GLOBR:
1161 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n");
1162 val = GLGEN_RTRIG_GLOBR_M;
1165 return ICE_ERR_PARAM;
1168 val |= rd32(hw, GLGEN_RTRIG);
1169 wr32(hw, GLGEN_RTRIG, val);
1172 /* wait for the FW to be ready */
1173 return ice_check_reset(hw);
1177 * ice_copy_rxq_ctx_to_hw
1178 * @hw: pointer to the hardware structure
1179 * @ice_rxq_ctx: pointer to the rxq context
1180 * @rxq_index: the index of the Rx queue
1182 * Copies rxq context from dense structure to HW register space
1184 static enum ice_status
1185 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index)
1190 return ICE_ERR_BAD_PTR;
1192 if (rxq_index > QRX_CTRL_MAX_INDEX)
1193 return ICE_ERR_PARAM;
1195 /* Copy each dword separately to HW */
1196 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) {
1197 wr32(hw, QRX_CONTEXT(i, rxq_index),
1198 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1200 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i,
1201 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1207 /* LAN Rx Queue Context */
1208 static const struct ice_ctx_ele ice_rlan_ctx_info[] = {
1209 /* Field Width LSB */
1210 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0),
1211 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13),
1212 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32),
1213 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89),
1214 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102),
1215 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109),
1216 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114),
1217 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116),
1218 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117),
1219 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119),
1220 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120),
1221 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124),
1222 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127),
1223 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174),
1224 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193),
1225 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194),
1226 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195),
1227 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196),
1228 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198),
1229 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201),
1235 * @hw: pointer to the hardware structure
1236 * @rlan_ctx: pointer to the rxq context
1237 * @rxq_index: the index of the Rx queue
1239 * Converts rxq context from sparse to dense structure and then writes
1240 * it to HW register space and enables the hardware to prefetch descriptors
1241 * instead of only fetching them on demand
1244 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
1247 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 };
1250 return ICE_ERR_BAD_PTR;
1252 rlan_ctx->prefena = 1;
1254 ice_set_ctx(hw, (u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info);
1255 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index);
1258 /* LAN Tx Queue Context */
1259 const struct ice_ctx_ele ice_tlan_ctx_info[] = {
1260 /* Field Width LSB */
1261 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0),
1262 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57),
1263 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60),
1264 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65),
1265 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68),
1266 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78),
1267 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80),
1268 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90),
1269 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91),
1270 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92),
1271 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93),
1272 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101),
1273 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102),
1274 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103),
1275 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104),
1276 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105),
1277 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114),
1278 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128),
1279 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129),
1280 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135),
1281 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148),
1282 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152),
1283 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153),
1284 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164),
1285 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165),
1286 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166),
1287 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168),
1288 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 122, 171),
1292 /* FW Admin Queue command wrappers */
1294 /* Software lock/mutex that is meant to be held while the Global Config Lock
1295 * in firmware is acquired by the software to prevent most (but not all) types
1296 * of AQ commands from being sent to FW
1298 DEFINE_MUTEX(ice_global_cfg_lock_sw);
1301 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue
1302 * @hw: pointer to the HW struct
1303 * @desc: descriptor describing the command
1304 * @buf: buffer to use for indirect commands (NULL for direct commands)
1305 * @buf_size: size of buffer for indirect commands (0 for direct commands)
1306 * @cd: pointer to command details structure
1308 * Helper function to send FW Admin Queue commands to the FW Admin Queue.
1311 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf,
1312 u16 buf_size, struct ice_sq_cd *cd)
1314 struct ice_aqc_req_res *cmd = &desc->params.res_owner;
1315 bool lock_acquired = false;
1316 enum ice_status status;
1318 /* When a package download is in process (i.e. when the firmware's
1319 * Global Configuration Lock resource is held), only the Download
1320 * Package, Get Version, Get Package Info List and Release Resource
1321 * (with resource ID set to Global Config Lock) AdminQ commands are
1322 * allowed; all others must block until the package download completes
1323 * and the Global Config Lock is released. See also
1324 * ice_acquire_global_cfg_lock().
1326 switch (le16_to_cpu(desc->opcode)) {
1327 case ice_aqc_opc_download_pkg:
1328 case ice_aqc_opc_get_pkg_info_list:
1329 case ice_aqc_opc_get_ver:
1331 case ice_aqc_opc_release_res:
1332 if (le16_to_cpu(cmd->res_id) == ICE_AQC_RES_ID_GLBL_LOCK)
1336 mutex_lock(&ice_global_cfg_lock_sw);
1337 lock_acquired = true;
1341 status = ice_sq_send_cmd(hw, &hw->adminq, desc, buf, buf_size, cd);
1343 mutex_unlock(&ice_global_cfg_lock_sw);
1350 * @hw: pointer to the HW struct
1351 * @cd: pointer to command details structure or NULL
1353 * Get the firmware version (0x0001) from the admin queue commands
1355 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd)
1357 struct ice_aqc_get_ver *resp;
1358 struct ice_aq_desc desc;
1359 enum ice_status status;
1361 resp = &desc.params.get_ver;
1363 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver);
1365 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1368 hw->fw_branch = resp->fw_branch;
1369 hw->fw_maj_ver = resp->fw_major;
1370 hw->fw_min_ver = resp->fw_minor;
1371 hw->fw_patch = resp->fw_patch;
1372 hw->fw_build = le32_to_cpu(resp->fw_build);
1373 hw->api_branch = resp->api_branch;
1374 hw->api_maj_ver = resp->api_major;
1375 hw->api_min_ver = resp->api_minor;
1376 hw->api_patch = resp->api_patch;
1383 * ice_aq_send_driver_ver
1384 * @hw: pointer to the HW struct
1385 * @dv: driver's major, minor version
1386 * @cd: pointer to command details structure or NULL
1388 * Send the driver version (0x0002) to the firmware
1391 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv,
1392 struct ice_sq_cd *cd)
1394 struct ice_aqc_driver_ver *cmd;
1395 struct ice_aq_desc desc;
1398 cmd = &desc.params.driver_ver;
1401 return ICE_ERR_PARAM;
1403 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver);
1405 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
1406 cmd->major_ver = dv->major_ver;
1407 cmd->minor_ver = dv->minor_ver;
1408 cmd->build_ver = dv->build_ver;
1409 cmd->subbuild_ver = dv->subbuild_ver;
1412 while (len < sizeof(dv->driver_string) &&
1413 isascii(dv->driver_string[len]) && dv->driver_string[len])
1416 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd);
1421 * @hw: pointer to the HW struct
1422 * @unloading: is the driver unloading itself
1424 * Tell the Firmware that we're shutting down the AdminQ and whether
1425 * or not the driver is unloading as well (0x0003).
1427 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading)
1429 struct ice_aqc_q_shutdown *cmd;
1430 struct ice_aq_desc desc;
1432 cmd = &desc.params.q_shutdown;
1434 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown);
1437 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING;
1439 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1444 * @hw: pointer to the HW struct
1446 * @access: access type
1447 * @sdp_number: resource number
1448 * @timeout: the maximum time in ms that the driver may hold the resource
1449 * @cd: pointer to command details structure or NULL
1451 * Requests common resource using the admin queue commands (0x0008).
1452 * When attempting to acquire the Global Config Lock, the driver can
1453 * learn of three states:
1454 * 1) ICE_SUCCESS - acquired lock, and can perform download package
1455 * 2) ICE_ERR_AQ_ERROR - did not get lock, driver should fail to load
1456 * 3) ICE_ERR_AQ_NO_WORK - did not get lock, but another driver has
1457 * successfully downloaded the package; the driver does
1458 * not have to download the package and can continue
1461 * Note that if the caller is in an acquire lock, perform action, release lock
1462 * phase of operation, it is possible that the FW may detect a timeout and issue
1463 * a CORER. In this case, the driver will receive a CORER interrupt and will
1464 * have to determine its cause. The calling thread that is handling this flow
1465 * will likely get an error propagated back to it indicating the Download
1466 * Package, Update Package or the Release Resource AQ commands timed out.
1468 static enum ice_status
1469 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1470 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout,
1471 struct ice_sq_cd *cd)
1473 struct ice_aqc_req_res *cmd_resp;
1474 struct ice_aq_desc desc;
1475 enum ice_status status;
1477 cmd_resp = &desc.params.res_owner;
1479 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res);
1481 cmd_resp->res_id = cpu_to_le16(res);
1482 cmd_resp->access_type = cpu_to_le16(access);
1483 cmd_resp->res_number = cpu_to_le32(sdp_number);
1484 cmd_resp->timeout = cpu_to_le32(*timeout);
1487 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1489 /* The completion specifies the maximum time in ms that the driver
1490 * may hold the resource in the Timeout field.
1493 /* Global config lock response utilizes an additional status field.
1495 * If the Global config lock resource is held by some other driver, the
1496 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field
1497 * and the timeout field indicates the maximum time the current owner
1498 * of the resource has to free it.
1500 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) {
1501 if (le16_to_cpu(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) {
1502 *timeout = le32_to_cpu(cmd_resp->timeout);
1504 } else if (le16_to_cpu(cmd_resp->status) ==
1505 ICE_AQ_RES_GLBL_IN_PROG) {
1506 *timeout = le32_to_cpu(cmd_resp->timeout);
1507 return ICE_ERR_AQ_ERROR;
1508 } else if (le16_to_cpu(cmd_resp->status) ==
1509 ICE_AQ_RES_GLBL_DONE) {
1510 return ICE_ERR_AQ_NO_WORK;
1513 /* invalid FW response, force a timeout immediately */
1515 return ICE_ERR_AQ_ERROR;
1518 /* If the resource is held by some other driver, the command completes
1519 * with a busy return value and the timeout field indicates the maximum
1520 * time the current owner of the resource has to free it.
1522 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY)
1523 *timeout = le32_to_cpu(cmd_resp->timeout);
1529 * ice_aq_release_res
1530 * @hw: pointer to the HW struct
1532 * @sdp_number: resource number
1533 * @cd: pointer to command details structure or NULL
1535 * release common resource using the admin queue commands (0x0009)
1537 static enum ice_status
1538 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number,
1539 struct ice_sq_cd *cd)
1541 struct ice_aqc_req_res *cmd;
1542 struct ice_aq_desc desc;
1544 cmd = &desc.params.res_owner;
1546 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res);
1548 cmd->res_id = cpu_to_le16(res);
1549 cmd->res_number = cpu_to_le32(sdp_number);
1551 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1556 * @hw: pointer to the HW structure
1558 * @access: access type (read or write)
1559 * @timeout: timeout in milliseconds
1561 * This function will attempt to acquire the ownership of a resource.
1564 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1565 enum ice_aq_res_access_type access, u32 timeout)
1567 #define ICE_RES_POLLING_DELAY_MS 10
1568 u32 delay = ICE_RES_POLLING_DELAY_MS;
1569 u32 time_left = timeout;
1570 enum ice_status status;
1572 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1574 /* A return code of ICE_ERR_AQ_NO_WORK means that another driver has
1575 * previously acquired the resource and performed any necessary updates;
1576 * in this case the caller does not obtain the resource and has no
1577 * further work to do.
1579 if (status == ICE_ERR_AQ_NO_WORK)
1580 goto ice_acquire_res_exit;
1583 ice_debug(hw, ICE_DBG_RES,
1584 "resource %d acquire type %d failed.\n", res, access);
1586 /* If necessary, poll until the current lock owner timeouts */
1587 timeout = time_left;
1588 while (status && timeout && time_left) {
1590 timeout = (timeout > delay) ? timeout - delay : 0;
1591 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1593 if (status == ICE_ERR_AQ_NO_WORK)
1594 /* lock free, but no work to do */
1601 if (status && status != ICE_ERR_AQ_NO_WORK)
1602 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n");
1604 ice_acquire_res_exit:
1605 if (status == ICE_ERR_AQ_NO_WORK) {
1606 if (access == ICE_RES_WRITE)
1607 ice_debug(hw, ICE_DBG_RES,
1608 "resource indicates no work to do.\n");
1610 ice_debug(hw, ICE_DBG_RES,
1611 "Warning: ICE_ERR_AQ_NO_WORK not expected\n");
1618 * @hw: pointer to the HW structure
1621 * This function will release a resource using the proper Admin Command.
1623 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res)
1625 enum ice_status status;
1626 u32 total_delay = 0;
1628 status = ice_aq_release_res(hw, res, 0, NULL);
1630 /* there are some rare cases when trying to release the resource
1631 * results in an admin queue timeout, so handle them correctly
1633 while ((status == ICE_ERR_AQ_TIMEOUT) &&
1634 (total_delay < hw->adminq.sq_cmd_timeout)) {
1636 status = ice_aq_release_res(hw, res, 0, NULL);
1642 * ice_aq_alloc_free_res - command to allocate/free resources
1643 * @hw: pointer to the HW struct
1644 * @num_entries: number of resource entries in buffer
1645 * @buf: Indirect buffer to hold data parameters and response
1646 * @buf_size: size of buffer for indirect commands
1647 * @opc: pass in the command opcode
1648 * @cd: pointer to command details structure or NULL
1650 * Helper function to allocate/free resources using the admin queue commands
1653 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries,
1654 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size,
1655 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
1657 struct ice_aqc_alloc_free_res_cmd *cmd;
1658 struct ice_aq_desc desc;
1660 cmd = &desc.params.sw_res_ctrl;
1663 return ICE_ERR_PARAM;
1665 if (buf_size < (num_entries * sizeof(buf->elem[0])))
1666 return ICE_ERR_PARAM;
1668 ice_fill_dflt_direct_cmd_desc(&desc, opc);
1670 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
1672 cmd->num_entries = cpu_to_le16(num_entries);
1674 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
1678 * ice_alloc_hw_res - allocate resource
1679 * @hw: pointer to the HW struct
1680 * @type: type of resource
1681 * @num: number of resources to allocate
1682 * @btm: allocate from bottom
1683 * @res: pointer to array that will receive the resources
1686 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res)
1688 struct ice_aqc_alloc_free_res_elem *buf;
1689 enum ice_status status;
1692 buf_len = struct_size(buf, elem, num);
1693 buf = kzalloc(buf_len, GFP_KERNEL);
1695 return ICE_ERR_NO_MEMORY;
1697 /* Prepare buffer to allocate resource. */
1698 buf->num_elems = cpu_to_le16(num);
1699 buf->res_type = cpu_to_le16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED |
1700 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX);
1702 buf->res_type |= cpu_to_le16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM);
1704 status = ice_aq_alloc_free_res(hw, 1, buf, buf_len,
1705 ice_aqc_opc_alloc_res, NULL);
1707 goto ice_alloc_res_exit;
1709 memcpy(res, buf->elem, sizeof(*buf->elem) * num);
1717 * ice_free_hw_res - free allocated HW resource
1718 * @hw: pointer to the HW struct
1719 * @type: type of resource to free
1720 * @num: number of resources
1721 * @res: pointer to array that contains the resources to free
1724 ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res)
1726 struct ice_aqc_alloc_free_res_elem *buf;
1727 enum ice_status status;
1730 buf_len = struct_size(buf, elem, num);
1731 buf = kzalloc(buf_len, GFP_KERNEL);
1733 return ICE_ERR_NO_MEMORY;
1735 /* Prepare buffer to free resource. */
1736 buf->num_elems = cpu_to_le16(num);
1737 buf->res_type = cpu_to_le16(type);
1738 memcpy(buf->elem, res, sizeof(*buf->elem) * num);
1740 status = ice_aq_alloc_free_res(hw, num, buf, buf_len,
1741 ice_aqc_opc_free_res, NULL);
1743 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n");
1750 * ice_get_num_per_func - determine number of resources per PF
1751 * @hw: pointer to the HW structure
1752 * @max: value to be evenly split between each PF
1754 * Determine the number of valid functions by going through the bitmap returned
1755 * from parsing capabilities and use this to calculate the number of resources
1756 * per PF based on the max value passed in.
1758 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max)
1762 #define ICE_CAPS_VALID_FUNCS_M 0xFF
1763 funcs = hweight8(hw->dev_caps.common_cap.valid_functions &
1764 ICE_CAPS_VALID_FUNCS_M);
1773 * ice_parse_common_caps - parse common device/function capabilities
1774 * @hw: pointer to the HW struct
1775 * @caps: pointer to common capabilities structure
1776 * @elem: the capability element to parse
1777 * @prefix: message prefix for tracing capabilities
1779 * Given a capability element, extract relevant details into the common
1780 * capability structure.
1782 * Returns: true if the capability matches one of the common capability ids,
1786 ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps,
1787 struct ice_aqc_list_caps_elem *elem, const char *prefix)
1789 u32 logical_id = le32_to_cpu(elem->logical_id);
1790 u32 phys_id = le32_to_cpu(elem->phys_id);
1791 u32 number = le32_to_cpu(elem->number);
1792 u16 cap = le16_to_cpu(elem->cap);
1796 case ICE_AQC_CAPS_VALID_FUNCTIONS:
1797 caps->valid_functions = number;
1798 ice_debug(hw, ICE_DBG_INIT,
1799 "%s: valid_functions (bitmap) = %d\n", prefix,
1800 caps->valid_functions);
1802 case ICE_AQC_CAPS_SRIOV:
1803 caps->sr_iov_1_1 = (number == 1);
1804 ice_debug(hw, ICE_DBG_INIT,
1805 "%s: sr_iov_1_1 = %d\n", prefix,
1808 case ICE_AQC_CAPS_DCB:
1809 caps->dcb = (number == 1);
1810 caps->active_tc_bitmap = logical_id;
1811 caps->maxtc = phys_id;
1812 ice_debug(hw, ICE_DBG_INIT,
1813 "%s: dcb = %d\n", prefix, caps->dcb);
1814 ice_debug(hw, ICE_DBG_INIT,
1815 "%s: active_tc_bitmap = %d\n", prefix,
1816 caps->active_tc_bitmap);
1817 ice_debug(hw, ICE_DBG_INIT,
1818 "%s: maxtc = %d\n", prefix, caps->maxtc);
1820 case ICE_AQC_CAPS_RSS:
1821 caps->rss_table_size = number;
1822 caps->rss_table_entry_width = logical_id;
1823 ice_debug(hw, ICE_DBG_INIT,
1824 "%s: rss_table_size = %d\n", prefix,
1825 caps->rss_table_size);
1826 ice_debug(hw, ICE_DBG_INIT,
1827 "%s: rss_table_entry_width = %d\n", prefix,
1828 caps->rss_table_entry_width);
1830 case ICE_AQC_CAPS_RXQS:
1831 caps->num_rxq = number;
1832 caps->rxq_first_id = phys_id;
1833 ice_debug(hw, ICE_DBG_INIT,
1834 "%s: num_rxq = %d\n", prefix,
1836 ice_debug(hw, ICE_DBG_INIT,
1837 "%s: rxq_first_id = %d\n", prefix,
1838 caps->rxq_first_id);
1840 case ICE_AQC_CAPS_TXQS:
1841 caps->num_txq = number;
1842 caps->txq_first_id = phys_id;
1843 ice_debug(hw, ICE_DBG_INIT,
1844 "%s: num_txq = %d\n", prefix,
1846 ice_debug(hw, ICE_DBG_INIT,
1847 "%s: txq_first_id = %d\n", prefix,
1848 caps->txq_first_id);
1850 case ICE_AQC_CAPS_MSIX:
1851 caps->num_msix_vectors = number;
1852 caps->msix_vector_first_id = phys_id;
1853 ice_debug(hw, ICE_DBG_INIT,
1854 "%s: num_msix_vectors = %d\n", prefix,
1855 caps->num_msix_vectors);
1856 ice_debug(hw, ICE_DBG_INIT,
1857 "%s: msix_vector_first_id = %d\n", prefix,
1858 caps->msix_vector_first_id);
1860 case ICE_AQC_CAPS_PENDING_NVM_VER:
1861 caps->nvm_update_pending_nvm = true;
1862 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_nvm\n", prefix);
1864 case ICE_AQC_CAPS_PENDING_OROM_VER:
1865 caps->nvm_update_pending_orom = true;
1866 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_orom\n", prefix);
1868 case ICE_AQC_CAPS_PENDING_NET_VER:
1869 caps->nvm_update_pending_netlist = true;
1870 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_netlist\n", prefix);
1872 case ICE_AQC_CAPS_NVM_MGMT:
1873 caps->nvm_unified_update =
1874 (number & ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ?
1876 ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix,
1877 caps->nvm_unified_update);
1879 case ICE_AQC_CAPS_MAX_MTU:
1880 caps->max_mtu = number;
1881 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n",
1882 prefix, caps->max_mtu);
1885 /* Not one of the recognized common capabilities */
1893 * ice_recalc_port_limited_caps - Recalculate port limited capabilities
1894 * @hw: pointer to the HW structure
1895 * @caps: pointer to capabilities structure to fix
1897 * Re-calculate the capabilities that are dependent on the number of physical
1898 * ports; i.e. some features are not supported or function differently on
1899 * devices with more than 4 ports.
1902 ice_recalc_port_limited_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps)
1904 /* This assumes device capabilities are always scanned before function
1905 * capabilities during the initialization flow.
1907 if (hw->dev_caps.num_funcs > 4) {
1908 /* Max 4 TCs per port */
1910 ice_debug(hw, ICE_DBG_INIT,
1911 "reducing maxtc to %d (based on #ports)\n",
1917 * ice_parse_vf_func_caps - Parse ICE_AQC_CAPS_VF function caps
1918 * @hw: pointer to the HW struct
1919 * @func_p: pointer to function capabilities structure
1920 * @cap: pointer to the capability element to parse
1922 * Extract function capabilities for ICE_AQC_CAPS_VF.
1925 ice_parse_vf_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
1926 struct ice_aqc_list_caps_elem *cap)
1928 u32 logical_id = le32_to_cpu(cap->logical_id);
1929 u32 number = le32_to_cpu(cap->number);
1931 func_p->num_allocd_vfs = number;
1932 func_p->vf_base_id = logical_id;
1933 ice_debug(hw, ICE_DBG_INIT, "func caps: num_allocd_vfs = %d\n",
1934 func_p->num_allocd_vfs);
1935 ice_debug(hw, ICE_DBG_INIT, "func caps: vf_base_id = %d\n",
1936 func_p->vf_base_id);
1940 * ice_parse_vsi_func_caps - Parse ICE_AQC_CAPS_VSI function caps
1941 * @hw: pointer to the HW struct
1942 * @func_p: pointer to function capabilities structure
1943 * @cap: pointer to the capability element to parse
1945 * Extract function capabilities for ICE_AQC_CAPS_VSI.
1948 ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
1949 struct ice_aqc_list_caps_elem *cap)
1951 func_p->guar_num_vsi = ice_get_num_per_func(hw, ICE_MAX_VSI);
1952 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi (fw) = %d\n",
1953 le32_to_cpu(cap->number));
1954 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi = %d\n",
1955 func_p->guar_num_vsi);
1959 * ice_parse_fdir_func_caps - Parse ICE_AQC_CAPS_FD function caps
1960 * @hw: pointer to the HW struct
1961 * @func_p: pointer to function capabilities structure
1963 * Extract function capabilities for ICE_AQC_CAPS_FD.
1966 ice_parse_fdir_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p)
1970 reg_val = rd32(hw, GLQF_FD_SIZE);
1971 val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >>
1972 GLQF_FD_SIZE_FD_GSIZE_S;
1973 func_p->fd_fltr_guar =
1974 ice_get_num_per_func(hw, val);
1975 val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >>
1976 GLQF_FD_SIZE_FD_BSIZE_S;
1977 func_p->fd_fltr_best_effort = val;
1979 ice_debug(hw, ICE_DBG_INIT,
1980 "func caps: fd_fltr_guar = %d\n",
1981 func_p->fd_fltr_guar);
1982 ice_debug(hw, ICE_DBG_INIT,
1983 "func caps: fd_fltr_best_effort = %d\n",
1984 func_p->fd_fltr_best_effort);
1988 * ice_parse_func_caps - Parse function capabilities
1989 * @hw: pointer to the HW struct
1990 * @func_p: pointer to function capabilities structure
1991 * @buf: buffer containing the function capability records
1992 * @cap_count: the number of capabilities
1994 * Helper function to parse function (0x000A) capabilities list. For
1995 * capabilities shared between device and function, this relies on
1996 * ice_parse_common_caps.
1998 * Loop through the list of provided capabilities and extract the relevant
1999 * data into the function capabilities structured.
2002 ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
2003 void *buf, u32 cap_count)
2005 struct ice_aqc_list_caps_elem *cap_resp;
2008 cap_resp = (struct ice_aqc_list_caps_elem *)buf;
2010 memset(func_p, 0, sizeof(*func_p));
2012 for (i = 0; i < cap_count; i++) {
2013 u16 cap = le16_to_cpu(cap_resp[i].cap);
2016 found = ice_parse_common_caps(hw, &func_p->common_cap,
2017 &cap_resp[i], "func caps");
2020 case ICE_AQC_CAPS_VF:
2021 ice_parse_vf_func_caps(hw, func_p, &cap_resp[i]);
2023 case ICE_AQC_CAPS_VSI:
2024 ice_parse_vsi_func_caps(hw, func_p, &cap_resp[i]);
2026 case ICE_AQC_CAPS_FD:
2027 ice_parse_fdir_func_caps(hw, func_p);
2030 /* Don't list common capabilities as unknown */
2032 ice_debug(hw, ICE_DBG_INIT,
2033 "func caps: unknown capability[%d]: 0x%x\n",
2039 ice_recalc_port_limited_caps(hw, &func_p->common_cap);
2043 * ice_parse_valid_functions_cap - Parse ICE_AQC_CAPS_VALID_FUNCTIONS caps
2044 * @hw: pointer to the HW struct
2045 * @dev_p: pointer to device capabilities structure
2046 * @cap: capability element to parse
2048 * Parse ICE_AQC_CAPS_VALID_FUNCTIONS for device capabilities.
2051 ice_parse_valid_functions_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2052 struct ice_aqc_list_caps_elem *cap)
2054 u32 number = le32_to_cpu(cap->number);
2056 dev_p->num_funcs = hweight32(number);
2057 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_funcs = %d\n",
2062 * ice_parse_vf_dev_caps - Parse ICE_AQC_CAPS_VF device caps
2063 * @hw: pointer to the HW struct
2064 * @dev_p: pointer to device capabilities structure
2065 * @cap: capability element to parse
2067 * Parse ICE_AQC_CAPS_VF for device capabilities.
2070 ice_parse_vf_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2071 struct ice_aqc_list_caps_elem *cap)
2073 u32 number = le32_to_cpu(cap->number);
2075 dev_p->num_vfs_exposed = number;
2076 ice_debug(hw, ICE_DBG_INIT, "dev_caps: num_vfs_exposed = %d\n",
2077 dev_p->num_vfs_exposed);
2081 * ice_parse_vsi_dev_caps - Parse ICE_AQC_CAPS_VSI device caps
2082 * @hw: pointer to the HW struct
2083 * @dev_p: pointer to device capabilities structure
2084 * @cap: capability element to parse
2086 * Parse ICE_AQC_CAPS_VSI for device capabilities.
2089 ice_parse_vsi_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2090 struct ice_aqc_list_caps_elem *cap)
2092 u32 number = le32_to_cpu(cap->number);
2094 dev_p->num_vsi_allocd_to_host = number;
2095 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_vsi_allocd_to_host = %d\n",
2096 dev_p->num_vsi_allocd_to_host);
2100 * ice_parse_fdir_dev_caps - Parse ICE_AQC_CAPS_FD device caps
2101 * @hw: pointer to the HW struct
2102 * @dev_p: pointer to device capabilities structure
2103 * @cap: capability element to parse
2105 * Parse ICE_AQC_CAPS_FD for device capabilities.
2108 ice_parse_fdir_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2109 struct ice_aqc_list_caps_elem *cap)
2111 u32 number = le32_to_cpu(cap->number);
2113 dev_p->num_flow_director_fltr = number;
2114 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_flow_director_fltr = %d\n",
2115 dev_p->num_flow_director_fltr);
2119 * ice_parse_dev_caps - Parse device capabilities
2120 * @hw: pointer to the HW struct
2121 * @dev_p: pointer to device capabilities structure
2122 * @buf: buffer containing the device capability records
2123 * @cap_count: the number of capabilities
2125 * Helper device to parse device (0x000B) capabilities list. For
2126 * capabilities shared between device and device, this relies on
2127 * ice_parse_common_caps.
2129 * Loop through the list of provided capabilities and extract the relevant
2130 * data into the device capabilities structured.
2133 ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2134 void *buf, u32 cap_count)
2136 struct ice_aqc_list_caps_elem *cap_resp;
2139 cap_resp = (struct ice_aqc_list_caps_elem *)buf;
2141 memset(dev_p, 0, sizeof(*dev_p));
2143 for (i = 0; i < cap_count; i++) {
2144 u16 cap = le16_to_cpu(cap_resp[i].cap);
2147 found = ice_parse_common_caps(hw, &dev_p->common_cap,
2148 &cap_resp[i], "dev caps");
2151 case ICE_AQC_CAPS_VALID_FUNCTIONS:
2152 ice_parse_valid_functions_cap(hw, dev_p, &cap_resp[i]);
2154 case ICE_AQC_CAPS_VF:
2155 ice_parse_vf_dev_caps(hw, dev_p, &cap_resp[i]);
2157 case ICE_AQC_CAPS_VSI:
2158 ice_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]);
2160 case ICE_AQC_CAPS_FD:
2161 ice_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]);
2164 /* Don't list common capabilities as unknown */
2166 ice_debug(hw, ICE_DBG_INIT,
2167 "dev caps: unknown capability[%d]: 0x%x\n",
2173 ice_recalc_port_limited_caps(hw, &dev_p->common_cap);
2177 * ice_aq_list_caps - query function/device capabilities
2178 * @hw: pointer to the HW struct
2179 * @buf: a buffer to hold the capabilities
2180 * @buf_size: size of the buffer
2181 * @cap_count: if not NULL, set to the number of capabilities reported
2182 * @opc: capabilities type to discover, device or function
2183 * @cd: pointer to command details structure or NULL
2185 * Get the function (0x000A) or device (0x000B) capabilities description from
2186 * firmware and store it in the buffer.
2188 * If the cap_count pointer is not NULL, then it is set to the number of
2189 * capabilities firmware will report. Note that if the buffer size is too
2190 * small, it is possible the command will return ICE_AQ_ERR_ENOMEM. The
2191 * cap_count will still be updated in this case. It is recommended that the
2192 * buffer size be set to ICE_AQ_MAX_BUF_LEN (the largest possible buffer that
2193 * firmware could return) to avoid this.
2196 ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count,
2197 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
2199 struct ice_aqc_list_caps *cmd;
2200 struct ice_aq_desc desc;
2201 enum ice_status status;
2203 cmd = &desc.params.get_cap;
2205 if (opc != ice_aqc_opc_list_func_caps &&
2206 opc != ice_aqc_opc_list_dev_caps)
2207 return ICE_ERR_PARAM;
2209 ice_fill_dflt_direct_cmd_desc(&desc, opc);
2210 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
2213 *cap_count = le32_to_cpu(cmd->count);
2219 * ice_discover_dev_caps - Read and extract device capabilities
2220 * @hw: pointer to the hardware structure
2221 * @dev_caps: pointer to device capabilities structure
2223 * Read the device capabilities and extract them into the dev_caps structure
2226 static enum ice_status
2227 ice_discover_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_caps)
2229 enum ice_status status;
2233 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL);
2235 return ICE_ERR_NO_MEMORY;
2237 /* Although the driver doesn't know the number of capabilities the
2238 * device will return, we can simply send a 4KB buffer, the maximum
2239 * possible size that firmware can return.
2241 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem);
2243 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count,
2244 ice_aqc_opc_list_dev_caps, NULL);
2246 ice_parse_dev_caps(hw, dev_caps, cbuf, cap_count);
2253 * ice_discover_func_caps - Read and extract function capabilities
2254 * @hw: pointer to the hardware structure
2255 * @func_caps: pointer to function capabilities structure
2257 * Read the function capabilities and extract them into the func_caps structure
2260 static enum ice_status
2261 ice_discover_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_caps)
2263 enum ice_status status;
2267 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL);
2269 return ICE_ERR_NO_MEMORY;
2271 /* Although the driver doesn't know the number of capabilities the
2272 * device will return, we can simply send a 4KB buffer, the maximum
2273 * possible size that firmware can return.
2275 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem);
2277 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count,
2278 ice_aqc_opc_list_func_caps, NULL);
2280 ice_parse_func_caps(hw, func_caps, cbuf, cap_count);
2287 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode
2288 * @hw: pointer to the hardware structure
2290 void ice_set_safe_mode_caps(struct ice_hw *hw)
2292 struct ice_hw_func_caps *func_caps = &hw->func_caps;
2293 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps;
2294 u32 valid_func, rxq_first_id, txq_first_id;
2295 u32 msix_vector_first_id, max_mtu;
2298 /* cache some func_caps values that should be restored after memset */
2299 valid_func = func_caps->common_cap.valid_functions;
2300 txq_first_id = func_caps->common_cap.txq_first_id;
2301 rxq_first_id = func_caps->common_cap.rxq_first_id;
2302 msix_vector_first_id = func_caps->common_cap.msix_vector_first_id;
2303 max_mtu = func_caps->common_cap.max_mtu;
2305 /* unset func capabilities */
2306 memset(func_caps, 0, sizeof(*func_caps));
2308 /* restore cached values */
2309 func_caps->common_cap.valid_functions = valid_func;
2310 func_caps->common_cap.txq_first_id = txq_first_id;
2311 func_caps->common_cap.rxq_first_id = rxq_first_id;
2312 func_caps->common_cap.msix_vector_first_id = msix_vector_first_id;
2313 func_caps->common_cap.max_mtu = max_mtu;
2315 /* one Tx and one Rx queue in safe mode */
2316 func_caps->common_cap.num_rxq = 1;
2317 func_caps->common_cap.num_txq = 1;
2319 /* two MSIX vectors, one for traffic and one for misc causes */
2320 func_caps->common_cap.num_msix_vectors = 2;
2321 func_caps->guar_num_vsi = 1;
2323 /* cache some dev_caps values that should be restored after memset */
2324 valid_func = dev_caps->common_cap.valid_functions;
2325 txq_first_id = dev_caps->common_cap.txq_first_id;
2326 rxq_first_id = dev_caps->common_cap.rxq_first_id;
2327 msix_vector_first_id = dev_caps->common_cap.msix_vector_first_id;
2328 max_mtu = dev_caps->common_cap.max_mtu;
2329 num_funcs = dev_caps->num_funcs;
2331 /* unset dev capabilities */
2332 memset(dev_caps, 0, sizeof(*dev_caps));
2334 /* restore cached values */
2335 dev_caps->common_cap.valid_functions = valid_func;
2336 dev_caps->common_cap.txq_first_id = txq_first_id;
2337 dev_caps->common_cap.rxq_first_id = rxq_first_id;
2338 dev_caps->common_cap.msix_vector_first_id = msix_vector_first_id;
2339 dev_caps->common_cap.max_mtu = max_mtu;
2340 dev_caps->num_funcs = num_funcs;
2342 /* one Tx and one Rx queue per function in safe mode */
2343 dev_caps->common_cap.num_rxq = num_funcs;
2344 dev_caps->common_cap.num_txq = num_funcs;
2346 /* two MSIX vectors per function */
2347 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs;
2351 * ice_get_caps - get info about the HW
2352 * @hw: pointer to the hardware structure
2354 enum ice_status ice_get_caps(struct ice_hw *hw)
2356 enum ice_status status;
2358 status = ice_discover_dev_caps(hw, &hw->dev_caps);
2362 return ice_discover_func_caps(hw, &hw->func_caps);
2366 * ice_aq_manage_mac_write - manage MAC address write command
2367 * @hw: pointer to the HW struct
2368 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address
2369 * @flags: flags to control write behavior
2370 * @cd: pointer to command details structure or NULL
2372 * This function is used to write MAC address to the NVM (0x0108).
2375 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,
2376 struct ice_sq_cd *cd)
2378 struct ice_aqc_manage_mac_write *cmd;
2379 struct ice_aq_desc desc;
2381 cmd = &desc.params.mac_write;
2382 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write);
2385 ether_addr_copy(cmd->mac_addr, mac_addr);
2387 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2391 * ice_aq_clear_pxe_mode
2392 * @hw: pointer to the HW struct
2394 * Tell the firmware that the driver is taking over from PXE (0x0110).
2396 static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw)
2398 struct ice_aq_desc desc;
2400 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode);
2401 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT;
2403 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
2407 * ice_clear_pxe_mode - clear pxe operations mode
2408 * @hw: pointer to the HW struct
2410 * Make sure all PXE mode settings are cleared, including things
2411 * like descriptor fetch/write-back mode.
2413 void ice_clear_pxe_mode(struct ice_hw *hw)
2415 if (ice_check_sq_alive(hw, &hw->adminq))
2416 ice_aq_clear_pxe_mode(hw);
2420 * ice_get_link_speed_based_on_phy_type - returns link speed
2421 * @phy_type_low: lower part of phy_type
2422 * @phy_type_high: higher part of phy_type
2424 * This helper function will convert an entry in PHY type structure
2425 * [phy_type_low, phy_type_high] to its corresponding link speed.
2426 * Note: In the structure of [phy_type_low, phy_type_high], there should
2427 * be one bit set, as this function will convert one PHY type to its
2429 * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
2430 * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
2433 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high)
2435 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
2436 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
2438 switch (phy_type_low) {
2439 case ICE_PHY_TYPE_LOW_100BASE_TX:
2440 case ICE_PHY_TYPE_LOW_100M_SGMII:
2441 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB;
2443 case ICE_PHY_TYPE_LOW_1000BASE_T:
2444 case ICE_PHY_TYPE_LOW_1000BASE_SX:
2445 case ICE_PHY_TYPE_LOW_1000BASE_LX:
2446 case ICE_PHY_TYPE_LOW_1000BASE_KX:
2447 case ICE_PHY_TYPE_LOW_1G_SGMII:
2448 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB;
2450 case ICE_PHY_TYPE_LOW_2500BASE_T:
2451 case ICE_PHY_TYPE_LOW_2500BASE_X:
2452 case ICE_PHY_TYPE_LOW_2500BASE_KX:
2453 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB;
2455 case ICE_PHY_TYPE_LOW_5GBASE_T:
2456 case ICE_PHY_TYPE_LOW_5GBASE_KR:
2457 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB;
2459 case ICE_PHY_TYPE_LOW_10GBASE_T:
2460 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
2461 case ICE_PHY_TYPE_LOW_10GBASE_SR:
2462 case ICE_PHY_TYPE_LOW_10GBASE_LR:
2463 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
2464 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC:
2465 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
2466 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB;
2468 case ICE_PHY_TYPE_LOW_25GBASE_T:
2469 case ICE_PHY_TYPE_LOW_25GBASE_CR:
2470 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
2471 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
2472 case ICE_PHY_TYPE_LOW_25GBASE_SR:
2473 case ICE_PHY_TYPE_LOW_25GBASE_LR:
2474 case ICE_PHY_TYPE_LOW_25GBASE_KR:
2475 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
2476 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
2477 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC:
2478 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
2479 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB;
2481 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
2482 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
2483 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
2484 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
2485 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC:
2486 case ICE_PHY_TYPE_LOW_40G_XLAUI:
2487 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB;
2489 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
2490 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
2491 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
2492 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
2493 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC:
2494 case ICE_PHY_TYPE_LOW_50G_LAUI2:
2495 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC:
2496 case ICE_PHY_TYPE_LOW_50G_AUI2:
2497 case ICE_PHY_TYPE_LOW_50GBASE_CP:
2498 case ICE_PHY_TYPE_LOW_50GBASE_SR:
2499 case ICE_PHY_TYPE_LOW_50GBASE_FR:
2500 case ICE_PHY_TYPE_LOW_50GBASE_LR:
2501 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
2502 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:
2503 case ICE_PHY_TYPE_LOW_50G_AUI1:
2504 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB;
2506 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
2507 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
2508 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
2509 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
2510 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC:
2511 case ICE_PHY_TYPE_LOW_100G_CAUI4:
2512 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC:
2513 case ICE_PHY_TYPE_LOW_100G_AUI4:
2514 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
2515 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
2516 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
2517 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
2518 case ICE_PHY_TYPE_LOW_100GBASE_DR:
2519 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB;
2522 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
2526 switch (phy_type_high) {
2527 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
2528 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC:
2529 case ICE_PHY_TYPE_HIGH_100G_CAUI2:
2530 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC:
2531 case ICE_PHY_TYPE_HIGH_100G_AUI2:
2532 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB;
2535 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
2539 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN &&
2540 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
2541 return ICE_AQ_LINK_SPEED_UNKNOWN;
2542 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
2543 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN)
2544 return ICE_AQ_LINK_SPEED_UNKNOWN;
2545 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
2546 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
2547 return speed_phy_type_low;
2549 return speed_phy_type_high;
2553 * ice_update_phy_type
2554 * @phy_type_low: pointer to the lower part of phy_type
2555 * @phy_type_high: pointer to the higher part of phy_type
2556 * @link_speeds_bitmap: targeted link speeds bitmap
2558 * Note: For the link_speeds_bitmap structure, you can check it at
2559 * [ice_aqc_get_link_status->link_speed]. Caller can pass in
2560 * link_speeds_bitmap include multiple speeds.
2562 * Each entry in this [phy_type_low, phy_type_high] structure will
2563 * present a certain link speed. This helper function will turn on bits
2564 * in [phy_type_low, phy_type_high] structure based on the value of
2565 * link_speeds_bitmap input parameter.
2568 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high,
2569 u16 link_speeds_bitmap)
2576 /* We first check with low part of phy_type */
2577 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) {
2578 pt_low = BIT_ULL(index);
2579 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0);
2581 if (link_speeds_bitmap & speed)
2582 *phy_type_low |= BIT_ULL(index);
2585 /* We then check with high part of phy_type */
2586 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) {
2587 pt_high = BIT_ULL(index);
2588 speed = ice_get_link_speed_based_on_phy_type(0, pt_high);
2590 if (link_speeds_bitmap & speed)
2591 *phy_type_high |= BIT_ULL(index);
2596 * ice_aq_set_phy_cfg
2597 * @hw: pointer to the HW struct
2598 * @pi: port info structure of the interested logical port
2599 * @cfg: structure with PHY configuration data to be set
2600 * @cd: pointer to command details structure or NULL
2602 * Set the various PHY configuration parameters supported on the Port.
2603 * One or more of the Set PHY config parameters may be ignored in an MFP
2604 * mode as the PF may not have the privilege to set some of the PHY Config
2605 * parameters. This status will be indicated by the command response (0x0601).
2608 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi,
2609 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd)
2611 struct ice_aq_desc desc;
2612 enum ice_status status;
2615 return ICE_ERR_PARAM;
2617 /* Ensure that only valid bits of cfg->caps can be turned on. */
2618 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) {
2619 ice_debug(hw, ICE_DBG_PHY,
2620 "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n",
2623 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK;
2626 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg);
2627 desc.params.set_phy.lport_num = pi->lport;
2628 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
2630 ice_debug(hw, ICE_DBG_LINK, "set phy cfg\n");
2631 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n",
2632 (unsigned long long)le64_to_cpu(cfg->phy_type_low));
2633 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n",
2634 (unsigned long long)le64_to_cpu(cfg->phy_type_high));
2635 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", cfg->caps);
2636 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n",
2637 cfg->low_power_ctrl_an);
2638 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", cfg->eee_cap);
2639 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", cfg->eeer_value);
2640 ice_debug(hw, ICE_DBG_LINK, " link_fec_opt = 0x%x\n",
2643 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd);
2644 if (hw->adminq.sq_last_status == ICE_AQ_RC_EMODE)
2648 pi->phy.curr_user_phy_cfg = *cfg;
2654 * ice_update_link_info - update status of the HW network link
2655 * @pi: port info structure of the interested logical port
2657 enum ice_status ice_update_link_info(struct ice_port_info *pi)
2659 struct ice_link_status *li;
2660 enum ice_status status;
2663 return ICE_ERR_PARAM;
2665 li = &pi->phy.link_info;
2667 status = ice_aq_get_link_info(pi, true, NULL, NULL);
2671 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) {
2672 struct ice_aqc_get_phy_caps_data *pcaps;
2676 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps),
2679 return ICE_ERR_NO_MEMORY;
2681 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP,
2684 devm_kfree(ice_hw_to_dev(hw), pcaps);
2691 * ice_cache_phy_user_req
2692 * @pi: port information structure
2693 * @cache_data: PHY logging data
2694 * @cache_mode: PHY logging mode
2696 * Log the user request on (FC, FEC, SPEED) for later use.
2699 ice_cache_phy_user_req(struct ice_port_info *pi,
2700 struct ice_phy_cache_mode_data cache_data,
2701 enum ice_phy_cache_mode cache_mode)
2706 switch (cache_mode) {
2708 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req;
2710 case ICE_SPEED_MODE:
2711 pi->phy.curr_user_speed_req =
2712 cache_data.data.curr_user_speed_req;
2715 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req;
2723 * ice_caps_to_fc_mode
2724 * @caps: PHY capabilities
2726 * Convert PHY FC capabilities to ice FC mode
2728 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps)
2730 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE &&
2731 caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
2734 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE)
2735 return ICE_FC_TX_PAUSE;
2737 if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
2738 return ICE_FC_RX_PAUSE;
2744 * ice_caps_to_fec_mode
2745 * @caps: PHY capabilities
2746 * @fec_options: Link FEC options
2748 * Convert PHY FEC capabilities to ice FEC mode
2750 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options)
2752 if (caps & ICE_AQC_PHY_EN_AUTO_FEC)
2753 return ICE_FEC_AUTO;
2755 if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
2756 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
2757 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN |
2758 ICE_AQC_PHY_FEC_25G_KR_REQ))
2759 return ICE_FEC_BASER;
2761 if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ |
2762 ICE_AQC_PHY_FEC_25G_RS_544_REQ |
2763 ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN))
2766 return ICE_FEC_NONE;
2770 * ice_cfg_phy_fc - Configure PHY FC data based on FC mode
2771 * @pi: port information structure
2772 * @cfg: PHY configuration data to set FC mode
2773 * @req_mode: FC mode to configure
2776 ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,
2777 enum ice_fc_mode req_mode)
2779 struct ice_phy_cache_mode_data cache_data;
2780 u8 pause_mask = 0x0;
2783 return ICE_ERR_BAD_PTR;
2787 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2788 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2790 case ICE_FC_RX_PAUSE:
2791 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2793 case ICE_FC_TX_PAUSE:
2794 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2800 /* clear the old pause settings */
2801 cfg->caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE |
2802 ICE_AQC_PHY_EN_RX_LINK_PAUSE);
2804 /* set the new capabilities */
2805 cfg->caps |= pause_mask;
2807 /* Cache user FC request */
2808 cache_data.data.curr_user_fc_req = req_mode;
2809 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE);
2816 * @pi: port information structure
2817 * @aq_failures: pointer to status code, specific to ice_set_fc routine
2818 * @ena_auto_link_update: enable automatic link update
2820 * Set the requested flow control mode.
2823 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update)
2825 struct ice_aqc_set_phy_cfg_data cfg = { 0 };
2826 struct ice_aqc_get_phy_caps_data *pcaps;
2827 enum ice_status status;
2830 if (!pi || !aq_failures)
2831 return ICE_ERR_BAD_PTR;
2836 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL);
2838 return ICE_ERR_NO_MEMORY;
2840 /* Get the current PHY config */
2841 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
2844 *aq_failures = ICE_SET_FC_AQ_FAIL_GET;
2848 ice_copy_phy_caps_to_cfg(pi, pcaps, &cfg);
2850 /* Configure the set PHY data */
2851 status = ice_cfg_phy_fc(pi, &cfg, pi->fc.req_mode);
2855 /* If the capabilities have changed, then set the new config */
2856 if (cfg.caps != pcaps->caps) {
2857 int retry_count, retry_max = 10;
2859 /* Auto restart link so settings take effect */
2860 if (ena_auto_link_update)
2861 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
2863 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
2865 *aq_failures = ICE_SET_FC_AQ_FAIL_SET;
2869 /* Update the link info
2870 * It sometimes takes a really long time for link to
2871 * come back from the atomic reset. Thus, we wait a
2874 for (retry_count = 0; retry_count < retry_max; retry_count++) {
2875 status = ice_update_link_info(pi);
2884 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE;
2888 devm_kfree(ice_hw_to_dev(hw), pcaps);
2893 * ice_phy_caps_equals_cfg
2894 * @phy_caps: PHY capabilities
2895 * @phy_cfg: PHY configuration
2897 * Helper function to determine if PHY capabilities matches PHY
2901 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps,
2902 struct ice_aqc_set_phy_cfg_data *phy_cfg)
2904 u8 caps_mask, cfg_mask;
2906 if (!phy_caps || !phy_cfg)
2909 /* These bits are not common between capabilities and configuration.
2910 * Do not use them to determine equality.
2912 caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE |
2913 ICE_AQC_GET_PHY_EN_MOD_QUAL);
2914 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
2916 if (phy_caps->phy_type_low != phy_cfg->phy_type_low ||
2917 phy_caps->phy_type_high != phy_cfg->phy_type_high ||
2918 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) ||
2919 phy_caps->low_power_ctrl_an != phy_cfg->low_power_ctrl_an ||
2920 phy_caps->eee_cap != phy_cfg->eee_cap ||
2921 phy_caps->eeer_value != phy_cfg->eeer_value ||
2922 phy_caps->link_fec_options != phy_cfg->link_fec_opt)
2929 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data
2930 * @pi: port information structure
2931 * @caps: PHY ability structure to copy date from
2932 * @cfg: PHY configuration structure to copy data to
2934 * Helper function to copy AQC PHY get ability data to PHY set configuration
2938 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi,
2939 struct ice_aqc_get_phy_caps_data *caps,
2940 struct ice_aqc_set_phy_cfg_data *cfg)
2942 if (!pi || !caps || !cfg)
2945 memset(cfg, 0, sizeof(*cfg));
2946 cfg->phy_type_low = caps->phy_type_low;
2947 cfg->phy_type_high = caps->phy_type_high;
2948 cfg->caps = caps->caps;
2949 cfg->low_power_ctrl_an = caps->low_power_ctrl_an;
2950 cfg->eee_cap = caps->eee_cap;
2951 cfg->eeer_value = caps->eeer_value;
2952 cfg->link_fec_opt = caps->link_fec_options;
2953 cfg->module_compliance_enforcement =
2954 caps->module_compliance_enforcement;
2956 if (ice_fw_supports_link_override(pi->hw)) {
2957 struct ice_link_default_override_tlv tlv;
2959 if (ice_get_link_default_override(&tlv, pi))
2962 if (tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE)
2963 cfg->module_compliance_enforcement |=
2964 ICE_LINK_OVERRIDE_STRICT_MODE;
2969 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode
2970 * @pi: port information structure
2971 * @cfg: PHY configuration data to set FEC mode
2972 * @fec: FEC mode to configure
2975 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,
2976 enum ice_fec_mode fec)
2978 struct ice_aqc_get_phy_caps_data *pcaps;
2979 enum ice_status status;
2982 return ICE_ERR_BAD_PTR;
2984 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL);
2986 return ICE_ERR_NO_MEMORY;
2988 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP, pcaps,
2993 cfg->caps |= pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC;
2994 cfg->link_fec_opt = pcaps->link_fec_options;
2998 /* Clear RS bits, and AND BASE-R ability
2999 * bits and OR request bits.
3001 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
3002 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN;
3003 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
3004 ICE_AQC_PHY_FEC_25G_KR_REQ;
3007 /* Clear BASE-R bits, and AND RS ability
3008 * bits and OR request bits.
3010 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN;
3011 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ |
3012 ICE_AQC_PHY_FEC_25G_RS_544_REQ;
3015 /* Clear all FEC option bits. */
3016 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK;
3019 /* AND auto FEC bit, and all caps bits. */
3020 cfg->caps &= ICE_AQC_PHY_CAPS_MASK;
3021 cfg->link_fec_opt |= pcaps->link_fec_options;
3024 status = ICE_ERR_PARAM;
3028 if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(pi->hw)) {
3029 struct ice_link_default_override_tlv tlv;
3031 if (ice_get_link_default_override(&tlv, pi))
3034 if (!(tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) &&
3035 (tlv.options & ICE_LINK_OVERRIDE_EN))
3036 cfg->link_fec_opt = tlv.fec_options;
3046 * ice_get_link_status - get status of the HW network link
3047 * @pi: port information structure
3048 * @link_up: pointer to bool (true/false = linkup/linkdown)
3050 * Variable link_up is true if link is up, false if link is down.
3051 * The variable link_up is invalid if status is non zero. As a
3052 * result of this call, link status reporting becomes enabled
3054 enum ice_status ice_get_link_status(struct ice_port_info *pi, bool *link_up)
3056 struct ice_phy_info *phy_info;
3057 enum ice_status status = 0;
3059 if (!pi || !link_up)
3060 return ICE_ERR_PARAM;
3062 phy_info = &pi->phy;
3064 if (phy_info->get_link_info) {
3065 status = ice_update_link_info(pi);
3068 ice_debug(pi->hw, ICE_DBG_LINK,
3069 "get link status error, status = %d\n",
3073 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP;
3079 * ice_aq_set_link_restart_an
3080 * @pi: pointer to the port information structure
3081 * @ena_link: if true: enable link, if false: disable link
3082 * @cd: pointer to command details structure or NULL
3084 * Sets up the link and restarts the Auto-Negotiation over the link.
3087 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
3088 struct ice_sq_cd *cd)
3090 struct ice_aqc_restart_an *cmd;
3091 struct ice_aq_desc desc;
3093 cmd = &desc.params.restart_an;
3095 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an);
3097 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART;
3098 cmd->lport_num = pi->lport;
3100 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE;
3102 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE;
3104 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
3108 * ice_aq_set_event_mask
3109 * @hw: pointer to the HW struct
3110 * @port_num: port number of the physical function
3111 * @mask: event mask to be set
3112 * @cd: pointer to command details structure or NULL
3114 * Set event mask (0x0613)
3117 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask,
3118 struct ice_sq_cd *cd)
3120 struct ice_aqc_set_event_mask *cmd;
3121 struct ice_aq_desc desc;
3123 cmd = &desc.params.set_event_mask;
3125 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask);
3127 cmd->lport_num = port_num;
3129 cmd->event_mask = cpu_to_le16(mask);
3130 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
3134 * ice_aq_set_mac_loopback
3135 * @hw: pointer to the HW struct
3136 * @ena_lpbk: Enable or Disable loopback
3137 * @cd: pointer to command details structure or NULL
3139 * Enable/disable loopback on a given port
3142 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd)
3144 struct ice_aqc_set_mac_lb *cmd;
3145 struct ice_aq_desc desc;
3147 cmd = &desc.params.set_mac_lb;
3149 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb);
3151 cmd->lb_mode = ICE_AQ_MAC_LB_EN;
3153 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
3157 * ice_aq_set_port_id_led
3158 * @pi: pointer to the port information
3159 * @is_orig_mode: is this LED set to original mode (by the net-list)
3160 * @cd: pointer to command details structure or NULL
3162 * Set LED value for the given port (0x06e9)
3165 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,
3166 struct ice_sq_cd *cd)
3168 struct ice_aqc_set_port_id_led *cmd;
3169 struct ice_hw *hw = pi->hw;
3170 struct ice_aq_desc desc;
3172 cmd = &desc.params.set_port_id_led;
3174 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led);
3177 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG;
3179 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK;
3181 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
3186 * @hw: pointer to the HW struct
3187 * @lport: bits [7:0] = logical port, bit [8] = logical port valid
3188 * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default)
3189 * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding.
3191 * @set_page: set or ignore the page
3192 * @data: pointer to data buffer to be read/written to the I2C device.
3193 * @length: 1-16 for read, 1 for write.
3194 * @write: 0 read, 1 for write.
3195 * @cd: pointer to command details structure or NULL
3197 * Read/Write SFF EEPROM (0x06EE)
3200 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr,
3201 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length,
3202 bool write, struct ice_sq_cd *cd)
3204 struct ice_aqc_sff_eeprom *cmd;
3205 struct ice_aq_desc desc;
3206 enum ice_status status;
3208 if (!data || (mem_addr & 0xff00))
3209 return ICE_ERR_PARAM;
3211 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom);
3212 cmd = &desc.params.read_write_sff_param;
3213 desc.flags = cpu_to_le16(ICE_AQ_FLAG_RD | ICE_AQ_FLAG_BUF);
3214 cmd->lport_num = (u8)(lport & 0xff);
3215 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01);
3216 cmd->i2c_bus_addr = cpu_to_le16(((bus_addr >> 1) &
3217 ICE_AQC_SFF_I2CBUS_7BIT_M) |
3219 ICE_AQC_SFF_SET_EEPROM_PAGE_S) &
3220 ICE_AQC_SFF_SET_EEPROM_PAGE_M));
3221 cmd->i2c_mem_addr = cpu_to_le16(mem_addr & 0xff);
3222 cmd->eeprom_page = cpu_to_le16((u16)page << ICE_AQC_SFF_EEPROM_PAGE_S);
3224 cmd->i2c_bus_addr |= cpu_to_le16(ICE_AQC_SFF_IS_WRITE);
3226 status = ice_aq_send_cmd(hw, &desc, data, length, cd);
3231 * __ice_aq_get_set_rss_lut
3232 * @hw: pointer to the hardware structure
3233 * @vsi_id: VSI FW index
3234 * @lut_type: LUT table type
3235 * @lut: pointer to the LUT buffer provided by the caller
3236 * @lut_size: size of the LUT buffer
3237 * @glob_lut_idx: global LUT index
3238 * @set: set true to set the table, false to get the table
3240 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table
3242 static enum ice_status
3243 __ice_aq_get_set_rss_lut(struct ice_hw *hw, u16 vsi_id, u8 lut_type, u8 *lut,
3244 u16 lut_size, u8 glob_lut_idx, bool set)
3246 struct ice_aqc_get_set_rss_lut *cmd_resp;
3247 struct ice_aq_desc desc;
3248 enum ice_status status;
3251 cmd_resp = &desc.params.get_set_rss_lut;
3254 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut);
3255 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
3257 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut);
3260 cmd_resp->vsi_id = cpu_to_le16(((vsi_id <<
3261 ICE_AQC_GSET_RSS_LUT_VSI_ID_S) &
3262 ICE_AQC_GSET_RSS_LUT_VSI_ID_M) |
3263 ICE_AQC_GSET_RSS_LUT_VSI_VALID);
3266 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI:
3267 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF:
3268 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL:
3269 flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) &
3270 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M);
3273 status = ICE_ERR_PARAM;
3274 goto ice_aq_get_set_rss_lut_exit;
3277 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) {
3278 flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) &
3279 ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M);
3282 goto ice_aq_get_set_rss_lut_send;
3283 } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
3285 goto ice_aq_get_set_rss_lut_send;
3287 goto ice_aq_get_set_rss_lut_send;
3290 /* LUT size is only valid for Global and PF table types */
3292 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128:
3294 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512:
3295 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG <<
3296 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
3297 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
3299 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K:
3300 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
3301 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG <<
3302 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
3303 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
3308 status = ICE_ERR_PARAM;
3309 goto ice_aq_get_set_rss_lut_exit;
3312 ice_aq_get_set_rss_lut_send:
3313 cmd_resp->flags = cpu_to_le16(flags);
3314 status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL);
3316 ice_aq_get_set_rss_lut_exit:
3321 * ice_aq_get_rss_lut
3322 * @hw: pointer to the hardware structure
3323 * @vsi_handle: software VSI handle
3324 * @lut_type: LUT table type
3325 * @lut: pointer to the LUT buffer provided by the caller
3326 * @lut_size: size of the LUT buffer
3328 * get the RSS lookup table, PF or VSI type
3331 ice_aq_get_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type,
3332 u8 *lut, u16 lut_size)
3334 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut)
3335 return ICE_ERR_PARAM;
3337 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3338 lut_type, lut, lut_size, 0, false);
3342 * ice_aq_set_rss_lut
3343 * @hw: pointer to the hardware structure
3344 * @vsi_handle: software VSI handle
3345 * @lut_type: LUT table type
3346 * @lut: pointer to the LUT buffer provided by the caller
3347 * @lut_size: size of the LUT buffer
3349 * set the RSS lookup table, PF or VSI type
3352 ice_aq_set_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type,
3353 u8 *lut, u16 lut_size)
3355 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut)
3356 return ICE_ERR_PARAM;
3358 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3359 lut_type, lut, lut_size, 0, true);
3363 * __ice_aq_get_set_rss_key
3364 * @hw: pointer to the HW struct
3365 * @vsi_id: VSI FW index
3366 * @key: pointer to key info struct
3367 * @set: set true to set the key, false to get the key
3369 * get (0x0B04) or set (0x0B02) the RSS key per VSI
3372 ice_status __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id,
3373 struct ice_aqc_get_set_rss_keys *key,
3376 struct ice_aqc_get_set_rss_key *cmd_resp;
3377 u16 key_size = sizeof(*key);
3378 struct ice_aq_desc desc;
3380 cmd_resp = &desc.params.get_set_rss_key;
3383 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key);
3384 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
3386 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key);
3389 cmd_resp->vsi_id = cpu_to_le16(((vsi_id <<
3390 ICE_AQC_GSET_RSS_KEY_VSI_ID_S) &
3391 ICE_AQC_GSET_RSS_KEY_VSI_ID_M) |
3392 ICE_AQC_GSET_RSS_KEY_VSI_VALID);
3394 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL);
3398 * ice_aq_get_rss_key
3399 * @hw: pointer to the HW struct
3400 * @vsi_handle: software VSI handle
3401 * @key: pointer to key info struct
3403 * get the RSS key per VSI
3406 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle,
3407 struct ice_aqc_get_set_rss_keys *key)
3409 if (!ice_is_vsi_valid(hw, vsi_handle) || !key)
3410 return ICE_ERR_PARAM;
3412 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3417 * ice_aq_set_rss_key
3418 * @hw: pointer to the HW struct
3419 * @vsi_handle: software VSI handle
3420 * @keys: pointer to key info struct
3422 * set the RSS key per VSI
3425 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle,
3426 struct ice_aqc_get_set_rss_keys *keys)
3428 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys)
3429 return ICE_ERR_PARAM;
3431 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3436 * ice_aq_add_lan_txq
3437 * @hw: pointer to the hardware structure
3438 * @num_qgrps: Number of added queue groups
3439 * @qg_list: list of queue groups to be added
3440 * @buf_size: size of buffer for indirect command
3441 * @cd: pointer to command details structure or NULL
3443 * Add Tx LAN queue (0x0C30)
3446 * Prior to calling add Tx LAN queue:
3447 * Initialize the following as part of the Tx queue context:
3448 * Completion queue ID if the queue uses Completion queue, Quanta profile,
3449 * Cache profile and Packet shaper profile.
3451 * After add Tx LAN queue AQ command is completed:
3452 * Interrupts should be associated with specific queues,
3453 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue
3456 static enum ice_status
3457 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps,
3458 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size,
3459 struct ice_sq_cd *cd)
3461 struct ice_aqc_add_tx_qgrp *list;
3462 struct ice_aqc_add_txqs *cmd;
3463 struct ice_aq_desc desc;
3464 u16 i, sum_size = 0;
3466 cmd = &desc.params.add_txqs;
3468 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs);
3471 return ICE_ERR_PARAM;
3473 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
3474 return ICE_ERR_PARAM;
3476 for (i = 0, list = qg_list; i < num_qgrps; i++) {
3477 sum_size += struct_size(list, txqs, list->num_txqs);
3478 list = (struct ice_aqc_add_tx_qgrp *)(list->txqs +
3482 if (buf_size != sum_size)
3483 return ICE_ERR_PARAM;
3485 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
3487 cmd->num_qgrps = num_qgrps;
3489 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
3493 * ice_aq_dis_lan_txq
3494 * @hw: pointer to the hardware structure
3495 * @num_qgrps: number of groups in the list
3496 * @qg_list: the list of groups to disable
3497 * @buf_size: the total size of the qg_list buffer in bytes
3498 * @rst_src: if called due to reset, specifies the reset source
3499 * @vmvf_num: the relative VM or VF number that is undergoing the reset
3500 * @cd: pointer to command details structure or NULL
3502 * Disable LAN Tx queue (0x0C31)
3504 static enum ice_status
3505 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps,
3506 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size,
3507 enum ice_disq_rst_src rst_src, u16 vmvf_num,
3508 struct ice_sq_cd *cd)
3510 struct ice_aqc_dis_txq_item *item;
3511 struct ice_aqc_dis_txqs *cmd;
3512 struct ice_aq_desc desc;
3513 enum ice_status status;
3516 cmd = &desc.params.dis_txqs;
3517 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs);
3519 /* qg_list can be NULL only in VM/VF reset flow */
3520 if (!qg_list && !rst_src)
3521 return ICE_ERR_PARAM;
3523 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
3524 return ICE_ERR_PARAM;
3526 cmd->num_entries = num_qgrps;
3528 cmd->vmvf_and_timeout = cpu_to_le16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) &
3529 ICE_AQC_Q_DIS_TIMEOUT_M);
3533 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET;
3534 cmd->vmvf_and_timeout |=
3535 cpu_to_le16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M);
3538 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VF_RESET;
3539 /* In this case, FW expects vmvf_num to be absolute VF ID */
3540 cmd->vmvf_and_timeout |=
3541 cpu_to_le16((vmvf_num + hw->func_caps.vf_base_id) &
3542 ICE_AQC_Q_DIS_VMVF_NUM_M);
3549 /* flush pipe on time out */
3550 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE;
3551 /* If no queue group info, we are in a reset flow. Issue the AQ */
3555 /* set RD bit to indicate that command buffer is provided by the driver
3556 * and it needs to be read by the firmware
3558 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
3560 for (i = 0, item = qg_list; i < num_qgrps; i++) {
3561 u16 item_size = struct_size(item, q_id, item->num_qs);
3563 /* If the num of queues is even, add 2 bytes of padding */
3564 if ((item->num_qs % 2) == 0)
3569 item = (struct ice_aqc_dis_txq_item *)((u8 *)item + item_size);
3573 return ICE_ERR_PARAM;
3576 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
3579 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n",
3580 vmvf_num, hw->adminq.sq_last_status);
3582 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n",
3583 le16_to_cpu(qg_list[0].q_id[0]),
3584 hw->adminq.sq_last_status);
3589 /* End of FW Admin Queue command wrappers */
3592 * ice_write_byte - write a byte to a packed context structure
3593 * @src_ctx: the context structure to read from
3594 * @dest_ctx: the context to be written to
3595 * @ce_info: a description of the struct to be filled
3598 ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3600 u8 src_byte, dest_byte, mask;
3604 /* copy from the next struct field */
3605 from = src_ctx + ce_info->offset;
3607 /* prepare the bits and mask */
3608 shift_width = ce_info->lsb % 8;
3609 mask = (u8)(BIT(ce_info->width) - 1);
3614 /* shift to correct alignment */
3615 mask <<= shift_width;
3616 src_byte <<= shift_width;
3618 /* get the current bits from the target bit string */
3619 dest = dest_ctx + (ce_info->lsb / 8);
3621 memcpy(&dest_byte, dest, sizeof(dest_byte));
3623 dest_byte &= ~mask; /* get the bits not changing */
3624 dest_byte |= src_byte; /* add in the new bits */
3626 /* put it all back */
3627 memcpy(dest, &dest_byte, sizeof(dest_byte));
3631 * ice_write_word - write a word to a packed context structure
3632 * @src_ctx: the context structure to read from
3633 * @dest_ctx: the context to be written to
3634 * @ce_info: a description of the struct to be filled
3637 ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3644 /* copy from the next struct field */
3645 from = src_ctx + ce_info->offset;
3647 /* prepare the bits and mask */
3648 shift_width = ce_info->lsb % 8;
3649 mask = BIT(ce_info->width) - 1;
3651 /* don't swizzle the bits until after the mask because the mask bits
3652 * will be in a different bit position on big endian machines
3654 src_word = *(u16 *)from;
3657 /* shift to correct alignment */
3658 mask <<= shift_width;
3659 src_word <<= shift_width;
3661 /* get the current bits from the target bit string */
3662 dest = dest_ctx + (ce_info->lsb / 8);
3664 memcpy(&dest_word, dest, sizeof(dest_word));
3666 dest_word &= ~(cpu_to_le16(mask)); /* get the bits not changing */
3667 dest_word |= cpu_to_le16(src_word); /* add in the new bits */
3669 /* put it all back */
3670 memcpy(dest, &dest_word, sizeof(dest_word));
3674 * ice_write_dword - write a dword to a packed context structure
3675 * @src_ctx: the context structure to read from
3676 * @dest_ctx: the context to be written to
3677 * @ce_info: a description of the struct to be filled
3680 ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3682 u32 src_dword, mask;
3687 /* copy from the next struct field */
3688 from = src_ctx + ce_info->offset;
3690 /* prepare the bits and mask */
3691 shift_width = ce_info->lsb % 8;
3693 /* if the field width is exactly 32 on an x86 machine, then the shift
3694 * operation will not work because the SHL instructions count is masked
3695 * to 5 bits so the shift will do nothing
3697 if (ce_info->width < 32)
3698 mask = BIT(ce_info->width) - 1;
3702 /* don't swizzle the bits until after the mask because the mask bits
3703 * will be in a different bit position on big endian machines
3705 src_dword = *(u32 *)from;
3708 /* shift to correct alignment */
3709 mask <<= shift_width;
3710 src_dword <<= shift_width;
3712 /* get the current bits from the target bit string */
3713 dest = dest_ctx + (ce_info->lsb / 8);
3715 memcpy(&dest_dword, dest, sizeof(dest_dword));
3717 dest_dword &= ~(cpu_to_le32(mask)); /* get the bits not changing */
3718 dest_dword |= cpu_to_le32(src_dword); /* add in the new bits */
3720 /* put it all back */
3721 memcpy(dest, &dest_dword, sizeof(dest_dword));
3725 * ice_write_qword - write a qword to a packed context structure
3726 * @src_ctx: the context structure to read from
3727 * @dest_ctx: the context to be written to
3728 * @ce_info: a description of the struct to be filled
3731 ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3733 u64 src_qword, mask;
3738 /* copy from the next struct field */
3739 from = src_ctx + ce_info->offset;
3741 /* prepare the bits and mask */
3742 shift_width = ce_info->lsb % 8;
3744 /* if the field width is exactly 64 on an x86 machine, then the shift
3745 * operation will not work because the SHL instructions count is masked
3746 * to 6 bits so the shift will do nothing
3748 if (ce_info->width < 64)
3749 mask = BIT_ULL(ce_info->width) - 1;
3753 /* don't swizzle the bits until after the mask because the mask bits
3754 * will be in a different bit position on big endian machines
3756 src_qword = *(u64 *)from;
3759 /* shift to correct alignment */
3760 mask <<= shift_width;
3761 src_qword <<= shift_width;
3763 /* get the current bits from the target bit string */
3764 dest = dest_ctx + (ce_info->lsb / 8);
3766 memcpy(&dest_qword, dest, sizeof(dest_qword));
3768 dest_qword &= ~(cpu_to_le64(mask)); /* get the bits not changing */
3769 dest_qword |= cpu_to_le64(src_qword); /* add in the new bits */
3771 /* put it all back */
3772 memcpy(dest, &dest_qword, sizeof(dest_qword));
3776 * ice_set_ctx - set context bits in packed structure
3777 * @hw: pointer to the hardware structure
3778 * @src_ctx: pointer to a generic non-packed context structure
3779 * @dest_ctx: pointer to memory for the packed structure
3780 * @ce_info: a description of the structure to be transformed
3783 ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx,
3784 const struct ice_ctx_ele *ce_info)
3788 for (f = 0; ce_info[f].width; f++) {
3789 /* We have to deal with each element of the FW response
3790 * using the correct size so that we are correct regardless
3791 * of the endianness of the machine.
3793 if (ce_info[f].width > (ce_info[f].size_of * BITS_PER_BYTE)) {
3794 ice_debug(hw, ICE_DBG_QCTX,
3795 "Field %d width of %d bits larger than size of %d byte(s) ... skipping write\n",
3796 f, ce_info[f].width, ce_info[f].size_of);
3799 switch (ce_info[f].size_of) {
3801 ice_write_byte(src_ctx, dest_ctx, &ce_info[f]);
3804 ice_write_word(src_ctx, dest_ctx, &ce_info[f]);
3807 ice_write_dword(src_ctx, dest_ctx, &ce_info[f]);
3810 ice_write_qword(src_ctx, dest_ctx, &ce_info[f]);
3813 return ICE_ERR_INVAL_SIZE;
3821 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC
3822 * @hw: pointer to the HW struct
3823 * @vsi_handle: software VSI handle
3825 * @q_handle: software queue handle
3828 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle)
3830 struct ice_vsi_ctx *vsi;
3831 struct ice_q_ctx *q_ctx;
3833 vsi = ice_get_vsi_ctx(hw, vsi_handle);
3836 if (q_handle >= vsi->num_lan_q_entries[tc])
3838 if (!vsi->lan_q_ctx[tc])
3840 q_ctx = vsi->lan_q_ctx[tc];
3841 return &q_ctx[q_handle];
3846 * @pi: port information structure
3847 * @vsi_handle: software VSI handle
3849 * @q_handle: software queue handle
3850 * @num_qgrps: Number of added queue groups
3851 * @buf: list of queue groups to be added
3852 * @buf_size: size of buffer for indirect command
3853 * @cd: pointer to command details structure or NULL
3855 * This function adds one LAN queue
3858 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle,
3859 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size,
3860 struct ice_sq_cd *cd)
3862 struct ice_aqc_txsched_elem_data node = { 0 };
3863 struct ice_sched_node *parent;
3864 struct ice_q_ctx *q_ctx;
3865 enum ice_status status;
3868 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
3871 if (num_qgrps > 1 || buf->num_txqs > 1)
3872 return ICE_ERR_MAX_LIMIT;
3876 if (!ice_is_vsi_valid(hw, vsi_handle))
3877 return ICE_ERR_PARAM;
3879 mutex_lock(&pi->sched_lock);
3881 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle);
3883 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n",
3885 status = ICE_ERR_PARAM;
3889 /* find a parent node */
3890 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc,
3891 ICE_SCHED_NODE_OWNER_LAN);
3893 status = ICE_ERR_PARAM;
3897 buf->parent_teid = parent->info.node_teid;
3898 node.parent_teid = parent->info.node_teid;
3899 /* Mark that the values in the "generic" section as valid. The default
3900 * value in the "generic" section is zero. This means that :
3901 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0.
3902 * - 0 priority among siblings, indicated by Bit 1-3.
3903 * - WFQ, indicated by Bit 4.
3904 * - 0 Adjustment value is used in PSM credit update flow, indicated by
3906 * - Bit 7 is reserved.
3907 * Without setting the generic section as valid in valid_sections, the
3908 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL.
3910 buf->txqs[0].info.valid_sections = ICE_AQC_ELEM_VALID_GENERIC;
3912 /* add the LAN queue */
3913 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd);
3915 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n",
3916 le16_to_cpu(buf->txqs[0].txq_id),
3917 hw->adminq.sq_last_status);
3921 node.node_teid = buf->txqs[0].q_teid;
3922 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF;
3923 q_ctx->q_handle = q_handle;
3924 q_ctx->q_teid = le32_to_cpu(node.node_teid);
3926 /* add a leaf node into scheduler tree queue layer */
3927 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node);
3929 status = ice_sched_replay_q_bw(pi, q_ctx);
3932 mutex_unlock(&pi->sched_lock);
3938 * @pi: port information structure
3939 * @vsi_handle: software VSI handle
3941 * @num_queues: number of queues
3942 * @q_handles: pointer to software queue handle array
3943 * @q_ids: pointer to the q_id array
3944 * @q_teids: pointer to queue node teids
3945 * @rst_src: if called due to reset, specifies the reset source
3946 * @vmvf_num: the relative VM or VF number that is undergoing the reset
3947 * @cd: pointer to command details structure or NULL
3949 * This function removes queues and their corresponding nodes in SW DB
3952 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues,
3953 u16 *q_handles, u16 *q_ids, u32 *q_teids,
3954 enum ice_disq_rst_src rst_src, u16 vmvf_num,
3955 struct ice_sq_cd *cd)
3957 enum ice_status status = ICE_ERR_DOES_NOT_EXIST;
3958 struct ice_aqc_dis_txq_item *qg_list;
3959 struct ice_q_ctx *q_ctx;
3963 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
3969 /* if queue is disabled already yet the disable queue command
3970 * has to be sent to complete the VF reset, then call
3971 * ice_aq_dis_lan_txq without any queue information
3974 return ice_aq_dis_lan_txq(hw, 0, NULL, 0, rst_src,
3979 buf_size = struct_size(qg_list, q_id, 1);
3980 qg_list = kzalloc(buf_size, GFP_KERNEL);
3982 return ICE_ERR_NO_MEMORY;
3984 mutex_lock(&pi->sched_lock);
3986 for (i = 0; i < num_queues; i++) {
3987 struct ice_sched_node *node;
3989 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]);
3992 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handles[i]);
3994 ice_debug(hw, ICE_DBG_SCHED, "invalid queue handle%d\n",
3998 if (q_ctx->q_handle != q_handles[i]) {
3999 ice_debug(hw, ICE_DBG_SCHED, "Err:handles %d %d\n",
4000 q_ctx->q_handle, q_handles[i]);
4003 qg_list->parent_teid = node->info.parent_teid;
4004 qg_list->num_qs = 1;
4005 qg_list->q_id[0] = cpu_to_le16(q_ids[i]);
4006 status = ice_aq_dis_lan_txq(hw, 1, qg_list, buf_size, rst_src,
4011 ice_free_sched_node(pi, node);
4012 q_ctx->q_handle = ICE_INVAL_Q_HANDLE;
4014 mutex_unlock(&pi->sched_lock);
4020 * ice_cfg_vsi_qs - configure the new/existing VSI queues
4021 * @pi: port information structure
4022 * @vsi_handle: software VSI handle
4023 * @tc_bitmap: TC bitmap
4024 * @maxqs: max queues array per TC
4025 * @owner: LAN or RDMA
4027 * This function adds/updates the VSI queues per TC.
4029 static enum ice_status
4030 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,
4031 u16 *maxqs, u8 owner)
4033 enum ice_status status = 0;
4036 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
4039 if (!ice_is_vsi_valid(pi->hw, vsi_handle))
4040 return ICE_ERR_PARAM;
4042 mutex_lock(&pi->sched_lock);
4044 ice_for_each_traffic_class(i) {
4045 /* configuration is possible only if TC node is present */
4046 if (!ice_sched_get_tc_node(pi, i))
4049 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner,
4050 ice_is_tc_ena(tc_bitmap, i));
4055 mutex_unlock(&pi->sched_lock);
4060 * ice_cfg_vsi_lan - configure VSI LAN queues
4061 * @pi: port information structure
4062 * @vsi_handle: software VSI handle
4063 * @tc_bitmap: TC bitmap
4064 * @max_lanqs: max LAN queues array per TC
4066 * This function adds/updates the VSI LAN queues per TC.
4069 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,
4072 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs,
4073 ICE_SCHED_NODE_OWNER_LAN);
4077 * ice_replay_pre_init - replay pre initialization
4078 * @hw: pointer to the HW struct
4080 * Initializes required config data for VSI, FD, ACL, and RSS before replay.
4082 static enum ice_status ice_replay_pre_init(struct ice_hw *hw)
4084 struct ice_switch_info *sw = hw->switch_info;
4087 /* Delete old entries from replay filter list head if there is any */
4088 ice_rm_all_sw_replay_rule_info(hw);
4089 /* In start of replay, move entries into replay_rules list, it
4090 * will allow adding rules entries back to filt_rules list,
4091 * which is operational list.
4093 for (i = 0; i < ICE_SW_LKUP_LAST; i++)
4094 list_replace_init(&sw->recp_list[i].filt_rules,
4095 &sw->recp_list[i].filt_replay_rules);
4101 * ice_replay_vsi - replay VSI configuration
4102 * @hw: pointer to the HW struct
4103 * @vsi_handle: driver VSI handle
4105 * Restore all VSI configuration after reset. It is required to call this
4106 * function with main VSI first.
4108 enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle)
4110 enum ice_status status;
4112 if (!ice_is_vsi_valid(hw, vsi_handle))
4113 return ICE_ERR_PARAM;
4115 /* Replay pre-initialization if there is any */
4116 if (vsi_handle == ICE_MAIN_VSI_HANDLE) {
4117 status = ice_replay_pre_init(hw);
4121 /* Replay per VSI all RSS configurations */
4122 status = ice_replay_rss_cfg(hw, vsi_handle);
4125 /* Replay per VSI all filters */
4126 status = ice_replay_vsi_all_fltr(hw, vsi_handle);
4131 * ice_replay_post - post replay configuration cleanup
4132 * @hw: pointer to the HW struct
4134 * Post replay cleanup.
4136 void ice_replay_post(struct ice_hw *hw)
4138 /* Delete old entries from replay filter list head */
4139 ice_rm_all_sw_replay_rule_info(hw);
4143 * ice_stat_update40 - read 40 bit stat from the chip and update stat values
4144 * @hw: ptr to the hardware info
4145 * @reg: offset of 64 bit HW register to read from
4146 * @prev_stat_loaded: bool to specify if previous stats are loaded
4147 * @prev_stat: ptr to previous loaded stat value
4148 * @cur_stat: ptr to current stat value
4151 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
4152 u64 *prev_stat, u64 *cur_stat)
4154 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1);
4156 /* device stats are not reset at PFR, they likely will not be zeroed
4157 * when the driver starts. Thus, save the value from the first read
4158 * without adding to the statistic value so that we report stats which
4159 * count up from zero.
4161 if (!prev_stat_loaded) {
4162 *prev_stat = new_data;
4166 /* Calculate the difference between the new and old values, and then
4167 * add it to the software stat value.
4169 if (new_data >= *prev_stat)
4170 *cur_stat += new_data - *prev_stat;
4172 /* to manage the potential roll-over */
4173 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat;
4175 /* Update the previously stored value to prepare for next read */
4176 *prev_stat = new_data;
4180 * ice_stat_update32 - read 32 bit stat from the chip and update stat values
4181 * @hw: ptr to the hardware info
4182 * @reg: offset of HW register to read from
4183 * @prev_stat_loaded: bool to specify if previous stats are loaded
4184 * @prev_stat: ptr to previous loaded stat value
4185 * @cur_stat: ptr to current stat value
4188 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
4189 u64 *prev_stat, u64 *cur_stat)
4193 new_data = rd32(hw, reg);
4195 /* device stats are not reset at PFR, they likely will not be zeroed
4196 * when the driver starts. Thus, save the value from the first read
4197 * without adding to the statistic value so that we report stats which
4198 * count up from zero.
4200 if (!prev_stat_loaded) {
4201 *prev_stat = new_data;
4205 /* Calculate the difference between the new and old values, and then
4206 * add it to the software stat value.
4208 if (new_data >= *prev_stat)
4209 *cur_stat += new_data - *prev_stat;
4211 /* to manage the potential roll-over */
4212 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat;
4214 /* Update the previously stored value to prepare for next read */
4215 *prev_stat = new_data;
4219 * ice_sched_query_elem - query element information from HW
4220 * @hw: pointer to the HW struct
4221 * @node_teid: node TEID to be queried
4222 * @buf: buffer to element information
4224 * This function queries HW element information
4227 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
4228 struct ice_aqc_txsched_elem_data *buf)
4230 u16 buf_size, num_elem_ret = 0;
4231 enum ice_status status;
4233 buf_size = sizeof(*buf);
4234 memset(buf, 0, buf_size);
4235 buf->node_teid = cpu_to_le32(node_teid);
4236 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret,
4238 if (status || num_elem_ret != 1)
4239 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n");
4244 * ice_fw_supports_link_override
4245 * @hw: pointer to the hardware structure
4247 * Checks if the firmware supports link override
4249 bool ice_fw_supports_link_override(struct ice_hw *hw)
4251 /* Currently, only supported for E810 devices */
4252 if (hw->mac_type != ICE_MAC_E810)
4255 if (hw->api_maj_ver == ICE_FW_API_LINK_OVERRIDE_MAJ) {
4256 if (hw->api_min_ver > ICE_FW_API_LINK_OVERRIDE_MIN)
4258 if (hw->api_min_ver == ICE_FW_API_LINK_OVERRIDE_MIN &&
4259 hw->api_patch >= ICE_FW_API_LINK_OVERRIDE_PATCH)
4261 } else if (hw->api_maj_ver > ICE_FW_API_LINK_OVERRIDE_MAJ) {
4269 * ice_get_link_default_override
4270 * @ldo: pointer to the link default override struct
4271 * @pi: pointer to the port info struct
4273 * Gets the link default override for a port
4276 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo,
4277 struct ice_port_info *pi)
4279 u16 i, tlv, tlv_len, tlv_start, buf, offset;
4280 struct ice_hw *hw = pi->hw;
4281 enum ice_status status;
4283 status = ice_get_pfa_module_tlv(hw, &tlv, &tlv_len,
4284 ICE_SR_LINK_DEFAULT_OVERRIDE_PTR);
4286 ice_debug(hw, ICE_DBG_INIT,
4287 "Failed to read link override TLV.\n");
4291 /* Each port has its own config; calculate for our port */
4292 tlv_start = tlv + pi->lport * ICE_SR_PFA_LINK_OVERRIDE_WORDS +
4293 ICE_SR_PFA_LINK_OVERRIDE_OFFSET;
4295 /* link options first */
4296 status = ice_read_sr_word(hw, tlv_start, &buf);
4298 ice_debug(hw, ICE_DBG_INIT,
4299 "Failed to read override link options.\n");
4302 ldo->options = buf & ICE_LINK_OVERRIDE_OPT_M;
4303 ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >>
4304 ICE_LINK_OVERRIDE_PHY_CFG_S;
4306 /* link PHY config */
4307 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET;
4308 status = ice_read_sr_word(hw, offset, &buf);
4310 ice_debug(hw, ICE_DBG_INIT,
4311 "Failed to read override phy config.\n");
4314 ldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M;
4317 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET;
4318 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) {
4319 status = ice_read_sr_word(hw, (offset + i), &buf);
4321 ice_debug(hw, ICE_DBG_INIT,
4322 "Failed to read override link options.\n");
4325 /* shift 16 bits at a time to fill 64 bits */
4326 ldo->phy_type_low |= ((u64)buf << (i * 16));
4329 /* PHY types high */
4330 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET +
4331 ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS;
4332 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) {
4333 status = ice_read_sr_word(hw, (offset + i), &buf);
4335 ice_debug(hw, ICE_DBG_INIT,
4336 "Failed to read override link options.\n");
4339 /* shift 16 bits at a time to fill 64 bits */
4340 ldo->phy_type_high |= ((u64)buf << (i * 16));
4347 * ice_is_phy_caps_an_enabled - check if PHY capabilities autoneg is enabled
4348 * @caps: get PHY capability data
4350 bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps)
4352 if (caps->caps & ICE_AQC_PHY_AN_MODE ||
4353 caps->low_power_ctrl_an & (ICE_AQC_PHY_AN_EN_CLAUSE28 |
4354 ICE_AQC_PHY_AN_EN_CLAUSE73 |
4355 ICE_AQC_PHY_AN_EN_CLAUSE37))