1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018, Intel Corporation. */
4 #ifndef _ICE_ADMINQ_CMD_H_
5 #define _ICE_ADMINQ_CMD_H_
7 /* This header file defines the Admin Queue commands, error codes and
8 * descriptor format. It is shared between Firmware and Software.
11 #define ICE_MAX_VSI 768
12 #define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9
13 #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728
15 struct ice_aqc_generic {
22 /* Get version (direct 0x0001) */
23 struct ice_aqc_get_ver {
36 /* Send driver version (indirect 0x0002) */
37 struct ice_aqc_driver_ver {
47 /* Queue Shutdown (direct 0x0003) */
48 struct ice_aqc_q_shutdown {
50 #define ICE_AQC_DRIVER_UNLOADING BIT(0)
54 /* Request resource ownership (direct 0x0008)
55 * Release resource ownership (direct 0x0009)
57 struct ice_aqc_req_res {
59 #define ICE_AQC_RES_ID_NVM 1
60 #define ICE_AQC_RES_ID_SDP 2
61 #define ICE_AQC_RES_ID_CHNG_LOCK 3
62 #define ICE_AQC_RES_ID_GLBL_LOCK 4
64 #define ICE_AQC_RES_ACCESS_READ 1
65 #define ICE_AQC_RES_ACCESS_WRITE 2
67 /* Upon successful completion, FW writes this value and driver is
68 * expected to release resource before timeout. This value is provided
72 #define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000
73 #define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000
74 #define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000
75 #define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000
76 /* For SDP: pin ID of the SDP */
78 /* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */
80 #define ICE_AQ_RES_GLBL_SUCCESS 0
81 #define ICE_AQ_RES_GLBL_IN_PROG 1
82 #define ICE_AQ_RES_GLBL_DONE 2
86 /* Get function capabilities (indirect 0x000A)
87 * Get device capabilities (indirect 0x000B)
89 struct ice_aqc_list_caps {
98 /* Device/Function buffer entry, repeated per reported capability */
99 struct ice_aqc_list_caps_elem {
101 #define ICE_AQC_CAPS_VALID_FUNCTIONS 0x0005
102 #define ICE_AQC_CAPS_SRIOV 0x0012
103 #define ICE_AQC_CAPS_VF 0x0013
104 #define ICE_AQC_CAPS_VSI 0x0017
105 #define ICE_AQC_CAPS_DCB 0x0018
106 #define ICE_AQC_CAPS_RSS 0x0040
107 #define ICE_AQC_CAPS_RXQS 0x0041
108 #define ICE_AQC_CAPS_TXQS 0x0042
109 #define ICE_AQC_CAPS_MSIX 0x0043
110 #define ICE_AQC_CAPS_FD 0x0045
111 #define ICE_AQC_CAPS_MAX_MTU 0x0047
115 /* Number of resources described by this capability */
117 /* Only meaningful for some types of resources */
119 /* Only meaningful for some types of resources */
125 /* Manage MAC address, read command - indirect (0x0107)
126 * This struct is also used for the response
128 struct ice_aqc_manage_mac_read {
129 __le16 flags; /* Zeroed by device driver */
130 #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4)
131 #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5)
132 #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6)
133 #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7)
134 #define ICE_AQC_MAN_MAC_READ_S 4
135 #define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S)
137 u8 num_addr; /* Used in response */
143 /* Response buffer format for manage MAC read command */
144 struct ice_aqc_manage_mac_read_resp {
147 #define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0
148 #define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1
149 u8 mac_addr[ETH_ALEN];
152 /* Manage MAC address, write command - direct (0x0108) */
153 struct ice_aqc_manage_mac_write {
156 #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0)
157 #define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1)
158 #define ICE_AQC_MAN_MAC_WR_S 6
159 #define ICE_AQC_MAN_MAC_WR_M ICE_M(3, ICE_AQC_MAN_MAC_WR_S)
160 #define ICE_AQC_MAN_MAC_UPDATE_LAA 0
161 #define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL BIT(ICE_AQC_MAN_MAC_WR_S)
162 /* byte stream in network order */
163 u8 mac_addr[ETH_ALEN];
168 /* Clear PXE Command and response (direct 0x0110) */
169 struct ice_aqc_clear_pxe {
171 #define ICE_AQC_CLEAR_PXE_RX_CNT 0x2
175 /* Get switch configuration (0x0200) */
176 struct ice_aqc_get_sw_cfg {
177 /* Reserved for command and copy of request flags for response */
179 /* First desc in case of command and next_elem in case of response
180 * In case of response, if it is not zero, means all the configuration
181 * was not returned and new command shall be sent with this value in
182 * the 'first desc' field
185 /* Reserved for command, only used for response */
192 /* Each entry in the response buffer is of the following type: */
193 struct ice_aqc_get_sw_cfg_resp_elem {
194 /* VSI/Port Number */
196 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0
197 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \
198 (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S)
199 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14
200 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S)
201 #define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0
202 #define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1
203 #define ICE_AQC_GET_SW_CONF_RESP_VSI 2
205 /* SWID VSI/Port belongs to */
208 /* Bit 14..0 : PF/VF number VSI belongs to
209 * Bit 15 : VF indication bit
212 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0
213 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \
214 (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S)
215 #define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15)
218 /* These resource type defines are used for all switch resource
219 * commands where a resource type is required, such as:
220 * Get Resource Allocation command (indirect 0x0204)
221 * Allocate Resources command (indirect 0x0208)
222 * Free Resources command (indirect 0x0209)
223 * Get Allocated Resource Descriptors Command (indirect 0x020A)
225 #define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03
226 #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04
227 #define ICE_AQC_RES_TYPE_FDIR_COUNTER_BLOCK 0x21
228 #define ICE_AQC_RES_TYPE_FDIR_GUARANTEED_ENTRIES 0x22
229 #define ICE_AQC_RES_TYPE_FDIR_SHARED_ENTRIES 0x23
230 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID 0x58
231 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_TCAM 0x59
232 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID 0x60
233 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_TCAM 0x61
235 #define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM BIT(12)
236 #define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX BIT(13)
238 #define ICE_AQC_RES_TYPE_FLAG_DEDICATED 0x00
240 #define ICE_AQC_RES_TYPE_S 0
241 #define ICE_AQC_RES_TYPE_M (0x07F << ICE_AQC_RES_TYPE_S)
243 /* Allocate Resources command (indirect 0x0208)
244 * Free Resources command (indirect 0x0209)
246 struct ice_aqc_alloc_free_res_cmd {
247 __le16 num_entries; /* Number of Resource entries */
253 /* Resource descriptor */
254 struct ice_aqc_res_elem {
261 /* Buffer for Allocate/Free Resources commands */
262 struct ice_aqc_alloc_free_res_elem {
263 __le16 res_type; /* Types defined above cmd 0x0204 */
264 #define ICE_AQC_RES_TYPE_SHARED_S 7
265 #define ICE_AQC_RES_TYPE_SHARED_M (0x1 << ICE_AQC_RES_TYPE_SHARED_S)
266 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8
267 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \
268 (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S)
270 struct ice_aqc_res_elem elem[];
273 /* Add VSI (indirect 0x0210)
274 * Update VSI (indirect 0x0211)
275 * Get VSI (indirect 0x0212)
276 * Free VSI (indirect 0x0213)
278 struct ice_aqc_add_get_update_free_vsi {
280 #define ICE_AQ_VSI_NUM_S 0
281 #define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S)
282 #define ICE_AQ_VSI_IS_VALID BIT(15)
284 #define ICE_AQ_VSI_KEEP_ALLOC 0x1
288 #define ICE_AQ_VSI_TYPE_S 0
289 #define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S)
290 #define ICE_AQ_VSI_TYPE_VF 0x0
291 #define ICE_AQ_VSI_TYPE_VMDQ2 0x1
292 #define ICE_AQ_VSI_TYPE_PF 0x2
293 #define ICE_AQ_VSI_TYPE_EMP_MNG 0x3
298 /* Response descriptor for:
299 * Add VSI (indirect 0x0210)
300 * Update VSI (indirect 0x0211)
301 * Free VSI (indirect 0x0213)
303 struct ice_aqc_add_update_free_vsi_resp {
312 struct ice_aqc_vsi_props {
313 __le16 valid_sections;
314 #define ICE_AQ_VSI_PROP_SW_VALID BIT(0)
315 #define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1)
316 #define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2)
317 #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3)
318 #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4)
319 #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5)
320 #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6)
321 #define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7)
322 #define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8)
323 #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11)
324 #define ICE_AQ_VSI_PROP_PASID_VALID BIT(12)
328 #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5)
329 #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6)
330 #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7)
332 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0
333 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M \
334 (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S)
335 #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0)
336 #define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4)
338 #define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0
339 #define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S)
340 #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5)
341 /* security section */
343 #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0)
344 #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2)
345 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4
346 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S)
347 #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0)
350 __le16 pvid; /* VLANS include priority bits */
351 u8 pvlan_reserved[2];
353 #define ICE_AQ_VSI_VLAN_MODE_S 0
354 #define ICE_AQ_VSI_VLAN_MODE_M (0x3 << ICE_AQ_VSI_VLAN_MODE_S)
355 #define ICE_AQ_VSI_VLAN_MODE_UNTAGGED 0x1
356 #define ICE_AQ_VSI_VLAN_MODE_TAGGED 0x2
357 #define ICE_AQ_VSI_VLAN_MODE_ALL 0x3
358 #define ICE_AQ_VSI_PVLAN_INSERT_PVID BIT(2)
359 #define ICE_AQ_VSI_VLAN_EMOD_S 3
360 #define ICE_AQ_VSI_VLAN_EMOD_M (0x3 << ICE_AQ_VSI_VLAN_EMOD_S)
361 #define ICE_AQ_VSI_VLAN_EMOD_STR_BOTH (0x0 << ICE_AQ_VSI_VLAN_EMOD_S)
362 #define ICE_AQ_VSI_VLAN_EMOD_STR_UP (0x1 << ICE_AQ_VSI_VLAN_EMOD_S)
363 #define ICE_AQ_VSI_VLAN_EMOD_STR (0x2 << ICE_AQ_VSI_VLAN_EMOD_S)
364 #define ICE_AQ_VSI_VLAN_EMOD_NOTHING (0x3 << ICE_AQ_VSI_VLAN_EMOD_S)
365 u8 pvlan_reserved2[3];
366 /* ingress egress up sections */
367 __le32 ingress_table; /* bitmap, 3 bits per up */
368 #define ICE_AQ_VSI_UP_TABLE_UP0_S 0
369 #define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S)
370 #define ICE_AQ_VSI_UP_TABLE_UP1_S 3
371 #define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S)
372 #define ICE_AQ_VSI_UP_TABLE_UP2_S 6
373 #define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S)
374 #define ICE_AQ_VSI_UP_TABLE_UP3_S 9
375 #define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S)
376 #define ICE_AQ_VSI_UP_TABLE_UP4_S 12
377 #define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S)
378 #define ICE_AQ_VSI_UP_TABLE_UP5_S 15
379 #define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S)
380 #define ICE_AQ_VSI_UP_TABLE_UP6_S 18
381 #define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S)
382 #define ICE_AQ_VSI_UP_TABLE_UP7_S 21
383 #define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S)
384 __le32 egress_table; /* same defines as for ingress table */
385 /* outer tags section */
388 #define ICE_AQ_VSI_OUTER_TAG_MODE_S 0
389 #define ICE_AQ_VSI_OUTER_TAG_MODE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_MODE_S)
390 #define ICE_AQ_VSI_OUTER_TAG_NOTHING 0x0
391 #define ICE_AQ_VSI_OUTER_TAG_REMOVE 0x1
392 #define ICE_AQ_VSI_OUTER_TAG_COPY 0x2
393 #define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2
394 #define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S)
395 #define ICE_AQ_VSI_OUTER_TAG_NONE 0x0
396 #define ICE_AQ_VSI_OUTER_TAG_STAG 0x1
397 #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2
398 #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3
399 #define ICE_AQ_VSI_OUTER_TAG_INSERT BIT(4)
400 #define ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST BIT(6)
401 u8 outer_tag_reserved;
402 /* queue mapping section */
403 __le16 mapping_flags;
404 #define ICE_AQ_VSI_Q_MAP_CONTIG 0x0
405 #define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0)
406 __le16 q_mapping[16];
407 #define ICE_AQ_VSI_Q_S 0
408 #define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S)
409 __le16 tc_mapping[8];
410 #define ICE_AQ_VSI_TC_Q_OFFSET_S 0
411 #define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S)
412 #define ICE_AQ_VSI_TC_Q_NUM_S 11
413 #define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S)
414 /* queueing option section */
416 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0
417 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S)
418 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0
419 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2
420 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3
421 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2
422 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S)
423 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6
424 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
425 #define ICE_AQ_VSI_Q_OPT_RSS_TPLZ (0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
426 #define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ (0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
427 #define ICE_AQ_VSI_Q_OPT_RSS_XOR (0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
428 #define ICE_AQ_VSI_Q_OPT_RSS_JHASH (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
430 #define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0
431 #define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S)
432 #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7)
434 #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0)
435 u8 q_opt_reserved[3];
436 /* outer up section */
437 __le32 outer_up_table; /* same structure and defines as ingress tbl */
439 __le16 sect_10_reserved;
440 /* flow director section */
442 #define ICE_AQ_VSI_FD_ENABLE BIT(0)
443 #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1)
444 #define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3)
445 __le16 max_fd_fltr_dedicated;
446 __le16 max_fd_fltr_shared;
448 #define ICE_AQ_VSI_FD_DEF_Q_S 0
449 #define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S)
450 #define ICE_AQ_VSI_FD_DEF_GRP_S 12
451 #define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S)
452 __le16 fd_report_opt;
453 #define ICE_AQ_VSI_FD_REPORT_Q_S 0
454 #define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S)
455 #define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12
456 #define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S)
457 #define ICE_AQ_VSI_FD_DEF_DROP BIT(15)
460 #define ICE_AQ_VSI_PASID_ID_S 0
461 #define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S)
462 #define ICE_AQ_VSI_PASID_ID_VALID BIT(31)
466 #define ICE_MAX_NUM_RECIPES 64
468 /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3)
470 struct ice_aqc_sw_rules {
471 /* ops: add switch rules, referring the number of rules.
472 * ops: update switch rules, referring the number of filters
473 * ops: remove switch rules, referring the entry index.
474 * ops: get switch rules, referring to the number of filters.
476 __le16 num_rules_fltr_entry_index;
482 /* Add/Update/Get/Remove lookup Rx/Tx command/response entry
483 * This structures describes the lookup rules and associated actions. "index"
484 * is returned as part of a response to a successful Add command, and can be
485 * used to identify the rule for Update/Get/Remove commands.
487 struct ice_sw_rule_lkup_rx_tx {
489 #define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10
490 /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */
494 /* Bit 0:1 - Action type */
495 #define ICE_SINGLE_ACT_TYPE_S 0x00
496 #define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S)
498 /* Bit 2 - Loop back enable
501 #define ICE_SINGLE_ACT_LB_ENABLE BIT(2)
502 #define ICE_SINGLE_ACT_LAN_ENABLE BIT(3)
504 /* Action type = 0 - Forward to VSI or VSI list */
505 #define ICE_SINGLE_ACT_VSI_FORWARDING 0x0
507 #define ICE_SINGLE_ACT_VSI_ID_S 4
508 #define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S)
509 #define ICE_SINGLE_ACT_VSI_LIST_ID_S 4
510 #define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S)
511 /* This bit needs to be set if action is forward to VSI list */
512 #define ICE_SINGLE_ACT_VSI_LIST BIT(14)
513 #define ICE_SINGLE_ACT_VALID_BIT BIT(17)
514 #define ICE_SINGLE_ACT_DROP BIT(18)
516 /* Action type = 1 - Forward to Queue of Queue group */
517 #define ICE_SINGLE_ACT_TO_Q 0x1
518 #define ICE_SINGLE_ACT_Q_INDEX_S 4
519 #define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S)
520 #define ICE_SINGLE_ACT_Q_REGION_S 15
521 #define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S)
522 #define ICE_SINGLE_ACT_Q_PRIORITY BIT(18)
524 /* Action type = 2 - Prune */
525 #define ICE_SINGLE_ACT_PRUNE 0x2
526 #define ICE_SINGLE_ACT_EGRESS BIT(15)
527 #define ICE_SINGLE_ACT_INGRESS BIT(16)
528 #define ICE_SINGLE_ACT_PRUNET BIT(17)
529 /* Bit 18 should be set to 0 for this action */
531 /* Action type = 2 - Pointer */
532 #define ICE_SINGLE_ACT_PTR 0x2
533 #define ICE_SINGLE_ACT_PTR_VAL_S 4
534 #define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S)
535 /* Bit 18 should be set to 1 */
536 #define ICE_SINGLE_ACT_PTR_BIT BIT(18)
538 /* Action type = 3 - Other actions. Last two bits
539 * are other action identifier
541 #define ICE_SINGLE_ACT_OTHER_ACTS 0x3
542 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17
543 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \
544 (0x3 << ICE_SINGLE_OTHER_ACT_IDENTIFIER_S)
546 /* Bit 17:18 - Defines other actions */
547 /* Other action = 0 - Mirror VSI */
548 #define ICE_SINGLE_OTHER_ACT_MIRROR 0
549 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4
550 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \
551 (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S)
553 /* Other action = 3 - Set Stat count */
554 #define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3
555 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4
556 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \
557 (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S)
559 __le16 index; /* The index of the rule in the lookup table */
560 /* Length and values of the header to be matched per recipe or
567 /* Add/Update/Remove large action command/response entry
568 * "index" is returned as part of a response to a successful Add command, and
569 * can be used to identify the action for Update/Get/Remove commands.
571 struct ice_sw_rule_lg_act {
572 __le16 index; /* Index in large action table */
574 /* Max number of large actions */
575 #define ICE_MAX_LG_ACT 4
576 /* Bit 0:1 - Action type */
577 #define ICE_LG_ACT_TYPE_S 0
578 #define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S)
580 /* Action type = 0 - Forward to VSI or VSI list */
581 #define ICE_LG_ACT_VSI_FORWARDING 0
582 #define ICE_LG_ACT_VSI_ID_S 3
583 #define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S)
584 #define ICE_LG_ACT_VSI_LIST_ID_S 3
585 #define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S)
586 /* This bit needs to be set if action is forward to VSI list */
587 #define ICE_LG_ACT_VSI_LIST BIT(13)
589 #define ICE_LG_ACT_VALID_BIT BIT(16)
591 /* Action type = 1 - Forward to Queue of Queue group */
592 #define ICE_LG_ACT_TO_Q 0x1
593 #define ICE_LG_ACT_Q_INDEX_S 3
594 #define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S)
595 #define ICE_LG_ACT_Q_REGION_S 14
596 #define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S)
597 #define ICE_LG_ACT_Q_PRIORITY_SET BIT(17)
599 /* Action type = 2 - Prune */
600 #define ICE_LG_ACT_PRUNE 0x2
601 #define ICE_LG_ACT_EGRESS BIT(14)
602 #define ICE_LG_ACT_INGRESS BIT(15)
603 #define ICE_LG_ACT_PRUNET BIT(16)
605 /* Action type = 3 - Mirror VSI */
606 #define ICE_LG_OTHER_ACT_MIRROR 0x3
607 #define ICE_LG_ACT_MIRROR_VSI_ID_S 3
608 #define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S)
610 /* Action type = 5 - Generic Value */
611 #define ICE_LG_ACT_GENERIC 0x5
612 #define ICE_LG_ACT_GENERIC_VALUE_S 3
613 #define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S)
614 #define ICE_LG_ACT_GENERIC_OFFSET_S 19
615 #define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S)
616 #define ICE_LG_ACT_GENERIC_PRIORITY_S 22
617 #define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S)
618 #define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX 7
620 /* Action = 7 - Set Stat count */
621 #define ICE_LG_ACT_STAT_COUNT 0x7
622 #define ICE_LG_ACT_STAT_COUNT_S 3
623 #define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S)
624 __le32 act[]; /* array of size for actions */
627 /* Add/Update/Remove VSI list command/response entry
628 * "index" is returned as part of a response to a successful Add command, and
629 * can be used to identify the VSI list for Update/Get/Remove commands.
631 struct ice_sw_rule_vsi_list {
632 __le16 index; /* Index of VSI/Prune list */
634 __le16 vsi[]; /* Array of number_vsi VSI numbers */
637 /* Query VSI list command/response entry */
638 struct ice_sw_rule_vsi_list_query {
640 DECLARE_BITMAP(vsi_list, ICE_MAX_VSI);
643 /* Add switch rule response:
644 * Content of return buffer is same as the input buffer. The status field and
645 * LUT index are updated as part of the response
647 struct ice_aqc_sw_rules_elem {
648 __le16 type; /* Switch rule type, one of T_... */
649 #define ICE_AQC_SW_RULES_T_LKUP_RX 0x0
650 #define ICE_AQC_SW_RULES_T_LKUP_TX 0x1
651 #define ICE_AQC_SW_RULES_T_LG_ACT 0x2
652 #define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3
653 #define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4
654 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5
655 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6
658 struct ice_sw_rule_lkup_rx_tx lkup_tx_rx;
659 struct ice_sw_rule_lg_act lg_act;
660 struct ice_sw_rule_vsi_list vsi_list;
661 struct ice_sw_rule_vsi_list_query vsi_list_query;
665 /* Get Default Topology (indirect 0x0400) */
666 struct ice_aqc_get_topo {
675 /* Update TSE (indirect 0x0403)
676 * Get TSE (indirect 0x0404)
677 * Add TSE (indirect 0x0401)
678 * Delete TSE (indirect 0x040F)
679 * Move TSE (indirect 0x0408)
680 * Suspend Nodes (indirect 0x0409)
681 * Resume Nodes (indirect 0x040A)
683 struct ice_aqc_sched_elem_cmd {
684 __le16 num_elem_req; /* Used by commands */
685 __le16 num_elem_resp; /* Used by responses */
691 struct ice_aqc_elem_info_bw {
692 __le16 bw_profile_idx;
696 struct ice_aqc_txsched_elem {
697 u8 elem_type; /* Special field, reserved for some aq calls */
698 #define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0
699 #define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1
700 #define ICE_AQC_ELEM_TYPE_TC 0x2
701 #define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3
702 #define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4
703 #define ICE_AQC_ELEM_TYPE_LEAF 0x5
704 #define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6
706 #define ICE_AQC_ELEM_VALID_GENERIC BIT(0)
707 #define ICE_AQC_ELEM_VALID_CIR BIT(1)
708 #define ICE_AQC_ELEM_VALID_EIR BIT(2)
709 #define ICE_AQC_ELEM_VALID_SHARED BIT(3)
711 #define ICE_AQC_ELEM_GENERIC_MODE_M 0x1
712 #define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1
713 #define ICE_AQC_ELEM_GENERIC_PRIO_M (0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S)
714 #define ICE_AQC_ELEM_GENERIC_SP_S 0x4
715 #define ICE_AQC_ELEM_GENERIC_SP_M (0x1 << ICE_AQC_ELEM_GENERIC_SP_S)
716 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5
717 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \
718 (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S)
719 u8 flags; /* Special field, reserved for some aq calls */
720 #define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1
721 struct ice_aqc_elem_info_bw cir_bw;
722 struct ice_aqc_elem_info_bw eir_bw;
727 struct ice_aqc_txsched_elem_data {
730 struct ice_aqc_txsched_elem data;
733 struct ice_aqc_txsched_topo_grp_info_hdr {
739 struct ice_aqc_add_elem {
740 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
741 struct ice_aqc_txsched_elem_data generic[];
744 struct ice_aqc_get_topo_elem {
745 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
746 struct ice_aqc_txsched_elem_data
747 generic[ICE_AQC_TOPO_MAX_LEVEL_NUM];
750 struct ice_aqc_delete_elem {
751 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
755 /* Query Port ETS (indirect 0x040E)
757 * This indirect command is used to query port TC node configuration.
759 struct ice_aqc_query_port_ets {
766 struct ice_aqc_port_ets_elem {
769 /* 3 bits for UP per TC 0-7, 4th byte reserved */
772 __le32 port_eir_prof_id;
773 __le32 port_cir_prof_id;
774 /* 3 bits per Node priority to TC 0-7, 4th byte reserved */
776 #define ICE_TC_NODE_PRIO_S 0x4
778 __le32 tc_node_teid[8]; /* Used for response, reserved in command */
781 /* Rate limiting profile for
782 * Add RL profile (indirect 0x0410)
783 * Query RL profile (indirect 0x0411)
784 * Remove RL profile (indirect 0x0415)
785 * These indirect commands acts on single or multiple
786 * RL profiles with specified data.
788 struct ice_aqc_rl_profile {
790 __le16 num_processed; /* Only for response. Reserved in Command. */
796 struct ice_aqc_rl_profile_elem {
799 #define ICE_AQC_RL_PROFILE_TYPE_S 0x0
800 #define ICE_AQC_RL_PROFILE_TYPE_M (0x3 << ICE_AQC_RL_PROFILE_TYPE_S)
801 #define ICE_AQC_RL_PROFILE_TYPE_CIR 0
802 #define ICE_AQC_RL_PROFILE_TYPE_EIR 1
803 #define ICE_AQC_RL_PROFILE_TYPE_SRL 2
804 /* The following flag is used for Query RL Profile Data */
805 #define ICE_AQC_RL_PROFILE_INVAL_S 0x7
806 #define ICE_AQC_RL_PROFILE_INVAL_M (0x1 << ICE_AQC_RL_PROFILE_INVAL_S)
809 __le16 max_burst_size;
815 /* Query Scheduler Resource Allocation (indirect 0x0412)
816 * This indirect command retrieves the scheduler resources allocated by
817 * EMP Firmware to the given PF.
819 struct ice_aqc_query_txsched_res {
825 struct ice_aqc_generic_sched_props {
827 __le16 logical_levels;
828 u8 flattening_bitmap;
836 struct ice_aqc_layer_props {
839 __le16 max_device_nodes;
842 __le16 max_sibl_grp_sz;
843 __le16 max_cir_rl_profiles;
844 __le16 max_eir_rl_profiles;
845 __le16 max_srl_profiles;
849 struct ice_aqc_query_txsched_res_resp {
850 struct ice_aqc_generic_sched_props sched_props;
851 struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM];
854 /* Get PHY capabilities (indirect 0x0600) */
855 struct ice_aqc_get_phy_caps {
859 /* 18.0 - Report qualified modules */
860 #define ICE_AQC_GET_PHY_RQM BIT(0)
861 /* 18.1 - 18.2 : Report mode
862 * 00b - Report NVM capabilities
863 * 01b - Report topology capabilities
864 * 10b - Report SW configured
866 #define ICE_AQC_REPORT_MODE_S 1
867 #define ICE_AQC_REPORT_MODE_M (3 << ICE_AQC_REPORT_MODE_S)
868 #define ICE_AQC_REPORT_NVM_CAP 0
869 #define ICE_AQC_REPORT_TOPO_CAP BIT(1)
870 #define ICE_AQC_REPORT_SW_CFG BIT(2)
876 /* This is #define of PHY type (Extended):
877 * The first set of defines is for phy_type_low.
879 #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0)
880 #define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1)
881 #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2)
882 #define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3)
883 #define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4)
884 #define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5)
885 #define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6)
886 #define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7)
887 #define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8)
888 #define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9)
889 #define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10)
890 #define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11)
891 #define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12)
892 #define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13)
893 #define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14)
894 #define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15)
895 #define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16)
896 #define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17)
897 #define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18)
898 #define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19)
899 #define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20)
900 #define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21)
901 #define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22)
902 #define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23)
903 #define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24)
904 #define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25)
905 #define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26)
906 #define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27)
907 #define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28)
908 #define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29)
909 #define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30)
910 #define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31)
911 #define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32)
912 #define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33)
913 #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34)
914 #define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35)
915 #define ICE_PHY_TYPE_LOW_50GBASE_CR2 BIT_ULL(36)
916 #define ICE_PHY_TYPE_LOW_50GBASE_SR2 BIT_ULL(37)
917 #define ICE_PHY_TYPE_LOW_50GBASE_LR2 BIT_ULL(38)
918 #define ICE_PHY_TYPE_LOW_50GBASE_KR2 BIT_ULL(39)
919 #define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC BIT_ULL(40)
920 #define ICE_PHY_TYPE_LOW_50G_LAUI2 BIT_ULL(41)
921 #define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC BIT_ULL(42)
922 #define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43)
923 #define ICE_PHY_TYPE_LOW_50GBASE_CP BIT_ULL(44)
924 #define ICE_PHY_TYPE_LOW_50GBASE_SR BIT_ULL(45)
925 #define ICE_PHY_TYPE_LOW_50GBASE_FR BIT_ULL(46)
926 #define ICE_PHY_TYPE_LOW_50GBASE_LR BIT_ULL(47)
927 #define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 BIT_ULL(48)
928 #define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC BIT_ULL(49)
929 #define ICE_PHY_TYPE_LOW_50G_AUI1 BIT_ULL(50)
930 #define ICE_PHY_TYPE_LOW_100GBASE_CR4 BIT_ULL(51)
931 #define ICE_PHY_TYPE_LOW_100GBASE_SR4 BIT_ULL(52)
932 #define ICE_PHY_TYPE_LOW_100GBASE_LR4 BIT_ULL(53)
933 #define ICE_PHY_TYPE_LOW_100GBASE_KR4 BIT_ULL(54)
934 #define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC BIT_ULL(55)
935 #define ICE_PHY_TYPE_LOW_100G_CAUI4 BIT_ULL(56)
936 #define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC BIT_ULL(57)
937 #define ICE_PHY_TYPE_LOW_100G_AUI4 BIT_ULL(58)
938 #define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 BIT_ULL(59)
939 #define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 BIT_ULL(60)
940 #define ICE_PHY_TYPE_LOW_100GBASE_CP2 BIT_ULL(61)
941 #define ICE_PHY_TYPE_LOW_100GBASE_SR2 BIT_ULL(62)
942 #define ICE_PHY_TYPE_LOW_100GBASE_DR BIT_ULL(63)
943 #define ICE_PHY_TYPE_LOW_MAX_INDEX 63
944 /* The second set of defines is for phy_type_high. */
945 #define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 BIT_ULL(0)
946 #define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC BIT_ULL(1)
947 #define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2)
948 #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3)
949 #define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4)
950 #define ICE_PHY_TYPE_HIGH_MAX_INDEX 5
952 struct ice_aqc_get_phy_caps_data {
953 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
954 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
956 #define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0)
957 #define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1)
958 #define ICE_AQC_PHY_LOW_POWER_MODE BIT(2)
959 #define ICE_AQC_PHY_EN_LINK BIT(3)
960 #define ICE_AQC_PHY_AN_MODE BIT(4)
961 #define ICE_AQC_GET_PHY_EN_MOD_QUAL BIT(5)
962 #define ICE_AQC_PHY_EN_AUTO_FEC BIT(7)
963 #define ICE_AQC_PHY_CAPS_MASK ICE_M(0xff, 0)
964 u8 low_power_ctrl_an;
965 #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0)
966 #define ICE_AQC_PHY_AN_EN_CLAUSE28 BIT(1)
967 #define ICE_AQC_PHY_AN_EN_CLAUSE73 BIT(2)
968 #define ICE_AQC_PHY_AN_EN_CLAUSE37 BIT(3)
970 #define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0)
971 #define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1)
972 #define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2)
973 #define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3)
974 #define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4)
975 #define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5)
976 #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6)
978 u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */
981 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0)
982 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1)
983 #define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2)
984 #define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3)
985 #define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4)
986 #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6)
987 #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7)
988 #define ICE_AQC_PHY_FEC_MASK ICE_M(0xdf, 0)
989 u8 module_compliance_enforcement;
990 #define ICE_AQC_MOD_ENFORCE_STRICT_MODE BIT(0)
991 u8 extended_compliance_code;
992 #define ICE_MODULE_TYPE_TOTAL_BYTE 3
993 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
994 #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0
995 #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80
996 #define ICE_AQC_MOD_TYPE_IDENT 1
997 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0)
998 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1)
999 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4)
1000 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5)
1001 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6)
1002 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7)
1003 #define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0
1004 #define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86
1005 u8 qualified_module_count;
1006 u8 rsvd2[7]; /* Bytes 47:41 reserved */
1007 #define ICE_AQC_QUAL_MOD_COUNT_MAX 16
1014 } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX];
1017 /* Set PHY capabilities (direct 0x0601)
1018 * NOTE: This command must be followed by setup link and restart auto-neg
1020 struct ice_aqc_set_phy_cfg {
1027 /* Set PHY config command data structure */
1028 struct ice_aqc_set_phy_cfg_data {
1029 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1030 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1032 #define ICE_AQ_PHY_ENA_VALID_MASK ICE_M(0xef, 0)
1033 #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0)
1034 #define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1)
1035 #define ICE_AQ_PHY_ENA_LOW_POWER BIT(2)
1036 #define ICE_AQ_PHY_ENA_LINK BIT(3)
1037 #define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5)
1038 #define ICE_AQ_PHY_ENA_LESM BIT(6)
1039 #define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7)
1040 u8 low_power_ctrl_an;
1041 __le16 eee_cap; /* Value from ice_aqc_get_phy_caps */
1043 u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */
1044 u8 module_compliance_enforcement;
1047 /* Set MAC Config command data structure (direct 0x0603) */
1048 struct ice_aqc_set_mac_cfg {
1049 __le16 max_frame_size;
1051 #define ICE_AQ_SET_MAC_PACE_S 3
1052 #define ICE_AQ_SET_MAC_PACE_M (0xF << ICE_AQ_SET_MAC_PACE_S)
1053 #define ICE_AQ_SET_MAC_PACE_TYPE_M BIT(7)
1054 #define ICE_AQ_SET_MAC_PACE_TYPE_RATE 0
1055 #define ICE_AQ_SET_MAC_PACE_TYPE_FIXED ICE_AQ_SET_MAC_PACE_TYPE_M
1057 __le16 tx_tmr_value;
1058 __le16 fc_refresh_threshold;
1060 #define ICE_AQ_SET_MAC_AUTO_DROP_MASK BIT(0)
1061 #define ICE_AQ_SET_MAC_AUTO_DROP_NONE 0
1062 #define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS BIT(0)
1066 /* Restart AN command data structure (direct 0x0605)
1067 * Also used for response, with only the lport_num field present.
1069 struct ice_aqc_restart_an {
1073 #define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1)
1074 #define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2)
1078 /* Get link status (indirect 0x0607), also used for Link Status Event */
1079 struct ice_aqc_get_link_status {
1083 #define ICE_AQ_LSE_M 0x3
1084 #define ICE_AQ_LSE_NOP 0x0
1085 #define ICE_AQ_LSE_DIS 0x2
1086 #define ICE_AQ_LSE_ENA 0x3
1087 /* only response uses this flag */
1088 #define ICE_AQ_LSE_IS_ENABLED 0x1
1094 /* Get link status response data structure, also used for Link Status Event */
1095 struct ice_aqc_get_link_status_data {
1096 u8 topo_media_conflict;
1097 #define ICE_AQ_LINK_TOPO_CONFLICT BIT(0)
1098 #define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1)
1099 #define ICE_AQ_LINK_TOPO_CORRUPT BIT(2)
1100 #define ICE_AQ_LINK_TOPO_UNREACH_PRT BIT(4)
1101 #define ICE_AQ_LINK_TOPO_UNDRUTIL_PRT BIT(5)
1102 #define ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA BIT(6)
1103 #define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA BIT(7)
1106 #define ICE_AQ_LINK_UP BIT(0) /* Link Status */
1107 #define ICE_AQ_LINK_FAULT BIT(1)
1108 #define ICE_AQ_LINK_FAULT_TX BIT(2)
1109 #define ICE_AQ_LINK_FAULT_RX BIT(3)
1110 #define ICE_AQ_LINK_FAULT_REMOTE BIT(4)
1111 #define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */
1112 #define ICE_AQ_MEDIA_AVAILABLE BIT(6)
1113 #define ICE_AQ_SIGNAL_DETECT BIT(7)
1115 #define ICE_AQ_AN_COMPLETED BIT(0)
1116 #define ICE_AQ_LP_AN_ABILITY BIT(1)
1117 #define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */
1118 #define ICE_AQ_FEC_EN BIT(3)
1119 #define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */
1120 #define ICE_AQ_LINK_PAUSE_TX BIT(5)
1121 #define ICE_AQ_LINK_PAUSE_RX BIT(6)
1122 #define ICE_AQ_QUALIFIED_MODULE BIT(7)
1124 #define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0)
1125 #define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */
1126 /* Port Tx Suspended */
1127 #define ICE_AQ_LINK_TX_S 2
1128 #define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S)
1129 #define ICE_AQ_LINK_TX_ACTIVE 0
1130 #define ICE_AQ_LINK_TX_DRAINED 1
1131 #define ICE_AQ_LINK_TX_FLUSHED 3
1133 __le16 max_frame_size;
1135 #define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0)
1136 #define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1)
1137 #define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2)
1138 #define ICE_AQ_FEC_MASK ICE_M(0x7, 0)
1140 #define ICE_AQ_CFG_PACING_S 3
1141 #define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S)
1142 #define ICE_AQ_CFG_PACING_TYPE_M BIT(7)
1143 #define ICE_AQ_CFG_PACING_TYPE_AVG 0
1144 #define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M
1145 /* External Device Power Ability */
1147 #define ICE_AQ_PWR_CLASS_M 0x3
1148 #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0
1149 #define ICE_AQ_LINK_PWR_BASET_HIGH 1
1150 #define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0
1151 #define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1
1152 #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2
1153 #define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3
1155 #define ICE_AQ_LINK_SPEED_M 0x7FF
1156 #define ICE_AQ_LINK_SPEED_10MB BIT(0)
1157 #define ICE_AQ_LINK_SPEED_100MB BIT(1)
1158 #define ICE_AQ_LINK_SPEED_1000MB BIT(2)
1159 #define ICE_AQ_LINK_SPEED_2500MB BIT(3)
1160 #define ICE_AQ_LINK_SPEED_5GB BIT(4)
1161 #define ICE_AQ_LINK_SPEED_10GB BIT(5)
1162 #define ICE_AQ_LINK_SPEED_20GB BIT(6)
1163 #define ICE_AQ_LINK_SPEED_25GB BIT(7)
1164 #define ICE_AQ_LINK_SPEED_40GB BIT(8)
1165 #define ICE_AQ_LINK_SPEED_50GB BIT(9)
1166 #define ICE_AQ_LINK_SPEED_100GB BIT(10)
1167 #define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15)
1168 __le32 reserved3; /* Aligns next field to 8-byte boundary */
1169 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1170 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1173 /* Set event mask command (direct 0x0613) */
1174 struct ice_aqc_set_event_mask {
1178 #define ICE_AQ_LINK_EVENT_UPDOWN BIT(1)
1179 #define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2)
1180 #define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3)
1181 #define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4)
1182 #define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5)
1183 #define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6)
1184 #define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7)
1185 #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8)
1186 #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9)
1190 /* Set MAC Loopback command (direct 0x0620) */
1191 struct ice_aqc_set_mac_lb {
1193 #define ICE_AQ_MAC_LB_EN BIT(0)
1194 #define ICE_AQ_MAC_LB_OSC_CLK BIT(1)
1198 struct ice_aqc_link_topo_addr {
1201 #define ICE_AQC_LINK_TOPO_PORT_NUM_VALID BIT(0)
1203 #define ICE_AQC_LINK_TOPO_NODE_TYPE_S 0
1204 #define ICE_AQC_LINK_TOPO_NODE_TYPE_M (0xF << ICE_AQC_LINK_TOPO_NODE_TYPE_S)
1205 #define ICE_AQC_LINK_TOPO_NODE_TYPE_PHY 0
1206 #define ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL 1
1207 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MUX_CTRL 2
1208 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED_CTRL 3
1209 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED 4
1210 #define ICE_AQC_LINK_TOPO_NODE_TYPE_THERMAL 5
1211 #define ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE 6
1212 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MEZZ 7
1213 #define ICE_AQC_LINK_TOPO_NODE_TYPE_ID_EEPROM 8
1214 #define ICE_AQC_LINK_TOPO_NODE_CTX_S 4
1215 #define ICE_AQC_LINK_TOPO_NODE_CTX_M \
1216 (0xF << ICE_AQC_LINK_TOPO_NODE_CTX_S)
1217 #define ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL 0
1218 #define ICE_AQC_LINK_TOPO_NODE_CTX_BOARD 1
1219 #define ICE_AQC_LINK_TOPO_NODE_CTX_PORT 2
1220 #define ICE_AQC_LINK_TOPO_NODE_CTX_NODE 3
1221 #define ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED 4
1222 #define ICE_AQC_LINK_TOPO_NODE_CTX_OVERRIDE 5
1225 #define ICE_AQC_LINK_TOPO_HANDLE_S 0
1226 #define ICE_AQC_LINK_TOPO_HANDLE_M (0x3FF << ICE_AQC_LINK_TOPO_HANDLE_S)
1227 /* Used to decode the handle field */
1228 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_M BIT(9)
1229 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_LOM BIT(9)
1230 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ 0
1231 #define ICE_AQC_LINK_TOPO_HANDLE_NODE_S 0
1232 /* In case of a Mezzanine type */
1233 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_NODE_M \
1234 (0x3F << ICE_AQC_LINK_TOPO_HANDLE_NODE_S)
1235 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S 6
1236 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_M (0x7 << ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S)
1237 /* In case of a LOM type */
1238 #define ICE_AQC_LINK_TOPO_HANDLE_LOM_NODE_M \
1239 (0x1FF << ICE_AQC_LINK_TOPO_HANDLE_NODE_S)
1242 /* Get Link Topology Handle (direct, 0x06E0) */
1243 struct ice_aqc_get_link_topo {
1244 struct ice_aqc_link_topo_addr addr;
1249 /* Set Port Identification LED (direct, 0x06E9) */
1250 struct ice_aqc_set_port_id_led {
1254 #define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0)
1255 #define ICE_AQC_PORT_IDENT_LED_ORIG 0
1259 /* Read/Write SFF EEPROM command (indirect 0x06EE) */
1260 struct ice_aqc_sff_eeprom {
1263 #define ICE_AQC_SFF_PORT_NUM_VALID BIT(0)
1264 __le16 i2c_bus_addr;
1265 #define ICE_AQC_SFF_I2CBUS_7BIT_M 0x7F
1266 #define ICE_AQC_SFF_I2CBUS_10BIT_M 0x3FF
1267 #define ICE_AQC_SFF_I2CBUS_TYPE_M BIT(10)
1268 #define ICE_AQC_SFF_I2CBUS_TYPE_7BIT 0
1269 #define ICE_AQC_SFF_I2CBUS_TYPE_10BIT ICE_AQC_SFF_I2CBUS_TYPE_M
1270 #define ICE_AQC_SFF_SET_EEPROM_PAGE_S 11
1271 #define ICE_AQC_SFF_SET_EEPROM_PAGE_M (0x3 << ICE_AQC_SFF_SET_EEPROM_PAGE_S)
1272 #define ICE_AQC_SFF_NO_PAGE_CHANGE 0
1273 #define ICE_AQC_SFF_SET_23_ON_MISMATCH 1
1274 #define ICE_AQC_SFF_SET_22_ON_MISMATCH 2
1275 #define ICE_AQC_SFF_IS_WRITE BIT(15)
1276 __le16 i2c_mem_addr;
1278 #define ICE_AQC_SFF_EEPROM_BANK_S 0
1279 #define ICE_AQC_SFF_EEPROM_BANK_M (0xFF << ICE_AQC_SFF_EEPROM_BANK_S)
1280 #define ICE_AQC_SFF_EEPROM_PAGE_S 8
1281 #define ICE_AQC_SFF_EEPROM_PAGE_M (0xFF << ICE_AQC_SFF_EEPROM_PAGE_S)
1286 /* NVM Read command (indirect 0x0701)
1287 * NVM Erase commands (direct 0x0702)
1288 * NVM Update commands (indirect 0x0703)
1290 struct ice_aqc_nvm {
1291 #define ICE_AQC_NVM_MAX_OFFSET 0xFFFFFF
1295 #define ICE_AQC_NVM_LAST_CMD BIT(0)
1296 #define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Update reply */
1297 #define ICE_AQC_NVM_PRESERVATION_S 1
1298 #define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S)
1299 #define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S)
1300 #define ICE_AQC_NVM_PRESERVE_ALL BIT(1)
1301 #define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S)
1302 #define ICE_AQC_NVM_FLASH_ONLY BIT(7)
1303 __le16 module_typeid;
1305 #define ICE_AQC_NVM_ERASE_LEN 0xFFFF
1310 #define ICE_AQC_NVM_START_POINT 0
1312 /* NVM Checksum Command (direct, 0x0706) */
1313 struct ice_aqc_nvm_checksum {
1315 #define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0)
1316 #define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1)
1318 __le16 checksum; /* Used only by response */
1319 #define ICE_AQC_NVM_CHECKSUM_CORRECT 0xBABA
1323 /* The result of netlist NVM read comes in a TLV format. The actual data
1324 * (netlist header) starts from word offset 1 (byte 2). The FW strips
1325 * out the type field from the TLV header so all the netlist fields
1326 * should adjust their offset value by 1 word (2 bytes) in order to map
1327 * their correct location.
1329 #define ICE_AQC_NVM_LINK_TOPO_NETLIST_MOD_ID 0x11B
1330 #define ICE_AQC_NVM_LINK_TOPO_NETLIST_LEN_OFFSET 1
1331 #define ICE_AQC_NVM_LINK_TOPO_NETLIST_LEN 2 /* In bytes */
1332 #define ICE_AQC_NVM_NETLIST_NODE_COUNT_OFFSET 2
1333 #define ICE_AQC_NVM_NETLIST_NODE_COUNT_LEN 2 /* In bytes */
1334 #define ICE_AQC_NVM_NETLIST_NODE_COUNT_M ICE_M(0x3FF, 0)
1335 #define ICE_AQC_NVM_NETLIST_ID_BLK_START_OFFSET 5
1336 #define ICE_AQC_NVM_NETLIST_ID_BLK_LEN 0x30 /* In words */
1338 /* netlist ID block field offsets (word offsets) */
1339 #define ICE_AQC_NVM_NETLIST_ID_BLK_MAJOR_VER_LOW 2
1340 #define ICE_AQC_NVM_NETLIST_ID_BLK_MAJOR_VER_HIGH 3
1341 #define ICE_AQC_NVM_NETLIST_ID_BLK_MINOR_VER_LOW 4
1342 #define ICE_AQC_NVM_NETLIST_ID_BLK_MINOR_VER_HIGH 5
1343 #define ICE_AQC_NVM_NETLIST_ID_BLK_TYPE_LOW 6
1344 #define ICE_AQC_NVM_NETLIST_ID_BLK_TYPE_HIGH 7
1345 #define ICE_AQC_NVM_NETLIST_ID_BLK_REV_LOW 8
1346 #define ICE_AQC_NVM_NETLIST_ID_BLK_REV_HIGH 9
1347 #define ICE_AQC_NVM_NETLIST_ID_BLK_SHA_HASH 0xA
1348 #define ICE_AQC_NVM_NETLIST_ID_BLK_CUST_VER 0x2F
1351 * Send to PF command (indirect 0x0801) ID is only used by PF
1353 * Send to VF command (indirect 0x0802) ID is only used by PF
1356 struct ice_aqc_pf_vf_msg {
1363 /* Get LLDP MIB (indirect 0x0A00)
1364 * Note: This is also used by the LLDP MIB Change Event (0x0A01)
1365 * as the format is the same.
1367 struct ice_aqc_lldp_get_mib {
1369 #define ICE_AQ_LLDP_MIB_TYPE_S 0
1370 #define ICE_AQ_LLDP_MIB_TYPE_M (0x3 << ICE_AQ_LLDP_MIB_TYPE_S)
1371 #define ICE_AQ_LLDP_MIB_LOCAL 0
1372 #define ICE_AQ_LLDP_MIB_REMOTE 1
1373 #define ICE_AQ_LLDP_MIB_LOCAL_AND_REMOTE 2
1374 #define ICE_AQ_LLDP_BRID_TYPE_S 2
1375 #define ICE_AQ_LLDP_BRID_TYPE_M (0x3 << ICE_AQ_LLDP_BRID_TYPE_S)
1376 #define ICE_AQ_LLDP_BRID_TYPE_NEAREST_BRID 0
1377 #define ICE_AQ_LLDP_BRID_TYPE_NON_TPMR 1
1378 /* Tx pause flags in the 0xA01 event use ICE_AQ_LLDP_TX_* */
1379 #define ICE_AQ_LLDP_TX_S 0x4
1380 #define ICE_AQ_LLDP_TX_M (0x03 << ICE_AQ_LLDP_TX_S)
1381 #define ICE_AQ_LLDP_TX_ACTIVE 0
1382 #define ICE_AQ_LLDP_TX_SUSPENDED 1
1383 #define ICE_AQ_LLDP_TX_FLUSHED 3
1384 /* The following bytes are reserved for the Get LLDP MIB command (0x0A00)
1385 * and in the LLDP MIB Change Event (0x0A01). They are valid for the
1386 * Get LLDP MIB (0x0A00) response only.
1396 /* Configure LLDP MIB Change Event (direct 0x0A01) */
1397 /* For MIB Change Event use ice_aqc_lldp_get_mib structure above */
1398 struct ice_aqc_lldp_set_mib_change {
1400 #define ICE_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
1401 #define ICE_AQ_LLDP_MIB_UPDATE_DIS 0x1
1405 /* Stop LLDP (direct 0x0A05) */
1406 struct ice_aqc_lldp_stop {
1408 #define ICE_AQ_LLDP_AGENT_STATE_MASK BIT(0)
1409 #define ICE_AQ_LLDP_AGENT_STOP 0x0
1410 #define ICE_AQ_LLDP_AGENT_SHUTDOWN ICE_AQ_LLDP_AGENT_STATE_MASK
1411 #define ICE_AQ_LLDP_AGENT_PERSIST_DIS BIT(1)
1415 /* Start LLDP (direct 0x0A06) */
1416 struct ice_aqc_lldp_start {
1418 #define ICE_AQ_LLDP_AGENT_START BIT(0)
1419 #define ICE_AQ_LLDP_AGENT_PERSIST_ENA BIT(1)
1423 /* Get CEE DCBX Oper Config (0x0A07)
1424 * The command uses the generic descriptor struct and
1425 * returns the struct below as an indirect response.
1427 struct ice_aqc_get_cee_dcb_cfg_resp {
1432 __le16 oper_app_prio;
1433 #define ICE_AQC_CEE_APP_FCOE_S 0
1434 #define ICE_AQC_CEE_APP_FCOE_M (0x7 << ICE_AQC_CEE_APP_FCOE_S)
1435 #define ICE_AQC_CEE_APP_ISCSI_S 3
1436 #define ICE_AQC_CEE_APP_ISCSI_M (0x7 << ICE_AQC_CEE_APP_ISCSI_S)
1437 #define ICE_AQC_CEE_APP_FIP_S 8
1438 #define ICE_AQC_CEE_APP_FIP_M (0x7 << ICE_AQC_CEE_APP_FIP_S)
1440 #define ICE_AQC_CEE_PG_STATUS_S 0
1441 #define ICE_AQC_CEE_PG_STATUS_M (0x7 << ICE_AQC_CEE_PG_STATUS_S)
1442 #define ICE_AQC_CEE_PFC_STATUS_S 3
1443 #define ICE_AQC_CEE_PFC_STATUS_M (0x7 << ICE_AQC_CEE_PFC_STATUS_S)
1444 #define ICE_AQC_CEE_FCOE_STATUS_S 8
1445 #define ICE_AQC_CEE_FCOE_STATUS_M (0x7 << ICE_AQC_CEE_FCOE_STATUS_S)
1446 #define ICE_AQC_CEE_ISCSI_STATUS_S 11
1447 #define ICE_AQC_CEE_ISCSI_STATUS_M (0x7 << ICE_AQC_CEE_ISCSI_STATUS_S)
1448 #define ICE_AQC_CEE_FIP_STATUS_S 16
1449 #define ICE_AQC_CEE_FIP_STATUS_M (0x7 << ICE_AQC_CEE_FIP_STATUS_S)
1453 /* Set Local LLDP MIB (indirect 0x0A08)
1454 * Used to replace the local MIB of a given LLDP agent. e.g. DCBX
1456 struct ice_aqc_lldp_set_local_mib {
1458 #define SET_LOCAL_MIB_TYPE_DCBX_M BIT(0)
1459 #define SET_LOCAL_MIB_TYPE_LOCAL_MIB 0
1460 #define SET_LOCAL_MIB_TYPE_CEE_M BIT(1)
1461 #define SET_LOCAL_MIB_TYPE_CEE_WILLING 0
1462 #define SET_LOCAL_MIB_TYPE_CEE_NON_WILLING SET_LOCAL_MIB_TYPE_CEE_M
1470 /* Stop/Start LLDP Agent (direct 0x0A09)
1471 * Used for stopping/starting specific LLDP agent. e.g. DCBX.
1472 * The same structure is used for the response, with the command field
1473 * being used as the status field.
1475 struct ice_aqc_lldp_stop_start_specific_agent {
1477 #define ICE_AQC_START_STOP_AGENT_M BIT(0)
1478 #define ICE_AQC_START_STOP_AGENT_STOP_DCBX 0
1479 #define ICE_AQC_START_STOP_AGENT_START_DCBX ICE_AQC_START_STOP_AGENT_M
1483 /* Get/Set RSS key (indirect 0x0B04/0x0B02) */
1484 struct ice_aqc_get_set_rss_key {
1485 #define ICE_AQC_GSET_RSS_KEY_VSI_VALID BIT(15)
1486 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_S 0
1487 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_KEY_VSI_ID_S)
1494 #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28
1495 #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC
1496 #define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE \
1497 (ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE + \
1498 ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE)
1500 struct ice_aqc_get_set_rss_keys {
1501 u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE];
1502 u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE];
1505 /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */
1506 struct ice_aqc_get_set_rss_lut {
1507 #define ICE_AQC_GSET_RSS_LUT_VSI_VALID BIT(15)
1508 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_S 0
1509 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_M (0x1FF << ICE_AQC_GSET_RSS_LUT_VSI_ID_S)
1511 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S 0
1512 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M \
1513 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S)
1515 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI 0
1516 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF 1
1517 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL 2
1519 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S 2
1520 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M \
1521 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S)
1523 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 128
1524 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG 0
1525 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 512
1526 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG 1
1527 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K 2048
1528 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG 2
1530 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S 4
1531 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M \
1532 (0xF << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S)
1540 /* Add Tx LAN Queues (indirect 0x0C30) */
1541 struct ice_aqc_add_txqs {
1549 /* This is the descriptor of each queue entry for the Add Tx LAN Queues
1550 * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp.
1552 struct ice_aqc_add_txqs_perq {
1558 struct ice_aqc_txsched_elem info;
1561 /* The format of the command buffer for Add Tx LAN Queues (0x0C30)
1562 * is an array of the following structs. Please note that the length of
1563 * each struct ice_aqc_add_tx_qgrp is variable due
1564 * to the variable number of queues in each group!
1566 struct ice_aqc_add_tx_qgrp {
1570 struct ice_aqc_add_txqs_perq txqs[];
1573 /* Disable Tx LAN Queues (indirect 0x0C31) */
1574 struct ice_aqc_dis_txqs {
1576 #define ICE_AQC_Q_DIS_CMD_S 0
1577 #define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S)
1578 #define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S)
1579 #define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S)
1580 #define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S)
1581 #define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S)
1582 #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2)
1583 #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3)
1585 __le16 vmvf_and_timeout;
1586 #define ICE_AQC_Q_DIS_VMVF_NUM_S 0
1587 #define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S)
1588 #define ICE_AQC_Q_DIS_TIMEOUT_S 10
1589 #define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S)
1590 __le32 blocked_cgds;
1595 /* The buffer for Disable Tx LAN Queues (indirect 0x0C31)
1596 * contains the following structures, arrayed one after the
1598 * Note: Since the q_id is 16 bits wide, if the
1599 * number of queues is even, then 2 bytes of alignment MUST be
1600 * added before the start of the next group, to allow correct
1601 * alignment of the parent_teid field.
1603 struct ice_aqc_dis_txq_item {
1607 /* The length of the q_id array varies according to num_qs */
1608 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15
1609 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \
1610 (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)
1611 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \
1612 (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)
1616 /* Configure Firmware Logging Command (indirect 0xFF09)
1617 * Logging Information Read Response (indirect 0xFF10)
1618 * Note: The 0xFF10 command has no input parameters.
1620 struct ice_aqc_fw_logging {
1622 #define ICE_AQC_FW_LOG_AQ_EN BIT(0)
1623 #define ICE_AQC_FW_LOG_UART_EN BIT(1)
1625 u8 log_ctrl_valid; /* Not used by 0xFF10 Response */
1626 #define ICE_AQC_FW_LOG_AQ_VALID BIT(0)
1627 #define ICE_AQC_FW_LOG_UART_VALID BIT(1)
1633 enum ice_aqc_fw_logging_mod {
1634 ICE_AQC_FW_LOG_ID_GENERAL = 0,
1635 ICE_AQC_FW_LOG_ID_CTRL,
1636 ICE_AQC_FW_LOG_ID_LINK,
1637 ICE_AQC_FW_LOG_ID_LINK_TOPO,
1638 ICE_AQC_FW_LOG_ID_DNL,
1639 ICE_AQC_FW_LOG_ID_I2C,
1640 ICE_AQC_FW_LOG_ID_SDP,
1641 ICE_AQC_FW_LOG_ID_MDIO,
1642 ICE_AQC_FW_LOG_ID_ADMINQ,
1643 ICE_AQC_FW_LOG_ID_HDMA,
1644 ICE_AQC_FW_LOG_ID_LLDP,
1645 ICE_AQC_FW_LOG_ID_DCBX,
1646 ICE_AQC_FW_LOG_ID_DCB,
1647 ICE_AQC_FW_LOG_ID_NETPROXY,
1648 ICE_AQC_FW_LOG_ID_NVM,
1649 ICE_AQC_FW_LOG_ID_AUTH,
1650 ICE_AQC_FW_LOG_ID_VPD,
1651 ICE_AQC_FW_LOG_ID_IOSF,
1652 ICE_AQC_FW_LOG_ID_PARSER,
1653 ICE_AQC_FW_LOG_ID_SW,
1654 ICE_AQC_FW_LOG_ID_SCHEDULER,
1655 ICE_AQC_FW_LOG_ID_TXQ,
1656 ICE_AQC_FW_LOG_ID_RSVD,
1657 ICE_AQC_FW_LOG_ID_POST,
1658 ICE_AQC_FW_LOG_ID_WATCHDOG,
1659 ICE_AQC_FW_LOG_ID_TASK_DISPATCH,
1660 ICE_AQC_FW_LOG_ID_MNG,
1661 ICE_AQC_FW_LOG_ID_MAX,
1664 /* Defines for both above FW logging command/response buffers */
1665 #define ICE_AQC_FW_LOG_ID_S 0
1666 #define ICE_AQC_FW_LOG_ID_M (0xFFF << ICE_AQC_FW_LOG_ID_S)
1668 #define ICE_AQC_FW_LOG_CONF_SUCCESS 0 /* Used by response */
1669 #define ICE_AQC_FW_LOG_CONF_BAD_INDX BIT(12) /* Used by response */
1671 #define ICE_AQC_FW_LOG_EN_S 12
1672 #define ICE_AQC_FW_LOG_EN_M (0xF << ICE_AQC_FW_LOG_EN_S)
1673 #define ICE_AQC_FW_LOG_INFO_EN BIT(12) /* Used by command */
1674 #define ICE_AQC_FW_LOG_INIT_EN BIT(13) /* Used by command */
1675 #define ICE_AQC_FW_LOG_FLOW_EN BIT(14) /* Used by command */
1676 #define ICE_AQC_FW_LOG_ERR_EN BIT(15) /* Used by command */
1678 /* Get/Clear FW Log (indirect 0xFF11) */
1679 struct ice_aqc_get_clear_fw_log {
1681 #define ICE_AQC_FW_LOG_CLEAR BIT(0)
1682 #define ICE_AQC_FW_LOG_MORE_DATA_AVAIL BIT(1)
1688 /* Download Package (indirect 0x0C40) */
1689 /* Also used for Update Package (indirect 0x0C42) */
1690 struct ice_aqc_download_pkg {
1692 #define ICE_AQC_DOWNLOAD_PKG_LAST_BUF 0x01
1699 struct ice_aqc_download_pkg_resp {
1700 __le32 error_offset;
1706 /* Get Package Info List (indirect 0x0C43) */
1707 struct ice_aqc_get_pkg_info_list {
1714 /* Version format for packages */
1715 struct ice_pkg_ver {
1722 #define ICE_PKG_NAME_SIZE 32
1723 #define ICE_SEG_NAME_SIZE 28
1725 struct ice_aqc_get_pkg_info {
1726 struct ice_pkg_ver ver;
1727 char name[ICE_SEG_NAME_SIZE];
1731 u8 is_active_at_boot;
1735 /* Get Package Info List response buffer format (0x0C43) */
1736 struct ice_aqc_get_pkg_info_resp {
1738 struct ice_aqc_get_pkg_info pkg_info[];
1741 /* Lan Queue Overflow Event (direct, 0x1001) */
1742 struct ice_aqc_event_lan_overflow {
1743 __le32 prtdcb_ruptq;
1749 * struct ice_aq_desc - Admin Queue (AQ) descriptor
1750 * @flags: ICE_AQ_FLAG_* flags
1751 * @opcode: AQ command opcode
1752 * @datalen: length in bytes of indirect/external data buffer
1753 * @retval: return value from firmware
1754 * @cookie_h: opaque data high-half
1755 * @cookie_l: opaque data low-half
1756 * @params: command-specific parameters
1758 * Descriptor format for commands the driver posts on the Admin Transmit Queue
1759 * (ATQ). The firmware writes back onto the command descriptor and returns
1760 * the result of the command. Asynchronous events that are not an immediate
1761 * result of the command are written to the Admin Receive Queue (ARQ) using
1762 * the same descriptor format. Descriptors are in little-endian notation with
1765 struct ice_aq_desc {
1774 struct ice_aqc_generic generic;
1775 struct ice_aqc_get_ver get_ver;
1776 struct ice_aqc_driver_ver driver_ver;
1777 struct ice_aqc_q_shutdown q_shutdown;
1778 struct ice_aqc_req_res res_owner;
1779 struct ice_aqc_manage_mac_read mac_read;
1780 struct ice_aqc_manage_mac_write mac_write;
1781 struct ice_aqc_clear_pxe clear_pxe;
1782 struct ice_aqc_list_caps get_cap;
1783 struct ice_aqc_get_phy_caps get_phy;
1784 struct ice_aqc_set_phy_cfg set_phy;
1785 struct ice_aqc_restart_an restart_an;
1786 struct ice_aqc_sff_eeprom read_write_sff_param;
1787 struct ice_aqc_set_port_id_led set_port_id_led;
1788 struct ice_aqc_get_sw_cfg get_sw_conf;
1789 struct ice_aqc_sw_rules sw_rules;
1790 struct ice_aqc_get_topo get_topo;
1791 struct ice_aqc_sched_elem_cmd sched_elem_cmd;
1792 struct ice_aqc_query_txsched_res query_sched_res;
1793 struct ice_aqc_query_port_ets port_ets;
1794 struct ice_aqc_rl_profile rl_profile;
1795 struct ice_aqc_nvm nvm;
1796 struct ice_aqc_nvm_checksum nvm_checksum;
1797 struct ice_aqc_pf_vf_msg virt;
1798 struct ice_aqc_lldp_get_mib lldp_get_mib;
1799 struct ice_aqc_lldp_set_mib_change lldp_set_event;
1800 struct ice_aqc_lldp_stop lldp_stop;
1801 struct ice_aqc_lldp_start lldp_start;
1802 struct ice_aqc_lldp_set_local_mib lldp_set_mib;
1803 struct ice_aqc_lldp_stop_start_specific_agent lldp_agent_ctrl;
1804 struct ice_aqc_get_set_rss_lut get_set_rss_lut;
1805 struct ice_aqc_get_set_rss_key get_set_rss_key;
1806 struct ice_aqc_add_txqs add_txqs;
1807 struct ice_aqc_dis_txqs dis_txqs;
1808 struct ice_aqc_add_get_update_free_vsi vsi_cmd;
1809 struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res;
1810 struct ice_aqc_fw_logging fw_logging;
1811 struct ice_aqc_get_clear_fw_log get_clear_fw_log;
1812 struct ice_aqc_download_pkg download_pkg;
1813 struct ice_aqc_set_mac_lb set_mac_lb;
1814 struct ice_aqc_alloc_free_res_cmd sw_res_ctrl;
1815 struct ice_aqc_set_mac_cfg set_mac_cfg;
1816 struct ice_aqc_set_event_mask set_event_mask;
1817 struct ice_aqc_get_link_status get_link_status;
1818 struct ice_aqc_event_lan_overflow lan_overflow;
1819 struct ice_aqc_get_link_topo get_link_topo;
1823 /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */
1824 #define ICE_AQ_LG_BUF 512
1826 #define ICE_AQ_FLAG_ERR_S 2
1827 #define ICE_AQ_FLAG_LB_S 9
1828 #define ICE_AQ_FLAG_RD_S 10
1829 #define ICE_AQ_FLAG_BUF_S 12
1830 #define ICE_AQ_FLAG_SI_S 13
1832 #define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */
1833 #define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */
1834 #define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */
1835 #define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */
1836 #define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */
1840 ICE_AQ_RC_OK = 0, /* Success */
1841 ICE_AQ_RC_EPERM = 1, /* Operation not permitted */
1842 ICE_AQ_RC_ENOENT = 2, /* No such element */
1843 ICE_AQ_RC_ENOMEM = 9, /* Out of memory */
1844 ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */
1845 ICE_AQ_RC_EEXIST = 13, /* Object already exists */
1846 ICE_AQ_RC_EINVAL = 14, /* Invalid argument */
1847 ICE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */
1848 ICE_AQ_RC_ENOSYS = 17, /* Function not implemented */
1849 ICE_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
1850 ICE_AQ_RC_ENOSEC = 24, /* Missing security manifest */
1851 ICE_AQ_RC_EBADSIG = 25, /* Bad RSA signature */
1852 ICE_AQ_RC_ESVN = 26, /* SVN number prohibits this package */
1853 ICE_AQ_RC_EBADMAN = 27, /* Manifest hash mismatch */
1854 ICE_AQ_RC_EBADBUF = 28, /* Buffer hash mismatches manifest */
1857 /* Admin Queue command opcodes */
1858 enum ice_adminq_opc {
1860 ice_aqc_opc_get_ver = 0x0001,
1861 ice_aqc_opc_driver_ver = 0x0002,
1862 ice_aqc_opc_q_shutdown = 0x0003,
1864 /* resource ownership */
1865 ice_aqc_opc_req_res = 0x0008,
1866 ice_aqc_opc_release_res = 0x0009,
1868 /* device/function capabilities */
1869 ice_aqc_opc_list_func_caps = 0x000A,
1870 ice_aqc_opc_list_dev_caps = 0x000B,
1872 /* manage MAC address */
1873 ice_aqc_opc_manage_mac_read = 0x0107,
1874 ice_aqc_opc_manage_mac_write = 0x0108,
1877 ice_aqc_opc_clear_pxe_mode = 0x0110,
1879 /* internal switch commands */
1880 ice_aqc_opc_get_sw_cfg = 0x0200,
1882 /* Alloc/Free/Get Resources */
1883 ice_aqc_opc_alloc_res = 0x0208,
1884 ice_aqc_opc_free_res = 0x0209,
1887 ice_aqc_opc_add_vsi = 0x0210,
1888 ice_aqc_opc_update_vsi = 0x0211,
1889 ice_aqc_opc_free_vsi = 0x0213,
1891 /* switch rules population commands */
1892 ice_aqc_opc_add_sw_rules = 0x02A0,
1893 ice_aqc_opc_update_sw_rules = 0x02A1,
1894 ice_aqc_opc_remove_sw_rules = 0x02A2,
1896 ice_aqc_opc_clear_pf_cfg = 0x02A4,
1898 /* transmit scheduler commands */
1899 ice_aqc_opc_get_dflt_topo = 0x0400,
1900 ice_aqc_opc_add_sched_elems = 0x0401,
1901 ice_aqc_opc_cfg_sched_elems = 0x0403,
1902 ice_aqc_opc_get_sched_elems = 0x0404,
1903 ice_aqc_opc_suspend_sched_elems = 0x0409,
1904 ice_aqc_opc_resume_sched_elems = 0x040A,
1905 ice_aqc_opc_query_port_ets = 0x040E,
1906 ice_aqc_opc_delete_sched_elems = 0x040F,
1907 ice_aqc_opc_add_rl_profiles = 0x0410,
1908 ice_aqc_opc_query_sched_res = 0x0412,
1909 ice_aqc_opc_remove_rl_profiles = 0x0415,
1912 ice_aqc_opc_get_phy_caps = 0x0600,
1913 ice_aqc_opc_set_phy_cfg = 0x0601,
1914 ice_aqc_opc_set_mac_cfg = 0x0603,
1915 ice_aqc_opc_restart_an = 0x0605,
1916 ice_aqc_opc_get_link_status = 0x0607,
1917 ice_aqc_opc_set_event_mask = 0x0613,
1918 ice_aqc_opc_set_mac_lb = 0x0620,
1919 ice_aqc_opc_get_link_topo = 0x06E0,
1920 ice_aqc_opc_set_port_id_led = 0x06E9,
1921 ice_aqc_opc_sff_eeprom = 0x06EE,
1924 ice_aqc_opc_nvm_read = 0x0701,
1925 ice_aqc_opc_nvm_checksum = 0x0706,
1927 /* PF/VF mailbox commands */
1928 ice_mbx_opc_send_msg_to_pf = 0x0801,
1929 ice_mbx_opc_send_msg_to_vf = 0x0802,
1931 ice_aqc_opc_lldp_get_mib = 0x0A00,
1932 ice_aqc_opc_lldp_set_mib_change = 0x0A01,
1933 ice_aqc_opc_lldp_stop = 0x0A05,
1934 ice_aqc_opc_lldp_start = 0x0A06,
1935 ice_aqc_opc_get_cee_dcb_cfg = 0x0A07,
1936 ice_aqc_opc_lldp_set_local_mib = 0x0A08,
1937 ice_aqc_opc_lldp_stop_start_specific_agent = 0x0A09,
1940 ice_aqc_opc_set_rss_key = 0x0B02,
1941 ice_aqc_opc_set_rss_lut = 0x0B03,
1942 ice_aqc_opc_get_rss_key = 0x0B04,
1943 ice_aqc_opc_get_rss_lut = 0x0B05,
1945 /* Tx queue handling commands/events */
1946 ice_aqc_opc_add_txqs = 0x0C30,
1947 ice_aqc_opc_dis_txqs = 0x0C31,
1949 /* package commands */
1950 ice_aqc_opc_download_pkg = 0x0C40,
1951 ice_aqc_opc_update_pkg = 0x0C42,
1952 ice_aqc_opc_get_pkg_info_list = 0x0C43,
1954 /* Standalone Commands/Events */
1955 ice_aqc_opc_event_lan_overflow = 0x1001,
1957 /* debug commands */
1958 ice_aqc_opc_fw_logging = 0xFF09,
1959 ice_aqc_opc_fw_logging_info = 0xFF10,
1962 #endif /* _ICE_ADMINQ_CMD_H_ */