1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018, Intel Corporation. */
4 #ifndef _ICE_ADMINQ_CMD_H_
5 #define _ICE_ADMINQ_CMD_H_
7 /* This header file defines the Admin Queue commands, error codes and
8 * descriptor format. It is shared between Firmware and Software.
11 #define ICE_MAX_VSI 768
12 #define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9
13 #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728
15 struct ice_aqc_generic {
22 /* Get version (direct 0x0001) */
23 struct ice_aqc_get_ver {
36 /* Send driver version (indirect 0x0002) */
37 struct ice_aqc_driver_ver {
47 /* Queue Shutdown (direct 0x0003) */
48 struct ice_aqc_q_shutdown {
50 #define ICE_AQC_DRIVER_UNLOADING BIT(0)
54 /* Request resource ownership (direct 0x0008)
55 * Release resource ownership (direct 0x0009)
57 struct ice_aqc_req_res {
59 #define ICE_AQC_RES_ID_NVM 1
60 #define ICE_AQC_RES_ID_SDP 2
61 #define ICE_AQC_RES_ID_CHNG_LOCK 3
62 #define ICE_AQC_RES_ID_GLBL_LOCK 4
64 #define ICE_AQC_RES_ACCESS_READ 1
65 #define ICE_AQC_RES_ACCESS_WRITE 2
67 /* Upon successful completion, FW writes this value and driver is
68 * expected to release resource before timeout. This value is provided
72 #define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000
73 #define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000
74 #define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000
75 #define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000
76 /* For SDP: pin ID of the SDP */
78 /* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */
80 #define ICE_AQ_RES_GLBL_SUCCESS 0
81 #define ICE_AQ_RES_GLBL_IN_PROG 1
82 #define ICE_AQ_RES_GLBL_DONE 2
86 /* Get function capabilities (indirect 0x000A)
87 * Get device capabilities (indirect 0x000B)
89 struct ice_aqc_list_caps {
98 /* Device/Function buffer entry, repeated per reported capability */
99 struct ice_aqc_list_caps_elem {
101 #define ICE_AQC_CAPS_VALID_FUNCTIONS 0x0005
102 #define ICE_AQC_CAPS_SRIOV 0x0012
103 #define ICE_AQC_CAPS_VF 0x0013
104 #define ICE_AQC_CAPS_VSI 0x0017
105 #define ICE_AQC_CAPS_DCB 0x0018
106 #define ICE_AQC_CAPS_RSS 0x0040
107 #define ICE_AQC_CAPS_RXQS 0x0041
108 #define ICE_AQC_CAPS_TXQS 0x0042
109 #define ICE_AQC_CAPS_MSIX 0x0043
110 #define ICE_AQC_CAPS_FD 0x0045
111 #define ICE_AQC_CAPS_1588 0x0046
112 #define ICE_AQC_CAPS_MAX_MTU 0x0047
113 #define ICE_AQC_CAPS_NVM_VER 0x0048
114 #define ICE_AQC_CAPS_PENDING_NVM_VER 0x0049
115 #define ICE_AQC_CAPS_OROM_VER 0x004A
116 #define ICE_AQC_CAPS_PENDING_OROM_VER 0x004B
117 #define ICE_AQC_CAPS_NET_VER 0x004C
118 #define ICE_AQC_CAPS_PENDING_NET_VER 0x004D
119 #define ICE_AQC_CAPS_RDMA 0x0051
120 #define ICE_AQC_CAPS_NVM_MGMT 0x0080
124 /* Number of resources described by this capability */
126 /* Only meaningful for some types of resources */
128 /* Only meaningful for some types of resources */
134 /* Manage MAC address, read command - indirect (0x0107)
135 * This struct is also used for the response
137 struct ice_aqc_manage_mac_read {
138 __le16 flags; /* Zeroed by device driver */
139 #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4)
140 #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5)
141 #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6)
142 #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7)
143 #define ICE_AQC_MAN_MAC_READ_S 4
144 #define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S)
146 u8 num_addr; /* Used in response */
152 /* Response buffer format for manage MAC read command */
153 struct ice_aqc_manage_mac_read_resp {
156 #define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0
157 #define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1
158 u8 mac_addr[ETH_ALEN];
161 /* Manage MAC address, write command - direct (0x0108) */
162 struct ice_aqc_manage_mac_write {
165 #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0)
166 #define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1)
167 #define ICE_AQC_MAN_MAC_WR_S 6
168 #define ICE_AQC_MAN_MAC_WR_M ICE_M(3, ICE_AQC_MAN_MAC_WR_S)
169 #define ICE_AQC_MAN_MAC_UPDATE_LAA 0
170 #define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL BIT(ICE_AQC_MAN_MAC_WR_S)
171 /* byte stream in network order */
172 u8 mac_addr[ETH_ALEN];
177 /* Clear PXE Command and response (direct 0x0110) */
178 struct ice_aqc_clear_pxe {
180 #define ICE_AQC_CLEAR_PXE_RX_CNT 0x2
184 /* Get switch configuration (0x0200) */
185 struct ice_aqc_get_sw_cfg {
186 /* Reserved for command and copy of request flags for response */
188 /* First desc in case of command and next_elem in case of response
189 * In case of response, if it is not zero, means all the configuration
190 * was not returned and new command shall be sent with this value in
191 * the 'first desc' field
194 /* Reserved for command, only used for response */
201 /* Each entry in the response buffer is of the following type: */
202 struct ice_aqc_get_sw_cfg_resp_elem {
203 /* VSI/Port Number */
205 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0
206 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \
207 (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S)
208 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14
209 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S)
210 #define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0
211 #define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1
212 #define ICE_AQC_GET_SW_CONF_RESP_VSI 2
214 /* SWID VSI/Port belongs to */
217 /* Bit 14..0 : PF/VF number VSI belongs to
218 * Bit 15 : VF indication bit
221 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0
222 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \
223 (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S)
224 #define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15)
227 /* These resource type defines are used for all switch resource
228 * commands where a resource type is required, such as:
229 * Get Resource Allocation command (indirect 0x0204)
230 * Allocate Resources command (indirect 0x0208)
231 * Free Resources command (indirect 0x0209)
232 * Get Allocated Resource Descriptors Command (indirect 0x020A)
234 #define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03
235 #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04
236 #define ICE_AQC_RES_TYPE_FDIR_COUNTER_BLOCK 0x21
237 #define ICE_AQC_RES_TYPE_FDIR_GUARANTEED_ENTRIES 0x22
238 #define ICE_AQC_RES_TYPE_FDIR_SHARED_ENTRIES 0x23
239 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID 0x58
240 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_TCAM 0x59
241 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID 0x60
242 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_TCAM 0x61
244 #define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM BIT(12)
245 #define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX BIT(13)
247 #define ICE_AQC_RES_TYPE_FLAG_DEDICATED 0x00
249 #define ICE_AQC_RES_TYPE_S 0
250 #define ICE_AQC_RES_TYPE_M (0x07F << ICE_AQC_RES_TYPE_S)
252 /* Allocate Resources command (indirect 0x0208)
253 * Free Resources command (indirect 0x0209)
255 struct ice_aqc_alloc_free_res_cmd {
256 __le16 num_entries; /* Number of Resource entries */
262 /* Resource descriptor */
263 struct ice_aqc_res_elem {
270 /* Buffer for Allocate/Free Resources commands */
271 struct ice_aqc_alloc_free_res_elem {
272 __le16 res_type; /* Types defined above cmd 0x0204 */
273 #define ICE_AQC_RES_TYPE_SHARED_S 7
274 #define ICE_AQC_RES_TYPE_SHARED_M (0x1 << ICE_AQC_RES_TYPE_SHARED_S)
275 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8
276 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \
277 (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S)
279 struct ice_aqc_res_elem elem[];
282 /* Add VSI (indirect 0x0210)
283 * Update VSI (indirect 0x0211)
284 * Get VSI (indirect 0x0212)
285 * Free VSI (indirect 0x0213)
287 struct ice_aqc_add_get_update_free_vsi {
289 #define ICE_AQ_VSI_NUM_S 0
290 #define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S)
291 #define ICE_AQ_VSI_IS_VALID BIT(15)
293 #define ICE_AQ_VSI_KEEP_ALLOC 0x1
297 #define ICE_AQ_VSI_TYPE_S 0
298 #define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S)
299 #define ICE_AQ_VSI_TYPE_VF 0x0
300 #define ICE_AQ_VSI_TYPE_VMDQ2 0x1
301 #define ICE_AQ_VSI_TYPE_PF 0x2
302 #define ICE_AQ_VSI_TYPE_EMP_MNG 0x3
307 /* Response descriptor for:
308 * Add VSI (indirect 0x0210)
309 * Update VSI (indirect 0x0211)
310 * Free VSI (indirect 0x0213)
312 struct ice_aqc_add_update_free_vsi_resp {
321 struct ice_aqc_vsi_props {
322 __le16 valid_sections;
323 #define ICE_AQ_VSI_PROP_SW_VALID BIT(0)
324 #define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1)
325 #define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2)
326 #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3)
327 #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4)
328 #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5)
329 #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6)
330 #define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7)
331 #define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8)
332 #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11)
333 #define ICE_AQ_VSI_PROP_PASID_VALID BIT(12)
337 #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5)
338 #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6)
339 #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7)
341 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0
342 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M \
343 (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S)
344 #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0)
345 #define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4)
347 #define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0
348 #define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S)
349 #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5)
350 /* security section */
352 #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0)
353 #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2)
354 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4
355 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S)
356 #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0)
359 __le16 pvid; /* VLANS include priority bits */
360 u8 pvlan_reserved[2];
362 #define ICE_AQ_VSI_VLAN_MODE_S 0
363 #define ICE_AQ_VSI_VLAN_MODE_M (0x3 << ICE_AQ_VSI_VLAN_MODE_S)
364 #define ICE_AQ_VSI_VLAN_MODE_UNTAGGED 0x1
365 #define ICE_AQ_VSI_VLAN_MODE_TAGGED 0x2
366 #define ICE_AQ_VSI_VLAN_MODE_ALL 0x3
367 #define ICE_AQ_VSI_PVLAN_INSERT_PVID BIT(2)
368 #define ICE_AQ_VSI_VLAN_EMOD_S 3
369 #define ICE_AQ_VSI_VLAN_EMOD_M (0x3 << ICE_AQ_VSI_VLAN_EMOD_S)
370 #define ICE_AQ_VSI_VLAN_EMOD_STR_BOTH (0x0 << ICE_AQ_VSI_VLAN_EMOD_S)
371 #define ICE_AQ_VSI_VLAN_EMOD_STR_UP (0x1 << ICE_AQ_VSI_VLAN_EMOD_S)
372 #define ICE_AQ_VSI_VLAN_EMOD_STR (0x2 << ICE_AQ_VSI_VLAN_EMOD_S)
373 #define ICE_AQ_VSI_VLAN_EMOD_NOTHING (0x3 << ICE_AQ_VSI_VLAN_EMOD_S)
374 u8 pvlan_reserved2[3];
375 /* ingress egress up sections */
376 __le32 ingress_table; /* bitmap, 3 bits per up */
377 #define ICE_AQ_VSI_UP_TABLE_UP0_S 0
378 #define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S)
379 #define ICE_AQ_VSI_UP_TABLE_UP1_S 3
380 #define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S)
381 #define ICE_AQ_VSI_UP_TABLE_UP2_S 6
382 #define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S)
383 #define ICE_AQ_VSI_UP_TABLE_UP3_S 9
384 #define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S)
385 #define ICE_AQ_VSI_UP_TABLE_UP4_S 12
386 #define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S)
387 #define ICE_AQ_VSI_UP_TABLE_UP5_S 15
388 #define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S)
389 #define ICE_AQ_VSI_UP_TABLE_UP6_S 18
390 #define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S)
391 #define ICE_AQ_VSI_UP_TABLE_UP7_S 21
392 #define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S)
393 __le32 egress_table; /* same defines as for ingress table */
394 /* outer tags section */
397 #define ICE_AQ_VSI_OUTER_TAG_MODE_S 0
398 #define ICE_AQ_VSI_OUTER_TAG_MODE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_MODE_S)
399 #define ICE_AQ_VSI_OUTER_TAG_NOTHING 0x0
400 #define ICE_AQ_VSI_OUTER_TAG_REMOVE 0x1
401 #define ICE_AQ_VSI_OUTER_TAG_COPY 0x2
402 #define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2
403 #define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S)
404 #define ICE_AQ_VSI_OUTER_TAG_NONE 0x0
405 #define ICE_AQ_VSI_OUTER_TAG_STAG 0x1
406 #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2
407 #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3
408 #define ICE_AQ_VSI_OUTER_TAG_INSERT BIT(4)
409 #define ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST BIT(6)
410 u8 outer_tag_reserved;
411 /* queue mapping section */
412 __le16 mapping_flags;
413 #define ICE_AQ_VSI_Q_MAP_CONTIG 0x0
414 #define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0)
415 __le16 q_mapping[16];
416 #define ICE_AQ_VSI_Q_S 0
417 #define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S)
418 __le16 tc_mapping[8];
419 #define ICE_AQ_VSI_TC_Q_OFFSET_S 0
420 #define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S)
421 #define ICE_AQ_VSI_TC_Q_NUM_S 11
422 #define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S)
423 /* queueing option section */
425 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0
426 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S)
427 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0
428 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2
429 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3
430 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2
431 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S)
432 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6
433 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
434 #define ICE_AQ_VSI_Q_OPT_RSS_TPLZ (0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
435 #define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ (0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
436 #define ICE_AQ_VSI_Q_OPT_RSS_XOR (0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
437 #define ICE_AQ_VSI_Q_OPT_RSS_JHASH (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
439 #define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0
440 #define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S)
441 #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7)
443 #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0)
444 u8 q_opt_reserved[3];
445 /* outer up section */
446 __le32 outer_up_table; /* same structure and defines as ingress tbl */
448 __le16 sect_10_reserved;
449 /* flow director section */
451 #define ICE_AQ_VSI_FD_ENABLE BIT(0)
452 #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1)
453 #define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3)
454 __le16 max_fd_fltr_dedicated;
455 __le16 max_fd_fltr_shared;
457 #define ICE_AQ_VSI_FD_DEF_Q_S 0
458 #define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S)
459 #define ICE_AQ_VSI_FD_DEF_GRP_S 12
460 #define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S)
461 __le16 fd_report_opt;
462 #define ICE_AQ_VSI_FD_REPORT_Q_S 0
463 #define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S)
464 #define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12
465 #define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S)
466 #define ICE_AQ_VSI_FD_DEF_DROP BIT(15)
469 #define ICE_AQ_VSI_PASID_ID_S 0
470 #define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S)
471 #define ICE_AQ_VSI_PASID_ID_VALID BIT(31)
475 #define ICE_MAX_NUM_RECIPES 64
477 /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3)
479 struct ice_aqc_sw_rules {
480 /* ops: add switch rules, referring the number of rules.
481 * ops: update switch rules, referring the number of filters
482 * ops: remove switch rules, referring the entry index.
483 * ops: get switch rules, referring to the number of filters.
485 __le16 num_rules_fltr_entry_index;
491 /* Add/Update/Get/Remove lookup Rx/Tx command/response entry
492 * This structures describes the lookup rules and associated actions. "index"
493 * is returned as part of a response to a successful Add command, and can be
494 * used to identify the rule for Update/Get/Remove commands.
496 struct ice_sw_rule_lkup_rx_tx {
498 #define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10
499 /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */
503 /* Bit 0:1 - Action type */
504 #define ICE_SINGLE_ACT_TYPE_S 0x00
505 #define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S)
507 /* Bit 2 - Loop back enable
510 #define ICE_SINGLE_ACT_LB_ENABLE BIT(2)
511 #define ICE_SINGLE_ACT_LAN_ENABLE BIT(3)
513 /* Action type = 0 - Forward to VSI or VSI list */
514 #define ICE_SINGLE_ACT_VSI_FORWARDING 0x0
516 #define ICE_SINGLE_ACT_VSI_ID_S 4
517 #define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S)
518 #define ICE_SINGLE_ACT_VSI_LIST_ID_S 4
519 #define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S)
520 /* This bit needs to be set if action is forward to VSI list */
521 #define ICE_SINGLE_ACT_VSI_LIST BIT(14)
522 #define ICE_SINGLE_ACT_VALID_BIT BIT(17)
523 #define ICE_SINGLE_ACT_DROP BIT(18)
525 /* Action type = 1 - Forward to Queue of Queue group */
526 #define ICE_SINGLE_ACT_TO_Q 0x1
527 #define ICE_SINGLE_ACT_Q_INDEX_S 4
528 #define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S)
529 #define ICE_SINGLE_ACT_Q_REGION_S 15
530 #define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S)
531 #define ICE_SINGLE_ACT_Q_PRIORITY BIT(18)
533 /* Action type = 2 - Prune */
534 #define ICE_SINGLE_ACT_PRUNE 0x2
535 #define ICE_SINGLE_ACT_EGRESS BIT(15)
536 #define ICE_SINGLE_ACT_INGRESS BIT(16)
537 #define ICE_SINGLE_ACT_PRUNET BIT(17)
538 /* Bit 18 should be set to 0 for this action */
540 /* Action type = 2 - Pointer */
541 #define ICE_SINGLE_ACT_PTR 0x2
542 #define ICE_SINGLE_ACT_PTR_VAL_S 4
543 #define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S)
544 /* Bit 18 should be set to 1 */
545 #define ICE_SINGLE_ACT_PTR_BIT BIT(18)
547 /* Action type = 3 - Other actions. Last two bits
548 * are other action identifier
550 #define ICE_SINGLE_ACT_OTHER_ACTS 0x3
551 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17
552 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \
553 (0x3 << ICE_SINGLE_OTHER_ACT_IDENTIFIER_S)
555 /* Bit 17:18 - Defines other actions */
556 /* Other action = 0 - Mirror VSI */
557 #define ICE_SINGLE_OTHER_ACT_MIRROR 0
558 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4
559 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \
560 (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S)
562 /* Other action = 3 - Set Stat count */
563 #define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3
564 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4
565 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \
566 (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S)
568 __le16 index; /* The index of the rule in the lookup table */
569 /* Length and values of the header to be matched per recipe or
576 /* Add/Update/Remove large action command/response entry
577 * "index" is returned as part of a response to a successful Add command, and
578 * can be used to identify the action for Update/Get/Remove commands.
580 struct ice_sw_rule_lg_act {
581 __le16 index; /* Index in large action table */
583 /* Max number of large actions */
584 #define ICE_MAX_LG_ACT 4
585 /* Bit 0:1 - Action type */
586 #define ICE_LG_ACT_TYPE_S 0
587 #define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S)
589 /* Action type = 0 - Forward to VSI or VSI list */
590 #define ICE_LG_ACT_VSI_FORWARDING 0
591 #define ICE_LG_ACT_VSI_ID_S 3
592 #define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S)
593 #define ICE_LG_ACT_VSI_LIST_ID_S 3
594 #define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S)
595 /* This bit needs to be set if action is forward to VSI list */
596 #define ICE_LG_ACT_VSI_LIST BIT(13)
598 #define ICE_LG_ACT_VALID_BIT BIT(16)
600 /* Action type = 1 - Forward to Queue of Queue group */
601 #define ICE_LG_ACT_TO_Q 0x1
602 #define ICE_LG_ACT_Q_INDEX_S 3
603 #define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S)
604 #define ICE_LG_ACT_Q_REGION_S 14
605 #define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S)
606 #define ICE_LG_ACT_Q_PRIORITY_SET BIT(17)
608 /* Action type = 2 - Prune */
609 #define ICE_LG_ACT_PRUNE 0x2
610 #define ICE_LG_ACT_EGRESS BIT(14)
611 #define ICE_LG_ACT_INGRESS BIT(15)
612 #define ICE_LG_ACT_PRUNET BIT(16)
614 /* Action type = 3 - Mirror VSI */
615 #define ICE_LG_OTHER_ACT_MIRROR 0x3
616 #define ICE_LG_ACT_MIRROR_VSI_ID_S 3
617 #define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S)
619 /* Action type = 5 - Generic Value */
620 #define ICE_LG_ACT_GENERIC 0x5
621 #define ICE_LG_ACT_GENERIC_VALUE_S 3
622 #define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S)
623 #define ICE_LG_ACT_GENERIC_OFFSET_S 19
624 #define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S)
625 #define ICE_LG_ACT_GENERIC_PRIORITY_S 22
626 #define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S)
627 #define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX 7
629 /* Action = 7 - Set Stat count */
630 #define ICE_LG_ACT_STAT_COUNT 0x7
631 #define ICE_LG_ACT_STAT_COUNT_S 3
632 #define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S)
633 __le32 act[]; /* array of size for actions */
636 /* Add/Update/Remove VSI list command/response entry
637 * "index" is returned as part of a response to a successful Add command, and
638 * can be used to identify the VSI list for Update/Get/Remove commands.
640 struct ice_sw_rule_vsi_list {
641 __le16 index; /* Index of VSI/Prune list */
643 __le16 vsi[]; /* Array of number_vsi VSI numbers */
646 /* Query VSI list command/response entry */
647 struct ice_sw_rule_vsi_list_query {
649 DECLARE_BITMAP(vsi_list, ICE_MAX_VSI);
652 /* Add switch rule response:
653 * Content of return buffer is same as the input buffer. The status field and
654 * LUT index are updated as part of the response
656 struct ice_aqc_sw_rules_elem {
657 __le16 type; /* Switch rule type, one of T_... */
658 #define ICE_AQC_SW_RULES_T_LKUP_RX 0x0
659 #define ICE_AQC_SW_RULES_T_LKUP_TX 0x1
660 #define ICE_AQC_SW_RULES_T_LG_ACT 0x2
661 #define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3
662 #define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4
663 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5
664 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6
667 struct ice_sw_rule_lkup_rx_tx lkup_tx_rx;
668 struct ice_sw_rule_lg_act lg_act;
669 struct ice_sw_rule_vsi_list vsi_list;
670 struct ice_sw_rule_vsi_list_query vsi_list_query;
674 /* Get Default Topology (indirect 0x0400) */
675 struct ice_aqc_get_topo {
684 /* Update TSE (indirect 0x0403)
685 * Get TSE (indirect 0x0404)
686 * Add TSE (indirect 0x0401)
687 * Delete TSE (indirect 0x040F)
688 * Move TSE (indirect 0x0408)
689 * Suspend Nodes (indirect 0x0409)
690 * Resume Nodes (indirect 0x040A)
692 struct ice_aqc_sched_elem_cmd {
693 __le16 num_elem_req; /* Used by commands */
694 __le16 num_elem_resp; /* Used by responses */
700 struct ice_aqc_txsched_move_grp_info_hdr {
701 __le32 src_parent_teid;
702 __le32 dest_parent_teid;
707 struct ice_aqc_move_elem {
708 struct ice_aqc_txsched_move_grp_info_hdr hdr;
712 struct ice_aqc_elem_info_bw {
713 __le16 bw_profile_idx;
717 struct ice_aqc_txsched_elem {
718 u8 elem_type; /* Special field, reserved for some aq calls */
719 #define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0
720 #define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1
721 #define ICE_AQC_ELEM_TYPE_TC 0x2
722 #define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3
723 #define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4
724 #define ICE_AQC_ELEM_TYPE_LEAF 0x5
725 #define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6
727 #define ICE_AQC_ELEM_VALID_GENERIC BIT(0)
728 #define ICE_AQC_ELEM_VALID_CIR BIT(1)
729 #define ICE_AQC_ELEM_VALID_EIR BIT(2)
730 #define ICE_AQC_ELEM_VALID_SHARED BIT(3)
732 #define ICE_AQC_ELEM_GENERIC_MODE_M 0x1
733 #define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1
734 #define ICE_AQC_ELEM_GENERIC_PRIO_M (0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S)
735 #define ICE_AQC_ELEM_GENERIC_SP_S 0x4
736 #define ICE_AQC_ELEM_GENERIC_SP_M (0x1 << ICE_AQC_ELEM_GENERIC_SP_S)
737 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5
738 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \
739 (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S)
740 u8 flags; /* Special field, reserved for some aq calls */
741 #define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1
742 struct ice_aqc_elem_info_bw cir_bw;
743 struct ice_aqc_elem_info_bw eir_bw;
748 struct ice_aqc_txsched_elem_data {
751 struct ice_aqc_txsched_elem data;
754 struct ice_aqc_txsched_topo_grp_info_hdr {
760 struct ice_aqc_add_elem {
761 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
762 struct ice_aqc_txsched_elem_data generic[];
765 struct ice_aqc_get_topo_elem {
766 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
767 struct ice_aqc_txsched_elem_data
768 generic[ICE_AQC_TOPO_MAX_LEVEL_NUM];
771 struct ice_aqc_delete_elem {
772 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
776 /* Query Port ETS (indirect 0x040E)
778 * This indirect command is used to query port TC node configuration.
780 struct ice_aqc_query_port_ets {
787 struct ice_aqc_port_ets_elem {
790 /* 3 bits for UP per TC 0-7, 4th byte reserved */
793 __le32 port_eir_prof_id;
794 __le32 port_cir_prof_id;
795 /* 3 bits per Node priority to TC 0-7, 4th byte reserved */
797 #define ICE_TC_NODE_PRIO_S 0x4
799 __le32 tc_node_teid[8]; /* Used for response, reserved in command */
802 /* Rate limiting profile for
803 * Add RL profile (indirect 0x0410)
804 * Query RL profile (indirect 0x0411)
805 * Remove RL profile (indirect 0x0415)
806 * These indirect commands acts on single or multiple
807 * RL profiles with specified data.
809 struct ice_aqc_rl_profile {
811 __le16 num_processed; /* Only for response. Reserved in Command. */
817 struct ice_aqc_rl_profile_elem {
820 #define ICE_AQC_RL_PROFILE_TYPE_S 0x0
821 #define ICE_AQC_RL_PROFILE_TYPE_M (0x3 << ICE_AQC_RL_PROFILE_TYPE_S)
822 #define ICE_AQC_RL_PROFILE_TYPE_CIR 0
823 #define ICE_AQC_RL_PROFILE_TYPE_EIR 1
824 #define ICE_AQC_RL_PROFILE_TYPE_SRL 2
825 /* The following flag is used for Query RL Profile Data */
826 #define ICE_AQC_RL_PROFILE_INVAL_S 0x7
827 #define ICE_AQC_RL_PROFILE_INVAL_M (0x1 << ICE_AQC_RL_PROFILE_INVAL_S)
830 __le16 max_burst_size;
836 /* Query Scheduler Resource Allocation (indirect 0x0412)
837 * This indirect command retrieves the scheduler resources allocated by
838 * EMP Firmware to the given PF.
840 struct ice_aqc_query_txsched_res {
846 struct ice_aqc_generic_sched_props {
848 __le16 logical_levels;
849 u8 flattening_bitmap;
857 struct ice_aqc_layer_props {
860 __le16 max_device_nodes;
863 __le16 max_sibl_grp_sz;
864 __le16 max_cir_rl_profiles;
865 __le16 max_eir_rl_profiles;
866 __le16 max_srl_profiles;
870 struct ice_aqc_query_txsched_res_resp {
871 struct ice_aqc_generic_sched_props sched_props;
872 struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM];
875 /* Get PHY capabilities (indirect 0x0600) */
876 struct ice_aqc_get_phy_caps {
880 /* 18.0 - Report qualified modules */
881 #define ICE_AQC_GET_PHY_RQM BIT(0)
882 /* 18.1 - 18.3 : Report mode
883 * 000b - Report NVM capabilities
884 * 001b - Report topology capabilities
885 * 010b - Report SW configured
886 * 100b - Report default capabilities
888 #define ICE_AQC_REPORT_MODE_S 1
889 #define ICE_AQC_REPORT_MODE_M (7 << ICE_AQC_REPORT_MODE_S)
890 #define ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA 0
891 #define ICE_AQC_REPORT_TOPO_CAP_MEDIA BIT(1)
892 #define ICE_AQC_REPORT_ACTIVE_CFG BIT(2)
893 #define ICE_AQC_REPORT_DFLT_CFG BIT(3)
899 /* This is #define of PHY type (Extended):
900 * The first set of defines is for phy_type_low.
902 #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0)
903 #define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1)
904 #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2)
905 #define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3)
906 #define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4)
907 #define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5)
908 #define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6)
909 #define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7)
910 #define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8)
911 #define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9)
912 #define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10)
913 #define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11)
914 #define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12)
915 #define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13)
916 #define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14)
917 #define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15)
918 #define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16)
919 #define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17)
920 #define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18)
921 #define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19)
922 #define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20)
923 #define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21)
924 #define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22)
925 #define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23)
926 #define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24)
927 #define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25)
928 #define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26)
929 #define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27)
930 #define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28)
931 #define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29)
932 #define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30)
933 #define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31)
934 #define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32)
935 #define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33)
936 #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34)
937 #define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35)
938 #define ICE_PHY_TYPE_LOW_50GBASE_CR2 BIT_ULL(36)
939 #define ICE_PHY_TYPE_LOW_50GBASE_SR2 BIT_ULL(37)
940 #define ICE_PHY_TYPE_LOW_50GBASE_LR2 BIT_ULL(38)
941 #define ICE_PHY_TYPE_LOW_50GBASE_KR2 BIT_ULL(39)
942 #define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC BIT_ULL(40)
943 #define ICE_PHY_TYPE_LOW_50G_LAUI2 BIT_ULL(41)
944 #define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC BIT_ULL(42)
945 #define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43)
946 #define ICE_PHY_TYPE_LOW_50GBASE_CP BIT_ULL(44)
947 #define ICE_PHY_TYPE_LOW_50GBASE_SR BIT_ULL(45)
948 #define ICE_PHY_TYPE_LOW_50GBASE_FR BIT_ULL(46)
949 #define ICE_PHY_TYPE_LOW_50GBASE_LR BIT_ULL(47)
950 #define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 BIT_ULL(48)
951 #define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC BIT_ULL(49)
952 #define ICE_PHY_TYPE_LOW_50G_AUI1 BIT_ULL(50)
953 #define ICE_PHY_TYPE_LOW_100GBASE_CR4 BIT_ULL(51)
954 #define ICE_PHY_TYPE_LOW_100GBASE_SR4 BIT_ULL(52)
955 #define ICE_PHY_TYPE_LOW_100GBASE_LR4 BIT_ULL(53)
956 #define ICE_PHY_TYPE_LOW_100GBASE_KR4 BIT_ULL(54)
957 #define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC BIT_ULL(55)
958 #define ICE_PHY_TYPE_LOW_100G_CAUI4 BIT_ULL(56)
959 #define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC BIT_ULL(57)
960 #define ICE_PHY_TYPE_LOW_100G_AUI4 BIT_ULL(58)
961 #define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 BIT_ULL(59)
962 #define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 BIT_ULL(60)
963 #define ICE_PHY_TYPE_LOW_100GBASE_CP2 BIT_ULL(61)
964 #define ICE_PHY_TYPE_LOW_100GBASE_SR2 BIT_ULL(62)
965 #define ICE_PHY_TYPE_LOW_100GBASE_DR BIT_ULL(63)
966 #define ICE_PHY_TYPE_LOW_MAX_INDEX 63
967 /* The second set of defines is for phy_type_high. */
968 #define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 BIT_ULL(0)
969 #define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC BIT_ULL(1)
970 #define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2)
971 #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3)
972 #define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4)
973 #define ICE_PHY_TYPE_HIGH_MAX_INDEX 5
975 struct ice_aqc_get_phy_caps_data {
976 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
977 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
979 #define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0)
980 #define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1)
981 #define ICE_AQC_PHY_LOW_POWER_MODE BIT(2)
982 #define ICE_AQC_PHY_EN_LINK BIT(3)
983 #define ICE_AQC_PHY_AN_MODE BIT(4)
984 #define ICE_AQC_GET_PHY_EN_MOD_QUAL BIT(5)
985 #define ICE_AQC_PHY_EN_AUTO_FEC BIT(7)
986 #define ICE_AQC_PHY_CAPS_MASK ICE_M(0xff, 0)
987 u8 low_power_ctrl_an;
988 #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0)
989 #define ICE_AQC_PHY_AN_EN_CLAUSE28 BIT(1)
990 #define ICE_AQC_PHY_AN_EN_CLAUSE73 BIT(2)
991 #define ICE_AQC_PHY_AN_EN_CLAUSE37 BIT(3)
993 #define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0)
994 #define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1)
995 #define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2)
996 #define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3)
997 #define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4)
998 #define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5)
999 #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6)
1001 u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */
1003 u8 link_fec_options;
1004 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0)
1005 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1)
1006 #define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2)
1007 #define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3)
1008 #define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4)
1009 #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6)
1010 #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7)
1011 #define ICE_AQC_PHY_FEC_MASK ICE_M(0xdf, 0)
1012 u8 module_compliance_enforcement;
1013 #define ICE_AQC_MOD_ENFORCE_STRICT_MODE BIT(0)
1014 u8 extended_compliance_code;
1015 #define ICE_MODULE_TYPE_TOTAL_BYTE 3
1016 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
1017 #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0
1018 #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80
1019 #define ICE_AQC_MOD_TYPE_IDENT 1
1020 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0)
1021 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1)
1022 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4)
1023 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5)
1024 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6)
1025 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7)
1026 #define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0
1027 #define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86
1028 u8 qualified_module_count;
1029 u8 rsvd2[7]; /* Bytes 47:41 reserved */
1030 #define ICE_AQC_QUAL_MOD_COUNT_MAX 16
1037 } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX];
1040 /* Set PHY capabilities (direct 0x0601)
1041 * NOTE: This command must be followed by setup link and restart auto-neg
1043 struct ice_aqc_set_phy_cfg {
1050 /* Set PHY config command data structure */
1051 struct ice_aqc_set_phy_cfg_data {
1052 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1053 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1055 #define ICE_AQ_PHY_ENA_VALID_MASK ICE_M(0xef, 0)
1056 #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0)
1057 #define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1)
1058 #define ICE_AQ_PHY_ENA_LOW_POWER BIT(2)
1059 #define ICE_AQ_PHY_ENA_LINK BIT(3)
1060 #define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5)
1061 #define ICE_AQ_PHY_ENA_LESM BIT(6)
1062 #define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7)
1063 u8 low_power_ctrl_an;
1064 __le16 eee_cap; /* Value from ice_aqc_get_phy_caps */
1066 u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */
1067 u8 module_compliance_enforcement;
1070 /* Set MAC Config command data structure (direct 0x0603) */
1071 struct ice_aqc_set_mac_cfg {
1072 __le16 max_frame_size;
1074 #define ICE_AQ_SET_MAC_PACE_S 3
1075 #define ICE_AQ_SET_MAC_PACE_M (0xF << ICE_AQ_SET_MAC_PACE_S)
1076 #define ICE_AQ_SET_MAC_PACE_TYPE_M BIT(7)
1077 #define ICE_AQ_SET_MAC_PACE_TYPE_RATE 0
1078 #define ICE_AQ_SET_MAC_PACE_TYPE_FIXED ICE_AQ_SET_MAC_PACE_TYPE_M
1080 __le16 tx_tmr_value;
1081 __le16 fc_refresh_threshold;
1083 #define ICE_AQ_SET_MAC_AUTO_DROP_MASK BIT(0)
1084 #define ICE_AQ_SET_MAC_AUTO_DROP_NONE 0
1085 #define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS BIT(0)
1089 /* Restart AN command data structure (direct 0x0605)
1090 * Also used for response, with only the lport_num field present.
1092 struct ice_aqc_restart_an {
1096 #define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1)
1097 #define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2)
1101 /* Get link status (indirect 0x0607), also used for Link Status Event */
1102 struct ice_aqc_get_link_status {
1106 #define ICE_AQ_LSE_M 0x3
1107 #define ICE_AQ_LSE_NOP 0x0
1108 #define ICE_AQ_LSE_DIS 0x2
1109 #define ICE_AQ_LSE_ENA 0x3
1110 /* only response uses this flag */
1111 #define ICE_AQ_LSE_IS_ENABLED 0x1
1117 /* Get link status response data structure, also used for Link Status Event */
1118 struct ice_aqc_get_link_status_data {
1119 u8 topo_media_conflict;
1120 #define ICE_AQ_LINK_TOPO_CONFLICT BIT(0)
1121 #define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1)
1122 #define ICE_AQ_LINK_TOPO_CORRUPT BIT(2)
1123 #define ICE_AQ_LINK_TOPO_UNREACH_PRT BIT(4)
1124 #define ICE_AQ_LINK_TOPO_UNDRUTIL_PRT BIT(5)
1125 #define ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA BIT(6)
1126 #define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA BIT(7)
1128 #define ICE_AQ_LINK_MODULE_POWER_UNSUPPORTED BIT(5)
1129 #define ICE_AQ_LINK_INVAL_MAX_POWER_LIMIT BIT(7)
1131 #define ICE_AQ_LINK_UP BIT(0) /* Link Status */
1132 #define ICE_AQ_LINK_FAULT BIT(1)
1133 #define ICE_AQ_LINK_FAULT_TX BIT(2)
1134 #define ICE_AQ_LINK_FAULT_RX BIT(3)
1135 #define ICE_AQ_LINK_FAULT_REMOTE BIT(4)
1136 #define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */
1137 #define ICE_AQ_MEDIA_AVAILABLE BIT(6)
1138 #define ICE_AQ_SIGNAL_DETECT BIT(7)
1140 #define ICE_AQ_AN_COMPLETED BIT(0)
1141 #define ICE_AQ_LP_AN_ABILITY BIT(1)
1142 #define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */
1143 #define ICE_AQ_FEC_EN BIT(3)
1144 #define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */
1145 #define ICE_AQ_LINK_PAUSE_TX BIT(5)
1146 #define ICE_AQ_LINK_PAUSE_RX BIT(6)
1147 #define ICE_AQ_QUALIFIED_MODULE BIT(7)
1149 #define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0)
1150 #define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */
1151 /* Port Tx Suspended */
1152 #define ICE_AQ_LINK_TX_S 2
1153 #define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S)
1154 #define ICE_AQ_LINK_TX_ACTIVE 0
1155 #define ICE_AQ_LINK_TX_DRAINED 1
1156 #define ICE_AQ_LINK_TX_FLUSHED 3
1158 __le16 max_frame_size;
1160 #define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0)
1161 #define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1)
1162 #define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2)
1163 #define ICE_AQ_FEC_MASK ICE_M(0x7, 0)
1165 #define ICE_AQ_CFG_PACING_S 3
1166 #define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S)
1167 #define ICE_AQ_CFG_PACING_TYPE_M BIT(7)
1168 #define ICE_AQ_CFG_PACING_TYPE_AVG 0
1169 #define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M
1170 /* External Device Power Ability */
1172 #define ICE_AQ_PWR_CLASS_M 0x3F
1173 #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0
1174 #define ICE_AQ_LINK_PWR_BASET_HIGH 1
1175 #define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0
1176 #define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1
1177 #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2
1178 #define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3
1180 #define ICE_AQ_LINK_SPEED_M 0x7FF
1181 #define ICE_AQ_LINK_SPEED_10MB BIT(0)
1182 #define ICE_AQ_LINK_SPEED_100MB BIT(1)
1183 #define ICE_AQ_LINK_SPEED_1000MB BIT(2)
1184 #define ICE_AQ_LINK_SPEED_2500MB BIT(3)
1185 #define ICE_AQ_LINK_SPEED_5GB BIT(4)
1186 #define ICE_AQ_LINK_SPEED_10GB BIT(5)
1187 #define ICE_AQ_LINK_SPEED_20GB BIT(6)
1188 #define ICE_AQ_LINK_SPEED_25GB BIT(7)
1189 #define ICE_AQ_LINK_SPEED_40GB BIT(8)
1190 #define ICE_AQ_LINK_SPEED_50GB BIT(9)
1191 #define ICE_AQ_LINK_SPEED_100GB BIT(10)
1192 #define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15)
1193 __le32 reserved3; /* Aligns next field to 8-byte boundary */
1194 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1195 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1198 /* Set event mask command (direct 0x0613) */
1199 struct ice_aqc_set_event_mask {
1203 #define ICE_AQ_LINK_EVENT_UPDOWN BIT(1)
1204 #define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2)
1205 #define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3)
1206 #define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4)
1207 #define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5)
1208 #define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6)
1209 #define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7)
1210 #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8)
1211 #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9)
1215 /* Set MAC Loopback command (direct 0x0620) */
1216 struct ice_aqc_set_mac_lb {
1218 #define ICE_AQ_MAC_LB_EN BIT(0)
1219 #define ICE_AQ_MAC_LB_OSC_CLK BIT(1)
1223 struct ice_aqc_link_topo_addr {
1226 #define ICE_AQC_LINK_TOPO_PORT_NUM_VALID BIT(0)
1228 #define ICE_AQC_LINK_TOPO_NODE_TYPE_S 0
1229 #define ICE_AQC_LINK_TOPO_NODE_TYPE_M (0xF << ICE_AQC_LINK_TOPO_NODE_TYPE_S)
1230 #define ICE_AQC_LINK_TOPO_NODE_TYPE_PHY 0
1231 #define ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL 1
1232 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MUX_CTRL 2
1233 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED_CTRL 3
1234 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED 4
1235 #define ICE_AQC_LINK_TOPO_NODE_TYPE_THERMAL 5
1236 #define ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE 6
1237 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MEZZ 7
1238 #define ICE_AQC_LINK_TOPO_NODE_TYPE_ID_EEPROM 8
1239 #define ICE_AQC_LINK_TOPO_NODE_CTX_S 4
1240 #define ICE_AQC_LINK_TOPO_NODE_CTX_M \
1241 (0xF << ICE_AQC_LINK_TOPO_NODE_CTX_S)
1242 #define ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL 0
1243 #define ICE_AQC_LINK_TOPO_NODE_CTX_BOARD 1
1244 #define ICE_AQC_LINK_TOPO_NODE_CTX_PORT 2
1245 #define ICE_AQC_LINK_TOPO_NODE_CTX_NODE 3
1246 #define ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED 4
1247 #define ICE_AQC_LINK_TOPO_NODE_CTX_OVERRIDE 5
1250 #define ICE_AQC_LINK_TOPO_HANDLE_S 0
1251 #define ICE_AQC_LINK_TOPO_HANDLE_M (0x3FF << ICE_AQC_LINK_TOPO_HANDLE_S)
1252 /* Used to decode the handle field */
1253 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_M BIT(9)
1254 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_LOM BIT(9)
1255 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ 0
1256 #define ICE_AQC_LINK_TOPO_HANDLE_NODE_S 0
1257 /* In case of a Mezzanine type */
1258 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_NODE_M \
1259 (0x3F << ICE_AQC_LINK_TOPO_HANDLE_NODE_S)
1260 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S 6
1261 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_M (0x7 << ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S)
1262 /* In case of a LOM type */
1263 #define ICE_AQC_LINK_TOPO_HANDLE_LOM_NODE_M \
1264 (0x1FF << ICE_AQC_LINK_TOPO_HANDLE_NODE_S)
1267 /* Get Link Topology Handle (direct, 0x06E0) */
1268 struct ice_aqc_get_link_topo {
1269 struct ice_aqc_link_topo_addr addr;
1274 /* Set Port Identification LED (direct, 0x06E9) */
1275 struct ice_aqc_set_port_id_led {
1279 #define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0)
1280 #define ICE_AQC_PORT_IDENT_LED_ORIG 0
1284 /* Read/Write SFF EEPROM command (indirect 0x06EE) */
1285 struct ice_aqc_sff_eeprom {
1288 #define ICE_AQC_SFF_PORT_NUM_VALID BIT(0)
1289 __le16 i2c_bus_addr;
1290 #define ICE_AQC_SFF_I2CBUS_7BIT_M 0x7F
1291 #define ICE_AQC_SFF_I2CBUS_10BIT_M 0x3FF
1292 #define ICE_AQC_SFF_I2CBUS_TYPE_M BIT(10)
1293 #define ICE_AQC_SFF_I2CBUS_TYPE_7BIT 0
1294 #define ICE_AQC_SFF_I2CBUS_TYPE_10BIT ICE_AQC_SFF_I2CBUS_TYPE_M
1295 #define ICE_AQC_SFF_SET_EEPROM_PAGE_S 11
1296 #define ICE_AQC_SFF_SET_EEPROM_PAGE_M (0x3 << ICE_AQC_SFF_SET_EEPROM_PAGE_S)
1297 #define ICE_AQC_SFF_NO_PAGE_CHANGE 0
1298 #define ICE_AQC_SFF_SET_23_ON_MISMATCH 1
1299 #define ICE_AQC_SFF_SET_22_ON_MISMATCH 2
1300 #define ICE_AQC_SFF_IS_WRITE BIT(15)
1301 __le16 i2c_mem_addr;
1303 #define ICE_AQC_SFF_EEPROM_BANK_S 0
1304 #define ICE_AQC_SFF_EEPROM_BANK_M (0xFF << ICE_AQC_SFF_EEPROM_BANK_S)
1305 #define ICE_AQC_SFF_EEPROM_PAGE_S 8
1306 #define ICE_AQC_SFF_EEPROM_PAGE_M (0xFF << ICE_AQC_SFF_EEPROM_PAGE_S)
1311 /* NVM Read command (indirect 0x0701)
1312 * NVM Erase commands (direct 0x0702)
1313 * NVM Update commands (indirect 0x0703)
1315 struct ice_aqc_nvm {
1316 #define ICE_AQC_NVM_MAX_OFFSET 0xFFFFFF
1320 #define ICE_AQC_NVM_LAST_CMD BIT(0)
1321 #define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Update reply */
1322 #define ICE_AQC_NVM_PRESERVATION_S 1
1323 #define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S)
1324 #define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S)
1325 #define ICE_AQC_NVM_PRESERVE_ALL BIT(1)
1326 #define ICE_AQC_NVM_FACTORY_DEFAULT (2 << ICE_AQC_NVM_PRESERVATION_S)
1327 #define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S)
1328 #define ICE_AQC_NVM_ACTIV_SEL_NVM BIT(3) /* Write Activate/SR Dump only */
1329 #define ICE_AQC_NVM_ACTIV_SEL_OROM BIT(4)
1330 #define ICE_AQC_NVM_ACTIV_SEL_NETLIST BIT(5)
1331 #define ICE_AQC_NVM_SPECIAL_UPDATE BIT(6)
1332 #define ICE_AQC_NVM_REVERT_LAST_ACTIV BIT(6) /* Write Activate only */
1333 #define ICE_AQC_NVM_ACTIV_SEL_MASK ICE_M(0x7, 3)
1334 #define ICE_AQC_NVM_FLASH_ONLY BIT(7)
1335 __le16 module_typeid;
1337 #define ICE_AQC_NVM_ERASE_LEN 0xFFFF
1342 #define ICE_AQC_NVM_START_POINT 0
1344 /* NVM Checksum Command (direct, 0x0706) */
1345 struct ice_aqc_nvm_checksum {
1347 #define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0)
1348 #define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1)
1350 __le16 checksum; /* Used only by response */
1351 #define ICE_AQC_NVM_CHECKSUM_CORRECT 0xBABA
1355 /* Used for NVM Set Package Data command - 0x070A */
1356 struct ice_aqc_nvm_pkg_data {
1359 #define ICE_AQC_NVM_PKG_DELETE BIT(0) /* used for command call */
1360 #define ICE_AQC_NVM_PKG_SKIPPED BIT(0) /* used for command response */
1367 /* Used for Pass Component Table command - 0x070B */
1368 struct ice_aqc_nvm_pass_comp_tbl {
1369 u8 component_response; /* Response only */
1370 #define ICE_AQ_NVM_PASS_COMP_CAN_BE_UPDATED 0x0
1371 #define ICE_AQ_NVM_PASS_COMP_CAN_MAY_BE_UPDATEABLE 0x1
1372 #define ICE_AQ_NVM_PASS_COMP_CAN_NOT_BE_UPDATED 0x2
1373 u8 component_response_code; /* Response only */
1374 #define ICE_AQ_NVM_PASS_COMP_CAN_BE_UPDATED_CODE 0x0
1375 #define ICE_AQ_NVM_PASS_COMP_STAMP_IDENTICAL_CODE 0x1
1376 #define ICE_AQ_NVM_PASS_COMP_STAMP_LOWER 0x2
1377 #define ICE_AQ_NVM_PASS_COMP_INVALID_STAMP_CODE 0x3
1378 #define ICE_AQ_NVM_PASS_COMP_CONFLICT_CODE 0x4
1379 #define ICE_AQ_NVM_PASS_COMP_PRE_REQ_NOT_MET_CODE 0x5
1380 #define ICE_AQ_NVM_PASS_COMP_NOT_SUPPORTED_CODE 0x6
1381 #define ICE_AQ_NVM_PASS_COMP_CANNOT_DOWNGRADE_CODE 0x7
1382 #define ICE_AQ_NVM_PASS_COMP_INCOMPLETE_IMAGE_CODE 0x8
1383 #define ICE_AQ_NVM_PASS_COMP_VER_STR_IDENTICAL_CODE 0xA
1384 #define ICE_AQ_NVM_PASS_COMP_VER_STR_LOWER_CODE 0xB
1387 #define ICE_AQ_NVM_PASS_COMP_TBL_START 0x1
1388 #define ICE_AQ_NVM_PASS_COMP_TBL_MIDDLE 0x2
1389 #define ICE_AQ_NVM_PASS_COMP_TBL_END 0x4
1390 #define ICE_AQ_NVM_PASS_COMP_TBL_START_AND_END 0x5
1396 struct ice_aqc_nvm_comp_tbl {
1398 #define NVM_COMP_CLASS_ALL_FW 0x000A
1401 #define NVM_COMP_ID_OROM 0x5
1402 #define NVM_COMP_ID_NVM 0x6
1403 #define NVM_COMP_ID_NETLIST 0x8
1406 #define FWU_COMP_CLASS_IDX_NOT_USE 0x0
1408 __le32 comp_cmp_stamp;
1410 #define NVM_CVS_TYPE_ASCII 0x1
1413 u8 cvs[]; /* Component Version String */
1416 /* Send to PF command (indirect 0x0801) ID is only used by PF
1418 * Send to VF command (indirect 0x0802) ID is only used by PF
1421 struct ice_aqc_pf_vf_msg {
1428 /* Get LLDP MIB (indirect 0x0A00)
1429 * Note: This is also used by the LLDP MIB Change Event (0x0A01)
1430 * as the format is the same.
1432 struct ice_aqc_lldp_get_mib {
1434 #define ICE_AQ_LLDP_MIB_TYPE_S 0
1435 #define ICE_AQ_LLDP_MIB_TYPE_M (0x3 << ICE_AQ_LLDP_MIB_TYPE_S)
1436 #define ICE_AQ_LLDP_MIB_LOCAL 0
1437 #define ICE_AQ_LLDP_MIB_REMOTE 1
1438 #define ICE_AQ_LLDP_MIB_LOCAL_AND_REMOTE 2
1439 #define ICE_AQ_LLDP_BRID_TYPE_S 2
1440 #define ICE_AQ_LLDP_BRID_TYPE_M (0x3 << ICE_AQ_LLDP_BRID_TYPE_S)
1441 #define ICE_AQ_LLDP_BRID_TYPE_NEAREST_BRID 0
1442 #define ICE_AQ_LLDP_BRID_TYPE_NON_TPMR 1
1443 /* Tx pause flags in the 0xA01 event use ICE_AQ_LLDP_TX_* */
1444 #define ICE_AQ_LLDP_TX_S 0x4
1445 #define ICE_AQ_LLDP_TX_M (0x03 << ICE_AQ_LLDP_TX_S)
1446 #define ICE_AQ_LLDP_TX_ACTIVE 0
1447 #define ICE_AQ_LLDP_TX_SUSPENDED 1
1448 #define ICE_AQ_LLDP_TX_FLUSHED 3
1449 /* The following bytes are reserved for the Get LLDP MIB command (0x0A00)
1450 * and in the LLDP MIB Change Event (0x0A01). They are valid for the
1451 * Get LLDP MIB (0x0A00) response only.
1461 /* Configure LLDP MIB Change Event (direct 0x0A01) */
1462 /* For MIB Change Event use ice_aqc_lldp_get_mib structure above */
1463 struct ice_aqc_lldp_set_mib_change {
1465 #define ICE_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
1466 #define ICE_AQ_LLDP_MIB_UPDATE_DIS 0x1
1470 /* Stop LLDP (direct 0x0A05) */
1471 struct ice_aqc_lldp_stop {
1473 #define ICE_AQ_LLDP_AGENT_STATE_MASK BIT(0)
1474 #define ICE_AQ_LLDP_AGENT_STOP 0x0
1475 #define ICE_AQ_LLDP_AGENT_SHUTDOWN ICE_AQ_LLDP_AGENT_STATE_MASK
1476 #define ICE_AQ_LLDP_AGENT_PERSIST_DIS BIT(1)
1480 /* Start LLDP (direct 0x0A06) */
1481 struct ice_aqc_lldp_start {
1483 #define ICE_AQ_LLDP_AGENT_START BIT(0)
1484 #define ICE_AQ_LLDP_AGENT_PERSIST_ENA BIT(1)
1488 /* Get CEE DCBX Oper Config (0x0A07)
1489 * The command uses the generic descriptor struct and
1490 * returns the struct below as an indirect response.
1492 struct ice_aqc_get_cee_dcb_cfg_resp {
1497 __le16 oper_app_prio;
1498 #define ICE_AQC_CEE_APP_FCOE_S 0
1499 #define ICE_AQC_CEE_APP_FCOE_M (0x7 << ICE_AQC_CEE_APP_FCOE_S)
1500 #define ICE_AQC_CEE_APP_ISCSI_S 3
1501 #define ICE_AQC_CEE_APP_ISCSI_M (0x7 << ICE_AQC_CEE_APP_ISCSI_S)
1502 #define ICE_AQC_CEE_APP_FIP_S 8
1503 #define ICE_AQC_CEE_APP_FIP_M (0x7 << ICE_AQC_CEE_APP_FIP_S)
1505 #define ICE_AQC_CEE_PG_STATUS_S 0
1506 #define ICE_AQC_CEE_PG_STATUS_M (0x7 << ICE_AQC_CEE_PG_STATUS_S)
1507 #define ICE_AQC_CEE_PFC_STATUS_S 3
1508 #define ICE_AQC_CEE_PFC_STATUS_M (0x7 << ICE_AQC_CEE_PFC_STATUS_S)
1509 #define ICE_AQC_CEE_FCOE_STATUS_S 8
1510 #define ICE_AQC_CEE_FCOE_STATUS_M (0x7 << ICE_AQC_CEE_FCOE_STATUS_S)
1511 #define ICE_AQC_CEE_ISCSI_STATUS_S 11
1512 #define ICE_AQC_CEE_ISCSI_STATUS_M (0x7 << ICE_AQC_CEE_ISCSI_STATUS_S)
1513 #define ICE_AQC_CEE_FIP_STATUS_S 16
1514 #define ICE_AQC_CEE_FIP_STATUS_M (0x7 << ICE_AQC_CEE_FIP_STATUS_S)
1518 /* Set Local LLDP MIB (indirect 0x0A08)
1519 * Used to replace the local MIB of a given LLDP agent. e.g. DCBX
1521 struct ice_aqc_lldp_set_local_mib {
1523 #define SET_LOCAL_MIB_TYPE_DCBX_M BIT(0)
1524 #define SET_LOCAL_MIB_TYPE_LOCAL_MIB 0
1525 #define SET_LOCAL_MIB_TYPE_CEE_M BIT(1)
1526 #define SET_LOCAL_MIB_TYPE_CEE_WILLING 0
1527 #define SET_LOCAL_MIB_TYPE_CEE_NON_WILLING SET_LOCAL_MIB_TYPE_CEE_M
1535 /* Stop/Start LLDP Agent (direct 0x0A09)
1536 * Used for stopping/starting specific LLDP agent. e.g. DCBX.
1537 * The same structure is used for the response, with the command field
1538 * being used as the status field.
1540 struct ice_aqc_lldp_stop_start_specific_agent {
1542 #define ICE_AQC_START_STOP_AGENT_M BIT(0)
1543 #define ICE_AQC_START_STOP_AGENT_STOP_DCBX 0
1544 #define ICE_AQC_START_STOP_AGENT_START_DCBX ICE_AQC_START_STOP_AGENT_M
1548 /* LLDP Filter Control (direct 0x0A0A) */
1549 struct ice_aqc_lldp_filter_ctrl {
1551 #define ICE_AQC_LLDP_FILTER_ACTION_ADD 0x0
1552 #define ICE_AQC_LLDP_FILTER_ACTION_DELETE 0x1
1558 /* Get/Set RSS key (indirect 0x0B04/0x0B02) */
1559 struct ice_aqc_get_set_rss_key {
1560 #define ICE_AQC_GSET_RSS_KEY_VSI_VALID BIT(15)
1561 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_S 0
1562 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_KEY_VSI_ID_S)
1569 #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28
1570 #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC
1571 #define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE \
1572 (ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE + \
1573 ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE)
1575 struct ice_aqc_get_set_rss_keys {
1576 u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE];
1577 u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE];
1580 /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */
1581 struct ice_aqc_get_set_rss_lut {
1582 #define ICE_AQC_GSET_RSS_LUT_VSI_VALID BIT(15)
1583 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_S 0
1584 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_LUT_VSI_ID_S)
1586 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S 0
1587 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M \
1588 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S)
1590 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI 0
1591 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF 1
1592 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL 2
1594 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S 2
1595 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M \
1596 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S)
1598 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 128
1599 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG 0
1600 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 512
1601 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG 1
1602 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K 2048
1603 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG 2
1605 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S 4
1606 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M \
1607 (0xF << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S)
1615 /* Sideband Control Interface Commands */
1616 /* Neighbor Device Request (indirect 0x0C00); also used for the response. */
1617 struct ice_aqc_neigh_dev_req {
1624 /* Add Tx LAN Queues (indirect 0x0C30) */
1625 struct ice_aqc_add_txqs {
1633 /* This is the descriptor of each queue entry for the Add Tx LAN Queues
1634 * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp.
1636 struct ice_aqc_add_txqs_perq {
1642 struct ice_aqc_txsched_elem info;
1645 /* The format of the command buffer for Add Tx LAN Queues (0x0C30)
1646 * is an array of the following structs. Please note that the length of
1647 * each struct ice_aqc_add_tx_qgrp is variable due
1648 * to the variable number of queues in each group!
1650 struct ice_aqc_add_tx_qgrp {
1654 struct ice_aqc_add_txqs_perq txqs[];
1657 /* Disable Tx LAN Queues (indirect 0x0C31) */
1658 struct ice_aqc_dis_txqs {
1660 #define ICE_AQC_Q_DIS_CMD_S 0
1661 #define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S)
1662 #define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S)
1663 #define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S)
1664 #define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S)
1665 #define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S)
1666 #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2)
1667 #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3)
1669 __le16 vmvf_and_timeout;
1670 #define ICE_AQC_Q_DIS_VMVF_NUM_S 0
1671 #define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S)
1672 #define ICE_AQC_Q_DIS_TIMEOUT_S 10
1673 #define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S)
1674 __le32 blocked_cgds;
1679 /* The buffer for Disable Tx LAN Queues (indirect 0x0C31)
1680 * contains the following structures, arrayed one after the
1682 * Note: Since the q_id is 16 bits wide, if the
1683 * number of queues is even, then 2 bytes of alignment MUST be
1684 * added before the start of the next group, to allow correct
1685 * alignment of the parent_teid field.
1687 struct ice_aqc_dis_txq_item {
1691 /* The length of the q_id array varies according to num_qs */
1692 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15
1693 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \
1694 (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)
1695 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \
1696 (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)
1700 /* Add Tx RDMA Queue Set (indirect 0x0C33) */
1701 struct ice_aqc_add_rdma_qset {
1708 /* This is the descriptor of each Qset entry for the Add Tx RDMA Queue Set
1709 * command (0x0C33). Only used within struct ice_aqc_add_rdma_qset.
1711 struct ice_aqc_add_tx_rdma_qset_entry {
1715 struct ice_aqc_txsched_elem info;
1718 /* The format of the command buffer for Add Tx RDMA Queue Set(0x0C33)
1719 * is an array of the following structs. Please note that the length of
1720 * each struct ice_aqc_add_rdma_qset is variable due to the variable
1721 * number of queues in each group!
1723 struct ice_aqc_add_rdma_qset_data {
1727 struct ice_aqc_add_tx_rdma_qset_entry rdma_qsets[];
1730 /* Configure Firmware Logging Command (indirect 0xFF09)
1731 * Logging Information Read Response (indirect 0xFF10)
1732 * Note: The 0xFF10 command has no input parameters.
1734 struct ice_aqc_fw_logging {
1736 #define ICE_AQC_FW_LOG_AQ_EN BIT(0)
1737 #define ICE_AQC_FW_LOG_UART_EN BIT(1)
1739 u8 log_ctrl_valid; /* Not used by 0xFF10 Response */
1740 #define ICE_AQC_FW_LOG_AQ_VALID BIT(0)
1741 #define ICE_AQC_FW_LOG_UART_VALID BIT(1)
1747 enum ice_aqc_fw_logging_mod {
1748 ICE_AQC_FW_LOG_ID_GENERAL = 0,
1749 ICE_AQC_FW_LOG_ID_CTRL,
1750 ICE_AQC_FW_LOG_ID_LINK,
1751 ICE_AQC_FW_LOG_ID_LINK_TOPO,
1752 ICE_AQC_FW_LOG_ID_DNL,
1753 ICE_AQC_FW_LOG_ID_I2C,
1754 ICE_AQC_FW_LOG_ID_SDP,
1755 ICE_AQC_FW_LOG_ID_MDIO,
1756 ICE_AQC_FW_LOG_ID_ADMINQ,
1757 ICE_AQC_FW_LOG_ID_HDMA,
1758 ICE_AQC_FW_LOG_ID_LLDP,
1759 ICE_AQC_FW_LOG_ID_DCBX,
1760 ICE_AQC_FW_LOG_ID_DCB,
1761 ICE_AQC_FW_LOG_ID_NETPROXY,
1762 ICE_AQC_FW_LOG_ID_NVM,
1763 ICE_AQC_FW_LOG_ID_AUTH,
1764 ICE_AQC_FW_LOG_ID_VPD,
1765 ICE_AQC_FW_LOG_ID_IOSF,
1766 ICE_AQC_FW_LOG_ID_PARSER,
1767 ICE_AQC_FW_LOG_ID_SW,
1768 ICE_AQC_FW_LOG_ID_SCHEDULER,
1769 ICE_AQC_FW_LOG_ID_TXQ,
1770 ICE_AQC_FW_LOG_ID_RSVD,
1771 ICE_AQC_FW_LOG_ID_POST,
1772 ICE_AQC_FW_LOG_ID_WATCHDOG,
1773 ICE_AQC_FW_LOG_ID_TASK_DISPATCH,
1774 ICE_AQC_FW_LOG_ID_MNG,
1775 ICE_AQC_FW_LOG_ID_MAX,
1778 /* Defines for both above FW logging command/response buffers */
1779 #define ICE_AQC_FW_LOG_ID_S 0
1780 #define ICE_AQC_FW_LOG_ID_M (0xFFF << ICE_AQC_FW_LOG_ID_S)
1782 #define ICE_AQC_FW_LOG_CONF_SUCCESS 0 /* Used by response */
1783 #define ICE_AQC_FW_LOG_CONF_BAD_INDX BIT(12) /* Used by response */
1785 #define ICE_AQC_FW_LOG_EN_S 12
1786 #define ICE_AQC_FW_LOG_EN_M (0xF << ICE_AQC_FW_LOG_EN_S)
1787 #define ICE_AQC_FW_LOG_INFO_EN BIT(12) /* Used by command */
1788 #define ICE_AQC_FW_LOG_INIT_EN BIT(13) /* Used by command */
1789 #define ICE_AQC_FW_LOG_FLOW_EN BIT(14) /* Used by command */
1790 #define ICE_AQC_FW_LOG_ERR_EN BIT(15) /* Used by command */
1792 /* Get/Clear FW Log (indirect 0xFF11) */
1793 struct ice_aqc_get_clear_fw_log {
1795 #define ICE_AQC_FW_LOG_CLEAR BIT(0)
1796 #define ICE_AQC_FW_LOG_MORE_DATA_AVAIL BIT(1)
1802 /* Download Package (indirect 0x0C40) */
1803 /* Also used for Update Package (indirect 0x0C42) */
1804 struct ice_aqc_download_pkg {
1806 #define ICE_AQC_DOWNLOAD_PKG_LAST_BUF 0x01
1813 struct ice_aqc_download_pkg_resp {
1814 __le32 error_offset;
1820 /* Get Package Info List (indirect 0x0C43) */
1821 struct ice_aqc_get_pkg_info_list {
1828 /* Version format for packages */
1829 struct ice_pkg_ver {
1836 #define ICE_PKG_NAME_SIZE 32
1837 #define ICE_SEG_ID_SIZE 28
1838 #define ICE_SEG_NAME_SIZE 28
1840 struct ice_aqc_get_pkg_info {
1841 struct ice_pkg_ver ver;
1842 char name[ICE_SEG_NAME_SIZE];
1846 u8 is_active_at_boot;
1850 /* Get Package Info List response buffer format (0x0C43) */
1851 struct ice_aqc_get_pkg_info_resp {
1853 struct ice_aqc_get_pkg_info pkg_info[];
1856 /* Lan Queue Overflow Event (direct, 0x1001) */
1857 struct ice_aqc_event_lan_overflow {
1858 __le32 prtdcb_ruptq;
1864 * struct ice_aq_desc - Admin Queue (AQ) descriptor
1865 * @flags: ICE_AQ_FLAG_* flags
1866 * @opcode: AQ command opcode
1867 * @datalen: length in bytes of indirect/external data buffer
1868 * @retval: return value from firmware
1869 * @cookie_high: opaque data high-half
1870 * @cookie_low: opaque data low-half
1871 * @params: command-specific parameters
1873 * Descriptor format for commands the driver posts on the Admin Transmit Queue
1874 * (ATQ). The firmware writes back onto the command descriptor and returns
1875 * the result of the command. Asynchronous events that are not an immediate
1876 * result of the command are written to the Admin Receive Queue (ARQ) using
1877 * the same descriptor format. Descriptors are in little-endian notation with
1880 struct ice_aq_desc {
1889 struct ice_aqc_generic generic;
1890 struct ice_aqc_get_ver get_ver;
1891 struct ice_aqc_driver_ver driver_ver;
1892 struct ice_aqc_q_shutdown q_shutdown;
1893 struct ice_aqc_req_res res_owner;
1894 struct ice_aqc_manage_mac_read mac_read;
1895 struct ice_aqc_manage_mac_write mac_write;
1896 struct ice_aqc_clear_pxe clear_pxe;
1897 struct ice_aqc_list_caps get_cap;
1898 struct ice_aqc_get_phy_caps get_phy;
1899 struct ice_aqc_set_phy_cfg set_phy;
1900 struct ice_aqc_restart_an restart_an;
1901 struct ice_aqc_sff_eeprom read_write_sff_param;
1902 struct ice_aqc_set_port_id_led set_port_id_led;
1903 struct ice_aqc_get_sw_cfg get_sw_conf;
1904 struct ice_aqc_sw_rules sw_rules;
1905 struct ice_aqc_get_topo get_topo;
1906 struct ice_aqc_sched_elem_cmd sched_elem_cmd;
1907 struct ice_aqc_query_txsched_res query_sched_res;
1908 struct ice_aqc_query_port_ets port_ets;
1909 struct ice_aqc_rl_profile rl_profile;
1910 struct ice_aqc_nvm nvm;
1911 struct ice_aqc_nvm_checksum nvm_checksum;
1912 struct ice_aqc_nvm_pkg_data pkg_data;
1913 struct ice_aqc_nvm_pass_comp_tbl pass_comp_tbl;
1914 struct ice_aqc_pf_vf_msg virt;
1915 struct ice_aqc_lldp_get_mib lldp_get_mib;
1916 struct ice_aqc_lldp_set_mib_change lldp_set_event;
1917 struct ice_aqc_lldp_stop lldp_stop;
1918 struct ice_aqc_lldp_start lldp_start;
1919 struct ice_aqc_lldp_set_local_mib lldp_set_mib;
1920 struct ice_aqc_lldp_stop_start_specific_agent lldp_agent_ctrl;
1921 struct ice_aqc_lldp_filter_ctrl lldp_filter_ctrl;
1922 struct ice_aqc_get_set_rss_lut get_set_rss_lut;
1923 struct ice_aqc_get_set_rss_key get_set_rss_key;
1924 struct ice_aqc_neigh_dev_req neigh_dev;
1925 struct ice_aqc_add_txqs add_txqs;
1926 struct ice_aqc_dis_txqs dis_txqs;
1927 struct ice_aqc_add_rdma_qset add_rdma_qset;
1928 struct ice_aqc_add_get_update_free_vsi vsi_cmd;
1929 struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res;
1930 struct ice_aqc_fw_logging fw_logging;
1931 struct ice_aqc_get_clear_fw_log get_clear_fw_log;
1932 struct ice_aqc_download_pkg download_pkg;
1933 struct ice_aqc_set_mac_lb set_mac_lb;
1934 struct ice_aqc_alloc_free_res_cmd sw_res_ctrl;
1935 struct ice_aqc_set_mac_cfg set_mac_cfg;
1936 struct ice_aqc_set_event_mask set_event_mask;
1937 struct ice_aqc_get_link_status get_link_status;
1938 struct ice_aqc_event_lan_overflow lan_overflow;
1939 struct ice_aqc_get_link_topo get_link_topo;
1943 /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */
1944 #define ICE_AQ_LG_BUF 512
1946 #define ICE_AQ_FLAG_ERR_S 2
1947 #define ICE_AQ_FLAG_LB_S 9
1948 #define ICE_AQ_FLAG_RD_S 10
1949 #define ICE_AQ_FLAG_BUF_S 12
1950 #define ICE_AQ_FLAG_SI_S 13
1952 #define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */
1953 #define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */
1954 #define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */
1955 #define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */
1956 #define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */
1960 ICE_AQ_RC_OK = 0, /* Success */
1961 ICE_AQ_RC_EPERM = 1, /* Operation not permitted */
1962 ICE_AQ_RC_ENOENT = 2, /* No such element */
1963 ICE_AQ_RC_ENOMEM = 9, /* Out of memory */
1964 ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */
1965 ICE_AQ_RC_EEXIST = 13, /* Object already exists */
1966 ICE_AQ_RC_EINVAL = 14, /* Invalid argument */
1967 ICE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */
1968 ICE_AQ_RC_ENOSYS = 17, /* Function not implemented */
1969 ICE_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
1970 ICE_AQ_RC_ENOSEC = 24, /* Missing security manifest */
1971 ICE_AQ_RC_EBADSIG = 25, /* Bad RSA signature */
1972 ICE_AQ_RC_ESVN = 26, /* SVN number prohibits this package */
1973 ICE_AQ_RC_EBADMAN = 27, /* Manifest hash mismatch */
1974 ICE_AQ_RC_EBADBUF = 28, /* Buffer hash mismatches manifest */
1977 /* Admin Queue command opcodes */
1978 enum ice_adminq_opc {
1980 ice_aqc_opc_get_ver = 0x0001,
1981 ice_aqc_opc_driver_ver = 0x0002,
1982 ice_aqc_opc_q_shutdown = 0x0003,
1984 /* resource ownership */
1985 ice_aqc_opc_req_res = 0x0008,
1986 ice_aqc_opc_release_res = 0x0009,
1988 /* device/function capabilities */
1989 ice_aqc_opc_list_func_caps = 0x000A,
1990 ice_aqc_opc_list_dev_caps = 0x000B,
1992 /* manage MAC address */
1993 ice_aqc_opc_manage_mac_read = 0x0107,
1994 ice_aqc_opc_manage_mac_write = 0x0108,
1997 ice_aqc_opc_clear_pxe_mode = 0x0110,
1999 /* internal switch commands */
2000 ice_aqc_opc_get_sw_cfg = 0x0200,
2002 /* Alloc/Free/Get Resources */
2003 ice_aqc_opc_alloc_res = 0x0208,
2004 ice_aqc_opc_free_res = 0x0209,
2007 ice_aqc_opc_add_vsi = 0x0210,
2008 ice_aqc_opc_update_vsi = 0x0211,
2009 ice_aqc_opc_free_vsi = 0x0213,
2011 /* switch rules population commands */
2012 ice_aqc_opc_add_sw_rules = 0x02A0,
2013 ice_aqc_opc_update_sw_rules = 0x02A1,
2014 ice_aqc_opc_remove_sw_rules = 0x02A2,
2016 ice_aqc_opc_clear_pf_cfg = 0x02A4,
2018 /* transmit scheduler commands */
2019 ice_aqc_opc_get_dflt_topo = 0x0400,
2020 ice_aqc_opc_add_sched_elems = 0x0401,
2021 ice_aqc_opc_cfg_sched_elems = 0x0403,
2022 ice_aqc_opc_get_sched_elems = 0x0404,
2023 ice_aqc_opc_move_sched_elems = 0x0408,
2024 ice_aqc_opc_suspend_sched_elems = 0x0409,
2025 ice_aqc_opc_resume_sched_elems = 0x040A,
2026 ice_aqc_opc_query_port_ets = 0x040E,
2027 ice_aqc_opc_delete_sched_elems = 0x040F,
2028 ice_aqc_opc_add_rl_profiles = 0x0410,
2029 ice_aqc_opc_query_sched_res = 0x0412,
2030 ice_aqc_opc_remove_rl_profiles = 0x0415,
2033 ice_aqc_opc_get_phy_caps = 0x0600,
2034 ice_aqc_opc_set_phy_cfg = 0x0601,
2035 ice_aqc_opc_set_mac_cfg = 0x0603,
2036 ice_aqc_opc_restart_an = 0x0605,
2037 ice_aqc_opc_get_link_status = 0x0607,
2038 ice_aqc_opc_set_event_mask = 0x0613,
2039 ice_aqc_opc_set_mac_lb = 0x0620,
2040 ice_aqc_opc_get_link_topo = 0x06E0,
2041 ice_aqc_opc_set_port_id_led = 0x06E9,
2042 ice_aqc_opc_sff_eeprom = 0x06EE,
2045 ice_aqc_opc_nvm_read = 0x0701,
2046 ice_aqc_opc_nvm_erase = 0x0702,
2047 ice_aqc_opc_nvm_write = 0x0703,
2048 ice_aqc_opc_nvm_checksum = 0x0706,
2049 ice_aqc_opc_nvm_write_activate = 0x0707,
2050 ice_aqc_opc_nvm_update_empr = 0x0709,
2051 ice_aqc_opc_nvm_pkg_data = 0x070A,
2052 ice_aqc_opc_nvm_pass_component_tbl = 0x070B,
2054 /* PF/VF mailbox commands */
2055 ice_mbx_opc_send_msg_to_pf = 0x0801,
2056 ice_mbx_opc_send_msg_to_vf = 0x0802,
2058 ice_aqc_opc_lldp_get_mib = 0x0A00,
2059 ice_aqc_opc_lldp_set_mib_change = 0x0A01,
2060 ice_aqc_opc_lldp_stop = 0x0A05,
2061 ice_aqc_opc_lldp_start = 0x0A06,
2062 ice_aqc_opc_get_cee_dcb_cfg = 0x0A07,
2063 ice_aqc_opc_lldp_set_local_mib = 0x0A08,
2064 ice_aqc_opc_lldp_stop_start_specific_agent = 0x0A09,
2065 ice_aqc_opc_lldp_filter_ctrl = 0x0A0A,
2068 ice_aqc_opc_set_rss_key = 0x0B02,
2069 ice_aqc_opc_set_rss_lut = 0x0B03,
2070 ice_aqc_opc_get_rss_key = 0x0B04,
2071 ice_aqc_opc_get_rss_lut = 0x0B05,
2073 /* Sideband Control Interface commands */
2074 ice_aqc_opc_neighbour_device_request = 0x0C00,
2076 /* Tx queue handling commands/events */
2077 ice_aqc_opc_add_txqs = 0x0C30,
2078 ice_aqc_opc_dis_txqs = 0x0C31,
2079 ice_aqc_opc_add_rdma_qset = 0x0C33,
2081 /* package commands */
2082 ice_aqc_opc_download_pkg = 0x0C40,
2083 ice_aqc_opc_update_pkg = 0x0C42,
2084 ice_aqc_opc_get_pkg_info_list = 0x0C43,
2086 /* Standalone Commands/Events */
2087 ice_aqc_opc_event_lan_overflow = 0x1001,
2089 /* debug commands */
2090 ice_aqc_opc_fw_logging = 0xFF09,
2091 ice_aqc_opc_fw_logging_info = 0xFF10,
2094 #endif /* _ICE_ADMINQ_CMD_H_ */