1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018, Intel Corporation. */
4 #ifndef _ICE_ADMINQ_CMD_H_
5 #define _ICE_ADMINQ_CMD_H_
7 /* This header file defines the Admin Queue commands, error codes and
8 * descriptor format. It is shared between Firmware and Software.
11 #define ICE_MAX_VSI 768
12 #define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9
13 #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728
15 struct ice_aqc_generic {
22 /* Get version (direct 0x0001) */
23 struct ice_aqc_get_ver {
36 /* Queue Shutdown (direct 0x0003) */
37 struct ice_aqc_q_shutdown {
38 #define ICE_AQC_DRIVER_UNLOADING BIT(0)
39 __le32 driver_unloading;
43 /* Request resource ownership (direct 0x0008)
44 * Release resource ownership (direct 0x0009)
46 struct ice_aqc_req_res {
48 #define ICE_AQC_RES_ID_NVM 1
49 #define ICE_AQC_RES_ID_SDP 2
50 #define ICE_AQC_RES_ID_CHNG_LOCK 3
51 #define ICE_AQC_RES_ID_GLBL_LOCK 4
53 #define ICE_AQC_RES_ACCESS_READ 1
54 #define ICE_AQC_RES_ACCESS_WRITE 2
56 /* Upon successful completion, FW writes this value and driver is
57 * expected to release resource before timeout. This value is provided
61 #define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000
62 #define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000
63 #define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000
64 #define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000
65 /* For SDP: pin id of the SDP */
67 /* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */
69 #define ICE_AQ_RES_GLBL_SUCCESS 0
70 #define ICE_AQ_RES_GLBL_IN_PROG 1
71 #define ICE_AQ_RES_GLBL_DONE 2
75 /* Get function capabilities (indirect 0x000A)
76 * Get device capabilities (indirect 0x000B)
78 struct ice_aqc_list_caps {
87 /* Device/Function buffer entry, repeated per reported capability */
88 struct ice_aqc_list_caps_elem {
90 #define ICE_AQC_CAPS_VSI 0x0017
91 #define ICE_AQC_CAPS_RSS 0x0040
92 #define ICE_AQC_CAPS_RXQS 0x0041
93 #define ICE_AQC_CAPS_TXQS 0x0042
94 #define ICE_AQC_CAPS_MSIX 0x0043
95 #define ICE_AQC_CAPS_MAX_MTU 0x0047
99 /* Number of resources described by this capability */
101 /* Only meaningful for some types of resources */
103 /* Only meaningful for some types of resources */
109 /* Manage MAC address, read command - indirect (0x0107)
110 * This struct is also used for the response
112 struct ice_aqc_manage_mac_read {
113 __le16 flags; /* Zeroed by device driver */
114 #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4)
115 #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5)
116 #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6)
117 #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7)
118 #define ICE_AQC_MAN_MAC_READ_S 4
119 #define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S)
122 #define ICE_AQC_MAN_MAC_PORT_NUM_IS_VALID BIT(0)
123 u8 num_addr; /* Used in response */
129 /* Response buffer format for manage MAC read command */
130 struct ice_aqc_manage_mac_read_resp {
133 #define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0
134 #define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1
135 u8 mac_addr[ETH_ALEN];
138 /* Manage MAC address, write command - direct (0x0108) */
139 struct ice_aqc_manage_mac_write {
142 #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0)
143 #define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1)
144 #define ICE_AQC_MAN_MAC_WR_S 6
145 #define ICE_AQC_MAN_MAC_WR_M (3 << ICE_AQC_MAN_MAC_WR_S)
146 #define ICE_AQC_MAN_MAC_UPDATE_LAA 0
147 #define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL (BIT(0) << ICE_AQC_MAN_MAC_WR_S)
148 /* High 16 bits of MAC address in big endian order */
150 /* Low 32 bits of MAC address in big endian order */
156 /* Clear PXE Command and response (direct 0x0110) */
157 struct ice_aqc_clear_pxe {
159 #define ICE_AQC_CLEAR_PXE_RX_CNT 0x2
163 /* Get switch configuration (0x0200) */
164 struct ice_aqc_get_sw_cfg {
165 /* Reserved for command and copy of request flags for response */
167 /* First desc in case of command and next_elem in case of response
168 * In case of response, if it is not zero, means all the configuration
169 * was not returned and new command shall be sent with this value in
170 * the 'first desc' field
173 /* Reserved for command, only used for response */
180 /* Each entry in the response buffer is of the following type: */
181 struct ice_aqc_get_sw_cfg_resp_elem {
182 /* VSI/Port Number */
184 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0
185 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \
186 (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S)
187 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14
188 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S)
189 #define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0
190 #define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1
191 #define ICE_AQC_GET_SW_CONF_RESP_VSI 2
193 /* SWID VSI/Port belongs to */
196 /* Bit 14..0 : PF/VF number VSI belongs to
197 * Bit 15 : VF indication bit
200 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0
201 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \
202 (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S)
203 #define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15)
206 /* The response buffer is as follows. Note that the length of the
207 * elements array varies with the length of the command response.
209 struct ice_aqc_get_sw_cfg_resp {
210 struct ice_aqc_get_sw_cfg_resp_elem elements[1];
213 /* These resource type defines are used for all switch resource
214 * commands where a resource type is required, such as:
215 * Get Resource Allocation command (indirect 0x0204)
216 * Allocate Resources command (indirect 0x0208)
217 * Free Resources command (indirect 0x0209)
218 * Get Allocated Resource Descriptors Command (indirect 0x020A)
220 #define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03
221 #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04
223 /* Allocate Resources command (indirect 0x0208)
224 * Free Resources command (indirect 0x0209)
226 struct ice_aqc_alloc_free_res_cmd {
227 __le16 num_entries; /* Number of Resource entries */
233 /* Resource descriptor */
234 struct ice_aqc_res_elem {
241 /* Buffer for Allocate/Free Resources commands */
242 struct ice_aqc_alloc_free_res_elem {
243 __le16 res_type; /* Types defined above cmd 0x0204 */
244 #define ICE_AQC_RES_TYPE_SHARED_S 7
245 #define ICE_AQC_RES_TYPE_SHARED_M (0x1 << ICE_AQC_RES_TYPE_SHARED_S)
246 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8
247 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \
248 (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S)
250 struct ice_aqc_res_elem elem[1];
253 /* Add VSI (indirect 0x0210)
254 * Update VSI (indirect 0x0211)
255 * Get VSI (indirect 0x0212)
256 * Free VSI (indirect 0x0213)
258 struct ice_aqc_add_get_update_free_vsi {
260 #define ICE_AQ_VSI_NUM_S 0
261 #define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S)
262 #define ICE_AQ_VSI_IS_VALID BIT(15)
264 #define ICE_AQ_VSI_KEEP_ALLOC 0x1
268 #define ICE_AQ_VSI_TYPE_S 0
269 #define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S)
270 #define ICE_AQ_VSI_TYPE_VF 0x0
271 #define ICE_AQ_VSI_TYPE_VMDQ2 0x1
272 #define ICE_AQ_VSI_TYPE_PF 0x2
273 #define ICE_AQ_VSI_TYPE_EMP_MNG 0x3
278 /* Response descriptor for:
279 * Add VSI (indirect 0x0210)
280 * Update VSI (indirect 0x0211)
281 * Free VSI (indirect 0x0213)
283 struct ice_aqc_add_update_free_vsi_resp {
292 struct ice_aqc_vsi_props {
293 __le16 valid_sections;
294 #define ICE_AQ_VSI_PROP_SW_VALID BIT(0)
295 #define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1)
296 #define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2)
297 #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3)
298 #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4)
299 #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5)
300 #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6)
301 #define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7)
302 #define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8)
303 #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11)
304 #define ICE_AQ_VSI_PROP_PASID_VALID BIT(12)
308 #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5)
309 #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6)
310 #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7)
312 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0
313 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M \
314 (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S)
315 #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0)
316 #define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4)
318 #define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0
319 #define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S)
320 #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5)
321 /* security section */
323 #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0)
324 #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2)
325 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4
326 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S)
327 #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0)
330 __le16 pvid; /* VLANS include priority bits */
331 u8 pvlan_reserved[2];
333 #define ICE_AQ_VSI_VLAN_MODE_S 0
334 #define ICE_AQ_VSI_VLAN_MODE_M (0x3 << ICE_AQ_VSI_VLAN_MODE_S)
335 #define ICE_AQ_VSI_VLAN_MODE_UNTAGGED 0x1
336 #define ICE_AQ_VSI_VLAN_MODE_TAGGED 0x2
337 #define ICE_AQ_VSI_VLAN_MODE_ALL 0x3
338 #define ICE_AQ_VSI_PVLAN_INSERT_PVID BIT(2)
339 #define ICE_AQ_VSI_VLAN_EMOD_S 3
340 #define ICE_AQ_VSI_VLAN_EMOD_M (0x3 << ICE_AQ_VSI_VLAN_EMOD_S)
341 #define ICE_AQ_VSI_VLAN_EMOD_STR_BOTH (0x0 << ICE_AQ_VSI_VLAN_EMOD_S)
342 #define ICE_AQ_VSI_VLAN_EMOD_STR_UP (0x1 << ICE_AQ_VSI_VLAN_EMOD_S)
343 #define ICE_AQ_VSI_VLAN_EMOD_STR (0x2 << ICE_AQ_VSI_VLAN_EMOD_S)
344 #define ICE_AQ_VSI_VLAN_EMOD_NOTHING (0x3 << ICE_AQ_VSI_VLAN_EMOD_S)
345 u8 pvlan_reserved2[3];
346 /* ingress egress up sections */
347 __le32 ingress_table; /* bitmap, 3 bits per up */
348 #define ICE_AQ_VSI_UP_TABLE_UP0_S 0
349 #define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S)
350 #define ICE_AQ_VSI_UP_TABLE_UP1_S 3
351 #define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S)
352 #define ICE_AQ_VSI_UP_TABLE_UP2_S 6
353 #define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S)
354 #define ICE_AQ_VSI_UP_TABLE_UP3_S 9
355 #define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S)
356 #define ICE_AQ_VSI_UP_TABLE_UP4_S 12
357 #define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S)
358 #define ICE_AQ_VSI_UP_TABLE_UP5_S 15
359 #define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S)
360 #define ICE_AQ_VSI_UP_TABLE_UP6_S 18
361 #define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S)
362 #define ICE_AQ_VSI_UP_TABLE_UP7_S 21
363 #define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S)
364 __le32 egress_table; /* same defines as for ingress table */
365 /* outer tags section */
368 #define ICE_AQ_VSI_OUTER_TAG_MODE_S 0
369 #define ICE_AQ_VSI_OUTER_TAG_MODE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_MODE_S)
370 #define ICE_AQ_VSI_OUTER_TAG_NOTHING 0x0
371 #define ICE_AQ_VSI_OUTER_TAG_REMOVE 0x1
372 #define ICE_AQ_VSI_OUTER_TAG_COPY 0x2
373 #define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2
374 #define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S)
375 #define ICE_AQ_VSI_OUTER_TAG_NONE 0x0
376 #define ICE_AQ_VSI_OUTER_TAG_STAG 0x1
377 #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2
378 #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3
379 #define ICE_AQ_VSI_OUTER_TAG_INSERT BIT(4)
380 #define ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST BIT(6)
381 u8 outer_tag_reserved;
382 /* queue mapping section */
383 __le16 mapping_flags;
384 #define ICE_AQ_VSI_Q_MAP_CONTIG 0x0
385 #define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0)
386 __le16 q_mapping[16];
387 #define ICE_AQ_VSI_Q_S 0
388 #define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S)
389 __le16 tc_mapping[8];
390 #define ICE_AQ_VSI_TC_Q_OFFSET_S 0
391 #define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S)
392 #define ICE_AQ_VSI_TC_Q_NUM_S 11
393 #define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S)
394 /* queueing option section */
396 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0
397 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S)
398 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0
399 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2
400 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3
401 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2
402 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S)
403 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6
404 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
405 #define ICE_AQ_VSI_Q_OPT_RSS_TPLZ (0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
406 #define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ (0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
407 #define ICE_AQ_VSI_Q_OPT_RSS_XOR (0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
408 #define ICE_AQ_VSI_Q_OPT_RSS_JHASH (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
410 #define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0
411 #define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S)
412 #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7)
414 #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0)
415 u8 q_opt_reserved[3];
416 /* outer up section */
417 __le32 outer_up_table; /* same structure and defines as ingress tbl */
419 __le16 sect_10_reserved;
420 /* flow director section */
422 #define ICE_AQ_VSI_FD_ENABLE BIT(0)
423 #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1)
424 #define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3)
425 __le16 max_fd_fltr_dedicated;
426 __le16 max_fd_fltr_shared;
428 #define ICE_AQ_VSI_FD_DEF_Q_S 0
429 #define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S)
430 #define ICE_AQ_VSI_FD_DEF_GRP_S 12
431 #define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S)
432 __le16 fd_report_opt;
433 #define ICE_AQ_VSI_FD_REPORT_Q_S 0
434 #define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S)
435 #define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12
436 #define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S)
437 #define ICE_AQ_VSI_FD_DEF_DROP BIT(15)
440 #define ICE_AQ_VSI_PASID_ID_S 0
441 #define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S)
442 #define ICE_AQ_VSI_PASID_ID_VALID BIT(31)
446 /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3)
448 struct ice_aqc_sw_rules {
449 /* ops: add switch rules, referring the number of rules.
450 * ops: update switch rules, referring the number of filters
451 * ops: remove switch rules, referring the entry index.
452 * ops: get switch rules, referring to the number of filters.
454 __le16 num_rules_fltr_entry_index;
460 /* Add/Update/Get/Remove lookup Rx/Tx command/response entry
461 * This structures describes the lookup rules and associated actions. "index"
462 * is returned as part of a response to a successful Add command, and can be
463 * used to identify the rule for Update/Get/Remove commands.
465 struct ice_sw_rule_lkup_rx_tx {
467 #define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10
468 /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */
472 /* Bit 0:1 - Action type */
473 #define ICE_SINGLE_ACT_TYPE_S 0x00
474 #define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S)
476 /* Bit 2 - Loop back enable
479 #define ICE_SINGLE_ACT_LB_ENABLE BIT(2)
480 #define ICE_SINGLE_ACT_LAN_ENABLE BIT(3)
482 /* Action type = 0 - Forward to VSI or VSI list */
483 #define ICE_SINGLE_ACT_VSI_FORWARDING 0x0
485 #define ICE_SINGLE_ACT_VSI_ID_S 4
486 #define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S)
487 #define ICE_SINGLE_ACT_VSI_LIST_ID_S 4
488 #define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S)
489 /* This bit needs to be set if action is forward to VSI list */
490 #define ICE_SINGLE_ACT_VSI_LIST BIT(14)
491 #define ICE_SINGLE_ACT_VALID_BIT BIT(17)
492 #define ICE_SINGLE_ACT_DROP BIT(18)
494 /* Action type = 1 - Forward to Queue of Queue group */
495 #define ICE_SINGLE_ACT_TO_Q 0x1
496 #define ICE_SINGLE_ACT_Q_INDEX_S 4
497 #define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S)
498 #define ICE_SINGLE_ACT_Q_REGION_S 15
499 #define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S)
500 #define ICE_SINGLE_ACT_Q_PRIORITY BIT(18)
502 /* Action type = 2 - Prune */
503 #define ICE_SINGLE_ACT_PRUNE 0x2
504 #define ICE_SINGLE_ACT_EGRESS BIT(15)
505 #define ICE_SINGLE_ACT_INGRESS BIT(16)
506 #define ICE_SINGLE_ACT_PRUNET BIT(17)
507 /* Bit 18 should be set to 0 for this action */
509 /* Action type = 2 - Pointer */
510 #define ICE_SINGLE_ACT_PTR 0x2
511 #define ICE_SINGLE_ACT_PTR_VAL_S 4
512 #define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S)
513 /* Bit 18 should be set to 1 */
514 #define ICE_SINGLE_ACT_PTR_BIT BIT(18)
516 /* Action type = 3 - Other actions. Last two bits
517 * are other action identifier
519 #define ICE_SINGLE_ACT_OTHER_ACTS 0x3
520 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17
521 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \
522 (0x3 << \ ICE_SINGLE_OTHER_ACT_IDENTIFIER_S)
524 /* Bit 17:18 - Defines other actions */
525 /* Other action = 0 - Mirror VSI */
526 #define ICE_SINGLE_OTHER_ACT_MIRROR 0
527 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4
528 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \
529 (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S)
531 /* Other action = 3 - Set Stat count */
532 #define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3
533 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4
534 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \
535 (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S)
537 __le16 index; /* The index of the rule in the lookup table */
538 /* Length and values of the header to be matched per recipe or
545 /* Add/Update/Remove large action command/response entry
546 * "index" is returned as part of a response to a successful Add command, and
547 * can be used to identify the action for Update/Get/Remove commands.
549 struct ice_sw_rule_lg_act {
550 __le16 index; /* Index in large action table */
552 __le32 act[1]; /* array of size for actions */
553 /* Max number of large actions */
554 #define ICE_MAX_LG_ACT 4
555 /* Bit 0:1 - Action type */
556 #define ICE_LG_ACT_TYPE_S 0
557 #define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S)
559 /* Action type = 0 - Forward to VSI or VSI list */
560 #define ICE_LG_ACT_VSI_FORWARDING 0
561 #define ICE_LG_ACT_VSI_ID_S 3
562 #define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S)
563 #define ICE_LG_ACT_VSI_LIST_ID_S 3
564 #define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S)
565 /* This bit needs to be set if action is forward to VSI list */
566 #define ICE_LG_ACT_VSI_LIST BIT(13)
568 #define ICE_LG_ACT_VALID_BIT BIT(16)
570 /* Action type = 1 - Forward to Queue of Queue group */
571 #define ICE_LG_ACT_TO_Q 0x1
572 #define ICE_LG_ACT_Q_INDEX_S 3
573 #define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S)
574 #define ICE_LG_ACT_Q_REGION_S 14
575 #define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S)
576 #define ICE_LG_ACT_Q_PRIORITY_SET BIT(17)
578 /* Action type = 2 - Prune */
579 #define ICE_LG_ACT_PRUNE 0x2
580 #define ICE_LG_ACT_EGRESS BIT(14)
581 #define ICE_LG_ACT_INGRESS BIT(15)
582 #define ICE_LG_ACT_PRUNET BIT(16)
584 /* Action type = 3 - Mirror VSI */
585 #define ICE_LG_OTHER_ACT_MIRROR 0x3
586 #define ICE_LG_ACT_MIRROR_VSI_ID_S 3
587 #define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S)
589 /* Action type = 5 - Generic Value */
590 #define ICE_LG_ACT_GENERIC 0x5
591 #define ICE_LG_ACT_GENERIC_VALUE_S 3
592 #define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S)
593 #define ICE_LG_ACT_GENERIC_OFFSET_S 19
594 #define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S)
595 #define ICE_LG_ACT_GENERIC_PRIORITY_S 22
596 #define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S)
597 #define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX 7
599 /* Action = 7 - Set Stat count */
600 #define ICE_LG_ACT_STAT_COUNT 0x7
601 #define ICE_LG_ACT_STAT_COUNT_S 3
602 #define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S)
605 /* Add/Update/Remove VSI list command/response entry
606 * "index" is returned as part of a response to a successful Add command, and
607 * can be used to identify the VSI list for Update/Get/Remove commands.
609 struct ice_sw_rule_vsi_list {
610 __le16 index; /* Index of VSI/Prune list */
612 __le16 vsi[1]; /* Array of number_vsi VSI numbers */
615 /* Query VSI list command/response entry */
616 struct ice_sw_rule_vsi_list_query {
618 DECLARE_BITMAP(vsi_list, ICE_MAX_VSI);
621 /* Add switch rule response:
622 * Content of return buffer is same as the input buffer. The status field and
623 * LUT index are updated as part of the response
625 struct ice_aqc_sw_rules_elem {
626 __le16 type; /* Switch rule type, one of T_... */
627 #define ICE_AQC_SW_RULES_T_LKUP_RX 0x0
628 #define ICE_AQC_SW_RULES_T_LKUP_TX 0x1
629 #define ICE_AQC_SW_RULES_T_LG_ACT 0x2
630 #define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3
631 #define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4
632 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5
633 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6
636 struct ice_sw_rule_lkup_rx_tx lkup_tx_rx;
637 struct ice_sw_rule_lg_act lg_act;
638 struct ice_sw_rule_vsi_list vsi_list;
639 struct ice_sw_rule_vsi_list_query vsi_list_query;
643 /* Get Default Topology (indirect 0x0400) */
644 struct ice_aqc_get_topo {
653 /* Update TSE (indirect 0x0403)
654 * Get TSE (indirect 0x0404)
656 struct ice_aqc_get_cfg_elem {
657 __le16 num_elem_req; /* Used by commands */
658 __le16 num_elem_resp; /* Used by responses */
664 /* This is the buffer for:
665 * Suspend Nodes (indirect 0x0409)
666 * Resume Nodes (indirect 0x040A)
668 struct ice_aqc_suspend_resume_elem {
672 /* Add TSE (indirect 0x0401)
673 * Delete TSE (indirect 0x040F)
674 * Move TSE (indirect 0x0408)
676 struct ice_aqc_add_move_delete_elem {
678 __le16 num_grps_updated;
684 struct ice_aqc_elem_info_bw {
685 __le16 bw_profile_idx;
689 struct ice_aqc_txsched_elem {
690 u8 elem_type; /* Special field, reserved for some aq calls */
691 #define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0
692 #define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1
693 #define ICE_AQC_ELEM_TYPE_TC 0x2
694 #define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3
695 #define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4
696 #define ICE_AQC_ELEM_TYPE_LEAF 0x5
697 #define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6
699 #define ICE_AQC_ELEM_VALID_GENERIC BIT(0)
700 #define ICE_AQC_ELEM_VALID_CIR BIT(1)
701 #define ICE_AQC_ELEM_VALID_EIR BIT(2)
702 #define ICE_AQC_ELEM_VALID_SHARED BIT(3)
704 #define ICE_AQC_ELEM_GENERIC_MODE_M 0x1
705 #define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1
706 #define ICE_AQC_ELEM_GENERIC_PRIO_M (0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S)
707 #define ICE_AQC_ELEM_GENERIC_SP_S 0x4
708 #define ICE_AQC_ELEM_GENERIC_SP_M (0x1 << ICE_AQC_ELEM_GENERIC_SP_S)
709 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5
710 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \
711 (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S)
712 u8 flags; /* Special field, reserved for some aq calls */
713 #define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1
714 struct ice_aqc_elem_info_bw cir_bw;
715 struct ice_aqc_elem_info_bw eir_bw;
720 struct ice_aqc_txsched_elem_data {
723 struct ice_aqc_txsched_elem data;
726 struct ice_aqc_txsched_topo_grp_info_hdr {
732 struct ice_aqc_add_elem {
733 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
734 struct ice_aqc_txsched_elem_data generic[1];
737 struct ice_aqc_get_topo_elem {
738 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
739 struct ice_aqc_txsched_elem_data
740 generic[ICE_AQC_TOPO_MAX_LEVEL_NUM];
743 struct ice_aqc_delete_elem {
744 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
748 /* Query Scheduler Resource Allocation (indirect 0x0412)
749 * This indirect command retrieves the scheduler resources allocated by
750 * EMP Firmware to the given PF.
752 struct ice_aqc_query_txsched_res {
758 struct ice_aqc_generic_sched_props {
760 __le16 logical_levels;
761 u8 flattening_bitmap;
769 struct ice_aqc_layer_props {
772 __le16 max_device_nodes;
775 __le16 max_shared_rate_lmtr;
777 __le16 max_cir_rl_profiles;
778 __le16 max_eir_rl_profiles;
779 __le16 max_srl_profiles;
783 struct ice_aqc_query_txsched_res_resp {
784 struct ice_aqc_generic_sched_props sched_props;
785 struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM];
788 /* Get PHY capabilities (indirect 0x0600) */
789 struct ice_aqc_get_phy_caps {
793 /* 18.0 - Report qualified modules */
794 #define ICE_AQC_GET_PHY_RQM BIT(0)
795 /* 18.1 - 18.2 : Report mode
796 * 00b - Report NVM capabilities
797 * 01b - Report topology capabilities
798 * 10b - Report SW configured
800 #define ICE_AQC_REPORT_MODE_S 1
801 #define ICE_AQC_REPORT_MODE_M (3 << ICE_AQC_REPORT_MODE_S)
802 #define ICE_AQC_REPORT_NVM_CAP 0
803 #define ICE_AQC_REPORT_TOPO_CAP BIT(1)
804 #define ICE_AQC_REPORT_SW_CFG BIT(2)
810 /* This is #define of PHY type (Extended):
811 * The first set of defines is for phy_type_low.
813 #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0)
814 #define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1)
815 #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2)
816 #define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3)
817 #define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4)
818 #define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5)
819 #define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6)
820 #define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7)
821 #define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8)
822 #define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9)
823 #define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10)
824 #define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11)
825 #define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12)
826 #define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13)
827 #define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14)
828 #define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15)
829 #define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16)
830 #define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17)
831 #define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18)
832 #define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19)
833 #define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20)
834 #define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21)
835 #define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22)
836 #define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23)
837 #define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24)
838 #define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25)
839 #define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26)
840 #define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27)
841 #define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28)
842 #define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29)
843 #define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30)
844 #define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31)
845 #define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32)
846 #define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33)
847 #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34)
848 #define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35)
849 #define ICE_PHY_TYPE_LOW_MAX_INDEX 63
851 struct ice_aqc_get_phy_caps_data {
852 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
855 #define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0)
856 #define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1)
857 #define ICE_AQC_PHY_LOW_POWER_MODE BIT(2)
858 #define ICE_AQC_PHY_EN_LINK BIT(3)
859 #define ICE_AQC_PHY_AN_MODE BIT(4)
860 #define ICE_AQC_GET_PHY_EN_MOD_QUAL BIT(5)
862 #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0)
864 #define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0)
865 #define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1)
866 #define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2)
867 #define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3)
868 #define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4)
869 #define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5)
870 #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6)
872 u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */
874 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0)
875 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1)
876 #define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2)
877 #define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3)
878 #define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4)
879 #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6)
880 #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7)
881 u8 extended_compliance_code;
882 #define ICE_MODULE_TYPE_TOTAL_BYTE 3
883 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
884 #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0
885 #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80
886 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0)
887 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1)
888 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4)
889 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5)
890 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6)
891 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7)
892 #define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0
893 #define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86
894 u8 qualified_module_count;
895 #define ICE_AQC_QUAL_MOD_COUNT_MAX 16
902 } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX];
905 /* Set PHY capabilities (direct 0x0601)
906 * NOTE: This command must be followed by setup link and restart auto-neg
908 struct ice_aqc_set_phy_cfg {
915 /* Set PHY config command data structure */
916 struct ice_aqc_set_phy_cfg_data {
917 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
920 #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0)
921 #define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1)
922 #define ICE_AQ_PHY_ENA_LOW_POWER BIT(2)
923 #define ICE_AQ_PHY_ENA_LINK BIT(3)
924 #define ICE_AQ_PHY_ENA_ATOMIC_LINK BIT(5)
926 __le16 eee_cap; /* Value from ice_aqc_get_phy_caps */
928 u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */
932 /* Restart AN command data structure (direct 0x0605)
933 * Also used for response, with only the lport_num field present.
935 struct ice_aqc_restart_an {
939 #define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1)
940 #define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2)
944 /* Get link status (indirect 0x0607), also used for Link Status Event */
945 struct ice_aqc_get_link_status {
949 #define ICE_AQ_LSE_M 0x3
950 #define ICE_AQ_LSE_NOP 0x0
951 #define ICE_AQ_LSE_DIS 0x2
952 #define ICE_AQ_LSE_ENA 0x3
953 /* only response uses this flag */
954 #define ICE_AQ_LSE_IS_ENABLED 0x1
960 /* Get link status response data structure, also used for Link Status Event */
961 struct ice_aqc_get_link_status_data {
962 u8 topo_media_conflict;
963 #define ICE_AQ_LINK_TOPO_CONFLICT BIT(0)
964 #define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1)
965 #define ICE_AQ_LINK_TOPO_CORRUPT BIT(2)
968 #define ICE_AQ_LINK_UP BIT(0) /* Link Status */
969 #define ICE_AQ_LINK_FAULT BIT(1)
970 #define ICE_AQ_LINK_FAULT_TX BIT(2)
971 #define ICE_AQ_LINK_FAULT_RX BIT(3)
972 #define ICE_AQ_LINK_FAULT_REMOTE BIT(4)
973 #define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */
974 #define ICE_AQ_MEDIA_AVAILABLE BIT(6)
975 #define ICE_AQ_SIGNAL_DETECT BIT(7)
977 #define ICE_AQ_AN_COMPLETED BIT(0)
978 #define ICE_AQ_LP_AN_ABILITY BIT(1)
979 #define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */
980 #define ICE_AQ_FEC_EN BIT(3)
981 #define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */
982 #define ICE_AQ_LINK_PAUSE_TX BIT(5)
983 #define ICE_AQ_LINK_PAUSE_RX BIT(6)
984 #define ICE_AQ_QUALIFIED_MODULE BIT(7)
986 #define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0)
987 #define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */
988 /* Port TX Suspended */
989 #define ICE_AQ_LINK_TX_S 2
990 #define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S)
991 #define ICE_AQ_LINK_TX_ACTIVE 0
992 #define ICE_AQ_LINK_TX_DRAINED 1
993 #define ICE_AQ_LINK_TX_FLUSHED 3
995 __le16 max_frame_size;
997 #define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0)
998 #define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1)
999 #define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2)
1001 #define ICE_AQ_CFG_PACING_S 3
1002 #define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S)
1003 #define ICE_AQ_CFG_PACING_TYPE_M BIT(7)
1004 #define ICE_AQ_CFG_PACING_TYPE_AVG 0
1005 #define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M
1006 /* External Device Power Ability */
1008 #define ICE_AQ_PWR_CLASS_M 0x3
1009 #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0
1010 #define ICE_AQ_LINK_PWR_BASET_HIGH 1
1011 #define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0
1012 #define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1
1013 #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2
1014 #define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3
1016 #define ICE_AQ_LINK_SPEED_10MB BIT(0)
1017 #define ICE_AQ_LINK_SPEED_100MB BIT(1)
1018 #define ICE_AQ_LINK_SPEED_1000MB BIT(2)
1019 #define ICE_AQ_LINK_SPEED_2500MB BIT(3)
1020 #define ICE_AQ_LINK_SPEED_5GB BIT(4)
1021 #define ICE_AQ_LINK_SPEED_10GB BIT(5)
1022 #define ICE_AQ_LINK_SPEED_20GB BIT(6)
1023 #define ICE_AQ_LINK_SPEED_25GB BIT(7)
1024 #define ICE_AQ_LINK_SPEED_40GB BIT(8)
1025 #define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15)
1026 __le32 reserved3; /* Aligns next field to 8-byte boundary */
1027 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1031 /* Set event mask command (direct 0x0613) */
1032 struct ice_aqc_set_event_mask {
1036 #define ICE_AQ_LINK_EVENT_UPDOWN BIT(1)
1037 #define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2)
1038 #define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3)
1039 #define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4)
1040 #define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5)
1041 #define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6)
1042 #define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7)
1043 #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8)
1044 #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9)
1048 /* NVM Read command (indirect 0x0701)
1049 * NVM Erase commands (direct 0x0702)
1050 * NVM Update commands (indirect 0x0703)
1052 struct ice_aqc_nvm {
1056 #define ICE_AQC_NVM_LAST_CMD BIT(0)
1057 #define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Update reply */
1058 #define ICE_AQC_NVM_PRESERVATION_S 1
1059 #define ICE_AQC_NVM_PRESERVATION_M (3 << CSR_AQ_NVM_PRESERVATION_S)
1060 #define ICE_AQC_NVM_NO_PRESERVATION (0 << CSR_AQ_NVM_PRESERVATION_S)
1061 #define ICE_AQC_NVM_PRESERVE_ALL BIT(1)
1062 #define ICE_AQC_NVM_PRESERVE_SELECTED (3 << CSR_AQ_NVM_PRESERVATION_S)
1063 #define ICE_AQC_NVM_FLASH_ONLY BIT(7)
1064 __le16 module_typeid;
1066 #define ICE_AQC_NVM_ERASE_LEN 0xFFFF
1071 /* Get/Set RSS key (indirect 0x0B04/0x0B02) */
1072 struct ice_aqc_get_set_rss_key {
1073 #define ICE_AQC_GSET_RSS_KEY_VSI_VALID BIT(15)
1074 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_S 0
1075 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_KEY_VSI_ID_S)
1082 #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28
1083 #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC
1085 struct ice_aqc_get_set_rss_keys {
1086 u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE];
1087 u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE];
1090 /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */
1091 struct ice_aqc_get_set_rss_lut {
1092 #define ICE_AQC_GSET_RSS_LUT_VSI_VALID BIT(15)
1093 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_S 0
1094 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_M (0x1FF << ICE_AQC_GSET_RSS_LUT_VSI_ID_S)
1096 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S 0
1097 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M \
1098 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S)
1100 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI 0
1101 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF 1
1102 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL 2
1104 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S 2
1105 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M \
1106 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S)
1108 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 128
1109 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG 0
1110 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 512
1111 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG 1
1112 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K 2048
1113 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG 2
1115 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S 4
1116 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M \
1117 (0xF << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S)
1125 /* Add TX LAN Queues (indirect 0x0C30) */
1126 struct ice_aqc_add_txqs {
1134 /* This is the descriptor of each queue entry for the Add TX LAN Queues
1135 * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp.
1137 struct ice_aqc_add_txqs_perq {
1143 struct ice_aqc_txsched_elem info;
1146 /* The format of the command buffer for Add TX LAN Queues (0x0C30)
1147 * is an array of the following structs. Please note that the length of
1148 * each struct ice_aqc_add_tx_qgrp is variable due
1149 * to the variable number of queues in each group!
1151 struct ice_aqc_add_tx_qgrp {
1155 struct ice_aqc_add_txqs_perq txqs[1];
1158 /* Disable TX LAN Queues (indirect 0x0C31) */
1159 struct ice_aqc_dis_txqs {
1161 #define ICE_AQC_Q_DIS_CMD_S 0
1162 #define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S)
1163 #define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S)
1164 #define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S)
1165 #define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S)
1166 #define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S)
1167 #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2)
1168 #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3)
1170 __le16 vmvf_and_timeout;
1171 #define ICE_AQC_Q_DIS_VMVF_NUM_S 0
1172 #define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S)
1173 #define ICE_AQC_Q_DIS_TIMEOUT_S 10
1174 #define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S)
1175 __le32 blocked_cgds;
1180 /* The buffer for Disable TX LAN Queues (indirect 0x0C31)
1181 * contains the following structures, arrayed one after the
1183 * Note: Since the q_id is 16 bits wide, if the
1184 * number of queues is even, then 2 bytes of alignment MUST be
1185 * added before the start of the next group, to allow correct
1186 * alignment of the parent_teid field.
1188 struct ice_aqc_dis_txq_item {
1192 /* The length of the q_id array varies according to num_qs */
1194 /* This only applies from F8 onward */
1195 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15
1196 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \
1197 (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)
1198 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \
1199 (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)
1202 struct ice_aqc_dis_txq {
1203 struct ice_aqc_dis_txq_item qgrps[1];
1207 * struct ice_aq_desc - Admin Queue (AQ) descriptor
1208 * @flags: ICE_AQ_FLAG_* flags
1209 * @opcode: AQ command opcode
1210 * @datalen: length in bytes of indirect/external data buffer
1211 * @retval: return value from firmware
1212 * @cookie_h: opaque data high-half
1213 * @cookie_l: opaque data low-half
1214 * @params: command-specific parameters
1216 * Descriptor format for commands the driver posts on the Admin Transmit Queue
1217 * (ATQ). The firmware writes back onto the command descriptor and returns
1218 * the result of the command. Asynchronous events that are not an immediate
1219 * result of the command are written to the Admin Receive Queue (ARQ) using
1220 * the same descriptor format. Descriptors are in little-endian notation with
1223 struct ice_aq_desc {
1232 struct ice_aqc_generic generic;
1233 struct ice_aqc_get_ver get_ver;
1234 struct ice_aqc_q_shutdown q_shutdown;
1235 struct ice_aqc_req_res res_owner;
1236 struct ice_aqc_manage_mac_read mac_read;
1237 struct ice_aqc_manage_mac_write mac_write;
1238 struct ice_aqc_clear_pxe clear_pxe;
1239 struct ice_aqc_list_caps get_cap;
1240 struct ice_aqc_get_phy_caps get_phy;
1241 struct ice_aqc_set_phy_cfg set_phy;
1242 struct ice_aqc_restart_an restart_an;
1243 struct ice_aqc_get_sw_cfg get_sw_conf;
1244 struct ice_aqc_sw_rules sw_rules;
1245 struct ice_aqc_get_topo get_topo;
1246 struct ice_aqc_get_cfg_elem get_update_elem;
1247 struct ice_aqc_query_txsched_res query_sched_res;
1248 struct ice_aqc_add_move_delete_elem add_move_delete_elem;
1249 struct ice_aqc_nvm nvm;
1250 struct ice_aqc_get_set_rss_lut get_set_rss_lut;
1251 struct ice_aqc_get_set_rss_key get_set_rss_key;
1252 struct ice_aqc_add_txqs add_txqs;
1253 struct ice_aqc_dis_txqs dis_txqs;
1254 struct ice_aqc_add_get_update_free_vsi vsi_cmd;
1255 struct ice_aqc_alloc_free_res_cmd sw_res_ctrl;
1256 struct ice_aqc_set_event_mask set_event_mask;
1257 struct ice_aqc_get_link_status get_link_status;
1261 /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */
1262 #define ICE_AQ_LG_BUF 512
1264 #define ICE_AQ_FLAG_ERR_S 2
1265 #define ICE_AQ_FLAG_LB_S 9
1266 #define ICE_AQ_FLAG_RD_S 10
1267 #define ICE_AQ_FLAG_BUF_S 12
1268 #define ICE_AQ_FLAG_SI_S 13
1270 #define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */
1271 #define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */
1272 #define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */
1273 #define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */
1274 #define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */
1278 ICE_AQ_RC_OK = 0, /* success */
1279 ICE_AQ_RC_ENOMEM = 9, /* Out of memory */
1280 ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */
1281 ICE_AQ_RC_EEXIST = 13, /* object already exists */
1282 ICE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */
1285 /* Admin Queue command opcodes */
1286 enum ice_adminq_opc {
1288 ice_aqc_opc_get_ver = 0x0001,
1289 ice_aqc_opc_q_shutdown = 0x0003,
1291 /* resource ownership */
1292 ice_aqc_opc_req_res = 0x0008,
1293 ice_aqc_opc_release_res = 0x0009,
1295 /* device/function capabilities */
1296 ice_aqc_opc_list_func_caps = 0x000A,
1297 ice_aqc_opc_list_dev_caps = 0x000B,
1299 /* manage MAC address */
1300 ice_aqc_opc_manage_mac_read = 0x0107,
1301 ice_aqc_opc_manage_mac_write = 0x0108,
1304 ice_aqc_opc_clear_pxe_mode = 0x0110,
1306 /* internal switch commands */
1307 ice_aqc_opc_get_sw_cfg = 0x0200,
1309 /* Alloc/Free/Get Resources */
1310 ice_aqc_opc_alloc_res = 0x0208,
1311 ice_aqc_opc_free_res = 0x0209,
1314 ice_aqc_opc_add_vsi = 0x0210,
1315 ice_aqc_opc_update_vsi = 0x0211,
1316 ice_aqc_opc_free_vsi = 0x0213,
1318 /* switch rules population commands */
1319 ice_aqc_opc_add_sw_rules = 0x02A0,
1320 ice_aqc_opc_update_sw_rules = 0x02A1,
1321 ice_aqc_opc_remove_sw_rules = 0x02A2,
1323 ice_aqc_opc_clear_pf_cfg = 0x02A4,
1325 /* transmit scheduler commands */
1326 ice_aqc_opc_get_dflt_topo = 0x0400,
1327 ice_aqc_opc_add_sched_elems = 0x0401,
1328 ice_aqc_opc_suspend_sched_elems = 0x0409,
1329 ice_aqc_opc_resume_sched_elems = 0x040A,
1330 ice_aqc_opc_delete_sched_elems = 0x040F,
1331 ice_aqc_opc_query_sched_res = 0x0412,
1334 ice_aqc_opc_get_phy_caps = 0x0600,
1335 ice_aqc_opc_set_phy_cfg = 0x0601,
1336 ice_aqc_opc_restart_an = 0x0605,
1337 ice_aqc_opc_get_link_status = 0x0607,
1338 ice_aqc_opc_set_event_mask = 0x0613,
1341 ice_aqc_opc_nvm_read = 0x0701,
1344 ice_aqc_opc_set_rss_key = 0x0B02,
1345 ice_aqc_opc_set_rss_lut = 0x0B03,
1346 ice_aqc_opc_get_rss_key = 0x0B04,
1347 ice_aqc_opc_get_rss_lut = 0x0B05,
1349 /* TX queue handling commands/events */
1350 ice_aqc_opc_add_txqs = 0x0C30,
1351 ice_aqc_opc_dis_txqs = 0x0C31,
1354 #endif /* _ICE_ADMINQ_CMD_H_ */