1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018, Intel Corporation. */
4 #ifndef _ICE_ADMINQ_CMD_H_
5 #define _ICE_ADMINQ_CMD_H_
7 /* This header file defines the Admin Queue commands, error codes and
8 * descriptor format. It is shared between Firmware and Software.
11 #define ICE_MAX_VSI 768
12 #define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9
13 #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728
15 struct ice_aqc_generic {
22 /* Get version (direct 0x0001) */
23 struct ice_aqc_get_ver {
36 /* Send driver version (indirect 0x0002) */
37 struct ice_aqc_driver_ver {
47 /* Queue Shutdown (direct 0x0003) */
48 struct ice_aqc_q_shutdown {
50 #define ICE_AQC_DRIVER_UNLOADING BIT(0)
54 /* Request resource ownership (direct 0x0008)
55 * Release resource ownership (direct 0x0009)
57 struct ice_aqc_req_res {
59 #define ICE_AQC_RES_ID_NVM 1
60 #define ICE_AQC_RES_ID_SDP 2
61 #define ICE_AQC_RES_ID_CHNG_LOCK 3
62 #define ICE_AQC_RES_ID_GLBL_LOCK 4
64 #define ICE_AQC_RES_ACCESS_READ 1
65 #define ICE_AQC_RES_ACCESS_WRITE 2
67 /* Upon successful completion, FW writes this value and driver is
68 * expected to release resource before timeout. This value is provided
72 #define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000
73 #define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000
74 #define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000
75 #define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000
76 /* For SDP: pin ID of the SDP */
78 /* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */
80 #define ICE_AQ_RES_GLBL_SUCCESS 0
81 #define ICE_AQ_RES_GLBL_IN_PROG 1
82 #define ICE_AQ_RES_GLBL_DONE 2
86 /* Get function capabilities (indirect 0x000A)
87 * Get device capabilities (indirect 0x000B)
89 struct ice_aqc_list_caps {
98 /* Device/Function buffer entry, repeated per reported capability */
99 struct ice_aqc_list_caps_elem {
101 #define ICE_AQC_CAPS_VALID_FUNCTIONS 0x0005
102 #define ICE_AQC_CAPS_SRIOV 0x0012
103 #define ICE_AQC_CAPS_VF 0x0013
104 #define ICE_AQC_CAPS_VSI 0x0017
105 #define ICE_AQC_CAPS_DCB 0x0018
106 #define ICE_AQC_CAPS_RSS 0x0040
107 #define ICE_AQC_CAPS_RXQS 0x0041
108 #define ICE_AQC_CAPS_TXQS 0x0042
109 #define ICE_AQC_CAPS_MSIX 0x0043
110 #define ICE_AQC_CAPS_FD 0x0045
111 #define ICE_AQC_CAPS_MAX_MTU 0x0047
112 #define ICE_AQC_CAPS_NVM_MGMT 0x0080
116 /* Number of resources described by this capability */
118 /* Only meaningful for some types of resources */
120 /* Only meaningful for some types of resources */
126 /* Manage MAC address, read command - indirect (0x0107)
127 * This struct is also used for the response
129 struct ice_aqc_manage_mac_read {
130 __le16 flags; /* Zeroed by device driver */
131 #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4)
132 #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5)
133 #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6)
134 #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7)
135 #define ICE_AQC_MAN_MAC_READ_S 4
136 #define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S)
138 u8 num_addr; /* Used in response */
144 /* Response buffer format for manage MAC read command */
145 struct ice_aqc_manage_mac_read_resp {
148 #define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0
149 #define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1
150 u8 mac_addr[ETH_ALEN];
153 /* Manage MAC address, write command - direct (0x0108) */
154 struct ice_aqc_manage_mac_write {
157 #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0)
158 #define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1)
159 #define ICE_AQC_MAN_MAC_WR_S 6
160 #define ICE_AQC_MAN_MAC_WR_M ICE_M(3, ICE_AQC_MAN_MAC_WR_S)
161 #define ICE_AQC_MAN_MAC_UPDATE_LAA 0
162 #define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL BIT(ICE_AQC_MAN_MAC_WR_S)
163 /* byte stream in network order */
164 u8 mac_addr[ETH_ALEN];
169 /* Clear PXE Command and response (direct 0x0110) */
170 struct ice_aqc_clear_pxe {
172 #define ICE_AQC_CLEAR_PXE_RX_CNT 0x2
176 /* Get switch configuration (0x0200) */
177 struct ice_aqc_get_sw_cfg {
178 /* Reserved for command and copy of request flags for response */
180 /* First desc in case of command and next_elem in case of response
181 * In case of response, if it is not zero, means all the configuration
182 * was not returned and new command shall be sent with this value in
183 * the 'first desc' field
186 /* Reserved for command, only used for response */
193 /* Each entry in the response buffer is of the following type: */
194 struct ice_aqc_get_sw_cfg_resp_elem {
195 /* VSI/Port Number */
197 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0
198 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \
199 (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S)
200 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14
201 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S)
202 #define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0
203 #define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1
204 #define ICE_AQC_GET_SW_CONF_RESP_VSI 2
206 /* SWID VSI/Port belongs to */
209 /* Bit 14..0 : PF/VF number VSI belongs to
210 * Bit 15 : VF indication bit
213 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0
214 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \
215 (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S)
216 #define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15)
219 /* These resource type defines are used for all switch resource
220 * commands where a resource type is required, such as:
221 * Get Resource Allocation command (indirect 0x0204)
222 * Allocate Resources command (indirect 0x0208)
223 * Free Resources command (indirect 0x0209)
224 * Get Allocated Resource Descriptors Command (indirect 0x020A)
226 #define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03
227 #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04
228 #define ICE_AQC_RES_TYPE_FDIR_COUNTER_BLOCK 0x21
229 #define ICE_AQC_RES_TYPE_FDIR_GUARANTEED_ENTRIES 0x22
230 #define ICE_AQC_RES_TYPE_FDIR_SHARED_ENTRIES 0x23
231 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID 0x58
232 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_TCAM 0x59
233 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID 0x60
234 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_TCAM 0x61
236 #define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM BIT(12)
237 #define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX BIT(13)
239 #define ICE_AQC_RES_TYPE_FLAG_DEDICATED 0x00
241 #define ICE_AQC_RES_TYPE_S 0
242 #define ICE_AQC_RES_TYPE_M (0x07F << ICE_AQC_RES_TYPE_S)
244 /* Allocate Resources command (indirect 0x0208)
245 * Free Resources command (indirect 0x0209)
247 struct ice_aqc_alloc_free_res_cmd {
248 __le16 num_entries; /* Number of Resource entries */
254 /* Resource descriptor */
255 struct ice_aqc_res_elem {
262 /* Buffer for Allocate/Free Resources commands */
263 struct ice_aqc_alloc_free_res_elem {
264 __le16 res_type; /* Types defined above cmd 0x0204 */
265 #define ICE_AQC_RES_TYPE_SHARED_S 7
266 #define ICE_AQC_RES_TYPE_SHARED_M (0x1 << ICE_AQC_RES_TYPE_SHARED_S)
267 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8
268 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \
269 (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S)
271 struct ice_aqc_res_elem elem[];
274 /* Add VSI (indirect 0x0210)
275 * Update VSI (indirect 0x0211)
276 * Get VSI (indirect 0x0212)
277 * Free VSI (indirect 0x0213)
279 struct ice_aqc_add_get_update_free_vsi {
281 #define ICE_AQ_VSI_NUM_S 0
282 #define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S)
283 #define ICE_AQ_VSI_IS_VALID BIT(15)
285 #define ICE_AQ_VSI_KEEP_ALLOC 0x1
289 #define ICE_AQ_VSI_TYPE_S 0
290 #define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S)
291 #define ICE_AQ_VSI_TYPE_VF 0x0
292 #define ICE_AQ_VSI_TYPE_VMDQ2 0x1
293 #define ICE_AQ_VSI_TYPE_PF 0x2
294 #define ICE_AQ_VSI_TYPE_EMP_MNG 0x3
299 /* Response descriptor for:
300 * Add VSI (indirect 0x0210)
301 * Update VSI (indirect 0x0211)
302 * Free VSI (indirect 0x0213)
304 struct ice_aqc_add_update_free_vsi_resp {
313 struct ice_aqc_vsi_props {
314 __le16 valid_sections;
315 #define ICE_AQ_VSI_PROP_SW_VALID BIT(0)
316 #define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1)
317 #define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2)
318 #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3)
319 #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4)
320 #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5)
321 #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6)
322 #define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7)
323 #define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8)
324 #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11)
325 #define ICE_AQ_VSI_PROP_PASID_VALID BIT(12)
329 #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5)
330 #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6)
331 #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7)
333 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0
334 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M \
335 (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S)
336 #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0)
337 #define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4)
339 #define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0
340 #define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S)
341 #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5)
342 /* security section */
344 #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0)
345 #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2)
346 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4
347 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S)
348 #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0)
351 __le16 pvid; /* VLANS include priority bits */
352 u8 pvlan_reserved[2];
354 #define ICE_AQ_VSI_VLAN_MODE_S 0
355 #define ICE_AQ_VSI_VLAN_MODE_M (0x3 << ICE_AQ_VSI_VLAN_MODE_S)
356 #define ICE_AQ_VSI_VLAN_MODE_UNTAGGED 0x1
357 #define ICE_AQ_VSI_VLAN_MODE_TAGGED 0x2
358 #define ICE_AQ_VSI_VLAN_MODE_ALL 0x3
359 #define ICE_AQ_VSI_PVLAN_INSERT_PVID BIT(2)
360 #define ICE_AQ_VSI_VLAN_EMOD_S 3
361 #define ICE_AQ_VSI_VLAN_EMOD_M (0x3 << ICE_AQ_VSI_VLAN_EMOD_S)
362 #define ICE_AQ_VSI_VLAN_EMOD_STR_BOTH (0x0 << ICE_AQ_VSI_VLAN_EMOD_S)
363 #define ICE_AQ_VSI_VLAN_EMOD_STR_UP (0x1 << ICE_AQ_VSI_VLAN_EMOD_S)
364 #define ICE_AQ_VSI_VLAN_EMOD_STR (0x2 << ICE_AQ_VSI_VLAN_EMOD_S)
365 #define ICE_AQ_VSI_VLAN_EMOD_NOTHING (0x3 << ICE_AQ_VSI_VLAN_EMOD_S)
366 u8 pvlan_reserved2[3];
367 /* ingress egress up sections */
368 __le32 ingress_table; /* bitmap, 3 bits per up */
369 #define ICE_AQ_VSI_UP_TABLE_UP0_S 0
370 #define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S)
371 #define ICE_AQ_VSI_UP_TABLE_UP1_S 3
372 #define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S)
373 #define ICE_AQ_VSI_UP_TABLE_UP2_S 6
374 #define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S)
375 #define ICE_AQ_VSI_UP_TABLE_UP3_S 9
376 #define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S)
377 #define ICE_AQ_VSI_UP_TABLE_UP4_S 12
378 #define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S)
379 #define ICE_AQ_VSI_UP_TABLE_UP5_S 15
380 #define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S)
381 #define ICE_AQ_VSI_UP_TABLE_UP6_S 18
382 #define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S)
383 #define ICE_AQ_VSI_UP_TABLE_UP7_S 21
384 #define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S)
385 __le32 egress_table; /* same defines as for ingress table */
386 /* outer tags section */
389 #define ICE_AQ_VSI_OUTER_TAG_MODE_S 0
390 #define ICE_AQ_VSI_OUTER_TAG_MODE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_MODE_S)
391 #define ICE_AQ_VSI_OUTER_TAG_NOTHING 0x0
392 #define ICE_AQ_VSI_OUTER_TAG_REMOVE 0x1
393 #define ICE_AQ_VSI_OUTER_TAG_COPY 0x2
394 #define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2
395 #define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S)
396 #define ICE_AQ_VSI_OUTER_TAG_NONE 0x0
397 #define ICE_AQ_VSI_OUTER_TAG_STAG 0x1
398 #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2
399 #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3
400 #define ICE_AQ_VSI_OUTER_TAG_INSERT BIT(4)
401 #define ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST BIT(6)
402 u8 outer_tag_reserved;
403 /* queue mapping section */
404 __le16 mapping_flags;
405 #define ICE_AQ_VSI_Q_MAP_CONTIG 0x0
406 #define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0)
407 __le16 q_mapping[16];
408 #define ICE_AQ_VSI_Q_S 0
409 #define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S)
410 __le16 tc_mapping[8];
411 #define ICE_AQ_VSI_TC_Q_OFFSET_S 0
412 #define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S)
413 #define ICE_AQ_VSI_TC_Q_NUM_S 11
414 #define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S)
415 /* queueing option section */
417 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0
418 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S)
419 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0
420 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2
421 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3
422 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2
423 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S)
424 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6
425 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
426 #define ICE_AQ_VSI_Q_OPT_RSS_TPLZ (0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
427 #define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ (0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
428 #define ICE_AQ_VSI_Q_OPT_RSS_XOR (0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
429 #define ICE_AQ_VSI_Q_OPT_RSS_JHASH (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
431 #define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0
432 #define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S)
433 #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7)
435 #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0)
436 u8 q_opt_reserved[3];
437 /* outer up section */
438 __le32 outer_up_table; /* same structure and defines as ingress tbl */
440 __le16 sect_10_reserved;
441 /* flow director section */
443 #define ICE_AQ_VSI_FD_ENABLE BIT(0)
444 #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1)
445 #define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3)
446 __le16 max_fd_fltr_dedicated;
447 __le16 max_fd_fltr_shared;
449 #define ICE_AQ_VSI_FD_DEF_Q_S 0
450 #define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S)
451 #define ICE_AQ_VSI_FD_DEF_GRP_S 12
452 #define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S)
453 __le16 fd_report_opt;
454 #define ICE_AQ_VSI_FD_REPORT_Q_S 0
455 #define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S)
456 #define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12
457 #define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S)
458 #define ICE_AQ_VSI_FD_DEF_DROP BIT(15)
461 #define ICE_AQ_VSI_PASID_ID_S 0
462 #define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S)
463 #define ICE_AQ_VSI_PASID_ID_VALID BIT(31)
467 #define ICE_MAX_NUM_RECIPES 64
469 /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3)
471 struct ice_aqc_sw_rules {
472 /* ops: add switch rules, referring the number of rules.
473 * ops: update switch rules, referring the number of filters
474 * ops: remove switch rules, referring the entry index.
475 * ops: get switch rules, referring to the number of filters.
477 __le16 num_rules_fltr_entry_index;
483 /* Add/Update/Get/Remove lookup Rx/Tx command/response entry
484 * This structures describes the lookup rules and associated actions. "index"
485 * is returned as part of a response to a successful Add command, and can be
486 * used to identify the rule for Update/Get/Remove commands.
488 struct ice_sw_rule_lkup_rx_tx {
490 #define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10
491 /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */
495 /* Bit 0:1 - Action type */
496 #define ICE_SINGLE_ACT_TYPE_S 0x00
497 #define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S)
499 /* Bit 2 - Loop back enable
502 #define ICE_SINGLE_ACT_LB_ENABLE BIT(2)
503 #define ICE_SINGLE_ACT_LAN_ENABLE BIT(3)
505 /* Action type = 0 - Forward to VSI or VSI list */
506 #define ICE_SINGLE_ACT_VSI_FORWARDING 0x0
508 #define ICE_SINGLE_ACT_VSI_ID_S 4
509 #define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S)
510 #define ICE_SINGLE_ACT_VSI_LIST_ID_S 4
511 #define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S)
512 /* This bit needs to be set if action is forward to VSI list */
513 #define ICE_SINGLE_ACT_VSI_LIST BIT(14)
514 #define ICE_SINGLE_ACT_VALID_BIT BIT(17)
515 #define ICE_SINGLE_ACT_DROP BIT(18)
517 /* Action type = 1 - Forward to Queue of Queue group */
518 #define ICE_SINGLE_ACT_TO_Q 0x1
519 #define ICE_SINGLE_ACT_Q_INDEX_S 4
520 #define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S)
521 #define ICE_SINGLE_ACT_Q_REGION_S 15
522 #define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S)
523 #define ICE_SINGLE_ACT_Q_PRIORITY BIT(18)
525 /* Action type = 2 - Prune */
526 #define ICE_SINGLE_ACT_PRUNE 0x2
527 #define ICE_SINGLE_ACT_EGRESS BIT(15)
528 #define ICE_SINGLE_ACT_INGRESS BIT(16)
529 #define ICE_SINGLE_ACT_PRUNET BIT(17)
530 /* Bit 18 should be set to 0 for this action */
532 /* Action type = 2 - Pointer */
533 #define ICE_SINGLE_ACT_PTR 0x2
534 #define ICE_SINGLE_ACT_PTR_VAL_S 4
535 #define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S)
536 /* Bit 18 should be set to 1 */
537 #define ICE_SINGLE_ACT_PTR_BIT BIT(18)
539 /* Action type = 3 - Other actions. Last two bits
540 * are other action identifier
542 #define ICE_SINGLE_ACT_OTHER_ACTS 0x3
543 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17
544 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \
545 (0x3 << ICE_SINGLE_OTHER_ACT_IDENTIFIER_S)
547 /* Bit 17:18 - Defines other actions */
548 /* Other action = 0 - Mirror VSI */
549 #define ICE_SINGLE_OTHER_ACT_MIRROR 0
550 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4
551 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \
552 (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S)
554 /* Other action = 3 - Set Stat count */
555 #define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3
556 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4
557 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \
558 (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S)
560 __le16 index; /* The index of the rule in the lookup table */
561 /* Length and values of the header to be matched per recipe or
568 /* Add/Update/Remove large action command/response entry
569 * "index" is returned as part of a response to a successful Add command, and
570 * can be used to identify the action for Update/Get/Remove commands.
572 struct ice_sw_rule_lg_act {
573 __le16 index; /* Index in large action table */
575 /* Max number of large actions */
576 #define ICE_MAX_LG_ACT 4
577 /* Bit 0:1 - Action type */
578 #define ICE_LG_ACT_TYPE_S 0
579 #define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S)
581 /* Action type = 0 - Forward to VSI or VSI list */
582 #define ICE_LG_ACT_VSI_FORWARDING 0
583 #define ICE_LG_ACT_VSI_ID_S 3
584 #define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S)
585 #define ICE_LG_ACT_VSI_LIST_ID_S 3
586 #define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S)
587 /* This bit needs to be set if action is forward to VSI list */
588 #define ICE_LG_ACT_VSI_LIST BIT(13)
590 #define ICE_LG_ACT_VALID_BIT BIT(16)
592 /* Action type = 1 - Forward to Queue of Queue group */
593 #define ICE_LG_ACT_TO_Q 0x1
594 #define ICE_LG_ACT_Q_INDEX_S 3
595 #define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S)
596 #define ICE_LG_ACT_Q_REGION_S 14
597 #define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S)
598 #define ICE_LG_ACT_Q_PRIORITY_SET BIT(17)
600 /* Action type = 2 - Prune */
601 #define ICE_LG_ACT_PRUNE 0x2
602 #define ICE_LG_ACT_EGRESS BIT(14)
603 #define ICE_LG_ACT_INGRESS BIT(15)
604 #define ICE_LG_ACT_PRUNET BIT(16)
606 /* Action type = 3 - Mirror VSI */
607 #define ICE_LG_OTHER_ACT_MIRROR 0x3
608 #define ICE_LG_ACT_MIRROR_VSI_ID_S 3
609 #define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S)
611 /* Action type = 5 - Generic Value */
612 #define ICE_LG_ACT_GENERIC 0x5
613 #define ICE_LG_ACT_GENERIC_VALUE_S 3
614 #define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S)
615 #define ICE_LG_ACT_GENERIC_OFFSET_S 19
616 #define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S)
617 #define ICE_LG_ACT_GENERIC_PRIORITY_S 22
618 #define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S)
619 #define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX 7
621 /* Action = 7 - Set Stat count */
622 #define ICE_LG_ACT_STAT_COUNT 0x7
623 #define ICE_LG_ACT_STAT_COUNT_S 3
624 #define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S)
625 __le32 act[]; /* array of size for actions */
628 /* Add/Update/Remove VSI list command/response entry
629 * "index" is returned as part of a response to a successful Add command, and
630 * can be used to identify the VSI list for Update/Get/Remove commands.
632 struct ice_sw_rule_vsi_list {
633 __le16 index; /* Index of VSI/Prune list */
635 __le16 vsi[]; /* Array of number_vsi VSI numbers */
638 /* Query VSI list command/response entry */
639 struct ice_sw_rule_vsi_list_query {
641 DECLARE_BITMAP(vsi_list, ICE_MAX_VSI);
644 /* Add switch rule response:
645 * Content of return buffer is same as the input buffer. The status field and
646 * LUT index are updated as part of the response
648 struct ice_aqc_sw_rules_elem {
649 __le16 type; /* Switch rule type, one of T_... */
650 #define ICE_AQC_SW_RULES_T_LKUP_RX 0x0
651 #define ICE_AQC_SW_RULES_T_LKUP_TX 0x1
652 #define ICE_AQC_SW_RULES_T_LG_ACT 0x2
653 #define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3
654 #define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4
655 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5
656 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6
659 struct ice_sw_rule_lkup_rx_tx lkup_tx_rx;
660 struct ice_sw_rule_lg_act lg_act;
661 struct ice_sw_rule_vsi_list vsi_list;
662 struct ice_sw_rule_vsi_list_query vsi_list_query;
666 /* Get Default Topology (indirect 0x0400) */
667 struct ice_aqc_get_topo {
676 /* Update TSE (indirect 0x0403)
677 * Get TSE (indirect 0x0404)
678 * Add TSE (indirect 0x0401)
679 * Delete TSE (indirect 0x040F)
680 * Move TSE (indirect 0x0408)
681 * Suspend Nodes (indirect 0x0409)
682 * Resume Nodes (indirect 0x040A)
684 struct ice_aqc_sched_elem_cmd {
685 __le16 num_elem_req; /* Used by commands */
686 __le16 num_elem_resp; /* Used by responses */
692 struct ice_aqc_elem_info_bw {
693 __le16 bw_profile_idx;
697 struct ice_aqc_txsched_elem {
698 u8 elem_type; /* Special field, reserved for some aq calls */
699 #define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0
700 #define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1
701 #define ICE_AQC_ELEM_TYPE_TC 0x2
702 #define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3
703 #define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4
704 #define ICE_AQC_ELEM_TYPE_LEAF 0x5
705 #define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6
707 #define ICE_AQC_ELEM_VALID_GENERIC BIT(0)
708 #define ICE_AQC_ELEM_VALID_CIR BIT(1)
709 #define ICE_AQC_ELEM_VALID_EIR BIT(2)
710 #define ICE_AQC_ELEM_VALID_SHARED BIT(3)
712 #define ICE_AQC_ELEM_GENERIC_MODE_M 0x1
713 #define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1
714 #define ICE_AQC_ELEM_GENERIC_PRIO_M (0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S)
715 #define ICE_AQC_ELEM_GENERIC_SP_S 0x4
716 #define ICE_AQC_ELEM_GENERIC_SP_M (0x1 << ICE_AQC_ELEM_GENERIC_SP_S)
717 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5
718 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \
719 (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S)
720 u8 flags; /* Special field, reserved for some aq calls */
721 #define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1
722 struct ice_aqc_elem_info_bw cir_bw;
723 struct ice_aqc_elem_info_bw eir_bw;
728 struct ice_aqc_txsched_elem_data {
731 struct ice_aqc_txsched_elem data;
734 struct ice_aqc_txsched_topo_grp_info_hdr {
740 struct ice_aqc_add_elem {
741 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
742 struct ice_aqc_txsched_elem_data generic[];
745 struct ice_aqc_get_topo_elem {
746 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
747 struct ice_aqc_txsched_elem_data
748 generic[ICE_AQC_TOPO_MAX_LEVEL_NUM];
751 struct ice_aqc_delete_elem {
752 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
756 /* Query Port ETS (indirect 0x040E)
758 * This indirect command is used to query port TC node configuration.
760 struct ice_aqc_query_port_ets {
767 struct ice_aqc_port_ets_elem {
770 /* 3 bits for UP per TC 0-7, 4th byte reserved */
773 __le32 port_eir_prof_id;
774 __le32 port_cir_prof_id;
775 /* 3 bits per Node priority to TC 0-7, 4th byte reserved */
777 #define ICE_TC_NODE_PRIO_S 0x4
779 __le32 tc_node_teid[8]; /* Used for response, reserved in command */
782 /* Rate limiting profile for
783 * Add RL profile (indirect 0x0410)
784 * Query RL profile (indirect 0x0411)
785 * Remove RL profile (indirect 0x0415)
786 * These indirect commands acts on single or multiple
787 * RL profiles with specified data.
789 struct ice_aqc_rl_profile {
791 __le16 num_processed; /* Only for response. Reserved in Command. */
797 struct ice_aqc_rl_profile_elem {
800 #define ICE_AQC_RL_PROFILE_TYPE_S 0x0
801 #define ICE_AQC_RL_PROFILE_TYPE_M (0x3 << ICE_AQC_RL_PROFILE_TYPE_S)
802 #define ICE_AQC_RL_PROFILE_TYPE_CIR 0
803 #define ICE_AQC_RL_PROFILE_TYPE_EIR 1
804 #define ICE_AQC_RL_PROFILE_TYPE_SRL 2
805 /* The following flag is used for Query RL Profile Data */
806 #define ICE_AQC_RL_PROFILE_INVAL_S 0x7
807 #define ICE_AQC_RL_PROFILE_INVAL_M (0x1 << ICE_AQC_RL_PROFILE_INVAL_S)
810 __le16 max_burst_size;
816 /* Query Scheduler Resource Allocation (indirect 0x0412)
817 * This indirect command retrieves the scheduler resources allocated by
818 * EMP Firmware to the given PF.
820 struct ice_aqc_query_txsched_res {
826 struct ice_aqc_generic_sched_props {
828 __le16 logical_levels;
829 u8 flattening_bitmap;
837 struct ice_aqc_layer_props {
840 __le16 max_device_nodes;
843 __le16 max_sibl_grp_sz;
844 __le16 max_cir_rl_profiles;
845 __le16 max_eir_rl_profiles;
846 __le16 max_srl_profiles;
850 struct ice_aqc_query_txsched_res_resp {
851 struct ice_aqc_generic_sched_props sched_props;
852 struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM];
855 /* Get PHY capabilities (indirect 0x0600) */
856 struct ice_aqc_get_phy_caps {
860 /* 18.0 - Report qualified modules */
861 #define ICE_AQC_GET_PHY_RQM BIT(0)
862 /* 18.1 - 18.2 : Report mode
863 * 00b - Report NVM capabilities
864 * 01b - Report topology capabilities
865 * 10b - Report SW configured
867 #define ICE_AQC_REPORT_MODE_S 1
868 #define ICE_AQC_REPORT_MODE_M (3 << ICE_AQC_REPORT_MODE_S)
869 #define ICE_AQC_REPORT_NVM_CAP 0
870 #define ICE_AQC_REPORT_TOPO_CAP BIT(1)
871 #define ICE_AQC_REPORT_SW_CFG BIT(2)
877 /* This is #define of PHY type (Extended):
878 * The first set of defines is for phy_type_low.
880 #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0)
881 #define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1)
882 #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2)
883 #define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3)
884 #define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4)
885 #define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5)
886 #define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6)
887 #define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7)
888 #define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8)
889 #define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9)
890 #define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10)
891 #define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11)
892 #define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12)
893 #define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13)
894 #define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14)
895 #define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15)
896 #define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16)
897 #define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17)
898 #define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18)
899 #define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19)
900 #define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20)
901 #define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21)
902 #define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22)
903 #define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23)
904 #define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24)
905 #define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25)
906 #define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26)
907 #define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27)
908 #define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28)
909 #define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29)
910 #define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30)
911 #define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31)
912 #define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32)
913 #define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33)
914 #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34)
915 #define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35)
916 #define ICE_PHY_TYPE_LOW_50GBASE_CR2 BIT_ULL(36)
917 #define ICE_PHY_TYPE_LOW_50GBASE_SR2 BIT_ULL(37)
918 #define ICE_PHY_TYPE_LOW_50GBASE_LR2 BIT_ULL(38)
919 #define ICE_PHY_TYPE_LOW_50GBASE_KR2 BIT_ULL(39)
920 #define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC BIT_ULL(40)
921 #define ICE_PHY_TYPE_LOW_50G_LAUI2 BIT_ULL(41)
922 #define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC BIT_ULL(42)
923 #define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43)
924 #define ICE_PHY_TYPE_LOW_50GBASE_CP BIT_ULL(44)
925 #define ICE_PHY_TYPE_LOW_50GBASE_SR BIT_ULL(45)
926 #define ICE_PHY_TYPE_LOW_50GBASE_FR BIT_ULL(46)
927 #define ICE_PHY_TYPE_LOW_50GBASE_LR BIT_ULL(47)
928 #define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 BIT_ULL(48)
929 #define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC BIT_ULL(49)
930 #define ICE_PHY_TYPE_LOW_50G_AUI1 BIT_ULL(50)
931 #define ICE_PHY_TYPE_LOW_100GBASE_CR4 BIT_ULL(51)
932 #define ICE_PHY_TYPE_LOW_100GBASE_SR4 BIT_ULL(52)
933 #define ICE_PHY_TYPE_LOW_100GBASE_LR4 BIT_ULL(53)
934 #define ICE_PHY_TYPE_LOW_100GBASE_KR4 BIT_ULL(54)
935 #define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC BIT_ULL(55)
936 #define ICE_PHY_TYPE_LOW_100G_CAUI4 BIT_ULL(56)
937 #define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC BIT_ULL(57)
938 #define ICE_PHY_TYPE_LOW_100G_AUI4 BIT_ULL(58)
939 #define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 BIT_ULL(59)
940 #define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 BIT_ULL(60)
941 #define ICE_PHY_TYPE_LOW_100GBASE_CP2 BIT_ULL(61)
942 #define ICE_PHY_TYPE_LOW_100GBASE_SR2 BIT_ULL(62)
943 #define ICE_PHY_TYPE_LOW_100GBASE_DR BIT_ULL(63)
944 #define ICE_PHY_TYPE_LOW_MAX_INDEX 63
945 /* The second set of defines is for phy_type_high. */
946 #define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 BIT_ULL(0)
947 #define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC BIT_ULL(1)
948 #define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2)
949 #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3)
950 #define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4)
951 #define ICE_PHY_TYPE_HIGH_MAX_INDEX 5
953 struct ice_aqc_get_phy_caps_data {
954 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
955 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
957 #define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0)
958 #define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1)
959 #define ICE_AQC_PHY_LOW_POWER_MODE BIT(2)
960 #define ICE_AQC_PHY_EN_LINK BIT(3)
961 #define ICE_AQC_PHY_AN_MODE BIT(4)
962 #define ICE_AQC_GET_PHY_EN_MOD_QUAL BIT(5)
963 #define ICE_AQC_PHY_EN_AUTO_FEC BIT(7)
964 #define ICE_AQC_PHY_CAPS_MASK ICE_M(0xff, 0)
965 u8 low_power_ctrl_an;
966 #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0)
967 #define ICE_AQC_PHY_AN_EN_CLAUSE28 BIT(1)
968 #define ICE_AQC_PHY_AN_EN_CLAUSE73 BIT(2)
969 #define ICE_AQC_PHY_AN_EN_CLAUSE37 BIT(3)
971 #define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0)
972 #define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1)
973 #define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2)
974 #define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3)
975 #define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4)
976 #define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5)
977 #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6)
979 u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */
982 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0)
983 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1)
984 #define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2)
985 #define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3)
986 #define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4)
987 #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6)
988 #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7)
989 #define ICE_AQC_PHY_FEC_MASK ICE_M(0xdf, 0)
990 u8 module_compliance_enforcement;
991 #define ICE_AQC_MOD_ENFORCE_STRICT_MODE BIT(0)
992 u8 extended_compliance_code;
993 #define ICE_MODULE_TYPE_TOTAL_BYTE 3
994 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
995 #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0
996 #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80
997 #define ICE_AQC_MOD_TYPE_IDENT 1
998 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0)
999 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1)
1000 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4)
1001 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5)
1002 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6)
1003 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7)
1004 #define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0
1005 #define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86
1006 u8 qualified_module_count;
1007 u8 rsvd2[7]; /* Bytes 47:41 reserved */
1008 #define ICE_AQC_QUAL_MOD_COUNT_MAX 16
1015 } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX];
1018 /* Set PHY capabilities (direct 0x0601)
1019 * NOTE: This command must be followed by setup link and restart auto-neg
1021 struct ice_aqc_set_phy_cfg {
1028 /* Set PHY config command data structure */
1029 struct ice_aqc_set_phy_cfg_data {
1030 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1031 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1033 #define ICE_AQ_PHY_ENA_VALID_MASK ICE_M(0xef, 0)
1034 #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0)
1035 #define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1)
1036 #define ICE_AQ_PHY_ENA_LOW_POWER BIT(2)
1037 #define ICE_AQ_PHY_ENA_LINK BIT(3)
1038 #define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5)
1039 #define ICE_AQ_PHY_ENA_LESM BIT(6)
1040 #define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7)
1041 u8 low_power_ctrl_an;
1042 __le16 eee_cap; /* Value from ice_aqc_get_phy_caps */
1044 u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */
1045 u8 module_compliance_enforcement;
1048 /* Set MAC Config command data structure (direct 0x0603) */
1049 struct ice_aqc_set_mac_cfg {
1050 __le16 max_frame_size;
1052 #define ICE_AQ_SET_MAC_PACE_S 3
1053 #define ICE_AQ_SET_MAC_PACE_M (0xF << ICE_AQ_SET_MAC_PACE_S)
1054 #define ICE_AQ_SET_MAC_PACE_TYPE_M BIT(7)
1055 #define ICE_AQ_SET_MAC_PACE_TYPE_RATE 0
1056 #define ICE_AQ_SET_MAC_PACE_TYPE_FIXED ICE_AQ_SET_MAC_PACE_TYPE_M
1058 __le16 tx_tmr_value;
1059 __le16 fc_refresh_threshold;
1061 #define ICE_AQ_SET_MAC_AUTO_DROP_MASK BIT(0)
1062 #define ICE_AQ_SET_MAC_AUTO_DROP_NONE 0
1063 #define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS BIT(0)
1067 /* Restart AN command data structure (direct 0x0605)
1068 * Also used for response, with only the lport_num field present.
1070 struct ice_aqc_restart_an {
1074 #define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1)
1075 #define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2)
1079 /* Get link status (indirect 0x0607), also used for Link Status Event */
1080 struct ice_aqc_get_link_status {
1084 #define ICE_AQ_LSE_M 0x3
1085 #define ICE_AQ_LSE_NOP 0x0
1086 #define ICE_AQ_LSE_DIS 0x2
1087 #define ICE_AQ_LSE_ENA 0x3
1088 /* only response uses this flag */
1089 #define ICE_AQ_LSE_IS_ENABLED 0x1
1095 /* Get link status response data structure, also used for Link Status Event */
1096 struct ice_aqc_get_link_status_data {
1097 u8 topo_media_conflict;
1098 #define ICE_AQ_LINK_TOPO_CONFLICT BIT(0)
1099 #define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1)
1100 #define ICE_AQ_LINK_TOPO_CORRUPT BIT(2)
1101 #define ICE_AQ_LINK_TOPO_UNREACH_PRT BIT(4)
1102 #define ICE_AQ_LINK_TOPO_UNDRUTIL_PRT BIT(5)
1103 #define ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA BIT(6)
1104 #define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA BIT(7)
1107 #define ICE_AQ_LINK_UP BIT(0) /* Link Status */
1108 #define ICE_AQ_LINK_FAULT BIT(1)
1109 #define ICE_AQ_LINK_FAULT_TX BIT(2)
1110 #define ICE_AQ_LINK_FAULT_RX BIT(3)
1111 #define ICE_AQ_LINK_FAULT_REMOTE BIT(4)
1112 #define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */
1113 #define ICE_AQ_MEDIA_AVAILABLE BIT(6)
1114 #define ICE_AQ_SIGNAL_DETECT BIT(7)
1116 #define ICE_AQ_AN_COMPLETED BIT(0)
1117 #define ICE_AQ_LP_AN_ABILITY BIT(1)
1118 #define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */
1119 #define ICE_AQ_FEC_EN BIT(3)
1120 #define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */
1121 #define ICE_AQ_LINK_PAUSE_TX BIT(5)
1122 #define ICE_AQ_LINK_PAUSE_RX BIT(6)
1123 #define ICE_AQ_QUALIFIED_MODULE BIT(7)
1125 #define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0)
1126 #define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */
1127 /* Port Tx Suspended */
1128 #define ICE_AQ_LINK_TX_S 2
1129 #define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S)
1130 #define ICE_AQ_LINK_TX_ACTIVE 0
1131 #define ICE_AQ_LINK_TX_DRAINED 1
1132 #define ICE_AQ_LINK_TX_FLUSHED 3
1134 __le16 max_frame_size;
1136 #define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0)
1137 #define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1)
1138 #define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2)
1139 #define ICE_AQ_FEC_MASK ICE_M(0x7, 0)
1141 #define ICE_AQ_CFG_PACING_S 3
1142 #define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S)
1143 #define ICE_AQ_CFG_PACING_TYPE_M BIT(7)
1144 #define ICE_AQ_CFG_PACING_TYPE_AVG 0
1145 #define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M
1146 /* External Device Power Ability */
1148 #define ICE_AQ_PWR_CLASS_M 0x3
1149 #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0
1150 #define ICE_AQ_LINK_PWR_BASET_HIGH 1
1151 #define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0
1152 #define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1
1153 #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2
1154 #define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3
1156 #define ICE_AQ_LINK_SPEED_M 0x7FF
1157 #define ICE_AQ_LINK_SPEED_10MB BIT(0)
1158 #define ICE_AQ_LINK_SPEED_100MB BIT(1)
1159 #define ICE_AQ_LINK_SPEED_1000MB BIT(2)
1160 #define ICE_AQ_LINK_SPEED_2500MB BIT(3)
1161 #define ICE_AQ_LINK_SPEED_5GB BIT(4)
1162 #define ICE_AQ_LINK_SPEED_10GB BIT(5)
1163 #define ICE_AQ_LINK_SPEED_20GB BIT(6)
1164 #define ICE_AQ_LINK_SPEED_25GB BIT(7)
1165 #define ICE_AQ_LINK_SPEED_40GB BIT(8)
1166 #define ICE_AQ_LINK_SPEED_50GB BIT(9)
1167 #define ICE_AQ_LINK_SPEED_100GB BIT(10)
1168 #define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15)
1169 __le32 reserved3; /* Aligns next field to 8-byte boundary */
1170 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1171 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1174 /* Set event mask command (direct 0x0613) */
1175 struct ice_aqc_set_event_mask {
1179 #define ICE_AQ_LINK_EVENT_UPDOWN BIT(1)
1180 #define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2)
1181 #define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3)
1182 #define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4)
1183 #define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5)
1184 #define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6)
1185 #define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7)
1186 #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8)
1187 #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9)
1191 /* Set MAC Loopback command (direct 0x0620) */
1192 struct ice_aqc_set_mac_lb {
1194 #define ICE_AQ_MAC_LB_EN BIT(0)
1195 #define ICE_AQ_MAC_LB_OSC_CLK BIT(1)
1199 struct ice_aqc_link_topo_addr {
1202 #define ICE_AQC_LINK_TOPO_PORT_NUM_VALID BIT(0)
1204 #define ICE_AQC_LINK_TOPO_NODE_TYPE_S 0
1205 #define ICE_AQC_LINK_TOPO_NODE_TYPE_M (0xF << ICE_AQC_LINK_TOPO_NODE_TYPE_S)
1206 #define ICE_AQC_LINK_TOPO_NODE_TYPE_PHY 0
1207 #define ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL 1
1208 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MUX_CTRL 2
1209 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED_CTRL 3
1210 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED 4
1211 #define ICE_AQC_LINK_TOPO_NODE_TYPE_THERMAL 5
1212 #define ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE 6
1213 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MEZZ 7
1214 #define ICE_AQC_LINK_TOPO_NODE_TYPE_ID_EEPROM 8
1215 #define ICE_AQC_LINK_TOPO_NODE_CTX_S 4
1216 #define ICE_AQC_LINK_TOPO_NODE_CTX_M \
1217 (0xF << ICE_AQC_LINK_TOPO_NODE_CTX_S)
1218 #define ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL 0
1219 #define ICE_AQC_LINK_TOPO_NODE_CTX_BOARD 1
1220 #define ICE_AQC_LINK_TOPO_NODE_CTX_PORT 2
1221 #define ICE_AQC_LINK_TOPO_NODE_CTX_NODE 3
1222 #define ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED 4
1223 #define ICE_AQC_LINK_TOPO_NODE_CTX_OVERRIDE 5
1226 #define ICE_AQC_LINK_TOPO_HANDLE_S 0
1227 #define ICE_AQC_LINK_TOPO_HANDLE_M (0x3FF << ICE_AQC_LINK_TOPO_HANDLE_S)
1228 /* Used to decode the handle field */
1229 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_M BIT(9)
1230 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_LOM BIT(9)
1231 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ 0
1232 #define ICE_AQC_LINK_TOPO_HANDLE_NODE_S 0
1233 /* In case of a Mezzanine type */
1234 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_NODE_M \
1235 (0x3F << ICE_AQC_LINK_TOPO_HANDLE_NODE_S)
1236 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S 6
1237 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_M (0x7 << ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S)
1238 /* In case of a LOM type */
1239 #define ICE_AQC_LINK_TOPO_HANDLE_LOM_NODE_M \
1240 (0x1FF << ICE_AQC_LINK_TOPO_HANDLE_NODE_S)
1243 /* Get Link Topology Handle (direct, 0x06E0) */
1244 struct ice_aqc_get_link_topo {
1245 struct ice_aqc_link_topo_addr addr;
1250 /* Set Port Identification LED (direct, 0x06E9) */
1251 struct ice_aqc_set_port_id_led {
1255 #define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0)
1256 #define ICE_AQC_PORT_IDENT_LED_ORIG 0
1260 /* Read/Write SFF EEPROM command (indirect 0x06EE) */
1261 struct ice_aqc_sff_eeprom {
1264 #define ICE_AQC_SFF_PORT_NUM_VALID BIT(0)
1265 __le16 i2c_bus_addr;
1266 #define ICE_AQC_SFF_I2CBUS_7BIT_M 0x7F
1267 #define ICE_AQC_SFF_I2CBUS_10BIT_M 0x3FF
1268 #define ICE_AQC_SFF_I2CBUS_TYPE_M BIT(10)
1269 #define ICE_AQC_SFF_I2CBUS_TYPE_7BIT 0
1270 #define ICE_AQC_SFF_I2CBUS_TYPE_10BIT ICE_AQC_SFF_I2CBUS_TYPE_M
1271 #define ICE_AQC_SFF_SET_EEPROM_PAGE_S 11
1272 #define ICE_AQC_SFF_SET_EEPROM_PAGE_M (0x3 << ICE_AQC_SFF_SET_EEPROM_PAGE_S)
1273 #define ICE_AQC_SFF_NO_PAGE_CHANGE 0
1274 #define ICE_AQC_SFF_SET_23_ON_MISMATCH 1
1275 #define ICE_AQC_SFF_SET_22_ON_MISMATCH 2
1276 #define ICE_AQC_SFF_IS_WRITE BIT(15)
1277 __le16 i2c_mem_addr;
1279 #define ICE_AQC_SFF_EEPROM_BANK_S 0
1280 #define ICE_AQC_SFF_EEPROM_BANK_M (0xFF << ICE_AQC_SFF_EEPROM_BANK_S)
1281 #define ICE_AQC_SFF_EEPROM_PAGE_S 8
1282 #define ICE_AQC_SFF_EEPROM_PAGE_M (0xFF << ICE_AQC_SFF_EEPROM_PAGE_S)
1287 /* NVM Read command (indirect 0x0701)
1288 * NVM Erase commands (direct 0x0702)
1289 * NVM Update commands (indirect 0x0703)
1291 struct ice_aqc_nvm {
1292 #define ICE_AQC_NVM_MAX_OFFSET 0xFFFFFF
1296 #define ICE_AQC_NVM_LAST_CMD BIT(0)
1297 #define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Update reply */
1298 #define ICE_AQC_NVM_PRESERVATION_S 1
1299 #define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S)
1300 #define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S)
1301 #define ICE_AQC_NVM_PRESERVE_ALL BIT(1)
1302 #define ICE_AQC_NVM_FACTORY_DEFAULT (2 << ICE_AQC_NVM_PRESERVATION_S)
1303 #define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S)
1304 #define ICE_AQC_NVM_ACTIV_SEL_NVM BIT(3) /* Write Activate/SR Dump only */
1305 #define ICE_AQC_NVM_ACTIV_SEL_OROM BIT(4)
1306 #define ICE_AQC_NVM_ACTIV_SEL_NETLIST BIT(5)
1307 #define ICE_AQC_NVM_SPECIAL_UPDATE BIT(6)
1308 #define ICE_AQC_NVM_REVERT_LAST_ACTIV BIT(6) /* Write Activate only */
1309 #define ICE_AQC_NVM_ACTIV_SEL_MASK ICE_M(0x7, 3)
1310 #define ICE_AQC_NVM_FLASH_ONLY BIT(7)
1311 __le16 module_typeid;
1313 #define ICE_AQC_NVM_ERASE_LEN 0xFFFF
1318 #define ICE_AQC_NVM_START_POINT 0
1320 /* NVM Checksum Command (direct, 0x0706) */
1321 struct ice_aqc_nvm_checksum {
1323 #define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0)
1324 #define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1)
1326 __le16 checksum; /* Used only by response */
1327 #define ICE_AQC_NVM_CHECKSUM_CORRECT 0xBABA
1331 /* The result of netlist NVM read comes in a TLV format. The actual data
1332 * (netlist header) starts from word offset 1 (byte 2). The FW strips
1333 * out the type field from the TLV header so all the netlist fields
1334 * should adjust their offset value by 1 word (2 bytes) in order to map
1335 * their correct location.
1337 #define ICE_AQC_NVM_LINK_TOPO_NETLIST_MOD_ID 0x11B
1338 #define ICE_AQC_NVM_LINK_TOPO_NETLIST_LEN_OFFSET 1
1339 #define ICE_AQC_NVM_LINK_TOPO_NETLIST_LEN 2 /* In bytes */
1340 #define ICE_AQC_NVM_NETLIST_NODE_COUNT_OFFSET 2
1341 #define ICE_AQC_NVM_NETLIST_NODE_COUNT_LEN 2 /* In bytes */
1342 #define ICE_AQC_NVM_NETLIST_NODE_COUNT_M ICE_M(0x3FF, 0)
1343 #define ICE_AQC_NVM_NETLIST_ID_BLK_START_OFFSET 5
1344 #define ICE_AQC_NVM_NETLIST_ID_BLK_LEN 0x30 /* In words */
1346 /* netlist ID block field offsets (word offsets) */
1347 #define ICE_AQC_NVM_NETLIST_ID_BLK_MAJOR_VER_LOW 2
1348 #define ICE_AQC_NVM_NETLIST_ID_BLK_MAJOR_VER_HIGH 3
1349 #define ICE_AQC_NVM_NETLIST_ID_BLK_MINOR_VER_LOW 4
1350 #define ICE_AQC_NVM_NETLIST_ID_BLK_MINOR_VER_HIGH 5
1351 #define ICE_AQC_NVM_NETLIST_ID_BLK_TYPE_LOW 6
1352 #define ICE_AQC_NVM_NETLIST_ID_BLK_TYPE_HIGH 7
1353 #define ICE_AQC_NVM_NETLIST_ID_BLK_REV_LOW 8
1354 #define ICE_AQC_NVM_NETLIST_ID_BLK_REV_HIGH 9
1355 #define ICE_AQC_NVM_NETLIST_ID_BLK_SHA_HASH 0xA
1356 #define ICE_AQC_NVM_NETLIST_ID_BLK_CUST_VER 0x2F
1358 /* Used for NVM Set Package Data command - 0x070A */
1359 struct ice_aqc_nvm_pkg_data {
1362 #define ICE_AQC_NVM_PKG_DELETE BIT(0) /* used for command call */
1363 #define ICE_AQC_NVM_PKG_SKIPPED BIT(0) /* used for command response */
1370 /* Used for Pass Component Table command - 0x070B */
1371 struct ice_aqc_nvm_pass_comp_tbl {
1372 u8 component_response; /* Response only */
1373 #define ICE_AQ_NVM_PASS_COMP_CAN_BE_UPDATED 0x0
1374 #define ICE_AQ_NVM_PASS_COMP_CAN_MAY_BE_UPDATEABLE 0x1
1375 #define ICE_AQ_NVM_PASS_COMP_CAN_NOT_BE_UPDATED 0x2
1376 u8 component_response_code; /* Response only */
1377 #define ICE_AQ_NVM_PASS_COMP_CAN_BE_UPDATED_CODE 0x0
1378 #define ICE_AQ_NVM_PASS_COMP_STAMP_IDENTICAL_CODE 0x1
1379 #define ICE_AQ_NVM_PASS_COMP_STAMP_LOWER 0x2
1380 #define ICE_AQ_NVM_PASS_COMP_INVALID_STAMP_CODE 0x3
1381 #define ICE_AQ_NVM_PASS_COMP_CONFLICT_CODE 0x4
1382 #define ICE_AQ_NVM_PASS_COMP_PRE_REQ_NOT_MET_CODE 0x5
1383 #define ICE_AQ_NVM_PASS_COMP_NOT_SUPPORTED_CODE 0x6
1384 #define ICE_AQ_NVM_PASS_COMP_CANNOT_DOWNGRADE_CODE 0x7
1385 #define ICE_AQ_NVM_PASS_COMP_INCOMPLETE_IMAGE_CODE 0x8
1386 #define ICE_AQ_NVM_PASS_COMP_VER_STR_IDENTICAL_CODE 0xA
1387 #define ICE_AQ_NVM_PASS_COMP_VER_STR_LOWER_CODE 0xB
1390 #define ICE_AQ_NVM_PASS_COMP_TBL_START 0x1
1391 #define ICE_AQ_NVM_PASS_COMP_TBL_MIDDLE 0x2
1392 #define ICE_AQ_NVM_PASS_COMP_TBL_END 0x4
1393 #define ICE_AQ_NVM_PASS_COMP_TBL_START_AND_END 0x5
1399 struct ice_aqc_nvm_comp_tbl {
1401 #define NVM_COMP_CLASS_ALL_FW 0x000A
1404 #define NVM_COMP_ID_OROM 0x5
1405 #define NVM_COMP_ID_NVM 0x6
1406 #define NVM_COMP_ID_NETLIST 0x8
1409 #define FWU_COMP_CLASS_IDX_NOT_USE 0x0
1411 __le32 comp_cmp_stamp;
1413 #define NVM_CVS_TYPE_ASCII 0x1
1416 u8 cvs[]; /* Component Version String */
1420 * Send to PF command (indirect 0x0801) ID is only used by PF
1422 * Send to VF command (indirect 0x0802) ID is only used by PF
1425 struct ice_aqc_pf_vf_msg {
1432 /* Get LLDP MIB (indirect 0x0A00)
1433 * Note: This is also used by the LLDP MIB Change Event (0x0A01)
1434 * as the format is the same.
1436 struct ice_aqc_lldp_get_mib {
1438 #define ICE_AQ_LLDP_MIB_TYPE_S 0
1439 #define ICE_AQ_LLDP_MIB_TYPE_M (0x3 << ICE_AQ_LLDP_MIB_TYPE_S)
1440 #define ICE_AQ_LLDP_MIB_LOCAL 0
1441 #define ICE_AQ_LLDP_MIB_REMOTE 1
1442 #define ICE_AQ_LLDP_MIB_LOCAL_AND_REMOTE 2
1443 #define ICE_AQ_LLDP_BRID_TYPE_S 2
1444 #define ICE_AQ_LLDP_BRID_TYPE_M (0x3 << ICE_AQ_LLDP_BRID_TYPE_S)
1445 #define ICE_AQ_LLDP_BRID_TYPE_NEAREST_BRID 0
1446 #define ICE_AQ_LLDP_BRID_TYPE_NON_TPMR 1
1447 /* Tx pause flags in the 0xA01 event use ICE_AQ_LLDP_TX_* */
1448 #define ICE_AQ_LLDP_TX_S 0x4
1449 #define ICE_AQ_LLDP_TX_M (0x03 << ICE_AQ_LLDP_TX_S)
1450 #define ICE_AQ_LLDP_TX_ACTIVE 0
1451 #define ICE_AQ_LLDP_TX_SUSPENDED 1
1452 #define ICE_AQ_LLDP_TX_FLUSHED 3
1453 /* The following bytes are reserved for the Get LLDP MIB command (0x0A00)
1454 * and in the LLDP MIB Change Event (0x0A01). They are valid for the
1455 * Get LLDP MIB (0x0A00) response only.
1465 /* Configure LLDP MIB Change Event (direct 0x0A01) */
1466 /* For MIB Change Event use ice_aqc_lldp_get_mib structure above */
1467 struct ice_aqc_lldp_set_mib_change {
1469 #define ICE_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
1470 #define ICE_AQ_LLDP_MIB_UPDATE_DIS 0x1
1474 /* Stop LLDP (direct 0x0A05) */
1475 struct ice_aqc_lldp_stop {
1477 #define ICE_AQ_LLDP_AGENT_STATE_MASK BIT(0)
1478 #define ICE_AQ_LLDP_AGENT_STOP 0x0
1479 #define ICE_AQ_LLDP_AGENT_SHUTDOWN ICE_AQ_LLDP_AGENT_STATE_MASK
1480 #define ICE_AQ_LLDP_AGENT_PERSIST_DIS BIT(1)
1484 /* Start LLDP (direct 0x0A06) */
1485 struct ice_aqc_lldp_start {
1487 #define ICE_AQ_LLDP_AGENT_START BIT(0)
1488 #define ICE_AQ_LLDP_AGENT_PERSIST_ENA BIT(1)
1492 /* Get CEE DCBX Oper Config (0x0A07)
1493 * The command uses the generic descriptor struct and
1494 * returns the struct below as an indirect response.
1496 struct ice_aqc_get_cee_dcb_cfg_resp {
1501 __le16 oper_app_prio;
1502 #define ICE_AQC_CEE_APP_FCOE_S 0
1503 #define ICE_AQC_CEE_APP_FCOE_M (0x7 << ICE_AQC_CEE_APP_FCOE_S)
1504 #define ICE_AQC_CEE_APP_ISCSI_S 3
1505 #define ICE_AQC_CEE_APP_ISCSI_M (0x7 << ICE_AQC_CEE_APP_ISCSI_S)
1506 #define ICE_AQC_CEE_APP_FIP_S 8
1507 #define ICE_AQC_CEE_APP_FIP_M (0x7 << ICE_AQC_CEE_APP_FIP_S)
1509 #define ICE_AQC_CEE_PG_STATUS_S 0
1510 #define ICE_AQC_CEE_PG_STATUS_M (0x7 << ICE_AQC_CEE_PG_STATUS_S)
1511 #define ICE_AQC_CEE_PFC_STATUS_S 3
1512 #define ICE_AQC_CEE_PFC_STATUS_M (0x7 << ICE_AQC_CEE_PFC_STATUS_S)
1513 #define ICE_AQC_CEE_FCOE_STATUS_S 8
1514 #define ICE_AQC_CEE_FCOE_STATUS_M (0x7 << ICE_AQC_CEE_FCOE_STATUS_S)
1515 #define ICE_AQC_CEE_ISCSI_STATUS_S 11
1516 #define ICE_AQC_CEE_ISCSI_STATUS_M (0x7 << ICE_AQC_CEE_ISCSI_STATUS_S)
1517 #define ICE_AQC_CEE_FIP_STATUS_S 16
1518 #define ICE_AQC_CEE_FIP_STATUS_M (0x7 << ICE_AQC_CEE_FIP_STATUS_S)
1522 /* Set Local LLDP MIB (indirect 0x0A08)
1523 * Used to replace the local MIB of a given LLDP agent. e.g. DCBX
1525 struct ice_aqc_lldp_set_local_mib {
1527 #define SET_LOCAL_MIB_TYPE_DCBX_M BIT(0)
1528 #define SET_LOCAL_MIB_TYPE_LOCAL_MIB 0
1529 #define SET_LOCAL_MIB_TYPE_CEE_M BIT(1)
1530 #define SET_LOCAL_MIB_TYPE_CEE_WILLING 0
1531 #define SET_LOCAL_MIB_TYPE_CEE_NON_WILLING SET_LOCAL_MIB_TYPE_CEE_M
1539 /* Stop/Start LLDP Agent (direct 0x0A09)
1540 * Used for stopping/starting specific LLDP agent. e.g. DCBX.
1541 * The same structure is used for the response, with the command field
1542 * being used as the status field.
1544 struct ice_aqc_lldp_stop_start_specific_agent {
1546 #define ICE_AQC_START_STOP_AGENT_M BIT(0)
1547 #define ICE_AQC_START_STOP_AGENT_STOP_DCBX 0
1548 #define ICE_AQC_START_STOP_AGENT_START_DCBX ICE_AQC_START_STOP_AGENT_M
1552 /* Get/Set RSS key (indirect 0x0B04/0x0B02) */
1553 struct ice_aqc_get_set_rss_key {
1554 #define ICE_AQC_GSET_RSS_KEY_VSI_VALID BIT(15)
1555 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_S 0
1556 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_KEY_VSI_ID_S)
1563 #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28
1564 #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC
1565 #define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE \
1566 (ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE + \
1567 ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE)
1569 struct ice_aqc_get_set_rss_keys {
1570 u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE];
1571 u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE];
1574 /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */
1575 struct ice_aqc_get_set_rss_lut {
1576 #define ICE_AQC_GSET_RSS_LUT_VSI_VALID BIT(15)
1577 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_S 0
1578 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_M (0x1FF << ICE_AQC_GSET_RSS_LUT_VSI_ID_S)
1580 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S 0
1581 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M \
1582 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S)
1584 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI 0
1585 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF 1
1586 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL 2
1588 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S 2
1589 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M \
1590 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S)
1592 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 128
1593 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG 0
1594 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 512
1595 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG 1
1596 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K 2048
1597 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG 2
1599 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S 4
1600 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M \
1601 (0xF << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S)
1609 /* Add Tx LAN Queues (indirect 0x0C30) */
1610 struct ice_aqc_add_txqs {
1618 /* This is the descriptor of each queue entry for the Add Tx LAN Queues
1619 * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp.
1621 struct ice_aqc_add_txqs_perq {
1627 struct ice_aqc_txsched_elem info;
1630 /* The format of the command buffer for Add Tx LAN Queues (0x0C30)
1631 * is an array of the following structs. Please note that the length of
1632 * each struct ice_aqc_add_tx_qgrp is variable due
1633 * to the variable number of queues in each group!
1635 struct ice_aqc_add_tx_qgrp {
1639 struct ice_aqc_add_txqs_perq txqs[];
1642 /* Disable Tx LAN Queues (indirect 0x0C31) */
1643 struct ice_aqc_dis_txqs {
1645 #define ICE_AQC_Q_DIS_CMD_S 0
1646 #define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S)
1647 #define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S)
1648 #define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S)
1649 #define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S)
1650 #define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S)
1651 #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2)
1652 #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3)
1654 __le16 vmvf_and_timeout;
1655 #define ICE_AQC_Q_DIS_VMVF_NUM_S 0
1656 #define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S)
1657 #define ICE_AQC_Q_DIS_TIMEOUT_S 10
1658 #define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S)
1659 __le32 blocked_cgds;
1664 /* The buffer for Disable Tx LAN Queues (indirect 0x0C31)
1665 * contains the following structures, arrayed one after the
1667 * Note: Since the q_id is 16 bits wide, if the
1668 * number of queues is even, then 2 bytes of alignment MUST be
1669 * added before the start of the next group, to allow correct
1670 * alignment of the parent_teid field.
1672 struct ice_aqc_dis_txq_item {
1676 /* The length of the q_id array varies according to num_qs */
1677 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15
1678 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \
1679 (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)
1680 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \
1681 (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)
1685 /* Configure Firmware Logging Command (indirect 0xFF09)
1686 * Logging Information Read Response (indirect 0xFF10)
1687 * Note: The 0xFF10 command has no input parameters.
1689 struct ice_aqc_fw_logging {
1691 #define ICE_AQC_FW_LOG_AQ_EN BIT(0)
1692 #define ICE_AQC_FW_LOG_UART_EN BIT(1)
1694 u8 log_ctrl_valid; /* Not used by 0xFF10 Response */
1695 #define ICE_AQC_FW_LOG_AQ_VALID BIT(0)
1696 #define ICE_AQC_FW_LOG_UART_VALID BIT(1)
1702 enum ice_aqc_fw_logging_mod {
1703 ICE_AQC_FW_LOG_ID_GENERAL = 0,
1704 ICE_AQC_FW_LOG_ID_CTRL,
1705 ICE_AQC_FW_LOG_ID_LINK,
1706 ICE_AQC_FW_LOG_ID_LINK_TOPO,
1707 ICE_AQC_FW_LOG_ID_DNL,
1708 ICE_AQC_FW_LOG_ID_I2C,
1709 ICE_AQC_FW_LOG_ID_SDP,
1710 ICE_AQC_FW_LOG_ID_MDIO,
1711 ICE_AQC_FW_LOG_ID_ADMINQ,
1712 ICE_AQC_FW_LOG_ID_HDMA,
1713 ICE_AQC_FW_LOG_ID_LLDP,
1714 ICE_AQC_FW_LOG_ID_DCBX,
1715 ICE_AQC_FW_LOG_ID_DCB,
1716 ICE_AQC_FW_LOG_ID_NETPROXY,
1717 ICE_AQC_FW_LOG_ID_NVM,
1718 ICE_AQC_FW_LOG_ID_AUTH,
1719 ICE_AQC_FW_LOG_ID_VPD,
1720 ICE_AQC_FW_LOG_ID_IOSF,
1721 ICE_AQC_FW_LOG_ID_PARSER,
1722 ICE_AQC_FW_LOG_ID_SW,
1723 ICE_AQC_FW_LOG_ID_SCHEDULER,
1724 ICE_AQC_FW_LOG_ID_TXQ,
1725 ICE_AQC_FW_LOG_ID_RSVD,
1726 ICE_AQC_FW_LOG_ID_POST,
1727 ICE_AQC_FW_LOG_ID_WATCHDOG,
1728 ICE_AQC_FW_LOG_ID_TASK_DISPATCH,
1729 ICE_AQC_FW_LOG_ID_MNG,
1730 ICE_AQC_FW_LOG_ID_MAX,
1733 /* Defines for both above FW logging command/response buffers */
1734 #define ICE_AQC_FW_LOG_ID_S 0
1735 #define ICE_AQC_FW_LOG_ID_M (0xFFF << ICE_AQC_FW_LOG_ID_S)
1737 #define ICE_AQC_FW_LOG_CONF_SUCCESS 0 /* Used by response */
1738 #define ICE_AQC_FW_LOG_CONF_BAD_INDX BIT(12) /* Used by response */
1740 #define ICE_AQC_FW_LOG_EN_S 12
1741 #define ICE_AQC_FW_LOG_EN_M (0xF << ICE_AQC_FW_LOG_EN_S)
1742 #define ICE_AQC_FW_LOG_INFO_EN BIT(12) /* Used by command */
1743 #define ICE_AQC_FW_LOG_INIT_EN BIT(13) /* Used by command */
1744 #define ICE_AQC_FW_LOG_FLOW_EN BIT(14) /* Used by command */
1745 #define ICE_AQC_FW_LOG_ERR_EN BIT(15) /* Used by command */
1747 /* Get/Clear FW Log (indirect 0xFF11) */
1748 struct ice_aqc_get_clear_fw_log {
1750 #define ICE_AQC_FW_LOG_CLEAR BIT(0)
1751 #define ICE_AQC_FW_LOG_MORE_DATA_AVAIL BIT(1)
1757 /* Download Package (indirect 0x0C40) */
1758 /* Also used for Update Package (indirect 0x0C42) */
1759 struct ice_aqc_download_pkg {
1761 #define ICE_AQC_DOWNLOAD_PKG_LAST_BUF 0x01
1768 struct ice_aqc_download_pkg_resp {
1769 __le32 error_offset;
1775 /* Get Package Info List (indirect 0x0C43) */
1776 struct ice_aqc_get_pkg_info_list {
1783 /* Version format for packages */
1784 struct ice_pkg_ver {
1791 #define ICE_PKG_NAME_SIZE 32
1792 #define ICE_SEG_NAME_SIZE 28
1794 struct ice_aqc_get_pkg_info {
1795 struct ice_pkg_ver ver;
1796 char name[ICE_SEG_NAME_SIZE];
1800 u8 is_active_at_boot;
1804 /* Get Package Info List response buffer format (0x0C43) */
1805 struct ice_aqc_get_pkg_info_resp {
1807 struct ice_aqc_get_pkg_info pkg_info[];
1810 /* Lan Queue Overflow Event (direct, 0x1001) */
1811 struct ice_aqc_event_lan_overflow {
1812 __le32 prtdcb_ruptq;
1818 * struct ice_aq_desc - Admin Queue (AQ) descriptor
1819 * @flags: ICE_AQ_FLAG_* flags
1820 * @opcode: AQ command opcode
1821 * @datalen: length in bytes of indirect/external data buffer
1822 * @retval: return value from firmware
1823 * @cookie_h: opaque data high-half
1824 * @cookie_l: opaque data low-half
1825 * @params: command-specific parameters
1827 * Descriptor format for commands the driver posts on the Admin Transmit Queue
1828 * (ATQ). The firmware writes back onto the command descriptor and returns
1829 * the result of the command. Asynchronous events that are not an immediate
1830 * result of the command are written to the Admin Receive Queue (ARQ) using
1831 * the same descriptor format. Descriptors are in little-endian notation with
1834 struct ice_aq_desc {
1843 struct ice_aqc_generic generic;
1844 struct ice_aqc_get_ver get_ver;
1845 struct ice_aqc_driver_ver driver_ver;
1846 struct ice_aqc_q_shutdown q_shutdown;
1847 struct ice_aqc_req_res res_owner;
1848 struct ice_aqc_manage_mac_read mac_read;
1849 struct ice_aqc_manage_mac_write mac_write;
1850 struct ice_aqc_clear_pxe clear_pxe;
1851 struct ice_aqc_list_caps get_cap;
1852 struct ice_aqc_get_phy_caps get_phy;
1853 struct ice_aqc_set_phy_cfg set_phy;
1854 struct ice_aqc_restart_an restart_an;
1855 struct ice_aqc_sff_eeprom read_write_sff_param;
1856 struct ice_aqc_set_port_id_led set_port_id_led;
1857 struct ice_aqc_get_sw_cfg get_sw_conf;
1858 struct ice_aqc_sw_rules sw_rules;
1859 struct ice_aqc_get_topo get_topo;
1860 struct ice_aqc_sched_elem_cmd sched_elem_cmd;
1861 struct ice_aqc_query_txsched_res query_sched_res;
1862 struct ice_aqc_query_port_ets port_ets;
1863 struct ice_aqc_rl_profile rl_profile;
1864 struct ice_aqc_nvm nvm;
1865 struct ice_aqc_nvm_checksum nvm_checksum;
1866 struct ice_aqc_nvm_pkg_data pkg_data;
1867 struct ice_aqc_nvm_pass_comp_tbl pass_comp_tbl;
1868 struct ice_aqc_pf_vf_msg virt;
1869 struct ice_aqc_lldp_get_mib lldp_get_mib;
1870 struct ice_aqc_lldp_set_mib_change lldp_set_event;
1871 struct ice_aqc_lldp_stop lldp_stop;
1872 struct ice_aqc_lldp_start lldp_start;
1873 struct ice_aqc_lldp_set_local_mib lldp_set_mib;
1874 struct ice_aqc_lldp_stop_start_specific_agent lldp_agent_ctrl;
1875 struct ice_aqc_get_set_rss_lut get_set_rss_lut;
1876 struct ice_aqc_get_set_rss_key get_set_rss_key;
1877 struct ice_aqc_add_txqs add_txqs;
1878 struct ice_aqc_dis_txqs dis_txqs;
1879 struct ice_aqc_add_get_update_free_vsi vsi_cmd;
1880 struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res;
1881 struct ice_aqc_fw_logging fw_logging;
1882 struct ice_aqc_get_clear_fw_log get_clear_fw_log;
1883 struct ice_aqc_download_pkg download_pkg;
1884 struct ice_aqc_set_mac_lb set_mac_lb;
1885 struct ice_aqc_alloc_free_res_cmd sw_res_ctrl;
1886 struct ice_aqc_set_mac_cfg set_mac_cfg;
1887 struct ice_aqc_set_event_mask set_event_mask;
1888 struct ice_aqc_get_link_status get_link_status;
1889 struct ice_aqc_event_lan_overflow lan_overflow;
1890 struct ice_aqc_get_link_topo get_link_topo;
1894 /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */
1895 #define ICE_AQ_LG_BUF 512
1897 #define ICE_AQ_FLAG_ERR_S 2
1898 #define ICE_AQ_FLAG_LB_S 9
1899 #define ICE_AQ_FLAG_RD_S 10
1900 #define ICE_AQ_FLAG_BUF_S 12
1901 #define ICE_AQ_FLAG_SI_S 13
1903 #define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */
1904 #define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */
1905 #define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */
1906 #define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */
1907 #define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */
1911 ICE_AQ_RC_OK = 0, /* Success */
1912 ICE_AQ_RC_EPERM = 1, /* Operation not permitted */
1913 ICE_AQ_RC_ENOENT = 2, /* No such element */
1914 ICE_AQ_RC_ENOMEM = 9, /* Out of memory */
1915 ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */
1916 ICE_AQ_RC_EEXIST = 13, /* Object already exists */
1917 ICE_AQ_RC_EINVAL = 14, /* Invalid argument */
1918 ICE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */
1919 ICE_AQ_RC_ENOSYS = 17, /* Function not implemented */
1920 ICE_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
1921 ICE_AQ_RC_ENOSEC = 24, /* Missing security manifest */
1922 ICE_AQ_RC_EBADSIG = 25, /* Bad RSA signature */
1923 ICE_AQ_RC_ESVN = 26, /* SVN number prohibits this package */
1924 ICE_AQ_RC_EBADMAN = 27, /* Manifest hash mismatch */
1925 ICE_AQ_RC_EBADBUF = 28, /* Buffer hash mismatches manifest */
1928 /* Admin Queue command opcodes */
1929 enum ice_adminq_opc {
1931 ice_aqc_opc_get_ver = 0x0001,
1932 ice_aqc_opc_driver_ver = 0x0002,
1933 ice_aqc_opc_q_shutdown = 0x0003,
1935 /* resource ownership */
1936 ice_aqc_opc_req_res = 0x0008,
1937 ice_aqc_opc_release_res = 0x0009,
1939 /* device/function capabilities */
1940 ice_aqc_opc_list_func_caps = 0x000A,
1941 ice_aqc_opc_list_dev_caps = 0x000B,
1943 /* manage MAC address */
1944 ice_aqc_opc_manage_mac_read = 0x0107,
1945 ice_aqc_opc_manage_mac_write = 0x0108,
1948 ice_aqc_opc_clear_pxe_mode = 0x0110,
1950 /* internal switch commands */
1951 ice_aqc_opc_get_sw_cfg = 0x0200,
1953 /* Alloc/Free/Get Resources */
1954 ice_aqc_opc_alloc_res = 0x0208,
1955 ice_aqc_opc_free_res = 0x0209,
1958 ice_aqc_opc_add_vsi = 0x0210,
1959 ice_aqc_opc_update_vsi = 0x0211,
1960 ice_aqc_opc_free_vsi = 0x0213,
1962 /* switch rules population commands */
1963 ice_aqc_opc_add_sw_rules = 0x02A0,
1964 ice_aqc_opc_update_sw_rules = 0x02A1,
1965 ice_aqc_opc_remove_sw_rules = 0x02A2,
1967 ice_aqc_opc_clear_pf_cfg = 0x02A4,
1969 /* transmit scheduler commands */
1970 ice_aqc_opc_get_dflt_topo = 0x0400,
1971 ice_aqc_opc_add_sched_elems = 0x0401,
1972 ice_aqc_opc_cfg_sched_elems = 0x0403,
1973 ice_aqc_opc_get_sched_elems = 0x0404,
1974 ice_aqc_opc_suspend_sched_elems = 0x0409,
1975 ice_aqc_opc_resume_sched_elems = 0x040A,
1976 ice_aqc_opc_query_port_ets = 0x040E,
1977 ice_aqc_opc_delete_sched_elems = 0x040F,
1978 ice_aqc_opc_add_rl_profiles = 0x0410,
1979 ice_aqc_opc_query_sched_res = 0x0412,
1980 ice_aqc_opc_remove_rl_profiles = 0x0415,
1983 ice_aqc_opc_get_phy_caps = 0x0600,
1984 ice_aqc_opc_set_phy_cfg = 0x0601,
1985 ice_aqc_opc_set_mac_cfg = 0x0603,
1986 ice_aqc_opc_restart_an = 0x0605,
1987 ice_aqc_opc_get_link_status = 0x0607,
1988 ice_aqc_opc_set_event_mask = 0x0613,
1989 ice_aqc_opc_set_mac_lb = 0x0620,
1990 ice_aqc_opc_get_link_topo = 0x06E0,
1991 ice_aqc_opc_set_port_id_led = 0x06E9,
1992 ice_aqc_opc_sff_eeprom = 0x06EE,
1995 ice_aqc_opc_nvm_read = 0x0701,
1996 ice_aqc_opc_nvm_erase = 0x0702,
1997 ice_aqc_opc_nvm_write = 0x0703,
1998 ice_aqc_opc_nvm_checksum = 0x0706,
1999 ice_aqc_opc_nvm_write_activate = 0x0707,
2000 ice_aqc_opc_nvm_update_empr = 0x0709,
2001 ice_aqc_opc_nvm_pkg_data = 0x070A,
2002 ice_aqc_opc_nvm_pass_component_tbl = 0x070B,
2004 /* PF/VF mailbox commands */
2005 ice_mbx_opc_send_msg_to_pf = 0x0801,
2006 ice_mbx_opc_send_msg_to_vf = 0x0802,
2008 ice_aqc_opc_lldp_get_mib = 0x0A00,
2009 ice_aqc_opc_lldp_set_mib_change = 0x0A01,
2010 ice_aqc_opc_lldp_stop = 0x0A05,
2011 ice_aqc_opc_lldp_start = 0x0A06,
2012 ice_aqc_opc_get_cee_dcb_cfg = 0x0A07,
2013 ice_aqc_opc_lldp_set_local_mib = 0x0A08,
2014 ice_aqc_opc_lldp_stop_start_specific_agent = 0x0A09,
2017 ice_aqc_opc_set_rss_key = 0x0B02,
2018 ice_aqc_opc_set_rss_lut = 0x0B03,
2019 ice_aqc_opc_get_rss_key = 0x0B04,
2020 ice_aqc_opc_get_rss_lut = 0x0B05,
2022 /* Tx queue handling commands/events */
2023 ice_aqc_opc_add_txqs = 0x0C30,
2024 ice_aqc_opc_dis_txqs = 0x0C31,
2026 /* package commands */
2027 ice_aqc_opc_download_pkg = 0x0C40,
2028 ice_aqc_opc_update_pkg = 0x0C42,
2029 ice_aqc_opc_get_pkg_info_list = 0x0C43,
2031 /* Standalone Commands/Events */
2032 ice_aqc_opc_event_lan_overflow = 0x1001,
2034 /* debug commands */
2035 ice_aqc_opc_fw_logging = 0xFF09,
2036 ice_aqc_opc_fw_logging_info = 0xFF10,
2039 #endif /* _ICE_ADMINQ_CMD_H_ */