1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018, Intel Corporation. */
7 #include <linux/types.h>
8 #include <linux/errno.h>
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/firmware.h>
12 #include <linux/netdevice.h>
13 #include <linux/compiler.h>
14 #include <linux/etherdevice.h>
15 #include <linux/skbuff.h>
16 #include <linux/cpumask.h>
17 #include <linux/rtnetlink.h>
18 #include <linux/if_vlan.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/pci.h>
21 #include <linux/workqueue.h>
22 #include <linux/wait.h>
23 #include <linux/aer.h>
24 #include <linux/interrupt.h>
25 #include <linux/ethtool.h>
26 #include <linux/timer.h>
27 #include <linux/delay.h>
28 #include <linux/bitmap.h>
29 #include <linux/log2.h>
31 #include <linux/sctp.h>
32 #include <linux/ipv6.h>
33 #include <linux/pkt_sched.h>
34 #include <linux/if_bridge.h>
35 #include <linux/ctype.h>
36 #include <linux/bpf.h>
37 #include <linux/avf/virtchnl.h>
38 #include <linux/cpu_rmap.h>
39 #include <linux/dim.h>
40 #include <net/devlink.h>
42 #include <net/xdp_sock.h>
43 #include <net/xdp_sock_drv.h>
44 #include <net/geneve.h>
46 #include <net/udp_tunnel.h>
47 #include <net/vxlan.h>
48 #if IS_ENABLED(CONFIG_DCB)
49 #include <scsi/iscsi_proto.h>
50 #endif /* CONFIG_DCB */
51 #include "ice_devids.h"
55 #include "ice_switch.h"
56 #include "ice_common.h"
57 #include "ice_sched.h"
58 #include "ice_idc_int.h"
59 #include "ice_virtchnl_pf.h"
60 #include "ice_sriov.h"
67 #define ICE_REQ_DESC_MULTIPLE 32
68 #define ICE_MIN_NUM_DESC 64
69 #define ICE_MAX_NUM_DESC 8160
70 #define ICE_DFLT_MIN_RX_DESC 512
71 #define ICE_DFLT_NUM_TX_DESC 256
72 #define ICE_DFLT_NUM_RX_DESC 2048
74 #define ICE_DFLT_TRAFFIC_CLASS BIT(0)
75 #define ICE_INT_NAME_STR_LEN (IFNAMSIZ + 16)
77 #define ICE_MBXSQ_LEN 64
78 #define ICE_MIN_LAN_TXRX_MSIX 1
79 #define ICE_MIN_LAN_OICR_MSIX 1
80 #define ICE_MIN_MSIX (ICE_MIN_LAN_TXRX_MSIX + ICE_MIN_LAN_OICR_MSIX)
81 #define ICE_FDIR_MSIX 2
82 #define ICE_RDMA_NUM_AEQ_MSIX 4
83 #define ICE_MIN_RDMA_MSIX 2
84 #define ICE_NO_VSI 0xffff
85 #define ICE_VSI_MAP_CONTIG 0
86 #define ICE_VSI_MAP_SCATTER 1
87 #define ICE_MAX_SCATTER_TXQS 16
88 #define ICE_MAX_SCATTER_RXQS 16
89 #define ICE_Q_WAIT_RETRY_LIMIT 10
90 #define ICE_Q_WAIT_MAX_RETRY (5 * ICE_Q_WAIT_RETRY_LIMIT)
91 #define ICE_MAX_LG_RSS_QS 256
92 #define ICE_RES_VALID_BIT 0x8000
93 #define ICE_RES_MISC_VEC_ID (ICE_RES_VALID_BIT - 1)
94 #define ICE_RES_RDMA_VEC_ID (ICE_RES_MISC_VEC_ID - 1)
95 /* All VF control VSIs share the same IRQ, so assign a unique ID for them */
96 #define ICE_RES_VF_CTRL_VEC_ID (ICE_RES_RDMA_VEC_ID - 1)
97 #define ICE_INVAL_Q_INDEX 0xffff
98 #define ICE_INVAL_VFID 256
100 #define ICE_MAX_RXQS_PER_TC 256 /* Used when setting VSI context per TC Rx queues */
101 #define ICE_MAX_RESET_WAIT 20
103 #define ICE_VSIQF_HKEY_ARRAY_SIZE ((VSIQF_HKEY_MAX_INDEX + 1) * 4)
105 #define ICE_DFLT_NETIF_M (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
107 #define ICE_MAX_MTU (ICE_AQ_SET_MAC_FRAME_SIZE_MAX - ICE_ETH_PKT_HDR_PAD)
109 #define ICE_UP_TABLE_TRANSLATE(val, i) \
110 (((val) << ICE_AQ_VSI_UP_TABLE_UP##i##_S) & \
111 ICE_AQ_VSI_UP_TABLE_UP##i##_M)
113 #define ICE_TX_DESC(R, i) (&(((struct ice_tx_desc *)((R)->desc))[i]))
114 #define ICE_RX_DESC(R, i) (&(((union ice_32b_rx_flex_desc *)((R)->desc))[i]))
115 #define ICE_TX_CTX_DESC(R, i) (&(((struct ice_tx_ctx_desc *)((R)->desc))[i]))
116 #define ICE_TX_FDIRDESC(R, i) (&(((struct ice_fltr_desc *)((R)->desc))[i]))
118 /* Macro for each VSI in a PF */
119 #define ice_for_each_vsi(pf, i) \
120 for ((i) = 0; (i) < (pf)->num_alloc_vsi; (i)++)
122 /* Macros for each Tx/Rx ring in a VSI */
123 #define ice_for_each_txq(vsi, i) \
124 for ((i) = 0; (i) < (vsi)->num_txq; (i)++)
126 #define ice_for_each_rxq(vsi, i) \
127 for ((i) = 0; (i) < (vsi)->num_rxq; (i)++)
129 /* Macros for each allocated Tx/Rx ring whether used or not in a VSI */
130 #define ice_for_each_alloc_txq(vsi, i) \
131 for ((i) = 0; (i) < (vsi)->alloc_txq; (i)++)
133 #define ice_for_each_alloc_rxq(vsi, i) \
134 for ((i) = 0; (i) < (vsi)->alloc_rxq; (i)++)
136 #define ice_for_each_q_vector(vsi, i) \
137 for ((i) = 0; (i) < (vsi)->num_q_vectors; (i)++)
139 #define ICE_UCAST_PROMISC_BITS (ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX | \
140 ICE_PROMISC_UCAST_RX | ICE_PROMISC_MCAST_RX)
142 #define ICE_UCAST_VLAN_PROMISC_BITS (ICE_PROMISC_UCAST_TX | \
143 ICE_PROMISC_MCAST_TX | \
144 ICE_PROMISC_UCAST_RX | \
145 ICE_PROMISC_MCAST_RX | \
146 ICE_PROMISC_VLAN_TX | \
149 #define ICE_MCAST_PROMISC_BITS (ICE_PROMISC_MCAST_TX | ICE_PROMISC_MCAST_RX)
151 #define ICE_MCAST_VLAN_PROMISC_BITS (ICE_PROMISC_MCAST_TX | \
152 ICE_PROMISC_MCAST_RX | \
153 ICE_PROMISC_VLAN_TX | \
156 #define ice_pf_to_dev(pf) (&((pf)->pdev->dev))
158 struct ice_txq_meta {
159 u32 q_teid; /* Tx-scheduler element identifier */
160 u16 q_id; /* Entry in VSI's txq_map bitmap */
161 u16 q_handle; /* Relative index of Tx queue within TC */
162 u16 vsi_idx; /* VSI index that Tx queue belongs to */
163 u8 tc; /* TC number that Tx queue belongs to */
174 u8 numtc; /* Total number of enabled TCs */
175 u8 ena_tc; /* Tx map */
176 struct ice_tc_info tc_info[ICE_MAX_TRAFFIC_CLASS];
179 struct ice_res_tracker {
186 struct mutex *qs_mutex; /* will be assigned to &pf->avail_q_mutex */
187 unsigned long *pf_map;
188 unsigned long pf_map_size;
189 unsigned int q_count;
190 unsigned int scatter_count;
198 u16 sw_id; /* switch ID for this switch */
199 u16 bridge_mode; /* VEB/VEPA/Port Virtualizer */
200 struct ice_vsi *dflt_vsi; /* default VSI for this switch */
201 u8 dflt_vsi_ena:1; /* true if above dflt_vsi is enabled */
208 ICE_PREPARED_FOR_RESET, /* set by driver when prepared */
209 ICE_RESET_OICR_RECV, /* set by driver after rcv reset OICR */
210 ICE_PFR_REQ, /* set by driver */
211 ICE_CORER_REQ, /* set by driver */
212 ICE_GLOBR_REQ, /* set by driver */
213 ICE_CORER_RECV, /* set by OICR handler */
214 ICE_GLOBR_RECV, /* set by OICR handler */
215 ICE_EMPR_RECV, /* set by OICR handler */
216 ICE_SUSPENDED, /* set on module remove path */
217 ICE_RESET_FAILED, /* set by reset/rebuild */
218 /* When checking for the PF to be in a nominal operating state, the
219 * bits that are grouped at the beginning of the list need to be
220 * checked. Bits occurring before ICE_STATE_NOMINAL_CHECK_BITS will
221 * be checked. If you need to add a bit into consideration for nominal
222 * operating state, it must be added before
223 * ICE_STATE_NOMINAL_CHECK_BITS. Do not move this entry's position
224 * without appropriate consideration.
226 ICE_STATE_NOMINAL_CHECK_BITS,
227 ICE_ADMINQ_EVENT_PENDING,
228 ICE_MAILBOXQ_EVENT_PENDING,
229 ICE_MDD_EVENT_PENDING,
230 ICE_VFLR_EVENT_PENDING,
231 ICE_FLTR_OVERFLOW_PROMISC,
237 ICE_OICR_INTR_DIS, /* Global OICR interrupt disabled */
238 ICE_MDD_VF_PRINT_PENDING, /* set when MDD event handle */
239 ICE_VF_RESETS_DISABLED, /* disable resets during ice_remove */
240 ICE_LINK_DEFAULT_OVERRIDE_PENDING,
241 ICE_PHY_INIT_COMPLETE,
242 ICE_FD_VF_FLUSH_CTX, /* set at FD Rx IRQ or timeout */
243 ICE_STATE_NBITS /* must be last */
248 ICE_VSI_NEEDS_RESTART,
249 ICE_VSI_NETDEV_ALLOCD,
250 ICE_VSI_NETDEV_REGISTERED,
251 ICE_VSI_UMAC_FLTR_CHANGED,
252 ICE_VSI_MMAC_FLTR_CHANGED,
253 ICE_VSI_VLAN_FLTR_CHANGED,
254 ICE_VSI_PROMISC_CHANGED,
255 ICE_VSI_STATE_NBITS /* must be last */
258 /* struct that defines a VSI, associated with a dev */
260 struct net_device *netdev;
261 struct ice_sw *vsw; /* switch this VSI is on */
262 struct ice_pf *back; /* back pointer to PF */
263 struct ice_port_info *port_info; /* back pointer to port_info */
264 struct ice_ring **rx_rings; /* Rx ring array */
265 struct ice_ring **tx_rings; /* Tx ring array */
266 struct ice_q_vector **q_vectors; /* q_vector array */
268 irqreturn_t (*irq_handler)(int irq, void *data);
271 DECLARE_BITMAP(state, ICE_VSI_STATE_NBITS);
272 unsigned int current_netdev_flags;
278 u16 base_vector; /* IRQ base for OS reserved vectors */
279 enum ice_vsi_type type;
280 u16 vsi_num; /* HW (absolute) index of this VSI */
281 u16 idx; /* software index in pf->vsi[] */
283 s16 vf_id; /* VF ID for SR-IOV VSIs */
285 u16 ethtype; /* Ethernet protocol for pause frame */
290 u16 rss_table_size; /* HW RSS table size */
291 u16 rss_size; /* Allocated RSS queues */
292 u8 *rss_hkey_user; /* User configured hash keys */
293 u8 *rss_lut_user; /* User configured lookup table entries */
294 u8 rss_lut_type; /* used to configure Get/Set RSS LUT AQ call */
296 /* aRFS members only allocated for the PF VSI */
297 #define ICE_MAX_ARFS_LIST 1024
298 #define ICE_ARFS_LST_MASK (ICE_MAX_ARFS_LIST - 1)
299 struct hlist_head *arfs_fltr_list;
300 struct ice_arfs_active_fltr_cntrs *arfs_fltr_cntrs;
301 spinlock_t arfs_lock; /* protects aRFS hash table and filter state */
302 atomic_t *arfs_last_fltr_id;
304 /* devlink port data */
305 struct devlink_port devlink_port;
306 bool devlink_port_registered;
311 struct ice_aqc_vsi_props info; /* VSI properties */
314 struct rtnl_link_stats64 net_stats;
315 struct ice_eth_stats eth_stats;
316 struct ice_eth_stats eth_stats_prev;
318 struct list_head tmp_sync_list; /* MAC filters to be synced */
319 struct list_head tmp_unsync_list; /* MAC filters to be unsynced */
322 u8 current_isup:1; /* Sync 'link up' logging */
323 u8 stat_offsets_loaded:1;
326 /* queue information */
327 u8 tx_mapping_mode; /* ICE_MAP_MODE_[CONTIG|SCATTER] */
328 u8 rx_mapping_mode; /* ICE_MAP_MODE_[CONTIG|SCATTER] */
329 u16 *txq_map; /* index in pf->avail_txqs */
330 u16 *rxq_map; /* index in pf->avail_rxqs */
331 u16 alloc_txq; /* Allocated Tx queues */
332 u16 num_txq; /* Used Tx queues */
333 u16 alloc_rxq; /* Allocated Rx queues */
334 u16 num_rxq; /* Used Rx queues */
335 u16 req_txq; /* User requested Tx queues */
336 u16 req_rxq; /* User requested Rx queues */
339 u16 qset_handle[ICE_MAX_TRAFFIC_CLASS];
340 struct ice_tc_cfg tc_cfg;
341 struct bpf_prog *xdp_prog;
342 struct ice_ring **xdp_rings; /* XDP ring array */
343 u16 num_xdp_txq; /* Used XDP queues */
344 u8 xdp_mapping_mode; /* ICE_MAP_MODE_[CONTIG|SCATTER] */
346 /* setup back reference, to which aggregator node this VSI
349 struct ice_agg_node *agg_node;
350 } ____cacheline_internodealigned_in_smp;
352 /* struct that defines an interrupt vector */
353 struct ice_q_vector {
356 u16 v_idx; /* index in the vsi->q_vector array. */
358 u8 num_ring_rx; /* total number of Rx rings in vector */
359 u8 num_ring_tx; /* total number of Tx rings in vector */
360 u8 wb_on_itr:1; /* if true, WB on ITR is enabled */
361 /* in usecs, need to use ice_intrl_to_usecs_reg() before writing this
362 * value to the device
366 struct napi_struct napi;
368 struct ice_ring_container rx;
369 struct ice_ring_container tx;
371 cpumask_t affinity_mask;
372 struct irq_affinity_notify affinity_notify;
374 char name[ICE_INT_NAME_STR_LEN];
376 u16 total_events; /* net_dim(): number of interrupts processed */
377 } ____cacheline_internodealigned_in_smp;
384 ICE_FLAG_SRIOV_CAPABLE,
385 ICE_FLAG_DCB_CAPABLE,
389 ICE_FLAG_ADV_FEATURES,
390 ICE_FLAG_LINK_DOWN_ON_CLOSE_ENA,
391 ICE_FLAG_TOTAL_PORT_SHUTDOWN_ENA,
393 ICE_FLAG_FW_LLDP_AGENT,
394 ICE_FLAG_ETHTOOL_CTXT, /* set when ethtool holds RTNL lock */
396 ICE_FLAG_VF_TRUE_PROMISC_ENA,
397 ICE_FLAG_MDD_AUTO_RESET_VF,
398 ICE_FLAG_LINK_LENIENT_MODE_ENA,
399 ICE_PF_FLAGS_NBITS /* must be last */
402 struct ice_agg_node {
404 #define ICE_MAX_VSIS_IN_AGG_NODE 64
410 struct pci_dev *pdev;
412 struct devlink_region *nvm_region;
413 struct devlink_region *devcaps_region;
415 /* OS reserved IRQ details */
416 struct msix_entry *msix_entries;
417 struct ice_res_tracker *irq_tracker;
418 /* First MSIX vector used by SR-IOV VFs. Calculated by subtracting the
419 * number of MSIX vectors needed for all SR-IOV VFs from the number of
420 * MSIX vectors allowed on this PF.
422 u16 sriov_base_vector;
424 u16 ctrl_vsi_idx; /* control VSI index in pf->vsi array */
426 struct ice_vsi **vsi; /* VSIs created by the driver */
427 struct ice_sw *first_sw; /* first switch created by firmware */
428 /* Virtchnl/SR-IOV config info */
430 u16 num_alloc_vfs; /* actual number of VFs allocated */
431 u16 num_vfs_supported; /* num VFs supported for this PF */
434 /* used to ratelimit the MDD event logging */
435 unsigned long last_printed_mdd_jiffies;
436 DECLARE_BITMAP(malvfs, ICE_MAX_VF_COUNT);
437 DECLARE_BITMAP(state, ICE_STATE_NBITS);
438 DECLARE_BITMAP(flags, ICE_PF_FLAGS_NBITS);
439 unsigned long *avail_txqs; /* bitmap to track PF Tx queue usage */
440 unsigned long *avail_rxqs; /* bitmap to track PF Rx queue usage */
441 unsigned long serv_tmr_period;
442 unsigned long serv_tmr_prev;
443 struct timer_list serv_tmr;
444 struct work_struct serv_task;
445 struct mutex avail_q_mutex; /* protects access to avail_[rx|tx]qs */
446 struct mutex sw_mutex; /* lock for protecting VSI alloc flow */
447 struct mutex tc_mutex; /* lock to protect TC changes */
449 u16 num_rdma_msix; /* Total MSIX vectors for RDMA driver */
450 u16 rdma_base_vector;
452 /* spinlock to protect the AdminQ wait list */
453 spinlock_t aq_wait_lock;
454 struct hlist_head aq_wait_list;
455 wait_queue_head_t aq_wait_queue;
457 u32 hw_csum_rx_error;
458 u16 oicr_idx; /* Other interrupt cause MSIX vector index */
459 u16 num_avail_sw_msix; /* remaining MSIX SW vectors left unclaimed */
460 u16 max_pf_txqs; /* Total Tx queues PF wide */
461 u16 max_pf_rxqs; /* Total Rx queues PF wide */
462 u16 num_lan_msix; /* Total MSIX vectors for base driver */
463 u16 num_lan_tx; /* num LAN Tx queues setup */
464 u16 num_lan_rx; /* num LAN Rx queues setup */
465 u16 next_vsi; /* Next free slot in pf->vsi[] - 0-based! */
467 u16 corer_count; /* Core reset count */
468 u16 globr_count; /* Global reset count */
469 u16 empr_count; /* EMP reset count */
470 u16 pfr_count; /* PF reset count */
472 u8 wol_ena : 1; /* software state of WoL */
473 u32 wakeup_reason; /* last wakeup reason */
474 struct ice_hw_port_stats stats;
475 struct ice_hw_port_stats stats_prev;
477 u8 stat_prev_loaded:1; /* has previous stats been loaded */
479 u32 tx_timeout_count;
480 unsigned long tx_timeout_last_recovery;
481 u32 tx_timeout_recovery_level;
482 char int_name[ICE_INT_NAME_STR_LEN];
483 struct auxiliary_device *adev;
487 __le64 nvm_phy_type_lo; /* NVM PHY type low */
488 __le64 nvm_phy_type_hi; /* NVM PHY type high */
489 struct ice_link_default_override_tlv link_dflt_override;
490 struct ice_lag *lag; /* Link Aggregation information */
492 #define ICE_INVALID_AGG_NODE_ID 0
493 #define ICE_PF_AGG_NODE_ID_START 1
494 #define ICE_MAX_PF_AGG_NODES 32
495 struct ice_agg_node pf_agg_node[ICE_MAX_PF_AGG_NODES];
496 #define ICE_VF_AGG_NODE_ID_START 65
497 #define ICE_MAX_VF_AGG_NODES 32
498 struct ice_agg_node vf_agg_node[ICE_MAX_VF_AGG_NODES];
501 struct ice_netdev_priv {
506 * ice_irq_dynamic_ena - Enable default interrupt generation settings
507 * @hw: pointer to HW struct
508 * @vsi: pointer to VSI struct, can be NULL
509 * @q_vector: pointer to q_vector, can be NULL
512 ice_irq_dynamic_ena(struct ice_hw *hw, struct ice_vsi *vsi,
513 struct ice_q_vector *q_vector)
515 u32 vector = (vsi && q_vector) ? q_vector->reg_idx :
516 ((struct ice_pf *)hw->back)->oicr_idx;
517 int itr = ICE_ITR_NONE;
520 /* clear the PBA here, as this function is meant to clean out all
521 * previous interrupts and enable the interrupt
523 val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
524 (itr << GLINT_DYN_CTL_ITR_INDX_S);
526 if (test_bit(ICE_VSI_DOWN, vsi->state))
528 wr32(hw, GLINT_DYN_CTL(vector), val);
532 * ice_netdev_to_pf - Retrieve the PF struct associated with a netdev
533 * @netdev: pointer to the netdev struct
535 static inline struct ice_pf *ice_netdev_to_pf(struct net_device *netdev)
537 struct ice_netdev_priv *np = netdev_priv(netdev);
539 return np->vsi->back;
542 static inline bool ice_is_xdp_ena_vsi(struct ice_vsi *vsi)
544 return !!vsi->xdp_prog;
547 static inline void ice_set_ring_xdp(struct ice_ring *ring)
549 ring->flags |= ICE_TX_FLAGS_RING_XDP;
553 * ice_xsk_pool - get XSK buffer pool bound to a ring
556 * Returns a pointer to xdp_umem structure if there is a buffer pool present,
559 static inline struct xsk_buff_pool *ice_xsk_pool(struct ice_ring *ring)
561 u16 qid = ring->q_index;
563 if (ice_ring_is_xdp(ring))
564 qid -= ring->vsi->num_xdp_txq;
566 if (!ice_is_xdp_ena_vsi(ring->vsi))
569 return xsk_get_pool_from_qid(ring->vsi->netdev, qid);
573 * ice_get_main_vsi - Get the PF VSI
576 * returns pf->vsi[0], which by definition is the PF VSI
578 static inline struct ice_vsi *ice_get_main_vsi(struct ice_pf *pf)
587 * ice_get_ctrl_vsi - Get the control VSI
590 static inline struct ice_vsi *ice_get_ctrl_vsi(struct ice_pf *pf)
592 /* if pf->ctrl_vsi_idx is ICE_NO_VSI, control VSI was not set up */
593 if (!pf->vsi || pf->ctrl_vsi_idx == ICE_NO_VSI)
596 return pf->vsi[pf->ctrl_vsi_idx];
600 * ice_set_sriov_cap - enable SRIOV in PF flags
603 static inline void ice_set_sriov_cap(struct ice_pf *pf)
605 if (pf->hw.func_caps.common_cap.sr_iov_1_1)
606 set_bit(ICE_FLAG_SRIOV_CAPABLE, pf->flags);
610 * ice_clear_sriov_cap - disable SRIOV in PF flags
613 static inline void ice_clear_sriov_cap(struct ice_pf *pf)
615 clear_bit(ICE_FLAG_SRIOV_CAPABLE, pf->flags);
618 #define ICE_FD_STAT_CTR_BLOCK_COUNT 256
619 #define ICE_FD_STAT_PF_IDX(base_idx) \
620 ((base_idx) * ICE_FD_STAT_CTR_BLOCK_COUNT)
621 #define ICE_FD_SB_STAT_IDX(base_idx) ICE_FD_STAT_PF_IDX(base_idx)
623 bool netif_is_ice(struct net_device *dev);
624 int ice_vsi_setup_tx_rings(struct ice_vsi *vsi);
625 int ice_vsi_setup_rx_rings(struct ice_vsi *vsi);
626 int ice_vsi_open_ctrl(struct ice_vsi *vsi);
627 void ice_set_ethtool_ops(struct net_device *netdev);
628 void ice_set_ethtool_safe_mode_ops(struct net_device *netdev);
629 u16 ice_get_avail_txq_count(struct ice_pf *pf);
630 u16 ice_get_avail_rxq_count(struct ice_pf *pf);
631 int ice_vsi_recfg_qs(struct ice_vsi *vsi, int new_rx, int new_tx);
632 void ice_update_vsi_stats(struct ice_vsi *vsi);
633 void ice_update_pf_stats(struct ice_pf *pf);
634 int ice_up(struct ice_vsi *vsi);
635 int ice_down(struct ice_vsi *vsi);
636 int ice_vsi_cfg(struct ice_vsi *vsi);
637 struct ice_vsi *ice_lb_vsi_setup(struct ice_pf *pf, struct ice_port_info *pi);
638 int ice_prepare_xdp_rings(struct ice_vsi *vsi, struct bpf_prog *prog);
639 int ice_destroy_xdp_rings(struct ice_vsi *vsi);
641 ice_xdp_xmit(struct net_device *dev, int n, struct xdp_frame **frames,
643 int ice_set_rss_lut(struct ice_vsi *vsi, u8 *lut, u16 lut_size);
644 int ice_get_rss_lut(struct ice_vsi *vsi, u8 *lut, u16 lut_size);
645 int ice_set_rss_key(struct ice_vsi *vsi, u8 *seed);
646 int ice_get_rss_key(struct ice_vsi *vsi, u8 *seed);
647 void ice_fill_rss_lut(u8 *lut, u16 rss_table_size, u16 rss_size);
648 int ice_schedule_reset(struct ice_pf *pf, enum ice_reset_req reset);
649 void ice_print_link_msg(struct ice_vsi *vsi, bool isup);
650 int ice_init_rdma(struct ice_pf *pf);
651 const char *ice_stat_str(enum ice_status stat_err);
652 const char *ice_aq_str(enum ice_aq_err aq_err);
653 bool ice_is_wol_supported(struct ice_hw *hw);
655 ice_fdir_write_fltr(struct ice_pf *pf, struct ice_fdir_fltr *input, bool add,
657 void ice_vsi_manage_fdir(struct ice_vsi *vsi, bool ena);
658 int ice_add_fdir_ethtool(struct ice_vsi *vsi, struct ethtool_rxnfc *cmd);
659 int ice_del_fdir_ethtool(struct ice_vsi *vsi, struct ethtool_rxnfc *cmd);
660 int ice_get_ethtool_fdir_entry(struct ice_hw *hw, struct ethtool_rxnfc *cmd);
662 ice_get_fdir_fltr_ids(struct ice_hw *hw, struct ethtool_rxnfc *cmd,
664 void ice_fdir_release_flows(struct ice_hw *hw);
665 void ice_fdir_replay_flows(struct ice_hw *hw);
666 void ice_fdir_replay_fltrs(struct ice_pf *pf);
667 int ice_fdir_create_dflt_rules(struct ice_pf *pf);
668 int ice_aq_wait_for_event(struct ice_pf *pf, u16 opcode, unsigned long timeout,
669 struct ice_rq_event_info *event);
670 int ice_open(struct net_device *netdev);
671 int ice_open_internal(struct net_device *netdev);
672 int ice_stop(struct net_device *netdev);
673 void ice_service_task_schedule(struct ice_pf *pf);
676 * ice_set_rdma_cap - enable RDMA support
679 static inline void ice_set_rdma_cap(struct ice_pf *pf)
681 if (pf->hw.func_caps.common_cap.rdma && pf->num_rdma_msix)
682 set_bit(ICE_FLAG_RDMA_ENA, pf->flags);
686 * ice_clear_rdma_cap - disable RDMA support
689 static inline void ice_clear_rdma_cap(struct ice_pf *pf)
691 clear_bit(ICE_FLAG_RDMA_ENA, pf->flags);