drivers/net/ethernet/intel/i40evf/i40e_txrx.c

   1 /*******************************************************************************
   2  *
   3  * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
   4  * Copyright(c) 2013 - 2016 Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * The full GNU General Public License is included in this distribution in
  19  * the file called "COPYING".
  20  *
  21  * Contact Information:
  22  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24  *
  25  ******************************************************************************/
  26
  27 #include <linux/prefetch.h>
  28 #include <net/busy_poll.h>
  29
  30 #include "i40evf.h"
  31 #include "i40e_prototype.h"
  32
  33 static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size,
  34                                 u32 td_tag)
  35 {
  36         return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA |
  37                            ((u64)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
  38                            ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
  39                            ((u64)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
  40                            ((u64)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
  41 }
  42
  43 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
  44
  45 /**
  46  * i40e_unmap_and_free_tx_resource - Release a Tx buffer
  47  * @ring:      the ring that owns the buffer
  48  * @tx_buffer: the buffer to free
  49  **/
  50 static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring,
  51                                             struct i40e_tx_buffer *tx_buffer)
  52 {
  53         if (tx_buffer->skb) {
  54                 dev_kfree_skb_any(tx_buffer->skb);
  55                 if (dma_unmap_len(tx_buffer, len))
  56                         dma_unmap_single(ring->dev,
  57                                          dma_unmap_addr(tx_buffer, dma),
  58                                          dma_unmap_len(tx_buffer, len),
  59                                          DMA_TO_DEVICE);
  60         } else if (dma_unmap_len(tx_buffer, len)) {
  61                 dma_unmap_page(ring->dev,
  62                                dma_unmap_addr(tx_buffer, dma),
  63                                dma_unmap_len(tx_buffer, len),
  64                                DMA_TO_DEVICE);
  65         }
  66
  67         if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB)
  68                 kfree(tx_buffer->raw_buf);
  69
  70         tx_buffer->next_to_watch = NULL;
  71         tx_buffer->skb = NULL;
  72         dma_unmap_len_set(tx_buffer, len, 0);
  73         /* tx_buffer must be completely set up in the transmit path */
  74 }
  75
  76 /**
  77  * i40evf_clean_tx_ring - Free any empty Tx buffers
  78  * @tx_ring: ring to be cleaned
  79  **/
  80 void i40evf_clean_tx_ring(struct i40e_ring *tx_ring)
  81 {
  82         unsigned long bi_size;
  83         u16 i;
  84
  85         /* ring already cleared, nothing to do */
  86         if (!tx_ring->tx_bi)
  87                 return;
  88
  89         /* Free all the Tx ring sk_buffs */
  90         for (i = 0; i < tx_ring->count; i++)
  91                 i40e_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]);
  92
  93         bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
  94         memset(tx_ring->tx_bi, 0, bi_size);
  95
  96         /* Zero out the descriptor ring */
  97         memset(tx_ring->desc, 0, tx_ring->size);
  98
  99         tx_ring->next_to_use = 0;
 100         tx_ring->next_to_clean = 0;
 101
 102         if (!tx_ring->netdev)
 103                 return;
 104
 105         /* cleanup Tx queue statistics */
 106         netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring->netdev,
 107                                                   tx_ring->queue_index));
 108 }
 109
 110 /**
 111  * i40evf_free_tx_resources - Free Tx resources per queue
 112  * @tx_ring: Tx descriptor ring for a specific queue
 113  *
 114  * Free all transmit software resources
 115  **/
 116 void i40evf_free_tx_resources(struct i40e_ring *tx_ring)
 117 {
 118         i40evf_clean_tx_ring(tx_ring);
 119         kfree(tx_ring->tx_bi);
 120         tx_ring->tx_bi = NULL;
 121
 122         if (tx_ring->desc) {
 123                 dma_free_coherent(tx_ring->dev, tx_ring->size,
 124                                   tx_ring->desc, tx_ring->dma);
 125                 tx_ring->desc = NULL;
 126         }
 127 }
 128
 129 /**
 130  * i40evf_get_tx_pending - how many Tx descriptors not processed
 131  * @tx_ring: the ring of descriptors
 132  * @in_sw: is tx_pending being checked in SW or HW
 133  *
 134  * Since there is no access to the ring head register
 135  * in XL710, we need to use our local copies
 136  **/
 137 u32 i40evf_get_tx_pending(struct i40e_ring *ring, bool in_sw)
 138 {
 139         u32 head, tail;
 140
 141         if (!in_sw)
 142                 head = i40e_get_head(ring);
 143         else
 144                 head = ring->next_to_clean;
 145         tail = readl(ring->tail);
 146
 147         if (head != tail)
 148                 return (head < tail) ?
 149                         tail - head : (tail + ring->count - head);
 150
 151         return 0;
 152 }
 153
 154 #define WB_STRIDE 0x3
 155
 156 /**
 157  * i40e_clean_tx_irq - Reclaim resources after transmit completes
 158  * @vsi: the VSI we care about
 159  * @tx_ring: Tx ring to clean
 160  * @napi_budget: Used to determine if we are in netpoll
 161  *
 162  * Returns true if there's any budget left (e.g. the clean is finished)
 163  **/
 164 static bool i40e_clean_tx_irq(struct i40e_vsi *vsi,
 165                               struct i40e_ring *tx_ring, int napi_budget)
 166 {
 167         u16 i = tx_ring->next_to_clean;
 168         struct i40e_tx_buffer *tx_buf;
 169         struct i40e_tx_desc *tx_head;
 170         struct i40e_tx_desc *tx_desc;
 171         unsigned int total_bytes = 0, total_packets = 0;
 172         unsigned int budget = vsi->work_limit;
 173
 174         tx_buf = &tx_ring->tx_bi[i];
 175         tx_desc = I40E_TX_DESC(tx_ring, i);
 176         i -= tx_ring->count;
 177
 178         tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring));
 179
 180         do {
 181                 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
 182
 183                 /* if next_to_watch is not set then there is no work pending */
 184                 if (!eop_desc)
 185                         break;
 186
 187                 /* prevent any other reads prior to eop_desc */
 188                 read_barrier_depends();
 189
 190                 /* we have caught up to head, no work left to do */
 191                 if (tx_head == tx_desc)
 192                         break;
 193
 194                 /* clear next_to_watch to prevent false hangs */
 195                 tx_buf->next_to_watch = NULL;
 196
 197                 /* update the statistics for this packet */
 198                 total_bytes += tx_buf->bytecount;
 199                 total_packets += tx_buf->gso_segs;
 200
 201                 /* free the skb */
 202                 napi_consume_skb(tx_buf->skb, napi_budget);
 203
 204                 /* unmap skb header data */
 205                 dma_unmap_single(tx_ring->dev,
 206                                  dma_unmap_addr(tx_buf, dma),
 207                                  dma_unmap_len(tx_buf, len),
 208                                  DMA_TO_DEVICE);
 209
 210                 /* clear tx_buffer data */
 211                 tx_buf->skb = NULL;
 212                 dma_unmap_len_set(tx_buf, len, 0);
 213
 214                 /* unmap remaining buffers */
 215                 while (tx_desc != eop_desc) {
 216
 217                         tx_buf++;
 218                         tx_desc++;
 219                         i++;
 220                         if (unlikely(!i)) {
 221                                 i -= tx_ring->count;
 222                                 tx_buf = tx_ring->tx_bi;
 223                                 tx_desc = I40E_TX_DESC(tx_ring, 0);
 224                         }
 225
 226                         /* unmap any remaining paged data */
 227                         if (dma_unmap_len(tx_buf, len)) {
 228                                 dma_unmap_page(tx_ring->dev,
 229                                                dma_unmap_addr(tx_buf, dma),
 230                                                dma_unmap_len(tx_buf, len),
 231                                                DMA_TO_DEVICE);
 232                                 dma_unmap_len_set(tx_buf, len, 0);
 233                         }
 234                 }
 235
 236                 /* move us one more past the eop_desc for start of next pkt */
 237                 tx_buf++;
 238                 tx_desc++;
 239                 i++;
 240                 if (unlikely(!i)) {
 241                         i -= tx_ring->count;
 242                         tx_buf = tx_ring->tx_bi;
 243                         tx_desc = I40E_TX_DESC(tx_ring, 0);
 244                 }
 245
 246                 prefetch(tx_desc);
 247
 248                 /* update budget accounting */
 249                 budget--;
 250         } while (likely(budget));
 251
 252         i += tx_ring->count;
 253         tx_ring->next_to_clean = i;
 254         u64_stats_update_begin(&tx_ring->syncp);
 255         tx_ring->stats.bytes += total_bytes;
 256         tx_ring->stats.packets += total_packets;
 257         u64_stats_update_end(&tx_ring->syncp);
 258         tx_ring->q_vector->tx.total_bytes += total_bytes;
 259         tx_ring->q_vector->tx.total_packets += total_packets;
 260
 261         if (tx_ring->flags & I40E_TXR_FLAGS_WB_ON_ITR) {
 262                 unsigned int j = 0;
 263                 /* check to see if there are < 4 descriptors
 264                  * waiting to be written back, then kick the hardware to force
 265                  * them to be written back in case we stay in NAPI.
 266                  * In this mode on X722 we do not enable Interrupt.
 267                  */
 268                 j = i40evf_get_tx_pending(tx_ring, false);
 269
 270                 if (budget &&
 271                     ((j / (WB_STRIDE + 1)) == 0) && (j > 0) &&
 272                     !test_bit(__I40E_DOWN, &vsi->state) &&
 273                     (I40E_DESC_UNUSED(tx_ring) != tx_ring->count))
 274                         tx_ring->arm_wb = true;
 275         }
 276
 277         netdev_tx_completed_queue(netdev_get_tx_queue(tx_ring->netdev,
 278                                                       tx_ring->queue_index),
 279                                   total_packets, total_bytes);
 280
 281 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 282         if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
 283                      (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 284                 /* Make sure that anybody stopping the queue after this
 285                  * sees the new next_to_clean.
 286                  */
 287                 smp_mb();
 288                 if (__netif_subqueue_stopped(tx_ring->netdev,
 289                                              tx_ring->queue_index) &&
 290                    !test_bit(__I40E_DOWN, &vsi->state)) {
 291                         netif_wake_subqueue(tx_ring->netdev,
 292                                             tx_ring->queue_index);
 293                         ++tx_ring->tx_stats.restart_queue;
 294                 }
 295         }
 296
 297         return !!budget;
 298 }
 299
 300 /**
 301  * i40evf_enable_wb_on_itr - Arm hardware to do a wb, interrupts are not enabled
 302  * @vsi: the VSI we care about
 303  * @q_vector: the vector on which to enable writeback
 304  *
 305  **/
 306 static void i40e_enable_wb_on_itr(struct i40e_vsi *vsi,
 307                                   struct i40e_q_vector *q_vector)
 308 {
 309         u16 flags = q_vector->tx.ring[0].flags;
 310         u32 val;
 311
 312         if (!(flags & I40E_TXR_FLAGS_WB_ON_ITR))
 313                 return;
 314
 315         if (q_vector->arm_wb_state)
 316                 return;
 317
 318         val = I40E_VFINT_DYN_CTLN1_WB_ON_ITR_MASK |
 319               I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK; /* set noitr */
 320
 321         wr32(&vsi->back->hw,
 322              I40E_VFINT_DYN_CTLN1(q_vector->v_idx +
 323                                   vsi->base_vector - 1), val);
 324         q_vector->arm_wb_state = true;
 325 }
 326
 327 /**
 328  * i40evf_force_wb - Issue SW Interrupt so HW does a wb
 329  * @vsi: the VSI we care about
 330  * @q_vector: the vector  on which to force writeback
 331  *
 332  **/
 333 void i40evf_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector)
 334 {
 335         u32 val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
 336                   I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK | /* set noitr */
 337                   I40E_VFINT_DYN_CTLN1_SWINT_TRIG_MASK |
 338                   I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK
 339                   /* allow 00 to be written to the index */;
 340
 341         wr32(&vsi->back->hw,
 342              I40E_VFINT_DYN_CTLN1(q_vector->v_idx + vsi->base_vector - 1),
 343              val);
 344 }
 345
 346 /**
 347  * i40e_set_new_dynamic_itr - Find new ITR level
 348  * @rc: structure containing ring performance data
 349  *
 350  * Returns true if ITR changed, false if not
 351  *
 352  * Stores a new ITR value based on packets and byte counts during
 353  * the last interrupt.  The advantage of per interrupt computation
 354  * is faster updates and more accurate ITR for the current traffic
 355  * pattern.  Constants in this function were computed based on
 356  * theoretical maximum wire speed and thresholds were set based on
 357  * testing data as well as attempting to minimize response time
 358  * while increasing bulk throughput.
 359  **/
 360 static bool i40e_set_new_dynamic_itr(struct i40e_ring_container *rc)
 361 {
 362         enum i40e_latency_range new_latency_range = rc->latency_range;
 363         struct i40e_q_vector *qv = rc->ring->q_vector;
 364         u32 new_itr = rc->itr;
 365         int bytes_per_int;
 366         int usecs;
 367
 368         if (rc->total_packets == 0 || !rc->itr)
 369                 return false;
 370
 371         /* simple throttlerate management
 372          *   0-10MB/s   lowest (50000 ints/s)
 373          *  10-20MB/s   low    (20000 ints/s)
 374          *  20-1249MB/s bulk   (18000 ints/s)
 375          *  > 40000 Rx packets per second (8000 ints/s)
 376          *
 377          * The math works out because the divisor is in 10^(-6) which
 378          * turns the bytes/us input value into MB/s values, but
 379          * make sure to use usecs, as the register values written
 380          * are in 2 usec increments in the ITR registers, and make sure
 381          * to use the smoothed values that the countdown timer gives us.
 382          */
 383         usecs = (rc->itr << 1) * ITR_COUNTDOWN_START;
 384         bytes_per_int = rc->total_bytes / usecs;
 385
 386         switch (new_latency_range) {
 387         case I40E_LOWEST_LATENCY:
 388                 if (bytes_per_int > 10)
 389                         new_latency_range = I40E_LOW_LATENCY;
 390                 break;
 391         case I40E_LOW_LATENCY:
 392                 if (bytes_per_int > 20)
 393                         new_latency_range = I40E_BULK_LATENCY;
 394                 else if (bytes_per_int <= 10)
 395                         new_latency_range = I40E_LOWEST_LATENCY;
 396                 break;
 397         case I40E_BULK_LATENCY:
 398         case I40E_ULTRA_LATENCY:
 399         default:
 400                 if (bytes_per_int <= 20)
 401                         new_latency_range = I40E_LOW_LATENCY;
 402                 break;
 403         }
 404
 405         /* this is to adjust RX more aggressively when streaming small
 406          * packets.  The value of 40000 was picked as it is just beyond
 407          * what the hardware can receive per second if in low latency
 408          * mode.
 409          */
 410 #define RX_ULTRA_PACKET_RATE 40000
 411
 412         if ((((rc->total_packets * 1000000) / usecs) > RX_ULTRA_PACKET_RATE) &&
 413             (&qv->rx == rc))
 414                 new_latency_range = I40E_ULTRA_LATENCY;
 415
 416         rc->latency_range = new_latency_range;
 417
 418         switch (new_latency_range) {
 419         case I40E_LOWEST_LATENCY:
 420                 new_itr = I40E_ITR_50K;
 421                 break;
 422         case I40E_LOW_LATENCY:
 423                 new_itr = I40E_ITR_20K;
 424                 break;
 425         case I40E_BULK_LATENCY:
 426                 new_itr = I40E_ITR_18K;
 427                 break;
 428         case I40E_ULTRA_LATENCY:
 429                 new_itr = I40E_ITR_8K;
 430                 break;
 431         default:
 432                 break;
 433         }
 434
 435         rc->total_bytes = 0;
 436         rc->total_packets = 0;
 437
 438         if (new_itr != rc->itr) {
 439                 rc->itr = new_itr;
 440                 return true;
 441         }
 442
 443         return false;
 444 }
 445
 446 /**
 447  * i40evf_setup_tx_descriptors - Allocate the Tx descriptors
 448  * @tx_ring: the tx ring to set up
 449  *
 450  * Return 0 on success, negative on error
 451  **/
 452 int i40evf_setup_tx_descriptors(struct i40e_ring *tx_ring)
 453 {
 454         struct device *dev = tx_ring->dev;
 455         int bi_size;
 456
 457         if (!dev)
 458                 return -ENOMEM;
 459
 460         /* warn if we are about to overwrite the pointer */
 461         WARN_ON(tx_ring->tx_bi);
 462         bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
 463         tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL);
 464         if (!tx_ring->tx_bi)
 465                 goto err;
 466
 467         /* round up to nearest 4K */
 468         tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc);
 469         /* add u32 for head writeback, align after this takes care of
 470          * guaranteeing this is at least one cache line in size
 471          */
 472         tx_ring->size += sizeof(u32);
 473         tx_ring->size = ALIGN(tx_ring->size, 4096);
 474         tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
 475                                            &tx_ring->dma, GFP_KERNEL);
 476         if (!tx_ring->desc) {
 477                 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
 478                          tx_ring->size);
 479                 goto err;
 480         }
 481
 482         tx_ring->next_to_use = 0;
 483         tx_ring->next_to_clean = 0;
 484         return 0;
 485
 486 err:
 487         kfree(tx_ring->tx_bi);
 488         tx_ring->tx_bi = NULL;
 489         return -ENOMEM;
 490 }
 491
 492 /**
 493  * i40evf_clean_rx_ring - Free Rx buffers
 494  * @rx_ring: ring to be cleaned
 495  **/
 496 void i40evf_clean_rx_ring(struct i40e_ring *rx_ring)
 497 {
 498         struct device *dev = rx_ring->dev;
 499         struct i40e_rx_buffer *rx_bi;
 500         unsigned long bi_size;
 501         u16 i;
 502
 503         /* ring already cleared, nothing to do */
 504         if (!rx_ring->rx_bi)
 505                 return;
 506
 507         if (ring_is_ps_enabled(rx_ring)) {
 508                 int bufsz = ALIGN(rx_ring->rx_hdr_len, 256) * rx_ring->count;
 509
 510                 rx_bi = &rx_ring->rx_bi[0];
 511                 if (rx_bi->hdr_buf) {
 512                         dma_free_coherent(dev,
 513                                           bufsz,
 514                                           rx_bi->hdr_buf,
 515                                           rx_bi->dma);
 516                         for (i = 0; i < rx_ring->count; i++) {
 517                                 rx_bi = &rx_ring->rx_bi[i];
 518                                 rx_bi->dma = 0;
 519                                 rx_bi->hdr_buf = NULL;
 520                         }
 521                 }
 522         }
 523         /* Free all the Rx ring sk_buffs */
 524         for (i = 0; i < rx_ring->count; i++) {
 525                 rx_bi = &rx_ring->rx_bi[i];
 526                 if (rx_bi->dma) {
 527                         dma_unmap_single(dev,
 528                                          rx_bi->dma,
 529                                          rx_ring->rx_buf_len,
 530                                          DMA_FROM_DEVICE);
 531                         rx_bi->dma = 0;
 532                 }
 533                 if (rx_bi->skb) {
 534                         dev_kfree_skb(rx_bi->skb);
 535                         rx_bi->skb = NULL;
 536                 }
 537                 if (rx_bi->page) {
 538                         if (rx_bi->page_dma) {
 539                                 dma_unmap_page(dev,
 540                                                rx_bi->page_dma,
 541                                                PAGE_SIZE,
 542                                                DMA_FROM_DEVICE);
 543                                 rx_bi->page_dma = 0;
 544                         }
 545                         __free_page(rx_bi->page);
 546                         rx_bi->page = NULL;
 547                         rx_bi->page_offset = 0;
 548                 }
 549         }
 550
 551         bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
 552         memset(rx_ring->rx_bi, 0, bi_size);
 553
 554         /* Zero out the descriptor ring */
 555         memset(rx_ring->desc, 0, rx_ring->size);
 556
 557         rx_ring->next_to_clean = 0;
 558         rx_ring->next_to_use = 0;
 559 }
 560
 561 /**
 562  * i40evf_free_rx_resources - Free Rx resources
 563  * @rx_ring: ring to clean the resources from
 564  *
 565  * Free all receive software resources
 566  **/
 567 void i40evf_free_rx_resources(struct i40e_ring *rx_ring)
 568 {
 569         i40evf_clean_rx_ring(rx_ring);
 570         kfree(rx_ring->rx_bi);
 571         rx_ring->rx_bi = NULL;
 572
 573         if (rx_ring->desc) {
 574                 dma_free_coherent(rx_ring->dev, rx_ring->size,
 575                                   rx_ring->desc, rx_ring->dma);
 576                 rx_ring->desc = NULL;
 577         }
 578 }
 579
 580 /**
 581  * i40evf_alloc_rx_headers - allocate rx header buffers
 582  * @rx_ring: ring to alloc buffers
 583  *
 584  * Allocate rx header buffers for the entire ring. As these are static,
 585  * this is only called when setting up a new ring.
 586  **/
 587 void i40evf_alloc_rx_headers(struct i40e_ring *rx_ring)
 588 {
 589         struct device *dev = rx_ring->dev;
 590         struct i40e_rx_buffer *rx_bi;
 591         dma_addr_t dma;
 592         void *buffer;
 593         int buf_size;
 594         int i;
 595
 596         if (rx_ring->rx_bi[0].hdr_buf)
 597                 return;
 598         /* Make sure the buffers don't cross cache line boundaries. */
 599         buf_size = ALIGN(rx_ring->rx_hdr_len, 256);
 600         buffer = dma_alloc_coherent(dev, buf_size * rx_ring->count,
 601                                     &dma, GFP_KERNEL);
 602         if (!buffer)
 603                 return;
 604         for (i = 0; i < rx_ring->count; i++) {
 605                 rx_bi = &rx_ring->rx_bi[i];
 606                 rx_bi->dma = dma + (i * buf_size);
 607                 rx_bi->hdr_buf = buffer + (i * buf_size);
 608         }
 609 }
 610
 611 /**
 612  * i40evf_setup_rx_descriptors - Allocate Rx descriptors
 613  * @rx_ring: Rx descriptor ring (for a specific queue) to setup
 614  *
 615  * Returns 0 on success, negative on failure
 616  **/
 617 int i40evf_setup_rx_descriptors(struct i40e_ring *rx_ring)
 618 {
 619         struct device *dev = rx_ring->dev;
 620         int bi_size;
 621
 622         /* warn if we are about to overwrite the pointer */
 623         WARN_ON(rx_ring->rx_bi);
 624         bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
 625         rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL);
 626         if (!rx_ring->rx_bi)
 627                 goto err;
 628
 629         u64_stats_init(&rx_ring->syncp);
 630
 631         /* Round up to nearest 4K */
 632         rx_ring->size = ring_is_16byte_desc_enabled(rx_ring)
 633                 ? rx_ring->count * sizeof(union i40e_16byte_rx_desc)
 634                 : rx_ring->count * sizeof(union i40e_32byte_rx_desc);
 635         rx_ring->size = ALIGN(rx_ring->size, 4096);
 636         rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
 637                                            &rx_ring->dma, GFP_KERNEL);
 638
 639         if (!rx_ring->desc) {
 640                 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
 641                          rx_ring->size);
 642                 goto err;
 643         }
 644
 645         rx_ring->next_to_clean = 0;
 646         rx_ring->next_to_use = 0;
 647
 648         return 0;
 649 err:
 650         kfree(rx_ring->rx_bi);
 651         rx_ring->rx_bi = NULL;
 652         return -ENOMEM;
 653 }
 654
 655 /**
 656  * i40e_release_rx_desc - Store the new tail and head values
 657  * @rx_ring: ring to bump
 658  * @val: new head index
 659  **/
 660 static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
 661 {
 662         rx_ring->next_to_use = val;
 663         /* Force memory writes to complete before letting h/w
 664          * know there are new descriptors to fetch.  (Only
 665          * applicable for weak-ordered memory model archs,
 666          * such as IA-64).
 667          */
 668         wmb();
 669         writel(val, rx_ring->tail);
 670 }
 671
 672 /**
 673  * i40evf_alloc_rx_buffers_ps - Replace used receive buffers; packet split
 674  * @rx_ring: ring to place buffers on
 675  * @cleaned_count: number of buffers to replace
 676  *
 677  * Returns true if any errors on allocation
 678  **/
 679 bool i40evf_alloc_rx_buffers_ps(struct i40e_ring *rx_ring, u16 cleaned_count)
 680 {
 681         u16 i = rx_ring->next_to_use;
 682         union i40e_rx_desc *rx_desc;
 683         struct i40e_rx_buffer *bi;
 684         const int current_node = numa_node_id();
 685
 686         /* do nothing if no valid netdev defined */
 687         if (!rx_ring->netdev || !cleaned_count)
 688                 return false;
 689
 690         while (cleaned_count--) {
 691                 rx_desc = I40E_RX_DESC(rx_ring, i);
 692                 bi = &rx_ring->rx_bi[i];
 693
 694                 if (bi->skb) /* desc is in use */
 695                         goto no_buffers;
 696
 697         /* If we've been moved to a different NUMA node, release the
 698          * page so we can get a new one on the current node.
 699          */
 700                 if (bi->page &&  page_to_nid(bi->page) != current_node) {
 701                         dma_unmap_page(rx_ring->dev,
 702                                        bi->page_dma,
 703                                        PAGE_SIZE,
 704                                        DMA_FROM_DEVICE);
 705                         __free_page(bi->page);
 706                         bi->page = NULL;
 707                         bi->page_dma = 0;
 708                         rx_ring->rx_stats.realloc_count++;
 709                 } else if (bi->page) {
 710                         rx_ring->rx_stats.page_reuse_count++;
 711                 }
 712
 713                 if (!bi->page) {
 714                         bi->page = alloc_page(GFP_ATOMIC);
 715                         if (!bi->page) {
 716                                 rx_ring->rx_stats.alloc_page_failed++;
 717                                 goto no_buffers;
 718                         }
 719                         bi->page_dma = dma_map_page(rx_ring->dev,
 720                                                     bi->page,
 721                                                     0,
 722                                                     PAGE_SIZE,
 723                                                     DMA_FROM_DEVICE);
 724                         if (dma_mapping_error(rx_ring->dev, bi->page_dma)) {
 725                                 rx_ring->rx_stats.alloc_page_failed++;
 726                                 __free_page(bi->page);
 727                                 bi->page = NULL;
 728                                 bi->page_dma = 0;
 729                                 bi->page_offset = 0;
 730                                 goto no_buffers;
 731                         }
 732                         bi->page_offset = 0;
 733                 }
 734
 735                 /* Refresh the desc even if buffer_addrs didn't change
 736                  * because each write-back erases this info.
 737                  */
 738                 rx_desc->read.pkt_addr =
 739                                 cpu_to_le64(bi->page_dma + bi->page_offset);
 740                 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
 741                 i++;
 742                 if (i == rx_ring->count)
 743                         i = 0;
 744         }
 745
 746         if (rx_ring->next_to_use != i)
 747                 i40e_release_rx_desc(rx_ring, i);
 748
 749         return false;
 750
 751 no_buffers:
 752         if (rx_ring->next_to_use != i)
 753                 i40e_release_rx_desc(rx_ring, i);
 754
 755         /* make sure to come back via polling to try again after
 756          * allocation failure
 757          */
 758         return true;
 759 }
 760
 761 /**
 762  * i40evf_alloc_rx_buffers_1buf - Replace used receive buffers; single buffer
 763  * @rx_ring: ring to place buffers on
 764  * @cleaned_count: number of buffers to replace
 765  *
 766  * Returns true if any errors on allocation
 767  **/
 768 bool i40evf_alloc_rx_buffers_1buf(struct i40e_ring *rx_ring, u16 cleaned_count)
 769 {
 770         u16 i = rx_ring->next_to_use;
 771         union i40e_rx_desc *rx_desc;
 772         struct i40e_rx_buffer *bi;
 773         struct sk_buff *skb;
 774
 775         /* do nothing if no valid netdev defined */
 776         if (!rx_ring->netdev || !cleaned_count)
 777                 return false;
 778
 779         while (cleaned_count--) {
 780                 rx_desc = I40E_RX_DESC(rx_ring, i);
 781                 bi = &rx_ring->rx_bi[i];
 782                 skb = bi->skb;
 783
 784                 if (!skb) {
 785                         skb = __netdev_alloc_skb_ip_align(rx_ring->netdev,
 786                                                           rx_ring->rx_buf_len,
 787                                                           GFP_ATOMIC |
 788                                                           __GFP_NOWARN);
 789                         if (!skb) {
 790                                 rx_ring->rx_stats.alloc_buff_failed++;
 791                                 goto no_buffers;
 792                         }
 793                         /* initialize queue mapping */
 794                         skb_record_rx_queue(skb, rx_ring->queue_index);
 795                         bi->skb = skb;
 796                 }
 797
 798                 if (!bi->dma) {
 799                         bi->dma = dma_map_single(rx_ring->dev,
 800                                                  skb->data,
 801                                                  rx_ring->rx_buf_len,
 802                                                  DMA_FROM_DEVICE);
 803                         if (dma_mapping_error(rx_ring->dev, bi->dma)) {
 804                                 rx_ring->rx_stats.alloc_buff_failed++;
 805                                 bi->dma = 0;
 806                                 dev_kfree_skb(bi->skb);
 807                                 bi->skb = NULL;
 808                                 goto no_buffers;
 809                         }
 810                 }
 811
 812                 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
 813                 rx_desc->read.hdr_addr = 0;
 814                 i++;
 815                 if (i == rx_ring->count)
 816                         i = 0;
 817         }
 818
 819         if (rx_ring->next_to_use != i)
 820                 i40e_release_rx_desc(rx_ring, i);
 821
 822         return false;
 823
 824 no_buffers:
 825         if (rx_ring->next_to_use != i)
 826                 i40e_release_rx_desc(rx_ring, i);
 827
 828         /* make sure to come back via polling to try again after
 829          * allocation failure
 830          */
 831         return true;
 832 }
 833
 834 /**
 835  * i40e_receive_skb - Send a completed packet up the stack
 836  * @rx_ring:  rx ring in play
 837  * @skb: packet to send up
 838  * @vlan_tag: vlan tag for packet
 839  **/
 840 static void i40e_receive_skb(struct i40e_ring *rx_ring,
 841                              struct sk_buff *skb, u16 vlan_tag)
 842 {
 843         struct i40e_q_vector *q_vector = rx_ring->q_vector;
 844
 845         if (vlan_tag & VLAN_VID_MASK)
 846                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
 847
 848         napi_gro_receive(&q_vector->napi, skb);
 849 }
 850
 851 /**
 852  * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum
 853  * @vsi: the VSI we care about
 854  * @skb: skb currently being received and modified
 855  * @rx_status: status value of last descriptor in packet
 856  * @rx_error: error value of last descriptor in packet
 857  * @rx_ptype: ptype value of last descriptor in packet
 858  **/
 859 static inline void i40e_rx_checksum(struct i40e_vsi *vsi,
 860                                     struct sk_buff *skb,
 861                                     u32 rx_status,
 862                                     u32 rx_error,
 863                                     u16 rx_ptype)
 864 {
 865         struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(rx_ptype);
 866         bool ipv4, ipv6, ipv4_tunnel, ipv6_tunnel;
 867
 868         skb->ip_summed = CHECKSUM_NONE;
 869
 870         /* Rx csum enabled and ip headers found? */
 871         if (!(vsi->netdev->features & NETIF_F_RXCSUM))
 872                 return;
 873
 874         /* did the hardware decode the packet and checksum? */
 875         if (!(rx_status & BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT)))
 876                 return;
 877
 878         /* both known and outer_ip must be set for the below code to work */
 879         if (!(decoded.known && decoded.outer_ip))
 880                 return;
 881
 882         ipv4 = (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP) &&
 883                (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4);
 884         ipv6 = (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP) &&
 885                (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6);
 886
 887         if (ipv4 &&
 888             (rx_error & (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT) |
 889                          BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT))))
 890                 goto checksum_fail;
 891
 892         /* likely incorrect csum if alternate IP extension headers found */
 893         if (ipv6 &&
 894             rx_status & BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT))
 895                 /* don't increment checksum err here, non-fatal err */
 896                 return;
 897
 898         /* there was some L4 error, count error and punt packet to the stack */
 899         if (rx_error & BIT(I40E_RX_DESC_ERROR_L4E_SHIFT))
 900                 goto checksum_fail;
 901
 902         /* handle packets that were not able to be checksummed due
 903          * to arrival speed, in this case the stack can compute
 904          * the csum.
 905          */
 906         if (rx_error & BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT))
 907                 return;
 908
 909         /* The hardware supported by this driver does not validate outer
 910          * checksums for tunneled VXLAN or GENEVE frames.  I don't agree
 911          * with it but the specification states that you "MAY validate", it
 912          * doesn't make it a hard requirement so if we have validated the
 913          * inner checksum report CHECKSUM_UNNECESSARY.
 914          */
 915
 916         ipv4_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT4_MAC_PAY3) &&
 917                      (rx_ptype <= I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4);
 918         ipv6_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT6_MAC_PAY3) &&
 919                      (rx_ptype <= I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4);
 920
 921         skb->ip_summed = CHECKSUM_UNNECESSARY;
 922         skb->csum_level = ipv4_tunnel || ipv6_tunnel;
 923
 924         return;
 925
 926 checksum_fail:
 927         vsi->back->hw_csum_rx_error++;
 928 }
 929
 930 /**
 931  * i40e_ptype_to_htype - get a hash type
 932  * @ptype: the ptype value from the descriptor
 933  *
 934  * Returns a hash type to be used by skb_set_hash
 935  **/
 936 static inline enum pkt_hash_types i40e_ptype_to_htype(u8 ptype)
 937 {
 938         struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype);
 939
 940         if (!decoded.known)
 941                 return PKT_HASH_TYPE_NONE;
 942
 943         if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
 944             decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4)
 945                 return PKT_HASH_TYPE_L4;
 946         else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
 947                  decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3)
 948                 return PKT_HASH_TYPE_L3;
 949         else
 950                 return PKT_HASH_TYPE_L2;
 951 }
 952
 953 /**
 954  * i40e_rx_hash - set the hash value in the skb
 955  * @ring: descriptor ring
 956  * @rx_desc: specific descriptor
 957  **/
 958 static inline void i40e_rx_hash(struct i40e_ring *ring,
 959                                 union i40e_rx_desc *rx_desc,
 960                                 struct sk_buff *skb,
 961                                 u8 rx_ptype)
 962 {
 963         u32 hash;
 964         const __le64 rss_mask  =
 965                 cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH <<
 966                             I40E_RX_DESC_STATUS_FLTSTAT_SHIFT);
 967
 968         if (ring->netdev->features & NETIF_F_RXHASH)
 969                 return;
 970
 971         if ((rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask) {
 972                 hash = le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss);
 973                 skb_set_hash(skb, hash, i40e_ptype_to_htype(rx_ptype));
 974         }
 975 }
 976
 977 /**
 978  * i40e_clean_rx_irq_ps - Reclaim resources after receive; packet split
 979  * @rx_ring:  rx ring to clean
 980  * @budget:   how many cleans we're allowed
 981  *
 982  * Returns true if there's any budget left (e.g. the clean is finished)
 983  **/
 984 static int i40e_clean_rx_irq_ps(struct i40e_ring *rx_ring, const int budget)
 985 {
 986         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
 987         u16 rx_packet_len, rx_header_len, rx_sph, rx_hbo;
 988         u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
 989         struct i40e_vsi *vsi = rx_ring->vsi;
 990         u16 i = rx_ring->next_to_clean;
 991         union i40e_rx_desc *rx_desc;
 992         u32 rx_error, rx_status;
 993         bool failure = false;
 994         u8 rx_ptype;
 995         u64 qword;
 996         u32 copysize;
 997
 998         do {
 999                 struct i40e_rx_buffer *rx_bi;
1000                 struct sk_buff *skb;
1001                 u16 vlan_tag;
1002                 /* return some buffers to hardware, one at a time is too slow */
1003                 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
1004                         failure = failure ||
1005                                   i40evf_alloc_rx_buffers_ps(rx_ring,
1006                                                              cleaned_count);
1007                         cleaned_count = 0;
1008                 }
1009
1010                 i = rx_ring->next_to_clean;
1011                 rx_desc = I40E_RX_DESC(rx_ring, i);
1012                 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1013                 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1014                         I40E_RXD_QW1_STATUS_SHIFT;
1015
1016                 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))
1017                         break;
1018
1019                 /* This memory barrier is needed to keep us from reading
1020                  * any other fields out of the rx_desc until we know the
1021                  * DD bit is set.
1022                  */
1023                 dma_rmb();
1024                 /* sync header buffer for reading */
1025                 dma_sync_single_range_for_cpu(rx_ring->dev,
1026                                               rx_ring->rx_bi[0].dma,
1027                                               i * rx_ring->rx_hdr_len,
1028                                               rx_ring->rx_hdr_len,
1029                                               DMA_FROM_DEVICE);
1030                 rx_bi = &rx_ring->rx_bi[i];
1031                 skb = rx_bi->skb;
1032                 if (likely(!skb)) {
1033                         skb = __netdev_alloc_skb_ip_align(rx_ring->netdev,
1034                                                           rx_ring->rx_hdr_len,
1035                                                           GFP_ATOMIC |
1036                                                           __GFP_NOWARN);
1037                         if (!skb) {
1038                                 rx_ring->rx_stats.alloc_buff_failed++;
1039                                 failure = true;
1040                                 break;
1041                         }
1042
1043                         /* initialize queue mapping */
1044                         skb_record_rx_queue(skb, rx_ring->queue_index);
1045                         /* we are reusing so sync this buffer for CPU use */
1046                         dma_sync_single_range_for_cpu(rx_ring->dev,
1047                                                       rx_ring->rx_bi[0].dma,
1048                                                       i * rx_ring->rx_hdr_len,
1049                                                       rx_ring->rx_hdr_len,
1050                                                       DMA_FROM_DEVICE);
1051                 }
1052                 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1053                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1054                 rx_header_len = (qword & I40E_RXD_QW1_LENGTH_HBUF_MASK) >>
1055                                 I40E_RXD_QW1_LENGTH_HBUF_SHIFT;
1056                 rx_sph = (qword & I40E_RXD_QW1_LENGTH_SPH_MASK) >>
1057                          I40E_RXD_QW1_LENGTH_SPH_SHIFT;
1058
1059                 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1060                            I40E_RXD_QW1_ERROR_SHIFT;
1061                 rx_hbo = rx_error & BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
1062                 rx_error &= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
1063
1064                 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1065                            I40E_RXD_QW1_PTYPE_SHIFT;
1066                 /* sync half-page for reading */
1067                 dma_sync_single_range_for_cpu(rx_ring->dev,
1068                                               rx_bi->page_dma,
1069                                               rx_bi->page_offset,
1070                                               PAGE_SIZE / 2,
1071                                               DMA_FROM_DEVICE);
1072                 prefetch(page_address(rx_bi->page) + rx_bi->page_offset);
1073                 rx_bi->skb = NULL;
1074                 cleaned_count++;
1075                 copysize = 0;
1076                 if (rx_hbo || rx_sph) {
1077                         int len;
1078
1079                         if (rx_hbo)
1080                                 len = I40E_RX_HDR_SIZE;
1081                         else
1082                                 len = rx_header_len;
1083                         memcpy(__skb_put(skb, len), rx_bi->hdr_buf, len);
1084                 } else if (skb->len == 0) {
1085                         int len;
1086                         unsigned char *va = page_address(rx_bi->page) +
1087                                             rx_bi->page_offset;
1088
1089                         len = min(rx_packet_len, rx_ring->rx_hdr_len);
1090                         memcpy(__skb_put(skb, len), va, len);
1091                         copysize = len;
1092                         rx_packet_len -= len;
1093                 }
1094                 /* Get the rest of the data if this was a header split */
1095                 if (rx_packet_len) {
1096                         skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
1097                                         rx_bi->page,
1098                                         rx_bi->page_offset + copysize,
1099                                         rx_packet_len, I40E_RXBUFFER_2048);
1100
1101                         /* If the page count is more than 2, then both halves
1102                          * of the page are used and we need to free it. Do it
1103                          * here instead of in the alloc code. Otherwise one
1104                          * of the half-pages might be released between now and
1105                          * then, and we wouldn't know which one to use.
1106                          * Don't call get_page and free_page since those are
1107                          * both expensive atomic operations that just change
1108                          * the refcount in opposite directions. Just give the
1109                          * page to the stack; he can have our refcount.
1110                          */
1111                         if (page_count(rx_bi->page) > 2) {
1112                                 dma_unmap_page(rx_ring->dev,
1113                                                rx_bi->page_dma,
1114                                                PAGE_SIZE,
1115                                                DMA_FROM_DEVICE);
1116                                 rx_bi->page = NULL;
1117                                 rx_bi->page_dma = 0;
1118                                 rx_ring->rx_stats.realloc_count++;
1119                         } else {
1120                                 get_page(rx_bi->page);
1121                                 /* switch to the other half-page here; the
1122                                  * allocation code programs the right addr
1123                                  * into HW. If we haven't used this half-page,
1124                                  * the address won't be changed, and HW can
1125                                  * just use it next time through.
1126                                  */
1127                                 rx_bi->page_offset ^= PAGE_SIZE / 2;
1128                         }
1129
1130                 }
1131                 I40E_RX_INCREMENT(rx_ring, i);
1132
1133                 if (unlikely(
1134                     !(rx_status & BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
1135                         struct i40e_rx_buffer *next_buffer;
1136
1137                         next_buffer = &rx_ring->rx_bi[i];
1138                         next_buffer->skb = skb;
1139                         rx_ring->rx_stats.non_eop_descs++;
1140                         continue;
1141                 }
1142
1143                 /* ERR_MASK will only have valid bits if EOP set */
1144                 if (unlikely(rx_error & BIT(I40E_RX_DESC_ERROR_RXE_SHIFT))) {
1145                         dev_kfree_skb_any(skb);
1146                         continue;
1147                 }
1148
1149                 i40e_rx_hash(rx_ring, rx_desc, skb, rx_ptype);
1150
1151                 /* probably a little skewed due to removing CRC */
1152                 total_rx_bytes += skb->len;
1153                 total_rx_packets++;
1154
1155                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1156
1157                 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1158
1159                 vlan_tag = rx_status & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
1160                          ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1161                          : 0;
1162 #ifdef I40E_FCOE
1163                 if (unlikely(
1164                     i40e_rx_is_fcoe(rx_ptype) &&
1165                     !i40e_fcoe_handle_offload(rx_ring, rx_desc, skb))) {
1166                         dev_kfree_skb_any(skb);
1167                         continue;
1168                 }
1169 #endif
1170                 i40e_receive_skb(rx_ring, skb, vlan_tag);
1171
1172                 rx_desc->wb.qword1.status_error_len = 0;
1173
1174         } while (likely(total_rx_packets < budget));
1175
1176         u64_stats_update_begin(&rx_ring->syncp);
1177         rx_ring->stats.packets += total_rx_packets;
1178         rx_ring->stats.bytes += total_rx_bytes;
1179         u64_stats_update_end(&rx_ring->syncp);
1180         rx_ring->q_vector->rx.total_packets += total_rx_packets;
1181         rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1182
1183         return failure ? budget : total_rx_packets;
1184 }
1185
1186 /**
1187  * i40e_clean_rx_irq_1buf - Reclaim resources after receive; single buffer
1188  * @rx_ring:  rx ring to clean
1189  * @budget:   how many cleans we're allowed
1190  *
1191  * Returns number of packets cleaned
1192  **/
1193 static int i40e_clean_rx_irq_1buf(struct i40e_ring *rx_ring, int budget)
1194 {
1195         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1196         u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
1197         struct i40e_vsi *vsi = rx_ring->vsi;
1198         union i40e_rx_desc *rx_desc;
1199         u32 rx_error, rx_status;
1200         u16 rx_packet_len;
1201         bool failure = false;
1202         u8 rx_ptype;
1203         u64 qword;
1204         u16 i;
1205
1206         do {
1207                 struct i40e_rx_buffer *rx_bi;
1208                 struct sk_buff *skb;
1209                 u16 vlan_tag;
1210                 /* return some buffers to hardware, one at a time is too slow */
1211                 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
1212                         failure = failure ||
1213                                   i40evf_alloc_rx_buffers_1buf(rx_ring,
1214                                                                cleaned_count);
1215                         cleaned_count = 0;
1216                 }
1217
1218                 i = rx_ring->next_to_clean;
1219                 rx_desc = I40E_RX_DESC(rx_ring, i);
1220                 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1221                 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1222                         I40E_RXD_QW1_STATUS_SHIFT;
1223
1224                 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))
1225                         break;
1226
1227                 /* This memory barrier is needed to keep us from reading
1228                  * any other fields out of the rx_desc until we know the
1229                  * DD bit is set.
1230                  */
1231                 dma_rmb();
1232
1233                 rx_bi = &rx_ring->rx_bi[i];
1234                 skb = rx_bi->skb;
1235                 prefetch(skb->data);
1236
1237                 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1238                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1239
1240                 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1241                            I40E_RXD_QW1_ERROR_SHIFT;
1242                 rx_error &= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
1243
1244                 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1245                            I40E_RXD_QW1_PTYPE_SHIFT;
1246                 rx_bi->skb = NULL;
1247                 cleaned_count++;
1248
1249                 /* Get the header and possibly the whole packet
1250                  * If this is an skb from previous receive dma will be 0
1251                  */
1252                 skb_put(skb, rx_packet_len);
1253                 dma_unmap_single(rx_ring->dev, rx_bi->dma, rx_ring->rx_buf_len,
1254                                  DMA_FROM_DEVICE);
1255                 rx_bi->dma = 0;
1256
1257                 I40E_RX_INCREMENT(rx_ring, i);
1258
1259                 if (unlikely(
1260                     !(rx_status & BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
1261                         rx_ring->rx_stats.non_eop_descs++;
1262                         continue;
1263                 }
1264
1265                 /* ERR_MASK will only have valid bits if EOP set */
1266                 if (unlikely(rx_error & BIT(I40E_RX_DESC_ERROR_RXE_SHIFT))) {
1267                         dev_kfree_skb_any(skb);
1268                         continue;
1269                 }
1270
1271                 i40e_rx_hash(rx_ring, rx_desc, skb, rx_ptype);
1272                 /* probably a little skewed due to removing CRC */
1273                 total_rx_bytes += skb->len;
1274                 total_rx_packets++;
1275
1276                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1277
1278                 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1279
1280                 vlan_tag = rx_status & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
1281                          ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1282                          : 0;
1283                 i40e_receive_skb(rx_ring, skb, vlan_tag);
1284
1285                 rx_desc->wb.qword1.status_error_len = 0;
1286         } while (likely(total_rx_packets < budget));
1287
1288         u64_stats_update_begin(&rx_ring->syncp);
1289         rx_ring->stats.packets += total_rx_packets;
1290         rx_ring->stats.bytes += total_rx_bytes;
1291         u64_stats_update_end(&rx_ring->syncp);
1292         rx_ring->q_vector->rx.total_packets += total_rx_packets;
1293         rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1294
1295         return failure ? budget : total_rx_packets;
1296 }
1297
1298 static u32 i40e_buildreg_itr(const int type, const u16 itr)
1299 {
1300         u32 val;
1301
1302         val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1303               /* Don't clear PBA because that can cause lost interrupts that
1304                * came in while we were cleaning/polling
1305                */
1306               (type << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1307               (itr << I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT);
1308
1309         return val;
1310 }
1311
1312 /* a small macro to shorten up some long lines */
1313 #define INTREG I40E_VFINT_DYN_CTLN1
1314
1315 /**
1316  * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt
1317  * @vsi: the VSI we care about
1318  * @q_vector: q_vector for which itr is being updated and interrupt enabled
1319  *
1320  **/
1321 static inline void i40e_update_enable_itr(struct i40e_vsi *vsi,
1322                                           struct i40e_q_vector *q_vector)
1323 {
1324         struct i40e_hw *hw = &vsi->back->hw;
1325         bool rx = false, tx = false;
1326         u32 rxval, txval;
1327         int vector;
1328
1329         vector = (q_vector->v_idx + vsi->base_vector);
1330
1331         /* avoid dynamic calculation if in countdown mode OR if
1332          * all dynamic is disabled
1333          */
1334         rxval = txval = i40e_buildreg_itr(I40E_ITR_NONE, 0);
1335
1336         if (q_vector->itr_countdown > 0 ||
1337             (!ITR_IS_DYNAMIC(vsi->rx_itr_setting) &&
1338              !ITR_IS_DYNAMIC(vsi->tx_itr_setting))) {
1339                 goto enable_int;
1340         }
1341
1342         if (ITR_IS_DYNAMIC(vsi->rx_itr_setting)) {
1343                 rx = i40e_set_new_dynamic_itr(&q_vector->rx);
1344                 rxval = i40e_buildreg_itr(I40E_RX_ITR, q_vector->rx.itr);
1345         }
1346
1347         if (ITR_IS_DYNAMIC(vsi->tx_itr_setting)) {
1348                 tx = i40e_set_new_dynamic_itr(&q_vector->tx);
1349                 txval = i40e_buildreg_itr(I40E_TX_ITR, q_vector->tx.itr);
1350         }
1351
1352         if (rx || tx) {
1353                 /* get the higher of the two ITR adjustments and
1354                  * use the same value for both ITR registers
1355                  * when in adaptive mode (Rx and/or Tx)
1356                  */
1357                 u16 itr = max(q_vector->tx.itr, q_vector->rx.itr);
1358
1359                 q_vector->tx.itr = q_vector->rx.itr = itr;
1360                 txval = i40e_buildreg_itr(I40E_TX_ITR, itr);
1361                 tx = true;
1362                 rxval = i40e_buildreg_itr(I40E_RX_ITR, itr);
1363                 rx = true;
1364         }
1365
1366         /* only need to enable the interrupt once, but need
1367          * to possibly update both ITR values
1368          */
1369         if (rx) {
1370                 /* set the INTENA_MSK_MASK so that this first write
1371                  * won't actually enable the interrupt, instead just
1372                  * updating the ITR (it's bit 31 PF and VF)
1373                  */
1374                 rxval |= BIT(31);
1375                 /* don't check _DOWN because interrupt isn't being enabled */
1376                 wr32(hw, INTREG(vector - 1), rxval);
1377         }
1378
1379 enable_int:
1380         if (!test_bit(__I40E_DOWN, &vsi->state))
1381                 wr32(hw, INTREG(vector - 1), txval);
1382
1383         if (q_vector->itr_countdown)
1384                 q_vector->itr_countdown--;
1385         else
1386                 q_vector->itr_countdown = ITR_COUNTDOWN_START;
1387 }
1388
1389 /**
1390  * i40evf_napi_poll - NAPI polling Rx/Tx cleanup routine
1391  * @napi: napi struct with our devices info in it
1392  * @budget: amount of work driver is allowed to do this pass, in packets
1393  *
1394  * This function will clean all queues associated with a q_vector.
1395  *
1396  * Returns the amount of work done
1397  **/
1398 int i40evf_napi_poll(struct napi_struct *napi, int budget)
1399 {
1400         struct i40e_q_vector *q_vector =
1401                                container_of(napi, struct i40e_q_vector, napi);
1402         struct i40e_vsi *vsi = q_vector->vsi;
1403         struct i40e_ring *ring;
1404         bool clean_complete = true;
1405         bool arm_wb = false;
1406         int budget_per_ring;
1407         int work_done = 0;
1408
1409         if (test_bit(__I40E_DOWN, &vsi->state)) {
1410                 napi_complete(napi);
1411                 return 0;
1412         }
1413
1414         /* Since the actual Tx work is minimal, we can give the Tx a larger
1415          * budget and be more aggressive about cleaning up the Tx descriptors.
1416          */
1417         i40e_for_each_ring(ring, q_vector->tx) {
1418                 if (!i40e_clean_tx_irq(vsi, ring, budget)) {
1419                         clean_complete = false;
1420                         continue;
1421                 }
1422                 arm_wb |= ring->arm_wb;
1423                 ring->arm_wb = false;
1424         }
1425
1426         /* Handle case where we are called by netpoll with a budget of 0 */
1427         if (budget <= 0)
1428                 goto tx_only;
1429
1430         /* We attempt to distribute budget to each Rx queue fairly, but don't
1431          * allow the budget to go below 1 because that would exit polling early.
1432          */
1433         budget_per_ring = max(budget/q_vector->num_ringpairs, 1);
1434
1435         i40e_for_each_ring(ring, q_vector->rx) {
1436                 int cleaned;
1437
1438                 if (ring_is_ps_enabled(ring))
1439                         cleaned = i40e_clean_rx_irq_ps(ring, budget_per_ring);
1440                 else
1441                         cleaned = i40e_clean_rx_irq_1buf(ring, budget_per_ring);
1442
1443                 work_done += cleaned;
1444                 /* if we clean as many as budgeted, we must not be done */
1445                 if (cleaned >= budget_per_ring)
1446                         clean_complete = false;
1447         }
1448
1449         /* If work not completed, return budget and polling will return */
1450         if (!clean_complete) {
1451 tx_only:
1452                 if (arm_wb) {
1453                         q_vector->tx.ring[0].tx_stats.tx_force_wb++;
1454                         i40e_enable_wb_on_itr(vsi, q_vector);
1455                 }
1456                 return budget;
1457         }
1458
1459         if (vsi->back->flags & I40E_TXR_FLAGS_WB_ON_ITR)
1460                 q_vector->arm_wb_state = false;
1461
1462         /* Work is done so exit the polling mode and re-enable the interrupt */
1463         napi_complete_done(napi, work_done);
1464         i40e_update_enable_itr(vsi, q_vector);
1465         return 0;
1466 }
1467
1468 /**
1469  * i40evf_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
1470  * @skb:     send buffer
1471  * @tx_ring: ring to send buffer on
1472  * @flags:   the tx flags to be set
1473  *
1474  * Checks the skb and set up correspondingly several generic transmit flags
1475  * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
1476  *
1477  * Returns error code indicate the frame should be dropped upon error and the
1478  * otherwise  returns 0 to indicate the flags has been set properly.
1479  **/
1480 static inline int i40evf_tx_prepare_vlan_flags(struct sk_buff *skb,
1481                                                struct i40e_ring *tx_ring,
1482                                                u32 *flags)
1483 {
1484         __be16 protocol = skb->protocol;
1485         u32  tx_flags = 0;
1486
1487         if (protocol == htons(ETH_P_8021Q) &&
1488             !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
1489                 /* When HW VLAN acceleration is turned off by the user the
1490                  * stack sets the protocol to 8021q so that the driver
1491                  * can take any steps required to support the SW only
1492                  * VLAN handling.  In our case the driver doesn't need
1493                  * to take any further steps so just set the protocol
1494                  * to the encapsulated ethertype.
1495                  */
1496                 skb->protocol = vlan_get_protocol(skb);
1497                 goto out;
1498         }
1499
1500         /* if we have a HW VLAN tag being added, default to the HW one */
1501         if (skb_vlan_tag_present(skb)) {
1502                 tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT;
1503                 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
1504         /* else if it is a SW VLAN, check the next protocol and store the tag */
1505         } else if (protocol == htons(ETH_P_8021Q)) {
1506                 struct vlan_hdr *vhdr, _vhdr;
1507
1508                 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
1509                 if (!vhdr)
1510                         return -EINVAL;
1511
1512                 protocol = vhdr->h_vlan_encapsulated_proto;
1513                 tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT;
1514                 tx_flags |= I40E_TX_FLAGS_SW_VLAN;
1515         }
1516
1517 out:
1518         *flags = tx_flags;
1519         return 0;
1520 }
1521
1522 /**
1523  * i40e_tso - set up the tso context descriptor
1524  * @skb:      ptr to the skb we're sending
1525  * @hdr_len:  ptr to the size of the packet header
1526  * @cd_type_cmd_tso_mss: Quad Word 1
1527  *
1528  * Returns 0 if no TSO can happen, 1 if tso is going, or error
1529  **/
1530 static int i40e_tso(struct sk_buff *skb, u8 *hdr_len, u64 *cd_type_cmd_tso_mss)
1531 {
1532         u64 cd_cmd, cd_tso_len, cd_mss;
1533         union {
1534                 struct iphdr *v4;
1535                 struct ipv6hdr *v6;
1536                 unsigned char *hdr;
1537         } ip;
1538         union {
1539                 struct tcphdr *tcp;
1540                 struct udphdr *udp;
1541                 unsigned char *hdr;
1542         } l4;
1543         u32 paylen, l4_offset;
1544         int err;
1545
1546         if (skb->ip_summed != CHECKSUM_PARTIAL)
1547                 return 0;
1548
1549         if (!skb_is_gso(skb))
1550                 return 0;
1551
1552         err = skb_cow_head(skb, 0);
1553         if (err < 0)
1554                 return err;
1555
1556         ip.hdr = skb_network_header(skb);
1557         l4.hdr = skb_transport_header(skb);
1558
1559         /* initialize outer IP header fields */
1560         if (ip.v4->version == 4) {
1561                 ip.v4->tot_len = 0;
1562                 ip.v4->check = 0;
1563         } else {
1564                 ip.v6->payload_len = 0;
1565         }
1566
1567         if (skb_shinfo(skb)->gso_type & (SKB_GSO_UDP_TUNNEL | SKB_GSO_GRE |
1568                                          SKB_GSO_UDP_TUNNEL_CSUM)) {
1569                 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM) {
1570                         /* determine offset of outer transport header */
1571                         l4_offset = l4.hdr - skb->data;
1572
1573                         /* remove payload length from outer checksum */
1574                         paylen = skb->len - l4_offset;
1575                         csum_replace_by_diff(&l4.udp->check, htonl(paylen));
1576                 }
1577
1578                 /* reset pointers to inner headers */
1579                 ip.hdr = skb_inner_network_header(skb);
1580                 l4.hdr = skb_inner_transport_header(skb);
1581
1582                 /* initialize inner IP header fields */
1583                 if (ip.v4->version == 4) {
1584                         ip.v4->tot_len = 0;
1585                         ip.v4->check = 0;
1586                 } else {
1587                         ip.v6->payload_len = 0;
1588                 }
1589         }
1590
1591         /* determine offset of inner transport header */
1592         l4_offset = l4.hdr - skb->data;
1593
1594         /* remove payload length from inner checksum */
1595         paylen = skb->len - l4_offset;
1596         csum_replace_by_diff(&l4.tcp->check, htonl(paylen));
1597
1598         /* compute length of segmentation header */
1599         *hdr_len = (l4.tcp->doff * 4) + l4_offset;
1600
1601         /* find the field values */
1602         cd_cmd = I40E_TX_CTX_DESC_TSO;
1603         cd_tso_len = skb->len - *hdr_len;
1604         cd_mss = skb_shinfo(skb)->gso_size;
1605         *cd_type_cmd_tso_mss |= (cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1606                                 (cd_tso_len << I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1607                                 (cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT);
1608         return 1;
1609 }
1610
1611 /**
1612  * i40e_tx_enable_csum - Enable Tx checksum offloads
1613  * @skb: send buffer
1614  * @tx_flags: pointer to Tx flags currently set
1615  * @td_cmd: Tx descriptor command bits to set
1616  * @td_offset: Tx descriptor header offsets to set
1617  * @tx_ring: Tx descriptor ring
1618  * @cd_tunneling: ptr to context desc bits
1619  **/
1620 static int i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags,
1621                                u32 *td_cmd, u32 *td_offset,
1622                                struct i40e_ring *tx_ring,
1623                                u32 *cd_tunneling)
1624 {
1625         union {
1626                 struct iphdr *v4;
1627                 struct ipv6hdr *v6;
1628                 unsigned char *hdr;
1629         } ip;
1630         union {
1631                 struct tcphdr *tcp;
1632                 struct udphdr *udp;
1633                 unsigned char *hdr;
1634         } l4;
1635         unsigned char *exthdr;
1636         u32 offset, cmd = 0;
1637         __be16 frag_off;
1638         u8 l4_proto = 0;
1639
1640         if (skb->ip_summed != CHECKSUM_PARTIAL)
1641                 return 0;
1642
1643         ip.hdr = skb_network_header(skb);
1644         l4.hdr = skb_transport_header(skb);
1645
1646         /* compute outer L2 header size */
1647         offset = ((ip.hdr - skb->data) / 2) << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
1648
1649         if (skb->encapsulation) {
1650                 u32 tunnel = 0;
1651                 /* define outer network header type */
1652                 if (*tx_flags & I40E_TX_FLAGS_IPV4) {
1653                         tunnel |= (*tx_flags & I40E_TX_FLAGS_TSO) ?
1654                                   I40E_TX_CTX_EXT_IP_IPV4 :
1655                                   I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
1656
1657                         l4_proto = ip.v4->protocol;
1658                 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
1659                         tunnel |= I40E_TX_CTX_EXT_IP_IPV6;
1660
1661                         exthdr = ip.hdr + sizeof(*ip.v6);
1662                         l4_proto = ip.v6->nexthdr;
1663                         if (l4.hdr != exthdr)
1664                                 ipv6_skip_exthdr(skb, exthdr - skb->data,
1665                                                  &l4_proto, &frag_off);
1666                 }
1667
1668                 /* compute outer L3 header size */
1669                 tunnel |= ((l4.hdr - ip.hdr) / 4) <<
1670                           I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT;
1671
1672                 /* switch IP header pointer from outer to inner header */
1673                 ip.hdr = skb_inner_network_header(skb);
1674
1675                 /* define outer transport */
1676                 switch (l4_proto) {
1677                 case IPPROTO_UDP:
1678                         tunnel |= I40E_TXD_CTX_UDP_TUNNELING;
1679                         *tx_flags |= I40E_TX_FLAGS_VXLAN_TUNNEL;
1680                         break;
1681                 case IPPROTO_GRE:
1682                         tunnel |= I40E_TXD_CTX_GRE_TUNNELING;
1683                         *tx_flags |= I40E_TX_FLAGS_VXLAN_TUNNEL;
1684                         break;
1685                 default:
1686                         if (*tx_flags & I40E_TX_FLAGS_TSO)
1687                                 return -1;
1688
1689                         skb_checksum_help(skb);
1690                         return 0;
1691                 }
1692
1693                 /* compute tunnel header size */
1694                 tunnel |= ((ip.hdr - l4.hdr) / 2) <<
1695                           I40E_TXD_CTX_QW0_NATLEN_SHIFT;
1696
1697                 /* indicate if we need to offload outer UDP header */
1698                 if ((*tx_flags & I40E_TX_FLAGS_TSO) &&
1699                     (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM))
1700                         tunnel |= I40E_TXD_CTX_QW0_L4T_CS_MASK;
1701
1702                 /* record tunnel offload values */
1703                 *cd_tunneling |= tunnel;
1704
1705                 /* switch L4 header pointer from outer to inner */
1706                 l4.hdr = skb_inner_transport_header(skb);
1707                 l4_proto = 0;
1708
1709                 /* reset type as we transition from outer to inner headers */
1710                 *tx_flags &= ~(I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6);
1711                 if (ip.v4->version == 4)
1712                         *tx_flags |= I40E_TX_FLAGS_IPV4;
1713                 if (ip.v6->version == 6)
1714                         *tx_flags |= I40E_TX_FLAGS_IPV6;
1715         }
1716
1717         /* Enable IP checksum offloads */
1718         if (*tx_flags & I40E_TX_FLAGS_IPV4) {
1719                 l4_proto = ip.v4->protocol;
1720                 /* the stack computes the IP header already, the only time we
1721                  * need the hardware to recompute it is in the case of TSO.
1722                  */
1723                 cmd |= (*tx_flags & I40E_TX_FLAGS_TSO) ?
1724                        I40E_TX_DESC_CMD_IIPT_IPV4_CSUM :
1725                        I40E_TX_DESC_CMD_IIPT_IPV4;
1726         } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
1727                 cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
1728
1729                 exthdr = ip.hdr + sizeof(*ip.v6);
1730                 l4_proto = ip.v6->nexthdr;
1731                 if (l4.hdr != exthdr)
1732                         ipv6_skip_exthdr(skb, exthdr - skb->data,
1733                                          &l4_proto, &frag_off);
1734         }
1735
1736         /* compute inner L3 header size */
1737         offset |= ((l4.hdr - ip.hdr) / 4) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1738
1739         /* Enable L4 checksum offloads */
1740         switch (l4_proto) {
1741         case IPPROTO_TCP:
1742                 /* enable checksum offloads */
1743                 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
1744                 offset |= l4.tcp->doff << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1745                 break;
1746         case IPPROTO_SCTP:
1747                 /* enable SCTP checksum offload */
1748                 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
1749                 offset |= (sizeof(struct sctphdr) >> 2) <<
1750                           I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1751                 break;
1752         case IPPROTO_UDP:
1753                 /* enable UDP checksum offload */
1754                 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
1755                 offset |= (sizeof(struct udphdr) >> 2) <<
1756                           I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1757                 break;
1758         default:
1759                 if (*tx_flags & I40E_TX_FLAGS_TSO)
1760                         return -1;
1761                 skb_checksum_help(skb);
1762                 return 0;
1763         }
1764
1765         *td_cmd |= cmd;
1766         *td_offset |= offset;
1767
1768         return 1;
1769 }
1770
1771 /**
1772  * i40e_create_tx_ctx Build the Tx context descriptor
1773  * @tx_ring:  ring to create the descriptor on
1774  * @cd_type_cmd_tso_mss: Quad Word 1
1775  * @cd_tunneling: Quad Word 0 - bits 0-31
1776  * @cd_l2tag2: Quad Word 0 - bits 32-63
1777  **/
1778 static void i40e_create_tx_ctx(struct i40e_ring *tx_ring,
1779                                const u64 cd_type_cmd_tso_mss,
1780                                const u32 cd_tunneling, const u32 cd_l2tag2)
1781 {
1782         struct i40e_tx_context_desc *context_desc;
1783         int i = tx_ring->next_to_use;
1784
1785         if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) &&
1786             !cd_tunneling && !cd_l2tag2)
1787                 return;
1788
1789         /* grab the next descriptor */
1790         context_desc = I40E_TX_CTXTDESC(tx_ring, i);
1791
1792         i++;
1793         tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
1794
1795         /* cpu_to_le32 and assign to struct fields */
1796         context_desc->tunneling_params = cpu_to_le32(cd_tunneling);
1797         context_desc->l2tag2 = cpu_to_le16(cd_l2tag2);
1798         context_desc->rsvd = cpu_to_le16(0);
1799         context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss);
1800 }
1801
1802 /**
1803  * __i40evf_chk_linearize - Check if there are more than 8 buffers per packet
1804  * @skb:      send buffer
1805  *
1806  * Note: Our HW can't DMA more than 8 buffers to build a packet on the wire
1807  * and so we need to figure out the cases where we need to linearize the skb.
1808  *
1809  * For TSO we need to count the TSO header and segment payload separately.
1810  * As such we need to check cases where we have 7 fragments or more as we
1811  * can potentially require 9 DMA transactions, 1 for the TSO header, 1 for
1812  * the segment payload in the first descriptor, and another 7 for the
1813  * fragments.
1814  **/
1815 bool __i40evf_chk_linearize(struct sk_buff *skb)
1816 {
1817         const struct skb_frag_struct *frag, *stale;
1818         int nr_frags, sum;
1819
1820         /* no need to check if number of frags is less than 7 */
1821         nr_frags = skb_shinfo(skb)->nr_frags;
1822         if (nr_frags < (I40E_MAX_BUFFER_TXD - 1))
1823                 return false;
1824
1825         /* We need to walk through the list and validate that each group
1826          * of 6 fragments totals at least gso_size.  However we don't need
1827          * to perform such validation on the last 6 since the last 6 cannot
1828          * inherit any data from a descriptor after them.
1829          */
1830         nr_frags -= I40E_MAX_BUFFER_TXD - 2;
1831         frag = &skb_shinfo(skb)->frags[0];
1832
1833         /* Initialize size to the negative value of gso_size minus 1.  We
1834          * use this as the worst case scenerio in which the frag ahead
1835          * of us only provides one byte which is why we are limited to 6
1836          * descriptors for a single transmit as the header and previous
1837          * fragment are already consuming 2 descriptors.
1838          */
1839         sum = 1 - skb_shinfo(skb)->gso_size;
1840
1841         /* Add size of frags 0 through 4 to create our initial sum */
1842         sum += skb_frag_size(frag++);
1843         sum += skb_frag_size(frag++);
1844         sum += skb_frag_size(frag++);
1845         sum += skb_frag_size(frag++);
1846         sum += skb_frag_size(frag++);
1847
1848         /* Walk through fragments adding latest fragment, testing it, and
1849          * then removing stale fragments from the sum.
1850          */
1851         stale = &skb_shinfo(skb)->frags[0];
1852         for (;;) {
1853                 sum += skb_frag_size(frag++);
1854
1855                 /* if sum is negative we failed to make sufficient progress */
1856                 if (sum < 0)
1857                         return true;
1858
1859                 /* use pre-decrement to avoid processing last fragment */
1860                 if (!--nr_frags)
1861                         break;
1862
1863                 sum -= skb_frag_size(stale++);
1864         }
1865
1866         return false;
1867 }
1868
1869 /**
1870  * __i40evf_maybe_stop_tx - 2nd level check for tx stop conditions
1871  * @tx_ring: the ring to be checked
1872  * @size:    the size buffer we want to assure is available
1873  *
1874  * Returns -EBUSY if a stop is needed, else 0
1875  **/
1876 int __i40evf_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
1877 {
1878         netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1879         /* Memory barrier before checking head and tail */
1880         smp_mb();
1881
1882         /* Check again in a case another CPU has just made room available. */
1883         if (likely(I40E_DESC_UNUSED(tx_ring) < size))
1884                 return -EBUSY;
1885
1886         /* A reprieve! - use start_queue because it doesn't call schedule */
1887         netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
1888         ++tx_ring->tx_stats.restart_queue;
1889         return 0;
1890 }
1891
1892 /**
1893  * i40evf_tx_map - Build the Tx descriptor
1894  * @tx_ring:  ring to send buffer on
1895  * @skb:      send buffer
1896  * @first:    first buffer info buffer to use
1897  * @tx_flags: collected send information
1898  * @hdr_len:  size of the packet header
1899  * @td_cmd:   the command field in the descriptor
1900  * @td_offset: offset for checksum or crc
1901  **/
1902 static inline void i40evf_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
1903                                  struct i40e_tx_buffer *first, u32 tx_flags,
1904                                  const u8 hdr_len, u32 td_cmd, u32 td_offset)
1905 {
1906         unsigned int data_len = skb->data_len;
1907         unsigned int size = skb_headlen(skb);
1908         struct skb_frag_struct *frag;
1909         struct i40e_tx_buffer *tx_bi;
1910         struct i40e_tx_desc *tx_desc;
1911         u16 i = tx_ring->next_to_use;
1912         u32 td_tag = 0;
1913         dma_addr_t dma;
1914         u16 gso_segs;
1915         u16 desc_count = 0;
1916         bool tail_bump = true;
1917         bool do_rs = false;
1918
1919         if (tx_flags & I40E_TX_FLAGS_HW_VLAN) {
1920                 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1921                 td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >>
1922                          I40E_TX_FLAGS_VLAN_SHIFT;
1923         }
1924
1925         if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO))
1926                 gso_segs = skb_shinfo(skb)->gso_segs;
1927         else
1928                 gso_segs = 1;
1929
1930         /* multiply data chunks by size of headers */
1931         first->bytecount = skb->len - hdr_len + (gso_segs * hdr_len);
1932         first->gso_segs = gso_segs;
1933         first->skb = skb;
1934         first->tx_flags = tx_flags;
1935
1936         dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
1937
1938         tx_desc = I40E_TX_DESC(tx_ring, i);
1939         tx_bi = first;
1940
1941         for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
1942                 unsigned int max_data = I40E_MAX_DATA_PER_TXD_ALIGNED;
1943
1944                 if (dma_mapping_error(tx_ring->dev, dma))
1945                         goto dma_error;
1946
1947                 /* record length, and DMA address */
1948                 dma_unmap_len_set(tx_bi, len, size);
1949                 dma_unmap_addr_set(tx_bi, dma, dma);
1950
1951                 /* align size to end of page */
1952                 max_data += -dma & (I40E_MAX_READ_REQ_SIZE - 1);
1953                 tx_desc->buffer_addr = cpu_to_le64(dma);
1954
1955                 while (unlikely(size > I40E_MAX_DATA_PER_TXD)) {
1956                         tx_desc->cmd_type_offset_bsz =
1957                                 build_ctob(td_cmd, td_offset,
1958                                            max_data, td_tag);
1959
1960                         tx_desc++;
1961                         i++;
1962                         desc_count++;
1963
1964                         if (i == tx_ring->count) {
1965                                 tx_desc = I40E_TX_DESC(tx_ring, 0);
1966                                 i = 0;
1967                         }
1968
1969                         dma += max_data;
1970                         size -= max_data;
1971
1972                         max_data = I40E_MAX_DATA_PER_TXD_ALIGNED;
1973                         tx_desc->buffer_addr = cpu_to_le64(dma);
1974                 }
1975
1976                 if (likely(!data_len))
1977                         break;
1978
1979                 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset,
1980                                                           size, td_tag);
1981
1982                 tx_desc++;
1983                 i++;
1984                 desc_count++;
1985
1986                 if (i == tx_ring->count) {
1987                         tx_desc = I40E_TX_DESC(tx_ring, 0);
1988                         i = 0;
1989                 }
1990
1991                 size = skb_frag_size(frag);
1992                 data_len -= size;
1993
1994                 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
1995                                        DMA_TO_DEVICE);
1996
1997                 tx_bi = &tx_ring->tx_bi[i];
1998         }
1999
2000         /* set next_to_watch value indicating a packet is present */
2001         first->next_to_watch = tx_desc;
2002
2003         i++;
2004         if (i == tx_ring->count)
2005                 i = 0;
2006
2007         tx_ring->next_to_use = i;
2008
2009         netdev_tx_sent_queue(netdev_get_tx_queue(tx_ring->netdev,
2010                                                  tx_ring->queue_index),
2011                                                  first->bytecount);
2012         i40e_maybe_stop_tx(tx_ring, DESC_NEEDED);
2013
2014         /* Algorithm to optimize tail and RS bit setting:
2015          * if xmit_more is supported
2016          *      if xmit_more is true
2017          *              do not update tail and do not mark RS bit.
2018          *      if xmit_more is false and last xmit_more was false
2019          *              if every packet spanned less than 4 desc
2020          *                      then set RS bit on 4th packet and update tail
2021          *                      on every packet
2022          *              else
2023          *                      update tail and set RS bit on every packet.
2024          *      if xmit_more is false and last_xmit_more was true
2025          *              update tail and set RS bit.
2026          *
2027          * Optimization: wmb to be issued only in case of tail update.
2028          * Also optimize the Descriptor WB path for RS bit with the same
2029          * algorithm.
2030          *
2031          * Note: If there are less than 4 packets
2032          * pending and interrupts were disabled the service task will
2033          * trigger a force WB.
2034          */
2035         if (skb->xmit_more  &&
2036             !netif_xmit_stopped(netdev_get_tx_queue(tx_ring->netdev,
2037                                                     tx_ring->queue_index))) {
2038                 tx_ring->flags |= I40E_TXR_FLAGS_LAST_XMIT_MORE_SET;
2039                 tail_bump = false;
2040         } else if (!skb->xmit_more &&
2041                    !netif_xmit_stopped(netdev_get_tx_queue(tx_ring->netdev,
2042                                                        tx_ring->queue_index)) &&
2043                    (!(tx_ring->flags & I40E_TXR_FLAGS_LAST_XMIT_MORE_SET)) &&
2044                    (tx_ring->packet_stride < WB_STRIDE) &&
2045                    (desc_count < WB_STRIDE)) {
2046                 tx_ring->packet_stride++;
2047         } else {
2048                 tx_ring->packet_stride = 0;
2049                 tx_ring->flags &= ~I40E_TXR_FLAGS_LAST_XMIT_MORE_SET;
2050                 do_rs = true;
2051         }
2052         if (do_rs)
2053                 tx_ring->packet_stride = 0;
2054
2055         tx_desc->cmd_type_offset_bsz =
2056                         build_ctob(td_cmd, td_offset, size, td_tag) |
2057                         cpu_to_le64((u64)(do_rs ? I40E_TXD_CMD :
2058                                                   I40E_TX_DESC_CMD_EOP) <<
2059                                                   I40E_TXD_QW1_CMD_SHIFT);
2060
2061         /* notify HW of packet */
2062         if (!tail_bump)
2063                 prefetchw(tx_desc + 1);
2064
2065         if (tail_bump) {
2066                 /* Force memory writes to complete before letting h/w
2067                  * know there are new descriptors to fetch.  (Only
2068                  * applicable for weak-ordered memory model archs,
2069                  * such as IA-64).
2070                  */
2071                 wmb();
2072                 writel(i, tx_ring->tail);
2073         }
2074
2075         return;
2076
2077 dma_error:
2078         dev_info(tx_ring->dev, "TX DMA map failed\n");
2079
2080         /* clear dma mappings for failed tx_bi map */
2081         for (;;) {
2082                 tx_bi = &tx_ring->tx_bi[i];
2083                 i40e_unmap_and_free_tx_resource(tx_ring, tx_bi);
2084                 if (tx_bi == first)
2085                         break;
2086                 if (i == 0)
2087                         i = tx_ring->count;
2088                 i--;
2089         }
2090
2091         tx_ring->next_to_use = i;
2092 }
2093
2094 /**
2095  * i40e_xmit_frame_ring - Sends buffer on Tx ring
2096  * @skb:     send buffer
2097  * @tx_ring: ring to send buffer on
2098  *
2099  * Returns NETDEV_TX_OK if sent, else an error code
2100  **/
2101 static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb,
2102                                         struct i40e_ring *tx_ring)
2103 {
2104         u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT;
2105         u32 cd_tunneling = 0, cd_l2tag2 = 0;
2106         struct i40e_tx_buffer *first;
2107         u32 td_offset = 0;
2108         u32 tx_flags = 0;
2109         __be16 protocol;
2110         u32 td_cmd = 0;
2111         u8 hdr_len = 0;
2112         int tso, count;
2113
2114         /* prefetch the data, we'll need it later */
2115         prefetch(skb->data);
2116
2117         count = i40e_xmit_descriptor_count(skb);
2118         if (i40e_chk_linearize(skb, count)) {
2119                 if (__skb_linearize(skb))
2120                         goto out_drop;
2121                 count = i40e_txd_use_count(skb->len);
2122                 tx_ring->tx_stats.tx_linearize++;
2123         }
2124
2125         /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD,
2126          *       + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD,
2127          *       + 4 desc gap to avoid the cache line where head is,
2128          *       + 1 desc for context descriptor,
2129          * otherwise try next time
2130          */
2131         if (i40e_maybe_stop_tx(tx_ring, count + 4 + 1)) {
2132                 tx_ring->tx_stats.tx_busy++;
2133                 return NETDEV_TX_BUSY;
2134         }
2135
2136         /* prepare the xmit flags */
2137         if (i40evf_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags))
2138                 goto out_drop;
2139
2140         /* obtain protocol of skb */
2141         protocol = vlan_get_protocol(skb);
2142
2143         /* record the location of the first descriptor for this packet */
2144         first = &tx_ring->tx_bi[tx_ring->next_to_use];
2145
2146         /* setup IPv4/IPv6 offloads */
2147         if (protocol == htons(ETH_P_IP))
2148                 tx_flags |= I40E_TX_FLAGS_IPV4;
2149         else if (protocol == htons(ETH_P_IPV6))
2150                 tx_flags |= I40E_TX_FLAGS_IPV6;
2151
2152         tso = i40e_tso(skb, &hdr_len, &cd_type_cmd_tso_mss);
2153
2154         if (tso < 0)
2155                 goto out_drop;
2156         else if (tso)
2157                 tx_flags |= I40E_TX_FLAGS_TSO;
2158
2159         /* Always offload the checksum, since it's in the data descriptor */
2160         tso = i40e_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset,
2161                                   tx_ring, &cd_tunneling);
2162         if (tso < 0)
2163                 goto out_drop;
2164
2165         skb_tx_timestamp(skb);
2166
2167         /* always enable CRC insertion offload */
2168         td_cmd |= I40E_TX_DESC_CMD_ICRC;
2169
2170         i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss,
2171                            cd_tunneling, cd_l2tag2);
2172
2173         i40evf_tx_map(tx_ring, skb, first, tx_flags, hdr_len,
2174                       td_cmd, td_offset);
2175
2176         return NETDEV_TX_OK;
2177
2178 out_drop:
2179         dev_kfree_skb_any(skb);
2180         return NETDEV_TX_OK;
2181 }
2182
2183 /**
2184  * i40evf_xmit_frame - Selects the correct VSI and Tx queue to send buffer
2185  * @skb:    send buffer
2186  * @netdev: network interface device structure
2187  *
2188  * Returns NETDEV_TX_OK if sent, else an error code
2189  **/
2190 netdev_tx_t i40evf_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2191 {
2192         struct i40evf_adapter *adapter = netdev_priv(netdev);
2193         struct i40e_ring *tx_ring = &adapter->tx_rings[skb->queue_mapping];
2194
2195         /* hardware can't handle really short frames, hardware padding works
2196          * beyond this point
2197          */
2198         if (unlikely(skb->len < I40E_MIN_TX_LEN)) {
2199                 if (skb_pad(skb, I40E_MIN_TX_LEN - skb->len))
2200                         return NETDEV_TX_OK;
2201                 skb->len = I40E_MIN_TX_LEN;
2202                 skb_set_tail_pointer(skb, I40E_MIN_TX_LEN);
2203         }
2204
2205         return i40e_xmit_frame_ring(skb, tx_ring);
2206 }