drivers/net/ethernet/intel/i40e/i40e_type.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
   3
   4 #ifndef _I40E_TYPE_H_
   5 #define _I40E_TYPE_H_
   6
   7 #include "i40e_status.h"
   8 #include "i40e_osdep.h"
   9 #include "i40e_register.h"
  10 #include "i40e_adminq.h"
  11 #include "i40e_hmc.h"
  12 #include "i40e_lan_hmc.h"
  13 #include "i40e_devids.h"
  14
  15 /* I40E_MASK is a macro used on 32 bit registers */
  16 #define I40E_MASK(mask, shift) ((u32)(mask) << (shift))
  17
  18 #define I40E_MAX_VSI_QP                 16
  19 #define I40E_MAX_VF_VSI                 4
  20 #define I40E_MAX_CHAINED_RX_BUFFERS     5
  21 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS   16
  22
  23 /* Max default timeout in ms, */
  24 #define I40E_MAX_NVM_TIMEOUT            18000
  25
  26 /* Max timeout in ms for the phy to respond */
  27 #define I40E_MAX_PHY_TIMEOUT            500
  28
  29 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
  30 #define I40E_MS_TO_GTIME(time)          ((time) * 1000)
  31
  32 /* forward declaration */
  33 struct i40e_hw;
  34 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
  35
  36 /* Data type manipulation macros. */
  37
  38 #define I40E_DESC_UNUSED(R)     \
  39         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
  40         (R)->next_to_clean - (R)->next_to_use - 1)
  41
  42 /* bitfields for Tx queue mapping in QTX_CTL */
  43 #define I40E_QTX_CTL_VF_QUEUE   0x0
  44 #define I40E_QTX_CTL_VM_QUEUE   0x1
  45 #define I40E_QTX_CTL_PF_QUEUE   0x2
  46
  47 /* debug masks - set these bits in hw->debug_mask to control output */
  48 enum i40e_debug_mask {
  49         I40E_DEBUG_INIT                 = 0x00000001,
  50         I40E_DEBUG_RELEASE              = 0x00000002,
  51
  52         I40E_DEBUG_LINK                 = 0x00000010,
  53         I40E_DEBUG_PHY                  = 0x00000020,
  54         I40E_DEBUG_HMC                  = 0x00000040,
  55         I40E_DEBUG_NVM                  = 0x00000080,
  56         I40E_DEBUG_LAN                  = 0x00000100,
  57         I40E_DEBUG_FLOW                 = 0x00000200,
  58         I40E_DEBUG_DCB                  = 0x00000400,
  59         I40E_DEBUG_DIAG                 = 0x00000800,
  60         I40E_DEBUG_FD                   = 0x00001000,
  61         I40E_DEBUG_PACKAGE              = 0x00002000,
  62         I40E_DEBUG_IWARP                = 0x00F00000,
  63         I40E_DEBUG_AQ_MESSAGE           = 0x01000000,
  64         I40E_DEBUG_AQ_DESCRIPTOR        = 0x02000000,
  65         I40E_DEBUG_AQ_DESC_BUFFER       = 0x04000000,
  66         I40E_DEBUG_AQ_COMMAND           = 0x06000000,
  67         I40E_DEBUG_AQ                   = 0x0F000000,
  68
  69         I40E_DEBUG_USER                 = 0xF0000000,
  70
  71         I40E_DEBUG_ALL                  = 0xFFFFFFFF
  72 };
  73
  74 #define I40E_MDIO_CLAUSE22_STCODE_MASK  I40E_MASK(1, \
  75                                                   I40E_GLGEN_MSCA_STCODE_SHIFT)
  76 #define I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK    I40E_MASK(1, \
  77                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
  78 #define I40E_MDIO_CLAUSE22_OPCODE_READ_MASK     I40E_MASK(2, \
  79                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
  80
  81 #define I40E_MDIO_CLAUSE45_STCODE_MASK  I40E_MASK(0, \
  82                                                   I40E_GLGEN_MSCA_STCODE_SHIFT)
  83 #define I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK  I40E_MASK(0, \
  84                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
  85 #define I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK    I40E_MASK(1, \
  86                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
  87 #define I40E_MDIO_CLAUSE45_OPCODE_READ_MASK     I40E_MASK(3, \
  88                                                 I40E_GLGEN_MSCA_OPCODE_SHIFT)
  89
  90 #define I40E_PHY_COM_REG_PAGE                   0x1E
  91 #define I40E_PHY_LED_LINK_MODE_MASK             0xF0
  92 #define I40E_PHY_LED_MANUAL_ON                  0x100
  93 #define I40E_PHY_LED_PROV_REG_1                 0xC430
  94 #define I40E_PHY_LED_MODE_MASK                  0xFFFF
  95 #define I40E_PHY_LED_MODE_ORIG                  0x80000000
  96
  97 /* These are structs for managing the hardware information and the operations.
  98  * The structures of function pointers are filled out at init time when we
  99  * know for sure exactly which hardware we're working with.  This gives us the
 100  * flexibility of using the same main driver code but adapting to slightly
 101  * different hardware needs as new parts are developed.  For this architecture,
 102  * the Firmware and AdminQ are intended to insulate the driver from most of the
 103  * future changes, but these structures will also do part of the job.
 104  */
 105 enum i40e_mac_type {
 106         I40E_MAC_UNKNOWN = 0,
 107         I40E_MAC_XL710,
 108         I40E_MAC_VF,
 109         I40E_MAC_X722,
 110         I40E_MAC_X722_VF,
 111         I40E_MAC_GENERIC,
 112 };
 113
 114 enum i40e_media_type {
 115         I40E_MEDIA_TYPE_UNKNOWN = 0,
 116         I40E_MEDIA_TYPE_FIBER,
 117         I40E_MEDIA_TYPE_BASET,
 118         I40E_MEDIA_TYPE_BACKPLANE,
 119         I40E_MEDIA_TYPE_CX4,
 120         I40E_MEDIA_TYPE_DA,
 121         I40E_MEDIA_TYPE_VIRTUAL
 122 };
 123
 124 enum i40e_fc_mode {
 125         I40E_FC_NONE = 0,
 126         I40E_FC_RX_PAUSE,
 127         I40E_FC_TX_PAUSE,
 128         I40E_FC_FULL,
 129         I40E_FC_PFC,
 130         I40E_FC_DEFAULT
 131 };
 132
 133 enum i40e_set_fc_aq_failures {
 134         I40E_SET_FC_AQ_FAIL_NONE = 0,
 135         I40E_SET_FC_AQ_FAIL_GET = 1,
 136         I40E_SET_FC_AQ_FAIL_SET = 2,
 137         I40E_SET_FC_AQ_FAIL_UPDATE = 4,
 138         I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
 139 };
 140
 141 enum i40e_vsi_type {
 142         I40E_VSI_MAIN   = 0,
 143         I40E_VSI_VMDQ1  = 1,
 144         I40E_VSI_VMDQ2  = 2,
 145         I40E_VSI_CTRL   = 3,
 146         I40E_VSI_FCOE   = 4,
 147         I40E_VSI_MIRROR = 5,
 148         I40E_VSI_SRIOV  = 6,
 149         I40E_VSI_FDIR   = 7,
 150         I40E_VSI_IWARP  = 8,
 151         I40E_VSI_TYPE_UNKNOWN
 152 };
 153
 154 enum i40e_queue_type {
 155         I40E_QUEUE_TYPE_RX = 0,
 156         I40E_QUEUE_TYPE_TX,
 157         I40E_QUEUE_TYPE_PE_CEQ,
 158         I40E_QUEUE_TYPE_UNKNOWN
 159 };
 160
 161 struct i40e_link_status {
 162         enum i40e_aq_phy_type phy_type;
 163         enum i40e_aq_link_speed link_speed;
 164         u8 link_info;
 165         u8 an_info;
 166         u8 req_fec_info;
 167         u8 fec_info;
 168         u8 ext_info;
 169         u8 loopback;
 170         /* is Link Status Event notification to SW enabled */
 171         bool lse_enable;
 172         u16 max_frame_size;
 173         bool crc_enable;
 174         u8 pacing;
 175         u8 requested_speeds;
 176         u8 module_type[3];
 177         /* 1st byte: module identifier */
 178 #define I40E_MODULE_TYPE_SFP            0x03
 179         /* 3rd byte: ethernet compliance codes for 1G */
 180 #define I40E_MODULE_TYPE_1000BASE_SX    0x01
 181 #define I40E_MODULE_TYPE_1000BASE_LX    0x02
 182 };
 183
 184 struct i40e_phy_info {
 185         struct i40e_link_status link_info;
 186         struct i40e_link_status link_info_old;
 187         bool get_link_info;
 188         enum i40e_media_type media_type;
 189         /* all the phy types the NVM is capable of */
 190         u64 phy_types;
 191 };
 192
 193 #define I40E_CAP_PHY_TYPE_SGMII BIT_ULL(I40E_PHY_TYPE_SGMII)
 194 #define I40E_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(I40E_PHY_TYPE_1000BASE_KX)
 195 #define I40E_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4)
 196 #define I40E_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(I40E_PHY_TYPE_10GBASE_KR)
 197 #define I40E_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4)
 198 #define I40E_CAP_PHY_TYPE_XAUI BIT_ULL(I40E_PHY_TYPE_XAUI)
 199 #define I40E_CAP_PHY_TYPE_XFI BIT_ULL(I40E_PHY_TYPE_XFI)
 200 #define I40E_CAP_PHY_TYPE_SFI BIT_ULL(I40E_PHY_TYPE_SFI)
 201 #define I40E_CAP_PHY_TYPE_XLAUI BIT_ULL(I40E_PHY_TYPE_XLAUI)
 202 #define I40E_CAP_PHY_TYPE_XLPPI BIT_ULL(I40E_PHY_TYPE_XLPPI)
 203 #define I40E_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU)
 204 #define I40E_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU)
 205 #define I40E_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC)
 206 #define I40E_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC)
 207 #define I40E_CAP_PHY_TYPE_100BASE_TX BIT_ULL(I40E_PHY_TYPE_100BASE_TX)
 208 #define I40E_CAP_PHY_TYPE_1000BASE_T BIT_ULL(I40E_PHY_TYPE_1000BASE_T)
 209 #define I40E_CAP_PHY_TYPE_10GBASE_T BIT_ULL(I40E_PHY_TYPE_10GBASE_T)
 210 #define I40E_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(I40E_PHY_TYPE_10GBASE_SR)
 211 #define I40E_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(I40E_PHY_TYPE_10GBASE_LR)
 212 #define I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU)
 213 #define I40E_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1)
 214 #define I40E_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4)
 215 #define I40E_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4)
 216 #define I40E_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4)
 217 #define I40E_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(I40E_PHY_TYPE_1000BASE_SX)
 218 #define I40E_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(I40E_PHY_TYPE_1000BASE_LX)
 219 #define I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL \
 220                                 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL)
 221 #define I40E_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2)
 222 /* Defining the macro I40E_TYPE_OFFSET to implement a bit shift for some
 223  * PHY types. There is an unused bit (31) in the I40E_CAP_PHY_TYPE_* bit
 224  * fields but no corresponding gap in the i40e_aq_phy_type enumeration. So,
 225  * a shift is needed to adjust for this with values larger than 31. The
 226  * only affected values are I40E_PHY_TYPE_25GBASE_*.
 227  */
 228 #define I40E_PHY_TYPE_OFFSET 1
 229 #define I40E_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(I40E_PHY_TYPE_25GBASE_KR + \
 230                                              I40E_PHY_TYPE_OFFSET)
 231 #define I40E_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(I40E_PHY_TYPE_25GBASE_CR + \
 232                                              I40E_PHY_TYPE_OFFSET)
 233 #define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_PHY_TYPE_25GBASE_SR + \
 234                                              I40E_PHY_TYPE_OFFSET)
 235 #define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_PHY_TYPE_25GBASE_LR + \
 236                                              I40E_PHY_TYPE_OFFSET)
 237 #define I40E_CAP_PHY_TYPE_25GBASE_AOC BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC + \
 238                                              I40E_PHY_TYPE_OFFSET)
 239 #define I40E_CAP_PHY_TYPE_25GBASE_ACC BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC + \
 240                                              I40E_PHY_TYPE_OFFSET)
 241 /* Offset for 2.5G/5G PHY Types value to bit number conversion */
 242 #define I40E_PHY_TYPE_OFFSET2 (-10)
 243 #define I40E_CAP_PHY_TYPE_2_5GBASE_T BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T + \
 244                                              I40E_PHY_TYPE_OFFSET2)
 245 #define I40E_CAP_PHY_TYPE_5GBASE_T BIT_ULL(I40E_PHY_TYPE_5GBASE_T + \
 246                                              I40E_PHY_TYPE_OFFSET2)
 247 #define I40E_HW_CAP_MAX_GPIO                    30
 248 /* Capabilities of a PF or a VF or the whole device */
 249 struct i40e_hw_capabilities {
 250         u32  switch_mode;
 251
 252         /* Cloud filter modes:
 253          * Mode1: Filter on L4 port only
 254          * Mode2: Filter for non-tunneled traffic
 255          * Mode3: Filter for tunnel traffic
 256          */
 257 #define I40E_CLOUD_FILTER_MODE1 0x6
 258 #define I40E_CLOUD_FILTER_MODE2 0x7
 259 #define I40E_SWITCH_MODE_MASK   0xF
 260
 261         u32  management_mode;
 262         u32  mng_protocols_over_mctp;
 263         u32  npar_enable;
 264         u32  os2bmc;
 265         u32  valid_functions;
 266         bool sr_iov_1_1;
 267         bool vmdq;
 268         bool evb_802_1_qbg; /* Edge Virtual Bridging */
 269         bool evb_802_1_qbh; /* Bridge Port Extension */
 270         bool dcb;
 271         bool fcoe;
 272         bool iscsi; /* Indicates iSCSI enabled */
 273         bool flex10_enable;
 274         bool flex10_capable;
 275         u32  flex10_mode;
 276
 277         u32 flex10_status;
 278
 279         bool sec_rev_disabled;
 280         bool update_disabled;
 281 #define I40E_NVM_MGMT_SEC_REV_DISABLED  0x1
 282 #define I40E_NVM_MGMT_UPDATE_DISABLED   0x2
 283
 284         bool mgmt_cem;
 285         bool ieee_1588;
 286         bool iwarp;
 287         bool fd;
 288         u32 fd_filters_guaranteed;
 289         u32 fd_filters_best_effort;
 290         bool rss;
 291         u32 rss_table_size;
 292         u32 rss_table_entry_width;
 293         bool led[I40E_HW_CAP_MAX_GPIO];
 294         bool sdp[I40E_HW_CAP_MAX_GPIO];
 295         u32 nvm_image_type;
 296         u32 num_flow_director_filters;
 297         u32 num_vfs;
 298         u32 vf_base_id;
 299         u32 num_vsis;
 300         u32 num_rx_qp;
 301         u32 num_tx_qp;
 302         u32 base_queue;
 303         u32 num_msix_vectors;
 304         u32 num_msix_vectors_vf;
 305         u32 led_pin_num;
 306         u32 sdp_pin_num;
 307         u32 mdio_port_num;
 308         u32 mdio_port_mode;
 309         u8 rx_buf_chain_len;
 310         u32 enabled_tcmap;
 311         u32 maxtc;
 312         u64 wr_csr_prot;
 313 };
 314
 315 struct i40e_mac_info {
 316         enum i40e_mac_type type;
 317         u8 addr[ETH_ALEN];
 318         u8 perm_addr[ETH_ALEN];
 319         u8 san_addr[ETH_ALEN];
 320         u8 port_addr[ETH_ALEN];
 321         u16 max_fcoeq;
 322 };
 323
 324 enum i40e_aq_resources_ids {
 325         I40E_NVM_RESOURCE_ID = 1
 326 };
 327
 328 enum i40e_aq_resource_access_type {
 329         I40E_RESOURCE_READ = 1,
 330         I40E_RESOURCE_WRITE
 331 };
 332
 333 struct i40e_nvm_info {
 334         u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
 335         u32 timeout;              /* [ms] */
 336         u16 sr_size;              /* Shadow RAM size in words */
 337         bool blank_nvm_mode;      /* is NVM empty (no FW present)*/
 338         u16 version;              /* NVM package version */
 339         u32 eetrack;              /* NVM data version */
 340         u32 oem_ver;              /* OEM version info */
 341 };
 342
 343 /* definitions used in NVM update support */
 344
 345 enum i40e_nvmupd_cmd {
 346         I40E_NVMUPD_INVALID,
 347         I40E_NVMUPD_READ_CON,
 348         I40E_NVMUPD_READ_SNT,
 349         I40E_NVMUPD_READ_LCB,
 350         I40E_NVMUPD_READ_SA,
 351         I40E_NVMUPD_WRITE_ERA,
 352         I40E_NVMUPD_WRITE_CON,
 353         I40E_NVMUPD_WRITE_SNT,
 354         I40E_NVMUPD_WRITE_LCB,
 355         I40E_NVMUPD_WRITE_SA,
 356         I40E_NVMUPD_CSUM_CON,
 357         I40E_NVMUPD_CSUM_SA,
 358         I40E_NVMUPD_CSUM_LCB,
 359         I40E_NVMUPD_STATUS,
 360         I40E_NVMUPD_EXEC_AQ,
 361         I40E_NVMUPD_GET_AQ_RESULT,
 362         I40E_NVMUPD_GET_AQ_EVENT,
 363 };
 364
 365 enum i40e_nvmupd_state {
 366         I40E_NVMUPD_STATE_INIT,
 367         I40E_NVMUPD_STATE_READING,
 368         I40E_NVMUPD_STATE_WRITING,
 369         I40E_NVMUPD_STATE_INIT_WAIT,
 370         I40E_NVMUPD_STATE_WRITE_WAIT,
 371         I40E_NVMUPD_STATE_ERROR
 372 };
 373
 374 /* nvm_access definition and its masks/shifts need to be accessible to
 375  * application, core driver, and shared code.  Where is the right file?
 376  */
 377 #define I40E_NVM_READ   0xB
 378 #define I40E_NVM_WRITE  0xC
 379
 380 #define I40E_NVM_MOD_PNT_MASK 0xFF
 381
 382 #define I40E_NVM_TRANS_SHIFT                    8
 383 #define I40E_NVM_TRANS_MASK                     (0xf << I40E_NVM_TRANS_SHIFT)
 384 #define I40E_NVM_PRESERVATION_FLAGS_SHIFT       12
 385 #define I40E_NVM_PRESERVATION_FLAGS_MASK \
 386                                 (0x3 << I40E_NVM_PRESERVATION_FLAGS_SHIFT)
 387 #define I40E_NVM_PRESERVATION_FLAGS_SELECTED    0x01
 388 #define I40E_NVM_PRESERVATION_FLAGS_ALL         0x02
 389 #define I40E_NVM_CON                            0x0
 390 #define I40E_NVM_SNT                            0x1
 391 #define I40E_NVM_LCB                            0x2
 392 #define I40E_NVM_SA                             (I40E_NVM_SNT | I40E_NVM_LCB)
 393 #define I40E_NVM_ERA                            0x4
 394 #define I40E_NVM_CSUM                           0x8
 395 #define I40E_NVM_AQE                            0xe
 396 #define I40E_NVM_EXEC                           0xf
 397
 398
 399 #define I40E_NVMUPD_MAX_DATA    4096
 400
 401 struct i40e_nvm_access {
 402         u32 command;
 403         u32 config;
 404         u32 offset;     /* in bytes */
 405         u32 data_size;  /* in bytes */
 406         u8 data[1];
 407 };
 408
 409 /* (Q)SFP module access definitions */
 410 #define I40E_I2C_EEPROM_DEV_ADDR        0xA0
 411 #define I40E_I2C_EEPROM_DEV_ADDR2       0xA2
 412 #define I40E_MODULE_REVISION_ADDR       0x01
 413 #define I40E_MODULE_SFF_8472_COMP       0x5E
 414 #define I40E_MODULE_SFF_8472_SWAP       0x5C
 415 #define I40E_MODULE_SFF_ADDR_MODE       0x04
 416 #define I40E_MODULE_SFF_DDM_IMPLEMENTED 0x40
 417 #define I40E_MODULE_TYPE_QSFP_PLUS      0x0D
 418 #define I40E_MODULE_TYPE_QSFP28         0x11
 419 #define I40E_MODULE_QSFP_MAX_LEN        640
 420
 421 /* PCI bus types */
 422 enum i40e_bus_type {
 423         i40e_bus_type_unknown = 0,
 424         i40e_bus_type_pci,
 425         i40e_bus_type_pcix,
 426         i40e_bus_type_pci_express,
 427         i40e_bus_type_reserved
 428 };
 429
 430 /* PCI bus speeds */
 431 enum i40e_bus_speed {
 432         i40e_bus_speed_unknown  = 0,
 433         i40e_bus_speed_33       = 33,
 434         i40e_bus_speed_66       = 66,
 435         i40e_bus_speed_100      = 100,
 436         i40e_bus_speed_120      = 120,
 437         i40e_bus_speed_133      = 133,
 438         i40e_bus_speed_2500     = 2500,
 439         i40e_bus_speed_5000     = 5000,
 440         i40e_bus_speed_8000     = 8000,
 441         i40e_bus_speed_reserved
 442 };
 443
 444 /* PCI bus widths */
 445 enum i40e_bus_width {
 446         i40e_bus_width_unknown  = 0,
 447         i40e_bus_width_pcie_x1  = 1,
 448         i40e_bus_width_pcie_x2  = 2,
 449         i40e_bus_width_pcie_x4  = 4,
 450         i40e_bus_width_pcie_x8  = 8,
 451         i40e_bus_width_32       = 32,
 452         i40e_bus_width_64       = 64,
 453         i40e_bus_width_reserved
 454 };
 455
 456 /* Bus parameters */
 457 struct i40e_bus_info {
 458         enum i40e_bus_speed speed;
 459         enum i40e_bus_width width;
 460         enum i40e_bus_type type;
 461
 462         u16 func;
 463         u16 device;
 464         u16 lan_id;
 465         u16 bus_id;
 466 };
 467
 468 /* Flow control (FC) parameters */
 469 struct i40e_fc_info {
 470         enum i40e_fc_mode current_mode; /* FC mode in effect */
 471         enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
 472 };
 473
 474 #define I40E_MAX_TRAFFIC_CLASS          8
 475 #define I40E_MAX_USER_PRIORITY          8
 476 #define I40E_DCBX_MAX_APPS              32
 477 #define I40E_LLDPDU_SIZE                1500
 478 #define I40E_TLV_STATUS_OPER            0x1
 479 #define I40E_TLV_STATUS_SYNC            0x2
 480 #define I40E_TLV_STATUS_ERR             0x4
 481 #define I40E_CEE_OPER_MAX_APPS          3
 482 #define I40E_APP_PROTOID_FCOE           0x8906
 483 #define I40E_APP_PROTOID_ISCSI          0x0cbc
 484 #define I40E_APP_PROTOID_FIP            0x8914
 485 #define I40E_APP_SEL_ETHTYPE            0x1
 486 #define I40E_APP_SEL_TCPIP              0x2
 487 #define I40E_CEE_APP_SEL_ETHTYPE        0x0
 488 #define I40E_CEE_APP_SEL_TCPIP          0x1
 489
 490 /* CEE or IEEE 802.1Qaz ETS Configuration data */
 491 struct i40e_dcb_ets_config {
 492         u8 willing;
 493         u8 cbs;
 494         u8 maxtcs;
 495         u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
 496         u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
 497         u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
 498 };
 499
 500 /* CEE or IEEE 802.1Qaz PFC Configuration data */
 501 struct i40e_dcb_pfc_config {
 502         u8 willing;
 503         u8 mbc;
 504         u8 pfccap;
 505         u8 pfcenable;
 506 };
 507
 508 /* CEE or IEEE 802.1Qaz Application Priority data */
 509 struct i40e_dcb_app_priority_table {
 510         u8  priority;
 511         u8  selector;
 512         u16 protocolid;
 513 };
 514
 515 struct i40e_dcbx_config {
 516         u8  dcbx_mode;
 517 #define I40E_DCBX_MODE_CEE      0x1
 518 #define I40E_DCBX_MODE_IEEE     0x2
 519         u8  app_mode;
 520         u32 numapps;
 521         u32 tlv_status; /* CEE mode TLV status */
 522         struct i40e_dcb_ets_config etscfg;
 523         struct i40e_dcb_ets_config etsrec;
 524         struct i40e_dcb_pfc_config pfc;
 525         struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
 526 };
 527
 528 /* Port hardware description */
 529 struct i40e_hw {
 530         u8 __iomem *hw_addr;
 531         void *back;
 532
 533         /* subsystem structs */
 534         struct i40e_phy_info phy;
 535         struct i40e_mac_info mac;
 536         struct i40e_bus_info bus;
 537         struct i40e_nvm_info nvm;
 538         struct i40e_fc_info fc;
 539
 540         /* pci info */
 541         u16 device_id;
 542         u16 vendor_id;
 543         u16 subsystem_device_id;
 544         u16 subsystem_vendor_id;
 545         u8 revision_id;
 546         u8 port;
 547         bool adapter_stopped;
 548
 549         /* capabilities for entire device and PCI func */
 550         struct i40e_hw_capabilities dev_caps;
 551         struct i40e_hw_capabilities func_caps;
 552
 553         /* Flow Director shared filter space */
 554         u16 fdir_shared_filter_count;
 555
 556         /* device profile info */
 557         u8  pf_id;
 558         u16 main_vsi_seid;
 559
 560         /* for multi-function MACs */
 561         u16 partition_id;
 562         u16 num_partitions;
 563         u16 num_ports;
 564
 565         /* Closest numa node to the device */
 566         u16 numa_node;
 567
 568         /* Admin Queue info */
 569         struct i40e_adminq_info aq;
 570
 571         /* state of nvm update process */
 572         enum i40e_nvmupd_state nvmupd_state;
 573         struct i40e_aq_desc nvm_wb_desc;
 574         struct i40e_aq_desc nvm_aq_event_desc;
 575         struct i40e_virt_mem nvm_buff;
 576         bool nvm_release_on_done;
 577         u16 nvm_wait_opcode;
 578
 579         /* HMC info */
 580         struct i40e_hmc_info hmc; /* HMC info struct */
 581
 582         /* LLDP/DCBX Status */
 583         u16 dcbx_status;
 584
 585         /* DCBX info */
 586         struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */
 587         struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */
 588         struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */
 589
 590 #define I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0)
 591 #define I40E_HW_FLAG_802_1AD_CAPABLE        BIT_ULL(1)
 592 #define I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE  BIT_ULL(2)
 593 #define I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK BIT_ULL(3)
 594 #define I40E_HW_FLAG_FW_LLDP_STOPPABLE      BIT_ULL(4)
 595 #define I40E_HW_FLAG_FW_LLDP_PERSISTENT     BIT_ULL(5)
 596 #define I40E_HW_FLAG_AQ_PHY_ACCESS_EXTENDED BIT_ULL(6)
 597 #define I40E_HW_FLAG_DROP_MODE              BIT_ULL(7)
 598 #define I40E_HW_FLAG_X722_FEC_REQUEST_CAPABLE BIT_ULL(8)
 599         u64 flags;
 600
 601         /* Used in set switch config AQ command */
 602         u16 switch_tag;
 603         u16 first_tag;
 604         u16 second_tag;
 605
 606         /* debug mask */
 607         u32 debug_mask;
 608         char err_str[16];
 609 };
 610
 611 static inline bool i40e_is_vf(struct i40e_hw *hw)
 612 {
 613         return (hw->mac.type == I40E_MAC_VF ||
 614                 hw->mac.type == I40E_MAC_X722_VF);
 615 }
 616
 617 struct i40e_driver_version {
 618         u8 major_version;
 619         u8 minor_version;
 620         u8 build_version;
 621         u8 subbuild_version;
 622         u8 driver_string[32];
 623 };
 624
 625 /* RX Descriptors */
 626 union i40e_16byte_rx_desc {
 627         struct {
 628                 __le64 pkt_addr; /* Packet buffer address */
 629                 __le64 hdr_addr; /* Header buffer address */
 630         } read;
 631         struct {
 632                 struct i40e_16b_rx_wb_qw0 {
 633                         struct {
 634                                 union {
 635                                         __le16 mirroring_status;
 636                                         __le16 fcoe_ctx_id;
 637                                 } mirr_fcoe;
 638                                 __le16 l2tag1;
 639                         } lo_dword;
 640                         union {
 641                                 __le32 rss; /* RSS Hash */
 642                                 __le32 fd_id; /* Flow director filter id */
 643                                 __le32 fcoe_param; /* FCoE DDP Context id */
 644                         } hi_dword;
 645                 } qword0;
 646                 struct {
 647                         /* ext status/error/pktype/length */
 648                         __le64 status_error_len;
 649                 } qword1;
 650         } wb;  /* writeback */
 651         struct {
 652                 u64 qword[2];
 653         } raw;
 654 };
 655
 656 union i40e_32byte_rx_desc {
 657         struct {
 658                 __le64  pkt_addr; /* Packet buffer address */
 659                 __le64  hdr_addr; /* Header buffer address */
 660                         /* bit 0 of hdr_buffer_addr is DD bit */
 661                 __le64  rsvd1;
 662                 __le64  rsvd2;
 663         } read;
 664         struct {
 665                 struct i40e_32b_rx_wb_qw0 {
 666                         struct {
 667                                 union {
 668                                         __le16 mirroring_status;
 669                                         __le16 fcoe_ctx_id;
 670                                 } mirr_fcoe;
 671                                 __le16 l2tag1;
 672                         } lo_dword;
 673                         union {
 674                                 __le32 rss; /* RSS Hash */
 675                                 __le32 fcoe_param; /* FCoE DDP Context id */
 676                                 /* Flow director filter id in case of
 677                                  * Programming status desc WB
 678                                  */
 679                                 __le32 fd_id;
 680                         } hi_dword;
 681                 } qword0;
 682                 struct {
 683                         /* status/error/pktype/length */
 684                         __le64 status_error_len;
 685                 } qword1;
 686                 struct {
 687                         __le16 ext_status; /* extended status */
 688                         __le16 rsvd;
 689                         __le16 l2tag2_1;
 690                         __le16 l2tag2_2;
 691                 } qword2;
 692                 struct {
 693                         union {
 694                                 __le32 flex_bytes_lo;
 695                                 __le32 pe_status;
 696                         } lo_dword;
 697                         union {
 698                                 __le32 flex_bytes_hi;
 699                                 __le32 fd_id;
 700                         } hi_dword;
 701                 } qword3;
 702         } wb;  /* writeback */
 703         struct {
 704                 u64 qword[4];
 705         } raw;
 706 };
 707
 708 enum i40e_rx_desc_status_bits {
 709         /* Note: These are predefined bit offsets */
 710         I40E_RX_DESC_STATUS_DD_SHIFT            = 0,
 711         I40E_RX_DESC_STATUS_EOF_SHIFT           = 1,
 712         I40E_RX_DESC_STATUS_L2TAG1P_SHIFT       = 2,
 713         I40E_RX_DESC_STATUS_L3L4P_SHIFT         = 3,
 714         I40E_RX_DESC_STATUS_CRCP_SHIFT          = 4,
 715         I40E_RX_DESC_STATUS_TSYNINDX_SHIFT      = 5, /* 2 BITS */
 716         I40E_RX_DESC_STATUS_TSYNVALID_SHIFT     = 7,
 717         /* Note: Bit 8 is reserved in X710 and XL710 */
 718         I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT     = 8,
 719         I40E_RX_DESC_STATUS_UMBCAST_SHIFT       = 9, /* 2 BITS */
 720         I40E_RX_DESC_STATUS_FLM_SHIFT           = 11,
 721         I40E_RX_DESC_STATUS_FLTSTAT_SHIFT       = 12, /* 2 BITS */
 722         I40E_RX_DESC_STATUS_LPBK_SHIFT          = 14,
 723         I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT     = 15,
 724         I40E_RX_DESC_STATUS_RESERVED_SHIFT      = 16, /* 2 BITS */
 725         /* Note: For non-tunnel packets INT_UDP_0 is the right status for
 726          * UDP header
 727          */
 728         I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT     = 18,
 729         I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
 730 };
 731
 732 #define I40E_RXD_QW1_STATUS_SHIFT       0
 733 #define I40E_RXD_QW1_STATUS_MASK        ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) \
 734                                          << I40E_RXD_QW1_STATUS_SHIFT)
 735
 736 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT   I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
 737 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK       (0x3UL << \
 738                                              I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
 739
 740 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT  I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
 741 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK \
 742                                     BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
 743
 744 enum i40e_rx_desc_fltstat_values {
 745         I40E_RX_DESC_FLTSTAT_NO_DATA    = 0,
 746         I40E_RX_DESC_FLTSTAT_RSV_FD_ID  = 1, /* 16byte desc? FD_ID : RSV */
 747         I40E_RX_DESC_FLTSTAT_RSV        = 2,
 748         I40E_RX_DESC_FLTSTAT_RSS_HASH   = 3,
 749 };
 750
 751 #define I40E_RXD_QW1_ERROR_SHIFT        19
 752 #define I40E_RXD_QW1_ERROR_MASK         (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
 753
 754 enum i40e_rx_desc_error_bits {
 755         /* Note: These are predefined bit offsets */
 756         I40E_RX_DESC_ERROR_RXE_SHIFT            = 0,
 757         I40E_RX_DESC_ERROR_RECIPE_SHIFT         = 1,
 758         I40E_RX_DESC_ERROR_HBO_SHIFT            = 2,
 759         I40E_RX_DESC_ERROR_L3L4E_SHIFT          = 3, /* 3 BITS */
 760         I40E_RX_DESC_ERROR_IPE_SHIFT            = 3,
 761         I40E_RX_DESC_ERROR_L4E_SHIFT            = 4,
 762         I40E_RX_DESC_ERROR_EIPE_SHIFT           = 5,
 763         I40E_RX_DESC_ERROR_OVERSIZE_SHIFT       = 6,
 764         I40E_RX_DESC_ERROR_PPRS_SHIFT           = 7
 765 };
 766
 767 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
 768         I40E_RX_DESC_ERROR_L3L4E_NONE           = 0,
 769         I40E_RX_DESC_ERROR_L3L4E_PROT           = 1,
 770         I40E_RX_DESC_ERROR_L3L4E_FC             = 2,
 771         I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR       = 3,
 772         I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN      = 4
 773 };
 774
 775 #define I40E_RXD_QW1_PTYPE_SHIFT        30
 776 #define I40E_RXD_QW1_PTYPE_MASK         (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
 777
 778 /* Packet type non-ip values */
 779 enum i40e_rx_l2_ptype {
 780         I40E_RX_PTYPE_L2_RESERVED                       = 0,
 781         I40E_RX_PTYPE_L2_MAC_PAY2                       = 1,
 782         I40E_RX_PTYPE_L2_TIMESYNC_PAY2                  = 2,
 783         I40E_RX_PTYPE_L2_FIP_PAY2                       = 3,
 784         I40E_RX_PTYPE_L2_OUI_PAY2                       = 4,
 785         I40E_RX_PTYPE_L2_MACCNTRL_PAY2                  = 5,
 786         I40E_RX_PTYPE_L2_LLDP_PAY2                      = 6,
 787         I40E_RX_PTYPE_L2_ECP_PAY2                       = 7,
 788         I40E_RX_PTYPE_L2_EVB_PAY2                       = 8,
 789         I40E_RX_PTYPE_L2_QCN_PAY2                       = 9,
 790         I40E_RX_PTYPE_L2_EAPOL_PAY2                     = 10,
 791         I40E_RX_PTYPE_L2_ARP                            = 11,
 792         I40E_RX_PTYPE_L2_FCOE_PAY3                      = 12,
 793         I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3               = 13,
 794         I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3                = 14,
 795         I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3                = 15,
 796         I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA                = 16,
 797         I40E_RX_PTYPE_L2_FCOE_VFT_PAY3                  = 17,
 798         I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA                = 18,
 799         I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY                 = 19,
 800         I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP                 = 20,
 801         I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER               = 21,
 802         I40E_RX_PTYPE_GRENAT4_MAC_PAY3                  = 58,
 803         I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4    = 87,
 804         I40E_RX_PTYPE_GRENAT6_MAC_PAY3                  = 124,
 805         I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4    = 153
 806 };
 807
 808 struct i40e_rx_ptype_decoded {
 809         u32 ptype:8;
 810         u32 known:1;
 811         u32 outer_ip:1;
 812         u32 outer_ip_ver:1;
 813         u32 outer_frag:1;
 814         u32 tunnel_type:3;
 815         u32 tunnel_end_prot:2;
 816         u32 tunnel_end_frag:1;
 817         u32 inner_prot:4;
 818         u32 payload_layer:3;
 819 };
 820
 821 enum i40e_rx_ptype_outer_ip {
 822         I40E_RX_PTYPE_OUTER_L2  = 0,
 823         I40E_RX_PTYPE_OUTER_IP  = 1
 824 };
 825
 826 enum i40e_rx_ptype_outer_ip_ver {
 827         I40E_RX_PTYPE_OUTER_NONE        = 0,
 828         I40E_RX_PTYPE_OUTER_IPV4        = 0,
 829         I40E_RX_PTYPE_OUTER_IPV6        = 1
 830 };
 831
 832 enum i40e_rx_ptype_outer_fragmented {
 833         I40E_RX_PTYPE_NOT_FRAG  = 0,
 834         I40E_RX_PTYPE_FRAG      = 1
 835 };
 836
 837 enum i40e_rx_ptype_tunnel_type {
 838         I40E_RX_PTYPE_TUNNEL_NONE               = 0,
 839         I40E_RX_PTYPE_TUNNEL_IP_IP              = 1,
 840         I40E_RX_PTYPE_TUNNEL_IP_GRENAT          = 2,
 841         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC      = 3,
 842         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
 843 };
 844
 845 enum i40e_rx_ptype_tunnel_end_prot {
 846         I40E_RX_PTYPE_TUNNEL_END_NONE   = 0,
 847         I40E_RX_PTYPE_TUNNEL_END_IPV4   = 1,
 848         I40E_RX_PTYPE_TUNNEL_END_IPV6   = 2,
 849 };
 850
 851 enum i40e_rx_ptype_inner_prot {
 852         I40E_RX_PTYPE_INNER_PROT_NONE           = 0,
 853         I40E_RX_PTYPE_INNER_PROT_UDP            = 1,
 854         I40E_RX_PTYPE_INNER_PROT_TCP            = 2,
 855         I40E_RX_PTYPE_INNER_PROT_SCTP           = 3,
 856         I40E_RX_PTYPE_INNER_PROT_ICMP           = 4,
 857         I40E_RX_PTYPE_INNER_PROT_TIMESYNC       = 5
 858 };
 859
 860 enum i40e_rx_ptype_payload_layer {
 861         I40E_RX_PTYPE_PAYLOAD_LAYER_NONE        = 0,
 862         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2        = 1,
 863         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3        = 2,
 864         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4        = 3,
 865 };
 866
 867 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT  38
 868 #define I40E_RXD_QW1_LENGTH_PBUF_MASK   (0x3FFFULL << \
 869                                          I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
 870
 871
 872 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT   63
 873 #define I40E_RXD_QW1_LENGTH_SPH_MASK    BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
 874
 875 enum i40e_rx_desc_ext_status_bits {
 876         /* Note: These are predefined bit offsets */
 877         I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT   = 0,
 878         I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT   = 1,
 879         I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT    = 2, /* 2 BITS */
 880         I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT    = 4, /* 2 BITS */
 881         I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT   = 9,
 882         I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
 883         I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT   = 11,
 884 };
 885
 886 enum i40e_rx_desc_pe_status_bits {
 887         /* Note: These are predefined bit offsets */
 888         I40E_RX_DESC_PE_STATUS_QPID_SHIFT       = 0, /* 18 BITS */
 889         I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT     = 0, /* 16 BITS */
 890         I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT    = 16, /* 8 BITS */
 891         I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT    = 24,
 892         I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT   = 25,
 893         I40E_RX_DESC_PE_STATUS_PORTV_SHIFT      = 26,
 894         I40E_RX_DESC_PE_STATUS_URG_SHIFT        = 27,
 895         I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT     = 28,
 896         I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT      = 29
 897 };
 898
 899 #define I40E_RX_PROG_STATUS_DESC_LENGTH                 0x2000000
 900
 901 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT       2
 902 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK        (0x7UL << \
 903                                 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
 904
 905 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT        19
 906 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK         (0x3FUL << \
 907                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
 908
 909 enum i40e_rx_prog_status_desc_status_bits {
 910         /* Note: These are predefined bit offsets */
 911         I40E_RX_PROG_STATUS_DESC_DD_SHIFT       = 0,
 912         I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT  = 2 /* 3 BITS */
 913 };
 914
 915 enum i40e_rx_prog_status_desc_prog_id_masks {
 916         I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS       = 1,
 917         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS  = 2,
 918         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS  = 4,
 919 };
 920
 921 enum i40e_rx_prog_status_desc_error_bits {
 922         /* Note: These are predefined bit offsets */
 923         I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT      = 0,
 924         I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT      = 1,
 925         I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT    = 2,
 926         I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT    = 3
 927 };
 928
 929 /* TX Descriptor */
 930 struct i40e_tx_desc {
 931         __le64 buffer_addr; /* Address of descriptor's data buf */
 932         __le64 cmd_type_offset_bsz;
 933 };
 934
 935
 936 enum i40e_tx_desc_dtype_value {
 937         I40E_TX_DESC_DTYPE_DATA         = 0x0,
 938         I40E_TX_DESC_DTYPE_NOP          = 0x1, /* same as Context desc */
 939         I40E_TX_DESC_DTYPE_CONTEXT      = 0x1,
 940         I40E_TX_DESC_DTYPE_FCOE_CTX     = 0x2,
 941         I40E_TX_DESC_DTYPE_FILTER_PROG  = 0x8,
 942         I40E_TX_DESC_DTYPE_DDP_CTX      = 0x9,
 943         I40E_TX_DESC_DTYPE_FLEX_DATA    = 0xB,
 944         I40E_TX_DESC_DTYPE_FLEX_CTX_1   = 0xC,
 945         I40E_TX_DESC_DTYPE_FLEX_CTX_2   = 0xD,
 946         I40E_TX_DESC_DTYPE_DESC_DONE    = 0xF
 947 };
 948
 949 #define I40E_TXD_QW1_CMD_SHIFT  4
 950
 951 enum i40e_tx_desc_cmd_bits {
 952         I40E_TX_DESC_CMD_EOP                    = 0x0001,
 953         I40E_TX_DESC_CMD_RS                     = 0x0002,
 954         I40E_TX_DESC_CMD_ICRC                   = 0x0004,
 955         I40E_TX_DESC_CMD_IL2TAG1                = 0x0008,
 956         I40E_TX_DESC_CMD_DUMMY                  = 0x0010,
 957         I40E_TX_DESC_CMD_IIPT_NONIP             = 0x0000, /* 2 BITS */
 958         I40E_TX_DESC_CMD_IIPT_IPV6              = 0x0020, /* 2 BITS */
 959         I40E_TX_DESC_CMD_IIPT_IPV4              = 0x0040, /* 2 BITS */
 960         I40E_TX_DESC_CMD_IIPT_IPV4_CSUM         = 0x0060, /* 2 BITS */
 961         I40E_TX_DESC_CMD_FCOET                  = 0x0080,
 962         I40E_TX_DESC_CMD_L4T_EOFT_UNK           = 0x0000, /* 2 BITS */
 963         I40E_TX_DESC_CMD_L4T_EOFT_TCP           = 0x0100, /* 2 BITS */
 964         I40E_TX_DESC_CMD_L4T_EOFT_SCTP          = 0x0200, /* 2 BITS */
 965         I40E_TX_DESC_CMD_L4T_EOFT_UDP           = 0x0300, /* 2 BITS */
 966         I40E_TX_DESC_CMD_L4T_EOFT_EOF_N         = 0x0000, /* 2 BITS */
 967         I40E_TX_DESC_CMD_L4T_EOFT_EOF_T         = 0x0100, /* 2 BITS */
 968         I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI        = 0x0200, /* 2 BITS */
 969         I40E_TX_DESC_CMD_L4T_EOFT_EOF_A         = 0x0300, /* 2 BITS */
 970 };
 971
 972 #define I40E_TXD_QW1_OFFSET_SHIFT       16
 973
 974 enum i40e_tx_desc_length_fields {
 975         /* Note: These are predefined bit offsets */
 976         I40E_TX_DESC_LENGTH_MACLEN_SHIFT        = 0, /* 7 BITS */
 977         I40E_TX_DESC_LENGTH_IPLEN_SHIFT         = 7, /* 7 BITS */
 978         I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT     = 14 /* 4 BITS */
 979 };
 980
 981 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT    34
 982
 983 #define I40E_TXD_QW1_L2TAG1_SHIFT       48
 984
 985 /* Context descriptors */
 986 struct i40e_tx_context_desc {
 987         __le32 tunneling_params;
 988         __le16 l2tag2;
 989         __le16 rsvd;
 990         __le64 type_cmd_tso_mss;
 991 };
 992
 993
 994 #define I40E_TXD_CTX_QW1_CMD_SHIFT      4
 995
 996 enum i40e_tx_ctx_desc_cmd_bits {
 997         I40E_TX_CTX_DESC_TSO            = 0x01,
 998         I40E_TX_CTX_DESC_TSYN           = 0x02,
 999         I40E_TX_CTX_DESC_IL2TAG2        = 0x04,
1000         I40E_TX_CTX_DESC_IL2TAG2_IL2H   = 0x08,
1001         I40E_TX_CTX_DESC_SWTCH_NOTAG    = 0x00,
1002         I40E_TX_CTX_DESC_SWTCH_UPLINK   = 0x10,
1003         I40E_TX_CTX_DESC_SWTCH_LOCAL    = 0x20,
1004         I40E_TX_CTX_DESC_SWTCH_VSI      = 0x30,
1005         I40E_TX_CTX_DESC_SWPE           = 0x40
1006 };
1007
1008 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT  30
1009
1010 #define I40E_TXD_CTX_QW1_MSS_SHIFT      50
1011
1012
1013
1014 enum i40e_tx_ctx_desc_eipt_offload {
1015         I40E_TX_CTX_EXT_IP_NONE         = 0x0,
1016         I40E_TX_CTX_EXT_IP_IPV6         = 0x1,
1017         I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
1018         I40E_TX_CTX_EXT_IP_IPV4         = 0x3
1019 };
1020
1021 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT        2
1022
1023 #define I40E_TXD_CTX_QW0_NATT_SHIFT     9
1024
1025 #define I40E_TXD_CTX_UDP_TUNNELING      BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
1026 #define I40E_TXD_CTX_GRE_TUNNELING      (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1027
1028
1029
1030 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT   12
1031
1032
1033 #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT   23
1034 #define I40E_TXD_CTX_QW0_L4T_CS_MASK    BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
1035 struct i40e_filter_program_desc {
1036         __le32 qindex_flex_ptype_vsi;
1037         __le32 rsvd;
1038         __le32 dtype_cmd_cntindex;
1039         __le32 fd_id;
1040 };
1041 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT  0
1042 #define I40E_TXD_FLTR_QW0_QINDEX_MASK   (0x7FFUL << \
1043                                          I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
1044 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1045 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK  (0x7UL << \
1046                                          I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1047 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT  17
1048 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK   (0x3FUL << \
1049                                          I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
1050
1051 /* Packet Classifier Types for filters */
1052 enum i40e_filter_pctype {
1053         /* Note: Values 0-28 are reserved for future use.
1054          * Value 29, 30, 32 are not supported on XL710 and X710.
1055          */
1056         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP        = 29,
1057         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP      = 30,
1058         I40E_FILTER_PCTYPE_NONF_IPV4_UDP                = 31,
1059         I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK     = 32,
1060         I40E_FILTER_PCTYPE_NONF_IPV4_TCP                = 33,
1061         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP               = 34,
1062         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER              = 35,
1063         I40E_FILTER_PCTYPE_FRAG_IPV4                    = 36,
1064         /* Note: Values 37-38 are reserved for future use.
1065          * Value 39, 40, 42 are not supported on XL710 and X710.
1066          */
1067         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP        = 39,
1068         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP      = 40,
1069         I40E_FILTER_PCTYPE_NONF_IPV6_UDP                = 41,
1070         I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK     = 42,
1071         I40E_FILTER_PCTYPE_NONF_IPV6_TCP                = 43,
1072         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP               = 44,
1073         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER              = 45,
1074         I40E_FILTER_PCTYPE_FRAG_IPV6                    = 46,
1075         /* Note: Value 47 is reserved for future use */
1076         I40E_FILTER_PCTYPE_FCOE_OX                      = 48,
1077         I40E_FILTER_PCTYPE_FCOE_RX                      = 49,
1078         I40E_FILTER_PCTYPE_FCOE_OTHER                   = 50,
1079         /* Note: Values 51-62 are reserved for future use */
1080         I40E_FILTER_PCTYPE_L2_PAYLOAD                   = 63,
1081 };
1082
1083 enum i40e_filter_program_desc_dest {
1084         I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET               = 0x0,
1085         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX      = 0x1,
1086         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER       = 0x2,
1087 };
1088
1089 enum i40e_filter_program_desc_fd_status {
1090         I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE                 = 0x0,
1091         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID                = 0x1,
1092         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES    = 0x2,
1093         I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES          = 0x3,
1094 };
1095
1096 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT        23
1097 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1098                                          I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1099
1100 #define I40E_TXD_FLTR_QW1_CMD_SHIFT     4
1101
1102 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT    (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1103
1104 enum i40e_filter_program_desc_pcmd {
1105         I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE        = 0x1,
1106         I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE            = 0x2,
1107 };
1108
1109 #define I40E_TXD_FLTR_QW1_DEST_SHIFT    (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1110 #define I40E_TXD_FLTR_QW1_DEST_MASK     (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1111
1112 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1113 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK  BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1114
1115 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT       (0x9ULL + \
1116                                                  I40E_TXD_FLTR_QW1_CMD_SHIFT)
1117 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1118                                           I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1119
1120 #define I40E_TXD_FLTR_QW1_ATR_SHIFT     (0xEULL + \
1121                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1122 #define I40E_TXD_FLTR_QW1_ATR_MASK      BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
1123
1124 #define I40E_TXD_FLTR_QW1_ATR_SHIFT     (0xEULL + \
1125                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1126 #define I40E_TXD_FLTR_QW1_ATR_MASK      BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
1127
1128 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1129 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1130                                          I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1131
1132 enum i40e_filter_type {
1133         I40E_FLOW_DIRECTOR_FLTR = 0,
1134         I40E_PE_QUAD_HASH_FLTR = 1,
1135         I40E_ETHERTYPE_FLTR,
1136         I40E_FCOE_CTX_FLTR,
1137         I40E_MAC_VLAN_FLTR,
1138         I40E_HASH_FLTR
1139 };
1140
1141 struct i40e_vsi_context {
1142         u16 seid;
1143         u16 uplink_seid;
1144         u16 vsi_number;
1145         u16 vsis_allocated;
1146         u16 vsis_unallocated;
1147         u16 flags;
1148         u8 pf_num;
1149         u8 vf_num;
1150         u8 connection_type;
1151         struct i40e_aqc_vsi_properties_data info;
1152 };
1153
1154 struct i40e_veb_context {
1155         u16 seid;
1156         u16 uplink_seid;
1157         u16 veb_number;
1158         u16 vebs_allocated;
1159         u16 vebs_unallocated;
1160         u16 flags;
1161         struct i40e_aqc_get_veb_parameters_completion info;
1162 };
1163
1164 /* Statistics collected by each port, VSI, VEB, and S-channel */
1165 struct i40e_eth_stats {
1166         u64 rx_bytes;                   /* gorc */
1167         u64 rx_unicast;                 /* uprc */
1168         u64 rx_multicast;               /* mprc */
1169         u64 rx_broadcast;               /* bprc */
1170         u64 rx_discards;                /* rdpc */
1171         u64 rx_unknown_protocol;        /* rupp */
1172         u64 tx_bytes;                   /* gotc */
1173         u64 tx_unicast;                 /* uptc */
1174         u64 tx_multicast;               /* mptc */
1175         u64 tx_broadcast;               /* bptc */
1176         u64 tx_discards;                /* tdpc */
1177         u64 tx_errors;                  /* tepc */
1178 };
1179
1180 /* Statistics collected per VEB per TC */
1181 struct i40e_veb_tc_stats {
1182         u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1183         u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1184         u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1185         u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1186 };
1187
1188 /* Statistics collected by the MAC */
1189 struct i40e_hw_port_stats {
1190         /* eth stats collected by the port */
1191         struct i40e_eth_stats eth;
1192
1193         /* additional port specific stats */
1194         u64 tx_dropped_link_down;       /* tdold */
1195         u64 crc_errors;                 /* crcerrs */
1196         u64 illegal_bytes;              /* illerrc */
1197         u64 error_bytes;                /* errbc */
1198         u64 mac_local_faults;           /* mlfc */
1199         u64 mac_remote_faults;          /* mrfc */
1200         u64 rx_length_errors;           /* rlec */
1201         u64 link_xon_rx;                /* lxonrxc */
1202         u64 link_xoff_rx;               /* lxoffrxc */
1203         u64 priority_xon_rx[8];         /* pxonrxc[8] */
1204         u64 priority_xoff_rx[8];        /* pxoffrxc[8] */
1205         u64 link_xon_tx;                /* lxontxc */
1206         u64 link_xoff_tx;               /* lxofftxc */
1207         u64 priority_xon_tx[8];         /* pxontxc[8] */
1208         u64 priority_xoff_tx[8];        /* pxofftxc[8] */
1209         u64 priority_xon_2_xoff[8];     /* pxon2offc[8] */
1210         u64 rx_size_64;                 /* prc64 */
1211         u64 rx_size_127;                /* prc127 */
1212         u64 rx_size_255;                /* prc255 */
1213         u64 rx_size_511;                /* prc511 */
1214         u64 rx_size_1023;               /* prc1023 */
1215         u64 rx_size_1522;               /* prc1522 */
1216         u64 rx_size_big;                /* prc9522 */
1217         u64 rx_undersize;               /* ruc */
1218         u64 rx_fragments;               /* rfc */
1219         u64 rx_oversize;                /* roc */
1220         u64 rx_jabber;                  /* rjc */
1221         u64 tx_size_64;                 /* ptc64 */
1222         u64 tx_size_127;                /* ptc127 */
1223         u64 tx_size_255;                /* ptc255 */
1224         u64 tx_size_511;                /* ptc511 */
1225         u64 tx_size_1023;               /* ptc1023 */
1226         u64 tx_size_1522;               /* ptc1522 */
1227         u64 tx_size_big;                /* ptc9522 */
1228         u64 mac_short_packet_dropped;   /* mspdc */
1229         u64 checksum_error;             /* xec */
1230         /* flow director stats */
1231         u64 fd_atr_match;
1232         u64 fd_sb_match;
1233         u64 fd_atr_tunnel_match;
1234         u32 fd_atr_status;
1235         u32 fd_sb_status;
1236         /* EEE LPI */
1237         u32 tx_lpi_status;
1238         u32 rx_lpi_status;
1239         u64 tx_lpi_count;               /* etlpic */
1240         u64 rx_lpi_count;               /* erlpic */
1241 };
1242
1243 /* Checksum and Shadow RAM pointers */
1244 #define I40E_SR_NVM_CONTROL_WORD                0x00
1245 #define I40E_EMP_MODULE_PTR                     0x0F
1246 #define I40E_SR_EMP_MODULE_PTR                  0x48
1247 #define I40E_SR_PBA_FLAGS                       0x15
1248 #define I40E_SR_PBA_BLOCK_PTR                   0x16
1249 #define I40E_SR_BOOT_CONFIG_PTR                 0x17
1250 #define I40E_NVM_OEM_VER_OFF                    0x83
1251 #define I40E_SR_NVM_DEV_STARTER_VERSION         0x18
1252 #define I40E_SR_NVM_WAKE_ON_LAN                 0x19
1253 #define I40E_SR_NVM_EETRACK_LO                  0x2D
1254 #define I40E_SR_NVM_EETRACK_HI                  0x2E
1255 #define I40E_SR_VPD_PTR                         0x2F
1256 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR          0x3E
1257 #define I40E_SR_SW_CHECKSUM_WORD                0x3F
1258 #define I40E_SR_EMP_SR_SETTINGS_PTR             0x48
1259
1260 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1261 #define I40E_SR_VPD_MODULE_MAX_SIZE             1024
1262 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE        1024
1263 #define I40E_SR_CONTROL_WORD_1_SHIFT            0x06
1264 #define I40E_SR_CONTROL_WORD_1_MASK     (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1265 #define I40E_SR_NVM_MAP_STRUCTURE_TYPE          BIT(12)
1266 #define I40E_PTR_TYPE                           BIT(15)
1267 #define I40E_SR_OCP_CFG_WORD0                   0x2B
1268 #define I40E_SR_OCP_ENABLED                     BIT(15)
1269
1270 /* Shadow RAM related */
1271 #define I40E_SR_SECTOR_SIZE_IN_WORDS    0x800
1272 #define I40E_SR_WORDS_IN_1KB            512
1273 /* Checksum should be calculated such that after adding all the words,
1274  * including the checksum word itself, the sum should be 0xBABA.
1275  */
1276 #define I40E_SR_SW_CHECKSUM_BASE        0xBABA
1277
1278 #define I40E_SRRD_SRCTL_ATTEMPTS        100000
1279
1280 enum i40e_switch_element_types {
1281         I40E_SWITCH_ELEMENT_TYPE_MAC    = 1,
1282         I40E_SWITCH_ELEMENT_TYPE_PF     = 2,
1283         I40E_SWITCH_ELEMENT_TYPE_VF     = 3,
1284         I40E_SWITCH_ELEMENT_TYPE_EMP    = 4,
1285         I40E_SWITCH_ELEMENT_TYPE_BMC    = 6,
1286         I40E_SWITCH_ELEMENT_TYPE_PE     = 16,
1287         I40E_SWITCH_ELEMENT_TYPE_VEB    = 17,
1288         I40E_SWITCH_ELEMENT_TYPE_PA     = 18,
1289         I40E_SWITCH_ELEMENT_TYPE_VSI    = 19,
1290 };
1291
1292 /* Supported EtherType filters */
1293 enum i40e_ether_type_index {
1294         I40E_ETHER_TYPE_1588            = 0,
1295         I40E_ETHER_TYPE_FIP             = 1,
1296         I40E_ETHER_TYPE_OUI_EXTENDED    = 2,
1297         I40E_ETHER_TYPE_MAC_CONTROL     = 3,
1298         I40E_ETHER_TYPE_LLDP            = 4,
1299         I40E_ETHER_TYPE_EVB_PROTOCOL1   = 5,
1300         I40E_ETHER_TYPE_EVB_PROTOCOL2   = 6,
1301         I40E_ETHER_TYPE_QCN_CNM         = 7,
1302         I40E_ETHER_TYPE_8021X           = 8,
1303         I40E_ETHER_TYPE_ARP             = 9,
1304         I40E_ETHER_TYPE_RSV1            = 10,
1305         I40E_ETHER_TYPE_RSV2            = 11,
1306 };
1307
1308 /* Filter context base size is 1K */
1309 #define I40E_HASH_FILTER_BASE_SIZE      1024
1310 /* Supported Hash filter values */
1311 enum i40e_hash_filter_size {
1312         I40E_HASH_FILTER_SIZE_1K        = 0,
1313         I40E_HASH_FILTER_SIZE_2K        = 1,
1314         I40E_HASH_FILTER_SIZE_4K        = 2,
1315         I40E_HASH_FILTER_SIZE_8K        = 3,
1316         I40E_HASH_FILTER_SIZE_16K       = 4,
1317         I40E_HASH_FILTER_SIZE_32K       = 5,
1318         I40E_HASH_FILTER_SIZE_64K       = 6,
1319         I40E_HASH_FILTER_SIZE_128K      = 7,
1320         I40E_HASH_FILTER_SIZE_256K      = 8,
1321         I40E_HASH_FILTER_SIZE_512K      = 9,
1322         I40E_HASH_FILTER_SIZE_1M        = 10,
1323 };
1324
1325 /* DMA context base size is 0.5K */
1326 #define I40E_DMA_CNTX_BASE_SIZE         512
1327 /* Supported DMA context values */
1328 enum i40e_dma_cntx_size {
1329         I40E_DMA_CNTX_SIZE_512          = 0,
1330         I40E_DMA_CNTX_SIZE_1K           = 1,
1331         I40E_DMA_CNTX_SIZE_2K           = 2,
1332         I40E_DMA_CNTX_SIZE_4K           = 3,
1333         I40E_DMA_CNTX_SIZE_8K           = 4,
1334         I40E_DMA_CNTX_SIZE_16K          = 5,
1335         I40E_DMA_CNTX_SIZE_32K          = 6,
1336         I40E_DMA_CNTX_SIZE_64K          = 7,
1337         I40E_DMA_CNTX_SIZE_128K         = 8,
1338         I40E_DMA_CNTX_SIZE_256K         = 9,
1339 };
1340
1341 /* Supported Hash look up table (LUT) sizes */
1342 enum i40e_hash_lut_size {
1343         I40E_HASH_LUT_SIZE_128          = 0,
1344         I40E_HASH_LUT_SIZE_512          = 1,
1345 };
1346
1347 /* Structure to hold a per PF filter control settings */
1348 struct i40e_filter_control_settings {
1349         /* number of PE Quad Hash filter buckets */
1350         enum i40e_hash_filter_size pe_filt_num;
1351         /* number of PE Quad Hash contexts */
1352         enum i40e_dma_cntx_size pe_cntx_num;
1353         /* number of FCoE filter buckets */
1354         enum i40e_hash_filter_size fcoe_filt_num;
1355         /* number of FCoE DDP contexts */
1356         enum i40e_dma_cntx_size fcoe_cntx_num;
1357         /* size of the Hash LUT */
1358         enum i40e_hash_lut_size hash_lut_size;
1359         /* enable FDIR filters for PF and its VFs */
1360         bool enable_fdir;
1361         /* enable Ethertype filters for PF and its VFs */
1362         bool enable_ethtype;
1363         /* enable MAC/VLAN filters for PF and its VFs */
1364         bool enable_macvlan;
1365 };
1366
1367 /* Structure to hold device level control filter counts */
1368 struct i40e_control_filter_stats {
1369         u16 mac_etype_used;   /* Used perfect match MAC/EtherType filters */
1370         u16 etype_used;       /* Used perfect EtherType filters */
1371         u16 mac_etype_free;   /* Un-used perfect match MAC/EtherType filters */
1372         u16 etype_free;       /* Un-used perfect EtherType filters */
1373 };
1374
1375 enum i40e_reset_type {
1376         I40E_RESET_POR          = 0,
1377         I40E_RESET_CORER        = 1,
1378         I40E_RESET_GLOBR        = 2,
1379         I40E_RESET_EMPR         = 3,
1380 };
1381
1382 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1383 #define I40E_NVM_LLDP_CFG_PTR   0x06
1384 #define I40E_SR_LLDP_CFG_PTR    0x31
1385 struct i40e_lldp_variables {
1386         u16 length;
1387         u16 adminstatus;
1388         u16 msgfasttx;
1389         u16 msgtxinterval;
1390         u16 txparams;
1391         u16 timers;
1392         u16 crc8;
1393 };
1394
1395 /* Offsets into Alternate Ram */
1396 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET         0   /* in dwords */
1397 #define I40E_ALT_STRUCT_DWORDS_PER_PF           64   /* in dwords */
1398 #define I40E_ALT_STRUCT_MIN_BW_OFFSET           0xE  /* in dwords */
1399 #define I40E_ALT_STRUCT_MAX_BW_OFFSET           0xF  /* in dwords */
1400
1401 /* Alternate Ram Bandwidth Masks */
1402 #define I40E_ALT_BW_VALUE_MASK          0xFF
1403 #define I40E_ALT_BW_VALID_MASK          0x80000000
1404
1405 /* RSS Hash Table Size */
1406 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1407
1408 /* INPUT SET MASK for RSS, flow director, and flexible payload */
1409 #define I40E_L3_SRC_SHIFT               47
1410 #define I40E_L3_SRC_MASK                (0x3ULL << I40E_L3_SRC_SHIFT)
1411 #define I40E_L3_V6_SRC_SHIFT            43
1412 #define I40E_L3_V6_SRC_MASK             (0xFFULL << I40E_L3_V6_SRC_SHIFT)
1413 #define I40E_L3_DST_SHIFT               35
1414 #define I40E_L3_DST_MASK                (0x3ULL << I40E_L3_DST_SHIFT)
1415 #define I40E_L3_V6_DST_SHIFT            35
1416 #define I40E_L3_V6_DST_MASK             (0xFFULL << I40E_L3_V6_DST_SHIFT)
1417 #define I40E_L4_SRC_SHIFT               34
1418 #define I40E_L4_SRC_MASK                (0x1ULL << I40E_L4_SRC_SHIFT)
1419 #define I40E_L4_DST_SHIFT               33
1420 #define I40E_L4_DST_MASK                (0x1ULL << I40E_L4_DST_SHIFT)
1421 #define I40E_VERIFY_TAG_SHIFT           31
1422 #define I40E_VERIFY_TAG_MASK            (0x3ULL << I40E_VERIFY_TAG_SHIFT)
1423
1424 #define I40E_FLEX_50_SHIFT              13
1425 #define I40E_FLEX_50_MASK               (0x1ULL << I40E_FLEX_50_SHIFT)
1426 #define I40E_FLEX_51_SHIFT              12
1427 #define I40E_FLEX_51_MASK               (0x1ULL << I40E_FLEX_51_SHIFT)
1428 #define I40E_FLEX_52_SHIFT              11
1429 #define I40E_FLEX_52_MASK               (0x1ULL << I40E_FLEX_52_SHIFT)
1430 #define I40E_FLEX_53_SHIFT              10
1431 #define I40E_FLEX_53_MASK               (0x1ULL << I40E_FLEX_53_SHIFT)
1432 #define I40E_FLEX_54_SHIFT              9
1433 #define I40E_FLEX_54_MASK               (0x1ULL << I40E_FLEX_54_SHIFT)
1434 #define I40E_FLEX_55_SHIFT              8
1435 #define I40E_FLEX_55_MASK               (0x1ULL << I40E_FLEX_55_SHIFT)
1436 #define I40E_FLEX_56_SHIFT              7
1437 #define I40E_FLEX_56_MASK               (0x1ULL << I40E_FLEX_56_SHIFT)
1438 #define I40E_FLEX_57_SHIFT              6
1439 #define I40E_FLEX_57_MASK               (0x1ULL << I40E_FLEX_57_SHIFT)
1440
1441 /* Version format for Dynamic Device Personalization(DDP) */
1442 struct i40e_ddp_version {
1443         u8 major;
1444         u8 minor;
1445         u8 update;
1446         u8 draft;
1447 };
1448
1449 #define I40E_DDP_NAME_SIZE      32
1450
1451 /* Package header */
1452 struct i40e_package_header {
1453         struct i40e_ddp_version version;
1454         u32 segment_count;
1455         u32 segment_offset[1];
1456 };
1457
1458 /* Generic segment header */
1459 struct i40e_generic_seg_header {
1460 #define SEGMENT_TYPE_METADATA   0x00000001
1461 #define SEGMENT_TYPE_I40E       0x00000011
1462         u32 type;
1463         struct i40e_ddp_version version;
1464         u32 size;
1465         char name[I40E_DDP_NAME_SIZE];
1466 };
1467
1468 struct i40e_metadata_segment {
1469         struct i40e_generic_seg_header header;
1470         struct i40e_ddp_version version;
1471 #define I40E_DDP_TRACKID_INVALID        0xFFFFFFFF
1472         u32 track_id;
1473         char name[I40E_DDP_NAME_SIZE];
1474 };
1475
1476 struct i40e_device_id_entry {
1477         u32 vendor_dev_id;
1478         u32 sub_vendor_dev_id;
1479 };
1480
1481 struct i40e_profile_segment {
1482         struct i40e_generic_seg_header header;
1483         struct i40e_ddp_version version;
1484         char name[I40E_DDP_NAME_SIZE];
1485         u32 device_table_count;
1486         struct i40e_device_id_entry device_table[1];
1487 };
1488
1489 struct i40e_section_table {
1490         u32 section_count;
1491         u32 section_offset[1];
1492 };
1493
1494 struct i40e_profile_section_header {
1495         u16 tbl_size;
1496         u16 data_end;
1497         struct {
1498 #define SECTION_TYPE_INFO       0x00000010
1499 #define SECTION_TYPE_MMIO       0x00000800
1500 #define SECTION_TYPE_RB_MMIO    0x00001800
1501 #define SECTION_TYPE_AQ         0x00000801
1502 #define SECTION_TYPE_RB_AQ      0x00001801
1503 #define SECTION_TYPE_NOTE       0x80000000
1504                 u32 type;
1505                 u32 offset;
1506                 u32 size;
1507         } section;
1508 };
1509
1510 struct i40e_profile_tlv_section_record {
1511         u8 rtype;
1512         u8 type;
1513         u16 len;
1514         u8 data[12];
1515 };
1516
1517 /* Generic AQ section in proflie */
1518 struct i40e_profile_aq_section {
1519         u16 opcode;
1520         u16 flags;
1521         u8  param[16];
1522         u16 datalen;
1523         u8  data[1];
1524 };
1525
1526 struct i40e_profile_info {
1527         u32 track_id;
1528         struct i40e_ddp_version version;
1529         u8 op;
1530 #define I40E_DDP_ADD_TRACKID            0x01
1531 #define I40E_DDP_REMOVE_TRACKID 0x02
1532         u8 reserved[7];
1533         u8 name[I40E_DDP_NAME_SIZE];
1534 };
1535 #endif /* _I40E_TYPE_H_ */