1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
4 #ifndef _I40E_ADMINQ_CMD_H_
5 #define _I40E_ADMINQ_CMD_H_
7 /* This header file defines the i40e Admin Queue commands and is shared between
8 * i40e Firmware and Software.
10 * This file needs to comply with the Linux Kernel coding style.
13 #define I40E_FW_API_VERSION_MAJOR 0x0001
14 #define I40E_FW_API_VERSION_MINOR_X722 0x0009
15 #define I40E_FW_API_VERSION_MINOR_X710 0x0009
17 #define I40E_FW_MINOR_VERSION(_h) ((_h)->mac.type == I40E_MAC_XL710 ? \
18 I40E_FW_API_VERSION_MINOR_X710 : \
19 I40E_FW_API_VERSION_MINOR_X722)
21 /* API version 1.7 implements additional link and PHY-specific APIs */
22 #define I40E_MINOR_VER_GET_LINK_INFO_XL710 0x0007
23 /* API version 1.9 for X722 implements additional link and PHY-specific APIs */
24 #define I40E_MINOR_VER_GET_LINK_INFO_X722 0x0009
25 /* API version 1.6 for X722 devices adds ability to stop FW LLDP agent */
26 #define I40E_MINOR_VER_FW_LLDP_STOPPABLE_X722 0x0006
52 /* Flags sub-structure
53 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
54 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
57 /* command flags and offsets*/
58 #define I40E_AQ_FLAG_ERR_SHIFT 2
59 #define I40E_AQ_FLAG_LB_SHIFT 9
60 #define I40E_AQ_FLAG_RD_SHIFT 10
61 #define I40E_AQ_FLAG_BUF_SHIFT 12
62 #define I40E_AQ_FLAG_SI_SHIFT 13
64 #define I40E_AQ_FLAG_ERR BIT(I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */
65 #define I40E_AQ_FLAG_LB BIT(I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */
66 #define I40E_AQ_FLAG_RD BIT(I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */
67 #define I40E_AQ_FLAG_BUF BIT(I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
68 #define I40E_AQ_FLAG_SI BIT(I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */
71 enum i40e_admin_queue_err {
72 I40E_AQ_RC_OK = 0, /* success */
73 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */
74 I40E_AQ_RC_ENOENT = 2, /* No such element */
75 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */
76 I40E_AQ_RC_EINTR = 4, /* operation interrupted */
77 I40E_AQ_RC_EIO = 5, /* I/O error */
78 I40E_AQ_RC_ENXIO = 6, /* No such resource */
79 I40E_AQ_RC_E2BIG = 7, /* Arg too long */
80 I40E_AQ_RC_EAGAIN = 8, /* Try again */
81 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */
82 I40E_AQ_RC_EACCES = 10, /* Permission denied */
83 I40E_AQ_RC_EFAULT = 11, /* Bad address */
84 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */
85 I40E_AQ_RC_EEXIST = 13, /* object already exists */
86 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */
87 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */
88 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */
89 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */
90 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */
91 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */
92 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */
93 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
94 I40E_AQ_RC_EFBIG = 22, /* File too large */
97 /* Admin Queue command opcodes */
98 enum i40e_admin_queue_opc {
100 i40e_aqc_opc_get_version = 0x0001,
101 i40e_aqc_opc_driver_version = 0x0002,
102 i40e_aqc_opc_queue_shutdown = 0x0003,
103 i40e_aqc_opc_set_pf_context = 0x0004,
105 /* resource ownership */
106 i40e_aqc_opc_request_resource = 0x0008,
107 i40e_aqc_opc_release_resource = 0x0009,
109 i40e_aqc_opc_list_func_capabilities = 0x000A,
110 i40e_aqc_opc_list_dev_capabilities = 0x000B,
113 i40e_aqc_opc_set_proxy_config = 0x0104,
114 i40e_aqc_opc_set_ns_proxy_table_entry = 0x0105,
117 i40e_aqc_opc_mac_address_read = 0x0107,
118 i40e_aqc_opc_mac_address_write = 0x0108,
121 i40e_aqc_opc_clear_pxe_mode = 0x0110,
124 i40e_aqc_opc_set_wol_filter = 0x0120,
125 i40e_aqc_opc_get_wake_reason = 0x0121,
127 /* internal switch commands */
128 i40e_aqc_opc_get_switch_config = 0x0200,
129 i40e_aqc_opc_add_statistics = 0x0201,
130 i40e_aqc_opc_remove_statistics = 0x0202,
131 i40e_aqc_opc_set_port_parameters = 0x0203,
132 i40e_aqc_opc_get_switch_resource_alloc = 0x0204,
133 i40e_aqc_opc_set_switch_config = 0x0205,
134 i40e_aqc_opc_rx_ctl_reg_read = 0x0206,
135 i40e_aqc_opc_rx_ctl_reg_write = 0x0207,
137 i40e_aqc_opc_add_vsi = 0x0210,
138 i40e_aqc_opc_update_vsi_parameters = 0x0211,
139 i40e_aqc_opc_get_vsi_parameters = 0x0212,
141 i40e_aqc_opc_add_pv = 0x0220,
142 i40e_aqc_opc_update_pv_parameters = 0x0221,
143 i40e_aqc_opc_get_pv_parameters = 0x0222,
145 i40e_aqc_opc_add_veb = 0x0230,
146 i40e_aqc_opc_update_veb_parameters = 0x0231,
147 i40e_aqc_opc_get_veb_parameters = 0x0232,
149 i40e_aqc_opc_delete_element = 0x0243,
151 i40e_aqc_opc_add_macvlan = 0x0250,
152 i40e_aqc_opc_remove_macvlan = 0x0251,
153 i40e_aqc_opc_add_vlan = 0x0252,
154 i40e_aqc_opc_remove_vlan = 0x0253,
155 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254,
156 i40e_aqc_opc_add_tag = 0x0255,
157 i40e_aqc_opc_remove_tag = 0x0256,
158 i40e_aqc_opc_add_multicast_etag = 0x0257,
159 i40e_aqc_opc_remove_multicast_etag = 0x0258,
160 i40e_aqc_opc_update_tag = 0x0259,
161 i40e_aqc_opc_add_control_packet_filter = 0x025A,
162 i40e_aqc_opc_remove_control_packet_filter = 0x025B,
163 i40e_aqc_opc_add_cloud_filters = 0x025C,
164 i40e_aqc_opc_remove_cloud_filters = 0x025D,
165 i40e_aqc_opc_clear_wol_switch_filters = 0x025E,
167 i40e_aqc_opc_add_mirror_rule = 0x0260,
168 i40e_aqc_opc_delete_mirror_rule = 0x0261,
170 /* Dynamic Device Personalization */
171 i40e_aqc_opc_write_personalization_profile = 0x0270,
172 i40e_aqc_opc_get_personalization_profile_list = 0x0271,
175 i40e_aqc_opc_dcb_ignore_pfc = 0x0301,
176 i40e_aqc_opc_dcb_updated = 0x0302,
177 i40e_aqc_opc_set_dcb_parameters = 0x0303,
180 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400,
181 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406,
182 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407,
183 i40e_aqc_opc_query_vsi_bw_config = 0x0408,
184 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A,
185 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410,
187 i40e_aqc_opc_enable_switching_comp_ets = 0x0413,
188 i40e_aqc_opc_modify_switching_comp_ets = 0x0414,
189 i40e_aqc_opc_disable_switching_comp_ets = 0x0415,
190 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416,
191 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417,
192 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418,
193 i40e_aqc_opc_query_port_ets_config = 0x0419,
194 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A,
195 i40e_aqc_opc_suspend_port_tx = 0x041B,
196 i40e_aqc_opc_resume_port_tx = 0x041C,
197 i40e_aqc_opc_configure_partition_bw = 0x041D,
199 i40e_aqc_opc_query_hmc_resource_profile = 0x0500,
200 i40e_aqc_opc_set_hmc_resource_profile = 0x0501,
203 i40e_aqc_opc_get_phy_abilities = 0x0600,
204 i40e_aqc_opc_set_phy_config = 0x0601,
205 i40e_aqc_opc_set_mac_config = 0x0603,
206 i40e_aqc_opc_set_link_restart_an = 0x0605,
207 i40e_aqc_opc_get_link_status = 0x0607,
208 i40e_aqc_opc_set_phy_int_mask = 0x0613,
209 i40e_aqc_opc_get_local_advt_reg = 0x0614,
210 i40e_aqc_opc_set_local_advt_reg = 0x0615,
211 i40e_aqc_opc_get_partner_advt = 0x0616,
212 i40e_aqc_opc_set_lb_modes = 0x0618,
213 i40e_aqc_opc_get_phy_wol_caps = 0x0621,
214 i40e_aqc_opc_set_phy_debug = 0x0622,
215 i40e_aqc_opc_upload_ext_phy_fm = 0x0625,
216 i40e_aqc_opc_run_phy_activity = 0x0626,
217 i40e_aqc_opc_set_phy_register = 0x0628,
218 i40e_aqc_opc_get_phy_register = 0x0629,
221 i40e_aqc_opc_nvm_read = 0x0701,
222 i40e_aqc_opc_nvm_erase = 0x0702,
223 i40e_aqc_opc_nvm_update = 0x0703,
224 i40e_aqc_opc_nvm_config_read = 0x0704,
225 i40e_aqc_opc_nvm_config_write = 0x0705,
226 i40e_aqc_opc_oem_post_update = 0x0720,
227 i40e_aqc_opc_thermal_sensor = 0x0721,
229 /* virtualization commands */
230 i40e_aqc_opc_send_msg_to_pf = 0x0801,
231 i40e_aqc_opc_send_msg_to_vf = 0x0802,
232 i40e_aqc_opc_send_msg_to_peer = 0x0803,
234 /* alternate structure */
235 i40e_aqc_opc_alternate_write = 0x0900,
236 i40e_aqc_opc_alternate_write_indirect = 0x0901,
237 i40e_aqc_opc_alternate_read = 0x0902,
238 i40e_aqc_opc_alternate_read_indirect = 0x0903,
239 i40e_aqc_opc_alternate_write_done = 0x0904,
240 i40e_aqc_opc_alternate_set_mode = 0x0905,
241 i40e_aqc_opc_alternate_clear_port = 0x0906,
244 i40e_aqc_opc_lldp_get_mib = 0x0A00,
245 i40e_aqc_opc_lldp_update_mib = 0x0A01,
246 i40e_aqc_opc_lldp_add_tlv = 0x0A02,
247 i40e_aqc_opc_lldp_update_tlv = 0x0A03,
248 i40e_aqc_opc_lldp_delete_tlv = 0x0A04,
249 i40e_aqc_opc_lldp_stop = 0x0A05,
250 i40e_aqc_opc_lldp_start = 0x0A06,
251 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07,
252 i40e_aqc_opc_lldp_set_local_mib = 0x0A08,
253 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09,
254 i40e_aqc_opc_lldp_restore = 0x0A0A,
256 /* Tunnel commands */
257 i40e_aqc_opc_add_udp_tunnel = 0x0B00,
258 i40e_aqc_opc_del_udp_tunnel = 0x0B01,
259 i40e_aqc_opc_set_rss_key = 0x0B02,
260 i40e_aqc_opc_set_rss_lut = 0x0B03,
261 i40e_aqc_opc_get_rss_key = 0x0B04,
262 i40e_aqc_opc_get_rss_lut = 0x0B05,
265 i40e_aqc_opc_event_lan_overflow = 0x1001,
268 i40e_aqc_opc_oem_parameter_change = 0xFE00,
269 i40e_aqc_opc_oem_device_status_change = 0xFE01,
270 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02,
271 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03,
274 i40e_aqc_opc_debug_read_reg = 0xFF03,
275 i40e_aqc_opc_debug_write_reg = 0xFF04,
276 i40e_aqc_opc_debug_modify_reg = 0xFF07,
277 i40e_aqc_opc_debug_dump_internals = 0xFF08,
280 /* command structures and indirect data structures */
282 /* Structure naming conventions:
283 * - no suffix for direct command descriptor structures
284 * - _data for indirect sent data
285 * - _resp for indirect return data (data which is both will use _data)
286 * - _completion for direct return data
287 * - _element_ for repeated elements (may also be _data or _resp)
289 * Command structures are expected to overlay the params.raw member of the basic
290 * descriptor, and as such cannot exceed 16 bytes in length.
293 /* This macro is used to generate a compilation error if a structure
294 * is not exactly the correct length. It gives a divide by zero error if the
295 * structure is not of the correct size, otherwise it creates an enum that is
298 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \
299 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
301 /* This macro is used extensively to ensure that command structures are 16
302 * bytes in length as they have to map to the raw array of that size.
304 #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X)
306 /* internal (0x00XX) commands */
308 /* Get version (direct 0x0001) */
309 struct i40e_aqc_get_version {
318 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version);
320 /* Send driver version (indirect 0x0002) */
321 struct i40e_aqc_driver_version {
325 u8 driver_subbuild_ver;
331 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version);
333 /* Queue Shutdown (direct 0x0003) */
334 struct i40e_aqc_queue_shutdown {
335 __le32 driver_unloading;
336 #define I40E_AQ_DRIVER_UNLOADING 0x1
340 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);
342 /* Set PF context (0x0004, direct) */
343 struct i40e_aqc_set_pf_context {
348 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context);
350 /* Request resource ownership (direct 0x0008)
351 * Release resource ownership (direct 0x0009)
353 struct i40e_aqc_request_resource {
357 __le32 resource_number;
361 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource);
363 /* Get function capabilities (indirect 0x000A)
364 * Get device capabilities (indirect 0x000B)
366 struct i40e_aqc_list_capabilites {
375 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites);
377 struct i40e_aqc_list_capabilities_element_resp {
389 #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001
390 #define I40E_AQ_CAP_ID_MNG_MODE 0x0002
391 #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003
392 #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004
393 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005
394 #define I40E_AQ_CAP_ID_SRIOV 0x0012
395 #define I40E_AQ_CAP_ID_VF 0x0013
396 #define I40E_AQ_CAP_ID_VMDQ 0x0014
397 #define I40E_AQ_CAP_ID_8021QBG 0x0015
398 #define I40E_AQ_CAP_ID_8021QBR 0x0016
399 #define I40E_AQ_CAP_ID_VSI 0x0017
400 #define I40E_AQ_CAP_ID_DCB 0x0018
401 #define I40E_AQ_CAP_ID_FCOE 0x0021
402 #define I40E_AQ_CAP_ID_ISCSI 0x0022
403 #define I40E_AQ_CAP_ID_RSS 0x0040
404 #define I40E_AQ_CAP_ID_RXQ 0x0041
405 #define I40E_AQ_CAP_ID_TXQ 0x0042
406 #define I40E_AQ_CAP_ID_MSIX 0x0043
407 #define I40E_AQ_CAP_ID_VF_MSIX 0x0044
408 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045
409 #define I40E_AQ_CAP_ID_1588 0x0046
410 #define I40E_AQ_CAP_ID_IWARP 0x0051
411 #define I40E_AQ_CAP_ID_LED 0x0061
412 #define I40E_AQ_CAP_ID_SDP 0x0062
413 #define I40E_AQ_CAP_ID_MDIO 0x0063
414 #define I40E_AQ_CAP_ID_WSR_PROT 0x0064
415 #define I40E_AQ_CAP_ID_NVM_MGMT 0x0080
416 #define I40E_AQ_CAP_ID_FLEX10 0x00F1
417 #define I40E_AQ_CAP_ID_CEM 0x00F2
419 /* Set CPPM Configuration (direct 0x0103) */
420 struct i40e_aqc_cppm_configuration {
421 __le16 command_flags;
430 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration);
432 /* Set ARP Proxy command / response (indirect 0x0104) */
433 struct i40e_aqc_arp_proxy_data {
434 __le16 command_flags;
436 __le32 enabled_offloads;
442 I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data);
444 /* Set NS Proxy Table Entry Command (indirect 0x0105) */
445 struct i40e_aqc_ns_proxy_data {
446 __le16 table_idx_mac_addr_0;
447 __le16 table_idx_mac_addr_1;
448 __le16 table_idx_ipv6_0;
449 __le16 table_idx_ipv6_1;
453 u8 local_mac_addr[6];
454 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */
458 I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data);
460 /* Manage LAA Command (0x0106) - obsolete */
461 struct i40e_aqc_mng_laa {
462 __le16 command_flags;
469 I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa);
471 /* Manage MAC Address Read Command (indirect 0x0107) */
472 struct i40e_aqc_mac_address_read {
473 __le16 command_flags;
474 #define I40E_AQC_LAN_ADDR_VALID 0x10
475 #define I40E_AQC_PORT_ADDR_VALID 0x40
481 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read);
483 struct i40e_aqc_mac_address_read_data {
490 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data);
492 /* Manage MAC Address Write Command (0x0108) */
493 struct i40e_aqc_mac_address_write {
494 __le16 command_flags;
495 #define I40E_AQC_MC_MAG_EN 0x0100
496 #define I40E_AQC_WOL_PRESERVE_ON_PFR 0x0200
497 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000
498 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000
499 #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000
506 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write);
508 /* PXE commands (0x011x) */
510 /* Clear PXE Command and response (direct 0x0110) */
511 struct i40e_aqc_clear_pxe {
516 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe);
518 /* Set WoL Filter (0x0120) */
520 struct i40e_aqc_set_wol_filter {
530 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_wol_filter);
532 struct i40e_aqc_set_wol_filter_data {
537 I40E_CHECK_STRUCT_LEN(0x90, i40e_aqc_set_wol_filter_data);
539 /* Get Wake Reason (0x0121) */
541 struct i40e_aqc_get_wake_reason_completion {
547 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_wake_reason_completion);
549 /* Switch configuration commands (0x02xx) */
551 /* Used by many indirect commands that only pass an seid and a buffer in the
554 struct i40e_aqc_switch_seid {
561 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid);
563 /* Get Switch Configuration command (indirect 0x0200)
564 * uses i40e_aqc_switch_seid for the descriptor
566 struct i40e_aqc_get_switch_config_header_resp {
572 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp);
574 struct i40e_aqc_switch_config_element_resp {
579 __le16 downlink_seid;
586 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp);
588 /* Get Switch Configuration (indirect 0x0200)
589 * an array of elements are returned in the response buffer
590 * the first in the array is the header, remainder are elements
592 struct i40e_aqc_get_switch_config_resp {
593 struct i40e_aqc_get_switch_config_header_resp header;
594 struct i40e_aqc_switch_config_element_resp element[1];
597 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp);
599 /* Add Statistics (direct 0x0201)
600 * Remove Statistics (direct 0x0202)
602 struct i40e_aqc_add_remove_statistics {
609 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics);
611 /* Set Port Parameters command (direct 0x0203) */
612 struct i40e_aqc_set_port_parameters {
613 __le16 command_flags;
614 __le16 bad_frame_vsi;
615 __le16 default_seid; /* reserved for command */
619 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters);
621 /* Get Switch Resource Allocation (indirect 0x0204) */
622 struct i40e_aqc_get_switch_resource_alloc {
623 u8 num_entries; /* reserved for command */
629 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc);
631 /* expect an array of these structs in the response buffer */
632 struct i40e_aqc_switch_resource_alloc_element_resp {
638 __le16 total_unalloced;
642 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp);
644 /* Set Switch Configuration (direct 0x0205) */
645 struct i40e_aqc_set_switch_config {
647 /* flags used for both fields below */
648 #define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001
650 /* The ethertype in switch_tag is dropped on ingress and used
651 * internally by the switch. Set this to zero for the default
652 * of 0x88a8 (802.1ad). Should be zero for firmware API
653 * versions lower than 1.7.
656 /* The ethertypes in first_tag and second_tag are used to
657 * match the outer and inner VLAN tags (respectively) when HW
658 * double VLAN tagging is enabled via the set port parameters
659 * AQ command. Otherwise these are both ignored. Set them to
660 * zero for their defaults of 0x8100 (802.1Q). Should be zero
661 * for firmware API versions lower than 1.7.
665 /* Next byte is split into following:
666 * Bit 7 : 0 : No action, 1: Switch to mode defined by bits 6:0
667 * Bit 6 : 0 : Destination Port, 1: source port
672 * 3: Both TCP and UDP
675 * 1: L4 port only mode
676 * 2: non-tunneled mode
679 #define I40E_AQ_SET_SWITCH_BIT7_VALID 0x80
682 #define I40E_AQ_SET_SWITCH_L4_TYPE_TCP 0x10
684 #define I40E_AQ_SET_SWITCH_MODE_NON_TUNNEL 0x02
689 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config);
691 /* Read Receive control registers (direct 0x0206)
692 * Write Receive control registers (direct 0x0207)
693 * used for accessing Rx control registers that can be
694 * slow and need special handling when under high Rx load
696 struct i40e_aqc_rx_ctl_reg_read_write {
703 I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write);
705 /* Add VSI (indirect 0x0210)
706 * this indirect command uses struct i40e_aqc_vsi_properties_data
707 * as the indirect buffer (128 bytes)
709 * Update VSI (indirect 0x211)
710 * uses the same data structure as Add VSI
712 * Get VSI (indirect 0x0212)
713 * uses the same completion and data structure as Add VSI
715 struct i40e_aqc_add_get_update_vsi {
718 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1
723 #define I40E_AQ_VSI_TYPE_VF 0x0
724 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1
725 #define I40E_AQ_VSI_TYPE_PF 0x2
730 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi);
732 struct i40e_aqc_add_get_update_vsi_completion {
741 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion);
743 struct i40e_aqc_vsi_properties_data {
744 /* first 96 byte are written by SW */
745 __le16 valid_sections;
746 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001
747 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002
748 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004
749 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040
750 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080
751 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200
753 __le16 switch_id; /* 12bit id combined with flags below */
754 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000
755 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)
756 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000
757 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000
759 /* security section */
761 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02
762 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04
765 __le16 pvid; /* VLANS include priority bits */
768 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00
769 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \
770 I40E_AQ_VSI_PVLAN_MODE_SHIFT)
771 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01
772 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03
773 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04
774 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03
775 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \
776 I40E_AQ_VSI_PVLAN_EMOD_SHIFT)
777 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0
778 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10
779 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18
780 u8 pvlan_reserved[3];
781 /* ingress egress up sections */
782 __le32 ingress_table; /* bitmap, 3 bits per up */
783 __le32 egress_table; /* same defines as for ingress table */
784 /* cascaded PV section */
788 /* queue mapping section */
789 __le16 mapping_flags;
790 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0
791 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1
792 __le16 queue_mapping[16];
793 __le16 tc_mapping[8];
794 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0
795 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9
796 /* queueing option section */
797 u8 queueing_opt_flags;
798 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10
799 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40
800 u8 queueing_opt_reserved[3];
801 /* scheduler section */
804 /* outer up section */
805 __le32 outer_up_table; /* same structure and defines as ingress tbl */
807 /* last 32 bytes are written by FW */
809 #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF
810 __le16 stat_counter_idx;
812 u8 resp_reserved[12];
815 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data);
817 /* Add Port Virtualizer (direct 0x0220)
818 * also used for update PV (direct 0x0221) but only flags are used
819 * (IS_CTRL_PORT only works on add PV)
821 struct i40e_aqc_add_update_pv {
822 __le16 command_flags;
824 __le16 connected_seid;
828 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv);
830 struct i40e_aqc_add_update_pv_completion {
831 /* reserved for update; for add also encodes error if rc == ENOSPC */
836 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion);
838 /* Get PV Params (direct 0x0222)
839 * uses i40e_aqc_switch_seid for the descriptor
842 struct i40e_aqc_get_pv_params_completion {
845 __le16 pv_flags; /* same flags as add_pv */
847 __le16 default_port_seid;
850 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion);
852 /* Add VEB (direct 0x0230) */
853 struct i40e_aqc_add_veb {
855 __le16 downlink_seid;
857 #define I40E_AQC_ADD_VEB_FLOATING 0x1
858 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2
859 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4
860 #define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10
865 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb);
867 struct i40e_aqc_add_veb_completion {
870 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */
872 __le16 statistic_index;
877 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion);
879 /* Get VEB Parameters (direct 0x0232)
880 * uses i40e_aqc_switch_seid for the descriptor
882 struct i40e_aqc_get_veb_parameters_completion {
885 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */
886 __le16 statistic_index;
892 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion);
894 /* Delete Element (direct 0x0243)
895 * uses the generic i40e_aqc_switch_seid
898 /* Add MAC-VLAN (indirect 0x0250) */
900 /* used for the command for most vlan commands */
901 struct i40e_aqc_macvlan {
902 __le16 num_addresses;
904 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000
909 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan);
911 /* indirect data for command and response */
912 struct i40e_aqc_add_macvlan_element_data {
916 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001
917 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004
918 #define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010
920 /* response section */
922 #define I40E_AQC_MM_ERR_NO_RES 0xFF
926 struct i40e_aqc_add_remove_macvlan_completion {
927 __le16 perfect_mac_used;
928 __le16 perfect_mac_free;
929 __le16 unicast_hash_free;
930 __le16 multicast_hash_free;
935 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion);
937 /* Remove MAC-VLAN (indirect 0x0251)
938 * uses i40e_aqc_macvlan for the descriptor
939 * data points to an array of num_addresses of elements
942 struct i40e_aqc_remove_macvlan_element_data {
946 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01
947 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08
951 u8 reply_reserved[3];
954 /* Add VLAN (indirect 0x0252)
955 * Remove VLAN (indirect 0x0253)
956 * use the generic i40e_aqc_macvlan for the command
958 struct i40e_aqc_add_remove_vlan_element_data {
966 struct i40e_aqc_add_remove_vlan_completion {
974 /* Set VSI Promiscuous Modes (direct 0x0254) */
975 struct i40e_aqc_set_vsi_promiscuous_modes {
976 __le16 promiscuous_flags;
978 /* flags used for both fields above */
979 #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01
980 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02
981 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04
982 #define I40E_AQC_SET_VSI_DEFAULT 0x08
983 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10
984 #define I40E_AQC_SET_VSI_PROMISC_TX 0x8000
987 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000
991 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes);
993 /* Add S/E-tag command (direct 0x0255)
994 * Uses generic i40e_aqc_add_remove_tag_completion for completion
996 struct i40e_aqc_add_tag {
1000 __le16 queue_number;
1004 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag);
1006 struct i40e_aqc_add_remove_tag_completion {
1012 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion);
1014 /* Remove S/E-tag command (direct 0x0256)
1015 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1017 struct i40e_aqc_remove_tag {
1023 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag);
1025 /* Add multicast E-Tag (direct 0x0257)
1026 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
1027 * and no external data
1029 struct i40e_aqc_add_remove_mcast_etag {
1032 u8 num_unicast_etags;
1034 __le32 addr_high; /* address of array of 2-byte s-tags */
1038 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag);
1040 struct i40e_aqc_add_remove_mcast_etag_completion {
1042 __le16 mcast_etags_used;
1043 __le16 mcast_etags_free;
1049 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion);
1051 /* Update S/E-Tag (direct 0x0259) */
1052 struct i40e_aqc_update_tag {
1059 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag);
1061 struct i40e_aqc_update_tag_completion {
1067 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion);
1069 /* Add Control Packet filter (direct 0x025A)
1070 * Remove Control Packet filter (direct 0x025B)
1071 * uses the i40e_aqc_add_oveb_cloud,
1072 * and the generic direct completion structure
1074 struct i40e_aqc_add_remove_control_packet_filter {
1078 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001
1079 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002
1080 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008
1086 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter);
1088 struct i40e_aqc_add_remove_control_packet_filter_completion {
1089 __le16 mac_etype_used;
1091 __le16 mac_etype_free;
1096 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion);
1098 /* Add Cloud filters (indirect 0x025C)
1099 * Remove Cloud filters (indirect 0x025D)
1100 * uses the i40e_aqc_add_remove_cloud_filters,
1101 * and the generic indirect completion structure
1103 struct i40e_aqc_add_remove_cloud_filters {
1108 #define I40E_AQC_ADD_CLOUD_CMD_BB 1
1114 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters);
1116 struct i40e_aqc_cloud_filters_element_data {
1133 /* 0x0000 reserved */
1134 /* 0x0001 reserved */
1135 /* 0x0002 reserved */
1136 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003
1137 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004
1138 /* 0x0005 reserved */
1139 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006
1140 /* 0x0007 reserved */
1141 /* 0x0008 reserved */
1142 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009
1143 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A
1144 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B
1145 #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C
1146 /* 0x000D reserved */
1147 /* 0x000E reserved */
1148 /* 0x000F reserved */
1149 /* 0x0010 to 0x0017 is for custom filters */
1150 #define I40E_AQC_ADD_CLOUD_FILTER_IP_PORT 0x0010 /* Dest IP + L4 Port */
1151 #define I40E_AQC_ADD_CLOUD_FILTER_MAC_PORT 0x0011 /* Dest MAC + L4 Port */
1152 #define I40E_AQC_ADD_CLOUD_FILTER_MAC_VLAN_PORT 0x0012 /* Dest MAC + VLAN + L4 Port */
1154 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0
1155 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100
1157 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9
1158 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00
1159 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2
1164 __le16 queue_number;
1166 /* response section */
1167 u8 allocation_result;
1168 u8 response_reserved[7];
1171 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_cloud_filters_element_data);
1173 /* i40e_aqc_cloud_filters_element_bb is used when
1174 * I40E_AQC_CLOUD_CMD_BB flag is set.
1176 struct i40e_aqc_cloud_filters_element_bb {
1177 struct i40e_aqc_cloud_filters_element_data element;
1178 u16 general_fields[32];
1179 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD0 15
1182 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_cloud_filters_element_bb);
1184 struct i40e_aqc_remove_cloud_filters_completion {
1185 __le16 perfect_ovlan_used;
1186 __le16 perfect_ovlan_free;
1193 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion);
1195 /* Replace filter Command 0x025F
1196 * uses the i40e_aqc_replace_cloud_filters,
1197 * and the generic indirect completion structure
1199 struct i40e_filter_data {
1204 I40E_CHECK_STRUCT_LEN(4, i40e_filter_data);
1206 struct i40e_aqc_replace_cloud_filters_cmd {
1216 I40E_CHECK_CMD_LENGTH(i40e_aqc_replace_cloud_filters_cmd);
1218 struct i40e_aqc_replace_cloud_filters_cmd_buf {
1220 struct i40e_filter_data filters[8];
1223 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_replace_cloud_filters_cmd_buf);
1225 /* Add Mirror Rule (indirect or direct 0x0260)
1226 * Delete Mirror Rule (indirect or direct 0x0261)
1227 * note: some rule types (4,5) do not use an external buffer.
1228 * take care to set the flags correctly.
1230 struct i40e_aqc_add_delete_mirror_rule {
1233 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0
1234 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \
1235 I40E_AQC_MIRROR_RULE_TYPE_SHIFT)
1236 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3
1237 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4
1238 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5
1240 __le16 destination; /* VSI for add, rule id for delete */
1241 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */
1245 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule);
1247 struct i40e_aqc_add_delete_mirror_rule_completion {
1249 __le16 rule_id; /* only used on add */
1250 __le16 mirror_rules_used;
1251 __le16 mirror_rules_free;
1256 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion);
1258 /* Dynamic Device Personalization */
1259 struct i40e_aqc_write_personalization_profile {
1262 __le32 profile_track_id;
1267 I40E_CHECK_CMD_LENGTH(i40e_aqc_write_personalization_profile);
1269 struct i40e_aqc_write_ddp_resp {
1270 __le32 error_offset;
1276 struct i40e_aqc_get_applied_profiles {
1284 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_applied_profiles);
1288 /* PFC Ignore (direct 0x0301)
1289 * the command and response use the same descriptor structure
1291 struct i40e_aqc_pfc_ignore {
1293 u8 command_flags; /* unused on response */
1297 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore);
1299 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure
1300 * with no parameters
1303 /* TX scheduler 0x04xx */
1305 /* Almost all the indirect commands use
1306 * this generic struct to pass the SEID in param0
1308 struct i40e_aqc_tx_sched_ind {
1315 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind);
1317 /* Several commands respond with a set of queue set handles */
1318 struct i40e_aqc_qs_handles_resp {
1319 __le16 qs_handles[8];
1322 /* Configure VSI BW limits (direct 0x0400) */
1323 struct i40e_aqc_configure_vsi_bw_limit {
1328 u8 max_credit; /* 0-3, limit = 2^max */
1332 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit);
1334 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
1335 * responds with i40e_aqc_qs_handles_resp
1337 struct i40e_aqc_configure_vsi_ets_sla_bw_data {
1340 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */
1342 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1343 __le16 tc_bw_max[2];
1347 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data);
1349 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
1350 * responds with i40e_aqc_qs_handles_resp
1352 struct i40e_aqc_configure_vsi_tc_bw_data {
1355 u8 tc_bw_credits[8];
1357 __le16 qs_handles[8];
1360 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data);
1362 /* Query vsi bw configuration (indirect 0x0408) */
1363 struct i40e_aqc_query_vsi_bw_config_resp {
1365 u8 tc_suspended_bits;
1367 __le16 qs_handles[8];
1369 __le16 port_bw_limit;
1371 u8 max_bw; /* 0-3, limit = 2^max */
1375 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp);
1377 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
1378 struct i40e_aqc_query_vsi_ets_sla_config_resp {
1381 u8 share_credits[8];
1384 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1385 __le16 tc_bw_max[2];
1388 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp);
1390 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */
1391 struct i40e_aqc_configure_switching_comp_bw_limit {
1396 u8 max_bw; /* 0-3, limit = 2^max */
1400 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit);
1402 /* Enable Physical Port ETS (indirect 0x0413)
1403 * Modify Physical Port ETS (indirect 0x0414)
1404 * Disable Physical Port ETS (indirect 0x0415)
1406 struct i40e_aqc_configure_switching_comp_ets_data {
1410 u8 tc_strict_priority_flags;
1412 u8 tc_bw_share_credits[8];
1416 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data);
1418 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
1419 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data {
1422 __le16 tc_bw_credit[8];
1424 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1425 __le16 tc_bw_max[2];
1429 I40E_CHECK_STRUCT_LEN(0x40,
1430 i40e_aqc_configure_switching_comp_ets_bw_limit_data);
1432 /* Configure Switching Component Bandwidth Allocation per Tc
1435 struct i40e_aqc_configure_switching_comp_bw_config_data {
1438 u8 absolute_credits; /* bool */
1439 u8 tc_bw_share_credits[8];
1443 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data);
1445 /* Query Switching Component Configuration (indirect 0x0418) */
1446 struct i40e_aqc_query_switching_comp_ets_config_resp {
1449 __le16 port_bw_limit;
1451 u8 tc_bw_max; /* 0-3, limit = 2^max */
1455 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp);
1457 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */
1458 struct i40e_aqc_query_port_ets_config_resp {
1462 u8 tc_strict_priority_bits;
1464 u8 tc_bw_share_credits[8];
1465 __le16 tc_bw_limits[8];
1467 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
1468 __le16 tc_bw_max[2];
1472 I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp);
1474 /* Query Switching Component Bandwidth Allocation per Traffic Type
1477 struct i40e_aqc_query_switching_comp_bw_config_resp {
1480 u8 absolute_credits_enable; /* bool */
1481 u8 tc_bw_share_credits[8];
1482 __le16 tc_bw_limits[8];
1484 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1485 __le16 tc_bw_max[2];
1488 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp);
1490 /* Suspend/resume port TX traffic
1491 * (direct 0x041B and 0x041C) uses the generic SEID struct
1494 /* Configure partition BW
1497 struct i40e_aqc_configure_partition_bw_data {
1498 __le16 pf_valid_bits;
1499 u8 min_bw[16]; /* guaranteed bandwidth */
1500 u8 max_bw[16]; /* bandwidth limit */
1503 I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data);
1505 /* Get and set the active HMC resource profile and status.
1506 * (direct 0x0500) and (direct 0x0501)
1508 struct i40e_aq_get_set_hmc_resource_profile {
1514 I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile);
1516 enum i40e_aq_hmc_profile {
1517 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */
1518 I40E_HMC_PROFILE_DEFAULT = 1,
1519 I40E_HMC_PROFILE_FAVOR_VF = 2,
1520 I40E_HMC_PROFILE_EQUAL = 3,
1523 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
1525 /* set in param0 for get phy abilities to report qualified modules */
1526 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001
1527 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002
1529 enum i40e_aq_phy_type {
1530 I40E_PHY_TYPE_SGMII = 0x0,
1531 I40E_PHY_TYPE_1000BASE_KX = 0x1,
1532 I40E_PHY_TYPE_10GBASE_KX4 = 0x2,
1533 I40E_PHY_TYPE_10GBASE_KR = 0x3,
1534 I40E_PHY_TYPE_40GBASE_KR4 = 0x4,
1535 I40E_PHY_TYPE_XAUI = 0x5,
1536 I40E_PHY_TYPE_XFI = 0x6,
1537 I40E_PHY_TYPE_SFI = 0x7,
1538 I40E_PHY_TYPE_XLAUI = 0x8,
1539 I40E_PHY_TYPE_XLPPI = 0x9,
1540 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA,
1541 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB,
1542 I40E_PHY_TYPE_10GBASE_AOC = 0xC,
1543 I40E_PHY_TYPE_40GBASE_AOC = 0xD,
1544 I40E_PHY_TYPE_UNRECOGNIZED = 0xE,
1545 I40E_PHY_TYPE_UNSUPPORTED = 0xF,
1546 I40E_PHY_TYPE_100BASE_TX = 0x11,
1547 I40E_PHY_TYPE_1000BASE_T = 0x12,
1548 I40E_PHY_TYPE_10GBASE_T = 0x13,
1549 I40E_PHY_TYPE_10GBASE_SR = 0x14,
1550 I40E_PHY_TYPE_10GBASE_LR = 0x15,
1551 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16,
1552 I40E_PHY_TYPE_10GBASE_CR1 = 0x17,
1553 I40E_PHY_TYPE_40GBASE_CR4 = 0x18,
1554 I40E_PHY_TYPE_40GBASE_SR4 = 0x19,
1555 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A,
1556 I40E_PHY_TYPE_1000BASE_SX = 0x1B,
1557 I40E_PHY_TYPE_1000BASE_LX = 0x1C,
1558 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D,
1559 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E,
1560 I40E_PHY_TYPE_25GBASE_KR = 0x1F,
1561 I40E_PHY_TYPE_25GBASE_CR = 0x20,
1562 I40E_PHY_TYPE_25GBASE_SR = 0x21,
1563 I40E_PHY_TYPE_25GBASE_LR = 0x22,
1564 I40E_PHY_TYPE_25GBASE_AOC = 0x23,
1565 I40E_PHY_TYPE_25GBASE_ACC = 0x24,
1566 I40E_PHY_TYPE_2_5GBASE_T = 0x30,
1567 I40E_PHY_TYPE_5GBASE_T = 0x31,
1569 I40E_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP = 0xFD,
1570 I40E_PHY_TYPE_EMPTY = 0xFE,
1571 I40E_PHY_TYPE_DEFAULT = 0xFF,
1574 #define I40E_PHY_TYPES_BITMASK (BIT_ULL(I40E_PHY_TYPE_SGMII) | \
1575 BIT_ULL(I40E_PHY_TYPE_1000BASE_KX) | \
1576 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4) | \
1577 BIT_ULL(I40E_PHY_TYPE_10GBASE_KR) | \
1578 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4) | \
1579 BIT_ULL(I40E_PHY_TYPE_XAUI) | \
1580 BIT_ULL(I40E_PHY_TYPE_XFI) | \
1581 BIT_ULL(I40E_PHY_TYPE_SFI) | \
1582 BIT_ULL(I40E_PHY_TYPE_XLAUI) | \
1583 BIT_ULL(I40E_PHY_TYPE_XLPPI) | \
1584 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU) | \
1585 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU) | \
1586 BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC) | \
1587 BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC) | \
1588 BIT_ULL(I40E_PHY_TYPE_UNRECOGNIZED) | \
1589 BIT_ULL(I40E_PHY_TYPE_UNSUPPORTED) | \
1590 BIT_ULL(I40E_PHY_TYPE_100BASE_TX) | \
1591 BIT_ULL(I40E_PHY_TYPE_1000BASE_T) | \
1592 BIT_ULL(I40E_PHY_TYPE_10GBASE_T) | \
1593 BIT_ULL(I40E_PHY_TYPE_10GBASE_SR) | \
1594 BIT_ULL(I40E_PHY_TYPE_10GBASE_LR) | \
1595 BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU) | \
1596 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1) | \
1597 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4) | \
1598 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4) | \
1599 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4) | \
1600 BIT_ULL(I40E_PHY_TYPE_1000BASE_SX) | \
1601 BIT_ULL(I40E_PHY_TYPE_1000BASE_LX) | \
1602 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL) | \
1603 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2) | \
1604 BIT_ULL(I40E_PHY_TYPE_25GBASE_KR) | \
1605 BIT_ULL(I40E_PHY_TYPE_25GBASE_CR) | \
1606 BIT_ULL(I40E_PHY_TYPE_25GBASE_SR) | \
1607 BIT_ULL(I40E_PHY_TYPE_25GBASE_LR) | \
1608 BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC) | \
1609 BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC) | \
1610 BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T) | \
1611 BIT_ULL(I40E_PHY_TYPE_5GBASE_T))
1613 #define I40E_LINK_SPEED_2_5GB_SHIFT 0x0
1614 #define I40E_LINK_SPEED_100MB_SHIFT 0x1
1615 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2
1616 #define I40E_LINK_SPEED_10GB_SHIFT 0x3
1617 #define I40E_LINK_SPEED_40GB_SHIFT 0x4
1618 #define I40E_LINK_SPEED_20GB_SHIFT 0x5
1619 #define I40E_LINK_SPEED_25GB_SHIFT 0x6
1620 #define I40E_LINK_SPEED_5GB_SHIFT 0x7
1622 enum i40e_aq_link_speed {
1623 I40E_LINK_SPEED_UNKNOWN = 0,
1624 I40E_LINK_SPEED_100MB = BIT(I40E_LINK_SPEED_100MB_SHIFT),
1625 I40E_LINK_SPEED_1GB = BIT(I40E_LINK_SPEED_1000MB_SHIFT),
1626 I40E_LINK_SPEED_2_5GB = (1 << I40E_LINK_SPEED_2_5GB_SHIFT),
1627 I40E_LINK_SPEED_5GB = (1 << I40E_LINK_SPEED_5GB_SHIFT),
1628 I40E_LINK_SPEED_10GB = BIT(I40E_LINK_SPEED_10GB_SHIFT),
1629 I40E_LINK_SPEED_40GB = BIT(I40E_LINK_SPEED_40GB_SHIFT),
1630 I40E_LINK_SPEED_20GB = BIT(I40E_LINK_SPEED_20GB_SHIFT),
1631 I40E_LINK_SPEED_25GB = BIT(I40E_LINK_SPEED_25GB_SHIFT),
1634 struct i40e_aqc_module_desc {
1642 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc);
1644 struct i40e_aq_get_phy_abilities_resp {
1645 __le32 phy_type; /* bitmap using the above enum for offsets */
1646 u8 link_speed; /* bitmap using the above enum bit patterns */
1648 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01
1649 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02
1650 __le16 eee_capability;
1654 #define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01
1655 #define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02
1656 #define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04
1657 #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08
1658 u8 fec_cfg_curr_mod_ext_info;
1659 #define I40E_AQ_REQUEST_FEC_KR 0x04
1660 #define I40E_AQ_REQUEST_FEC_RS 0x08
1661 #define I40E_AQ_ENABLE_FEC_AUTO 0x10
1666 u8 qualified_module_count;
1667 #define I40E_AQ_PHY_MAX_QMS 16
1668 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS];
1671 I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp);
1673 /* Set PHY Config (direct 0x0601) */
1674 struct i40e_aq_set_phy_config { /* same bits as above in all */
1678 /* bits 0-2 use the values from get_phy_abilities_resp */
1679 #define I40E_AQ_PHY_ENABLE_LINK 0x08
1680 #define I40E_AQ_PHY_ENABLE_AN 0x10
1681 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20
1682 __le16 eee_capability;
1686 #define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01
1687 #define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02
1688 #define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04
1689 #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08
1691 #define I40E_AQ_SET_FEC_ABILITY_KR BIT(0)
1692 #define I40E_AQ_SET_FEC_ABILITY_RS BIT(1)
1693 #define I40E_AQ_SET_FEC_REQUEST_KR BIT(2)
1694 #define I40E_AQ_SET_FEC_REQUEST_RS BIT(3)
1695 #define I40E_AQ_SET_FEC_AUTO BIT(4)
1696 #define I40E_AQ_PHY_FEC_CONFIG_SHIFT 0x0
1697 #define I40E_AQ_PHY_FEC_CONFIG_MASK (0x1F << I40E_AQ_PHY_FEC_CONFIG_SHIFT)
1701 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);
1703 /* Set MAC Config command data structure (direct 0x0603) */
1704 struct i40e_aq_set_mac_config {
1705 __le16 max_frame_size;
1707 u8 tx_timer_priority; /* bitmap */
1708 __le16 tx_timer_value;
1709 __le16 fc_refresh_threshold;
1713 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config);
1715 /* Restart Auto-Negotiation (direct 0x605) */
1716 struct i40e_aqc_set_link_restart_an {
1718 #define I40E_AQ_PHY_RESTART_AN 0x02
1719 #define I40E_AQ_PHY_LINK_ENABLE 0x04
1723 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an);
1725 /* Get Link Status cmd & response data structure (direct 0x0607) */
1726 struct i40e_aqc_get_link_status {
1727 __le16 command_flags; /* only field set on command */
1728 #define I40E_AQ_LSE_DISABLE 0x2
1729 #define I40E_AQ_LSE_ENABLE 0x3
1730 /* only response uses this flag */
1731 #define I40E_AQ_LSE_IS_ENABLED 0x1
1732 u8 phy_type; /* i40e_aq_phy_type */
1733 u8 link_speed; /* i40e_aq_link_speed */
1735 #define I40E_AQ_LINK_UP 0x01 /* obsolete */
1736 #define I40E_AQ_MEDIA_AVAILABLE 0x40
1738 #define I40E_AQ_AN_COMPLETED 0x01
1739 #define I40E_AQ_LINK_PAUSE_TX 0x20
1740 #define I40E_AQ_LINK_PAUSE_RX 0x40
1741 #define I40E_AQ_QUALIFIED_MODULE 0x80
1743 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */
1744 /* Since firmware API 1.7 loopback field keeps power class info as well */
1745 #define I40E_AQ_LOOPBACK_MASK 0x07
1746 __le16 max_frame_size;
1748 #define I40E_AQ_CONFIG_FEC_KR_ENA 0x01
1749 #define I40E_AQ_CONFIG_FEC_RS_ENA 0x02
1750 #define I40E_AQ_CONFIG_CRC_ENA 0x04
1751 #define I40E_AQ_CONFIG_PACING_MASK 0x78
1764 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status);
1766 /* Set event mask command (direct 0x613) */
1767 struct i40e_aqc_set_phy_int_mask {
1770 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002
1771 #define I40E_AQ_EVENT_MEDIA_NA 0x0004
1772 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100
1776 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask);
1778 /* Get Local AN advt register (direct 0x0614)
1779 * Set Local AN advt register (direct 0x0615)
1780 * Get Link Partner AN advt register (direct 0x0616)
1782 struct i40e_aqc_an_advt_reg {
1783 __le32 local_an_reg0;
1784 __le16 local_an_reg1;
1788 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg);
1790 /* Set Loopback mode (0x0618) */
1791 struct i40e_aqc_set_lb_mode {
1793 #define I40E_AQ_LB_PHY_LOCAL 0x01
1794 #define I40E_AQ_LB_PHY_REMOTE 0x02
1795 #define I40E_AQ_LB_MAC_LOCAL 0x04
1799 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode);
1801 /* Set PHY Debug command (0x0622) */
1802 struct i40e_aqc_set_phy_debug {
1804 /* Disable link manageability on a single port */
1805 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10
1806 /* Disable link manageability on all ports */
1807 #define I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW 0x20
1811 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug);
1813 enum i40e_aq_phy_reg_type {
1814 I40E_AQC_PHY_REG_INTERNAL = 0x1,
1815 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2,
1816 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3
1819 /* Run PHY Activity (0x0626) */
1820 struct i40e_aqc_run_phy_activity {
1829 I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity);
1831 /* Set PHY Register command (0x0628) */
1832 /* Get PHY Register command (0x0629) */
1833 struct i40e_aqc_phy_register_access {
1835 #define I40E_AQ_PHY_REG_ACCESS_EXTERNAL 1
1836 #define I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE 2
1839 #define I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE 0x01
1840 #define I40E_AQ_PHY_REG_ACCESS_SET_MDIO_IF_NUMBER 0x02
1841 #define I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_SHIFT 2
1842 #define I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_MASK (0x3 << \
1843 I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_SHIFT)
1850 I40E_CHECK_CMD_LENGTH(i40e_aqc_phy_register_access);
1852 /* NVM Read command (indirect 0x0701)
1853 * NVM Erase commands (direct 0x0702)
1854 * NVM Update commands (indirect 0x0703)
1856 struct i40e_aqc_nvm_update {
1858 #define I40E_AQ_NVM_LAST_CMD 0x01
1859 #define I40E_AQ_NVM_REARRANGE_TO_FLAT 0x20
1860 #define I40E_AQ_NVM_REARRANGE_TO_STRUCT 0x40
1861 #define I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT 1
1862 #define I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED 0x03
1863 #define I40E_AQ_NVM_PRESERVATION_FLAGS_ALL 0x01
1871 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);
1873 /* NVM Config Read (indirect 0x0704) */
1874 struct i40e_aqc_nvm_config_read {
1876 __le16 element_count;
1877 __le16 element_id; /* Feature/field ID */
1878 __le16 element_id_msw; /* MSWord of field ID */
1879 __le32 address_high;
1883 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read);
1885 /* NVM Config Write (indirect 0x0705) */
1886 struct i40e_aqc_nvm_config_write {
1888 __le16 element_count;
1890 __le32 address_high;
1894 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);
1896 /* Used for 0x0704 as well as for 0x0705 commands */
1897 struct i40e_aqc_nvm_config_data_feature {
1899 __le16 feature_options;
1900 __le16 feature_selection;
1903 I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature);
1905 struct i40e_aqc_nvm_config_data_immediate_field {
1908 __le16 field_options;
1912 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field);
1914 /* OEM Post Update (indirect 0x0720)
1915 * no command data struct used
1917 struct i40e_aqc_nvm_oem_post_update {
1922 I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update);
1924 struct i40e_aqc_nvm_oem_post_update_buffer {
1931 I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer);
1933 /* Thermal Sensor (indirect 0x0721)
1934 * read or set thermal sensor configs and values
1935 * takes a sensor and command specific data buffer, not detailed here
1937 struct i40e_aqc_thermal_sensor {
1944 I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor);
1946 /* Send to PF command (indirect 0x0801) id is only used by PF
1947 * Send to VF command (indirect 0x0802) id is only used by PF
1948 * Send to Peer PF command (indirect 0x0803)
1950 struct i40e_aqc_pf_vf_message {
1957 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message);
1959 /* Alternate structure */
1961 /* Direct write (direct 0x0900)
1962 * Direct read (direct 0x0902)
1964 struct i40e_aqc_alternate_write {
1971 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write);
1973 /* Indirect write (indirect 0x0901)
1974 * Indirect read (indirect 0x0903)
1977 struct i40e_aqc_alternate_ind_write {
1984 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write);
1986 /* Done alternate write (direct 0x0904)
1989 struct i40e_aqc_alternate_write_done {
1994 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done);
1996 /* Set OEM mode (direct 0x0905) */
1997 struct i40e_aqc_alternate_set_mode {
2002 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode);
2004 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */
2006 /* async events 0x10xx */
2008 /* Lan Queue Overflow Event (direct, 0x1001) */
2009 struct i40e_aqc_lan_overflow {
2010 __le32 prtdcb_rupto;
2015 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow);
2017 /* Get LLDP MIB (indirect 0x0A00) */
2018 struct i40e_aqc_lldp_get_mib {
2021 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3
2022 #define I40E_AQ_LLDP_MIB_LOCAL 0x0
2023 #define I40E_AQ_LLDP_MIB_REMOTE 0x1
2024 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC
2025 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2
2026 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0
2027 /* TX pause flags use I40E_AQ_LINK_TX_* above */
2035 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib);
2037 /* Configure LLDP MIB Change Event (direct 0x0A01)
2038 * also used for the event (with type in the command field)
2040 struct i40e_aqc_lldp_update_mib {
2042 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1
2048 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib);
2050 /* Add LLDP TLV (indirect 0x0A02)
2051 * Delete LLDP TLV (indirect 0x0A04)
2053 struct i40e_aqc_lldp_add_tlv {
2054 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2062 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv);
2064 /* Update LLDP TLV (indirect 0x0A03) */
2065 struct i40e_aqc_lldp_update_tlv {
2066 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2075 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv);
2077 /* Stop LLDP (direct 0x0A05) */
2078 struct i40e_aqc_lldp_stop {
2080 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1
2081 #define I40E_AQ_LLDP_AGENT_STOP_PERSIST 0x2
2085 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop);
2087 /* Start LLDP (direct 0x0A06) */
2088 struct i40e_aqc_lldp_start {
2090 #define I40E_AQ_LLDP_AGENT_START 0x1
2091 #define I40E_AQ_LLDP_AGENT_START_PERSIST 0x2
2095 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start);
2097 /* Set DCB (direct 0x0303) */
2098 struct i40e_aqc_set_dcb_parameters {
2100 #define I40E_AQ_DCB_SET_AGENT 0x1
2101 #define I40E_DCB_VALID 0x1
2106 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_dcb_parameters);
2108 /* Get CEE DCBX Oper Config (0x0A07)
2109 * uses the generic descriptor struct
2110 * returns below as indirect response
2113 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0
2114 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT)
2115 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3
2116 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
2117 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8
2118 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2120 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0
2121 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
2122 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3
2123 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
2124 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8
2125 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
2126 #define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8
2127 #define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT)
2128 #define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB
2129 #define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT)
2130 #define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10
2131 #define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT)
2133 /* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with
2134 * word boundary layout issues, which the Linux compilers silently deal
2135 * with by adding padding, making the actual struct larger than designed.
2136 * However, the FW compiler for the NIC is less lenient and complains
2137 * about the struct. Hence, the struct defined here has an extra byte in
2138 * fields reserved3 and reserved4 to directly acknowledge that padding,
2139 * and the new length is used in the length check macro.
2141 struct i40e_aqc_get_cee_dcb_cfg_v1_resp {
2149 __le16 oper_app_prio;
2154 I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp);
2156 struct i40e_aqc_get_cee_dcb_cfg_resp {
2161 __le16 oper_app_prio;
2162 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0
2163 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT)
2164 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3
2165 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
2166 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8
2167 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2168 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2170 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0
2171 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
2172 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3
2173 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
2174 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8
2175 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
2179 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp);
2181 /* Set Local LLDP MIB (indirect 0x0A08)
2182 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx
2184 struct i40e_aqc_lldp_set_local_mib {
2189 __le32 address_high;
2193 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib);
2195 /* Stop/Start LLDP Agent (direct 0x0A09)
2196 * Used for stopping/starting specific LLDP agent. e.g. DCBx
2198 struct i40e_aqc_lldp_stop_start_specific_agent {
2203 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent);
2205 /* Restore LLDP Agent factory settings (direct 0x0A0A) */
2206 struct i40e_aqc_lldp_restore {
2208 #define I40E_AQ_LLDP_AGENT_RESTORE 0x1
2212 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_restore);
2214 /* Add Udp Tunnel command and completion (direct 0x0B00) */
2215 struct i40e_aqc_add_udp_tunnel {
2219 #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00
2220 #define I40E_AQC_TUNNEL_TYPE_NGE 0x01
2224 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel);
2226 struct i40e_aqc_add_udp_tunnel_completion {
2228 u8 filter_entry_index;
2234 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion);
2236 /* remove UDP Tunnel command (0x0B01) */
2237 struct i40e_aqc_remove_udp_tunnel {
2239 u8 index; /* 0 to 15 */
2243 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel);
2245 struct i40e_aqc_del_udp_tunnel_completion {
2247 u8 index; /* 0 to 15 */
2249 u8 total_filters_used;
2253 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);
2255 struct i40e_aqc_get_set_rss_key {
2256 #define I40E_AQC_SET_RSS_KEY_VSI_VALID BIT(15)
2257 #define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0
2258 #define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \
2259 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT)
2266 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key);
2268 struct i40e_aqc_get_set_rss_key_data {
2269 u8 standard_rss_key[0x28];
2270 u8 extended_hash_key[0xc];
2273 I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data);
2275 struct i40e_aqc_get_set_rss_lut {
2276 #define I40E_AQC_SET_RSS_LUT_VSI_VALID BIT(15)
2277 #define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0
2278 #define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \
2279 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT)
2281 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0
2282 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK BIT(I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT)
2284 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0
2285 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1
2292 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut);
2294 /* tunnel key structure 0x0B10 */
2296 struct i40e_aqc_tunnel_key_structure {
2299 u8 key1_len; /* 0 to 15 */
2300 u8 key2_len; /* 0 to 15 */
2302 u8 network_key_index;
2306 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure);
2308 /* OEM mode commands (direct 0xFE0x) */
2309 struct i40e_aqc_oem_param_change {
2311 __le32 param_value1;
2312 __le16 param_value2;
2316 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change);
2318 struct i40e_aqc_oem_state_change {
2323 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change);
2325 /* Initialize OCSD (0xFE02, direct) */
2326 struct i40e_aqc_opc_oem_ocsd_initialize {
2329 __le32 ocsd_memory_block_addr_high;
2330 __le32 ocsd_memory_block_addr_low;
2331 __le32 requested_update_interval;
2334 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize);
2336 /* Initialize OCBB (0xFE03, direct) */
2337 struct i40e_aqc_opc_oem_ocbb_initialize {
2340 __le32 ocbb_memory_block_addr_high;
2341 __le32 ocbb_memory_block_addr_low;
2345 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize);
2347 /* debug commands */
2349 /* get device id (0xFF00) uses the generic structure */
2351 /* set test more (0xFF01, internal) */
2353 struct i40e_acq_set_test_mode {
2358 __le32 address_high;
2362 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode);
2364 /* Debug Read Register command (0xFF03)
2365 * Debug Write Register command (0xFF04)
2367 struct i40e_aqc_debug_reg_read_write {
2374 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write);
2376 /* Scatter/gather Reg Read (indirect 0xFF05)
2377 * Scatter/gather Reg Write (indirect 0xFF06)
2380 /* i40e_aq_desc is used for the command */
2381 struct i40e_aqc_debug_reg_sg_element_data {
2386 /* Debug Modify register (direct 0xFF07) */
2387 struct i40e_aqc_debug_modify_reg {
2394 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg);
2396 /* dump internal data (0xFF08, indirect) */
2397 struct i40e_aqc_debug_dump_internals {
2402 __le32 address_high;
2406 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals);
2408 struct i40e_aqc_debug_modify_internals {
2410 u8 cluster_specific_params[7];
2411 __le32 address_high;
2415 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals);
2417 #endif /* _I40E_ADMINQ_CMD_H_ */