1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
4 #ifndef _I40E_ADMINQ_CMD_H_
5 #define _I40E_ADMINQ_CMD_H_
7 /* This header file defines the i40e Admin Queue commands and is shared between
8 * i40e Firmware and Software.
10 * This file needs to comply with the Linux Kernel coding style.
13 #define I40E_FW_API_VERSION_MAJOR 0x0001
14 #define I40E_FW_API_VERSION_MINOR_X722 0x0009
15 #define I40E_FW_API_VERSION_MINOR_X710 0x0009
17 #define I40E_FW_MINOR_VERSION(_h) ((_h)->mac.type == I40E_MAC_XL710 ? \
18 I40E_FW_API_VERSION_MINOR_X710 : \
19 I40E_FW_API_VERSION_MINOR_X722)
21 /* API version 1.7 implements additional link and PHY-specific APIs */
22 #define I40E_MINOR_VER_GET_LINK_INFO_XL710 0x0007
23 /* API version 1.9 for X722 implements additional link and PHY-specific APIs */
24 #define I40E_MINOR_VER_GET_LINK_INFO_X722 0x0009
25 /* API version 1.6 for X722 devices adds ability to stop FW LLDP agent */
26 #define I40E_MINOR_VER_FW_LLDP_STOPPABLE_X722 0x0006
27 /* API version 1.10 for X722 devices adds ability to request FEC encoding */
28 #define I40E_MINOR_VER_FW_REQUEST_FEC_X722 0x000A
54 /* Flags sub-structure
55 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
56 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
59 /* command flags and offsets*/
60 #define I40E_AQ_FLAG_ERR_SHIFT 2
61 #define I40E_AQ_FLAG_LB_SHIFT 9
62 #define I40E_AQ_FLAG_RD_SHIFT 10
63 #define I40E_AQ_FLAG_BUF_SHIFT 12
64 #define I40E_AQ_FLAG_SI_SHIFT 13
66 #define I40E_AQ_FLAG_ERR BIT(I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */
67 #define I40E_AQ_FLAG_LB BIT(I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */
68 #define I40E_AQ_FLAG_RD BIT(I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */
69 #define I40E_AQ_FLAG_BUF BIT(I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
70 #define I40E_AQ_FLAG_SI BIT(I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */
73 enum i40e_admin_queue_err {
74 I40E_AQ_RC_OK = 0, /* success */
75 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */
76 I40E_AQ_RC_ENOENT = 2, /* No such element */
77 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */
78 I40E_AQ_RC_EINTR = 4, /* operation interrupted */
79 I40E_AQ_RC_EIO = 5, /* I/O error */
80 I40E_AQ_RC_ENXIO = 6, /* No such resource */
81 I40E_AQ_RC_E2BIG = 7, /* Arg too long */
82 I40E_AQ_RC_EAGAIN = 8, /* Try again */
83 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */
84 I40E_AQ_RC_EACCES = 10, /* Permission denied */
85 I40E_AQ_RC_EFAULT = 11, /* Bad address */
86 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */
87 I40E_AQ_RC_EEXIST = 13, /* object already exists */
88 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */
89 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */
90 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */
91 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */
92 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */
93 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */
94 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */
95 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
96 I40E_AQ_RC_EFBIG = 22, /* File too large */
99 /* Admin Queue command opcodes */
100 enum i40e_admin_queue_opc {
102 i40e_aqc_opc_get_version = 0x0001,
103 i40e_aqc_opc_driver_version = 0x0002,
104 i40e_aqc_opc_queue_shutdown = 0x0003,
105 i40e_aqc_opc_set_pf_context = 0x0004,
107 /* resource ownership */
108 i40e_aqc_opc_request_resource = 0x0008,
109 i40e_aqc_opc_release_resource = 0x0009,
111 i40e_aqc_opc_list_func_capabilities = 0x000A,
112 i40e_aqc_opc_list_dev_capabilities = 0x000B,
115 i40e_aqc_opc_set_proxy_config = 0x0104,
116 i40e_aqc_opc_set_ns_proxy_table_entry = 0x0105,
119 i40e_aqc_opc_mac_address_read = 0x0107,
120 i40e_aqc_opc_mac_address_write = 0x0108,
123 i40e_aqc_opc_clear_pxe_mode = 0x0110,
126 i40e_aqc_opc_set_wol_filter = 0x0120,
127 i40e_aqc_opc_get_wake_reason = 0x0121,
129 /* internal switch commands */
130 i40e_aqc_opc_get_switch_config = 0x0200,
131 i40e_aqc_opc_add_statistics = 0x0201,
132 i40e_aqc_opc_remove_statistics = 0x0202,
133 i40e_aqc_opc_set_port_parameters = 0x0203,
134 i40e_aqc_opc_get_switch_resource_alloc = 0x0204,
135 i40e_aqc_opc_set_switch_config = 0x0205,
136 i40e_aqc_opc_rx_ctl_reg_read = 0x0206,
137 i40e_aqc_opc_rx_ctl_reg_write = 0x0207,
139 i40e_aqc_opc_add_vsi = 0x0210,
140 i40e_aqc_opc_update_vsi_parameters = 0x0211,
141 i40e_aqc_opc_get_vsi_parameters = 0x0212,
143 i40e_aqc_opc_add_pv = 0x0220,
144 i40e_aqc_opc_update_pv_parameters = 0x0221,
145 i40e_aqc_opc_get_pv_parameters = 0x0222,
147 i40e_aqc_opc_add_veb = 0x0230,
148 i40e_aqc_opc_update_veb_parameters = 0x0231,
149 i40e_aqc_opc_get_veb_parameters = 0x0232,
151 i40e_aqc_opc_delete_element = 0x0243,
153 i40e_aqc_opc_add_macvlan = 0x0250,
154 i40e_aqc_opc_remove_macvlan = 0x0251,
155 i40e_aqc_opc_add_vlan = 0x0252,
156 i40e_aqc_opc_remove_vlan = 0x0253,
157 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254,
158 i40e_aqc_opc_add_tag = 0x0255,
159 i40e_aqc_opc_remove_tag = 0x0256,
160 i40e_aqc_opc_add_multicast_etag = 0x0257,
161 i40e_aqc_opc_remove_multicast_etag = 0x0258,
162 i40e_aqc_opc_update_tag = 0x0259,
163 i40e_aqc_opc_add_control_packet_filter = 0x025A,
164 i40e_aqc_opc_remove_control_packet_filter = 0x025B,
165 i40e_aqc_opc_add_cloud_filters = 0x025C,
166 i40e_aqc_opc_remove_cloud_filters = 0x025D,
167 i40e_aqc_opc_clear_wol_switch_filters = 0x025E,
169 i40e_aqc_opc_add_mirror_rule = 0x0260,
170 i40e_aqc_opc_delete_mirror_rule = 0x0261,
172 /* Dynamic Device Personalization */
173 i40e_aqc_opc_write_personalization_profile = 0x0270,
174 i40e_aqc_opc_get_personalization_profile_list = 0x0271,
177 i40e_aqc_opc_dcb_ignore_pfc = 0x0301,
178 i40e_aqc_opc_dcb_updated = 0x0302,
179 i40e_aqc_opc_set_dcb_parameters = 0x0303,
182 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400,
183 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406,
184 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407,
185 i40e_aqc_opc_query_vsi_bw_config = 0x0408,
186 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A,
187 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410,
189 i40e_aqc_opc_enable_switching_comp_ets = 0x0413,
190 i40e_aqc_opc_modify_switching_comp_ets = 0x0414,
191 i40e_aqc_opc_disable_switching_comp_ets = 0x0415,
192 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416,
193 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417,
194 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418,
195 i40e_aqc_opc_query_port_ets_config = 0x0419,
196 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A,
197 i40e_aqc_opc_suspend_port_tx = 0x041B,
198 i40e_aqc_opc_resume_port_tx = 0x041C,
199 i40e_aqc_opc_configure_partition_bw = 0x041D,
201 i40e_aqc_opc_query_hmc_resource_profile = 0x0500,
202 i40e_aqc_opc_set_hmc_resource_profile = 0x0501,
205 i40e_aqc_opc_get_phy_abilities = 0x0600,
206 i40e_aqc_opc_set_phy_config = 0x0601,
207 i40e_aqc_opc_set_mac_config = 0x0603,
208 i40e_aqc_opc_set_link_restart_an = 0x0605,
209 i40e_aqc_opc_get_link_status = 0x0607,
210 i40e_aqc_opc_set_phy_int_mask = 0x0613,
211 i40e_aqc_opc_get_local_advt_reg = 0x0614,
212 i40e_aqc_opc_set_local_advt_reg = 0x0615,
213 i40e_aqc_opc_get_partner_advt = 0x0616,
214 i40e_aqc_opc_set_lb_modes = 0x0618,
215 i40e_aqc_opc_get_phy_wol_caps = 0x0621,
216 i40e_aqc_opc_set_phy_debug = 0x0622,
217 i40e_aqc_opc_upload_ext_phy_fm = 0x0625,
218 i40e_aqc_opc_run_phy_activity = 0x0626,
219 i40e_aqc_opc_set_phy_register = 0x0628,
220 i40e_aqc_opc_get_phy_register = 0x0629,
223 i40e_aqc_opc_nvm_read = 0x0701,
224 i40e_aqc_opc_nvm_erase = 0x0702,
225 i40e_aqc_opc_nvm_update = 0x0703,
226 i40e_aqc_opc_nvm_config_read = 0x0704,
227 i40e_aqc_opc_nvm_config_write = 0x0705,
228 i40e_aqc_opc_oem_post_update = 0x0720,
229 i40e_aqc_opc_thermal_sensor = 0x0721,
231 /* virtualization commands */
232 i40e_aqc_opc_send_msg_to_pf = 0x0801,
233 i40e_aqc_opc_send_msg_to_vf = 0x0802,
234 i40e_aqc_opc_send_msg_to_peer = 0x0803,
236 /* alternate structure */
237 i40e_aqc_opc_alternate_write = 0x0900,
238 i40e_aqc_opc_alternate_write_indirect = 0x0901,
239 i40e_aqc_opc_alternate_read = 0x0902,
240 i40e_aqc_opc_alternate_read_indirect = 0x0903,
241 i40e_aqc_opc_alternate_write_done = 0x0904,
242 i40e_aqc_opc_alternate_set_mode = 0x0905,
243 i40e_aqc_opc_alternate_clear_port = 0x0906,
246 i40e_aqc_opc_lldp_get_mib = 0x0A00,
247 i40e_aqc_opc_lldp_update_mib = 0x0A01,
248 i40e_aqc_opc_lldp_add_tlv = 0x0A02,
249 i40e_aqc_opc_lldp_update_tlv = 0x0A03,
250 i40e_aqc_opc_lldp_delete_tlv = 0x0A04,
251 i40e_aqc_opc_lldp_stop = 0x0A05,
252 i40e_aqc_opc_lldp_start = 0x0A06,
253 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07,
254 i40e_aqc_opc_lldp_set_local_mib = 0x0A08,
255 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09,
256 i40e_aqc_opc_lldp_restore = 0x0A0A,
258 /* Tunnel commands */
259 i40e_aqc_opc_add_udp_tunnel = 0x0B00,
260 i40e_aqc_opc_del_udp_tunnel = 0x0B01,
261 i40e_aqc_opc_set_rss_key = 0x0B02,
262 i40e_aqc_opc_set_rss_lut = 0x0B03,
263 i40e_aqc_opc_get_rss_key = 0x0B04,
264 i40e_aqc_opc_get_rss_lut = 0x0B05,
267 i40e_aqc_opc_event_lan_overflow = 0x1001,
270 i40e_aqc_opc_oem_parameter_change = 0xFE00,
271 i40e_aqc_opc_oem_device_status_change = 0xFE01,
272 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02,
273 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03,
276 i40e_aqc_opc_debug_read_reg = 0xFF03,
277 i40e_aqc_opc_debug_write_reg = 0xFF04,
278 i40e_aqc_opc_debug_modify_reg = 0xFF07,
279 i40e_aqc_opc_debug_dump_internals = 0xFF08,
282 /* command structures and indirect data structures */
284 /* Structure naming conventions:
285 * - no suffix for direct command descriptor structures
286 * - _data for indirect sent data
287 * - _resp for indirect return data (data which is both will use _data)
288 * - _completion for direct return data
289 * - _element_ for repeated elements (may also be _data or _resp)
291 * Command structures are expected to overlay the params.raw member of the basic
292 * descriptor, and as such cannot exceed 16 bytes in length.
295 /* This macro is used to generate a compilation error if a structure
296 * is not exactly the correct length. It gives a divide by zero error if the
297 * structure is not of the correct size, otherwise it creates an enum that is
300 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \
301 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
303 /* This macro is used extensively to ensure that command structures are 16
304 * bytes in length as they have to map to the raw array of that size.
306 #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X)
308 /* internal (0x00XX) commands */
310 /* Get version (direct 0x0001) */
311 struct i40e_aqc_get_version {
320 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version);
322 /* Send driver version (indirect 0x0002) */
323 struct i40e_aqc_driver_version {
327 u8 driver_subbuild_ver;
333 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version);
335 /* Queue Shutdown (direct 0x0003) */
336 struct i40e_aqc_queue_shutdown {
337 __le32 driver_unloading;
338 #define I40E_AQ_DRIVER_UNLOADING 0x1
342 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);
344 /* Set PF context (0x0004, direct) */
345 struct i40e_aqc_set_pf_context {
350 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context);
352 /* Request resource ownership (direct 0x0008)
353 * Release resource ownership (direct 0x0009)
355 struct i40e_aqc_request_resource {
359 __le32 resource_number;
363 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource);
365 /* Get function capabilities (indirect 0x000A)
366 * Get device capabilities (indirect 0x000B)
368 struct i40e_aqc_list_capabilites {
377 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites);
379 struct i40e_aqc_list_capabilities_element_resp {
391 #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001
392 #define I40E_AQ_CAP_ID_MNG_MODE 0x0002
393 #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003
394 #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004
395 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005
396 #define I40E_AQ_CAP_ID_SRIOV 0x0012
397 #define I40E_AQ_CAP_ID_VF 0x0013
398 #define I40E_AQ_CAP_ID_VMDQ 0x0014
399 #define I40E_AQ_CAP_ID_8021QBG 0x0015
400 #define I40E_AQ_CAP_ID_8021QBR 0x0016
401 #define I40E_AQ_CAP_ID_VSI 0x0017
402 #define I40E_AQ_CAP_ID_DCB 0x0018
403 #define I40E_AQ_CAP_ID_FCOE 0x0021
404 #define I40E_AQ_CAP_ID_ISCSI 0x0022
405 #define I40E_AQ_CAP_ID_RSS 0x0040
406 #define I40E_AQ_CAP_ID_RXQ 0x0041
407 #define I40E_AQ_CAP_ID_TXQ 0x0042
408 #define I40E_AQ_CAP_ID_MSIX 0x0043
409 #define I40E_AQ_CAP_ID_VF_MSIX 0x0044
410 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045
411 #define I40E_AQ_CAP_ID_1588 0x0046
412 #define I40E_AQ_CAP_ID_IWARP 0x0051
413 #define I40E_AQ_CAP_ID_LED 0x0061
414 #define I40E_AQ_CAP_ID_SDP 0x0062
415 #define I40E_AQ_CAP_ID_MDIO 0x0063
416 #define I40E_AQ_CAP_ID_WSR_PROT 0x0064
417 #define I40E_AQ_CAP_ID_NVM_MGMT 0x0080
418 #define I40E_AQ_CAP_ID_FLEX10 0x00F1
419 #define I40E_AQ_CAP_ID_CEM 0x00F2
421 /* Set CPPM Configuration (direct 0x0103) */
422 struct i40e_aqc_cppm_configuration {
423 __le16 command_flags;
432 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration);
434 /* Set ARP Proxy command / response (indirect 0x0104) */
435 struct i40e_aqc_arp_proxy_data {
436 __le16 command_flags;
438 __le32 enabled_offloads;
444 I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data);
446 /* Set NS Proxy Table Entry Command (indirect 0x0105) */
447 struct i40e_aqc_ns_proxy_data {
448 __le16 table_idx_mac_addr_0;
449 __le16 table_idx_mac_addr_1;
450 __le16 table_idx_ipv6_0;
451 __le16 table_idx_ipv6_1;
455 u8 local_mac_addr[6];
456 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */
460 I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data);
462 /* Manage LAA Command (0x0106) - obsolete */
463 struct i40e_aqc_mng_laa {
464 __le16 command_flags;
471 I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa);
473 /* Manage MAC Address Read Command (indirect 0x0107) */
474 struct i40e_aqc_mac_address_read {
475 __le16 command_flags;
476 #define I40E_AQC_LAN_ADDR_VALID 0x10
477 #define I40E_AQC_PORT_ADDR_VALID 0x40
483 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read);
485 struct i40e_aqc_mac_address_read_data {
492 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data);
494 /* Manage MAC Address Write Command (0x0108) */
495 struct i40e_aqc_mac_address_write {
496 __le16 command_flags;
497 #define I40E_AQC_MC_MAG_EN 0x0100
498 #define I40E_AQC_WOL_PRESERVE_ON_PFR 0x0200
499 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000
500 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000
501 #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000
508 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write);
510 /* PXE commands (0x011x) */
512 /* Clear PXE Command and response (direct 0x0110) */
513 struct i40e_aqc_clear_pxe {
518 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe);
520 /* Set WoL Filter (0x0120) */
522 struct i40e_aqc_set_wol_filter {
532 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_wol_filter);
534 struct i40e_aqc_set_wol_filter_data {
539 I40E_CHECK_STRUCT_LEN(0x90, i40e_aqc_set_wol_filter_data);
541 /* Get Wake Reason (0x0121) */
543 struct i40e_aqc_get_wake_reason_completion {
549 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_wake_reason_completion);
551 /* Switch configuration commands (0x02xx) */
553 /* Used by many indirect commands that only pass an seid and a buffer in the
556 struct i40e_aqc_switch_seid {
563 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid);
565 /* Get Switch Configuration command (indirect 0x0200)
566 * uses i40e_aqc_switch_seid for the descriptor
568 struct i40e_aqc_get_switch_config_header_resp {
574 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp);
576 struct i40e_aqc_switch_config_element_resp {
581 __le16 downlink_seid;
588 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp);
590 /* Get Switch Configuration (indirect 0x0200)
591 * an array of elements are returned in the response buffer
592 * the first in the array is the header, remainder are elements
594 struct i40e_aqc_get_switch_config_resp {
595 struct i40e_aqc_get_switch_config_header_resp header;
596 struct i40e_aqc_switch_config_element_resp element[1];
599 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp);
601 /* Add Statistics (direct 0x0201)
602 * Remove Statistics (direct 0x0202)
604 struct i40e_aqc_add_remove_statistics {
611 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics);
613 /* Set Port Parameters command (direct 0x0203) */
614 struct i40e_aqc_set_port_parameters {
615 __le16 command_flags;
616 __le16 bad_frame_vsi;
617 __le16 default_seid; /* reserved for command */
621 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters);
623 /* Get Switch Resource Allocation (indirect 0x0204) */
624 struct i40e_aqc_get_switch_resource_alloc {
625 u8 num_entries; /* reserved for command */
631 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc);
633 /* expect an array of these structs in the response buffer */
634 struct i40e_aqc_switch_resource_alloc_element_resp {
640 __le16 total_unalloced;
644 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp);
646 /* Set Switch Configuration (direct 0x0205) */
647 struct i40e_aqc_set_switch_config {
649 /* flags used for both fields below */
650 #define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001
652 /* The ethertype in switch_tag is dropped on ingress and used
653 * internally by the switch. Set this to zero for the default
654 * of 0x88a8 (802.1ad). Should be zero for firmware API
655 * versions lower than 1.7.
658 /* The ethertypes in first_tag and second_tag are used to
659 * match the outer and inner VLAN tags (respectively) when HW
660 * double VLAN tagging is enabled via the set port parameters
661 * AQ command. Otherwise these are both ignored. Set them to
662 * zero for their defaults of 0x8100 (802.1Q). Should be zero
663 * for firmware API versions lower than 1.7.
667 /* Next byte is split into following:
668 * Bit 7 : 0 : No action, 1: Switch to mode defined by bits 6:0
669 * Bit 6 : 0 : Destination Port, 1: source port
674 * 3: Both TCP and UDP
677 * 1: L4 port only mode
678 * 2: non-tunneled mode
681 #define I40E_AQ_SET_SWITCH_BIT7_VALID 0x80
684 #define I40E_AQ_SET_SWITCH_L4_TYPE_TCP 0x10
686 #define I40E_AQ_SET_SWITCH_MODE_NON_TUNNEL 0x02
691 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config);
693 /* Read Receive control registers (direct 0x0206)
694 * Write Receive control registers (direct 0x0207)
695 * used for accessing Rx control registers that can be
696 * slow and need special handling when under high Rx load
698 struct i40e_aqc_rx_ctl_reg_read_write {
705 I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write);
707 /* Add VSI (indirect 0x0210)
708 * this indirect command uses struct i40e_aqc_vsi_properties_data
709 * as the indirect buffer (128 bytes)
711 * Update VSI (indirect 0x211)
712 * uses the same data structure as Add VSI
714 * Get VSI (indirect 0x0212)
715 * uses the same completion and data structure as Add VSI
717 struct i40e_aqc_add_get_update_vsi {
720 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1
725 #define I40E_AQ_VSI_TYPE_VF 0x0
726 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1
727 #define I40E_AQ_VSI_TYPE_PF 0x2
732 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi);
734 struct i40e_aqc_add_get_update_vsi_completion {
743 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion);
745 struct i40e_aqc_vsi_properties_data {
746 /* first 96 byte are written by SW */
747 __le16 valid_sections;
748 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001
749 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002
750 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004
751 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040
752 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080
753 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200
755 __le16 switch_id; /* 12bit id combined with flags below */
756 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000
757 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)
758 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000
759 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000
761 /* security section */
763 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02
764 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04
767 __le16 pvid; /* VLANS include priority bits */
770 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00
771 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \
772 I40E_AQ_VSI_PVLAN_MODE_SHIFT)
773 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01
774 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03
775 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04
776 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03
777 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \
778 I40E_AQ_VSI_PVLAN_EMOD_SHIFT)
779 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0
780 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10
781 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18
782 u8 pvlan_reserved[3];
783 /* ingress egress up sections */
784 __le32 ingress_table; /* bitmap, 3 bits per up */
785 __le32 egress_table; /* same defines as for ingress table */
786 /* cascaded PV section */
790 /* queue mapping section */
791 __le16 mapping_flags;
792 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0
793 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1
794 __le16 queue_mapping[16];
795 __le16 tc_mapping[8];
796 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0
797 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9
798 /* queueing option section */
799 u8 queueing_opt_flags;
800 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10
801 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40
802 u8 queueing_opt_reserved[3];
803 /* scheduler section */
806 /* outer up section */
807 __le32 outer_up_table; /* same structure and defines as ingress tbl */
809 /* last 32 bytes are written by FW */
811 #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF
812 __le16 stat_counter_idx;
814 u8 resp_reserved[12];
817 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data);
819 /* Add Port Virtualizer (direct 0x0220)
820 * also used for update PV (direct 0x0221) but only flags are used
821 * (IS_CTRL_PORT only works on add PV)
823 struct i40e_aqc_add_update_pv {
824 __le16 command_flags;
826 __le16 connected_seid;
830 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv);
832 struct i40e_aqc_add_update_pv_completion {
833 /* reserved for update; for add also encodes error if rc == ENOSPC */
838 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion);
840 /* Get PV Params (direct 0x0222)
841 * uses i40e_aqc_switch_seid for the descriptor
844 struct i40e_aqc_get_pv_params_completion {
847 __le16 pv_flags; /* same flags as add_pv */
849 __le16 default_port_seid;
852 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion);
854 /* Add VEB (direct 0x0230) */
855 struct i40e_aqc_add_veb {
857 __le16 downlink_seid;
859 #define I40E_AQC_ADD_VEB_FLOATING 0x1
860 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2
861 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4
862 #define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10
867 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb);
869 struct i40e_aqc_add_veb_completion {
872 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */
874 __le16 statistic_index;
879 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion);
881 /* Get VEB Parameters (direct 0x0232)
882 * uses i40e_aqc_switch_seid for the descriptor
884 struct i40e_aqc_get_veb_parameters_completion {
887 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */
888 __le16 statistic_index;
894 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion);
896 /* Delete Element (direct 0x0243)
897 * uses the generic i40e_aqc_switch_seid
900 /* Add MAC-VLAN (indirect 0x0250) */
902 /* used for the command for most vlan commands */
903 struct i40e_aqc_macvlan {
904 __le16 num_addresses;
906 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000
911 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan);
913 /* indirect data for command and response */
914 struct i40e_aqc_add_macvlan_element_data {
918 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001
919 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004
920 #define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010
922 /* response section */
924 #define I40E_AQC_MM_ERR_NO_RES 0xFF
928 struct i40e_aqc_add_remove_macvlan_completion {
929 __le16 perfect_mac_used;
930 __le16 perfect_mac_free;
931 __le16 unicast_hash_free;
932 __le16 multicast_hash_free;
937 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion);
939 /* Remove MAC-VLAN (indirect 0x0251)
940 * uses i40e_aqc_macvlan for the descriptor
941 * data points to an array of num_addresses of elements
944 struct i40e_aqc_remove_macvlan_element_data {
948 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01
949 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08
953 u8 reply_reserved[3];
956 /* Add VLAN (indirect 0x0252)
957 * Remove VLAN (indirect 0x0253)
958 * use the generic i40e_aqc_macvlan for the command
960 struct i40e_aqc_add_remove_vlan_element_data {
968 struct i40e_aqc_add_remove_vlan_completion {
976 /* Set VSI Promiscuous Modes (direct 0x0254) */
977 struct i40e_aqc_set_vsi_promiscuous_modes {
978 __le16 promiscuous_flags;
980 /* flags used for both fields above */
981 #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01
982 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02
983 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04
984 #define I40E_AQC_SET_VSI_DEFAULT 0x08
985 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10
986 #define I40E_AQC_SET_VSI_PROMISC_RX_ONLY 0x8000
989 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000
993 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes);
995 /* Add S/E-tag command (direct 0x0255)
996 * Uses generic i40e_aqc_add_remove_tag_completion for completion
998 struct i40e_aqc_add_tag {
1002 __le16 queue_number;
1006 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag);
1008 struct i40e_aqc_add_remove_tag_completion {
1014 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion);
1016 /* Remove S/E-tag command (direct 0x0256)
1017 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1019 struct i40e_aqc_remove_tag {
1025 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag);
1027 /* Add multicast E-Tag (direct 0x0257)
1028 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
1029 * and no external data
1031 struct i40e_aqc_add_remove_mcast_etag {
1034 u8 num_unicast_etags;
1036 __le32 addr_high; /* address of array of 2-byte s-tags */
1040 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag);
1042 struct i40e_aqc_add_remove_mcast_etag_completion {
1044 __le16 mcast_etags_used;
1045 __le16 mcast_etags_free;
1051 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion);
1053 /* Update S/E-Tag (direct 0x0259) */
1054 struct i40e_aqc_update_tag {
1061 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag);
1063 struct i40e_aqc_update_tag_completion {
1069 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion);
1071 /* Add Control Packet filter (direct 0x025A)
1072 * Remove Control Packet filter (direct 0x025B)
1073 * uses the i40e_aqc_add_oveb_cloud,
1074 * and the generic direct completion structure
1076 struct i40e_aqc_add_remove_control_packet_filter {
1080 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001
1081 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002
1082 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008
1088 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter);
1090 struct i40e_aqc_add_remove_control_packet_filter_completion {
1091 __le16 mac_etype_used;
1093 __le16 mac_etype_free;
1098 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion);
1100 /* Add Cloud filters (indirect 0x025C)
1101 * Remove Cloud filters (indirect 0x025D)
1102 * uses the i40e_aqc_add_remove_cloud_filters,
1103 * and the generic indirect completion structure
1105 struct i40e_aqc_add_remove_cloud_filters {
1110 #define I40E_AQC_ADD_CLOUD_CMD_BB 1
1116 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters);
1118 struct i40e_aqc_cloud_filters_element_data {
1135 /* 0x0000 reserved */
1136 /* 0x0001 reserved */
1137 /* 0x0002 reserved */
1138 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003
1139 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004
1140 /* 0x0005 reserved */
1141 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006
1142 /* 0x0007 reserved */
1143 /* 0x0008 reserved */
1144 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009
1145 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A
1146 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B
1147 #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C
1148 /* 0x000D reserved */
1149 /* 0x000E reserved */
1150 /* 0x000F reserved */
1151 /* 0x0010 to 0x0017 is for custom filters */
1152 #define I40E_AQC_ADD_CLOUD_FILTER_IP_PORT 0x0010 /* Dest IP + L4 Port */
1153 #define I40E_AQC_ADD_CLOUD_FILTER_MAC_PORT 0x0011 /* Dest MAC + L4 Port */
1154 #define I40E_AQC_ADD_CLOUD_FILTER_MAC_VLAN_PORT 0x0012 /* Dest MAC + VLAN + L4 Port */
1156 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0
1157 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100
1159 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9
1160 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00
1161 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2
1166 __le16 queue_number;
1168 /* response section */
1169 u8 allocation_result;
1170 u8 response_reserved[7];
1173 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_cloud_filters_element_data);
1175 /* i40e_aqc_cloud_filters_element_bb is used when
1176 * I40E_AQC_CLOUD_CMD_BB flag is set.
1178 struct i40e_aqc_cloud_filters_element_bb {
1179 struct i40e_aqc_cloud_filters_element_data element;
1180 u16 general_fields[32];
1181 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD0 15
1184 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_cloud_filters_element_bb);
1186 struct i40e_aqc_remove_cloud_filters_completion {
1187 __le16 perfect_ovlan_used;
1188 __le16 perfect_ovlan_free;
1195 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion);
1197 /* Replace filter Command 0x025F
1198 * uses the i40e_aqc_replace_cloud_filters,
1199 * and the generic indirect completion structure
1201 struct i40e_filter_data {
1206 I40E_CHECK_STRUCT_LEN(4, i40e_filter_data);
1208 struct i40e_aqc_replace_cloud_filters_cmd {
1218 I40E_CHECK_CMD_LENGTH(i40e_aqc_replace_cloud_filters_cmd);
1220 struct i40e_aqc_replace_cloud_filters_cmd_buf {
1222 struct i40e_filter_data filters[8];
1225 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_replace_cloud_filters_cmd_buf);
1227 /* Add Mirror Rule (indirect or direct 0x0260)
1228 * Delete Mirror Rule (indirect or direct 0x0261)
1229 * note: some rule types (4,5) do not use an external buffer.
1230 * take care to set the flags correctly.
1232 struct i40e_aqc_add_delete_mirror_rule {
1235 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0
1236 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \
1237 I40E_AQC_MIRROR_RULE_TYPE_SHIFT)
1238 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3
1239 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4
1240 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5
1242 __le16 destination; /* VSI for add, rule id for delete */
1243 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */
1247 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule);
1249 struct i40e_aqc_add_delete_mirror_rule_completion {
1251 __le16 rule_id; /* only used on add */
1252 __le16 mirror_rules_used;
1253 __le16 mirror_rules_free;
1258 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion);
1260 /* Dynamic Device Personalization */
1261 struct i40e_aqc_write_personalization_profile {
1264 __le32 profile_track_id;
1269 I40E_CHECK_CMD_LENGTH(i40e_aqc_write_personalization_profile);
1271 struct i40e_aqc_write_ddp_resp {
1272 __le32 error_offset;
1278 struct i40e_aqc_get_applied_profiles {
1286 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_applied_profiles);
1290 /* PFC Ignore (direct 0x0301)
1291 * the command and response use the same descriptor structure
1293 struct i40e_aqc_pfc_ignore {
1295 u8 command_flags; /* unused on response */
1299 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore);
1301 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure
1302 * with no parameters
1305 /* TX scheduler 0x04xx */
1307 /* Almost all the indirect commands use
1308 * this generic struct to pass the SEID in param0
1310 struct i40e_aqc_tx_sched_ind {
1317 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind);
1319 /* Several commands respond with a set of queue set handles */
1320 struct i40e_aqc_qs_handles_resp {
1321 __le16 qs_handles[8];
1324 /* Configure VSI BW limits (direct 0x0400) */
1325 struct i40e_aqc_configure_vsi_bw_limit {
1330 u8 max_credit; /* 0-3, limit = 2^max */
1334 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit);
1336 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
1337 * responds with i40e_aqc_qs_handles_resp
1339 struct i40e_aqc_configure_vsi_ets_sla_bw_data {
1342 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */
1344 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1345 __le16 tc_bw_max[2];
1349 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data);
1351 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
1352 * responds with i40e_aqc_qs_handles_resp
1354 struct i40e_aqc_configure_vsi_tc_bw_data {
1357 u8 tc_bw_credits[8];
1359 __le16 qs_handles[8];
1362 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data);
1364 /* Query vsi bw configuration (indirect 0x0408) */
1365 struct i40e_aqc_query_vsi_bw_config_resp {
1367 u8 tc_suspended_bits;
1369 __le16 qs_handles[8];
1371 __le16 port_bw_limit;
1373 u8 max_bw; /* 0-3, limit = 2^max */
1377 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp);
1379 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
1380 struct i40e_aqc_query_vsi_ets_sla_config_resp {
1383 u8 share_credits[8];
1386 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1387 __le16 tc_bw_max[2];
1390 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp);
1392 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */
1393 struct i40e_aqc_configure_switching_comp_bw_limit {
1398 u8 max_bw; /* 0-3, limit = 2^max */
1402 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit);
1404 /* Enable Physical Port ETS (indirect 0x0413)
1405 * Modify Physical Port ETS (indirect 0x0414)
1406 * Disable Physical Port ETS (indirect 0x0415)
1408 struct i40e_aqc_configure_switching_comp_ets_data {
1412 u8 tc_strict_priority_flags;
1414 u8 tc_bw_share_credits[8];
1418 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data);
1420 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
1421 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data {
1424 __le16 tc_bw_credit[8];
1426 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1427 __le16 tc_bw_max[2];
1431 I40E_CHECK_STRUCT_LEN(0x40,
1432 i40e_aqc_configure_switching_comp_ets_bw_limit_data);
1434 /* Configure Switching Component Bandwidth Allocation per Tc
1437 struct i40e_aqc_configure_switching_comp_bw_config_data {
1440 u8 absolute_credits; /* bool */
1441 u8 tc_bw_share_credits[8];
1445 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data);
1447 /* Query Switching Component Configuration (indirect 0x0418) */
1448 struct i40e_aqc_query_switching_comp_ets_config_resp {
1451 __le16 port_bw_limit;
1453 u8 tc_bw_max; /* 0-3, limit = 2^max */
1457 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp);
1459 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */
1460 struct i40e_aqc_query_port_ets_config_resp {
1464 u8 tc_strict_priority_bits;
1466 u8 tc_bw_share_credits[8];
1467 __le16 tc_bw_limits[8];
1469 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
1470 __le16 tc_bw_max[2];
1474 I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp);
1476 /* Query Switching Component Bandwidth Allocation per Traffic Type
1479 struct i40e_aqc_query_switching_comp_bw_config_resp {
1482 u8 absolute_credits_enable; /* bool */
1483 u8 tc_bw_share_credits[8];
1484 __le16 tc_bw_limits[8];
1486 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1487 __le16 tc_bw_max[2];
1490 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp);
1492 /* Suspend/resume port TX traffic
1493 * (direct 0x041B and 0x041C) uses the generic SEID struct
1496 /* Configure partition BW
1499 struct i40e_aqc_configure_partition_bw_data {
1500 __le16 pf_valid_bits;
1501 u8 min_bw[16]; /* guaranteed bandwidth */
1502 u8 max_bw[16]; /* bandwidth limit */
1505 I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data);
1507 /* Get and set the active HMC resource profile and status.
1508 * (direct 0x0500) and (direct 0x0501)
1510 struct i40e_aq_get_set_hmc_resource_profile {
1516 I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile);
1518 enum i40e_aq_hmc_profile {
1519 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */
1520 I40E_HMC_PROFILE_DEFAULT = 1,
1521 I40E_HMC_PROFILE_FAVOR_VF = 2,
1522 I40E_HMC_PROFILE_EQUAL = 3,
1525 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
1527 /* set in param0 for get phy abilities to report qualified modules */
1528 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001
1529 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002
1531 enum i40e_aq_phy_type {
1532 I40E_PHY_TYPE_SGMII = 0x0,
1533 I40E_PHY_TYPE_1000BASE_KX = 0x1,
1534 I40E_PHY_TYPE_10GBASE_KX4 = 0x2,
1535 I40E_PHY_TYPE_10GBASE_KR = 0x3,
1536 I40E_PHY_TYPE_40GBASE_KR4 = 0x4,
1537 I40E_PHY_TYPE_XAUI = 0x5,
1538 I40E_PHY_TYPE_XFI = 0x6,
1539 I40E_PHY_TYPE_SFI = 0x7,
1540 I40E_PHY_TYPE_XLAUI = 0x8,
1541 I40E_PHY_TYPE_XLPPI = 0x9,
1542 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA,
1543 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB,
1544 I40E_PHY_TYPE_10GBASE_AOC = 0xC,
1545 I40E_PHY_TYPE_40GBASE_AOC = 0xD,
1546 I40E_PHY_TYPE_UNRECOGNIZED = 0xE,
1547 I40E_PHY_TYPE_UNSUPPORTED = 0xF,
1548 I40E_PHY_TYPE_100BASE_TX = 0x11,
1549 I40E_PHY_TYPE_1000BASE_T = 0x12,
1550 I40E_PHY_TYPE_10GBASE_T = 0x13,
1551 I40E_PHY_TYPE_10GBASE_SR = 0x14,
1552 I40E_PHY_TYPE_10GBASE_LR = 0x15,
1553 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16,
1554 I40E_PHY_TYPE_10GBASE_CR1 = 0x17,
1555 I40E_PHY_TYPE_40GBASE_CR4 = 0x18,
1556 I40E_PHY_TYPE_40GBASE_SR4 = 0x19,
1557 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A,
1558 I40E_PHY_TYPE_1000BASE_SX = 0x1B,
1559 I40E_PHY_TYPE_1000BASE_LX = 0x1C,
1560 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D,
1561 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E,
1562 I40E_PHY_TYPE_25GBASE_KR = 0x1F,
1563 I40E_PHY_TYPE_25GBASE_CR = 0x20,
1564 I40E_PHY_TYPE_25GBASE_SR = 0x21,
1565 I40E_PHY_TYPE_25GBASE_LR = 0x22,
1566 I40E_PHY_TYPE_25GBASE_AOC = 0x23,
1567 I40E_PHY_TYPE_25GBASE_ACC = 0x24,
1568 I40E_PHY_TYPE_2_5GBASE_T = 0x30,
1569 I40E_PHY_TYPE_5GBASE_T = 0x31,
1571 I40E_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP = 0xFD,
1572 I40E_PHY_TYPE_EMPTY = 0xFE,
1573 I40E_PHY_TYPE_DEFAULT = 0xFF,
1576 #define I40E_PHY_TYPES_BITMASK (BIT_ULL(I40E_PHY_TYPE_SGMII) | \
1577 BIT_ULL(I40E_PHY_TYPE_1000BASE_KX) | \
1578 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4) | \
1579 BIT_ULL(I40E_PHY_TYPE_10GBASE_KR) | \
1580 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4) | \
1581 BIT_ULL(I40E_PHY_TYPE_XAUI) | \
1582 BIT_ULL(I40E_PHY_TYPE_XFI) | \
1583 BIT_ULL(I40E_PHY_TYPE_SFI) | \
1584 BIT_ULL(I40E_PHY_TYPE_XLAUI) | \
1585 BIT_ULL(I40E_PHY_TYPE_XLPPI) | \
1586 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU) | \
1587 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU) | \
1588 BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC) | \
1589 BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC) | \
1590 BIT_ULL(I40E_PHY_TYPE_UNRECOGNIZED) | \
1591 BIT_ULL(I40E_PHY_TYPE_UNSUPPORTED) | \
1592 BIT_ULL(I40E_PHY_TYPE_100BASE_TX) | \
1593 BIT_ULL(I40E_PHY_TYPE_1000BASE_T) | \
1594 BIT_ULL(I40E_PHY_TYPE_10GBASE_T) | \
1595 BIT_ULL(I40E_PHY_TYPE_10GBASE_SR) | \
1596 BIT_ULL(I40E_PHY_TYPE_10GBASE_LR) | \
1597 BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU) | \
1598 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1) | \
1599 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4) | \
1600 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4) | \
1601 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4) | \
1602 BIT_ULL(I40E_PHY_TYPE_1000BASE_SX) | \
1603 BIT_ULL(I40E_PHY_TYPE_1000BASE_LX) | \
1604 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL) | \
1605 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2) | \
1606 BIT_ULL(I40E_PHY_TYPE_25GBASE_KR) | \
1607 BIT_ULL(I40E_PHY_TYPE_25GBASE_CR) | \
1608 BIT_ULL(I40E_PHY_TYPE_25GBASE_SR) | \
1609 BIT_ULL(I40E_PHY_TYPE_25GBASE_LR) | \
1610 BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC) | \
1611 BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC) | \
1612 BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T) | \
1613 BIT_ULL(I40E_PHY_TYPE_5GBASE_T))
1615 #define I40E_LINK_SPEED_2_5GB_SHIFT 0x0
1616 #define I40E_LINK_SPEED_100MB_SHIFT 0x1
1617 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2
1618 #define I40E_LINK_SPEED_10GB_SHIFT 0x3
1619 #define I40E_LINK_SPEED_40GB_SHIFT 0x4
1620 #define I40E_LINK_SPEED_20GB_SHIFT 0x5
1621 #define I40E_LINK_SPEED_25GB_SHIFT 0x6
1622 #define I40E_LINK_SPEED_5GB_SHIFT 0x7
1624 enum i40e_aq_link_speed {
1625 I40E_LINK_SPEED_UNKNOWN = 0,
1626 I40E_LINK_SPEED_100MB = BIT(I40E_LINK_SPEED_100MB_SHIFT),
1627 I40E_LINK_SPEED_1GB = BIT(I40E_LINK_SPEED_1000MB_SHIFT),
1628 I40E_LINK_SPEED_2_5GB = (1 << I40E_LINK_SPEED_2_5GB_SHIFT),
1629 I40E_LINK_SPEED_5GB = (1 << I40E_LINK_SPEED_5GB_SHIFT),
1630 I40E_LINK_SPEED_10GB = BIT(I40E_LINK_SPEED_10GB_SHIFT),
1631 I40E_LINK_SPEED_40GB = BIT(I40E_LINK_SPEED_40GB_SHIFT),
1632 I40E_LINK_SPEED_20GB = BIT(I40E_LINK_SPEED_20GB_SHIFT),
1633 I40E_LINK_SPEED_25GB = BIT(I40E_LINK_SPEED_25GB_SHIFT),
1636 struct i40e_aqc_module_desc {
1644 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc);
1646 struct i40e_aq_get_phy_abilities_resp {
1647 __le32 phy_type; /* bitmap using the above enum for offsets */
1648 u8 link_speed; /* bitmap using the above enum bit patterns */
1650 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01
1651 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02
1652 __le16 eee_capability;
1656 #define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01
1657 #define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02
1658 #define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04
1659 #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08
1660 u8 fec_cfg_curr_mod_ext_info;
1661 #define I40E_AQ_REQUEST_FEC_KR 0x04
1662 #define I40E_AQ_REQUEST_FEC_RS 0x08
1663 #define I40E_AQ_ENABLE_FEC_AUTO 0x10
1668 u8 qualified_module_count;
1669 #define I40E_AQ_PHY_MAX_QMS 16
1670 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS];
1673 I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp);
1675 /* Set PHY Config (direct 0x0601) */
1676 struct i40e_aq_set_phy_config { /* same bits as above in all */
1680 /* bits 0-2 use the values from get_phy_abilities_resp */
1681 #define I40E_AQ_PHY_ENABLE_LINK 0x08
1682 #define I40E_AQ_PHY_ENABLE_AN 0x10
1683 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20
1684 __le16 eee_capability;
1688 #define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01
1689 #define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02
1690 #define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04
1691 #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08
1693 #define I40E_AQ_SET_FEC_ABILITY_KR BIT(0)
1694 #define I40E_AQ_SET_FEC_ABILITY_RS BIT(1)
1695 #define I40E_AQ_SET_FEC_REQUEST_KR BIT(2)
1696 #define I40E_AQ_SET_FEC_REQUEST_RS BIT(3)
1697 #define I40E_AQ_SET_FEC_AUTO BIT(4)
1698 #define I40E_AQ_PHY_FEC_CONFIG_SHIFT 0x0
1699 #define I40E_AQ_PHY_FEC_CONFIG_MASK (0x1F << I40E_AQ_PHY_FEC_CONFIG_SHIFT)
1703 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);
1705 /* Set MAC Config command data structure (direct 0x0603) */
1706 struct i40e_aq_set_mac_config {
1707 __le16 max_frame_size;
1709 u8 tx_timer_priority; /* bitmap */
1710 __le16 tx_timer_value;
1711 __le16 fc_refresh_threshold;
1715 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config);
1717 /* Restart Auto-Negotiation (direct 0x605) */
1718 struct i40e_aqc_set_link_restart_an {
1720 #define I40E_AQ_PHY_RESTART_AN 0x02
1721 #define I40E_AQ_PHY_LINK_ENABLE 0x04
1725 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an);
1727 /* Get Link Status cmd & response data structure (direct 0x0607) */
1728 struct i40e_aqc_get_link_status {
1729 __le16 command_flags; /* only field set on command */
1730 #define I40E_AQ_LSE_DISABLE 0x2
1731 #define I40E_AQ_LSE_ENABLE 0x3
1732 /* only response uses this flag */
1733 #define I40E_AQ_LSE_IS_ENABLED 0x1
1734 u8 phy_type; /* i40e_aq_phy_type */
1735 u8 link_speed; /* i40e_aq_link_speed */
1737 #define I40E_AQ_LINK_UP 0x01 /* obsolete */
1738 #define I40E_AQ_MEDIA_AVAILABLE 0x40
1740 #define I40E_AQ_AN_COMPLETED 0x01
1741 #define I40E_AQ_LINK_PAUSE_TX 0x20
1742 #define I40E_AQ_LINK_PAUSE_RX 0x40
1743 #define I40E_AQ_QUALIFIED_MODULE 0x80
1745 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */
1746 /* Since firmware API 1.7 loopback field keeps power class info as well */
1747 #define I40E_AQ_LOOPBACK_MASK 0x07
1748 __le16 max_frame_size;
1750 #define I40E_AQ_CONFIG_FEC_KR_ENA 0x01
1751 #define I40E_AQ_CONFIG_FEC_RS_ENA 0x02
1752 #define I40E_AQ_CONFIG_CRC_ENA 0x04
1753 #define I40E_AQ_CONFIG_PACING_MASK 0x78
1766 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status);
1768 /* Set event mask command (direct 0x613) */
1769 struct i40e_aqc_set_phy_int_mask {
1772 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002
1773 #define I40E_AQ_EVENT_MEDIA_NA 0x0004
1774 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100
1778 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask);
1780 /* Get Local AN advt register (direct 0x0614)
1781 * Set Local AN advt register (direct 0x0615)
1782 * Get Link Partner AN advt register (direct 0x0616)
1784 struct i40e_aqc_an_advt_reg {
1785 __le32 local_an_reg0;
1786 __le16 local_an_reg1;
1790 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg);
1792 /* Set Loopback mode (0x0618) */
1793 struct i40e_aqc_set_lb_mode {
1795 #define I40E_AQ_LB_PHY_LOCAL 0x01
1796 #define I40E_AQ_LB_PHY_REMOTE 0x02
1797 #define I40E_AQ_LB_MAC_LOCAL 0x04
1801 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode);
1803 /* Set PHY Debug command (0x0622) */
1804 struct i40e_aqc_set_phy_debug {
1806 /* Disable link manageability on a single port */
1807 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10
1808 /* Disable link manageability on all ports */
1809 #define I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW 0x20
1813 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug);
1815 enum i40e_aq_phy_reg_type {
1816 I40E_AQC_PHY_REG_INTERNAL = 0x1,
1817 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2,
1818 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3
1821 /* Run PHY Activity (0x0626) */
1822 struct i40e_aqc_run_phy_activity {
1831 I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity);
1833 /* Set PHY Register command (0x0628) */
1834 /* Get PHY Register command (0x0629) */
1835 struct i40e_aqc_phy_register_access {
1837 #define I40E_AQ_PHY_REG_ACCESS_EXTERNAL 1
1838 #define I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE 2
1841 #define I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE 0x01
1842 #define I40E_AQ_PHY_REG_ACCESS_SET_MDIO_IF_NUMBER 0x02
1843 #define I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_SHIFT 2
1844 #define I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_MASK (0x3 << \
1845 I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_SHIFT)
1852 I40E_CHECK_CMD_LENGTH(i40e_aqc_phy_register_access);
1854 /* NVM Read command (indirect 0x0701)
1855 * NVM Erase commands (direct 0x0702)
1856 * NVM Update commands (indirect 0x0703)
1858 struct i40e_aqc_nvm_update {
1860 #define I40E_AQ_NVM_LAST_CMD 0x01
1861 #define I40E_AQ_NVM_REARRANGE_TO_FLAT 0x20
1862 #define I40E_AQ_NVM_REARRANGE_TO_STRUCT 0x40
1863 #define I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT 1
1864 #define I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED 0x03
1865 #define I40E_AQ_NVM_PRESERVATION_FLAGS_ALL 0x01
1873 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);
1875 /* NVM Config Read (indirect 0x0704) */
1876 struct i40e_aqc_nvm_config_read {
1878 __le16 element_count;
1879 __le16 element_id; /* Feature/field ID */
1880 __le16 element_id_msw; /* MSWord of field ID */
1881 __le32 address_high;
1885 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read);
1887 /* NVM Config Write (indirect 0x0705) */
1888 struct i40e_aqc_nvm_config_write {
1890 __le16 element_count;
1892 __le32 address_high;
1896 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);
1898 /* Used for 0x0704 as well as for 0x0705 commands */
1899 struct i40e_aqc_nvm_config_data_feature {
1901 __le16 feature_options;
1902 __le16 feature_selection;
1905 I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature);
1907 struct i40e_aqc_nvm_config_data_immediate_field {
1910 __le16 field_options;
1914 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field);
1916 /* OEM Post Update (indirect 0x0720)
1917 * no command data struct used
1919 struct i40e_aqc_nvm_oem_post_update {
1924 I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update);
1926 struct i40e_aqc_nvm_oem_post_update_buffer {
1933 I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer);
1935 /* Thermal Sensor (indirect 0x0721)
1936 * read or set thermal sensor configs and values
1937 * takes a sensor and command specific data buffer, not detailed here
1939 struct i40e_aqc_thermal_sensor {
1946 I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor);
1948 /* Send to PF command (indirect 0x0801) id is only used by PF
1949 * Send to VF command (indirect 0x0802) id is only used by PF
1950 * Send to Peer PF command (indirect 0x0803)
1952 struct i40e_aqc_pf_vf_message {
1959 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message);
1961 /* Alternate structure */
1963 /* Direct write (direct 0x0900)
1964 * Direct read (direct 0x0902)
1966 struct i40e_aqc_alternate_write {
1973 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write);
1975 /* Indirect write (indirect 0x0901)
1976 * Indirect read (indirect 0x0903)
1979 struct i40e_aqc_alternate_ind_write {
1986 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write);
1988 /* Done alternate write (direct 0x0904)
1991 struct i40e_aqc_alternate_write_done {
1996 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done);
1998 /* Set OEM mode (direct 0x0905) */
1999 struct i40e_aqc_alternate_set_mode {
2004 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode);
2006 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */
2008 /* async events 0x10xx */
2010 /* Lan Queue Overflow Event (direct, 0x1001) */
2011 struct i40e_aqc_lan_overflow {
2012 __le32 prtdcb_rupto;
2017 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow);
2019 /* Get LLDP MIB (indirect 0x0A00) */
2020 struct i40e_aqc_lldp_get_mib {
2023 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3
2024 #define I40E_AQ_LLDP_MIB_LOCAL 0x0
2025 #define I40E_AQ_LLDP_MIB_REMOTE 0x1
2026 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC
2027 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2
2028 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0
2029 /* TX pause flags use I40E_AQ_LINK_TX_* above */
2037 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib);
2039 /* Configure LLDP MIB Change Event (direct 0x0A01)
2040 * also used for the event (with type in the command field)
2042 struct i40e_aqc_lldp_update_mib {
2044 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1
2050 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib);
2052 /* Add LLDP TLV (indirect 0x0A02)
2053 * Delete LLDP TLV (indirect 0x0A04)
2055 struct i40e_aqc_lldp_add_tlv {
2056 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2064 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv);
2066 /* Update LLDP TLV (indirect 0x0A03) */
2067 struct i40e_aqc_lldp_update_tlv {
2068 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2077 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv);
2079 /* Stop LLDP (direct 0x0A05) */
2080 struct i40e_aqc_lldp_stop {
2082 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1
2083 #define I40E_AQ_LLDP_AGENT_STOP_PERSIST 0x2
2087 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop);
2089 /* Start LLDP (direct 0x0A06) */
2090 struct i40e_aqc_lldp_start {
2092 #define I40E_AQ_LLDP_AGENT_START 0x1
2093 #define I40E_AQ_LLDP_AGENT_START_PERSIST 0x2
2097 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start);
2099 /* Set DCB (direct 0x0303) */
2100 struct i40e_aqc_set_dcb_parameters {
2102 #define I40E_AQ_DCB_SET_AGENT 0x1
2103 #define I40E_DCB_VALID 0x1
2108 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_dcb_parameters);
2110 /* Get CEE DCBX Oper Config (0x0A07)
2111 * uses the generic descriptor struct
2112 * returns below as indirect response
2115 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0
2116 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT)
2117 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3
2118 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
2119 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8
2120 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2122 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0
2123 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
2124 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3
2125 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
2126 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8
2127 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
2128 #define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8
2129 #define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT)
2130 #define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB
2131 #define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT)
2132 #define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10
2133 #define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT)
2135 /* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with
2136 * word boundary layout issues, which the Linux compilers silently deal
2137 * with by adding padding, making the actual struct larger than designed.
2138 * However, the FW compiler for the NIC is less lenient and complains
2139 * about the struct. Hence, the struct defined here has an extra byte in
2140 * fields reserved3 and reserved4 to directly acknowledge that padding,
2141 * and the new length is used in the length check macro.
2143 struct i40e_aqc_get_cee_dcb_cfg_v1_resp {
2151 __le16 oper_app_prio;
2156 I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp);
2158 struct i40e_aqc_get_cee_dcb_cfg_resp {
2163 __le16 oper_app_prio;
2164 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0
2165 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT)
2166 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3
2167 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
2168 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8
2169 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2170 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2172 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0
2173 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
2174 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3
2175 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
2176 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8
2177 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
2181 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp);
2183 /* Set Local LLDP MIB (indirect 0x0A08)
2184 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx
2186 struct i40e_aqc_lldp_set_local_mib {
2191 __le32 address_high;
2195 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib);
2197 /* Stop/Start LLDP Agent (direct 0x0A09)
2198 * Used for stopping/starting specific LLDP agent. e.g. DCBx
2200 struct i40e_aqc_lldp_stop_start_specific_agent {
2205 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent);
2207 /* Restore LLDP Agent factory settings (direct 0x0A0A) */
2208 struct i40e_aqc_lldp_restore {
2210 #define I40E_AQ_LLDP_AGENT_RESTORE 0x1
2214 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_restore);
2216 /* Add Udp Tunnel command and completion (direct 0x0B00) */
2217 struct i40e_aqc_add_udp_tunnel {
2221 #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00
2222 #define I40E_AQC_TUNNEL_TYPE_NGE 0x01
2226 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel);
2228 struct i40e_aqc_add_udp_tunnel_completion {
2230 u8 filter_entry_index;
2236 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion);
2238 /* remove UDP Tunnel command (0x0B01) */
2239 struct i40e_aqc_remove_udp_tunnel {
2241 u8 index; /* 0 to 15 */
2245 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel);
2247 struct i40e_aqc_del_udp_tunnel_completion {
2249 u8 index; /* 0 to 15 */
2251 u8 total_filters_used;
2255 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);
2257 struct i40e_aqc_get_set_rss_key {
2258 #define I40E_AQC_SET_RSS_KEY_VSI_VALID BIT(15)
2259 #define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0
2260 #define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \
2261 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT)
2268 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key);
2270 struct i40e_aqc_get_set_rss_key_data {
2271 u8 standard_rss_key[0x28];
2272 u8 extended_hash_key[0xc];
2275 I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data);
2277 struct i40e_aqc_get_set_rss_lut {
2278 #define I40E_AQC_SET_RSS_LUT_VSI_VALID BIT(15)
2279 #define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0
2280 #define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \
2281 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT)
2283 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0
2284 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK BIT(I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT)
2286 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0
2287 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1
2294 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut);
2296 /* tunnel key structure 0x0B10 */
2298 struct i40e_aqc_tunnel_key_structure {
2301 u8 key1_len; /* 0 to 15 */
2302 u8 key2_len; /* 0 to 15 */
2304 u8 network_key_index;
2308 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure);
2310 /* OEM mode commands (direct 0xFE0x) */
2311 struct i40e_aqc_oem_param_change {
2313 __le32 param_value1;
2314 __le16 param_value2;
2318 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change);
2320 struct i40e_aqc_oem_state_change {
2325 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change);
2327 /* Initialize OCSD (0xFE02, direct) */
2328 struct i40e_aqc_opc_oem_ocsd_initialize {
2331 __le32 ocsd_memory_block_addr_high;
2332 __le32 ocsd_memory_block_addr_low;
2333 __le32 requested_update_interval;
2336 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize);
2338 /* Initialize OCBB (0xFE03, direct) */
2339 struct i40e_aqc_opc_oem_ocbb_initialize {
2342 __le32 ocbb_memory_block_addr_high;
2343 __le32 ocbb_memory_block_addr_low;
2347 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize);
2349 /* debug commands */
2351 /* get device id (0xFF00) uses the generic structure */
2353 /* set test more (0xFF01, internal) */
2355 struct i40e_acq_set_test_mode {
2360 __le32 address_high;
2364 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode);
2366 /* Debug Read Register command (0xFF03)
2367 * Debug Write Register command (0xFF04)
2369 struct i40e_aqc_debug_reg_read_write {
2376 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write);
2378 /* Scatter/gather Reg Read (indirect 0xFF05)
2379 * Scatter/gather Reg Write (indirect 0xFF06)
2382 /* i40e_aq_desc is used for the command */
2383 struct i40e_aqc_debug_reg_sg_element_data {
2388 /* Debug Modify register (direct 0xFF07) */
2389 struct i40e_aqc_debug_modify_reg {
2396 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg);
2398 /* dump internal data (0xFF08, indirect) */
2399 struct i40e_aqc_debug_dump_internals {
2404 __le32 address_high;
2408 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals);
2410 struct i40e_aqc_debug_modify_internals {
2412 u8 cluster_specific_params[7];
2413 __le32 address_high;
2417 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals);
2419 #endif /* _I40E_ADMINQ_CMD_H_ */