1 /*******************************************************************************
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2014 Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 ******************************************************************************/
27 #ifndef _I40E_ADMINQ_CMD_H_
28 #define _I40E_ADMINQ_CMD_H_
30 /* This header file defines the i40e Admin Queue commands and is shared between
31 * i40e Firmware and Software.
33 * This file needs to comply with the Linux Kernel coding style.
36 #define I40E_FW_API_VERSION_MAJOR 0x0001
37 #define I40E_FW_API_VERSION_MINOR 0x0002
63 /* Flags sub-structure
64 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
65 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
68 /* command flags and offsets*/
69 #define I40E_AQ_FLAG_DD_SHIFT 0
70 #define I40E_AQ_FLAG_CMP_SHIFT 1
71 #define I40E_AQ_FLAG_ERR_SHIFT 2
72 #define I40E_AQ_FLAG_VFE_SHIFT 3
73 #define I40E_AQ_FLAG_LB_SHIFT 9
74 #define I40E_AQ_FLAG_RD_SHIFT 10
75 #define I40E_AQ_FLAG_VFC_SHIFT 11
76 #define I40E_AQ_FLAG_BUF_SHIFT 12
77 #define I40E_AQ_FLAG_SI_SHIFT 13
78 #define I40E_AQ_FLAG_EI_SHIFT 14
79 #define I40E_AQ_FLAG_FE_SHIFT 15
81 #define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */
82 #define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */
83 #define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */
84 #define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */
85 #define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */
86 #define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */
87 #define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */
88 #define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
89 #define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */
90 #define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */
91 #define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */
94 enum i40e_admin_queue_err {
95 I40E_AQ_RC_OK = 0, /* success */
96 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */
97 I40E_AQ_RC_ENOENT = 2, /* No such element */
98 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */
99 I40E_AQ_RC_EINTR = 4, /* operation interrupted */
100 I40E_AQ_RC_EIO = 5, /* I/O error */
101 I40E_AQ_RC_ENXIO = 6, /* No such resource */
102 I40E_AQ_RC_E2BIG = 7, /* Arg too long */
103 I40E_AQ_RC_EAGAIN = 8, /* Try again */
104 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */
105 I40E_AQ_RC_EACCES = 10, /* Permission denied */
106 I40E_AQ_RC_EFAULT = 11, /* Bad address */
107 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */
108 I40E_AQ_RC_EEXIST = 13, /* object already exists */
109 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */
110 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */
111 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */
112 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */
113 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */
114 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed because of prev cmd error */
115 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */
116 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
117 I40E_AQ_RC_EFBIG = 22, /* File too large */
120 /* Admin Queue command opcodes */
121 enum i40e_admin_queue_opc {
123 i40e_aqc_opc_get_version = 0x0001,
124 i40e_aqc_opc_driver_version = 0x0002,
125 i40e_aqc_opc_queue_shutdown = 0x0003,
126 i40e_aqc_opc_set_pf_context = 0x0004,
128 /* resource ownership */
129 i40e_aqc_opc_request_resource = 0x0008,
130 i40e_aqc_opc_release_resource = 0x0009,
132 i40e_aqc_opc_list_func_capabilities = 0x000A,
133 i40e_aqc_opc_list_dev_capabilities = 0x000B,
135 i40e_aqc_opc_set_cppm_configuration = 0x0103,
136 i40e_aqc_opc_set_arp_proxy_entry = 0x0104,
137 i40e_aqc_opc_set_ns_proxy_entry = 0x0105,
140 i40e_aqc_opc_mng_laa = 0x0106, /* AQ obsolete */
141 i40e_aqc_opc_mac_address_read = 0x0107,
142 i40e_aqc_opc_mac_address_write = 0x0108,
145 i40e_aqc_opc_clear_pxe_mode = 0x0110,
147 /* internal switch commands */
148 i40e_aqc_opc_get_switch_config = 0x0200,
149 i40e_aqc_opc_add_statistics = 0x0201,
150 i40e_aqc_opc_remove_statistics = 0x0202,
151 i40e_aqc_opc_set_port_parameters = 0x0203,
152 i40e_aqc_opc_get_switch_resource_alloc = 0x0204,
154 i40e_aqc_opc_add_vsi = 0x0210,
155 i40e_aqc_opc_update_vsi_parameters = 0x0211,
156 i40e_aqc_opc_get_vsi_parameters = 0x0212,
158 i40e_aqc_opc_add_pv = 0x0220,
159 i40e_aqc_opc_update_pv_parameters = 0x0221,
160 i40e_aqc_opc_get_pv_parameters = 0x0222,
162 i40e_aqc_opc_add_veb = 0x0230,
163 i40e_aqc_opc_update_veb_parameters = 0x0231,
164 i40e_aqc_opc_get_veb_parameters = 0x0232,
166 i40e_aqc_opc_delete_element = 0x0243,
168 i40e_aqc_opc_add_macvlan = 0x0250,
169 i40e_aqc_opc_remove_macvlan = 0x0251,
170 i40e_aqc_opc_add_vlan = 0x0252,
171 i40e_aqc_opc_remove_vlan = 0x0253,
172 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254,
173 i40e_aqc_opc_add_tag = 0x0255,
174 i40e_aqc_opc_remove_tag = 0x0256,
175 i40e_aqc_opc_add_multicast_etag = 0x0257,
176 i40e_aqc_opc_remove_multicast_etag = 0x0258,
177 i40e_aqc_opc_update_tag = 0x0259,
178 i40e_aqc_opc_add_control_packet_filter = 0x025A,
179 i40e_aqc_opc_remove_control_packet_filter = 0x025B,
180 i40e_aqc_opc_add_cloud_filters = 0x025C,
181 i40e_aqc_opc_remove_cloud_filters = 0x025D,
183 i40e_aqc_opc_add_mirror_rule = 0x0260,
184 i40e_aqc_opc_delete_mirror_rule = 0x0261,
187 i40e_aqc_opc_dcb_ignore_pfc = 0x0301,
188 i40e_aqc_opc_dcb_updated = 0x0302,
191 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400,
192 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406,
193 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407,
194 i40e_aqc_opc_query_vsi_bw_config = 0x0408,
195 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A,
196 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410,
198 i40e_aqc_opc_enable_switching_comp_ets = 0x0413,
199 i40e_aqc_opc_modify_switching_comp_ets = 0x0414,
200 i40e_aqc_opc_disable_switching_comp_ets = 0x0415,
201 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416,
202 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417,
203 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418,
204 i40e_aqc_opc_query_port_ets_config = 0x0419,
205 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A,
206 i40e_aqc_opc_suspend_port_tx = 0x041B,
207 i40e_aqc_opc_resume_port_tx = 0x041C,
208 i40e_aqc_opc_configure_partition_bw = 0x041D,
211 i40e_aqc_opc_query_hmc_resource_profile = 0x0500,
212 i40e_aqc_opc_set_hmc_resource_profile = 0x0501,
215 i40e_aqc_opc_get_phy_abilities = 0x0600,
216 i40e_aqc_opc_set_phy_config = 0x0601,
217 i40e_aqc_opc_set_mac_config = 0x0603,
218 i40e_aqc_opc_set_link_restart_an = 0x0605,
219 i40e_aqc_opc_get_link_status = 0x0607,
220 i40e_aqc_opc_set_phy_int_mask = 0x0613,
221 i40e_aqc_opc_get_local_advt_reg = 0x0614,
222 i40e_aqc_opc_set_local_advt_reg = 0x0615,
223 i40e_aqc_opc_get_partner_advt = 0x0616,
224 i40e_aqc_opc_set_lb_modes = 0x0618,
225 i40e_aqc_opc_get_phy_wol_caps = 0x0621,
226 i40e_aqc_opc_set_phy_debug = 0x0622,
227 i40e_aqc_opc_upload_ext_phy_fm = 0x0625,
230 i40e_aqc_opc_nvm_read = 0x0701,
231 i40e_aqc_opc_nvm_erase = 0x0702,
232 i40e_aqc_opc_nvm_update = 0x0703,
233 i40e_aqc_opc_nvm_config_read = 0x0704,
234 i40e_aqc_opc_nvm_config_write = 0x0705,
236 /* virtualization commands */
237 i40e_aqc_opc_send_msg_to_pf = 0x0801,
238 i40e_aqc_opc_send_msg_to_vf = 0x0802,
239 i40e_aqc_opc_send_msg_to_peer = 0x0803,
241 /* alternate structure */
242 i40e_aqc_opc_alternate_write = 0x0900,
243 i40e_aqc_opc_alternate_write_indirect = 0x0901,
244 i40e_aqc_opc_alternate_read = 0x0902,
245 i40e_aqc_opc_alternate_read_indirect = 0x0903,
246 i40e_aqc_opc_alternate_write_done = 0x0904,
247 i40e_aqc_opc_alternate_set_mode = 0x0905,
248 i40e_aqc_opc_alternate_clear_port = 0x0906,
251 i40e_aqc_opc_lldp_get_mib = 0x0A00,
252 i40e_aqc_opc_lldp_update_mib = 0x0A01,
253 i40e_aqc_opc_lldp_add_tlv = 0x0A02,
254 i40e_aqc_opc_lldp_update_tlv = 0x0A03,
255 i40e_aqc_opc_lldp_delete_tlv = 0x0A04,
256 i40e_aqc_opc_lldp_stop = 0x0A05,
257 i40e_aqc_opc_lldp_start = 0x0A06,
259 /* Tunnel commands */
260 i40e_aqc_opc_add_udp_tunnel = 0x0B00,
261 i40e_aqc_opc_del_udp_tunnel = 0x0B01,
262 i40e_aqc_opc_tunnel_key_structure = 0x0B10,
265 i40e_aqc_opc_event_lan_overflow = 0x1001,
268 i40e_aqc_opc_oem_parameter_change = 0xFE00,
269 i40e_aqc_opc_oem_device_status_change = 0xFE01,
272 i40e_aqc_opc_debug_get_deviceid = 0xFF00,
273 i40e_aqc_opc_debug_set_mode = 0xFF01,
274 i40e_aqc_opc_debug_read_reg = 0xFF03,
275 i40e_aqc_opc_debug_write_reg = 0xFF04,
276 i40e_aqc_opc_debug_modify_reg = 0xFF07,
277 i40e_aqc_opc_debug_dump_internals = 0xFF08,
278 i40e_aqc_opc_debug_modify_internals = 0xFF09,
281 /* command structures and indirect data structures */
283 /* Structure naming conventions:
284 * - no suffix for direct command descriptor structures
285 * - _data for indirect sent data
286 * - _resp for indirect return data (data which is both will use _data)
287 * - _completion for direct return data
288 * - _element_ for repeated elements (may also be _data or _resp)
290 * Command structures are expected to overlay the params.raw member of the basic
291 * descriptor, and as such cannot exceed 16 bytes in length.
294 /* This macro is used to generate a compilation error if a structure
295 * is not exactly the correct length. It gives a divide by zero error if the
296 * structure is not of the correct size, otherwise it creates an enum that is
299 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \
300 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
302 /* This macro is used extensively to ensure that command structures are 16
303 * bytes in length as they have to map to the raw array of that size.
305 #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X)
307 /* internal (0x00XX) commands */
309 /* Get version (direct 0x0001) */
310 struct i40e_aqc_get_version {
319 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version);
321 /* Send driver version (indirect 0x0002) */
322 struct i40e_aqc_driver_version {
326 u8 driver_subbuild_ver;
332 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version);
334 /* Queue Shutdown (direct 0x0003) */
335 struct i40e_aqc_queue_shutdown {
336 __le32 driver_unloading;
337 #define I40E_AQ_DRIVER_UNLOADING 0x1
341 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);
343 /* Set PF context (0x0004, direct) */
344 struct i40e_aqc_set_pf_context {
349 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context);
351 /* Request resource ownership (direct 0x0008)
352 * Release resource ownership (direct 0x0009)
354 #define I40E_AQ_RESOURCE_NVM 1
355 #define I40E_AQ_RESOURCE_SDP 2
356 #define I40E_AQ_RESOURCE_ACCESS_READ 1
357 #define I40E_AQ_RESOURCE_ACCESS_WRITE 2
358 #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000
359 #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000
361 struct i40e_aqc_request_resource {
365 __le32 resource_number;
369 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource);
371 /* Get function capabilities (indirect 0x000A)
372 * Get device capabilities (indirect 0x000B)
374 struct i40e_aqc_list_capabilites {
376 #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1
384 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites);
386 struct i40e_aqc_list_capabilities_element_resp {
398 #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001
399 #define I40E_AQ_CAP_ID_MNG_MODE 0x0002
400 #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003
401 #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004
402 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005
403 #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006
404 #define I40E_AQ_CAP_ID_SRIOV 0x0012
405 #define I40E_AQ_CAP_ID_VF 0x0013
406 #define I40E_AQ_CAP_ID_VMDQ 0x0014
407 #define I40E_AQ_CAP_ID_8021QBG 0x0015
408 #define I40E_AQ_CAP_ID_8021QBR 0x0016
409 #define I40E_AQ_CAP_ID_VSI 0x0017
410 #define I40E_AQ_CAP_ID_DCB 0x0018
411 #define I40E_AQ_CAP_ID_FCOE 0x0021
412 #define I40E_AQ_CAP_ID_RSS 0x0040
413 #define I40E_AQ_CAP_ID_RXQ 0x0041
414 #define I40E_AQ_CAP_ID_TXQ 0x0042
415 #define I40E_AQ_CAP_ID_MSIX 0x0043
416 #define I40E_AQ_CAP_ID_VF_MSIX 0x0044
417 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045
418 #define I40E_AQ_CAP_ID_1588 0x0046
419 #define I40E_AQ_CAP_ID_IWARP 0x0051
420 #define I40E_AQ_CAP_ID_LED 0x0061
421 #define I40E_AQ_CAP_ID_SDP 0x0062
422 #define I40E_AQ_CAP_ID_MDIO 0x0063
423 #define I40E_AQ_CAP_ID_FLEX10 0x00F1
424 #define I40E_AQ_CAP_ID_CEM 0x00F2
426 /* Set CPPM Configuration (direct 0x0103) */
427 struct i40e_aqc_cppm_configuration {
428 __le16 command_flags;
429 #define I40E_AQ_CPPM_EN_LTRC 0x0800
430 #define I40E_AQ_CPPM_EN_DMCTH 0x1000
431 #define I40E_AQ_CPPM_EN_DMCTLX 0x2000
432 #define I40E_AQ_CPPM_EN_HPTC 0x4000
433 #define I40E_AQ_CPPM_EN_DMARC 0x8000
442 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration);
444 /* Set ARP Proxy command / response (indirect 0x0104) */
445 struct i40e_aqc_arp_proxy_data {
446 __le16 command_flags;
447 #define I40E_AQ_ARP_INIT_IPV4 0x0008
448 #define I40E_AQ_ARP_UNSUP_CTL 0x0010
449 #define I40E_AQ_ARP_ENA 0x0020
450 #define I40E_AQ_ARP_ADD_IPV4 0x0040
451 #define I40E_AQ_ARP_DEL_IPV4 0x0080
458 /* Set NS Proxy Table Entry Command (indirect 0x0105) */
459 struct i40e_aqc_ns_proxy_data {
460 __le16 table_idx_mac_addr_0;
461 __le16 table_idx_mac_addr_1;
462 __le16 table_idx_ipv6_0;
463 __le16 table_idx_ipv6_1;
465 #define I40E_AQ_NS_PROXY_ADD_0 0x0100
466 #define I40E_AQ_NS_PROXY_DEL_0 0x0200
467 #define I40E_AQ_NS_PROXY_ADD_1 0x0400
468 #define I40E_AQ_NS_PROXY_DEL_1 0x0800
469 #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x1000
470 #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x2000
471 #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x4000
472 #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x8000
473 #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0001
474 #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0002
475 #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0004
478 u8 local_mac_addr[6];
479 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */
483 /* Manage LAA Command (0x0106) - obsolete */
484 struct i40e_aqc_mng_laa {
485 __le16 command_flags;
486 #define I40E_AQ_LAA_FLAG_WR 0x8000
493 /* Manage MAC Address Read Command (indirect 0x0107) */
494 struct i40e_aqc_mac_address_read {
495 __le16 command_flags;
496 #define I40E_AQC_LAN_ADDR_VALID 0x10
497 #define I40E_AQC_SAN_ADDR_VALID 0x20
498 #define I40E_AQC_PORT_ADDR_VALID 0x40
499 #define I40E_AQC_WOL_ADDR_VALID 0x80
500 #define I40E_AQC_ADDR_VALID_MASK 0xf0
506 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read);
508 struct i40e_aqc_mac_address_read_data {
515 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data);
517 /* Manage MAC Address Write Command (0x0108) */
518 struct i40e_aqc_mac_address_write {
519 __le16 command_flags;
520 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000
521 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000
522 #define I40E_AQC_WRITE_TYPE_PORT 0x8000
523 #define I40E_AQC_WRITE_TYPE_MASK 0xc000
529 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write);
531 /* PXE commands (0x011x) */
533 /* Clear PXE Command and response (direct 0x0110) */
534 struct i40e_aqc_clear_pxe {
539 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe);
541 /* Switch configuration commands (0x02xx) */
543 /* Used by many indirect commands that only pass an seid and a buffer in the
546 struct i40e_aqc_switch_seid {
553 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid);
555 /* Get Switch Configuration command (indirect 0x0200)
556 * uses i40e_aqc_switch_seid for the descriptor
558 struct i40e_aqc_get_switch_config_header_resp {
564 struct i40e_aqc_switch_config_element_resp {
566 #define I40E_AQ_SW_ELEM_TYPE_MAC 1
567 #define I40E_AQ_SW_ELEM_TYPE_PF 2
568 #define I40E_AQ_SW_ELEM_TYPE_VF 3
569 #define I40E_AQ_SW_ELEM_TYPE_EMP 4
570 #define I40E_AQ_SW_ELEM_TYPE_BMC 5
571 #define I40E_AQ_SW_ELEM_TYPE_PV 16
572 #define I40E_AQ_SW_ELEM_TYPE_VEB 17
573 #define I40E_AQ_SW_ELEM_TYPE_PA 18
574 #define I40E_AQ_SW_ELEM_TYPE_VSI 19
576 #define I40E_AQ_SW_ELEM_REV_1 1
579 __le16 downlink_seid;
582 #define I40E_AQ_CONN_TYPE_REGULAR 0x1
583 #define I40E_AQ_CONN_TYPE_DEFAULT 0x2
584 #define I40E_AQ_CONN_TYPE_CASCADED 0x3
589 /* Get Switch Configuration (indirect 0x0200)
590 * an array of elements are returned in the response buffer
591 * the first in the array is the header, remainder are elements
593 struct i40e_aqc_get_switch_config_resp {
594 struct i40e_aqc_get_switch_config_header_resp header;
595 struct i40e_aqc_switch_config_element_resp element[1];
598 /* Add Statistics (direct 0x0201)
599 * Remove Statistics (direct 0x0202)
601 struct i40e_aqc_add_remove_statistics {
608 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics);
610 /* Set Port Parameters command (direct 0x0203) */
611 struct i40e_aqc_set_port_parameters {
612 __le16 command_flags;
613 #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1
614 #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */
615 #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4
616 __le16 bad_frame_vsi;
617 __le16 default_seid; /* reserved for command */
621 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters);
623 /* Get Switch Resource Allocation (indirect 0x0204) */
624 struct i40e_aqc_get_switch_resource_alloc {
625 u8 num_entries; /* reserved for command */
631 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc);
633 /* expect an array of these structs in the response buffer */
634 struct i40e_aqc_switch_resource_alloc_element_resp {
636 #define I40E_AQ_RESOURCE_TYPE_VEB 0x0
637 #define I40E_AQ_RESOURCE_TYPE_VSI 0x1
638 #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2
639 #define I40E_AQ_RESOURCE_TYPE_STAG 0x3
640 #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4
641 #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5
642 #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6
643 #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7
644 #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8
645 #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9
646 #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA
647 #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB
648 #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC
649 #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD
650 #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF
651 #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10
652 #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11
653 #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12
654 #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13
659 __le16 total_unalloced;
663 /* Add VSI (indirect 0x0210)
664 * this indirect command uses struct i40e_aqc_vsi_properties_data
665 * as the indirect buffer (128 bytes)
667 * Update VSI (indirect 0x211)
668 * uses the same data structure as Add VSI
670 * Get VSI (indirect 0x0212)
671 * uses the same completion and data structure as Add VSI
673 struct i40e_aqc_add_get_update_vsi {
676 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1
677 #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2
678 #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3
683 #define I40E_AQ_VSI_TYPE_SHIFT 0x0
684 #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT)
685 #define I40E_AQ_VSI_TYPE_VF 0x0
686 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1
687 #define I40E_AQ_VSI_TYPE_PF 0x2
688 #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3
689 #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4
694 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi);
696 struct i40e_aqc_add_get_update_vsi_completion {
705 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion);
707 struct i40e_aqc_vsi_properties_data {
708 /* first 96 byte are written by SW */
709 __le16 valid_sections;
710 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001
711 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002
712 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004
713 #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008
714 #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010
715 #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020
716 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040
717 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080
718 #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100
719 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200
721 __le16 switch_id; /* 12bit id combined with flags below */
722 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000
723 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)
724 #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000
725 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000
726 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000
728 /* security section */
730 #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01
731 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02
732 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04
735 __le16 pvid; /* VLANS include priority bits */
738 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00
739 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \
740 I40E_AQ_VSI_PVLAN_MODE_SHIFT)
741 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01
742 #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02
743 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03
744 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04
745 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03
746 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \
747 I40E_AQ_VSI_PVLAN_EMOD_SHIFT)
748 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0
749 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08
750 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10
751 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18
752 u8 pvlan_reserved[3];
753 /* ingress egress up sections */
754 __le32 ingress_table; /* bitmap, 3 bits per up */
755 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0
756 #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \
757 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT)
758 #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3
759 #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \
760 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT)
761 #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6
762 #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \
763 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT)
764 #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9
765 #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \
766 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT)
767 #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12
768 #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \
769 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT)
770 #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15
771 #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \
772 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT)
773 #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18
774 #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \
775 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT)
776 #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21
777 #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \
778 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT)
779 __le32 egress_table; /* same defines as for ingress table */
780 /* cascaded PV section */
783 #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00
784 #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \
785 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT)
786 #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00
787 #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01
788 #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02
789 #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10
790 #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20
791 #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40
793 /* queue mapping section */
794 __le16 mapping_flags;
795 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0
796 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1
797 __le16 queue_mapping[16];
798 #define I40E_AQ_VSI_QUEUE_SHIFT 0x0
799 #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT)
800 __le16 tc_mapping[8];
801 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0
802 #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \
803 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT)
804 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9
805 #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \
806 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)
807 /* queueing option section */
808 u8 queueing_opt_flags;
809 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10
810 #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20
811 u8 queueing_opt_reserved[3];
812 /* scheduler section */
815 /* outer up section */
816 __le32 outer_up_table; /* same structure and defines as ingress table */
818 /* last 32 bytes are written by FW */
820 #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF
821 __le16 stat_counter_idx;
823 u8 resp_reserved[12];
826 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data);
828 /* Add Port Virtualizer (direct 0x0220)
829 * also used for update PV (direct 0x0221) but only flags are used
830 * (IS_CTRL_PORT only works on add PV)
832 struct i40e_aqc_add_update_pv {
833 __le16 command_flags;
834 #define I40E_AQC_PV_FLAG_PV_TYPE 0x1
835 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2
836 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4
837 #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8
839 __le16 connected_seid;
843 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv);
845 struct i40e_aqc_add_update_pv_completion {
846 /* reserved for update; for add also encodes error if rc == ENOSPC */
848 #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1
849 #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2
850 #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4
851 #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8
855 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion);
857 /* Get PV Params (direct 0x0222)
858 * uses i40e_aqc_switch_seid for the descriptor
861 struct i40e_aqc_get_pv_params_completion {
864 __le16 pv_flags; /* same flags as add_pv */
865 #define I40E_AQC_GET_PV_PV_TYPE 0x1
866 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2
867 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4
869 __le16 default_port_seid;
872 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion);
874 /* Add VEB (direct 0x0230) */
875 struct i40e_aqc_add_veb {
877 __le16 downlink_seid;
879 #define I40E_AQC_ADD_VEB_FLOATING 0x1
880 #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1
881 #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \
882 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT)
883 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2
884 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4
885 #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8
890 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb);
892 struct i40e_aqc_add_veb_completion {
895 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */
897 #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1
898 #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2
899 #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4
900 #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8
901 __le16 statistic_index;
906 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion);
908 /* Get VEB Parameters (direct 0x0232)
909 * uses i40e_aqc_switch_seid for the descriptor
911 struct i40e_aqc_get_veb_parameters_completion {
914 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */
915 __le16 statistic_index;
921 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion);
923 /* Delete Element (direct 0x0243)
924 * uses the generic i40e_aqc_switch_seid
927 /* Add MAC-VLAN (indirect 0x0250) */
929 /* used for the command for most vlan commands */
930 struct i40e_aqc_macvlan {
931 __le16 num_addresses;
933 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0
934 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \
935 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
936 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000
941 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan);
943 /* indirect data for command and response */
944 struct i40e_aqc_add_macvlan_element_data {
948 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001
949 #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002
950 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004
951 #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008
953 #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0
954 #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \
955 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
956 /* response section */
958 #define I40E_AQC_MM_PERFECT_MATCH 0x01
959 #define I40E_AQC_MM_HASH_MATCH 0x02
960 #define I40E_AQC_MM_ERR_NO_RES 0xFF
964 struct i40e_aqc_add_remove_macvlan_completion {
965 __le16 perfect_mac_used;
966 __le16 perfect_mac_free;
967 __le16 unicast_hash_free;
968 __le16 multicast_hash_free;
973 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion);
975 /* Remove MAC-VLAN (indirect 0x0251)
976 * uses i40e_aqc_macvlan for the descriptor
977 * data points to an array of num_addresses of elements
980 struct i40e_aqc_remove_macvlan_element_data {
984 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01
985 #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02
986 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08
987 #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10
991 #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0
992 #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF
993 u8 reply_reserved[3];
996 /* Add VLAN (indirect 0x0252)
997 * Remove VLAN (indirect 0x0253)
998 * use the generic i40e_aqc_macvlan for the command
1000 struct i40e_aqc_add_remove_vlan_element_data {
1003 /* flags for add VLAN */
1004 #define I40E_AQC_ADD_VLAN_LOCAL 0x1
1005 #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1
1006 #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << \
1007 I40E_AQC_ADD_PVLAN_TYPE_SHIFT)
1008 #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0
1009 #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2
1010 #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4
1011 #define I40E_AQC_VLAN_PTYPE_SHIFT 3
1012 #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT)
1013 #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0
1014 #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8
1015 #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10
1016 #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18
1017 /* flags for remove VLAN */
1018 #define I40E_AQC_REMOVE_VLAN_ALL 0x1
1021 /* flags for add VLAN */
1022 #define I40E_AQC_ADD_VLAN_SUCCESS 0x0
1023 #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE
1024 #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF
1025 /* flags for remove VLAN */
1026 #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0
1027 #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF
1031 struct i40e_aqc_add_remove_vlan_completion {
1039 /* Set VSI Promiscuous Modes (direct 0x0254) */
1040 struct i40e_aqc_set_vsi_promiscuous_modes {
1041 __le16 promiscuous_flags;
1043 /* flags used for both fields above */
1044 #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01
1045 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02
1046 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04
1047 #define I40E_AQC_SET_VSI_DEFAULT 0x08
1048 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10
1050 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF
1052 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000
1056 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes);
1058 /* Add S/E-tag command (direct 0x0255)
1059 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1061 struct i40e_aqc_add_tag {
1063 #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001
1065 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0
1066 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1067 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT)
1069 __le16 queue_number;
1073 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag);
1075 struct i40e_aqc_add_remove_tag_completion {
1081 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion);
1083 /* Remove S/E-tag command (direct 0x0256)
1084 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1086 struct i40e_aqc_remove_tag {
1088 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0
1089 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1090 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT)
1095 /* Add multicast E-Tag (direct 0x0257)
1096 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
1097 * and no external data
1099 struct i40e_aqc_add_remove_mcast_etag {
1102 u8 num_unicast_etags;
1104 __le32 addr_high; /* address of array of 2-byte s-tags */
1108 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag);
1110 struct i40e_aqc_add_remove_mcast_etag_completion {
1112 __le16 mcast_etags_used;
1113 __le16 mcast_etags_free;
1119 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion);
1121 /* Update S/E-Tag (direct 0x0259) */
1122 struct i40e_aqc_update_tag {
1124 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0
1125 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1126 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT)
1132 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag);
1134 struct i40e_aqc_update_tag_completion {
1140 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion);
1142 /* Add Control Packet filter (direct 0x025A)
1143 * Remove Control Packet filter (direct 0x025B)
1144 * uses the i40e_aqc_add_oveb_cloud,
1145 * and the generic direct completion structure
1147 struct i40e_aqc_add_remove_control_packet_filter {
1151 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001
1152 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002
1153 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004
1154 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008
1155 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000
1157 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0
1158 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \
1159 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT)
1164 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter);
1166 struct i40e_aqc_add_remove_control_packet_filter_completion {
1167 __le16 mac_etype_used;
1169 __le16 mac_etype_free;
1174 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion);
1176 /* Add Cloud filters (indirect 0x025C)
1177 * Remove Cloud filters (indirect 0x025D)
1178 * uses the i40e_aqc_add_remove_cloud_filters,
1179 * and the generic indirect completion structure
1181 struct i40e_aqc_add_remove_cloud_filters {
1185 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0
1186 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \
1187 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)
1193 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters);
1195 struct i40e_aqc_add_remove_cloud_filters_element_data {
1209 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0
1210 #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \
1211 I40E_AQC_ADD_CLOUD_FILTER_SHIFT)
1212 /* 0x0000 reserved */
1213 #define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001
1214 /* 0x0002 reserved */
1215 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003
1216 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004
1217 /* 0x0005 reserved */
1218 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006
1219 /* 0x0007 reserved */
1220 /* 0x0008 reserved */
1221 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009
1222 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A
1223 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B
1224 #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C
1226 #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080
1227 #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6
1228 #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0
1229 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0
1230 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100
1232 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9
1233 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00
1234 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN 0
1235 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1
1236 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NGE 2
1237 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3
1241 __le16 queue_number;
1242 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0
1243 #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x3F << \
1244 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT)
1246 /* response section */
1247 u8 allocation_result;
1248 #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0
1249 #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF
1250 u8 response_reserved[7];
1253 struct i40e_aqc_remove_cloud_filters_completion {
1254 __le16 perfect_ovlan_used;
1255 __le16 perfect_ovlan_free;
1262 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion);
1264 /* Add Mirror Rule (indirect or direct 0x0260)
1265 * Delete Mirror Rule (indirect or direct 0x0261)
1266 * note: some rule types (4,5) do not use an external buffer.
1267 * take care to set the flags correctly.
1269 struct i40e_aqc_add_delete_mirror_rule {
1272 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0
1273 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \
1274 I40E_AQC_MIRROR_RULE_TYPE_SHIFT)
1275 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1
1276 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2
1277 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3
1278 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4
1279 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5
1281 __le16 destination; /* VSI for add, rule id for delete */
1282 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */
1286 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule);
1288 struct i40e_aqc_add_delete_mirror_rule_completion {
1290 __le16 rule_id; /* only used on add */
1291 __le16 mirror_rules_used;
1292 __le16 mirror_rules_free;
1297 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion);
1301 /* PFC Ignore (direct 0x0301)
1302 * the command and response use the same descriptor structure
1304 struct i40e_aqc_pfc_ignore {
1306 u8 command_flags; /* unused on response */
1307 #define I40E_AQC_PFC_IGNORE_SET 0x80
1308 #define I40E_AQC_PFC_IGNORE_CLEAR 0x0
1312 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore);
1314 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure
1315 * with no parameters
1318 /* TX scheduler 0x04xx */
1320 /* Almost all the indirect commands use
1321 * this generic struct to pass the SEID in param0
1323 struct i40e_aqc_tx_sched_ind {
1330 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind);
1332 /* Several commands respond with a set of queue set handles */
1333 struct i40e_aqc_qs_handles_resp {
1334 __le16 qs_handles[8];
1337 /* Configure VSI BW limits (direct 0x0400) */
1338 struct i40e_aqc_configure_vsi_bw_limit {
1343 u8 max_credit; /* 0-3, limit = 2^max */
1347 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit);
1349 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
1350 * responds with i40e_aqc_qs_handles_resp
1352 struct i40e_aqc_configure_vsi_ets_sla_bw_data {
1355 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */
1357 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1358 __le16 tc_bw_max[2];
1362 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
1363 * responds with i40e_aqc_qs_handles_resp
1365 struct i40e_aqc_configure_vsi_tc_bw_data {
1368 u8 tc_bw_credits[8];
1370 __le16 qs_handles[8];
1373 /* Query vsi bw configuration (indirect 0x0408) */
1374 struct i40e_aqc_query_vsi_bw_config_resp {
1376 u8 tc_suspended_bits;
1378 __le16 qs_handles[8];
1380 __le16 port_bw_limit;
1382 u8 max_bw; /* 0-3, limit = 2^max */
1386 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
1387 struct i40e_aqc_query_vsi_ets_sla_config_resp {
1390 u8 share_credits[8];
1393 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1394 __le16 tc_bw_max[2];
1397 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */
1398 struct i40e_aqc_configure_switching_comp_bw_limit {
1403 u8 max_bw; /* 0-3, limit = 2^max */
1407 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit);
1409 /* Enable Physical Port ETS (indirect 0x0413)
1410 * Modify Physical Port ETS (indirect 0x0414)
1411 * Disable Physical Port ETS (indirect 0x0415)
1413 struct i40e_aqc_configure_switching_comp_ets_data {
1417 #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1
1418 u8 tc_strict_priority_flags;
1420 u8 tc_bw_share_credits[8];
1424 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
1425 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data {
1428 __le16 tc_bw_credit[8];
1430 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1431 __le16 tc_bw_max[2];
1435 /* Configure Switching Component Bandwidth Allocation per Tc
1438 struct i40e_aqc_configure_switching_comp_bw_config_data {
1441 u8 absolute_credits; /* bool */
1442 u8 tc_bw_share_credits[8];
1446 /* Query Switching Component Configuration (indirect 0x0418) */
1447 struct i40e_aqc_query_switching_comp_ets_config_resp {
1450 __le16 port_bw_limit;
1452 u8 tc_bw_max; /* 0-3, limit = 2^max */
1456 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */
1457 struct i40e_aqc_query_port_ets_config_resp {
1461 u8 tc_strict_priority_bits;
1463 u8 tc_bw_share_credits[8];
1464 __le16 tc_bw_limits[8];
1466 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
1467 __le16 tc_bw_max[2];
1471 /* Query Switching Component Bandwidth Allocation per Traffic Type
1474 struct i40e_aqc_query_switching_comp_bw_config_resp {
1477 u8 absolute_credits_enable; /* bool */
1478 u8 tc_bw_share_credits[8];
1479 __le16 tc_bw_limits[8];
1481 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1482 __le16 tc_bw_max[2];
1485 /* Suspend/resume port TX traffic
1486 * (direct 0x041B and 0x041C) uses the generic SEID struct
1489 /* Configure partition BW
1492 struct i40e_aqc_configure_partition_bw_data {
1493 __le16 pf_valid_bits;
1494 u8 min_bw[16]; /* guaranteed bandwidth */
1495 u8 max_bw[16]; /* bandwidth limit */
1498 /* Get and set the active HMC resource profile and status.
1499 * (direct 0x0500) and (direct 0x0501)
1501 struct i40e_aq_get_set_hmc_resource_profile {
1507 I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile);
1509 enum i40e_aq_hmc_profile {
1510 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */
1511 I40E_HMC_PROFILE_DEFAULT = 1,
1512 I40E_HMC_PROFILE_FAVOR_VF = 2,
1513 I40E_HMC_PROFILE_EQUAL = 3,
1516 #define I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK 0xF
1517 #define I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK 0x3F
1519 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
1521 /* set in param0 for get phy abilities to report qualified modules */
1522 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001
1523 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002
1525 enum i40e_aq_phy_type {
1526 I40E_PHY_TYPE_SGMII = 0x0,
1527 I40E_PHY_TYPE_1000BASE_KX = 0x1,
1528 I40E_PHY_TYPE_10GBASE_KX4 = 0x2,
1529 I40E_PHY_TYPE_10GBASE_KR = 0x3,
1530 I40E_PHY_TYPE_40GBASE_KR4 = 0x4,
1531 I40E_PHY_TYPE_XAUI = 0x5,
1532 I40E_PHY_TYPE_XFI = 0x6,
1533 I40E_PHY_TYPE_SFI = 0x7,
1534 I40E_PHY_TYPE_XLAUI = 0x8,
1535 I40E_PHY_TYPE_XLPPI = 0x9,
1536 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA,
1537 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB,
1538 I40E_PHY_TYPE_10GBASE_AOC = 0xC,
1539 I40E_PHY_TYPE_40GBASE_AOC = 0xD,
1540 I40E_PHY_TYPE_100BASE_TX = 0x11,
1541 I40E_PHY_TYPE_1000BASE_T = 0x12,
1542 I40E_PHY_TYPE_10GBASE_T = 0x13,
1543 I40E_PHY_TYPE_10GBASE_SR = 0x14,
1544 I40E_PHY_TYPE_10GBASE_LR = 0x15,
1545 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16,
1546 I40E_PHY_TYPE_10GBASE_CR1 = 0x17,
1547 I40E_PHY_TYPE_40GBASE_CR4 = 0x18,
1548 I40E_PHY_TYPE_40GBASE_SR4 = 0x19,
1549 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A,
1550 I40E_PHY_TYPE_1000BASE_SX = 0x1B,
1551 I40E_PHY_TYPE_1000BASE_LX = 0x1C,
1552 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D,
1553 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E,
1557 #define I40E_LINK_SPEED_100MB_SHIFT 0x1
1558 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2
1559 #define I40E_LINK_SPEED_10GB_SHIFT 0x3
1560 #define I40E_LINK_SPEED_40GB_SHIFT 0x4
1561 #define I40E_LINK_SPEED_20GB_SHIFT 0x5
1563 enum i40e_aq_link_speed {
1564 I40E_LINK_SPEED_UNKNOWN = 0,
1565 I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT),
1566 I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT),
1567 I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT),
1568 I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT),
1569 I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT)
1572 struct i40e_aqc_module_desc {
1580 struct i40e_aq_get_phy_abilities_resp {
1581 __le32 phy_type; /* bitmap using the above enum for offsets */
1582 u8 link_speed; /* bitmap using the above enum bit patterns */
1584 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01
1585 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02
1586 #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04
1587 #define I40E_AQ_PHY_LINK_ENABLED 0x08
1588 #define I40E_AQ_PHY_AN_ENABLED 0x10
1589 #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20
1590 __le16 eee_capability;
1591 #define I40E_AQ_EEE_100BASE_TX 0x0002
1592 #define I40E_AQ_EEE_1000BASE_T 0x0004
1593 #define I40E_AQ_EEE_10GBASE_T 0x0008
1594 #define I40E_AQ_EEE_1000BASE_KX 0x0010
1595 #define I40E_AQ_EEE_10GBASE_KX4 0x0020
1596 #define I40E_AQ_EEE_10GBASE_KR 0x0040
1599 #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01
1603 u8 qualified_module_count;
1604 #define I40E_AQ_PHY_MAX_QMS 16
1605 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS];
1608 /* Set PHY Config (direct 0x0601) */
1609 struct i40e_aq_set_phy_config { /* same bits as above in all */
1613 /* bits 0-2 use the values from get_phy_abilities_resp */
1614 #define I40E_AQ_PHY_ENABLE_LINK 0x08
1615 #define I40E_AQ_PHY_ENABLE_AN 0x10
1616 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20
1617 __le16 eee_capability;
1623 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);
1625 /* Set MAC Config command data structure (direct 0x0603) */
1626 struct i40e_aq_set_mac_config {
1627 __le16 max_frame_size;
1629 #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04
1630 #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78
1631 #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3
1632 #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0
1633 #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF
1634 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9
1635 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8
1636 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7
1637 #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6
1638 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5
1639 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4
1640 #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3
1641 #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2
1642 #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1
1643 u8 tx_timer_priority; /* bitmap */
1644 __le16 tx_timer_value;
1645 __le16 fc_refresh_threshold;
1649 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config);
1651 /* Restart Auto-Negotiation (direct 0x605) */
1652 struct i40e_aqc_set_link_restart_an {
1654 #define I40E_AQ_PHY_RESTART_AN 0x02
1655 #define I40E_AQ_PHY_LINK_ENABLE 0x04
1659 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an);
1661 /* Get Link Status cmd & response data structure (direct 0x0607) */
1662 struct i40e_aqc_get_link_status {
1663 __le16 command_flags; /* only field set on command */
1664 #define I40E_AQ_LSE_MASK 0x3
1665 #define I40E_AQ_LSE_NOP 0x0
1666 #define I40E_AQ_LSE_DISABLE 0x2
1667 #define I40E_AQ_LSE_ENABLE 0x3
1668 /* only response uses this flag */
1669 #define I40E_AQ_LSE_IS_ENABLED 0x1
1670 u8 phy_type; /* i40e_aq_phy_type */
1671 u8 link_speed; /* i40e_aq_link_speed */
1673 #define I40E_AQ_LINK_UP 0x01
1674 #define I40E_AQ_LINK_FAULT 0x02
1675 #define I40E_AQ_LINK_FAULT_TX 0x04
1676 #define I40E_AQ_LINK_FAULT_RX 0x08
1677 #define I40E_AQ_LINK_FAULT_REMOTE 0x10
1678 #define I40E_AQ_MEDIA_AVAILABLE 0x40
1679 #define I40E_AQ_SIGNAL_DETECT 0x80
1681 #define I40E_AQ_AN_COMPLETED 0x01
1682 #define I40E_AQ_LP_AN_ABILITY 0x02
1683 #define I40E_AQ_PD_FAULT 0x04
1684 #define I40E_AQ_FEC_EN 0x08
1685 #define I40E_AQ_PHY_LOW_POWER 0x10
1686 #define I40E_AQ_LINK_PAUSE_TX 0x20
1687 #define I40E_AQ_LINK_PAUSE_RX 0x40
1688 #define I40E_AQ_QUALIFIED_MODULE 0x80
1690 #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01
1691 #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02
1692 #define I40E_AQ_LINK_TX_SHIFT 0x02
1693 #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT)
1694 #define I40E_AQ_LINK_TX_ACTIVE 0x00
1695 #define I40E_AQ_LINK_TX_DRAINED 0x01
1696 #define I40E_AQ_LINK_TX_FLUSHED 0x03
1697 #define I40E_AQ_LINK_FORCED_40G 0x10
1698 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */
1699 __le16 max_frame_size;
1701 #define I40E_AQ_CONFIG_CRC_ENA 0x04
1702 #define I40E_AQ_CONFIG_PACING_MASK 0x78
1706 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status);
1708 /* Set event mask command (direct 0x613) */
1709 struct i40e_aqc_set_phy_int_mask {
1712 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002
1713 #define I40E_AQ_EVENT_MEDIA_NA 0x0004
1714 #define I40E_AQ_EVENT_LINK_FAULT 0x0008
1715 #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010
1716 #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020
1717 #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040
1718 #define I40E_AQ_EVENT_AN_COMPLETED 0x0080
1719 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100
1720 #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200
1724 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask);
1726 /* Get Local AN advt register (direct 0x0614)
1727 * Set Local AN advt register (direct 0x0615)
1728 * Get Link Partner AN advt register (direct 0x0616)
1730 struct i40e_aqc_an_advt_reg {
1731 __le32 local_an_reg0;
1732 __le16 local_an_reg1;
1736 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg);
1738 /* Set Loopback mode (0x0618) */
1739 struct i40e_aqc_set_lb_mode {
1741 #define I40E_AQ_LB_PHY_LOCAL 0x01
1742 #define I40E_AQ_LB_PHY_REMOTE 0x02
1743 #define I40E_AQ_LB_MAC_LOCAL 0x04
1747 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode);
1749 /* Set PHY Debug command (0x0622) */
1750 struct i40e_aqc_set_phy_debug {
1752 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02
1753 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2
1754 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \
1755 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)
1756 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00
1757 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01
1758 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02
1759 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10
1763 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug);
1765 enum i40e_aq_phy_reg_type {
1766 I40E_AQC_PHY_REG_INTERNAL = 0x1,
1767 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2,
1768 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3
1771 /* NVM Read command (indirect 0x0701)
1772 * NVM Erase commands (direct 0x0702)
1773 * NVM Update commands (indirect 0x0703)
1775 struct i40e_aqc_nvm_update {
1777 #define I40E_AQ_NVM_LAST_CMD 0x01
1778 #define I40E_AQ_NVM_FLASH_ONLY 0x80
1786 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);
1788 /* NVM Config Read (indirect 0x0704) */
1789 struct i40e_aqc_nvm_config_read {
1791 #define ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1
1792 #define ANVM_READ_SINGLE_FEATURE 0
1793 #define ANVM_READ_MULTIPLE_FEATURES 1
1794 __le16 element_count;
1795 __le16 element_id; /* Feature/field ID */
1797 __le32 address_high;
1801 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read);
1803 /* NVM Config Write (indirect 0x0705) */
1804 struct i40e_aqc_nvm_config_write {
1806 __le16 element_count;
1808 __le32 address_high;
1812 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);
1814 struct i40e_aqc_nvm_config_data_feature {
1817 __le16 feature_options;
1818 __le16 feature_selection;
1821 struct i40e_aqc_nvm_config_data_immediate_field {
1822 #define ANVM_FEATURE_OR_IMMEDIATE_MASK 0x2
1825 __le16 field_options;
1829 /* Send to PF command (indirect 0x0801) id is only used by PF
1830 * Send to VF command (indirect 0x0802) id is only used by PF
1831 * Send to Peer PF command (indirect 0x0803)
1833 struct i40e_aqc_pf_vf_message {
1840 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message);
1842 /* Alternate structure */
1844 /* Direct write (direct 0x0900)
1845 * Direct read (direct 0x0902)
1847 struct i40e_aqc_alternate_write {
1854 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write);
1856 /* Indirect write (indirect 0x0901)
1857 * Indirect read (indirect 0x0903)
1860 struct i40e_aqc_alternate_ind_write {
1867 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write);
1869 /* Done alternate write (direct 0x0904)
1872 struct i40e_aqc_alternate_write_done {
1874 #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1
1875 #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0
1876 #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1
1877 #define I40E_AQ_ALTERNATE_RESET_NEEDED 2
1881 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done);
1883 /* Set OEM mode (direct 0x0905) */
1884 struct i40e_aqc_alternate_set_mode {
1886 #define I40E_AQ_ALTERNATE_MODE_NONE 0
1887 #define I40E_AQ_ALTERNATE_MODE_OEM 1
1891 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode);
1893 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */
1895 /* async events 0x10xx */
1897 /* Lan Queue Overflow Event (direct, 0x1001) */
1898 struct i40e_aqc_lan_overflow {
1899 __le32 prtdcb_rupto;
1904 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow);
1906 /* Get LLDP MIB (indirect 0x0A00) */
1907 struct i40e_aqc_lldp_get_mib {
1910 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3
1911 #define I40E_AQ_LLDP_MIB_LOCAL 0x0
1912 #define I40E_AQ_LLDP_MIB_REMOTE 0x1
1913 #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2
1914 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC
1915 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2
1916 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0
1917 #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1
1918 #define I40E_AQ_LLDP_TX_SHIFT 0x4
1919 #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT)
1920 /* TX pause flags use I40E_AQ_LINK_TX_* above */
1928 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib);
1930 /* Configure LLDP MIB Change Event (direct 0x0A01)
1931 * also used for the event (with type in the command field)
1933 struct i40e_aqc_lldp_update_mib {
1935 #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
1936 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1
1942 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib);
1944 /* Add LLDP TLV (indirect 0x0A02)
1945 * Delete LLDP TLV (indirect 0x0A04)
1947 struct i40e_aqc_lldp_add_tlv {
1948 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
1956 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv);
1958 /* Update LLDP TLV (indirect 0x0A03) */
1959 struct i40e_aqc_lldp_update_tlv {
1960 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
1969 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv);
1971 /* Stop LLDP (direct 0x0A05) */
1972 struct i40e_aqc_lldp_stop {
1974 #define I40E_AQ_LLDP_AGENT_STOP 0x0
1975 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1
1979 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop);
1981 /* Start LLDP (direct 0x0A06) */
1983 struct i40e_aqc_lldp_start {
1985 #define I40E_AQ_LLDP_AGENT_START 0x1
1989 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start);
1991 /* Apply MIB changes (0x0A07)
1992 * uses the generic struc as it contains no data
1995 /* Add Udp Tunnel command and completion (direct 0x0B00) */
1996 struct i40e_aqc_add_udp_tunnel {
2000 #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00
2001 #define I40E_AQC_TUNNEL_TYPE_NGE 0x01
2002 #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10
2006 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel);
2008 struct i40e_aqc_add_udp_tunnel_completion {
2010 u8 filter_entry_index;
2012 #define I40E_AQC_SINGLE_PF 0x0
2013 #define I40E_AQC_MULTIPLE_PFS 0x1
2018 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion);
2020 /* remove UDP Tunnel command (0x0B01) */
2021 struct i40e_aqc_remove_udp_tunnel {
2023 u8 index; /* 0 to 15 */
2027 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel);
2029 struct i40e_aqc_del_udp_tunnel_completion {
2031 u8 index; /* 0 to 15 */
2033 u8 total_filters_used;
2037 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);
2039 /* tunnel key structure 0x0B10 */
2041 struct i40e_aqc_tunnel_key_structure {
2044 u8 key1_len; /* 0 to 15 */
2045 u8 key2_len; /* 0 to 15 */
2047 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
2048 /* response flags */
2049 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01
2050 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02
2051 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
2052 u8 network_key_index;
2053 #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0
2054 #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1
2055 #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2
2056 #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3
2060 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure);
2062 /* OEM mode commands (direct 0xFE0x) */
2063 struct i40e_aqc_oem_param_change {
2065 #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0
2066 #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1
2067 #define I40E_AQ_OEM_PARAM_MAC 2
2068 __le32 param_value1;
2072 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change);
2074 struct i40e_aqc_oem_state_change {
2076 #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0
2077 #define I40E_AQ_OEM_STATE_LINK_UP 0x1
2081 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change);
2083 /* debug commands */
2085 /* get device id (0xFF00) uses the generic structure */
2087 /* set test more (0xFF01, internal) */
2089 struct i40e_acq_set_test_mode {
2091 #define I40E_AQ_TEST_PARTIAL 0
2092 #define I40E_AQ_TEST_FULL 1
2093 #define I40E_AQ_TEST_NVM 2
2096 #define I40E_AQ_TEST_OPEN 0
2097 #define I40E_AQ_TEST_CLOSE 1
2098 #define I40E_AQ_TEST_INC 2
2100 __le32 address_high;
2104 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode);
2106 /* Debug Read Register command (0xFF03)
2107 * Debug Write Register command (0xFF04)
2109 struct i40e_aqc_debug_reg_read_write {
2116 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write);
2118 /* Scatter/gather Reg Read (indirect 0xFF05)
2119 * Scatter/gather Reg Write (indirect 0xFF06)
2122 /* i40e_aq_desc is used for the command */
2123 struct i40e_aqc_debug_reg_sg_element_data {
2128 /* Debug Modify register (direct 0xFF07) */
2129 struct i40e_aqc_debug_modify_reg {
2136 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg);
2138 /* dump internal data (0xFF08, indirect) */
2140 #define I40E_AQ_CLUSTER_ID_AUX 0
2141 #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1
2142 #define I40E_AQ_CLUSTER_ID_TXSCHED 2
2143 #define I40E_AQ_CLUSTER_ID_HMC 3
2144 #define I40E_AQ_CLUSTER_ID_MAC0 4
2145 #define I40E_AQ_CLUSTER_ID_MAC1 5
2146 #define I40E_AQ_CLUSTER_ID_MAC2 6
2147 #define I40E_AQ_CLUSTER_ID_MAC3 7
2148 #define I40E_AQ_CLUSTER_ID_DCB 8
2149 #define I40E_AQ_CLUSTER_ID_EMP_MEM 9
2150 #define I40E_AQ_CLUSTER_ID_PKT_BUF 10
2151 #define I40E_AQ_CLUSTER_ID_ALTRAM 11
2153 struct i40e_aqc_debug_dump_internals {
2158 __le32 address_high;
2162 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals);
2164 struct i40e_aqc_debug_modify_internals {
2166 u8 cluster_specific_params[7];
2167 __le32 address_high;
2171 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals);