1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
4 #include "i40e_status.h"
6 #include "i40e_register.h"
7 #include "i40e_adminq.h"
8 #include "i40e_prototype.h"
10 static void i40e_resume_aq(struct i40e_hw *hw);
13 * i40e_adminq_init_regs - Initialize AdminQ registers
14 * @hw: pointer to the hardware structure
16 * This assumes the alloc_asq and alloc_arq functions have already been called
18 static void i40e_adminq_init_regs(struct i40e_hw *hw)
20 /* set head and tail registers in our local struct */
22 hw->aq.asq.tail = I40E_VF_ATQT1;
23 hw->aq.asq.head = I40E_VF_ATQH1;
24 hw->aq.asq.len = I40E_VF_ATQLEN1;
25 hw->aq.asq.bal = I40E_VF_ATQBAL1;
26 hw->aq.asq.bah = I40E_VF_ATQBAH1;
27 hw->aq.arq.tail = I40E_VF_ARQT1;
28 hw->aq.arq.head = I40E_VF_ARQH1;
29 hw->aq.arq.len = I40E_VF_ARQLEN1;
30 hw->aq.arq.bal = I40E_VF_ARQBAL1;
31 hw->aq.arq.bah = I40E_VF_ARQBAH1;
33 hw->aq.asq.tail = I40E_PF_ATQT;
34 hw->aq.asq.head = I40E_PF_ATQH;
35 hw->aq.asq.len = I40E_PF_ATQLEN;
36 hw->aq.asq.bal = I40E_PF_ATQBAL;
37 hw->aq.asq.bah = I40E_PF_ATQBAH;
38 hw->aq.arq.tail = I40E_PF_ARQT;
39 hw->aq.arq.head = I40E_PF_ARQH;
40 hw->aq.arq.len = I40E_PF_ARQLEN;
41 hw->aq.arq.bal = I40E_PF_ARQBAL;
42 hw->aq.arq.bah = I40E_PF_ARQBAH;
47 * i40e_alloc_adminq_asq_ring - Allocate Admin Queue send rings
48 * @hw: pointer to the hardware structure
50 static i40e_status i40e_alloc_adminq_asq_ring(struct i40e_hw *hw)
54 ret_code = i40e_allocate_dma_mem(hw, &hw->aq.asq.desc_buf,
56 (hw->aq.num_asq_entries *
57 sizeof(struct i40e_aq_desc)),
58 I40E_ADMINQ_DESC_ALIGNMENT);
62 ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.cmd_buf,
63 (hw->aq.num_asq_entries *
64 sizeof(struct i40e_asq_cmd_details)));
66 i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);
74 * i40e_alloc_adminq_arq_ring - Allocate Admin Queue receive rings
75 * @hw: pointer to the hardware structure
77 static i40e_status i40e_alloc_adminq_arq_ring(struct i40e_hw *hw)
81 ret_code = i40e_allocate_dma_mem(hw, &hw->aq.arq.desc_buf,
83 (hw->aq.num_arq_entries *
84 sizeof(struct i40e_aq_desc)),
85 I40E_ADMINQ_DESC_ALIGNMENT);
91 * i40e_free_adminq_asq - Free Admin Queue send rings
92 * @hw: pointer to the hardware structure
94 * This assumes the posted send buffers have already been cleaned
97 static void i40e_free_adminq_asq(struct i40e_hw *hw)
99 i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);
103 * i40e_free_adminq_arq - Free Admin Queue receive rings
104 * @hw: pointer to the hardware structure
106 * This assumes the posted receive buffers have already been cleaned
109 static void i40e_free_adminq_arq(struct i40e_hw *hw)
111 i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf);
115 * i40e_alloc_arq_bufs - Allocate pre-posted buffers for the receive queue
116 * @hw: pointer to the hardware structure
118 static i40e_status i40e_alloc_arq_bufs(struct i40e_hw *hw)
120 i40e_status ret_code;
121 struct i40e_aq_desc *desc;
122 struct i40e_dma_mem *bi;
125 /* We'll be allocating the buffer info memory first, then we can
126 * allocate the mapped buffers for the event processing
129 /* buffer_info structures do not need alignment */
130 ret_code = i40e_allocate_virt_mem(hw, &hw->aq.arq.dma_head,
131 (hw->aq.num_arq_entries * sizeof(struct i40e_dma_mem)));
134 hw->aq.arq.r.arq_bi = (struct i40e_dma_mem *)hw->aq.arq.dma_head.va;
136 /* allocate the mapped buffers */
137 for (i = 0; i < hw->aq.num_arq_entries; i++) {
138 bi = &hw->aq.arq.r.arq_bi[i];
139 ret_code = i40e_allocate_dma_mem(hw, bi,
142 I40E_ADMINQ_DESC_ALIGNMENT);
144 goto unwind_alloc_arq_bufs;
146 /* now configure the descriptors for use */
147 desc = I40E_ADMINQ_DESC(hw->aq.arq, i);
149 desc->flags = cpu_to_le16(I40E_AQ_FLAG_BUF);
150 if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF)
151 desc->flags |= cpu_to_le16(I40E_AQ_FLAG_LB);
153 /* This is in accordance with Admin queue design, there is no
154 * register for buffer size configuration
156 desc->datalen = cpu_to_le16((u16)bi->size);
158 desc->cookie_high = 0;
159 desc->cookie_low = 0;
160 desc->params.external.addr_high =
161 cpu_to_le32(upper_32_bits(bi->pa));
162 desc->params.external.addr_low =
163 cpu_to_le32(lower_32_bits(bi->pa));
164 desc->params.external.param0 = 0;
165 desc->params.external.param1 = 0;
171 unwind_alloc_arq_bufs:
172 /* don't try to free the one that failed... */
175 i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]);
176 i40e_free_virt_mem(hw, &hw->aq.arq.dma_head);
182 * i40e_alloc_asq_bufs - Allocate empty buffer structs for the send queue
183 * @hw: pointer to the hardware structure
185 static i40e_status i40e_alloc_asq_bufs(struct i40e_hw *hw)
187 i40e_status ret_code;
188 struct i40e_dma_mem *bi;
191 /* No mapped memory needed yet, just the buffer info structures */
192 ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.dma_head,
193 (hw->aq.num_asq_entries * sizeof(struct i40e_dma_mem)));
196 hw->aq.asq.r.asq_bi = (struct i40e_dma_mem *)hw->aq.asq.dma_head.va;
198 /* allocate the mapped buffers */
199 for (i = 0; i < hw->aq.num_asq_entries; i++) {
200 bi = &hw->aq.asq.r.asq_bi[i];
201 ret_code = i40e_allocate_dma_mem(hw, bi,
204 I40E_ADMINQ_DESC_ALIGNMENT);
206 goto unwind_alloc_asq_bufs;
211 unwind_alloc_asq_bufs:
212 /* don't try to free the one that failed... */
215 i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]);
216 i40e_free_virt_mem(hw, &hw->aq.asq.dma_head);
222 * i40e_free_arq_bufs - Free receive queue buffer info elements
223 * @hw: pointer to the hardware structure
225 static void i40e_free_arq_bufs(struct i40e_hw *hw)
229 /* free descriptors */
230 for (i = 0; i < hw->aq.num_arq_entries; i++)
231 i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]);
233 /* free the descriptor memory */
234 i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf);
236 /* free the dma header */
237 i40e_free_virt_mem(hw, &hw->aq.arq.dma_head);
241 * i40e_free_asq_bufs - Free send queue buffer info elements
242 * @hw: pointer to the hardware structure
244 static void i40e_free_asq_bufs(struct i40e_hw *hw)
248 /* only unmap if the address is non-NULL */
249 for (i = 0; i < hw->aq.num_asq_entries; i++)
250 if (hw->aq.asq.r.asq_bi[i].pa)
251 i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]);
253 /* free the buffer info list */
254 i40e_free_virt_mem(hw, &hw->aq.asq.cmd_buf);
256 /* free the descriptor memory */
257 i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);
259 /* free the dma header */
260 i40e_free_virt_mem(hw, &hw->aq.asq.dma_head);
264 * i40e_config_asq_regs - configure ASQ registers
265 * @hw: pointer to the hardware structure
267 * Configure base address and length registers for the transmit queue
269 static i40e_status i40e_config_asq_regs(struct i40e_hw *hw)
271 i40e_status ret_code = 0;
274 /* Clear Head and Tail */
275 wr32(hw, hw->aq.asq.head, 0);
276 wr32(hw, hw->aq.asq.tail, 0);
278 /* set starting point */
279 wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries |
280 I40E_PF_ATQLEN_ATQENABLE_MASK));
281 wr32(hw, hw->aq.asq.bal, lower_32_bits(hw->aq.asq.desc_buf.pa));
282 wr32(hw, hw->aq.asq.bah, upper_32_bits(hw->aq.asq.desc_buf.pa));
284 /* Check one register to verify that config was applied */
285 reg = rd32(hw, hw->aq.asq.bal);
286 if (reg != lower_32_bits(hw->aq.asq.desc_buf.pa))
287 ret_code = I40E_ERR_ADMIN_QUEUE_ERROR;
293 * i40e_config_arq_regs - ARQ register configuration
294 * @hw: pointer to the hardware structure
296 * Configure base address and length registers for the receive (event queue)
298 static i40e_status i40e_config_arq_regs(struct i40e_hw *hw)
300 i40e_status ret_code = 0;
303 /* Clear Head and Tail */
304 wr32(hw, hw->aq.arq.head, 0);
305 wr32(hw, hw->aq.arq.tail, 0);
307 /* set starting point */
308 wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries |
309 I40E_PF_ARQLEN_ARQENABLE_MASK));
310 wr32(hw, hw->aq.arq.bal, lower_32_bits(hw->aq.arq.desc_buf.pa));
311 wr32(hw, hw->aq.arq.bah, upper_32_bits(hw->aq.arq.desc_buf.pa));
313 /* Update tail in the HW to post pre-allocated buffers */
314 wr32(hw, hw->aq.arq.tail, hw->aq.num_arq_entries - 1);
316 /* Check one register to verify that config was applied */
317 reg = rd32(hw, hw->aq.arq.bal);
318 if (reg != lower_32_bits(hw->aq.arq.desc_buf.pa))
319 ret_code = I40E_ERR_ADMIN_QUEUE_ERROR;
325 * i40e_init_asq - main initialization routine for ASQ
326 * @hw: pointer to the hardware structure
328 * This is the main initialization routine for the Admin Send Queue
329 * Prior to calling this function, drivers *MUST* set the following fields
330 * in the hw->aq structure:
331 * - hw->aq.num_asq_entries
332 * - hw->aq.arq_buf_size
334 * Do *NOT* hold the lock when calling this as the memory allocation routines
335 * called are not going to be atomic context safe
337 static i40e_status i40e_init_asq(struct i40e_hw *hw)
339 i40e_status ret_code = 0;
341 if (hw->aq.asq.count > 0) {
342 /* queue already initialized */
343 ret_code = I40E_ERR_NOT_READY;
344 goto init_adminq_exit;
347 /* verify input for valid configuration */
348 if ((hw->aq.num_asq_entries == 0) ||
349 (hw->aq.asq_buf_size == 0)) {
350 ret_code = I40E_ERR_CONFIG;
351 goto init_adminq_exit;
354 hw->aq.asq.next_to_use = 0;
355 hw->aq.asq.next_to_clean = 0;
357 /* allocate the ring memory */
358 ret_code = i40e_alloc_adminq_asq_ring(hw);
360 goto init_adminq_exit;
362 /* allocate buffers in the rings */
363 ret_code = i40e_alloc_asq_bufs(hw);
365 goto init_adminq_free_rings;
367 /* initialize base registers */
368 ret_code = i40e_config_asq_regs(hw);
370 goto init_adminq_free_rings;
373 hw->aq.asq.count = hw->aq.num_asq_entries;
374 goto init_adminq_exit;
376 init_adminq_free_rings:
377 i40e_free_adminq_asq(hw);
384 * i40e_init_arq - initialize ARQ
385 * @hw: pointer to the hardware structure
387 * The main initialization routine for the Admin Receive (Event) Queue.
388 * Prior to calling this function, drivers *MUST* set the following fields
389 * in the hw->aq structure:
390 * - hw->aq.num_asq_entries
391 * - hw->aq.arq_buf_size
393 * Do *NOT* hold the lock when calling this as the memory allocation routines
394 * called are not going to be atomic context safe
396 static i40e_status i40e_init_arq(struct i40e_hw *hw)
398 i40e_status ret_code = 0;
400 if (hw->aq.arq.count > 0) {
401 /* queue already initialized */
402 ret_code = I40E_ERR_NOT_READY;
403 goto init_adminq_exit;
406 /* verify input for valid configuration */
407 if ((hw->aq.num_arq_entries == 0) ||
408 (hw->aq.arq_buf_size == 0)) {
409 ret_code = I40E_ERR_CONFIG;
410 goto init_adminq_exit;
413 hw->aq.arq.next_to_use = 0;
414 hw->aq.arq.next_to_clean = 0;
416 /* allocate the ring memory */
417 ret_code = i40e_alloc_adminq_arq_ring(hw);
419 goto init_adminq_exit;
421 /* allocate buffers in the rings */
422 ret_code = i40e_alloc_arq_bufs(hw);
424 goto init_adminq_free_rings;
426 /* initialize base registers */
427 ret_code = i40e_config_arq_regs(hw);
429 goto init_adminq_free_rings;
432 hw->aq.arq.count = hw->aq.num_arq_entries;
433 goto init_adminq_exit;
435 init_adminq_free_rings:
436 i40e_free_adminq_arq(hw);
443 * i40e_shutdown_asq - shutdown the ASQ
444 * @hw: pointer to the hardware structure
446 * The main shutdown routine for the Admin Send Queue
448 static i40e_status i40e_shutdown_asq(struct i40e_hw *hw)
450 i40e_status ret_code = 0;
452 mutex_lock(&hw->aq.asq_mutex);
454 if (hw->aq.asq.count == 0) {
455 ret_code = I40E_ERR_NOT_READY;
456 goto shutdown_asq_out;
459 /* Stop firmware AdminQ processing */
460 wr32(hw, hw->aq.asq.head, 0);
461 wr32(hw, hw->aq.asq.tail, 0);
462 wr32(hw, hw->aq.asq.len, 0);
463 wr32(hw, hw->aq.asq.bal, 0);
464 wr32(hw, hw->aq.asq.bah, 0);
466 hw->aq.asq.count = 0; /* to indicate uninitialized queue */
468 /* free ring buffers */
469 i40e_free_asq_bufs(hw);
472 mutex_unlock(&hw->aq.asq_mutex);
477 * i40e_shutdown_arq - shutdown ARQ
478 * @hw: pointer to the hardware structure
480 * The main shutdown routine for the Admin Receive Queue
482 static i40e_status i40e_shutdown_arq(struct i40e_hw *hw)
484 i40e_status ret_code = 0;
486 mutex_lock(&hw->aq.arq_mutex);
488 if (hw->aq.arq.count == 0) {
489 ret_code = I40E_ERR_NOT_READY;
490 goto shutdown_arq_out;
493 /* Stop firmware AdminQ processing */
494 wr32(hw, hw->aq.arq.head, 0);
495 wr32(hw, hw->aq.arq.tail, 0);
496 wr32(hw, hw->aq.arq.len, 0);
497 wr32(hw, hw->aq.arq.bal, 0);
498 wr32(hw, hw->aq.arq.bah, 0);
500 hw->aq.arq.count = 0; /* to indicate uninitialized queue */
502 /* free ring buffers */
503 i40e_free_arq_bufs(hw);
506 mutex_unlock(&hw->aq.arq_mutex);
511 * i40e_init_adminq - main initialization routine for Admin Queue
512 * @hw: pointer to the hardware structure
514 * Prior to calling this function, drivers *MUST* set the following fields
515 * in the hw->aq structure:
516 * - hw->aq.num_asq_entries
517 * - hw->aq.num_arq_entries
518 * - hw->aq.arq_buf_size
519 * - hw->aq.asq_buf_size
521 i40e_status i40e_init_adminq(struct i40e_hw *hw)
523 u16 cfg_ptr, oem_hi, oem_lo;
524 u16 eetrack_lo, eetrack_hi;
525 i40e_status ret_code;
528 /* verify input for valid configuration */
529 if ((hw->aq.num_arq_entries == 0) ||
530 (hw->aq.num_asq_entries == 0) ||
531 (hw->aq.arq_buf_size == 0) ||
532 (hw->aq.asq_buf_size == 0)) {
533 ret_code = I40E_ERR_CONFIG;
534 goto init_adminq_exit;
537 /* Set up register offsets */
538 i40e_adminq_init_regs(hw);
540 /* setup ASQ command write back timeout */
541 hw->aq.asq_cmd_timeout = I40E_ASQ_CMD_TIMEOUT;
543 /* allocate the ASQ */
544 ret_code = i40e_init_asq(hw);
546 goto init_adminq_destroy_locks;
548 /* allocate the ARQ */
549 ret_code = i40e_init_arq(hw);
551 goto init_adminq_free_asq;
553 /* There are some cases where the firmware may not be quite ready
554 * for AdminQ operations, so we retry the AdminQ setup a few times
555 * if we see timeouts in this first AQ call.
558 ret_code = i40e_aq_get_firmware_version(hw,
565 if (ret_code != I40E_ERR_ADMIN_QUEUE_TIMEOUT)
570 } while (retry < 10);
571 if (ret_code != I40E_SUCCESS)
572 goto init_adminq_free_arq;
574 /* get the NVM version info */
575 i40e_read_nvm_word(hw, I40E_SR_NVM_DEV_STARTER_VERSION,
577 i40e_read_nvm_word(hw, I40E_SR_NVM_EETRACK_LO, &eetrack_lo);
578 i40e_read_nvm_word(hw, I40E_SR_NVM_EETRACK_HI, &eetrack_hi);
579 hw->nvm.eetrack = (eetrack_hi << 16) | eetrack_lo;
580 i40e_read_nvm_word(hw, I40E_SR_BOOT_CONFIG_PTR, &cfg_ptr);
581 i40e_read_nvm_word(hw, (cfg_ptr + I40E_NVM_OEM_VER_OFF),
583 i40e_read_nvm_word(hw, (cfg_ptr + (I40E_NVM_OEM_VER_OFF + 1)),
585 hw->nvm.oem_ver = ((u32)oem_hi << 16) | oem_lo;
587 if (hw->mac.type == I40E_MAC_XL710 &&
588 hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
589 hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) {
590 hw->flags |= I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE;
591 hw->flags |= I40E_HW_FLAG_FW_LLDP_STOPPABLE;
593 if (hw->mac.type == I40E_MAC_X722 &&
594 hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
595 hw->aq.api_min_ver >= I40E_MINOR_VER_FW_LLDP_STOPPABLE_X722) {
596 hw->flags |= I40E_HW_FLAG_FW_LLDP_STOPPABLE;
599 /* Newer versions of firmware require lock when reading the NVM */
600 if (hw->aq.api_maj_ver > 1 ||
601 (hw->aq.api_maj_ver == 1 &&
602 hw->aq.api_min_ver >= 5))
603 hw->flags |= I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK;
605 /* The ability to RX (not drop) 802.1ad frames was added in API 1.7 */
606 if (hw->aq.api_maj_ver > 1 ||
607 (hw->aq.api_maj_ver == 1 &&
608 hw->aq.api_min_ver >= 7))
609 hw->flags |= I40E_HW_FLAG_802_1AD_CAPABLE;
611 if (hw->aq.api_maj_ver > I40E_FW_API_VERSION_MAJOR) {
612 ret_code = I40E_ERR_FIRMWARE_API_VERSION;
613 goto init_adminq_free_arq;
616 /* pre-emptive resource lock release */
617 i40e_aq_release_resource(hw, I40E_NVM_RESOURCE_ID, 0, NULL);
618 hw->nvm_release_on_done = false;
619 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
624 goto init_adminq_exit;
626 init_adminq_free_arq:
627 i40e_shutdown_arq(hw);
628 init_adminq_free_asq:
629 i40e_shutdown_asq(hw);
630 init_adminq_destroy_locks:
637 * i40e_shutdown_adminq - shutdown routine for the Admin Queue
638 * @hw: pointer to the hardware structure
640 i40e_status i40e_shutdown_adminq(struct i40e_hw *hw)
642 i40e_status ret_code = 0;
644 if (i40e_check_asq_alive(hw))
645 i40e_aq_queue_shutdown(hw, true);
647 i40e_shutdown_asq(hw);
648 i40e_shutdown_arq(hw);
651 i40e_free_virt_mem(hw, &hw->nvm_buff);
657 * i40e_clean_asq - cleans Admin send queue
658 * @hw: pointer to the hardware structure
660 * returns the number of free desc
662 static u16 i40e_clean_asq(struct i40e_hw *hw)
664 struct i40e_adminq_ring *asq = &(hw->aq.asq);
665 struct i40e_asq_cmd_details *details;
666 u16 ntc = asq->next_to_clean;
667 struct i40e_aq_desc desc_cb;
668 struct i40e_aq_desc *desc;
670 desc = I40E_ADMINQ_DESC(*asq, ntc);
671 details = I40E_ADMINQ_DETAILS(*asq, ntc);
672 while (rd32(hw, hw->aq.asq.head) != ntc) {
673 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
674 "ntc %d head %d.\n", ntc, rd32(hw, hw->aq.asq.head));
676 if (details->callback) {
677 I40E_ADMINQ_CALLBACK cb_func =
678 (I40E_ADMINQ_CALLBACK)details->callback;
680 cb_func(hw, &desc_cb);
682 memset(desc, 0, sizeof(*desc));
683 memset(details, 0, sizeof(*details));
685 if (ntc == asq->count)
687 desc = I40E_ADMINQ_DESC(*asq, ntc);
688 details = I40E_ADMINQ_DETAILS(*asq, ntc);
691 asq->next_to_clean = ntc;
693 return I40E_DESC_UNUSED(asq);
697 * i40e_asq_done - check if FW has processed the Admin Send Queue
698 * @hw: pointer to the hw struct
700 * Returns true if the firmware has processed all descriptors on the
701 * admin send queue. Returns false if there are still requests pending.
703 static bool i40e_asq_done(struct i40e_hw *hw)
705 /* AQ designers suggest use of head for better
706 * timing reliability than DD bit
708 return rd32(hw, hw->aq.asq.head) == hw->aq.asq.next_to_use;
713 * i40e_asq_send_command - send command to Admin Queue
714 * @hw: pointer to the hw struct
715 * @desc: prefilled descriptor describing the command (non DMA mem)
716 * @buff: buffer to use for indirect commands
717 * @buff_size: size of buffer for indirect commands
718 * @cmd_details: pointer to command details structure
720 * This is the main send command driver routine for the Admin Queue send
721 * queue. It runs the queue, cleans the queue, etc
723 i40e_status i40e_asq_send_command(struct i40e_hw *hw,
724 struct i40e_aq_desc *desc,
725 void *buff, /* can be NULL */
727 struct i40e_asq_cmd_details *cmd_details)
729 i40e_status status = 0;
730 struct i40e_dma_mem *dma_buff = NULL;
731 struct i40e_asq_cmd_details *details;
732 struct i40e_aq_desc *desc_on_ring;
733 bool cmd_completed = false;
737 mutex_lock(&hw->aq.asq_mutex);
739 if (hw->aq.asq.count == 0) {
740 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
741 "AQTX: Admin queue not initialized.\n");
742 status = I40E_ERR_QUEUE_EMPTY;
743 goto asq_send_command_error;
746 hw->aq.asq_last_status = I40E_AQ_RC_OK;
748 val = rd32(hw, hw->aq.asq.head);
749 if (val >= hw->aq.num_asq_entries) {
750 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
751 "AQTX: head overrun at %d\n", val);
752 status = I40E_ERR_QUEUE_EMPTY;
753 goto asq_send_command_error;
756 details = I40E_ADMINQ_DETAILS(hw->aq.asq, hw->aq.asq.next_to_use);
758 *details = *cmd_details;
760 /* If the cmd_details are defined copy the cookie. The
761 * cpu_to_le32 is not needed here because the data is ignored
762 * by the FW, only used by the driver
764 if (details->cookie) {
766 cpu_to_le32(upper_32_bits(details->cookie));
768 cpu_to_le32(lower_32_bits(details->cookie));
771 memset(details, 0, sizeof(struct i40e_asq_cmd_details));
774 /* clear requested flags and then set additional flags if defined */
775 desc->flags &= ~cpu_to_le16(details->flags_dis);
776 desc->flags |= cpu_to_le16(details->flags_ena);
778 if (buff_size > hw->aq.asq_buf_size) {
780 I40E_DEBUG_AQ_MESSAGE,
781 "AQTX: Invalid buffer size: %d.\n",
783 status = I40E_ERR_INVALID_SIZE;
784 goto asq_send_command_error;
787 if (details->postpone && !details->async) {
789 I40E_DEBUG_AQ_MESSAGE,
790 "AQTX: Async flag not set along with postpone flag");
791 status = I40E_ERR_PARAM;
792 goto asq_send_command_error;
795 /* call clean and check queue available function to reclaim the
796 * descriptors that were processed by FW, the function returns the
797 * number of desc available
799 /* the clean function called here could be called in a separate thread
800 * in case of asynchronous completions
802 if (i40e_clean_asq(hw) == 0) {
804 I40E_DEBUG_AQ_MESSAGE,
805 "AQTX: Error queue is full.\n");
806 status = I40E_ERR_ADMIN_QUEUE_FULL;
807 goto asq_send_command_error;
810 /* initialize the temp desc pointer with the right desc */
811 desc_on_ring = I40E_ADMINQ_DESC(hw->aq.asq, hw->aq.asq.next_to_use);
813 /* if the desc is available copy the temp desc to the right place */
814 *desc_on_ring = *desc;
816 /* if buff is not NULL assume indirect command */
818 dma_buff = &(hw->aq.asq.r.asq_bi[hw->aq.asq.next_to_use]);
819 /* copy the user buff into the respective DMA buff */
820 memcpy(dma_buff->va, buff, buff_size);
821 desc_on_ring->datalen = cpu_to_le16(buff_size);
823 /* Update the address values in the desc with the pa value
824 * for respective buffer
826 desc_on_ring->params.external.addr_high =
827 cpu_to_le32(upper_32_bits(dma_buff->pa));
828 desc_on_ring->params.external.addr_low =
829 cpu_to_le32(lower_32_bits(dma_buff->pa));
833 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, "AQTX: desc and buffer:\n");
834 i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc_on_ring,
836 (hw->aq.asq.next_to_use)++;
837 if (hw->aq.asq.next_to_use == hw->aq.asq.count)
838 hw->aq.asq.next_to_use = 0;
839 if (!details->postpone)
840 wr32(hw, hw->aq.asq.tail, hw->aq.asq.next_to_use);
842 /* if cmd_details are not defined or async flag is not set,
843 * we need to wait for desc write back
845 if (!details->async && !details->postpone) {
849 /* AQ designers suggest use of head for better
850 * timing reliability than DD bit
852 if (i40e_asq_done(hw))
856 } while (total_delay < hw->aq.asq_cmd_timeout);
859 /* if ready, copy the desc back to temp */
860 if (i40e_asq_done(hw)) {
861 *desc = *desc_on_ring;
863 memcpy(buff, dma_buff->va, buff_size);
864 retval = le16_to_cpu(desc->retval);
867 I40E_DEBUG_AQ_MESSAGE,
868 "AQTX: Command completed with error 0x%X.\n",
871 /* strip off FW internal code */
874 cmd_completed = true;
875 if ((enum i40e_admin_queue_err)retval == I40E_AQ_RC_OK)
877 else if ((enum i40e_admin_queue_err)retval == I40E_AQ_RC_EBUSY)
878 status = I40E_ERR_NOT_READY;
880 status = I40E_ERR_ADMIN_QUEUE_ERROR;
881 hw->aq.asq_last_status = (enum i40e_admin_queue_err)retval;
884 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
885 "AQTX: desc and buffer writeback:\n");
886 i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, buff, buff_size);
888 /* save writeback aq if requested */
889 if (details->wb_desc)
890 *details->wb_desc = *desc_on_ring;
892 /* update the error if time out occurred */
893 if ((!cmd_completed) &&
894 (!details->async && !details->postpone)) {
895 if (rd32(hw, hw->aq.asq.len) & I40E_GL_ATQLEN_ATQCRIT_MASK) {
896 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
897 "AQTX: AQ Critical error.\n");
898 status = I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR;
900 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
901 "AQTX: Writeback timeout.\n");
902 status = I40E_ERR_ADMIN_QUEUE_TIMEOUT;
906 asq_send_command_error:
907 mutex_unlock(&hw->aq.asq_mutex);
912 * i40e_fill_default_direct_cmd_desc - AQ descriptor helper function
913 * @desc: pointer to the temp descriptor (non DMA mem)
914 * @opcode: the opcode can be used to decide which flags to turn off or on
916 * Fill the desc with default values
918 void i40e_fill_default_direct_cmd_desc(struct i40e_aq_desc *desc,
921 /* zero out the desc */
922 memset((void *)desc, 0, sizeof(struct i40e_aq_desc));
923 desc->opcode = cpu_to_le16(opcode);
924 desc->flags = cpu_to_le16(I40E_AQ_FLAG_SI);
928 * i40e_clean_arq_element
929 * @hw: pointer to the hw struct
930 * @e: event info from the receive descriptor, includes any buffers
931 * @pending: number of events that could be left to process
933 * This function cleans one Admin Receive Queue element and returns
934 * the contents through e. It can also return how many events are
935 * left to process through 'pending'
937 i40e_status i40e_clean_arq_element(struct i40e_hw *hw,
938 struct i40e_arq_event_info *e,
941 i40e_status ret_code = 0;
942 u16 ntc = hw->aq.arq.next_to_clean;
943 struct i40e_aq_desc *desc;
944 struct i40e_dma_mem *bi;
950 /* pre-clean the event info */
951 memset(&e->desc, 0, sizeof(e->desc));
953 /* take the lock before we start messing with the ring */
954 mutex_lock(&hw->aq.arq_mutex);
956 if (hw->aq.arq.count == 0) {
957 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
958 "AQRX: Admin queue not initialized.\n");
959 ret_code = I40E_ERR_QUEUE_EMPTY;
960 goto clean_arq_element_err;
963 /* set next_to_use to head */
964 ntu = rd32(hw, hw->aq.arq.head) & I40E_PF_ARQH_ARQH_MASK;
966 /* nothing to do - shouldn't need to update ring's values */
967 ret_code = I40E_ERR_ADMIN_QUEUE_NO_WORK;
968 goto clean_arq_element_out;
971 /* now clean the next descriptor */
972 desc = I40E_ADMINQ_DESC(hw->aq.arq, ntc);
975 hw->aq.arq_last_status =
976 (enum i40e_admin_queue_err)le16_to_cpu(desc->retval);
977 flags = le16_to_cpu(desc->flags);
978 if (flags & I40E_AQ_FLAG_ERR) {
979 ret_code = I40E_ERR_ADMIN_QUEUE_ERROR;
981 I40E_DEBUG_AQ_MESSAGE,
982 "AQRX: Event received with error 0x%X.\n",
983 hw->aq.arq_last_status);
987 datalen = le16_to_cpu(desc->datalen);
988 e->msg_len = min(datalen, e->buf_len);
989 if (e->msg_buf != NULL && (e->msg_len != 0))
990 memcpy(e->msg_buf, hw->aq.arq.r.arq_bi[desc_idx].va,
993 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, "AQRX: desc and buffer:\n");
994 i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, e->msg_buf,
995 hw->aq.arq_buf_size);
997 /* Restore the original datalen and buffer address in the desc,
998 * FW updates datalen to indicate the event message
1001 bi = &hw->aq.arq.r.arq_bi[ntc];
1002 memset((void *)desc, 0, sizeof(struct i40e_aq_desc));
1004 desc->flags = cpu_to_le16(I40E_AQ_FLAG_BUF);
1005 if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF)
1006 desc->flags |= cpu_to_le16(I40E_AQ_FLAG_LB);
1007 desc->datalen = cpu_to_le16((u16)bi->size);
1008 desc->params.external.addr_high = cpu_to_le32(upper_32_bits(bi->pa));
1009 desc->params.external.addr_low = cpu_to_le32(lower_32_bits(bi->pa));
1011 /* set tail = the last cleaned desc index. */
1012 wr32(hw, hw->aq.arq.tail, ntc);
1013 /* ntc is updated to tail + 1 */
1015 if (ntc == hw->aq.num_arq_entries)
1017 hw->aq.arq.next_to_clean = ntc;
1018 hw->aq.arq.next_to_use = ntu;
1020 i40e_nvmupd_check_wait_event(hw, le16_to_cpu(e->desc.opcode), &e->desc);
1021 clean_arq_element_out:
1022 /* Set pending if needed, unlock and return */
1024 *pending = (ntc > ntu ? hw->aq.arq.count : 0) + (ntu - ntc);
1025 clean_arq_element_err:
1026 mutex_unlock(&hw->aq.arq_mutex);
1031 static void i40e_resume_aq(struct i40e_hw *hw)
1033 /* Registers are reset after PF reset */
1034 hw->aq.asq.next_to_use = 0;
1035 hw->aq.asq.next_to_clean = 0;
1037 i40e_config_asq_regs(hw);
1039 hw->aq.arq.next_to_use = 0;
1040 hw->aq.arq.next_to_clean = 0;
1042 i40e_config_arq_regs(hw);