1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
7 * e1000_raise_eec_clk - Raise EEPROM clock
8 * @hw: pointer to the HW structure
9 * @eecd: pointer to the EEPROM
11 * Enable/Raise the EEPROM clock bit.
13 static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
15 *eecd = *eecd | E1000_EECD_SK;
18 udelay(hw->nvm.delay_usec);
22 * e1000_lower_eec_clk - Lower EEPROM clock
23 * @hw: pointer to the HW structure
24 * @eecd: pointer to the EEPROM
26 * Clear/Lower the EEPROM clock bit.
28 static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
30 *eecd = *eecd & ~E1000_EECD_SK;
33 udelay(hw->nvm.delay_usec);
37 * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM
38 * @hw: pointer to the HW structure
39 * @data: data to send to the EEPROM
40 * @count: number of bits to shift out
42 * We need to shift 'count' bits out to the EEPROM. So, the value in the
43 * "data" parameter will be shifted out to the EEPROM one bit at a time.
44 * In order to do this, "data" must be broken down into bits.
46 static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
48 struct e1000_nvm_info *nvm = &hw->nvm;
49 u32 eecd = er32(EECD);
52 mask = BIT(count - 1);
53 if (nvm->type == e1000_nvm_eeprom_spi)
54 eecd |= E1000_EECD_DO;
57 eecd &= ~E1000_EECD_DI;
60 eecd |= E1000_EECD_DI;
65 udelay(nvm->delay_usec);
67 e1000_raise_eec_clk(hw, &eecd);
68 e1000_lower_eec_clk(hw, &eecd);
73 eecd &= ~E1000_EECD_DI;
78 * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM
79 * @hw: pointer to the HW structure
80 * @count: number of bits to shift in
82 * In order to read a register from the EEPROM, we need to shift 'count' bits
83 * in from the EEPROM. Bits are "shifted in" by raising the clock input to
84 * the EEPROM (setting the SK bit), and then reading the value of the data out
85 * "DO" bit. During this "shifting in" process the data in "DI" bit should
88 static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
95 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
98 for (i = 0; i < count; i++) {
100 e1000_raise_eec_clk(hw, &eecd);
104 eecd &= ~E1000_EECD_DI;
105 if (eecd & E1000_EECD_DO)
108 e1000_lower_eec_clk(hw, &eecd);
115 * e1000e_poll_eerd_eewr_done - Poll for EEPROM read/write completion
116 * @hw: pointer to the HW structure
117 * @ee_reg: EEPROM flag for polling
119 * Polls the EEPROM status bit for either read or write completion based
120 * upon the value of 'ee_reg'.
122 s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
124 u32 attempts = 100000;
127 for (i = 0; i < attempts; i++) {
128 if (ee_reg == E1000_NVM_POLL_READ)
133 if (reg & E1000_NVM_RW_REG_DONE)
139 return -E1000_ERR_NVM;
143 * e1000e_acquire_nvm - Generic request for access to EEPROM
144 * @hw: pointer to the HW structure
146 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
147 * Return successful if access grant bit set, else clear the request for
148 * EEPROM access and return -E1000_ERR_NVM (-1).
150 s32 e1000e_acquire_nvm(struct e1000_hw *hw)
152 u32 eecd = er32(EECD);
153 s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
155 ew32(EECD, eecd | E1000_EECD_REQ);
159 if (eecd & E1000_EECD_GNT)
167 eecd &= ~E1000_EECD_REQ;
169 e_dbg("Could not acquire NVM grant\n");
170 return -E1000_ERR_NVM;
177 * e1000_standby_nvm - Return EEPROM to standby state
178 * @hw: pointer to the HW structure
180 * Return the EEPROM to a standby state.
182 static void e1000_standby_nvm(struct e1000_hw *hw)
184 struct e1000_nvm_info *nvm = &hw->nvm;
185 u32 eecd = er32(EECD);
187 if (nvm->type == e1000_nvm_eeprom_spi) {
188 /* Toggle CS to flush commands */
189 eecd |= E1000_EECD_CS;
192 udelay(nvm->delay_usec);
193 eecd &= ~E1000_EECD_CS;
196 udelay(nvm->delay_usec);
201 * e1000_stop_nvm - Terminate EEPROM command
202 * @hw: pointer to the HW structure
204 * Terminates the current command by inverting the EEPROM's chip select pin.
206 static void e1000_stop_nvm(struct e1000_hw *hw)
211 if (hw->nvm.type == e1000_nvm_eeprom_spi) {
213 eecd |= E1000_EECD_CS;
214 e1000_lower_eec_clk(hw, &eecd);
219 * e1000e_release_nvm - Release exclusive access to EEPROM
220 * @hw: pointer to the HW structure
222 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
224 void e1000e_release_nvm(struct e1000_hw *hw)
231 eecd &= ~E1000_EECD_REQ;
236 * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write
237 * @hw: pointer to the HW structure
239 * Setups the EEPROM for reading and writing.
241 static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
243 struct e1000_nvm_info *nvm = &hw->nvm;
244 u32 eecd = er32(EECD);
247 if (nvm->type == e1000_nvm_eeprom_spi) {
248 u16 timeout = NVM_MAX_RETRY_SPI;
250 /* Clear SK and CS */
251 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
256 /* Read "Status Register" repeatedly until the LSB is cleared.
257 * The EEPROM will signal that the command has been completed
258 * by clearing bit 0 of the internal status register. If it's
259 * not cleared within 'timeout', then error out.
262 e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
263 hw->nvm.opcode_bits);
264 spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
265 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
269 e1000_standby_nvm(hw);
274 e_dbg("SPI NVM Status error\n");
275 return -E1000_ERR_NVM;
283 * e1000e_read_nvm_eerd - Reads EEPROM using EERD register
284 * @hw: pointer to the HW structure
285 * @offset: offset of word in the EEPROM to read
286 * @words: number of words to read
287 * @data: word read from the EEPROM
289 * Reads a 16 bit word from the EEPROM using the EERD register.
291 s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
293 struct e1000_nvm_info *nvm = &hw->nvm;
297 /* A check for invalid values: offset too large, too many words,
298 * too many words for the offset, and not enough words.
300 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
302 e_dbg("nvm parameter(s) out of bounds\n");
303 return -E1000_ERR_NVM;
306 for (i = 0; i < words; i++) {
307 eerd = ((offset + i) << E1000_NVM_RW_ADDR_SHIFT) +
308 E1000_NVM_RW_REG_START;
311 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
313 e_dbg("NVM read error: %d\n", ret_val);
317 data[i] = (er32(EERD) >> E1000_NVM_RW_REG_DATA);
324 * e1000e_write_nvm_spi - Write to EEPROM using SPI
325 * @hw: pointer to the HW structure
326 * @offset: offset within the EEPROM to be written to
327 * @words: number of words to write
328 * @data: 16 bit word(s) to be written to the EEPROM
330 * Writes data to EEPROM at offset using SPI interface.
332 * If e1000e_update_nvm_checksum is not called after this function , the
333 * EEPROM will most likely contain an invalid checksum.
335 s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
337 struct e1000_nvm_info *nvm = &hw->nvm;
338 s32 ret_val = -E1000_ERR_NVM;
341 /* A check for invalid values: offset too large, too many words,
342 * and not enough words.
344 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
346 e_dbg("nvm parameter(s) out of bounds\n");
347 return -E1000_ERR_NVM;
350 while (widx < words) {
351 u8 write_opcode = NVM_WRITE_OPCODE_SPI;
353 ret_val = nvm->ops.acquire(hw);
357 ret_val = e1000_ready_nvm_eeprom(hw);
359 nvm->ops.release(hw);
363 e1000_standby_nvm(hw);
365 /* Send the WRITE ENABLE command (8 bit opcode) */
366 e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
369 e1000_standby_nvm(hw);
371 /* Some SPI eeproms use the 8th address bit embedded in the
374 if ((nvm->address_bits == 8) && (offset >= 128))
375 write_opcode |= NVM_A8_OPCODE_SPI;
377 /* Send the Write command (8-bit opcode + addr) */
378 e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
379 e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
382 /* Loop to allow for up to whole page write of eeprom */
383 while (widx < words) {
384 u16 word_out = data[widx];
386 word_out = (word_out >> 8) | (word_out << 8);
387 e1000_shift_out_eec_bits(hw, word_out, 16);
390 if ((((offset + widx) * 2) % nvm->page_size) == 0) {
391 e1000_standby_nvm(hw);
395 usleep_range(10000, 20000);
396 nvm->ops.release(hw);
403 * e1000_read_pba_string_generic - Read device part number
404 * @hw: pointer to the HW structure
405 * @pba_num: pointer to device part number
406 * @pba_num_size: size of part number buffer
408 * Reads the product board assembly (PBA) number from the EEPROM and stores
409 * the value in pba_num.
411 s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
420 if (pba_num == NULL) {
421 e_dbg("PBA string buffer was null\n");
422 return -E1000_ERR_INVALID_ARGUMENT;
425 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
427 e_dbg("NVM Read Error\n");
431 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
433 e_dbg("NVM Read Error\n");
437 /* if nvm_data is not ptr guard the PBA must be in legacy format which
438 * means pba_ptr is actually our second data word for the PBA number
439 * and we can decode it into an ascii string
441 if (nvm_data != NVM_PBA_PTR_GUARD) {
442 e_dbg("NVM PBA number is not stored as string\n");
444 /* make sure callers buffer is big enough to store the PBA */
445 if (pba_num_size < E1000_PBANUM_LENGTH) {
446 e_dbg("PBA string buffer too small\n");
447 return E1000_ERR_NO_SPACE;
450 /* extract hex string from data and pba_ptr */
451 pba_num[0] = (nvm_data >> 12) & 0xF;
452 pba_num[1] = (nvm_data >> 8) & 0xF;
453 pba_num[2] = (nvm_data >> 4) & 0xF;
454 pba_num[3] = nvm_data & 0xF;
455 pba_num[4] = (pba_ptr >> 12) & 0xF;
456 pba_num[5] = (pba_ptr >> 8) & 0xF;
459 pba_num[8] = (pba_ptr >> 4) & 0xF;
460 pba_num[9] = pba_ptr & 0xF;
462 /* put a null character on the end of our string */
465 /* switch all the data but the '-' to hex char */
466 for (offset = 0; offset < 10; offset++) {
467 if (pba_num[offset] < 0xA)
468 pba_num[offset] += '0';
469 else if (pba_num[offset] < 0x10)
470 pba_num[offset] += 'A' - 0xA;
476 ret_val = e1000_read_nvm(hw, pba_ptr, 1, &length);
478 e_dbg("NVM Read Error\n");
482 if (length == 0xFFFF || length == 0) {
483 e_dbg("NVM PBA number section invalid length\n");
484 return -E1000_ERR_NVM_PBA_SECTION;
486 /* check if pba_num buffer is big enough */
487 if (pba_num_size < (((u32)length * 2) - 1)) {
488 e_dbg("PBA string buffer too small\n");
489 return -E1000_ERR_NO_SPACE;
492 /* trim pba length from start of string */
496 for (offset = 0; offset < length; offset++) {
497 ret_val = e1000_read_nvm(hw, pba_ptr + offset, 1, &nvm_data);
499 e_dbg("NVM Read Error\n");
502 pba_num[offset * 2] = (u8)(nvm_data >> 8);
503 pba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF);
505 pba_num[offset * 2] = '\0';
511 * e1000_read_mac_addr_generic - Read device MAC address
512 * @hw: pointer to the HW structure
514 * Reads the device MAC address from the EEPROM and stores the value.
515 * Since devices with two ports use the same EEPROM, we increment the
516 * last bit in the MAC address for the second port.
518 s32 e1000_read_mac_addr_generic(struct e1000_hw *hw)
524 rar_high = er32(RAH(0));
525 rar_low = er32(RAL(0));
527 for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
528 hw->mac.perm_addr[i] = (u8)(rar_low >> (i * 8));
530 for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
531 hw->mac.perm_addr[i + 4] = (u8)(rar_high >> (i * 8));
533 for (i = 0; i < ETH_ALEN; i++)
534 hw->mac.addr[i] = hw->mac.perm_addr[i];
540 * e1000e_validate_nvm_checksum_generic - Validate EEPROM checksum
541 * @hw: pointer to the HW structure
543 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
544 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
546 s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw)
552 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
553 ret_val = e1000_read_nvm(hw, i, 1, &nvm_data);
555 e_dbg("NVM Read Error\n");
558 checksum += nvm_data;
561 if (checksum != (u16)NVM_SUM) {
562 e_dbg("NVM Checksum Invalid\n");
563 return -E1000_ERR_NVM;
570 * e1000e_update_nvm_checksum_generic - Update EEPROM checksum
571 * @hw: pointer to the HW structure
573 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
574 * up to the checksum. Then calculates the EEPROM checksum and writes the
575 * value to the EEPROM.
577 s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw)
583 for (i = 0; i < NVM_CHECKSUM_REG; i++) {
584 ret_val = e1000_read_nvm(hw, i, 1, &nvm_data);
586 e_dbg("NVM Read Error while updating checksum.\n");
589 checksum += nvm_data;
591 checksum = (u16)NVM_SUM - checksum;
592 ret_val = e1000_write_nvm(hw, NVM_CHECKSUM_REG, 1, &checksum);
594 e_dbg("NVM Write Error while updating checksum.\n");
600 * e1000e_reload_nvm_generic - Reloads EEPROM
601 * @hw: pointer to the HW structure
603 * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
604 * extended control register.
606 void e1000e_reload_nvm_generic(struct e1000_hw *hw)
610 usleep_range(10, 20);
611 ctrl_ext = er32(CTRL_EXT);
612 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
613 ew32(CTRL_EXT, ctrl_ext);