1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2011 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
32 e1000_mng_mode_none = 0,
36 e1000_mng_mode_host_if_only
39 #define E1000_FACTPS_MNGCG 0x20000000
41 /* Intel(R) Active Management Technology signature */
42 #define E1000_IAMT_SIGNATURE 0x544D4149
45 * e1000e_get_bus_info_pcie - Get PCIe bus information
46 * @hw: pointer to the HW structure
48 * Determines and stores the system bus information for a particular
49 * network interface. The following bus information is determined and stored:
50 * bus speed, bus width, type (PCIe), and PCIe function.
52 s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw)
54 struct e1000_mac_info *mac = &hw->mac;
55 struct e1000_bus_info *bus = &hw->bus;
56 struct e1000_adapter *adapter = hw->adapter;
57 u16 pcie_link_status, cap_offset;
59 cap_offset = adapter->pdev->pcie_cap;
61 bus->width = e1000_bus_width_unknown;
63 pci_read_config_word(adapter->pdev,
64 cap_offset + PCIE_LINK_STATUS,
66 bus->width = (enum e1000_bus_width)((pcie_link_status &
67 PCIE_LINK_WIDTH_MASK) >>
68 PCIE_LINK_WIDTH_SHIFT);
71 mac->ops.set_lan_id(hw);
77 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
79 * @hw: pointer to the HW structure
81 * Determines the LAN function id by reading memory-mapped registers
82 * and swaps the port value if requested.
84 void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw)
86 struct e1000_bus_info *bus = &hw->bus;
90 * The status register reports the correct function number
91 * for the device regardless of function swap state.
94 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT;
98 * e1000_set_lan_id_single_port - Set LAN id for a single port device
99 * @hw: pointer to the HW structure
101 * Sets the LAN function id to zero for a single port device.
103 void e1000_set_lan_id_single_port(struct e1000_hw *hw)
105 struct e1000_bus_info *bus = &hw->bus;
111 * e1000_clear_vfta_generic - Clear VLAN filter table
112 * @hw: pointer to the HW structure
114 * Clears the register array which contains the VLAN filter table by
115 * setting all the values to 0.
117 void e1000_clear_vfta_generic(struct e1000_hw *hw)
121 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
122 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
128 * e1000_write_vfta_generic - Write value to VLAN filter table
129 * @hw: pointer to the HW structure
130 * @offset: register offset in VLAN filter table
131 * @value: register value written to VLAN filter table
133 * Writes value at the given offset in the register array which stores
134 * the VLAN filter table.
136 void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)
138 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
143 * e1000e_init_rx_addrs - Initialize receive address's
144 * @hw: pointer to the HW structure
145 * @rar_count: receive address registers
147 * Setup the receive address registers by setting the base receive address
148 * register to the devices MAC address and clearing all the other receive
149 * address registers to 0.
151 void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count)
154 u8 mac_addr[ETH_ALEN] = {0};
156 /* Setup the receive address */
157 e_dbg("Programming MAC Address into RAR[0]\n");
159 e1000e_rar_set(hw, hw->mac.addr, 0);
161 /* Zero out the other (rar_entry_count - 1) receive addresses */
162 e_dbg("Clearing RAR[1-%u]\n", rar_count-1);
163 for (i = 1; i < rar_count; i++)
164 e1000e_rar_set(hw, mac_addr, i);
168 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr
169 * @hw: pointer to the HW structure
171 * Checks the nvm for an alternate MAC address. An alternate MAC address
172 * can be setup by pre-boot software and must be treated like a permanent
173 * address and must override the actual permanent MAC address. If an
174 * alternate MAC address is found it is programmed into RAR0, replacing
175 * the permanent address that was installed into RAR0 by the Si on reset.
176 * This function will return SUCCESS unless it encounters an error while
177 * reading the EEPROM.
179 s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw)
183 u16 offset, nvm_alt_mac_addr_offset, nvm_data;
184 u8 alt_mac_addr[ETH_ALEN];
186 ret_val = e1000_read_nvm(hw, NVM_COMPAT, 1, &nvm_data);
190 /* not supported on older hardware or 82573 */
191 if ((hw->mac.type < e1000_82571) || (hw->mac.type == e1000_82573))
194 ret_val = e1000_read_nvm(hw, NVM_ALT_MAC_ADDR_PTR, 1,
195 &nvm_alt_mac_addr_offset);
197 e_dbg("NVM Read Error\n");
201 if ((nvm_alt_mac_addr_offset == 0xFFFF) ||
202 (nvm_alt_mac_addr_offset == 0x0000))
203 /* There is no Alternate MAC Address */
206 if (hw->bus.func == E1000_FUNC_1)
207 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1;
208 for (i = 0; i < ETH_ALEN; i += 2) {
209 offset = nvm_alt_mac_addr_offset + (i >> 1);
210 ret_val = e1000_read_nvm(hw, offset, 1, &nvm_data);
212 e_dbg("NVM Read Error\n");
216 alt_mac_addr[i] = (u8)(nvm_data & 0xFF);
217 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);
220 /* if multicast bit is set, the alternate address will not be used */
221 if (is_multicast_ether_addr(alt_mac_addr)) {
222 e_dbg("Ignoring Alternate Mac Address with MC bit set\n");
227 * We have a valid alternate MAC address, and we want to treat it the
228 * same as the normal permanent MAC address stored by the HW into the
229 * RAR. Do this by mapping this address into RAR0.
231 e1000e_rar_set(hw, alt_mac_addr, 0);
238 * e1000e_rar_set - Set receive address register
239 * @hw: pointer to the HW structure
240 * @addr: pointer to the receive address
241 * @index: receive address array register
243 * Sets the receive address array register at index to the address passed
246 void e1000e_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)
248 u32 rar_low, rar_high;
251 * HW expects these in little endian so we reverse the byte order
252 * from network order (big endian) to little endian
254 rar_low = ((u32) addr[0] |
255 ((u32) addr[1] << 8) |
256 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
258 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
260 /* If MAC address zero, no need to set the AV bit */
261 if (rar_low || rar_high)
262 rar_high |= E1000_RAH_AV;
265 * Some bridges will combine consecutive 32-bit writes into
266 * a single burst write, which will malfunction on some parts.
267 * The flushes avoid this.
269 ew32(RAL(index), rar_low);
271 ew32(RAH(index), rar_high);
276 * e1000_hash_mc_addr - Generate a multicast hash value
277 * @hw: pointer to the HW structure
278 * @mc_addr: pointer to a multicast address
280 * Generates a multicast address hash value which is used to determine
281 * the multicast filter table array address and new table value. See
282 * e1000_mta_set_generic()
284 static u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
286 u32 hash_value, hash_mask;
289 /* Register count multiplied by bits per register */
290 hash_mask = (hw->mac.mta_reg_count * 32) - 1;
293 * For a mc_filter_type of 0, bit_shift is the number of left-shifts
294 * where 0xFF would still fall within the hash mask.
296 while (hash_mask >> bit_shift != 0xFF)
300 * The portion of the address that is used for the hash table
301 * is determined by the mc_filter_type setting.
302 * The algorithm is such that there is a total of 8 bits of shifting.
303 * The bit_shift for a mc_filter_type of 0 represents the number of
304 * left-shifts where the MSB of mc_addr[5] would still fall within
305 * the hash_mask. Case 0 does this exactly. Since there are a total
306 * of 8 bits of shifting, then mc_addr[4] will shift right the
307 * remaining number of bits. Thus 8 - bit_shift. The rest of the
308 * cases are a variation of this algorithm...essentially raising the
309 * number of bits to shift mc_addr[5] left, while still keeping the
310 * 8-bit shifting total.
312 * For example, given the following Destination MAC Address and an
313 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
314 * we can see that the bit_shift for case 0 is 4. These are the hash
315 * values resulting from each mc_filter_type...
316 * [0] [1] [2] [3] [4] [5]
320 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
321 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
322 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
323 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
325 switch (hw->mac.mc_filter_type) {
340 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
341 (((u16) mc_addr[5]) << bit_shift)));
347 * e1000e_update_mc_addr_list_generic - Update Multicast addresses
348 * @hw: pointer to the HW structure
349 * @mc_addr_list: array of multicast addresses to program
350 * @mc_addr_count: number of multicast addresses to program
352 * Updates entire Multicast Table Array.
353 * The caller must have a packed mc_addr_list of multicast addresses.
355 void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw,
356 u8 *mc_addr_list, u32 mc_addr_count)
358 u32 hash_value, hash_bit, hash_reg;
361 /* clear mta_shadow */
362 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
364 /* update mta_shadow from mc_addr_list */
365 for (i = 0; (u32) i < mc_addr_count; i++) {
366 hash_value = e1000_hash_mc_addr(hw, mc_addr_list);
368 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
369 hash_bit = hash_value & 0x1F;
371 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit);
372 mc_addr_list += (ETH_ALEN);
375 /* replace the entire MTA table */
376 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)
377 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]);
382 * e1000e_clear_hw_cntrs_base - Clear base hardware counters
383 * @hw: pointer to the HW structure
385 * Clears the base hardware counters by reading the counter registers.
387 void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw)
429 * e1000e_check_for_copper_link - Check for link (Copper)
430 * @hw: pointer to the HW structure
432 * Checks to see of the link status of the hardware has changed. If a
433 * change in link status has been detected, then we read the PHY registers
434 * to get the current speed/duplex if link exists.
436 s32 e1000e_check_for_copper_link(struct e1000_hw *hw)
438 struct e1000_mac_info *mac = &hw->mac;
443 * We only want to go out to the PHY registers to see if Auto-Neg
444 * has completed and/or if our link status has changed. The
445 * get_link_status flag is set upon receiving a Link Status
446 * Change or Rx Sequence Error interrupt.
448 if (!mac->get_link_status)
452 * First we want to see if the MII Status Register reports
453 * link. If so, then we want to get the current speed/duplex
456 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
461 return ret_val; /* No link detected */
463 mac->get_link_status = false;
466 * Check if there was DownShift, must be checked
467 * immediately after link-up
469 e1000e_check_downshift(hw);
472 * If we are forcing speed/duplex, then we simply return since
473 * we have already determined whether we have link or not.
476 ret_val = -E1000_ERR_CONFIG;
481 * Auto-Neg is enabled. Auto Speed Detection takes care
482 * of MAC speed/duplex configuration. So we only need to
483 * configure Collision Distance in the MAC.
485 e1000e_config_collision_dist(hw);
488 * Configure Flow Control now that Auto-Neg has completed.
489 * First, we need to restore the desired flow control
490 * settings because we may have had to re-autoneg with a
491 * different link partner.
493 ret_val = e1000e_config_fc_after_link_up(hw);
495 e_dbg("Error configuring flow control\n");
501 * e1000e_check_for_fiber_link - Check for link (Fiber)
502 * @hw: pointer to the HW structure
504 * Checks for link up on the hardware. If link is not up and we have
505 * a signal, then we need to force link up.
507 s32 e1000e_check_for_fiber_link(struct e1000_hw *hw)
509 struct e1000_mac_info *mac = &hw->mac;
516 status = er32(STATUS);
520 * If we don't have link (auto-negotiation failed or link partner
521 * cannot auto-negotiate), the cable is plugged in (we have signal),
522 * and our link partner is not trying to auto-negotiate with us (we
523 * are receiving idles or data), we need to force link up. We also
524 * need to give auto-negotiation time to complete, in case the cable
525 * was just plugged in. The autoneg_failed flag does this.
527 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
528 if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) &&
529 (!(rxcw & E1000_RXCW_C))) {
530 if (mac->autoneg_failed == 0) {
531 mac->autoneg_failed = 1;
534 e_dbg("NOT Rx'ing /C/, disable AutoNeg and force link.\n");
536 /* Disable auto-negotiation in the TXCW register */
537 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
539 /* Force link-up and also force full-duplex. */
541 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
544 /* Configure Flow Control after forcing link up. */
545 ret_val = e1000e_config_fc_after_link_up(hw);
547 e_dbg("Error configuring flow control\n");
550 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
552 * If we are forcing link and we are receiving /C/ ordered
553 * sets, re-enable auto-negotiation in the TXCW register
554 * and disable forced link in the Device Control register
555 * in an attempt to auto-negotiate with our link partner.
557 e_dbg("Rx'ing /C/, enable AutoNeg and stop forcing link.\n");
558 ew32(TXCW, mac->txcw);
559 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
561 mac->serdes_has_link = true;
568 * e1000e_check_for_serdes_link - Check for link (Serdes)
569 * @hw: pointer to the HW structure
571 * Checks for link up on the hardware. If link is not up and we have
572 * a signal, then we need to force link up.
574 s32 e1000e_check_for_serdes_link(struct e1000_hw *hw)
576 struct e1000_mac_info *mac = &hw->mac;
583 status = er32(STATUS);
587 * If we don't have link (auto-negotiation failed or link partner
588 * cannot auto-negotiate), and our link partner is not trying to
589 * auto-negotiate with us (we are receiving idles or data),
590 * we need to force link up. We also need to give auto-negotiation
593 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
594 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) {
595 if (mac->autoneg_failed == 0) {
596 mac->autoneg_failed = 1;
599 e_dbg("NOT Rx'ing /C/, disable AutoNeg and force link.\n");
601 /* Disable auto-negotiation in the TXCW register */
602 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
604 /* Force link-up and also force full-duplex. */
606 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
609 /* Configure Flow Control after forcing link up. */
610 ret_val = e1000e_config_fc_after_link_up(hw);
612 e_dbg("Error configuring flow control\n");
615 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
617 * If we are forcing link and we are receiving /C/ ordered
618 * sets, re-enable auto-negotiation in the TXCW register
619 * and disable forced link in the Device Control register
620 * in an attempt to auto-negotiate with our link partner.
622 e_dbg("Rx'ing /C/, enable AutoNeg and stop forcing link.\n");
623 ew32(TXCW, mac->txcw);
624 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
626 mac->serdes_has_link = true;
627 } else if (!(E1000_TXCW_ANE & er32(TXCW))) {
629 * If we force link for non-auto-negotiation switch, check
630 * link status based on MAC synchronization for internal
633 /* SYNCH bit and IV bit are sticky. */
636 if (rxcw & E1000_RXCW_SYNCH) {
637 if (!(rxcw & E1000_RXCW_IV)) {
638 mac->serdes_has_link = true;
639 e_dbg("SERDES: Link up - forced.\n");
642 mac->serdes_has_link = false;
643 e_dbg("SERDES: Link down - force failed.\n");
647 if (E1000_TXCW_ANE & er32(TXCW)) {
648 status = er32(STATUS);
649 if (status & E1000_STATUS_LU) {
650 /* SYNCH bit and IV bit are sticky, so reread rxcw. */
653 if (rxcw & E1000_RXCW_SYNCH) {
654 if (!(rxcw & E1000_RXCW_IV)) {
655 mac->serdes_has_link = true;
656 e_dbg("SERDES: Link up - autoneg "
657 "completed successfully.\n");
659 mac->serdes_has_link = false;
660 e_dbg("SERDES: Link down - invalid"
661 "codewords detected in autoneg.\n");
664 mac->serdes_has_link = false;
665 e_dbg("SERDES: Link down - no sync.\n");
668 mac->serdes_has_link = false;
669 e_dbg("SERDES: Link down - autoneg failed\n");
677 * e1000_set_default_fc_generic - Set flow control default values
678 * @hw: pointer to the HW structure
680 * Read the EEPROM for the default values for flow control and store the
683 static s32 e1000_set_default_fc_generic(struct e1000_hw *hw)
689 * Read and store word 0x0F of the EEPROM. This word contains bits
690 * that determine the hardware's default PAUSE (flow control) mode,
691 * a bit that determines whether the HW defaults to enabling or
692 * disabling auto-negotiation, and the direction of the
693 * SW defined pins. If there is no SW over-ride of the flow
694 * control setting, then the variable hw->fc will
695 * be initialized based on a value in the EEPROM.
697 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data);
700 e_dbg("NVM Read Error\n");
704 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0)
705 hw->fc.requested_mode = e1000_fc_none;
706 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) ==
708 hw->fc.requested_mode = e1000_fc_tx_pause;
710 hw->fc.requested_mode = e1000_fc_full;
716 * e1000e_setup_link - Setup flow control and link settings
717 * @hw: pointer to the HW structure
719 * Determines which flow control settings to use, then configures flow
720 * control. Calls the appropriate media-specific link configuration
721 * function. Assuming the adapter has a valid link partner, a valid link
722 * should be established. Assumes the hardware has previously been reset
723 * and the transmitter and receiver are not enabled.
725 s32 e1000e_setup_link(struct e1000_hw *hw)
727 struct e1000_mac_info *mac = &hw->mac;
731 * In the case of the phy reset being blocked, we already have a link.
732 * We do not need to set it up again.
734 if (e1000_check_reset_block(hw))
738 * If requested flow control is set to default, set flow control
739 * based on the EEPROM flow control settings.
741 if (hw->fc.requested_mode == e1000_fc_default) {
742 ret_val = e1000_set_default_fc_generic(hw);
748 * Save off the requested flow control mode for use later. Depending
749 * on the link partner's capabilities, we may or may not use this mode.
751 hw->fc.current_mode = hw->fc.requested_mode;
753 e_dbg("After fix-ups FlowControl is now = %x\n",
754 hw->fc.current_mode);
756 /* Call the necessary media_type subroutine to configure the link. */
757 ret_val = mac->ops.setup_physical_interface(hw);
762 * Initialize the flow control address, type, and PAUSE timer
763 * registers to their default values. This is done even if flow
764 * control is disabled, because it does not hurt anything to
765 * initialize these registers.
767 e_dbg("Initializing the Flow Control address, type and timer regs\n");
768 ew32(FCT, FLOW_CONTROL_TYPE);
769 ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH);
770 ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW);
772 ew32(FCTTV, hw->fc.pause_time);
774 return e1000e_set_fc_watermarks(hw);
778 * e1000_commit_fc_settings_generic - Configure flow control
779 * @hw: pointer to the HW structure
781 * Write the flow control settings to the Transmit Config Word Register (TXCW)
782 * base on the flow control settings in e1000_mac_info.
784 static s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)
786 struct e1000_mac_info *mac = &hw->mac;
790 * Check for a software override of the flow control settings, and
791 * setup the device accordingly. If auto-negotiation is enabled, then
792 * software will have to set the "PAUSE" bits to the correct value in
793 * the Transmit Config Word Register (TXCW) and re-start auto-
794 * negotiation. However, if auto-negotiation is disabled, then
795 * software will have to manually configure the two flow control enable
796 * bits in the CTRL register.
798 * The possible values of the "fc" parameter are:
799 * 0: Flow control is completely disabled
800 * 1: Rx flow control is enabled (we can receive pause frames,
801 * but not send pause frames).
802 * 2: Tx flow control is enabled (we can send pause frames but we
803 * do not support receiving pause frames).
804 * 3: Both Rx and Tx flow control (symmetric) are enabled.
806 switch (hw->fc.current_mode) {
808 /* Flow control completely disabled by a software over-ride. */
809 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
811 case e1000_fc_rx_pause:
813 * Rx Flow control is enabled and Tx Flow control is disabled
814 * by a software over-ride. Since there really isn't a way to
815 * advertise that we are capable of Rx Pause ONLY, we will
816 * advertise that we support both symmetric and asymmetric Rx
817 * PAUSE. Later, we will disable the adapter's ability to send
820 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
822 case e1000_fc_tx_pause:
824 * Tx Flow control is enabled, and Rx Flow control is disabled,
825 * by a software over-ride.
827 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
831 * Flow control (both Rx and Tx) is enabled by a software
834 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
837 e_dbg("Flow control param set incorrectly\n");
838 return -E1000_ERR_CONFIG;
849 * e1000_poll_fiber_serdes_link_generic - Poll for link up
850 * @hw: pointer to the HW structure
852 * Polls for link up by reading the status register, if link fails to come
853 * up with auto-negotiation, then the link is forced if a signal is detected.
855 static s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)
857 struct e1000_mac_info *mac = &hw->mac;
862 * If we have a signal (the cable is plugged in, or assumed true for
863 * serdes media) then poll for a "Link-Up" indication in the Device
864 * Status Register. Time-out if a link isn't seen in 500 milliseconds
865 * seconds (Auto-negotiation should complete in less than 500
866 * milliseconds even if the other end is doing it in SW).
868 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
869 usleep_range(10000, 20000);
870 status = er32(STATUS);
871 if (status & E1000_STATUS_LU)
874 if (i == FIBER_LINK_UP_LIMIT) {
875 e_dbg("Never got a valid link from auto-neg!!!\n");
876 mac->autoneg_failed = 1;
878 * AutoNeg failed to achieve a link, so we'll call
879 * mac->check_for_link. This routine will force the
880 * link up if we detect a signal. This will allow us to
881 * communicate with non-autonegotiating link partners.
883 ret_val = mac->ops.check_for_link(hw);
885 e_dbg("Error while checking for link\n");
888 mac->autoneg_failed = 0;
890 mac->autoneg_failed = 0;
891 e_dbg("Valid Link Found\n");
898 * e1000e_setup_fiber_serdes_link - Setup link for fiber/serdes
899 * @hw: pointer to the HW structure
901 * Configures collision distance and flow control for fiber and serdes
902 * links. Upon successful setup, poll for link.
904 s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw)
911 /* Take the link out of reset */
912 ctrl &= ~E1000_CTRL_LRST;
914 e1000e_config_collision_dist(hw);
916 ret_val = e1000_commit_fc_settings_generic(hw);
921 * Since auto-negotiation is enabled, take the link out of reset (the
922 * link will be in reset, because we previously reset the chip). This
923 * will restart auto-negotiation. If auto-negotiation is successful
924 * then the link-up status bit will be set and the flow control enable
925 * bits (RFCE and TFCE) will be set according to their negotiated value.
927 e_dbg("Auto-negotiation enabled\n");
931 usleep_range(1000, 2000);
934 * For these adapters, the SW definable pin 1 is set when the optics
935 * detect a signal. If we have a signal, then poll for a "Link-Up"
938 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
939 (er32(CTRL) & E1000_CTRL_SWDPIN1)) {
940 ret_val = e1000_poll_fiber_serdes_link_generic(hw);
942 e_dbg("No signal detected\n");
949 * e1000e_config_collision_dist - Configure collision distance
950 * @hw: pointer to the HW structure
952 * Configures the collision distance to the default value and is used
953 * during link setup. Currently no func pointer exists and all
954 * implementations are handled in the generic version of this function.
956 void e1000e_config_collision_dist(struct e1000_hw *hw)
962 tctl &= ~E1000_TCTL_COLD;
963 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
970 * e1000e_set_fc_watermarks - Set flow control high/low watermarks
971 * @hw: pointer to the HW structure
973 * Sets the flow control high/low threshold (watermark) registers. If
974 * flow control XON frame transmission is enabled, then set XON frame
975 * transmission as well.
977 s32 e1000e_set_fc_watermarks(struct e1000_hw *hw)
979 u32 fcrtl = 0, fcrth = 0;
982 * Set the flow control receive threshold registers. Normally,
983 * these registers will be set to a default threshold that may be
984 * adjusted later by the driver's runtime code. However, if the
985 * ability to transmit pause frames is not enabled, then these
986 * registers will be set to 0.
988 if (hw->fc.current_mode & e1000_fc_tx_pause) {
990 * We need to set up the Receive Threshold high and low water
991 * marks as well as (optionally) enabling the transmission of
994 fcrtl = hw->fc.low_water;
995 fcrtl |= E1000_FCRTL_XONE;
996 fcrth = hw->fc.high_water;
1005 * e1000e_force_mac_fc - Force the MAC's flow control settings
1006 * @hw: pointer to the HW structure
1008 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
1009 * device control register to reflect the adapter settings. TFCE and RFCE
1010 * need to be explicitly set by software when a copper PHY is used because
1011 * autonegotiation is managed by the PHY rather than the MAC. Software must
1012 * also configure these bits when link is forced on a fiber connection.
1014 s32 e1000e_force_mac_fc(struct e1000_hw *hw)
1021 * Because we didn't get link via the internal auto-negotiation
1022 * mechanism (we either forced link or we got link via PHY
1023 * auto-neg), we have to manually enable/disable transmit an
1024 * receive flow control.
1026 * The "Case" statement below enables/disable flow control
1027 * according to the "hw->fc.current_mode" parameter.
1029 * The possible values of the "fc" parameter are:
1030 * 0: Flow control is completely disabled
1031 * 1: Rx flow control is enabled (we can receive pause
1032 * frames but not send pause frames).
1033 * 2: Tx flow control is enabled (we can send pause frames
1034 * frames but we do not receive pause frames).
1035 * 3: Both Rx and Tx flow control (symmetric) is enabled.
1036 * other: No other values should be possible at this point.
1038 e_dbg("hw->fc.current_mode = %u\n", hw->fc.current_mode);
1040 switch (hw->fc.current_mode) {
1042 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
1044 case e1000_fc_rx_pause:
1045 ctrl &= (~E1000_CTRL_TFCE);
1046 ctrl |= E1000_CTRL_RFCE;
1048 case e1000_fc_tx_pause:
1049 ctrl &= (~E1000_CTRL_RFCE);
1050 ctrl |= E1000_CTRL_TFCE;
1053 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
1056 e_dbg("Flow control param set incorrectly\n");
1057 return -E1000_ERR_CONFIG;
1066 * e1000e_config_fc_after_link_up - Configures flow control after link
1067 * @hw: pointer to the HW structure
1069 * Checks the status of auto-negotiation after link up to ensure that the
1070 * speed and duplex were not forced. If the link needed to be forced, then
1071 * flow control needs to be forced also. If auto-negotiation is enabled
1072 * and did not fail, then we configure flow control based on our link
1075 s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw)
1077 struct e1000_mac_info *mac = &hw->mac;
1079 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
1083 * Check for the case where we have fiber media and auto-neg failed
1084 * so we had to force link. In this case, we need to force the
1085 * configuration of the MAC to match the "fc" parameter.
1087 if (mac->autoneg_failed) {
1088 if (hw->phy.media_type == e1000_media_type_fiber ||
1089 hw->phy.media_type == e1000_media_type_internal_serdes)
1090 ret_val = e1000e_force_mac_fc(hw);
1092 if (hw->phy.media_type == e1000_media_type_copper)
1093 ret_val = e1000e_force_mac_fc(hw);
1097 e_dbg("Error forcing flow control settings\n");
1102 * Check for the case where we have copper media and auto-neg is
1103 * enabled. In this case, we need to check and see if Auto-Neg
1104 * has completed, and if so, how the PHY and link partner has
1105 * flow control configured.
1107 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
1109 * Read the MII Status Register and check to see if AutoNeg
1110 * has completed. We read this twice because this reg has
1111 * some "sticky" (latched) bits.
1113 ret_val = e1e_rphy(hw, PHY_STATUS, &mii_status_reg);
1116 ret_val = e1e_rphy(hw, PHY_STATUS, &mii_status_reg);
1120 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
1121 e_dbg("Copper PHY and Auto Neg "
1122 "has not completed.\n");
1127 * The AutoNeg process has completed, so we now need to
1128 * read both the Auto Negotiation Advertisement
1129 * Register (Address 4) and the Auto_Negotiation Base
1130 * Page Ability Register (Address 5) to determine how
1131 * flow control was negotiated.
1133 ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg);
1137 e1e_rphy(hw, PHY_LP_ABILITY, &mii_nway_lp_ability_reg);
1142 * Two bits in the Auto Negotiation Advertisement Register
1143 * (Address 4) and two bits in the Auto Negotiation Base
1144 * Page Ability Register (Address 5) determine flow control
1145 * for both the PHY and the link partner. The following
1146 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1147 * 1999, describes these PAUSE resolution bits and how flow
1148 * control is determined based upon these settings.
1149 * NOTE: DC = Don't Care
1151 * LOCAL DEVICE | LINK PARTNER
1152 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1153 *-------|---------|-------|---------|--------------------
1154 * 0 | 0 | DC | DC | e1000_fc_none
1155 * 0 | 1 | 0 | DC | e1000_fc_none
1156 * 0 | 1 | 1 | 0 | e1000_fc_none
1157 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1158 * 1 | 0 | 0 | DC | e1000_fc_none
1159 * 1 | DC | 1 | DC | e1000_fc_full
1160 * 1 | 1 | 0 | 0 | e1000_fc_none
1161 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1163 * Are both PAUSE bits set to 1? If so, this implies
1164 * Symmetric Flow Control is enabled at both ends. The
1165 * ASM_DIR bits are irrelevant per the spec.
1167 * For Symmetric Flow Control:
1169 * LOCAL DEVICE | LINK PARTNER
1170 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1171 *-------|---------|-------|---------|--------------------
1172 * 1 | DC | 1 | DC | E1000_fc_full
1175 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1176 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1178 * Now we need to check if the user selected Rx ONLY
1179 * of pause frames. In this case, we had to advertise
1180 * FULL flow control because we could not advertise Rx
1181 * ONLY. Hence, we must now check to see if we need to
1182 * turn OFF the TRANSMISSION of PAUSE frames.
1184 if (hw->fc.requested_mode == e1000_fc_full) {
1185 hw->fc.current_mode = e1000_fc_full;
1186 e_dbg("Flow Control = FULL.\r\n");
1188 hw->fc.current_mode = e1000_fc_rx_pause;
1189 e_dbg("Flow Control = "
1190 "Rx PAUSE frames only.\r\n");
1194 * For receiving PAUSE frames ONLY.
1196 * LOCAL DEVICE | LINK PARTNER
1197 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1198 *-------|---------|-------|---------|--------------------
1199 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1201 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1202 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1203 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1204 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1205 hw->fc.current_mode = e1000_fc_tx_pause;
1206 e_dbg("Flow Control = Tx PAUSE frames only.\r\n");
1209 * For transmitting PAUSE frames ONLY.
1211 * LOCAL DEVICE | LINK PARTNER
1212 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1213 *-------|---------|-------|---------|--------------------
1214 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1216 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1217 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1218 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1219 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1220 hw->fc.current_mode = e1000_fc_rx_pause;
1221 e_dbg("Flow Control = Rx PAUSE frames only.\r\n");
1224 * Per the IEEE spec, at this point flow control
1225 * should be disabled.
1227 hw->fc.current_mode = e1000_fc_none;
1228 e_dbg("Flow Control = NONE.\r\n");
1232 * Now we need to do one last check... If we auto-
1233 * negotiated to HALF DUPLEX, flow control should not be
1234 * enabled per IEEE 802.3 spec.
1236 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1238 e_dbg("Error getting link speed and duplex\n");
1242 if (duplex == HALF_DUPLEX)
1243 hw->fc.current_mode = e1000_fc_none;
1246 * Now we call a subroutine to actually force the MAC
1247 * controller to use the correct flow control settings.
1249 ret_val = e1000e_force_mac_fc(hw);
1251 e_dbg("Error forcing flow control settings\n");
1260 * e1000e_get_speed_and_duplex_copper - Retrieve current speed/duplex
1261 * @hw: pointer to the HW structure
1262 * @speed: stores the current speed
1263 * @duplex: stores the current duplex
1265 * Read the status register for the current speed/duplex and store the current
1266 * speed and duplex for copper connections.
1268 s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, u16 *duplex)
1272 status = er32(STATUS);
1273 if (status & E1000_STATUS_SPEED_1000)
1274 *speed = SPEED_1000;
1275 else if (status & E1000_STATUS_SPEED_100)
1280 if (status & E1000_STATUS_FD)
1281 *duplex = FULL_DUPLEX;
1283 *duplex = HALF_DUPLEX;
1285 e_dbg("%u Mbps, %s Duplex\n",
1286 *speed == SPEED_1000 ? 1000 : *speed == SPEED_100 ? 100 : 10,
1287 *duplex == FULL_DUPLEX ? "Full" : "Half");
1293 * e1000e_get_speed_and_duplex_fiber_serdes - Retrieve current speed/duplex
1294 * @hw: pointer to the HW structure
1295 * @speed: stores the current speed
1296 * @duplex: stores the current duplex
1298 * Sets the speed and duplex to gigabit full duplex (the only possible option)
1299 * for fiber/serdes links.
1301 s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, u16 *speed, u16 *duplex)
1303 *speed = SPEED_1000;
1304 *duplex = FULL_DUPLEX;
1310 * e1000e_get_hw_semaphore - Acquire hardware semaphore
1311 * @hw: pointer to the HW structure
1313 * Acquire the HW semaphore to access the PHY or NVM
1315 s32 e1000e_get_hw_semaphore(struct e1000_hw *hw)
1318 s32 timeout = hw->nvm.word_size + 1;
1321 /* Get the SW semaphore */
1322 while (i < timeout) {
1324 if (!(swsm & E1000_SWSM_SMBI))
1332 e_dbg("Driver can't access device - SMBI bit is set.\n");
1333 return -E1000_ERR_NVM;
1336 /* Get the FW semaphore. */
1337 for (i = 0; i < timeout; i++) {
1339 ew32(SWSM, swsm | E1000_SWSM_SWESMBI);
1341 /* Semaphore acquired if bit latched */
1342 if (er32(SWSM) & E1000_SWSM_SWESMBI)
1349 /* Release semaphores */
1350 e1000e_put_hw_semaphore(hw);
1351 e_dbg("Driver can't access the NVM\n");
1352 return -E1000_ERR_NVM;
1359 * e1000e_put_hw_semaphore - Release hardware semaphore
1360 * @hw: pointer to the HW structure
1362 * Release hardware semaphore used to access the PHY or NVM
1364 void e1000e_put_hw_semaphore(struct e1000_hw *hw)
1369 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1374 * e1000e_get_auto_rd_done - Check for auto read completion
1375 * @hw: pointer to the HW structure
1377 * Check EEPROM for Auto Read done bit.
1379 s32 e1000e_get_auto_rd_done(struct e1000_hw *hw)
1383 while (i < AUTO_READ_DONE_TIMEOUT) {
1384 if (er32(EECD) & E1000_EECD_AUTO_RD)
1386 usleep_range(1000, 2000);
1390 if (i == AUTO_READ_DONE_TIMEOUT) {
1391 e_dbg("Auto read by HW from NVM has not completed.\n");
1392 return -E1000_ERR_RESET;
1399 * e1000e_valid_led_default - Verify a valid default LED config
1400 * @hw: pointer to the HW structure
1401 * @data: pointer to the NVM (EEPROM)
1403 * Read the EEPROM for the current default LED configuration. If the
1404 * LED configuration is not valid, set to a valid LED configuration.
1406 s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data)
1410 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1412 e_dbg("NVM Read Error\n");
1416 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
1417 *data = ID_LED_DEFAULT;
1423 * e1000e_id_led_init -
1424 * @hw: pointer to the HW structure
1427 s32 e1000e_id_led_init(struct e1000_hw *hw)
1429 struct e1000_mac_info *mac = &hw->mac;
1431 const u32 ledctl_mask = 0x000000FF;
1432 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
1433 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
1435 const u16 led_mask = 0x0F;
1437 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
1441 mac->ledctl_default = er32(LEDCTL);
1442 mac->ledctl_mode1 = mac->ledctl_default;
1443 mac->ledctl_mode2 = mac->ledctl_default;
1445 for (i = 0; i < 4; i++) {
1446 temp = (data >> (i << 2)) & led_mask;
1448 case ID_LED_ON1_DEF2:
1449 case ID_LED_ON1_ON2:
1450 case ID_LED_ON1_OFF2:
1451 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1452 mac->ledctl_mode1 |= ledctl_on << (i << 3);
1454 case ID_LED_OFF1_DEF2:
1455 case ID_LED_OFF1_ON2:
1456 case ID_LED_OFF1_OFF2:
1457 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1458 mac->ledctl_mode1 |= ledctl_off << (i << 3);
1465 case ID_LED_DEF1_ON2:
1466 case ID_LED_ON1_ON2:
1467 case ID_LED_OFF1_ON2:
1468 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1469 mac->ledctl_mode2 |= ledctl_on << (i << 3);
1471 case ID_LED_DEF1_OFF2:
1472 case ID_LED_ON1_OFF2:
1473 case ID_LED_OFF1_OFF2:
1474 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1475 mac->ledctl_mode2 |= ledctl_off << (i << 3);
1487 * e1000e_setup_led_generic - Configures SW controllable LED
1488 * @hw: pointer to the HW structure
1490 * This prepares the SW controllable LED for use and saves the current state
1491 * of the LED so it can be later restored.
1493 s32 e1000e_setup_led_generic(struct e1000_hw *hw)
1497 if (hw->mac.ops.setup_led != e1000e_setup_led_generic)
1498 return -E1000_ERR_CONFIG;
1500 if (hw->phy.media_type == e1000_media_type_fiber) {
1501 ledctl = er32(LEDCTL);
1502 hw->mac.ledctl_default = ledctl;
1504 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
1505 E1000_LEDCTL_LED0_BLINK |
1506 E1000_LEDCTL_LED0_MODE_MASK);
1507 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
1508 E1000_LEDCTL_LED0_MODE_SHIFT);
1509 ew32(LEDCTL, ledctl);
1510 } else if (hw->phy.media_type == e1000_media_type_copper) {
1511 ew32(LEDCTL, hw->mac.ledctl_mode1);
1518 * e1000e_cleanup_led_generic - Set LED config to default operation
1519 * @hw: pointer to the HW structure
1521 * Remove the current LED configuration and set the LED configuration
1522 * to the default value, saved from the EEPROM.
1524 s32 e1000e_cleanup_led_generic(struct e1000_hw *hw)
1526 ew32(LEDCTL, hw->mac.ledctl_default);
1531 * e1000e_blink_led_generic - Blink LED
1532 * @hw: pointer to the HW structure
1534 * Blink the LEDs which are set to be on.
1536 s32 e1000e_blink_led_generic(struct e1000_hw *hw)
1538 u32 ledctl_blink = 0;
1541 if (hw->phy.media_type == e1000_media_type_fiber) {
1542 /* always blink LED0 for PCI-E fiber */
1543 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
1544 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
1547 * set the blink bit for each LED that's "on" (0x0E)
1550 ledctl_blink = hw->mac.ledctl_mode2;
1551 for (i = 0; i < 4; i++)
1552 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1553 E1000_LEDCTL_MODE_LED_ON)
1554 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK <<
1558 ew32(LEDCTL, ledctl_blink);
1564 * e1000e_led_on_generic - Turn LED on
1565 * @hw: pointer to the HW structure
1569 s32 e1000e_led_on_generic(struct e1000_hw *hw)
1573 switch (hw->phy.media_type) {
1574 case e1000_media_type_fiber:
1576 ctrl &= ~E1000_CTRL_SWDPIN0;
1577 ctrl |= E1000_CTRL_SWDPIO0;
1580 case e1000_media_type_copper:
1581 ew32(LEDCTL, hw->mac.ledctl_mode2);
1591 * e1000e_led_off_generic - Turn LED off
1592 * @hw: pointer to the HW structure
1596 s32 e1000e_led_off_generic(struct e1000_hw *hw)
1600 switch (hw->phy.media_type) {
1601 case e1000_media_type_fiber:
1603 ctrl |= E1000_CTRL_SWDPIN0;
1604 ctrl |= E1000_CTRL_SWDPIO0;
1607 case e1000_media_type_copper:
1608 ew32(LEDCTL, hw->mac.ledctl_mode1);
1618 * e1000e_set_pcie_no_snoop - Set PCI-express capabilities
1619 * @hw: pointer to the HW structure
1620 * @no_snoop: bitmap of snoop events
1622 * Set the PCI-express register to snoop for events enabled in 'no_snoop'.
1624 void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop)
1630 gcr &= ~(PCIE_NO_SNOOP_ALL);
1637 * e1000e_disable_pcie_master - Disables PCI-express master access
1638 * @hw: pointer to the HW structure
1640 * Returns 0 if successful, else returns -10
1641 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
1642 * the master requests to be disabled.
1644 * Disables PCI-Express master access and verifies there are no pending
1647 s32 e1000e_disable_pcie_master(struct e1000_hw *hw)
1650 s32 timeout = MASTER_DISABLE_TIMEOUT;
1653 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
1657 if (!(er32(STATUS) &
1658 E1000_STATUS_GIO_MASTER_ENABLE))
1665 e_dbg("Master requests are pending.\n");
1666 return -E1000_ERR_MASTER_REQUESTS_PENDING;
1673 * e1000e_reset_adaptive - Reset Adaptive Interframe Spacing
1674 * @hw: pointer to the HW structure
1676 * Reset the Adaptive Interframe Spacing throttle to default values.
1678 void e1000e_reset_adaptive(struct e1000_hw *hw)
1680 struct e1000_mac_info *mac = &hw->mac;
1682 if (!mac->adaptive_ifs) {
1683 e_dbg("Not in Adaptive IFS mode!\n");
1687 mac->current_ifs_val = 0;
1688 mac->ifs_min_val = IFS_MIN;
1689 mac->ifs_max_val = IFS_MAX;
1690 mac->ifs_step_size = IFS_STEP;
1691 mac->ifs_ratio = IFS_RATIO;
1693 mac->in_ifs_mode = false;
1700 * e1000e_update_adaptive - Update Adaptive Interframe Spacing
1701 * @hw: pointer to the HW structure
1703 * Update the Adaptive Interframe Spacing Throttle value based on the
1704 * time between transmitted packets and time between collisions.
1706 void e1000e_update_adaptive(struct e1000_hw *hw)
1708 struct e1000_mac_info *mac = &hw->mac;
1710 if (!mac->adaptive_ifs) {
1711 e_dbg("Not in Adaptive IFS mode!\n");
1715 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) {
1716 if (mac->tx_packet_delta > MIN_NUM_XMITS) {
1717 mac->in_ifs_mode = true;
1718 if (mac->current_ifs_val < mac->ifs_max_val) {
1719 if (!mac->current_ifs_val)
1720 mac->current_ifs_val = mac->ifs_min_val;
1722 mac->current_ifs_val +=
1724 ew32(AIT, mac->current_ifs_val);
1728 if (mac->in_ifs_mode &&
1729 (mac->tx_packet_delta <= MIN_NUM_XMITS)) {
1730 mac->current_ifs_val = 0;
1731 mac->in_ifs_mode = false;
1740 * e1000_raise_eec_clk - Raise EEPROM clock
1741 * @hw: pointer to the HW structure
1742 * @eecd: pointer to the EEPROM
1744 * Enable/Raise the EEPROM clock bit.
1746 static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
1748 *eecd = *eecd | E1000_EECD_SK;
1751 udelay(hw->nvm.delay_usec);
1755 * e1000_lower_eec_clk - Lower EEPROM clock
1756 * @hw: pointer to the HW structure
1757 * @eecd: pointer to the EEPROM
1759 * Clear/Lower the EEPROM clock bit.
1761 static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
1763 *eecd = *eecd & ~E1000_EECD_SK;
1766 udelay(hw->nvm.delay_usec);
1770 * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM
1771 * @hw: pointer to the HW structure
1772 * @data: data to send to the EEPROM
1773 * @count: number of bits to shift out
1775 * We need to shift 'count' bits out to the EEPROM. So, the value in the
1776 * "data" parameter will be shifted out to the EEPROM one bit at a time.
1777 * In order to do this, "data" must be broken down into bits.
1779 static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
1781 struct e1000_nvm_info *nvm = &hw->nvm;
1782 u32 eecd = er32(EECD);
1785 mask = 0x01 << (count - 1);
1786 if (nvm->type == e1000_nvm_eeprom_spi)
1787 eecd |= E1000_EECD_DO;
1790 eecd &= ~E1000_EECD_DI;
1793 eecd |= E1000_EECD_DI;
1798 udelay(nvm->delay_usec);
1800 e1000_raise_eec_clk(hw, &eecd);
1801 e1000_lower_eec_clk(hw, &eecd);
1806 eecd &= ~E1000_EECD_DI;
1811 * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM
1812 * @hw: pointer to the HW structure
1813 * @count: number of bits to shift in
1815 * In order to read a register from the EEPROM, we need to shift 'count' bits
1816 * in from the EEPROM. Bits are "shifted in" by raising the clock input to
1817 * the EEPROM (setting the SK bit), and then reading the value of the data out
1818 * "DO" bit. During this "shifting in" process the data in "DI" bit should
1821 static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
1829 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
1832 for (i = 0; i < count; i++) {
1834 e1000_raise_eec_clk(hw, &eecd);
1838 eecd &= ~E1000_EECD_DI;
1839 if (eecd & E1000_EECD_DO)
1842 e1000_lower_eec_clk(hw, &eecd);
1849 * e1000e_poll_eerd_eewr_done - Poll for EEPROM read/write completion
1850 * @hw: pointer to the HW structure
1851 * @ee_reg: EEPROM flag for polling
1853 * Polls the EEPROM status bit for either read or write completion based
1854 * upon the value of 'ee_reg'.
1856 s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
1858 u32 attempts = 100000;
1861 for (i = 0; i < attempts; i++) {
1862 if (ee_reg == E1000_NVM_POLL_READ)
1867 if (reg & E1000_NVM_RW_REG_DONE)
1873 return -E1000_ERR_NVM;
1877 * e1000e_acquire_nvm - Generic request for access to EEPROM
1878 * @hw: pointer to the HW structure
1880 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
1881 * Return successful if access grant bit set, else clear the request for
1882 * EEPROM access and return -E1000_ERR_NVM (-1).
1884 s32 e1000e_acquire_nvm(struct e1000_hw *hw)
1886 u32 eecd = er32(EECD);
1887 s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
1889 ew32(EECD, eecd | E1000_EECD_REQ);
1893 if (eecd & E1000_EECD_GNT)
1901 eecd &= ~E1000_EECD_REQ;
1903 e_dbg("Could not acquire NVM grant\n");
1904 return -E1000_ERR_NVM;
1911 * e1000_standby_nvm - Return EEPROM to standby state
1912 * @hw: pointer to the HW structure
1914 * Return the EEPROM to a standby state.
1916 static void e1000_standby_nvm(struct e1000_hw *hw)
1918 struct e1000_nvm_info *nvm = &hw->nvm;
1919 u32 eecd = er32(EECD);
1921 if (nvm->type == e1000_nvm_eeprom_spi) {
1922 /* Toggle CS to flush commands */
1923 eecd |= E1000_EECD_CS;
1926 udelay(nvm->delay_usec);
1927 eecd &= ~E1000_EECD_CS;
1930 udelay(nvm->delay_usec);
1935 * e1000_stop_nvm - Terminate EEPROM command
1936 * @hw: pointer to the HW structure
1938 * Terminates the current command by inverting the EEPROM's chip select pin.
1940 static void e1000_stop_nvm(struct e1000_hw *hw)
1945 if (hw->nvm.type == e1000_nvm_eeprom_spi) {
1947 eecd |= E1000_EECD_CS;
1948 e1000_lower_eec_clk(hw, &eecd);
1953 * e1000e_release_nvm - Release exclusive access to EEPROM
1954 * @hw: pointer to the HW structure
1956 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
1958 void e1000e_release_nvm(struct e1000_hw *hw)
1965 eecd &= ~E1000_EECD_REQ;
1970 * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write
1971 * @hw: pointer to the HW structure
1973 * Setups the EEPROM for reading and writing.
1975 static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
1977 struct e1000_nvm_info *nvm = &hw->nvm;
1978 u32 eecd = er32(EECD);
1981 if (nvm->type == e1000_nvm_eeprom_spi) {
1982 u16 timeout = NVM_MAX_RETRY_SPI;
1984 /* Clear SK and CS */
1985 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
1991 * Read "Status Register" repeatedly until the LSB is cleared.
1992 * The EEPROM will signal that the command has been completed
1993 * by clearing bit 0 of the internal status register. If it's
1994 * not cleared within 'timeout', then error out.
1997 e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
1998 hw->nvm.opcode_bits);
1999 spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
2000 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
2004 e1000_standby_nvm(hw);
2009 e_dbg("SPI NVM Status error\n");
2010 return -E1000_ERR_NVM;
2018 * e1000e_read_nvm_eerd - Reads EEPROM using EERD register
2019 * @hw: pointer to the HW structure
2020 * @offset: offset of word in the EEPROM to read
2021 * @words: number of words to read
2022 * @data: word read from the EEPROM
2024 * Reads a 16 bit word from the EEPROM using the EERD register.
2026 s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
2028 struct e1000_nvm_info *nvm = &hw->nvm;
2033 * A check for invalid values: offset too large, too many words,
2034 * too many words for the offset, and not enough words.
2036 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
2038 e_dbg("nvm parameter(s) out of bounds\n");
2039 return -E1000_ERR_NVM;
2042 for (i = 0; i < words; i++) {
2043 eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
2044 E1000_NVM_RW_REG_START;
2047 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
2051 data[i] = (er32(EERD) >> E1000_NVM_RW_REG_DATA);
2058 * e1000e_write_nvm_spi - Write to EEPROM using SPI
2059 * @hw: pointer to the HW structure
2060 * @offset: offset within the EEPROM to be written to
2061 * @words: number of words to write
2062 * @data: 16 bit word(s) to be written to the EEPROM
2064 * Writes data to EEPROM at offset using SPI interface.
2066 * If e1000e_update_nvm_checksum is not called after this function , the
2067 * EEPROM will most likely contain an invalid checksum.
2069 s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
2071 struct e1000_nvm_info *nvm = &hw->nvm;
2076 * A check for invalid values: offset too large, too many words,
2077 * and not enough words.
2079 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
2081 e_dbg("nvm parameter(s) out of bounds\n");
2082 return -E1000_ERR_NVM;
2085 ret_val = nvm->ops.acquire(hw);
2089 while (widx < words) {
2090 u8 write_opcode = NVM_WRITE_OPCODE_SPI;
2092 ret_val = e1000_ready_nvm_eeprom(hw);
2094 nvm->ops.release(hw);
2098 e1000_standby_nvm(hw);
2100 /* Send the WRITE ENABLE command (8 bit opcode) */
2101 e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
2104 e1000_standby_nvm(hw);
2107 * Some SPI eeproms use the 8th address bit embedded in the
2110 if ((nvm->address_bits == 8) && (offset >= 128))
2111 write_opcode |= NVM_A8_OPCODE_SPI;
2113 /* Send the Write command (8-bit opcode + addr) */
2114 e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
2115 e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
2118 /* Loop to allow for up to whole page write of eeprom */
2119 while (widx < words) {
2120 u16 word_out = data[widx];
2121 word_out = (word_out >> 8) | (word_out << 8);
2122 e1000_shift_out_eec_bits(hw, word_out, 16);
2125 if ((((offset + widx) * 2) % nvm->page_size) == 0) {
2126 e1000_standby_nvm(hw);
2132 usleep_range(10000, 20000);
2133 nvm->ops.release(hw);
2138 * e1000_read_pba_string_generic - Read device part number
2139 * @hw: pointer to the HW structure
2140 * @pba_num: pointer to device part number
2141 * @pba_num_size: size of part number buffer
2143 * Reads the product board assembly (PBA) number from the EEPROM and stores
2144 * the value in pba_num.
2146 s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
2155 if (pba_num == NULL) {
2156 e_dbg("PBA string buffer was null\n");
2157 ret_val = E1000_ERR_INVALID_ARGUMENT;
2161 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
2163 e_dbg("NVM Read Error\n");
2167 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
2169 e_dbg("NVM Read Error\n");
2174 * if nvm_data is not ptr guard the PBA must be in legacy format which
2175 * means pba_ptr is actually our second data word for the PBA number
2176 * and we can decode it into an ascii string
2178 if (nvm_data != NVM_PBA_PTR_GUARD) {
2179 e_dbg("NVM PBA number is not stored as string\n");
2181 /* we will need 11 characters to store the PBA */
2182 if (pba_num_size < 11) {
2183 e_dbg("PBA string buffer too small\n");
2184 return E1000_ERR_NO_SPACE;
2187 /* extract hex string from data and pba_ptr */
2188 pba_num[0] = (nvm_data >> 12) & 0xF;
2189 pba_num[1] = (nvm_data >> 8) & 0xF;
2190 pba_num[2] = (nvm_data >> 4) & 0xF;
2191 pba_num[3] = nvm_data & 0xF;
2192 pba_num[4] = (pba_ptr >> 12) & 0xF;
2193 pba_num[5] = (pba_ptr >> 8) & 0xF;
2196 pba_num[8] = (pba_ptr >> 4) & 0xF;
2197 pba_num[9] = pba_ptr & 0xF;
2199 /* put a null character on the end of our string */
2202 /* switch all the data but the '-' to hex char */
2203 for (offset = 0; offset < 10; offset++) {
2204 if (pba_num[offset] < 0xA)
2205 pba_num[offset] += '0';
2206 else if (pba_num[offset] < 0x10)
2207 pba_num[offset] += 'A' - 0xA;
2213 ret_val = e1000_read_nvm(hw, pba_ptr, 1, &length);
2215 e_dbg("NVM Read Error\n");
2219 if (length == 0xFFFF || length == 0) {
2220 e_dbg("NVM PBA number section invalid length\n");
2221 ret_val = E1000_ERR_NVM_PBA_SECTION;
2224 /* check if pba_num buffer is big enough */
2225 if (pba_num_size < (((u32)length * 2) - 1)) {
2226 e_dbg("PBA string buffer too small\n");
2227 ret_val = E1000_ERR_NO_SPACE;
2231 /* trim pba length from start of string */
2235 for (offset = 0; offset < length; offset++) {
2236 ret_val = e1000_read_nvm(hw, pba_ptr + offset, 1, &nvm_data);
2238 e_dbg("NVM Read Error\n");
2241 pba_num[offset * 2] = (u8)(nvm_data >> 8);
2242 pba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF);
2244 pba_num[offset * 2] = '\0';
2251 * e1000_read_mac_addr_generic - Read device MAC address
2252 * @hw: pointer to the HW structure
2254 * Reads the device MAC address from the EEPROM and stores the value.
2255 * Since devices with two ports use the same EEPROM, we increment the
2256 * last bit in the MAC address for the second port.
2258 s32 e1000_read_mac_addr_generic(struct e1000_hw *hw)
2264 rar_high = er32(RAH(0));
2265 rar_low = er32(RAL(0));
2267 for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
2268 hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));
2270 for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
2271 hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));
2273 for (i = 0; i < ETH_ALEN; i++)
2274 hw->mac.addr[i] = hw->mac.perm_addr[i];
2280 * e1000e_validate_nvm_checksum_generic - Validate EEPROM checksum
2281 * @hw: pointer to the HW structure
2283 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2284 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
2286 s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw)
2292 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
2293 ret_val = e1000_read_nvm(hw, i, 1, &nvm_data);
2295 e_dbg("NVM Read Error\n");
2298 checksum += nvm_data;
2301 if (checksum != (u16) NVM_SUM) {
2302 e_dbg("NVM Checksum Invalid\n");
2303 return -E1000_ERR_NVM;
2310 * e1000e_update_nvm_checksum_generic - Update EEPROM checksum
2311 * @hw: pointer to the HW structure
2313 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
2314 * up to the checksum. Then calculates the EEPROM checksum and writes the
2315 * value to the EEPROM.
2317 s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw)
2323 for (i = 0; i < NVM_CHECKSUM_REG; i++) {
2324 ret_val = e1000_read_nvm(hw, i, 1, &nvm_data);
2326 e_dbg("NVM Read Error while updating checksum.\n");
2329 checksum += nvm_data;
2331 checksum = (u16) NVM_SUM - checksum;
2332 ret_val = e1000_write_nvm(hw, NVM_CHECKSUM_REG, 1, &checksum);
2334 e_dbg("NVM Write Error while updating checksum.\n");
2340 * e1000e_reload_nvm - Reloads EEPROM
2341 * @hw: pointer to the HW structure
2343 * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
2344 * extended control register.
2346 void e1000e_reload_nvm(struct e1000_hw *hw)
2351 ctrl_ext = er32(CTRL_EXT);
2352 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
2353 ew32(CTRL_EXT, ctrl_ext);
2358 * e1000_calculate_checksum - Calculate checksum for buffer
2359 * @buffer: pointer to EEPROM
2360 * @length: size of EEPROM to calculate a checksum for
2362 * Calculates the checksum for some buffer on a specified length. The
2363 * checksum calculated is returned.
2365 static u8 e1000_calculate_checksum(u8 *buffer, u32 length)
2373 for (i = 0; i < length; i++)
2376 return (u8) (0 - sum);
2380 * e1000_mng_enable_host_if - Checks host interface is enabled
2381 * @hw: pointer to the HW structure
2383 * Returns E1000_success upon success, else E1000_ERR_HOST_INTERFACE_COMMAND
2385 * This function checks whether the HOST IF is enabled for command operation
2386 * and also checks whether the previous command is completed. It busy waits
2387 * in case of previous command is not completed.
2389 static s32 e1000_mng_enable_host_if(struct e1000_hw *hw)
2394 if (!(hw->mac.arc_subsystem_valid)) {
2395 e_dbg("ARC subsystem not valid.\n");
2396 return -E1000_ERR_HOST_INTERFACE_COMMAND;
2399 /* Check that the host interface is enabled. */
2401 if ((hicr & E1000_HICR_EN) == 0) {
2402 e_dbg("E1000_HOST_EN bit disabled.\n");
2403 return -E1000_ERR_HOST_INTERFACE_COMMAND;
2405 /* check the previous command is completed */
2406 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
2408 if (!(hicr & E1000_HICR_C))
2413 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
2414 e_dbg("Previous command timeout failed .\n");
2415 return -E1000_ERR_HOST_INTERFACE_COMMAND;
2422 * e1000e_check_mng_mode_generic - check management mode
2423 * @hw: pointer to the HW structure
2425 * Reads the firmware semaphore register and returns true (>0) if
2426 * manageability is enabled, else false (0).
2428 bool e1000e_check_mng_mode_generic(struct e1000_hw *hw)
2430 u32 fwsm = er32(FWSM);
2432 return (fwsm & E1000_FWSM_MODE_MASK) ==
2433 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
2437 * e1000e_enable_tx_pkt_filtering - Enable packet filtering on Tx
2438 * @hw: pointer to the HW structure
2440 * Enables packet filtering on transmit packets if manageability is enabled
2441 * and host interface is enabled.
2443 bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw)
2445 struct e1000_host_mng_dhcp_cookie *hdr = &hw->mng_cookie;
2446 u32 *buffer = (u32 *)&hw->mng_cookie;
2448 s32 ret_val, hdr_csum, csum;
2451 hw->mac.tx_pkt_filtering = true;
2453 /* No manageability, no filtering */
2454 if (!e1000e_check_mng_mode(hw)) {
2455 hw->mac.tx_pkt_filtering = false;
2460 * If we can't read from the host interface for whatever
2461 * reason, disable filtering.
2463 ret_val = e1000_mng_enable_host_if(hw);
2465 hw->mac.tx_pkt_filtering = false;
2469 /* Read in the header. Length and offset are in dwords. */
2470 len = E1000_MNG_DHCP_COOKIE_LENGTH >> 2;
2471 offset = E1000_MNG_DHCP_COOKIE_OFFSET >> 2;
2472 for (i = 0; i < len; i++)
2473 *(buffer + i) = E1000_READ_REG_ARRAY(hw, E1000_HOST_IF, offset + i);
2474 hdr_csum = hdr->checksum;
2476 csum = e1000_calculate_checksum((u8 *)hdr,
2477 E1000_MNG_DHCP_COOKIE_LENGTH);
2479 * If either the checksums or signature don't match, then
2480 * the cookie area isn't considered valid, in which case we
2481 * take the safe route of assuming Tx filtering is enabled.
2483 if ((hdr_csum != csum) || (hdr->signature != E1000_IAMT_SIGNATURE)) {
2484 hw->mac.tx_pkt_filtering = true;
2488 /* Cookie area is valid, make the final check for filtering. */
2489 if (!(hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING)) {
2490 hw->mac.tx_pkt_filtering = false;
2495 return hw->mac.tx_pkt_filtering;
2499 * e1000_mng_write_cmd_header - Writes manageability command header
2500 * @hw: pointer to the HW structure
2501 * @hdr: pointer to the host interface command header
2503 * Writes the command header after does the checksum calculation.
2505 static s32 e1000_mng_write_cmd_header(struct e1000_hw *hw,
2506 struct e1000_host_mng_command_header *hdr)
2508 u16 i, length = sizeof(struct e1000_host_mng_command_header);
2510 /* Write the whole command header structure with new checksum. */
2512 hdr->checksum = e1000_calculate_checksum((u8 *)hdr, length);
2515 /* Write the relevant command block into the ram area. */
2516 for (i = 0; i < length; i++) {
2517 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, i,
2518 *((u32 *) hdr + i));
2526 * e1000_mng_host_if_write - Write to the manageability host interface
2527 * @hw: pointer to the HW structure
2528 * @buffer: pointer to the host interface buffer
2529 * @length: size of the buffer
2530 * @offset: location in the buffer to write to
2531 * @sum: sum of the data (not checksum)
2533 * This function writes the buffer content at the offset given on the host if.
2534 * It also does alignment considerations to do the writes in most efficient
2535 * way. Also fills up the sum of the buffer in *buffer parameter.
2537 static s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer,
2538 u16 length, u16 offset, u8 *sum)
2541 u8 *bufptr = buffer;
2543 u16 remaining, i, j, prev_bytes;
2545 /* sum = only sum of the data and it is not checksum */
2547 if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH)
2548 return -E1000_ERR_PARAM;
2551 prev_bytes = offset & 0x3;
2555 data = E1000_READ_REG_ARRAY(hw, E1000_HOST_IF, offset);
2556 for (j = prev_bytes; j < sizeof(u32); j++) {
2557 *(tmp + j) = *bufptr++;
2560 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset, data);
2561 length -= j - prev_bytes;
2565 remaining = length & 0x3;
2566 length -= remaining;
2568 /* Calculate length in DWORDs */
2572 * The device driver writes the relevant command block into the
2575 for (i = 0; i < length; i++) {
2576 for (j = 0; j < sizeof(u32); j++) {
2577 *(tmp + j) = *bufptr++;
2581 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset + i, data);
2584 for (j = 0; j < sizeof(u32); j++) {
2586 *(tmp + j) = *bufptr++;
2592 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset + i, data);
2599 * e1000e_mng_write_dhcp_info - Writes DHCP info to host interface
2600 * @hw: pointer to the HW structure
2601 * @buffer: pointer to the host interface
2602 * @length: size of the buffer
2604 * Writes the DHCP information to the host interface.
2606 s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length)
2608 struct e1000_host_mng_command_header hdr;
2612 hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
2613 hdr.command_length = length;
2618 /* Enable the host interface */
2619 ret_val = e1000_mng_enable_host_if(hw);
2623 /* Populate the host interface with the contents of "buffer". */
2624 ret_val = e1000_mng_host_if_write(hw, buffer, length,
2625 sizeof(hdr), &(hdr.checksum));
2629 /* Write the manageability command header */
2630 ret_val = e1000_mng_write_cmd_header(hw, &hdr);
2634 /* Tell the ARC a new command is pending. */
2636 ew32(HICR, hicr | E1000_HICR_C);
2642 * e1000e_enable_mng_pass_thru - Check if management passthrough is needed
2643 * @hw: pointer to the HW structure
2645 * Verifies the hardware needs to leave interface enabled so that frames can
2646 * be directed to and from the management interface.
2648 bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw)
2652 bool ret_val = false;
2656 if (!(manc & E1000_MANC_RCV_TCO_EN))
2659 if (hw->mac.has_fwsm) {
2661 factps = er32(FACTPS);
2663 if (!(factps & E1000_FACTPS_MNGCG) &&
2664 ((fwsm & E1000_FWSM_MODE_MASK) ==
2665 (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT))) {
2669 } else if ((hw->mac.type == e1000_82574) ||
2670 (hw->mac.type == e1000_82583)) {
2673 factps = er32(FACTPS);
2674 e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data);
2676 if (!(factps & E1000_FACTPS_MNGCG) &&
2677 ((data & E1000_NVM_INIT_CTRL2_MNGM) ==
2678 (e1000_mng_mode_pt << 13))) {
2682 } else if ((manc & E1000_MANC_SMBUS_EN) &&
2683 !(manc & E1000_MANC_ASF_EN)) {