1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
4 /* 82562G 10/100 Network Connection
5 * 82562G-2 10/100 Network Connection
6 * 82562GT 10/100 Network Connection
7 * 82562GT-2 10/100 Network Connection
8 * 82562V 10/100 Network Connection
9 * 82562V-2 10/100 Network Connection
10 * 82566DC-2 Gigabit Network Connection
11 * 82566DC Gigabit Network Connection
12 * 82566DM-2 Gigabit Network Connection
13 * 82566DM Gigabit Network Connection
14 * 82566MC Gigabit Network Connection
15 * 82566MM Gigabit Network Connection
16 * 82567LM Gigabit Network Connection
17 * 82567LF Gigabit Network Connection
18 * 82567V Gigabit Network Connection
19 * 82567LM-2 Gigabit Network Connection
20 * 82567LF-2 Gigabit Network Connection
21 * 82567V-2 Gigabit Network Connection
22 * 82567LF-3 Gigabit Network Connection
23 * 82567LM-3 Gigabit Network Connection
24 * 82567LM-4 Gigabit Network Connection
25 * 82577LM Gigabit Network Connection
26 * 82577LC Gigabit Network Connection
27 * 82578DM Gigabit Network Connection
28 * 82578DC Gigabit Network Connection
29 * 82579LM Gigabit Network Connection
30 * 82579V Gigabit Network Connection
31 * Ethernet Connection I217-LM
32 * Ethernet Connection I217-V
33 * Ethernet Connection I218-V
34 * Ethernet Connection I218-LM
35 * Ethernet Connection (2) I218-LM
36 * Ethernet Connection (2) I218-V
37 * Ethernet Connection (3) I218-LM
38 * Ethernet Connection (3) I218-V
43 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
44 /* Offset 04h HSFSTS */
45 union ich8_hws_flash_status {
47 u16 flcdone:1; /* bit 0 Flash Cycle Done */
48 u16 flcerr:1; /* bit 1 Flash Cycle Error */
49 u16 dael:1; /* bit 2 Direct Access error Log */
50 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
51 u16 flcinprog:1; /* bit 5 flash cycle in Progress */
52 u16 reserved1:2; /* bit 13:6 Reserved */
53 u16 reserved2:6; /* bit 13:6 Reserved */
54 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */
55 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
60 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
61 /* Offset 06h FLCTL */
62 union ich8_hws_flash_ctrl {
64 u16 flcgo:1; /* 0 Flash Cycle Go */
65 u16 flcycle:2; /* 2:1 Flash Cycle */
66 u16 reserved:5; /* 7:3 Reserved */
67 u16 fldbcount:2; /* 9:8 Flash Data Byte Count */
68 u16 flockdn:6; /* 15:10 Reserved */
73 /* ICH Flash Region Access Permissions */
74 union ich8_hws_flash_regacc {
76 u32 grra:8; /* 0:7 GbE region Read Access */
77 u32 grwa:8; /* 8:15 GbE region Write Access */
78 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */
79 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */
84 /* ICH Flash Protected Region */
85 union ich8_flash_protected_range {
87 u32 base:13; /* 0:12 Protected Range Base */
88 u32 reserved1:2; /* 13:14 Reserved */
89 u32 rpe:1; /* 15 Read Protection Enable */
90 u32 limit:13; /* 16:28 Protected Range Limit */
91 u32 reserved2:2; /* 29:30 Reserved */
92 u32 wpe:1; /* 31 Write Protection Enable */
97 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
98 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
99 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
100 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
101 u32 offset, u8 byte);
102 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
104 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
106 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
108 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
110 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw,
111 u32 offset, u32 *data);
112 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw,
113 u32 offset, u32 data);
114 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
115 u32 offset, u32 dword);
116 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
117 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
118 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
119 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
120 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
121 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
122 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
123 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
124 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
125 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
126 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
127 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
128 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
129 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
130 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
131 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
132 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
133 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
134 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw);
135 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
136 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
137 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force);
138 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
139 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state);
141 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
143 return readw(hw->flash_address + reg);
146 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
148 return readl(hw->flash_address + reg);
151 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
153 writew(val, hw->flash_address + reg);
156 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
158 writel(val, hw->flash_address + reg);
161 #define er16flash(reg) __er16flash(hw, (reg))
162 #define er32flash(reg) __er32flash(hw, (reg))
163 #define ew16flash(reg, val) __ew16flash(hw, (reg), (val))
164 #define ew32flash(reg, val) __ew32flash(hw, (reg), (val))
167 * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
168 * @hw: pointer to the HW structure
170 * Test access to the PHY registers by reading the PHY ID registers. If
171 * the PHY ID is already known (e.g. resume path) compare it with known ID,
172 * otherwise assume the read PHY ID is correct if it is valid.
174 * Assumes the sw/fw/hw semaphore is already acquired.
176 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
184 for (retry_count = 0; retry_count < 2; retry_count++) {
185 ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg);
186 if (ret_val || (phy_reg == 0xFFFF))
188 phy_id = (u32)(phy_reg << 16);
190 ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg);
191 if (ret_val || (phy_reg == 0xFFFF)) {
195 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
200 if (hw->phy.id == phy_id)
204 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
208 /* In case the PHY needs to be in mdio slow mode,
209 * set slow mode and try to get the PHY id again.
211 if (hw->mac.type < e1000_pch_lpt) {
212 hw->phy.ops.release(hw);
213 ret_val = e1000_set_mdio_slow_mode_hv(hw);
215 ret_val = e1000e_get_phy_id(hw);
216 hw->phy.ops.acquire(hw);
222 if (hw->mac.type >= e1000_pch_lpt) {
223 /* Only unforce SMBus if ME is not active */
224 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
225 /* Unforce SMBus mode in PHY */
226 e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg);
227 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
228 e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg);
230 /* Unforce SMBus mode in MAC */
231 mac_reg = er32(CTRL_EXT);
232 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
233 ew32(CTRL_EXT, mac_reg);
241 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
242 * @hw: pointer to the HW structure
244 * Toggling the LANPHYPC pin value fully power-cycles the PHY and is
245 * used to reset the PHY to a quiescent state when necessary.
247 static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
251 /* Set Phy Config Counter to 50msec */
252 mac_reg = er32(FEXTNVM3);
253 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
254 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
255 ew32(FEXTNVM3, mac_reg);
257 /* Toggle LANPHYPC Value bit */
258 mac_reg = er32(CTRL);
259 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
260 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
263 usleep_range(10, 20);
264 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
268 if (hw->mac.type < e1000_pch_lpt) {
274 usleep_range(5000, 6000);
275 } while (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LPCD) && count--);
282 * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
283 * @hw: pointer to the HW structure
285 * Workarounds/flow necessary for PHY initialization during driver load
288 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
290 struct e1000_adapter *adapter = hw->adapter;
291 u32 mac_reg, fwsm = er32(FWSM);
294 /* Gate automatic PHY configuration by hardware on managed and
295 * non-managed 82579 and newer adapters.
297 e1000_gate_hw_phy_config_ich8lan(hw, true);
299 /* It is not possible to be certain of the current state of ULP
300 * so forcibly disable it.
302 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
303 ret_val = e1000_disable_ulp_lpt_lp(hw, true);
305 e_warn("Failed to disable ULP\n");
307 ret_val = hw->phy.ops.acquire(hw);
309 e_dbg("Failed to initialize PHY flow\n");
313 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is
314 * inaccessible and resetting the PHY is not blocked, toggle the
315 * LANPHYPC Value bit to force the interconnect to PCIe mode.
317 switch (hw->mac.type) {
325 if (e1000_phy_is_accessible_pchlan(hw))
328 /* Before toggling LANPHYPC, see if PHY is accessible by
329 * forcing MAC to SMBus mode first.
331 mac_reg = er32(CTRL_EXT);
332 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
333 ew32(CTRL_EXT, mac_reg);
335 /* Wait 50 milliseconds for MAC to finish any retries
336 * that it might be trying to perform from previous
337 * attempts to acknowledge any phy read requests.
343 if (e1000_phy_is_accessible_pchlan(hw))
348 if ((hw->mac.type == e1000_pchlan) &&
349 (fwsm & E1000_ICH_FWSM_FW_VALID))
352 if (hw->phy.ops.check_reset_block(hw)) {
353 e_dbg("Required LANPHYPC toggle blocked by ME\n");
354 ret_val = -E1000_ERR_PHY;
358 /* Toggle LANPHYPC Value bit */
359 e1000_toggle_lanphypc_pch_lpt(hw);
360 if (hw->mac.type >= e1000_pch_lpt) {
361 if (e1000_phy_is_accessible_pchlan(hw))
364 /* Toggling LANPHYPC brings the PHY out of SMBus mode
365 * so ensure that the MAC is also out of SMBus mode
367 mac_reg = er32(CTRL_EXT);
368 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
369 ew32(CTRL_EXT, mac_reg);
371 if (e1000_phy_is_accessible_pchlan(hw))
374 ret_val = -E1000_ERR_PHY;
381 hw->phy.ops.release(hw);
384 /* Check to see if able to reset PHY. Print error if not */
385 if (hw->phy.ops.check_reset_block(hw)) {
386 e_err("Reset blocked by ME\n");
390 /* Reset the PHY before any access to it. Doing so, ensures
391 * that the PHY is in a known good state before we read/write
392 * PHY registers. The generic reset is sufficient here,
393 * because we haven't determined the PHY type yet.
395 ret_val = e1000e_phy_hw_reset_generic(hw);
399 /* On a successful reset, possibly need to wait for the PHY
400 * to quiesce to an accessible state before returning control
401 * to the calling function. If the PHY does not quiesce, then
402 * return E1000E_BLK_PHY_RESET, as this is the condition that
405 ret_val = hw->phy.ops.check_reset_block(hw);
407 e_err("ME blocked access to PHY after reset\n");
411 /* Ungate automatic PHY configuration on non-managed 82579 */
412 if ((hw->mac.type == e1000_pch2lan) &&
413 !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
414 usleep_range(10000, 11000);
415 e1000_gate_hw_phy_config_ich8lan(hw, false);
422 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
423 * @hw: pointer to the HW structure
425 * Initialize family-specific PHY parameters and function pointers.
427 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
429 struct e1000_phy_info *phy = &hw->phy;
433 phy->reset_delay_us = 100;
435 phy->ops.set_page = e1000_set_page_igp;
436 phy->ops.read_reg = e1000_read_phy_reg_hv;
437 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
438 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;
439 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
440 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
441 phy->ops.write_reg = e1000_write_phy_reg_hv;
442 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
443 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
444 phy->ops.power_up = e1000_power_up_phy_copper;
445 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
446 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
448 phy->id = e1000_phy_unknown;
450 ret_val = e1000_init_phy_workarounds_pchlan(hw);
454 if (phy->id == e1000_phy_unknown)
455 switch (hw->mac.type) {
457 ret_val = e1000e_get_phy_id(hw);
460 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
471 /* In case the PHY needs to be in mdio slow mode,
472 * set slow mode and try to get the PHY id again.
474 ret_val = e1000_set_mdio_slow_mode_hv(hw);
477 ret_val = e1000e_get_phy_id(hw);
482 phy->type = e1000e_get_phy_type_from_id(phy->id);
485 case e1000_phy_82577:
486 case e1000_phy_82579:
488 phy->ops.check_polarity = e1000_check_polarity_82577;
489 phy->ops.force_speed_duplex =
490 e1000_phy_force_speed_duplex_82577;
491 phy->ops.get_cable_length = e1000_get_cable_length_82577;
492 phy->ops.get_info = e1000_get_phy_info_82577;
493 phy->ops.commit = e1000e_phy_sw_reset;
495 case e1000_phy_82578:
496 phy->ops.check_polarity = e1000_check_polarity_m88;
497 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
498 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
499 phy->ops.get_info = e1000e_get_phy_info_m88;
502 ret_val = -E1000_ERR_PHY;
510 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
511 * @hw: pointer to the HW structure
513 * Initialize family-specific PHY parameters and function pointers.
515 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
517 struct e1000_phy_info *phy = &hw->phy;
522 phy->reset_delay_us = 100;
524 phy->ops.power_up = e1000_power_up_phy_copper;
525 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
527 /* We may need to do this twice - once for IGP and if that fails,
528 * we'll set BM func pointers and try again
530 ret_val = e1000e_determine_phy_address(hw);
532 phy->ops.write_reg = e1000e_write_phy_reg_bm;
533 phy->ops.read_reg = e1000e_read_phy_reg_bm;
534 ret_val = e1000e_determine_phy_address(hw);
536 e_dbg("Cannot determine PHY addr. Erroring out\n");
542 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
544 usleep_range(1000, 1100);
545 ret_val = e1000e_get_phy_id(hw);
552 case IGP03E1000_E_PHY_ID:
553 phy->type = e1000_phy_igp_3;
554 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
555 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
556 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
557 phy->ops.get_info = e1000e_get_phy_info_igp;
558 phy->ops.check_polarity = e1000_check_polarity_igp;
559 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
562 case IFE_PLUS_E_PHY_ID:
564 phy->type = e1000_phy_ife;
565 phy->autoneg_mask = E1000_ALL_NOT_GIG;
566 phy->ops.get_info = e1000_get_phy_info_ife;
567 phy->ops.check_polarity = e1000_check_polarity_ife;
568 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
570 case BME1000_E_PHY_ID:
571 phy->type = e1000_phy_bm;
572 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
573 phy->ops.read_reg = e1000e_read_phy_reg_bm;
574 phy->ops.write_reg = e1000e_write_phy_reg_bm;
575 phy->ops.commit = e1000e_phy_sw_reset;
576 phy->ops.get_info = e1000e_get_phy_info_m88;
577 phy->ops.check_polarity = e1000_check_polarity_m88;
578 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
581 return -E1000_ERR_PHY;
588 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
589 * @hw: pointer to the HW structure
591 * Initialize family-specific NVM parameters and function
594 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
596 struct e1000_nvm_info *nvm = &hw->nvm;
597 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
598 u32 gfpreg, sector_base_addr, sector_end_addr;
602 nvm->type = e1000_nvm_flash_sw;
604 if (hw->mac.type >= e1000_pch_spt) {
605 /* in SPT, gfpreg doesn't exist. NVM size is taken from the
606 * STRAP register. This is because in SPT the GbE Flash region
607 * is no longer accessed through the flash registers. Instead,
608 * the mechanism has changed, and the Flash region access
609 * registers are now implemented in GbE memory space.
611 nvm->flash_base_addr = 0;
612 nvm_size = (((er32(STRAP) >> 1) & 0x1F) + 1)
613 * NVM_SIZE_MULTIPLIER;
614 nvm->flash_bank_size = nvm_size / 2;
615 /* Adjust to word count */
616 nvm->flash_bank_size /= sizeof(u16);
617 /* Set the base address for flash register access */
618 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR;
620 /* Can't read flash registers if register set isn't mapped. */
621 if (!hw->flash_address) {
622 e_dbg("ERROR: Flash registers not mapped\n");
623 return -E1000_ERR_CONFIG;
626 gfpreg = er32flash(ICH_FLASH_GFPREG);
628 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
629 * Add 1 to sector_end_addr since this sector is included in
632 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
633 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
635 /* flash_base_addr is byte-aligned */
636 nvm->flash_base_addr = sector_base_addr
637 << FLASH_SECTOR_ADDR_SHIFT;
639 /* find total size of the NVM, then cut in half since the total
640 * size represents two separate NVM banks.
642 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
643 << FLASH_SECTOR_ADDR_SHIFT);
644 nvm->flash_bank_size /= 2;
645 /* Adjust to word count */
646 nvm->flash_bank_size /= sizeof(u16);
649 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
651 /* Clear shadow ram */
652 for (i = 0; i < nvm->word_size; i++) {
653 dev_spec->shadow_ram[i].modified = false;
654 dev_spec->shadow_ram[i].value = 0xFFFF;
661 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
662 * @hw: pointer to the HW structure
664 * Initialize family-specific MAC parameters and function
667 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
669 struct e1000_mac_info *mac = &hw->mac;
671 /* Set media type function pointer */
672 hw->phy.media_type = e1000_media_type_copper;
674 /* Set mta register count */
675 mac->mta_reg_count = 32;
676 /* Set rar entry count */
677 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
678 if (mac->type == e1000_ich8lan)
679 mac->rar_entry_count--;
681 mac->has_fwsm = true;
682 /* ARC subsystem not supported */
683 mac->arc_subsystem_valid = false;
684 /* Adaptive IFS supported */
685 mac->adaptive_ifs = true;
687 /* LED and other operations */
692 /* check management mode */
693 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
695 mac->ops.id_led_init = e1000e_id_led_init_generic;
697 mac->ops.blink_led = e1000e_blink_led_generic;
699 mac->ops.setup_led = e1000e_setup_led_generic;
701 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
702 /* turn on/off LED */
703 mac->ops.led_on = e1000_led_on_ich8lan;
704 mac->ops.led_off = e1000_led_off_ich8lan;
707 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
708 mac->ops.rar_set = e1000_rar_set_pch2lan;
718 /* check management mode */
719 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
721 mac->ops.id_led_init = e1000_id_led_init_pchlan;
723 mac->ops.setup_led = e1000_setup_led_pchlan;
725 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
726 /* turn on/off LED */
727 mac->ops.led_on = e1000_led_on_pchlan;
728 mac->ops.led_off = e1000_led_off_pchlan;
734 if (mac->type >= e1000_pch_lpt) {
735 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
736 mac->ops.rar_set = e1000_rar_set_pch_lpt;
737 mac->ops.setup_physical_interface =
738 e1000_setup_copper_link_pch_lpt;
739 mac->ops.rar_get_count = e1000_rar_get_count_pch_lpt;
742 /* Enable PCS Lock-loss workaround for ICH8 */
743 if (mac->type == e1000_ich8lan)
744 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
750 * __e1000_access_emi_reg_locked - Read/write EMI register
751 * @hw: pointer to the HW structure
752 * @address: EMI address to program
753 * @data: pointer to value to read/write from/to the EMI address
754 * @read: boolean flag to indicate read or write
756 * This helper function assumes the SW/FW/HW Semaphore is already acquired.
758 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
759 u16 *data, bool read)
763 ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address);
768 ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data);
770 ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data);
776 * e1000_read_emi_reg_locked - Read Extended Management Interface register
777 * @hw: pointer to the HW structure
778 * @addr: EMI address to program
779 * @data: value to be read from the EMI address
781 * Assumes the SW/FW/HW Semaphore is already acquired.
783 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
785 return __e1000_access_emi_reg_locked(hw, addr, data, true);
789 * e1000_write_emi_reg_locked - Write Extended Management Interface register
790 * @hw: pointer to the HW structure
791 * @addr: EMI address to program
792 * @data: value to be written to the EMI address
794 * Assumes the SW/FW/HW Semaphore is already acquired.
796 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
798 return __e1000_access_emi_reg_locked(hw, addr, &data, false);
802 * e1000_set_eee_pchlan - Enable/disable EEE support
803 * @hw: pointer to the HW structure
805 * Enable/disable EEE based on setting in dev_spec structure, the duplex of
806 * the link and the EEE capabilities of the link partner. The LPI Control
807 * register bits will remain set only if/when link is up.
809 * EEE LPI must not be asserted earlier than one second after link is up.
810 * On 82579, EEE LPI should not be enabled until such time otherwise there
811 * can be link issues with some switches. Other devices can have EEE LPI
812 * enabled immediately upon link up since they have a timer in hardware which
813 * prevents LPI from being asserted too early.
815 s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
817 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
819 u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
821 switch (hw->phy.type) {
822 case e1000_phy_82579:
823 lpa = I82579_EEE_LP_ABILITY;
824 pcs_status = I82579_EEE_PCS_STATUS;
825 adv_addr = I82579_EEE_ADVERTISEMENT;
828 lpa = I217_EEE_LP_ABILITY;
829 pcs_status = I217_EEE_PCS_STATUS;
830 adv_addr = I217_EEE_ADVERTISEMENT;
836 ret_val = hw->phy.ops.acquire(hw);
840 ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
844 /* Clear bits that enable EEE in various speeds */
845 lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
847 /* Enable EEE if not disabled by user */
848 if (!dev_spec->eee_disable) {
849 /* Save off link partner's EEE ability */
850 ret_val = e1000_read_emi_reg_locked(hw, lpa,
851 &dev_spec->eee_lp_ability);
855 /* Read EEE advertisement */
856 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
860 /* Enable EEE only for speeds in which the link partner is
861 * EEE capable and for which we advertise EEE.
863 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
864 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
866 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
867 e1e_rphy_locked(hw, MII_LPA, &data);
868 if (data & LPA_100FULL)
869 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
871 /* EEE is not supported in 100Half, so ignore
872 * partner's EEE in 100 ability if full-duplex
875 dev_spec->eee_lp_ability &=
876 ~I82579_EEE_100_SUPPORTED;
880 if (hw->phy.type == e1000_phy_82579) {
881 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
886 data &= ~I82579_LPI_100_PLL_SHUT;
887 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
891 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
892 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
896 ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
898 hw->phy.ops.release(hw);
904 * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
905 * @hw: pointer to the HW structure
906 * @link: link up bool flag
908 * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
909 * preventing further DMA write requests. Workaround the issue by disabling
910 * the de-assertion of the clock request when in 1Gpbs mode.
911 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
912 * speeds in order to avoid Tx hangs.
914 static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
916 u32 fextnvm6 = er32(FEXTNVM6);
917 u32 status = er32(STATUS);
921 if (link && (status & E1000_STATUS_SPEED_1000)) {
922 ret_val = hw->phy.ops.acquire(hw);
927 e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
933 e1000e_write_kmrn_reg_locked(hw,
934 E1000_KMRNCTRLSTA_K1_CONFIG,
936 ~E1000_KMRNCTRLSTA_K1_ENABLE);
940 usleep_range(10, 20);
942 ew32(FEXTNVM6, fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
945 e1000e_write_kmrn_reg_locked(hw,
946 E1000_KMRNCTRLSTA_K1_CONFIG,
949 hw->phy.ops.release(hw);
951 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
952 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
954 if ((hw->phy.revision > 5) || !link ||
955 ((status & E1000_STATUS_SPEED_100) &&
956 (status & E1000_STATUS_FD)))
957 goto update_fextnvm6;
959 ret_val = e1e_rphy(hw, I217_INBAND_CTRL, ®);
963 /* Clear link status transmit timeout */
964 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
966 if (status & E1000_STATUS_SPEED_100) {
967 /* Set inband Tx timeout to 5x10us for 100Half */
968 reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
970 /* Do not extend the K1 entry latency for 100Half */
971 fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
973 /* Set inband Tx timeout to 50x10us for 10Full/Half */
975 I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
977 /* Extend the K1 entry latency for 10 Mbps */
978 fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
981 ret_val = e1e_wphy(hw, I217_INBAND_CTRL, reg);
986 ew32(FEXTNVM6, fextnvm6);
993 * e1000_platform_pm_pch_lpt - Set platform power management values
994 * @hw: pointer to the HW structure
995 * @link: bool indicating link status
997 * Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like"
998 * GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed
999 * when link is up (which must not exceed the maximum latency supported
1000 * by the platform), otherwise specify there is no LTR requirement.
1001 * Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop
1002 * latencies in the LTR Extended Capability Structure in the PCIe Extended
1003 * Capability register set, on this device LTR is set by writing the
1004 * equivalent snoop/no-snoop latencies in the LTRV register in the MAC and
1005 * set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB)
1006 * message to the PMC.
1008 static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)
1010 u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) |
1011 link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND;
1012 u32 max_ltr_enc_d = 0; /* maximum LTR decoded by platform */
1013 u32 lat_enc_d = 0; /* latency decoded */
1014 u16 lat_enc = 0; /* latency encoded */
1017 u16 speed, duplex, scale = 0;
1018 u16 max_snoop, max_nosnoop;
1019 u16 max_ltr_enc; /* max LTR latency encoded */
1023 if (!hw->adapter->max_frame_size) {
1024 e_dbg("max_frame_size not set.\n");
1025 return -E1000_ERR_CONFIG;
1028 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1030 e_dbg("Speed not set.\n");
1031 return -E1000_ERR_CONFIG;
1034 /* Rx Packet Buffer Allocation size (KB) */
1035 rxa = er32(PBA) & E1000_PBA_RXA_MASK;
1037 /* Determine the maximum latency tolerated by the device.
1039 * Per the PCIe spec, the tolerated latencies are encoded as
1040 * a 3-bit encoded scale (only 0-5 are valid) multiplied by
1041 * a 10-bit value (0-1023) to provide a range from 1 ns to
1042 * 2^25*(2^10-1) ns. The scale is encoded as 0=2^0ns,
1043 * 1=2^5ns, 2=2^10ns,...5=2^25ns.
1046 value = (rxa > hw->adapter->max_frame_size) ?
1047 (rxa - hw->adapter->max_frame_size) * (16000 / speed) :
1050 while (value > PCI_LTR_VALUE_MASK) {
1052 value = DIV_ROUND_UP(value, BIT(5));
1054 if (scale > E1000_LTRV_SCALE_MAX) {
1055 e_dbg("Invalid LTR latency scale %d\n", scale);
1056 return -E1000_ERR_CONFIG;
1058 lat_enc = (u16)((scale << PCI_LTR_SCALE_SHIFT) | value);
1060 /* Determine the maximum latency tolerated by the platform */
1061 pci_read_config_word(hw->adapter->pdev, E1000_PCI_LTR_CAP_LPT,
1063 pci_read_config_word(hw->adapter->pdev,
1064 E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop);
1065 max_ltr_enc = max_t(u16, max_snoop, max_nosnoop);
1067 lat_enc_d = (lat_enc & E1000_LTRV_VALUE_MASK) *
1068 (1U << (E1000_LTRV_SCALE_FACTOR *
1069 ((lat_enc & E1000_LTRV_SCALE_MASK)
1070 >> E1000_LTRV_SCALE_SHIFT)));
1072 max_ltr_enc_d = (max_ltr_enc & E1000_LTRV_VALUE_MASK) *
1073 (1U << (E1000_LTRV_SCALE_FACTOR *
1074 ((max_ltr_enc & E1000_LTRV_SCALE_MASK)
1075 >> E1000_LTRV_SCALE_SHIFT)));
1077 if (lat_enc_d > max_ltr_enc_d)
1078 lat_enc = max_ltr_enc;
1081 /* Set Snoop and No-Snoop latencies the same */
1082 reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT);
1089 * e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1090 * @hw: pointer to the HW structure
1091 * @to_sx: boolean indicating a system power state transition to Sx
1093 * When link is down, configure ULP mode to significantly reduce the power
1094 * to the PHY. If on a Manageability Engine (ME) enabled system, tell the
1095 * ME firmware to start the ULP configuration. If not on an ME enabled
1096 * system, configure the ULP mode by software.
1098 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1105 if ((hw->mac.type < e1000_pch_lpt) ||
1106 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1107 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) ||
1108 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) ||
1109 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) ||
1110 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1113 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
1114 /* Request ME configure ULP mode in the PHY */
1115 mac_reg = er32(H2ME);
1116 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
1117 ew32(H2ME, mac_reg);
1125 /* Poll up to 5 seconds for Cable Disconnected indication */
1126 while (!(er32(FEXT) & E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
1127 /* Bail if link is re-acquired */
1128 if (er32(STATUS) & E1000_STATUS_LU)
1129 return -E1000_ERR_PHY;
1136 e_dbg("CABLE_DISCONNECTED %s set after %dmsec\n",
1138 E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not", i * 50);
1141 ret_val = hw->phy.ops.acquire(hw);
1145 /* Force SMBus mode in PHY */
1146 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1149 phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1150 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1152 /* Force SMBus mode in MAC */
1153 mac_reg = er32(CTRL_EXT);
1154 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1155 ew32(CTRL_EXT, mac_reg);
1157 /* Si workaround for ULP entry flow on i127/rev6 h/w. Enable
1158 * LPLU and disable Gig speed when entering ULP
1160 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) {
1161 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS,
1167 phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS;
1169 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1176 /* Set Inband ULP Exit, Reset to SMBus mode and
1177 * Disable SMBus Release on PERST# in PHY
1179 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1182 phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1183 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1185 if (er32(WUFC) & E1000_WUFC_LNKC)
1186 phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1188 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1190 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1191 phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT;
1193 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1194 phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP;
1195 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1197 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1199 /* Set Disable SMBus Release on PERST# in MAC */
1200 mac_reg = er32(FEXTNVM7);
1201 mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1202 ew32(FEXTNVM7, mac_reg);
1204 /* Commit ULP changes in PHY by starting auto ULP configuration */
1205 phy_reg |= I218_ULP_CONFIG1_START;
1206 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1208 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) &&
1209 to_sx && (er32(STATUS) & E1000_STATUS_LU)) {
1210 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1217 hw->phy.ops.release(hw);
1220 e_dbg("Error in ULP enable flow: %d\n", ret_val);
1222 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1228 * e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1229 * @hw: pointer to the HW structure
1230 * @force: boolean indicating whether or not to force disabling ULP
1232 * Un-configure ULP mode when link is up, the system is transitioned from
1233 * Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled
1234 * system, poll for an indication from ME that ULP has been un-configured.
1235 * If not on an ME enabled system, un-configure the ULP mode by software.
1237 * During nominal operation, this function is called when link is acquired
1238 * to disable ULP mode (force=false); otherwise, for example when unloading
1239 * the driver or during Sx->S0 transitions, this is called with force=true
1240 * to forcibly disable ULP.
1242 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1249 if ((hw->mac.type < e1000_pch_lpt) ||
1250 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1251 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) ||
1252 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) ||
1253 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) ||
1254 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
1257 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
1258 struct e1000_adapter *adapter = hw->adapter;
1259 bool firmware_bug = false;
1262 /* Request ME un-configure ULP mode in the PHY */
1263 mac_reg = er32(H2ME);
1264 mac_reg &= ~E1000_H2ME_ULP;
1265 mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1266 ew32(H2ME, mac_reg);
1269 /* Poll up to 2.5 seconds for ME to clear ULP_CFG_DONE.
1270 * If this takes more than 1 second, show a warning indicating a
1273 while (er32(FWSM) & E1000_FWSM_ULP_CFG_DONE) {
1275 ret_val = -E1000_ERR_PHY;
1278 if (i > 100 && !firmware_bug)
1279 firmware_bug = true;
1281 usleep_range(10000, 11000);
1284 e_warn("ULP_CONFIG_DONE took %d msec. This is a firmware bug\n",
1287 e_dbg("ULP_CONFIG_DONE cleared after %d msec\n",
1291 mac_reg = er32(H2ME);
1292 mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
1293 ew32(H2ME, mac_reg);
1295 /* Clear H2ME.ULP after ME ULP configuration */
1296 mac_reg = er32(H2ME);
1297 mac_reg &= ~E1000_H2ME_ULP;
1298 ew32(H2ME, mac_reg);
1304 ret_val = hw->phy.ops.acquire(hw);
1309 /* Toggle LANPHYPC Value bit */
1310 e1000_toggle_lanphypc_pch_lpt(hw);
1312 /* Unforce SMBus mode in PHY */
1313 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1315 /* The MAC might be in PCIe mode, so temporarily force to
1316 * SMBus mode in order to access the PHY.
1318 mac_reg = er32(CTRL_EXT);
1319 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1320 ew32(CTRL_EXT, mac_reg);
1324 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1329 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1330 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1332 /* Unforce SMBus mode in MAC */
1333 mac_reg = er32(CTRL_EXT);
1334 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
1335 ew32(CTRL_EXT, mac_reg);
1337 /* When ULP mode was previously entered, K1 was disabled by the
1338 * hardware. Re-Enable K1 in the PHY when exiting ULP.
1340 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1343 phy_reg |= HV_PM_CTRL_K1_ENABLE;
1344 e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
1346 /* Clear ULP enabled configuration */
1347 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1350 phy_reg &= ~(I218_ULP_CONFIG1_IND |
1351 I218_ULP_CONFIG1_STICKY_ULP |
1352 I218_ULP_CONFIG1_RESET_TO_SMBUS |
1353 I218_ULP_CONFIG1_WOL_HOST |
1354 I218_ULP_CONFIG1_INBAND_EXIT |
1355 I218_ULP_CONFIG1_EN_ULP_LANPHYPC |
1356 I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST |
1357 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1358 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1360 /* Commit ULP changes by starting auto ULP configuration */
1361 phy_reg |= I218_ULP_CONFIG1_START;
1362 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1364 /* Clear Disable SMBus Release on PERST# in MAC */
1365 mac_reg = er32(FEXTNVM7);
1366 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
1367 ew32(FEXTNVM7, mac_reg);
1370 hw->phy.ops.release(hw);
1372 e1000_phy_hw_reset(hw);
1377 e_dbg("Error in ULP disable flow: %d\n", ret_val);
1379 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
1385 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1386 * @hw: pointer to the HW structure
1388 * Checks to see of the link status of the hardware has changed. If a
1389 * change in link status has been detected, then we read the PHY registers
1390 * to get the current speed/duplex if link exists.
1392 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1394 struct e1000_mac_info *mac = &hw->mac;
1395 s32 ret_val, tipg_reg = 0;
1396 u16 emi_addr, emi_val = 0;
1400 /* We only want to go out to the PHY registers to see if Auto-Neg
1401 * has completed and/or if our link status has changed. The
1402 * get_link_status flag is set upon receiving a Link Status
1403 * Change or Rx Sequence Error interrupt.
1405 if (!mac->get_link_status)
1407 mac->get_link_status = false;
1409 /* First we want to see if the MII Status Register reports
1410 * link. If so, then we want to get the current speed/duplex
1413 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1417 if (hw->mac.type == e1000_pchlan) {
1418 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1423 /* When connected at 10Mbps half-duplex, some parts are excessively
1424 * aggressive resulting in many collisions. To avoid this, increase
1425 * the IPG and reduce Rx latency in the PHY.
1427 if ((hw->mac.type >= e1000_pch2lan) && link) {
1430 e1000e_get_speed_and_duplex_copper(hw, &speed, &duplex);
1431 tipg_reg = er32(TIPG);
1432 tipg_reg &= ~E1000_TIPG_IPGT_MASK;
1434 if (duplex == HALF_DUPLEX && speed == SPEED_10) {
1436 /* Reduce Rx latency in analog PHY */
1438 } else if (hw->mac.type >= e1000_pch_spt &&
1439 duplex == FULL_DUPLEX && speed != SPEED_1000) {
1444 /* Roll back the default values */
1449 ew32(TIPG, tipg_reg);
1451 ret_val = hw->phy.ops.acquire(hw);
1455 if (hw->mac.type == e1000_pch2lan)
1456 emi_addr = I82579_RX_CONFIG;
1458 emi_addr = I217_RX_CONFIG;
1459 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val);
1461 if (hw->mac.type >= e1000_pch_lpt) {
1464 e1e_rphy_locked(hw, I217_PLL_CLOCK_GATE_REG, &phy_reg);
1465 phy_reg &= ~I217_PLL_CLOCK_GATE_MASK;
1466 if (speed == SPEED_100 || speed == SPEED_10)
1470 e1e_wphy_locked(hw, I217_PLL_CLOCK_GATE_REG, phy_reg);
1472 if (speed == SPEED_1000) {
1473 hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL,
1476 phy_reg |= HV_PM_CTRL_K1_CLK_REQ;
1478 hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL,
1482 hw->phy.ops.release(hw);
1487 if (hw->mac.type >= e1000_pch_spt) {
1491 if (speed == SPEED_1000) {
1492 ret_val = hw->phy.ops.acquire(hw);
1496 ret_val = e1e_rphy_locked(hw,
1500 hw->phy.ops.release(hw);
1504 ptr_gap = (data & (0x3FF << 2)) >> 2;
1505 if (ptr_gap < 0x18) {
1506 data &= ~(0x3FF << 2);
1507 data |= (0x18 << 2);
1513 hw->phy.ops.release(hw);
1517 ret_val = hw->phy.ops.acquire(hw);
1521 ret_val = e1e_wphy_locked(hw,
1524 hw->phy.ops.release(hw);
1532 /* I217 Packet Loss issue:
1533 * ensure that FEXTNVM4 Beacon Duration is set correctly
1535 * Set the Beacon Duration for I217 to 8 usec
1537 if (hw->mac.type >= e1000_pch_lpt) {
1540 mac_reg = er32(FEXTNVM4);
1541 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1542 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1543 ew32(FEXTNVM4, mac_reg);
1546 /* Work-around I218 hang issue */
1547 if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1548 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1549 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM3) ||
1550 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V3)) {
1551 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1555 if (hw->mac.type >= e1000_pch_lpt) {
1556 /* Set platform power management values for
1557 * Latency Tolerance Reporting (LTR)
1559 ret_val = e1000_platform_pm_pch_lpt(hw, link);
1564 /* Clear link partner's EEE ability */
1565 hw->dev_spec.ich8lan.eee_lp_ability = 0;
1567 if (hw->mac.type >= e1000_pch_lpt) {
1568 u32 fextnvm6 = er32(FEXTNVM6);
1570 if (hw->mac.type == e1000_pch_spt) {
1571 /* FEXTNVM6 K1-off workaround - for SPT only */
1572 u32 pcieanacfg = er32(PCIEANACFG);
1574 if (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE)
1575 fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE;
1577 fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
1580 ew32(FEXTNVM6, fextnvm6);
1586 switch (hw->mac.type) {
1588 ret_val = e1000_k1_workaround_lv(hw);
1593 if (hw->phy.type == e1000_phy_82578) {
1594 ret_val = e1000_link_stall_workaround_hv(hw);
1599 /* Workaround for PCHx parts in half-duplex:
1600 * Set the number of preambles removed from the packet
1601 * when it is passed from the PHY to the MAC to prevent
1602 * the MAC from misinterpreting the packet type.
1604 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1605 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1607 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD)
1608 phy_reg |= BIT(HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1610 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1616 /* Check if there was DownShift, must be checked
1617 * immediately after link-up
1619 e1000e_check_downshift(hw);
1621 /* Enable/Disable EEE after link up */
1622 if (hw->phy.type > e1000_phy_82579) {
1623 ret_val = e1000_set_eee_pchlan(hw);
1628 /* If we are forcing speed/duplex, then we simply return since
1629 * we have already determined whether we have link or not.
1632 return -E1000_ERR_CONFIG;
1634 /* Auto-Neg is enabled. Auto Speed Detection takes care
1635 * of MAC speed/duplex configuration. So we only need to
1636 * configure Collision Distance in the MAC.
1638 mac->ops.config_collision_dist(hw);
1640 /* Configure Flow Control now that Auto-Neg has completed.
1641 * First, we need to restore the desired flow control
1642 * settings because we may have had to re-autoneg with a
1643 * different link partner.
1645 ret_val = e1000e_config_fc_after_link_up(hw);
1647 e_dbg("Error configuring flow control\n");
1652 mac->get_link_status = true;
1656 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
1658 struct e1000_hw *hw = &adapter->hw;
1661 rc = e1000_init_mac_params_ich8lan(hw);
1665 rc = e1000_init_nvm_params_ich8lan(hw);
1669 switch (hw->mac.type) {
1672 case e1000_ich10lan:
1673 rc = e1000_init_phy_params_ich8lan(hw);
1684 rc = e1000_init_phy_params_pchlan(hw);
1692 /* Disable Jumbo Frame support on parts with Intel 10/100 PHY or
1693 * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
1695 if ((adapter->hw.phy.type == e1000_phy_ife) ||
1696 ((adapter->hw.mac.type >= e1000_pch2lan) &&
1697 (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) {
1698 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
1699 adapter->max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
1701 hw->mac.ops.blink_led = NULL;
1704 if ((adapter->hw.mac.type == e1000_ich8lan) &&
1705 (adapter->hw.phy.type != e1000_phy_ife))
1706 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
1708 /* Enable workaround for 82579 w/ ME enabled */
1709 if ((adapter->hw.mac.type == e1000_pch2lan) &&
1710 (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
1711 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA;
1716 static DEFINE_MUTEX(nvm_mutex);
1719 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1720 * @hw: pointer to the HW structure
1722 * Acquires the mutex for performing NVM operations.
1724 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1726 mutex_lock(&nvm_mutex);
1732 * e1000_release_nvm_ich8lan - Release NVM mutex
1733 * @hw: pointer to the HW structure
1735 * Releases the mutex used while performing NVM operations.
1737 static void e1000_release_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1739 mutex_unlock(&nvm_mutex);
1743 * e1000_acquire_swflag_ich8lan - Acquire software control flag
1744 * @hw: pointer to the HW structure
1746 * Acquires the software control flag for performing PHY and select
1749 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1751 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1754 if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE,
1755 &hw->adapter->state)) {
1756 e_dbg("contention for Phy access\n");
1757 return -E1000_ERR_PHY;
1761 extcnf_ctrl = er32(EXTCNF_CTRL);
1762 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1770 e_dbg("SW has already locked the resource.\n");
1771 ret_val = -E1000_ERR_CONFIG;
1775 timeout = SW_FLAG_TIMEOUT;
1777 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1778 ew32(EXTCNF_CTRL, extcnf_ctrl);
1781 extcnf_ctrl = er32(EXTCNF_CTRL);
1782 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1790 e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1791 er32(FWSM), extcnf_ctrl);
1792 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1793 ew32(EXTCNF_CTRL, extcnf_ctrl);
1794 ret_val = -E1000_ERR_CONFIG;
1800 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1806 * e1000_release_swflag_ich8lan - Release software control flag
1807 * @hw: pointer to the HW structure
1809 * Releases the software control flag for performing PHY and select
1812 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1816 extcnf_ctrl = er32(EXTCNF_CTRL);
1818 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1819 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1820 ew32(EXTCNF_CTRL, extcnf_ctrl);
1822 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");
1825 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1829 * e1000_check_mng_mode_ich8lan - Checks management mode
1830 * @hw: pointer to the HW structure
1832 * This checks if the adapter has any manageability enabled.
1833 * This is a function pointer entry point only called by read/write
1834 * routines for the PHY and NVM parts.
1836 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1841 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1842 ((fwsm & E1000_FWSM_MODE_MASK) ==
1843 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1847 * e1000_check_mng_mode_pchlan - Checks management mode
1848 * @hw: pointer to the HW structure
1850 * This checks if the adapter has iAMT enabled.
1851 * This is a function pointer entry point only called by read/write
1852 * routines for the PHY and NVM parts.
1854 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1859 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1860 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1864 * e1000_rar_set_pch2lan - Set receive address register
1865 * @hw: pointer to the HW structure
1866 * @addr: pointer to the receive address
1867 * @index: receive address array register
1869 * Sets the receive address array register at index to the address passed
1870 * in by addr. For 82579, RAR[0] is the base address register that is to
1871 * contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1872 * Use SHRA[0-3] in place of those reserved for ME.
1874 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1876 u32 rar_low, rar_high;
1878 /* HW expects these in little endian so we reverse the byte order
1879 * from network order (big endian) to little endian
1881 rar_low = ((u32)addr[0] |
1882 ((u32)addr[1] << 8) |
1883 ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1885 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1887 /* If MAC address zero, no need to set the AV bit */
1888 if (rar_low || rar_high)
1889 rar_high |= E1000_RAH_AV;
1892 ew32(RAL(index), rar_low);
1894 ew32(RAH(index), rar_high);
1899 /* RAR[1-6] are owned by manageability. Skip those and program the
1900 * next address into the SHRA register array.
1902 if (index < (u32)(hw->mac.rar_entry_count)) {
1905 ret_val = e1000_acquire_swflag_ich8lan(hw);
1909 ew32(SHRAL(index - 1), rar_low);
1911 ew32(SHRAH(index - 1), rar_high);
1914 e1000_release_swflag_ich8lan(hw);
1916 /* verify the register updates */
1917 if ((er32(SHRAL(index - 1)) == rar_low) &&
1918 (er32(SHRAH(index - 1)) == rar_high))
1921 e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1922 (index - 1), er32(FWSM));
1926 e_dbg("Failed to write receive address at index %d\n", index);
1927 return -E1000_ERR_CONFIG;
1931 * e1000_rar_get_count_pch_lpt - Get the number of available SHRA
1932 * @hw: pointer to the HW structure
1934 * Get the number of available receive registers that the Host can
1935 * program. SHRA[0-10] are the shared receive address registers
1936 * that are shared between the Host and manageability engine (ME).
1937 * ME can reserve any number of addresses and the host needs to be
1938 * able to tell how many available registers it has access to.
1940 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw)
1945 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
1946 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1948 switch (wlock_mac) {
1950 /* All SHRA[0..10] and RAR[0] available */
1951 num_entries = hw->mac.rar_entry_count;
1954 /* Only RAR[0] available */
1958 /* SHRA[0..(wlock_mac - 1)] available + RAR[0] */
1959 num_entries = wlock_mac + 1;
1967 * e1000_rar_set_pch_lpt - Set receive address registers
1968 * @hw: pointer to the HW structure
1969 * @addr: pointer to the receive address
1970 * @index: receive address array register
1972 * Sets the receive address register array at index to the address passed
1973 * in by addr. For LPT, RAR[0] is the base address register that is to
1974 * contain the MAC address. SHRA[0-10] are the shared receive address
1975 * registers that are shared between the Host and manageability engine (ME).
1977 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
1979 u32 rar_low, rar_high;
1982 /* HW expects these in little endian so we reverse the byte order
1983 * from network order (big endian) to little endian
1985 rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
1986 ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1988 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1990 /* If MAC address zero, no need to set the AV bit */
1991 if (rar_low || rar_high)
1992 rar_high |= E1000_RAH_AV;
1995 ew32(RAL(index), rar_low);
1997 ew32(RAH(index), rar_high);
2002 /* The manageability engine (ME) can lock certain SHRAR registers that
2003 * it is using - those registers are unavailable for use.
2005 if (index < hw->mac.rar_entry_count) {
2006 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
2007 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
2009 /* Check if all SHRAR registers are locked */
2013 if ((wlock_mac == 0) || (index <= wlock_mac)) {
2016 ret_val = e1000_acquire_swflag_ich8lan(hw);
2021 ew32(SHRAL_PCH_LPT(index - 1), rar_low);
2023 ew32(SHRAH_PCH_LPT(index - 1), rar_high);
2026 e1000_release_swflag_ich8lan(hw);
2028 /* verify the register updates */
2029 if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) &&
2030 (er32(SHRAH_PCH_LPT(index - 1)) == rar_high))
2036 e_dbg("Failed to write receive address at index %d\n", index);
2037 return -E1000_ERR_CONFIG;
2041 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
2042 * @hw: pointer to the HW structure
2044 * Checks if firmware is blocking the reset of the PHY.
2045 * This is a function pointer entry point only called by
2048 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
2050 bool blocked = false;
2053 /* Check the PHY (LCD) reset flag */
2054 if (hw->phy.reset_disable)
2057 while ((blocked = !(er32(FWSM) & E1000_ICH_FWSM_RSPCIPHY)) &&
2059 usleep_range(10000, 11000);
2060 return blocked ? E1000_BLK_PHY_RESET : 0;
2064 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
2065 * @hw: pointer to the HW structure
2067 * Assumes semaphore already acquired.
2070 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
2073 u32 strap = er32(STRAP);
2074 u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
2075 E1000_STRAP_SMT_FREQ_SHIFT;
2078 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
2080 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
2084 phy_data &= ~HV_SMB_ADDR_MASK;
2085 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
2086 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
2088 if (hw->phy.type == e1000_phy_i217) {
2089 /* Restore SMBus frequency */
2091 phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
2092 phy_data |= (freq & BIT(0)) <<
2093 HV_SMB_ADDR_FREQ_LOW_SHIFT;
2094 phy_data |= (freq & BIT(1)) <<
2095 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
2097 e_dbg("Unsupported SMB frequency in PHY\n");
2101 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
2105 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
2106 * @hw: pointer to the HW structure
2108 * SW should configure the LCD from the NVM extended configuration region
2109 * as a workaround for certain parts.
2111 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
2113 struct e1000_phy_info *phy = &hw->phy;
2114 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
2116 u16 word_addr, reg_data, reg_addr, phy_page = 0;
2118 /* Initialize the PHY from the NVM on ICH platforms. This
2119 * is needed due to an issue where the NVM configuration is
2120 * not properly autoloaded after power transitions.
2121 * Therefore, after each PHY reset, we will load the
2122 * configuration data out of the NVM manually.
2124 switch (hw->mac.type) {
2126 if (phy->type != e1000_phy_igp_3)
2129 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
2130 (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
2131 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
2144 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
2150 ret_val = hw->phy.ops.acquire(hw);
2154 data = er32(FEXTNVM);
2155 if (!(data & sw_cfg_mask))
2158 /* Make sure HW does not configure LCD from PHY
2159 * extended configuration before SW configuration
2161 data = er32(EXTCNF_CTRL);
2162 if ((hw->mac.type < e1000_pch2lan) &&
2163 (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
2166 cnf_size = er32(EXTCNF_SIZE);
2167 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
2168 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
2172 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
2173 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
2175 if (((hw->mac.type == e1000_pchlan) &&
2176 !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
2177 (hw->mac.type > e1000_pchlan)) {
2178 /* HW configures the SMBus address and LEDs when the
2179 * OEM and LCD Write Enable bits are set in the NVM.
2180 * When both NVM bits are cleared, SW will configure
2183 ret_val = e1000_write_smbus_addr(hw);
2187 data = er32(LEDCTL);
2188 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
2194 /* Configure LCD from extended configuration region. */
2196 /* cnf_base_addr is in DWORD */
2197 word_addr = (u16)(cnf_base_addr << 1);
2199 for (i = 0; i < cnf_size; i++) {
2200 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, ®_data);
2204 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
2209 /* Save off the PHY page for future writes. */
2210 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
2211 phy_page = reg_data;
2215 reg_addr &= PHY_REG_MASK;
2216 reg_addr |= phy_page;
2218 ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data);
2224 hw->phy.ops.release(hw);
2229 * e1000_k1_gig_workaround_hv - K1 Si workaround
2230 * @hw: pointer to the HW structure
2231 * @link: link up bool flag
2233 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
2234 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
2235 * If link is down, the function will restore the default K1 setting located
2238 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
2242 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
2244 if (hw->mac.type != e1000_pchlan)
2247 /* Wrap the whole flow with the sw flag */
2248 ret_val = hw->phy.ops.acquire(hw);
2252 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
2254 if (hw->phy.type == e1000_phy_82578) {
2255 ret_val = e1e_rphy_locked(hw, BM_CS_STATUS,
2260 status_reg &= (BM_CS_STATUS_LINK_UP |
2261 BM_CS_STATUS_RESOLVED |
2262 BM_CS_STATUS_SPEED_MASK);
2264 if (status_reg == (BM_CS_STATUS_LINK_UP |
2265 BM_CS_STATUS_RESOLVED |
2266 BM_CS_STATUS_SPEED_1000))
2270 if (hw->phy.type == e1000_phy_82577) {
2271 ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg);
2275 status_reg &= (HV_M_STATUS_LINK_UP |
2276 HV_M_STATUS_AUTONEG_COMPLETE |
2277 HV_M_STATUS_SPEED_MASK);
2279 if (status_reg == (HV_M_STATUS_LINK_UP |
2280 HV_M_STATUS_AUTONEG_COMPLETE |
2281 HV_M_STATUS_SPEED_1000))
2285 /* Link stall fix for link up */
2286 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100);
2291 /* Link stall fix for link down */
2292 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100);
2297 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2300 hw->phy.ops.release(hw);
2306 * e1000_configure_k1_ich8lan - Configure K1 power state
2307 * @hw: pointer to the HW structure
2308 * @k1_enable: K1 state to configure
2310 * Configure the K1 power state based on the provided parameter.
2311 * Assumes semaphore already acquired.
2313 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2315 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
2323 ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2329 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
2331 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
2333 ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2338 usleep_range(20, 40);
2339 ctrl_ext = er32(CTRL_EXT);
2340 ctrl_reg = er32(CTRL);
2342 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2343 reg |= E1000_CTRL_FRCSPD;
2346 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
2348 usleep_range(20, 40);
2349 ew32(CTRL, ctrl_reg);
2350 ew32(CTRL_EXT, ctrl_ext);
2352 usleep_range(20, 40);
2358 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2359 * @hw: pointer to the HW structure
2360 * @d0_state: boolean if entering d0 or d3 device state
2362 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
2363 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
2364 * in NVM determines whether HW should configure LPLU and Gbe Disable.
2366 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
2372 if (hw->mac.type < e1000_pchlan)
2375 ret_val = hw->phy.ops.acquire(hw);
2379 if (hw->mac.type == e1000_pchlan) {
2380 mac_reg = er32(EXTCNF_CTRL);
2381 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
2385 mac_reg = er32(FEXTNVM);
2386 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
2389 mac_reg = er32(PHY_CTRL);
2391 ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg);
2395 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
2398 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
2399 oem_reg |= HV_OEM_BITS_GBE_DIS;
2401 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
2402 oem_reg |= HV_OEM_BITS_LPLU;
2404 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
2405 E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
2406 oem_reg |= HV_OEM_BITS_GBE_DIS;
2408 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
2409 E1000_PHY_CTRL_NOND0A_LPLU))
2410 oem_reg |= HV_OEM_BITS_LPLU;
2413 /* Set Restart auto-neg to activate the bits */
2414 if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
2415 !hw->phy.ops.check_reset_block(hw))
2416 oem_reg |= HV_OEM_BITS_RESTART_AN;
2418 ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg);
2421 hw->phy.ops.release(hw);
2427 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2428 * @hw: pointer to the HW structure
2430 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
2435 ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
2439 data |= HV_KMRN_MDIO_SLOW;
2441 ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
2447 * e1000_hv_phy_workarounds_ich8lan - apply PHY workarounds
2448 * @hw: pointer to the HW structure
2450 * A series of PHY workarounds to be done after every PHY reset.
2452 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2457 if (hw->mac.type != e1000_pchlan)
2460 /* Set MDIO slow mode before any other MDIO access */
2461 if (hw->phy.type == e1000_phy_82577) {
2462 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2467 if (((hw->phy.type == e1000_phy_82577) &&
2468 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
2469 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
2470 /* Disable generation of early preamble */
2471 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
2475 /* Preamble tuning for SSC */
2476 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204);
2481 if (hw->phy.type == e1000_phy_82578) {
2482 /* Return registers to default by doing a soft reset then
2483 * writing 0x3140 to the control register.
2485 if (hw->phy.revision < 2) {
2486 e1000e_phy_sw_reset(hw);
2487 ret_val = e1e_wphy(hw, MII_BMCR, 0x3140);
2494 ret_val = hw->phy.ops.acquire(hw);
2499 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2500 hw->phy.ops.release(hw);
2504 /* Configure the K1 Si workaround during phy reset assuming there is
2505 * link so that it disables K1 if link is in 1Gbps.
2507 ret_val = e1000_k1_gig_workaround_hv(hw, true);
2511 /* Workaround for link disconnects on a busy hub in half duplex */
2512 ret_val = hw->phy.ops.acquire(hw);
2515 ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2518 ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF);
2522 /* set MSE higher to enable link to stay up when noise is high */
2523 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2525 hw->phy.ops.release(hw);
2531 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2532 * @hw: pointer to the HW structure
2534 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
2540 ret_val = hw->phy.ops.acquire(hw);
2543 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2547 /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
2548 for (i = 0; i < (hw->mac.rar_entry_count); i++) {
2549 mac_reg = er32(RAL(i));
2550 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
2551 (u16)(mac_reg & 0xFFFF));
2552 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
2553 (u16)((mac_reg >> 16) & 0xFFFF));
2555 mac_reg = er32(RAH(i));
2556 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
2557 (u16)(mac_reg & 0xFFFF));
2558 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
2559 (u16)((mac_reg & E1000_RAH_AV)
2563 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2566 hw->phy.ops.release(hw);
2570 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2572 * @hw: pointer to the HW structure
2573 * @enable: flag to enable/disable workaround when enabling/disabling jumbos
2575 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2582 if (hw->mac.type < e1000_pch2lan)
2585 /* disable Rx path while enabling/disabling workaround */
2586 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
2587 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | BIT(14));
2592 /* Write Rx addresses (rar_entry_count for RAL/H, and
2593 * SHRAL/H) and initial CRC values to the MAC
2595 for (i = 0; i < hw->mac.rar_entry_count; i++) {
2596 u8 mac_addr[ETH_ALEN] = { 0 };
2597 u32 addr_high, addr_low;
2599 addr_high = er32(RAH(i));
2600 if (!(addr_high & E1000_RAH_AV))
2602 addr_low = er32(RAL(i));
2603 mac_addr[0] = (addr_low & 0xFF);
2604 mac_addr[1] = ((addr_low >> 8) & 0xFF);
2605 mac_addr[2] = ((addr_low >> 16) & 0xFF);
2606 mac_addr[3] = ((addr_low >> 24) & 0xFF);
2607 mac_addr[4] = (addr_high & 0xFF);
2608 mac_addr[5] = ((addr_high >> 8) & 0xFF);
2610 ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr));
2613 /* Write Rx addresses to the PHY */
2614 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2616 /* Enable jumbo frame workaround in the MAC */
2617 mac_reg = er32(FFLT_DBG);
2618 mac_reg &= ~BIT(14);
2619 mac_reg |= (7 << 15);
2620 ew32(FFLT_DBG, mac_reg);
2622 mac_reg = er32(RCTL);
2623 mac_reg |= E1000_RCTL_SECRC;
2624 ew32(RCTL, mac_reg);
2626 ret_val = e1000e_read_kmrn_reg(hw,
2627 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2631 ret_val = e1000e_write_kmrn_reg(hw,
2632 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2636 ret_val = e1000e_read_kmrn_reg(hw,
2637 E1000_KMRNCTRLSTA_HD_CTRL,
2641 data &= ~(0xF << 8);
2643 ret_val = e1000e_write_kmrn_reg(hw,
2644 E1000_KMRNCTRLSTA_HD_CTRL,
2649 /* Enable jumbo frame workaround in the PHY */
2650 e1e_rphy(hw, PHY_REG(769, 23), &data);
2651 data &= ~(0x7F << 5);
2652 data |= (0x37 << 5);
2653 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2656 e1e_rphy(hw, PHY_REG(769, 16), &data);
2658 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2661 e1e_rphy(hw, PHY_REG(776, 20), &data);
2662 data &= ~(0x3FF << 2);
2663 data |= (E1000_TX_PTR_GAP << 2);
2664 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2667 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100);
2670 e1e_rphy(hw, HV_PM_CTRL, &data);
2671 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | BIT(10));
2675 /* Write MAC register values back to h/w defaults */
2676 mac_reg = er32(FFLT_DBG);
2677 mac_reg &= ~(0xF << 14);
2678 ew32(FFLT_DBG, mac_reg);
2680 mac_reg = er32(RCTL);
2681 mac_reg &= ~E1000_RCTL_SECRC;
2682 ew32(RCTL, mac_reg);
2684 ret_val = e1000e_read_kmrn_reg(hw,
2685 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2689 ret_val = e1000e_write_kmrn_reg(hw,
2690 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2694 ret_val = e1000e_read_kmrn_reg(hw,
2695 E1000_KMRNCTRLSTA_HD_CTRL,
2699 data &= ~(0xF << 8);
2701 ret_val = e1000e_write_kmrn_reg(hw,
2702 E1000_KMRNCTRLSTA_HD_CTRL,
2707 /* Write PHY register values back to h/w defaults */
2708 e1e_rphy(hw, PHY_REG(769, 23), &data);
2709 data &= ~(0x7F << 5);
2710 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2713 e1e_rphy(hw, PHY_REG(769, 16), &data);
2715 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2718 e1e_rphy(hw, PHY_REG(776, 20), &data);
2719 data &= ~(0x3FF << 2);
2721 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2724 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
2727 e1e_rphy(hw, HV_PM_CTRL, &data);
2728 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~BIT(10));
2733 /* re-enable Rx path after enabling/disabling workaround */
2734 return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~BIT(14));
2738 * e1000_lv_phy_workarounds_ich8lan - apply ich8 specific workarounds
2739 * @hw: pointer to the HW structure
2741 * A series of PHY workarounds to be done after every PHY reset.
2743 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2747 if (hw->mac.type != e1000_pch2lan)
2750 /* Set MDIO slow mode before any other MDIO access */
2751 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2755 ret_val = hw->phy.ops.acquire(hw);
2758 /* set MSE higher to enable link to stay up when noise is high */
2759 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2762 /* drop link after 5 times MSE threshold was reached */
2763 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2765 hw->phy.ops.release(hw);
2771 * e1000_k1_workaround_lv - K1 Si workaround
2772 * @hw: pointer to the HW structure
2774 * Workaround to set the K1 beacon duration for 82579 parts in 10Mbps
2775 * Disable K1 in 1000Mbps and 100Mbps
2777 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2782 if (hw->mac.type != e1000_pch2lan)
2785 /* Set K1 beacon duration based on 10Mbs speed */
2786 ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
2790 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2791 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2793 (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) {
2796 /* LV 1G/100 Packet drop issue wa */
2797 ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg);
2800 pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE;
2801 ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg);
2807 mac_reg = er32(FEXTNVM4);
2808 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
2809 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
2810 ew32(FEXTNVM4, mac_reg);
2818 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2819 * @hw: pointer to the HW structure
2820 * @gate: boolean set to true to gate, false to ungate
2822 * Gate/ungate the automatic PHY configuration via hardware; perform
2823 * the configuration via software instead.
2825 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2829 if (hw->mac.type < e1000_pch2lan)
2832 extcnf_ctrl = er32(EXTCNF_CTRL);
2835 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2837 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2839 ew32(EXTCNF_CTRL, extcnf_ctrl);
2843 * e1000_lan_init_done_ich8lan - Check for PHY config completion
2844 * @hw: pointer to the HW structure
2846 * Check the appropriate indication the MAC has finished configuring the
2847 * PHY after a software reset.
2849 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2851 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
2853 /* Wait for basic configuration completes before proceeding */
2855 data = er32(STATUS);
2856 data &= E1000_STATUS_LAN_INIT_DONE;
2857 usleep_range(100, 200);
2858 } while ((!data) && --loop);
2860 /* If basic configuration is incomplete before the above loop
2861 * count reaches 0, loading the configuration from NVM will
2862 * leave the PHY in a bad state possibly resulting in no link.
2865 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
2867 /* Clear the Init Done bit for the next init event */
2868 data = er32(STATUS);
2869 data &= ~E1000_STATUS_LAN_INIT_DONE;
2874 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
2875 * @hw: pointer to the HW structure
2877 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
2882 if (hw->phy.ops.check_reset_block(hw))
2885 /* Allow time for h/w to get to quiescent state after reset */
2886 usleep_range(10000, 11000);
2888 /* Perform any necessary post-reset workarounds */
2889 switch (hw->mac.type) {
2891 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2896 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
2904 /* Clear the host wakeup bit after lcd reset */
2905 if (hw->mac.type >= e1000_pchlan) {
2906 e1e_rphy(hw, BM_PORT_GEN_CFG, ®);
2907 reg &= ~BM_WUC_HOST_WU_BIT;
2908 e1e_wphy(hw, BM_PORT_GEN_CFG, reg);
2911 /* Configure the LCD with the extended configuration region in NVM */
2912 ret_val = e1000_sw_lcd_config_ich8lan(hw);
2916 /* Configure the LCD with the OEM bits in NVM */
2917 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2919 if (hw->mac.type == e1000_pch2lan) {
2920 /* Ungate automatic PHY configuration on non-managed 82579 */
2921 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
2922 usleep_range(10000, 11000);
2923 e1000_gate_hw_phy_config_ich8lan(hw, false);
2926 /* Set EEE LPI Update Timer to 200usec */
2927 ret_val = hw->phy.ops.acquire(hw);
2930 ret_val = e1000_write_emi_reg_locked(hw,
2931 I82579_LPI_UPDATE_TIMER,
2933 hw->phy.ops.release(hw);
2940 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
2941 * @hw: pointer to the HW structure
2944 * This is a function pointer entry point called by drivers
2945 * or other shared routines.
2947 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
2951 /* Gate automatic PHY configuration by hardware on non-managed 82579 */
2952 if ((hw->mac.type == e1000_pch2lan) &&
2953 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
2954 e1000_gate_hw_phy_config_ich8lan(hw, true);
2956 ret_val = e1000e_phy_hw_reset_generic(hw);
2960 return e1000_post_phy_reset_ich8lan(hw);
2964 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
2965 * @hw: pointer to the HW structure
2966 * @active: true to enable LPLU, false to disable
2968 * Sets the LPLU state according to the active flag. For PCH, if OEM write
2969 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
2970 * the phy speed. This function will manually set the LPLU bit and restart
2971 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
2972 * since it configures the same bit.
2974 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
2979 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
2984 oem_reg |= HV_OEM_BITS_LPLU;
2986 oem_reg &= ~HV_OEM_BITS_LPLU;
2988 if (!hw->phy.ops.check_reset_block(hw))
2989 oem_reg |= HV_OEM_BITS_RESTART_AN;
2991 return e1e_wphy(hw, HV_OEM_BITS, oem_reg);
2995 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
2996 * @hw: pointer to the HW structure
2997 * @active: true to enable LPLU, false to disable
2999 * Sets the LPLU D0 state according to the active flag. When
3000 * activating LPLU this function also disables smart speed
3001 * and vice versa. LPLU will not be activated unless the
3002 * device autonegotiation advertisement meets standards of
3003 * either 10 or 10/100 or 10/100/1000 at all duplexes.
3004 * This is a function pointer entry point only called by
3005 * PHY setup routines.
3007 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3009 struct e1000_phy_info *phy = &hw->phy;
3014 if (phy->type == e1000_phy_ife)
3017 phy_ctrl = er32(PHY_CTRL);
3020 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
3021 ew32(PHY_CTRL, phy_ctrl);
3023 if (phy->type != e1000_phy_igp_3)
3026 /* Call gig speed drop workaround on LPLU before accessing
3029 if (hw->mac.type == e1000_ich8lan)
3030 e1000e_gig_downshift_workaround_ich8lan(hw);
3032 /* When LPLU is enabled, we should disable SmartSpeed */
3033 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
3036 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3037 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
3041 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
3042 ew32(PHY_CTRL, phy_ctrl);
3044 if (phy->type != e1000_phy_igp_3)
3047 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
3048 * during Dx states where the power conservation is most
3049 * important. During driver activity we should enable
3050 * SmartSpeed, so performance is maintained.
3052 if (phy->smart_speed == e1000_smart_speed_on) {
3053 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3058 data |= IGP01E1000_PSCFR_SMART_SPEED;
3059 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3063 } else if (phy->smart_speed == e1000_smart_speed_off) {
3064 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3069 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3070 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3081 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
3082 * @hw: pointer to the HW structure
3083 * @active: true to enable LPLU, false to disable
3085 * Sets the LPLU D3 state according to the active flag. When
3086 * activating LPLU this function also disables smart speed
3087 * and vice versa. LPLU will not be activated unless the
3088 * device autonegotiation advertisement meets standards of
3089 * either 10 or 10/100 or 10/100/1000 at all duplexes.
3090 * This is a function pointer entry point only called by
3091 * PHY setup routines.
3093 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3095 struct e1000_phy_info *phy = &hw->phy;
3100 phy_ctrl = er32(PHY_CTRL);
3103 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
3104 ew32(PHY_CTRL, phy_ctrl);
3106 if (phy->type != e1000_phy_igp_3)
3109 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
3110 * during Dx states where the power conservation is most
3111 * important. During driver activity we should enable
3112 * SmartSpeed, so performance is maintained.
3114 if (phy->smart_speed == e1000_smart_speed_on) {
3115 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3120 data |= IGP01E1000_PSCFR_SMART_SPEED;
3121 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3125 } else if (phy->smart_speed == e1000_smart_speed_off) {
3126 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3131 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3132 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3137 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
3138 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
3139 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
3140 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
3141 ew32(PHY_CTRL, phy_ctrl);
3143 if (phy->type != e1000_phy_igp_3)
3146 /* Call gig speed drop workaround on LPLU before accessing
3149 if (hw->mac.type == e1000_ich8lan)
3150 e1000e_gig_downshift_workaround_ich8lan(hw);
3152 /* When LPLU is enabled, we should disable SmartSpeed */
3153 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
3157 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3158 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
3165 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
3166 * @hw: pointer to the HW structure
3167 * @bank: pointer to the variable that returns the active bank
3169 * Reads signature byte from the NVM using the flash access registers.
3170 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
3172 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
3175 struct e1000_nvm_info *nvm = &hw->nvm;
3176 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
3177 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
3182 switch (hw->mac.type) {
3189 bank1_offset = nvm->flash_bank_size;
3190 act_offset = E1000_ICH_NVM_SIG_WORD;
3192 /* set bank to 0 in case flash read fails */
3196 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset,
3200 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3201 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3202 E1000_ICH_NVM_SIG_VALUE) {
3208 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset +
3213 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3214 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3215 E1000_ICH_NVM_SIG_VALUE) {
3220 e_dbg("ERROR: No valid NVM bank present\n");
3221 return -E1000_ERR_NVM;
3225 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
3226 E1000_EECD_SEC1VAL_VALID_MASK) {
3227 if (eecd & E1000_EECD_SEC1VAL)
3234 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n");
3237 /* set bank to 0 in case flash read fails */
3241 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
3245 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3246 E1000_ICH_NVM_SIG_VALUE) {
3252 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
3257 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3258 E1000_ICH_NVM_SIG_VALUE) {
3263 e_dbg("ERROR: No valid NVM bank present\n");
3264 return -E1000_ERR_NVM;
3269 * e1000_read_nvm_spt - NVM access for SPT
3270 * @hw: pointer to the HW structure
3271 * @offset: The offset (in bytes) of the word(s) to read.
3272 * @words: Size of data to read in words.
3273 * @data: pointer to the word(s) to read at offset.
3275 * Reads a word(s) from the NVM
3277 static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
3280 struct e1000_nvm_info *nvm = &hw->nvm;
3281 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3289 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3291 e_dbg("nvm parameter(s) out of bounds\n");
3292 ret_val = -E1000_ERR_NVM;
3296 nvm->ops.acquire(hw);
3298 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3300 e_dbg("Could not detect valid bank, assuming bank 0\n");
3304 act_offset = (bank) ? nvm->flash_bank_size : 0;
3305 act_offset += offset;
3309 for (i = 0; i < words; i += 2) {
3310 if (words - i == 1) {
3311 if (dev_spec->shadow_ram[offset + i].modified) {
3313 dev_spec->shadow_ram[offset + i].value;
3315 offset_to_read = act_offset + i -
3316 ((act_offset + i) % 2);
3318 e1000_read_flash_dword_ich8lan(hw,
3323 if ((act_offset + i) % 2 == 0)
3324 data[i] = (u16)(dword & 0xFFFF);
3326 data[i] = (u16)((dword >> 16) & 0xFFFF);
3329 offset_to_read = act_offset + i;
3330 if (!(dev_spec->shadow_ram[offset + i].modified) ||
3331 !(dev_spec->shadow_ram[offset + i + 1].modified)) {
3333 e1000_read_flash_dword_ich8lan(hw,
3339 if (dev_spec->shadow_ram[offset + i].modified)
3341 dev_spec->shadow_ram[offset + i].value;
3343 data[i] = (u16)(dword & 0xFFFF);
3344 if (dev_spec->shadow_ram[offset + i].modified)
3346 dev_spec->shadow_ram[offset + i + 1].value;
3348 data[i + 1] = (u16)(dword >> 16 & 0xFFFF);
3352 nvm->ops.release(hw);
3356 e_dbg("NVM read error: %d\n", ret_val);
3362 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
3363 * @hw: pointer to the HW structure
3364 * @offset: The offset (in bytes) of the word(s) to read.
3365 * @words: Size of data to read in words
3366 * @data: Pointer to the word(s) to read at offset.
3368 * Reads a word(s) from the NVM using the flash access registers.
3370 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3373 struct e1000_nvm_info *nvm = &hw->nvm;
3374 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3380 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3382 e_dbg("nvm parameter(s) out of bounds\n");
3383 ret_val = -E1000_ERR_NVM;
3387 nvm->ops.acquire(hw);
3389 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3391 e_dbg("Could not detect valid bank, assuming bank 0\n");
3395 act_offset = (bank) ? nvm->flash_bank_size : 0;
3396 act_offset += offset;
3399 for (i = 0; i < words; i++) {
3400 if (dev_spec->shadow_ram[offset + i].modified) {
3401 data[i] = dev_spec->shadow_ram[offset + i].value;
3403 ret_val = e1000_read_flash_word_ich8lan(hw,
3412 nvm->ops.release(hw);
3416 e_dbg("NVM read error: %d\n", ret_val);
3422 * e1000_flash_cycle_init_ich8lan - Initialize flash
3423 * @hw: pointer to the HW structure
3425 * This function does initial flash setup so that a new read/write/erase cycle
3428 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3430 union ich8_hws_flash_status hsfsts;
3431 s32 ret_val = -E1000_ERR_NVM;
3433 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3435 /* Check if the flash descriptor is valid */
3436 if (!hsfsts.hsf_status.fldesvalid) {
3437 e_dbg("Flash descriptor invalid. SW Sequencing must be used.\n");
3438 return -E1000_ERR_NVM;
3441 /* Clear FCERR and DAEL in hw status by writing 1 */
3442 hsfsts.hsf_status.flcerr = 1;
3443 hsfsts.hsf_status.dael = 1;
3444 if (hw->mac.type >= e1000_pch_spt)
3445 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF);
3447 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3449 /* Either we should have a hardware SPI cycle in progress
3450 * bit to check against, in order to start a new cycle or
3451 * FDONE bit should be changed in the hardware so that it
3452 * is 1 after hardware reset, which can then be used as an
3453 * indication whether a cycle is in progress or has been
3457 if (!hsfsts.hsf_status.flcinprog) {
3458 /* There is no cycle running at present,
3459 * so we can start a cycle.
3460 * Begin by setting Flash Cycle Done.
3462 hsfsts.hsf_status.flcdone = 1;
3463 if (hw->mac.type >= e1000_pch_spt)
3464 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF);
3466 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3471 /* Otherwise poll for sometime so the current
3472 * cycle has a chance to end before giving up.
3474 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
3475 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3476 if (!hsfsts.hsf_status.flcinprog) {
3483 /* Successful in waiting for previous cycle to timeout,
3484 * now set the Flash Cycle Done.
3486 hsfsts.hsf_status.flcdone = 1;
3487 if (hw->mac.type >= e1000_pch_spt)
3488 ew32flash(ICH_FLASH_HSFSTS,
3489 hsfsts.regval & 0xFFFF);
3491 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3493 e_dbg("Flash controller busy, cannot get access\n");
3501 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3502 * @hw: pointer to the HW structure
3503 * @timeout: maximum time to wait for completion
3505 * This function starts a flash cycle and waits for its completion.
3507 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3509 union ich8_hws_flash_ctrl hsflctl;
3510 union ich8_hws_flash_status hsfsts;
3513 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3514 if (hw->mac.type >= e1000_pch_spt)
3515 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
3517 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3518 hsflctl.hsf_ctrl.flcgo = 1;
3520 if (hw->mac.type >= e1000_pch_spt)
3521 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
3523 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3525 /* wait till FDONE bit is set to 1 */
3527 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3528 if (hsfsts.hsf_status.flcdone)
3531 } while (i++ < timeout);
3533 if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
3536 return -E1000_ERR_NVM;
3540 * e1000_read_flash_dword_ich8lan - Read dword from flash
3541 * @hw: pointer to the HW structure
3542 * @offset: offset to data location
3543 * @data: pointer to the location for storing the data
3545 * Reads the flash dword at offset into data. Offset is converted
3546 * to bytes before read.
3548 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset,
3551 /* Must convert word offset into bytes. */
3553 return e1000_read_flash_data32_ich8lan(hw, offset, data);
3557 * e1000_read_flash_word_ich8lan - Read word from flash
3558 * @hw: pointer to the HW structure
3559 * @offset: offset to data location
3560 * @data: pointer to the location for storing the data
3562 * Reads the flash word at offset into data. Offset is converted
3563 * to bytes before read.
3565 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
3568 /* Must convert offset into bytes. */
3571 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
3575 * e1000_read_flash_byte_ich8lan - Read byte from flash
3576 * @hw: pointer to the HW structure
3577 * @offset: The offset of the byte to read.
3578 * @data: Pointer to a byte to store the value read.
3580 * Reads a single byte from the NVM using the flash access registers.
3582 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3588 /* In SPT, only 32 bits access is supported,
3589 * so this function should not be called.
3591 if (hw->mac.type >= e1000_pch_spt)
3592 return -E1000_ERR_NVM;
3594 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3605 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
3606 * @hw: pointer to the HW structure
3607 * @offset: The offset (in bytes) of the byte or word to read.
3608 * @size: Size of data to read, 1=byte 2=word
3609 * @data: Pointer to the word to store the value read.
3611 * Reads a byte or word from the NVM using the flash access registers.
3613 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3616 union ich8_hws_flash_status hsfsts;
3617 union ich8_hws_flash_ctrl hsflctl;
3618 u32 flash_linear_addr;
3620 s32 ret_val = -E1000_ERR_NVM;
3623 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3624 return -E1000_ERR_NVM;
3626 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3627 hw->nvm.flash_base_addr);
3632 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3636 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3637 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3638 hsflctl.hsf_ctrl.fldbcount = size - 1;
3639 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3640 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3642 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3645 e1000_flash_cycle_ich8lan(hw,
3646 ICH_FLASH_READ_COMMAND_TIMEOUT);
3648 /* Check if FCERR is set to 1, if set to 1, clear it
3649 * and try the whole sequence a few more times, else
3650 * read in (shift in) the Flash Data0, the order is
3651 * least significant byte first msb to lsb
3654 flash_data = er32flash(ICH_FLASH_FDATA0);
3656 *data = (u8)(flash_data & 0x000000FF);
3658 *data = (u16)(flash_data & 0x0000FFFF);
3661 /* If we've gotten here, then things are probably
3662 * completely hosed, but if the error condition is
3663 * detected, it won't hurt to give it another try...
3664 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3666 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3667 if (hsfsts.hsf_status.flcerr) {
3668 /* Repeat for some time before giving up. */
3670 } else if (!hsfsts.hsf_status.flcdone) {
3671 e_dbg("Timeout error - flash cycle did not complete.\n");
3675 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3681 * e1000_read_flash_data32_ich8lan - Read dword from NVM
3682 * @hw: pointer to the HW structure
3683 * @offset: The offset (in bytes) of the dword to read.
3684 * @data: Pointer to the dword to store the value read.
3686 * Reads a byte or word from the NVM using the flash access registers.
3689 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
3692 union ich8_hws_flash_status hsfsts;
3693 union ich8_hws_flash_ctrl hsflctl;
3694 u32 flash_linear_addr;
3695 s32 ret_val = -E1000_ERR_NVM;
3698 if (offset > ICH_FLASH_LINEAR_ADDR_MASK || hw->mac.type < e1000_pch_spt)
3699 return -E1000_ERR_NVM;
3700 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3701 hw->nvm.flash_base_addr);
3706 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3709 /* In SPT, This register is in Lan memory space, not flash.
3710 * Therefore, only 32 bit access is supported
3712 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
3714 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3715 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
3716 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3717 /* In SPT, This register is in Lan memory space, not flash.
3718 * Therefore, only 32 bit access is supported
3720 ew32flash(ICH_FLASH_HSFSTS, (u32)hsflctl.regval << 16);
3721 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3724 e1000_flash_cycle_ich8lan(hw,
3725 ICH_FLASH_READ_COMMAND_TIMEOUT);
3727 /* Check if FCERR is set to 1, if set to 1, clear it
3728 * and try the whole sequence a few more times, else
3729 * read in (shift in) the Flash Data0, the order is
3730 * least significant byte first msb to lsb
3733 *data = er32flash(ICH_FLASH_FDATA0);
3736 /* If we've gotten here, then things are probably
3737 * completely hosed, but if the error condition is
3738 * detected, it won't hurt to give it another try...
3739 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3741 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3742 if (hsfsts.hsf_status.flcerr) {
3743 /* Repeat for some time before giving up. */
3745 } else if (!hsfsts.hsf_status.flcdone) {
3746 e_dbg("Timeout error - flash cycle did not complete.\n");
3750 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3756 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
3757 * @hw: pointer to the HW structure
3758 * @offset: The offset (in bytes) of the word(s) to write.
3759 * @words: Size of data to write in words
3760 * @data: Pointer to the word(s) to write at offset.
3762 * Writes a byte or word to the NVM using the flash access registers.
3764 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3767 struct e1000_nvm_info *nvm = &hw->nvm;
3768 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3771 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3773 e_dbg("nvm parameter(s) out of bounds\n");
3774 return -E1000_ERR_NVM;
3777 nvm->ops.acquire(hw);
3779 for (i = 0; i < words; i++) {
3780 dev_spec->shadow_ram[offset + i].modified = true;
3781 dev_spec->shadow_ram[offset + i].value = data[i];
3784 nvm->ops.release(hw);
3790 * e1000_update_nvm_checksum_spt - Update the checksum for NVM
3791 * @hw: pointer to the HW structure
3793 * The NVM checksum is updated by calling the generic update_nvm_checksum,
3794 * which writes the checksum to the shadow ram. The changes in the shadow
3795 * ram are then committed to the EEPROM by processing each bank at a time
3796 * checking for the modified bit and writing only the pending changes.
3797 * After a successful commit, the shadow ram is cleared and is ready for
3800 static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw)
3802 struct e1000_nvm_info *nvm = &hw->nvm;
3803 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3804 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3808 ret_val = e1000e_update_nvm_checksum_generic(hw);
3812 if (nvm->type != e1000_nvm_flash_sw)
3815 nvm->ops.acquire(hw);
3817 /* We're writing to the opposite bank so if we're on bank 1,
3818 * write to bank 0 etc. We also need to erase the segment that
3819 * is going to be written
3821 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3823 e_dbg("Could not detect valid bank, assuming bank 0\n");
3828 new_bank_offset = nvm->flash_bank_size;
3829 old_bank_offset = 0;
3830 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3834 old_bank_offset = nvm->flash_bank_size;
3835 new_bank_offset = 0;
3836 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3840 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i += 2) {
3841 /* Determine whether to write the value stored
3842 * in the other NVM bank or a modified value stored
3845 ret_val = e1000_read_flash_dword_ich8lan(hw,
3846 i + old_bank_offset,
3849 if (dev_spec->shadow_ram[i].modified) {
3850 dword &= 0xffff0000;
3851 dword |= (dev_spec->shadow_ram[i].value & 0xffff);
3853 if (dev_spec->shadow_ram[i + 1].modified) {
3854 dword &= 0x0000ffff;
3855 dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff)
3861 /* If the word is 0x13, then make sure the signature bits
3862 * (15:14) are 11b until the commit has completed.
3863 * This will allow us to write 10b which indicates the
3864 * signature is valid. We want to do this after the write
3865 * has completed so that we don't mark the segment valid
3866 * while the write is still in progress
3868 if (i == E1000_ICH_NVM_SIG_WORD - 1)
3869 dword |= E1000_ICH_NVM_SIG_MASK << 16;
3871 /* Convert offset to bytes. */
3872 act_offset = (i + new_bank_offset) << 1;
3874 usleep_range(100, 200);
3876 /* Write the data to the new bank. Offset in words */
3877 act_offset = i + new_bank_offset;
3878 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset,
3884 /* Don't bother writing the segment valid bits if sector
3885 * programming failed.
3888 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
3889 e_dbg("Flash commit failed.\n");
3893 /* Finally validate the new segment by setting bit 15:14
3894 * to 10b in word 0x13 , this can be done without an
3895 * erase as well since these bits are 11 to start with
3896 * and we need to change bit 14 to 0b
3898 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
3900 /*offset in words but we read dword */
3902 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
3907 dword &= 0xBFFFFFFF;
3908 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
3913 /* offset in words but we read dword */
3914 act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1;
3915 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
3920 dword &= 0x00FFFFFF;
3921 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
3926 /* Great! Everything worked, we can now clear the cached entries. */
3927 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
3928 dev_spec->shadow_ram[i].modified = false;
3929 dev_spec->shadow_ram[i].value = 0xFFFF;
3933 nvm->ops.release(hw);
3935 /* Reload the EEPROM, or else modifications will not appear
3936 * until after the next adapter reset.
3939 nvm->ops.reload(hw);
3940 usleep_range(10000, 11000);
3945 e_dbg("NVM update error: %d\n", ret_val);
3951 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
3952 * @hw: pointer to the HW structure
3954 * The NVM checksum is updated by calling the generic update_nvm_checksum,
3955 * which writes the checksum to the shadow ram. The changes in the shadow
3956 * ram are then committed to the EEPROM by processing each bank at a time
3957 * checking for the modified bit and writing only the pending changes.
3958 * After a successful commit, the shadow ram is cleared and is ready for
3961 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
3963 struct e1000_nvm_info *nvm = &hw->nvm;
3964 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3965 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3969 ret_val = e1000e_update_nvm_checksum_generic(hw);
3973 if (nvm->type != e1000_nvm_flash_sw)
3976 nvm->ops.acquire(hw);
3978 /* We're writing to the opposite bank so if we're on bank 1,
3979 * write to bank 0 etc. We also need to erase the segment that
3980 * is going to be written
3982 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3984 e_dbg("Could not detect valid bank, assuming bank 0\n");
3989 new_bank_offset = nvm->flash_bank_size;
3990 old_bank_offset = 0;
3991 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3995 old_bank_offset = nvm->flash_bank_size;
3996 new_bank_offset = 0;
3997 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
4001 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
4002 if (dev_spec->shadow_ram[i].modified) {
4003 data = dev_spec->shadow_ram[i].value;
4005 ret_val = e1000_read_flash_word_ich8lan(hw, i +
4012 /* If the word is 0x13, then make sure the signature bits
4013 * (15:14) are 11b until the commit has completed.
4014 * This will allow us to write 10b which indicates the
4015 * signature is valid. We want to do this after the write
4016 * has completed so that we don't mark the segment valid
4017 * while the write is still in progress
4019 if (i == E1000_ICH_NVM_SIG_WORD)
4020 data |= E1000_ICH_NVM_SIG_MASK;
4022 /* Convert offset to bytes. */
4023 act_offset = (i + new_bank_offset) << 1;
4025 usleep_range(100, 200);
4026 /* Write the bytes to the new bank. */
4027 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4033 usleep_range(100, 200);
4034 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4041 /* Don't bother writing the segment valid bits if sector
4042 * programming failed.
4045 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
4046 e_dbg("Flash commit failed.\n");
4050 /* Finally validate the new segment by setting bit 15:14
4051 * to 10b in word 0x13 , this can be done without an
4052 * erase as well since these bits are 11 to start with
4053 * and we need to change bit 14 to 0b
4055 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
4056 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
4061 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4067 /* And invalidate the previously valid segment by setting
4068 * its signature word (0x13) high_byte to 0b. This can be
4069 * done without an erase because flash erase sets all bits
4070 * to 1's. We can write 1's to 0's without an erase
4072 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
4073 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
4077 /* Great! Everything worked, we can now clear the cached entries. */
4078 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
4079 dev_spec->shadow_ram[i].modified = false;
4080 dev_spec->shadow_ram[i].value = 0xFFFF;
4084 nvm->ops.release(hw);
4086 /* Reload the EEPROM, or else modifications will not appear
4087 * until after the next adapter reset.
4090 nvm->ops.reload(hw);
4091 usleep_range(10000, 11000);
4096 e_dbg("NVM update error: %d\n", ret_val);
4102 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
4103 * @hw: pointer to the HW structure
4105 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
4106 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
4107 * calculated, in which case we need to calculate the checksum and set bit 6.
4109 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
4114 u16 valid_csum_mask;
4116 /* Read NVM and check Invalid Image CSUM bit. If this bit is 0,
4117 * the checksum needs to be fixed. This bit is an indication that
4118 * the NVM was prepared by OEM software and did not calculate
4119 * the checksum...a likely scenario.
4121 switch (hw->mac.type) {
4130 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
4133 word = NVM_FUTURE_INIT_WORD1;
4134 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
4138 ret_val = e1000_read_nvm(hw, word, 1, &data);
4142 if (!(data & valid_csum_mask)) {
4143 e_dbg("NVM Checksum valid bit not set\n");
4145 if (hw->mac.type < e1000_pch_tgp) {
4146 data |= valid_csum_mask;
4147 ret_val = e1000_write_nvm(hw, word, 1, &data);
4150 ret_val = e1000e_update_nvm_checksum(hw);
4156 return e1000e_validate_nvm_checksum_generic(hw);
4160 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
4161 * @hw: pointer to the HW structure
4163 * To prevent malicious write/erase of the NVM, set it to be read-only
4164 * so that the hardware ignores all write/erase cycles of the NVM via
4165 * the flash control registers. The shadow-ram copy of the NVM will
4166 * still be updated, however any updates to this copy will not stick
4167 * across driver reloads.
4169 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
4171 struct e1000_nvm_info *nvm = &hw->nvm;
4172 union ich8_flash_protected_range pr0;
4173 union ich8_hws_flash_status hsfsts;
4176 nvm->ops.acquire(hw);
4178 gfpreg = er32flash(ICH_FLASH_GFPREG);
4180 /* Write-protect GbE Sector of NVM */
4181 pr0.regval = er32flash(ICH_FLASH_PR0);
4182 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
4183 pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
4184 pr0.range.wpe = true;
4185 ew32flash(ICH_FLASH_PR0, pr0.regval);
4187 /* Lock down a subset of GbE Flash Control Registers, e.g.
4188 * PR0 to prevent the write-protection from being lifted.
4189 * Once FLOCKDN is set, the registers protected by it cannot
4190 * be written until FLOCKDN is cleared by a hardware reset.
4192 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4193 hsfsts.hsf_status.flockdn = true;
4194 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
4196 nvm->ops.release(hw);
4200 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
4201 * @hw: pointer to the HW structure
4202 * @offset: The offset (in bytes) of the byte/word to read.
4203 * @size: Size of data to read, 1=byte 2=word
4204 * @data: The byte(s) to write to the NVM.
4206 * Writes one/two bytes to the NVM using the flash access registers.
4208 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
4211 union ich8_hws_flash_status hsfsts;
4212 union ich8_hws_flash_ctrl hsflctl;
4213 u32 flash_linear_addr;
4218 if (hw->mac.type >= e1000_pch_spt) {
4219 if (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4220 return -E1000_ERR_NVM;
4222 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4223 return -E1000_ERR_NVM;
4226 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4227 hw->nvm.flash_base_addr);
4232 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4235 /* In SPT, This register is in Lan memory space, not
4236 * flash. Therefore, only 32 bit access is supported
4238 if (hw->mac.type >= e1000_pch_spt)
4239 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
4241 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4243 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
4244 hsflctl.hsf_ctrl.fldbcount = size - 1;
4245 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4246 /* In SPT, This register is in Lan memory space,
4247 * not flash. Therefore, only 32 bit access is
4250 if (hw->mac.type >= e1000_pch_spt)
4251 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
4253 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4255 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4258 flash_data = (u32)data & 0x00FF;
4260 flash_data = (u32)data;
4262 ew32flash(ICH_FLASH_FDATA0, flash_data);
4264 /* check if FCERR is set to 1 , if set to 1, clear it
4265 * and try the whole sequence a few more times else done
4268 e1000_flash_cycle_ich8lan(hw,
4269 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4273 /* If we're here, then things are most likely
4274 * completely hosed, but if the error condition
4275 * is detected, it won't hurt to give it another
4276 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4278 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4279 if (hsfsts.hsf_status.flcerr)
4280 /* Repeat for some time before giving up. */
4282 if (!hsfsts.hsf_status.flcdone) {
4283 e_dbg("Timeout error - flash cycle did not complete.\n");
4286 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4292 * e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM
4293 * @hw: pointer to the HW structure
4294 * @offset: The offset (in bytes) of the dwords to read.
4295 * @data: The 4 bytes to write to the NVM.
4297 * Writes one/two/four bytes to the NVM using the flash access registers.
4299 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
4302 union ich8_hws_flash_status hsfsts;
4303 union ich8_hws_flash_ctrl hsflctl;
4304 u32 flash_linear_addr;
4308 if (hw->mac.type >= e1000_pch_spt) {
4309 if (offset > ICH_FLASH_LINEAR_ADDR_MASK)
4310 return -E1000_ERR_NVM;
4312 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4313 hw->nvm.flash_base_addr);
4317 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4321 /* In SPT, This register is in Lan memory space, not
4322 * flash. Therefore, only 32 bit access is supported
4324 if (hw->mac.type >= e1000_pch_spt)
4325 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS)
4328 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4330 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
4331 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4333 /* In SPT, This register is in Lan memory space,
4334 * not flash. Therefore, only 32 bit access is
4337 if (hw->mac.type >= e1000_pch_spt)
4338 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
4340 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4342 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4344 ew32flash(ICH_FLASH_FDATA0, data);
4346 /* check if FCERR is set to 1 , if set to 1, clear it
4347 * and try the whole sequence a few more times else done
4350 e1000_flash_cycle_ich8lan(hw,
4351 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4356 /* If we're here, then things are most likely
4357 * completely hosed, but if the error condition
4358 * is detected, it won't hurt to give it another
4359 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4361 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4363 if (hsfsts.hsf_status.flcerr)
4364 /* Repeat for some time before giving up. */
4366 if (!hsfsts.hsf_status.flcdone) {
4367 e_dbg("Timeout error - flash cycle did not complete.\n");
4370 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4376 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
4377 * @hw: pointer to the HW structure
4378 * @offset: The index of the byte to read.
4379 * @data: The byte to write to the NVM.
4381 * Writes a single byte to the NVM using the flash access registers.
4383 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
4386 u16 word = (u16)data;
4388 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
4392 * e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM
4393 * @hw: pointer to the HW structure
4394 * @offset: The offset of the word to write.
4395 * @dword: The dword to write to the NVM.
4397 * Writes a single dword to the NVM using the flash access registers.
4398 * Goes through a retry algorithm before giving up.
4400 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
4401 u32 offset, u32 dword)
4404 u16 program_retries;
4406 /* Must convert word offset into bytes. */
4408 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4412 for (program_retries = 0; program_retries < 100; program_retries++) {
4413 e_dbg("Retrying Byte %8.8X at offset %u\n", dword, offset);
4414 usleep_range(100, 200);
4415 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4419 if (program_retries == 100)
4420 return -E1000_ERR_NVM;
4426 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
4427 * @hw: pointer to the HW structure
4428 * @offset: The offset of the byte to write.
4429 * @byte: The byte to write to the NVM.
4431 * Writes a single byte to the NVM using the flash access registers.
4432 * Goes through a retry algorithm before giving up.
4434 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
4435 u32 offset, u8 byte)
4438 u16 program_retries;
4440 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4444 for (program_retries = 0; program_retries < 100; program_retries++) {
4445 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
4446 usleep_range(100, 200);
4447 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4451 if (program_retries == 100)
4452 return -E1000_ERR_NVM;
4458 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
4459 * @hw: pointer to the HW structure
4460 * @bank: 0 for first bank, 1 for second bank, etc.
4462 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
4463 * bank N is 4096 * N + flash_reg_addr.
4465 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
4467 struct e1000_nvm_info *nvm = &hw->nvm;
4468 union ich8_hws_flash_status hsfsts;
4469 union ich8_hws_flash_ctrl hsflctl;
4470 u32 flash_linear_addr;
4471 /* bank size is in 16bit words - adjust to bytes */
4472 u32 flash_bank_size = nvm->flash_bank_size * 2;
4475 s32 j, iteration, sector_size;
4477 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4479 /* Determine HW Sector size: Read BERASE bits of hw flash status
4481 * 00: The Hw sector is 256 bytes, hence we need to erase 16
4482 * consecutive sectors. The start index for the nth Hw sector
4483 * can be calculated as = bank * 4096 + n * 256
4484 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
4485 * The start index for the nth Hw sector can be calculated
4487 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
4488 * (ich9 only, otherwise error condition)
4489 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
4491 switch (hsfsts.hsf_status.berasesz) {
4493 /* Hw sector size 256 */
4494 sector_size = ICH_FLASH_SEG_SIZE_256;
4495 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
4498 sector_size = ICH_FLASH_SEG_SIZE_4K;
4502 sector_size = ICH_FLASH_SEG_SIZE_8K;
4506 sector_size = ICH_FLASH_SEG_SIZE_64K;
4510 return -E1000_ERR_NVM;
4513 /* Start with the base address, then add the sector offset. */
4514 flash_linear_addr = hw->nvm.flash_base_addr;
4515 flash_linear_addr += (bank) ? flash_bank_size : 0;
4517 for (j = 0; j < iteration; j++) {
4519 u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
4522 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4526 /* Write a value 11 (block Erase) in Flash
4527 * Cycle field in hw flash control
4529 if (hw->mac.type >= e1000_pch_spt)
4531 er32flash(ICH_FLASH_HSFSTS) >> 16;
4533 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4535 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
4536 if (hw->mac.type >= e1000_pch_spt)
4537 ew32flash(ICH_FLASH_HSFSTS,
4538 hsflctl.regval << 16);
4540 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4542 /* Write the last 24 bits of an index within the
4543 * block into Flash Linear address field in Flash
4546 flash_linear_addr += (j * sector_size);
4547 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4549 ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
4553 /* Check if FCERR is set to 1. If 1,
4554 * clear it and try the whole sequence
4555 * a few more times else Done
4557 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4558 if (hsfsts.hsf_status.flcerr)
4559 /* repeat for some time before giving up */
4561 else if (!hsfsts.hsf_status.flcdone)
4563 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
4570 * e1000_valid_led_default_ich8lan - Set the default LED settings
4571 * @hw: pointer to the HW structure
4572 * @data: Pointer to the LED settings
4574 * Reads the LED default settings from the NVM to data. If the NVM LED
4575 * settings is all 0's or F's, set the LED default to a valid LED default
4578 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
4582 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
4584 e_dbg("NVM Read Error\n");
4588 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
4589 *data = ID_LED_DEFAULT_ICH8LAN;
4595 * e1000_id_led_init_pchlan - store LED configurations
4596 * @hw: pointer to the HW structure
4598 * PCH does not control LEDs via the LEDCTL register, rather it uses
4599 * the PHY LED configuration register.
4601 * PCH also does not have an "always on" or "always off" mode which
4602 * complicates the ID feature. Instead of using the "on" mode to indicate
4603 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()),
4604 * use "link_up" mode. The LEDs will still ID on request if there is no
4605 * link based on logic in e1000_led_[on|off]_pchlan().
4607 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
4609 struct e1000_mac_info *mac = &hw->mac;
4611 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
4612 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
4613 u16 data, i, temp, shift;
4615 /* Get default ID LED modes */
4616 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
4620 mac->ledctl_default = er32(LEDCTL);
4621 mac->ledctl_mode1 = mac->ledctl_default;
4622 mac->ledctl_mode2 = mac->ledctl_default;
4624 for (i = 0; i < 4; i++) {
4625 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
4628 case ID_LED_ON1_DEF2:
4629 case ID_LED_ON1_ON2:
4630 case ID_LED_ON1_OFF2:
4631 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4632 mac->ledctl_mode1 |= (ledctl_on << shift);
4634 case ID_LED_OFF1_DEF2:
4635 case ID_LED_OFF1_ON2:
4636 case ID_LED_OFF1_OFF2:
4637 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4638 mac->ledctl_mode1 |= (ledctl_off << shift);
4645 case ID_LED_DEF1_ON2:
4646 case ID_LED_ON1_ON2:
4647 case ID_LED_OFF1_ON2:
4648 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4649 mac->ledctl_mode2 |= (ledctl_on << shift);
4651 case ID_LED_DEF1_OFF2:
4652 case ID_LED_ON1_OFF2:
4653 case ID_LED_OFF1_OFF2:
4654 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4655 mac->ledctl_mode2 |= (ledctl_off << shift);
4667 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
4668 * @hw: pointer to the HW structure
4670 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
4671 * register, so the bus width is hard coded.
4673 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
4675 struct e1000_bus_info *bus = &hw->bus;
4678 ret_val = e1000e_get_bus_info_pcie(hw);
4680 /* ICH devices are "PCI Express"-ish. They have
4681 * a configuration space, but do not contain
4682 * PCI Express Capability registers, so bus width
4683 * must be hardcoded.
4685 if (bus->width == e1000_bus_width_unknown)
4686 bus->width = e1000_bus_width_pcie_x1;
4692 * e1000_reset_hw_ich8lan - Reset the hardware
4693 * @hw: pointer to the HW structure
4695 * Does a full reset of the hardware which includes a reset of the PHY and
4698 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
4700 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4705 /* Prevent the PCI-E bus from sticking if there is no TLP connection
4706 * on the last TLP read/write transaction when MAC is reset.
4708 ret_val = e1000e_disable_pcie_master(hw);
4710 e_dbg("PCI-E Master disable polling has failed.\n");
4712 e_dbg("Masking off all interrupts\n");
4713 ew32(IMC, 0xffffffff);
4715 /* Disable the Transmit and Receive units. Then delay to allow
4716 * any pending transactions to complete before we hit the MAC
4717 * with the global reset.
4720 ew32(TCTL, E1000_TCTL_PSP);
4723 usleep_range(10000, 11000);
4725 /* Workaround for ICH8 bit corruption issue in FIFO memory */
4726 if (hw->mac.type == e1000_ich8lan) {
4727 /* Set Tx and Rx buffer allocation to 8k apiece. */
4728 ew32(PBA, E1000_PBA_8K);
4729 /* Set Packet Buffer Size to 16k. */
4730 ew32(PBS, E1000_PBS_16K);
4733 if (hw->mac.type == e1000_pchlan) {
4734 /* Save the NVM K1 bit setting */
4735 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
4739 if (kum_cfg & E1000_NVM_K1_ENABLE)
4740 dev_spec->nvm_k1_enabled = true;
4742 dev_spec->nvm_k1_enabled = false;
4747 if (!hw->phy.ops.check_reset_block(hw)) {
4748 /* Full-chip reset requires MAC and PHY reset at the same
4749 * time to make sure the interface between MAC and the
4750 * external PHY is reset.
4752 ctrl |= E1000_CTRL_PHY_RST;
4754 /* Gate automatic PHY configuration by hardware on
4757 if ((hw->mac.type == e1000_pch2lan) &&
4758 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
4759 e1000_gate_hw_phy_config_ich8lan(hw, true);
4761 ret_val = e1000_acquire_swflag_ich8lan(hw);
4762 e_dbg("Issuing a global reset to ich8lan\n");
4763 ew32(CTRL, (ctrl | E1000_CTRL_RST));
4764 /* cannot issue a flush here because it hangs the hardware */
4767 /* Set Phy Config Counter to 50msec */
4768 if (hw->mac.type == e1000_pch2lan) {
4769 reg = er32(FEXTNVM3);
4770 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
4771 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
4772 ew32(FEXTNVM3, reg);
4776 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
4778 if (ctrl & E1000_CTRL_PHY_RST) {
4779 ret_val = hw->phy.ops.get_cfg_done(hw);
4783 ret_val = e1000_post_phy_reset_ich8lan(hw);
4788 /* For PCH, this write will make sure that any noise
4789 * will be detected as a CRC error and be dropped rather than show up
4790 * as a bad packet to the DMA engine.
4792 if (hw->mac.type == e1000_pchlan)
4793 ew32(CRC_OFFSET, 0x65656565);
4795 ew32(IMC, 0xffffffff);
4798 reg = er32(KABGTXD);
4799 reg |= E1000_KABGTXD_BGSQLBIAS;
4806 * e1000_init_hw_ich8lan - Initialize the hardware
4807 * @hw: pointer to the HW structure
4809 * Prepares the hardware for transmit and receive by doing the following:
4810 * - initialize hardware bits
4811 * - initialize LED identification
4812 * - setup receive address registers
4813 * - setup flow control
4814 * - setup transmit descriptors
4815 * - clear statistics
4817 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
4819 struct e1000_mac_info *mac = &hw->mac;
4820 u32 ctrl_ext, txdctl, snoop, fflt_dbg;
4824 e1000_initialize_hw_bits_ich8lan(hw);
4826 /* Initialize identification LED */
4827 ret_val = mac->ops.id_led_init(hw);
4828 /* An error is not fatal and we should not stop init due to this */
4830 e_dbg("Error initializing identification LED\n");
4832 /* Setup the receive address. */
4833 e1000e_init_rx_addrs(hw, mac->rar_entry_count);
4835 /* Zero out the Multicast HASH table */
4836 e_dbg("Zeroing the MTA\n");
4837 for (i = 0; i < mac->mta_reg_count; i++)
4838 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
4840 /* The 82578 Rx buffer will stall if wakeup is enabled in host and
4841 * the ME. Disable wakeup by clearing the host wakeup bit.
4842 * Reset the phy after disabling host wakeup to reset the Rx buffer.
4844 if (hw->phy.type == e1000_phy_82578) {
4845 e1e_rphy(hw, BM_PORT_GEN_CFG, &i);
4846 i &= ~BM_WUC_HOST_WU_BIT;
4847 e1e_wphy(hw, BM_PORT_GEN_CFG, i);
4848 ret_val = e1000_phy_hw_reset_ich8lan(hw);
4853 /* Setup link and flow control */
4854 ret_val = mac->ops.setup_link(hw);
4856 /* Set the transmit descriptor write-back policy for both queues */
4857 txdctl = er32(TXDCTL(0));
4858 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4859 E1000_TXDCTL_FULL_TX_DESC_WB);
4860 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4861 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4862 ew32(TXDCTL(0), txdctl);
4863 txdctl = er32(TXDCTL(1));
4864 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4865 E1000_TXDCTL_FULL_TX_DESC_WB);
4866 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4867 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4868 ew32(TXDCTL(1), txdctl);
4870 /* ICH8 has opposite polarity of no_snoop bits.
4871 * By default, we should use snoop behavior.
4873 if (mac->type == e1000_ich8lan)
4874 snoop = PCIE_ICH8_SNOOP_ALL;
4876 snoop = (u32)~(PCIE_NO_SNOOP_ALL);
4877 e1000e_set_pcie_no_snoop(hw, snoop);
4879 /* Enable workaround for packet loss issue on TGP PCH
4880 * Do not gate DMA clock from the modPHY block
4882 if (mac->type >= e1000_pch_tgp) {
4883 fflt_dbg = er32(FFLT_DBG);
4884 fflt_dbg |= E1000_FFLT_DBG_DONT_GATE_WAKE_DMA_CLK;
4885 ew32(FFLT_DBG, fflt_dbg);
4888 ctrl_ext = er32(CTRL_EXT);
4889 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
4890 ew32(CTRL_EXT, ctrl_ext);
4892 /* Clear all of the statistics registers (clear on read). It is
4893 * important that we do this after we have tried to establish link
4894 * because the symbol error count will increment wildly if there
4897 e1000_clear_hw_cntrs_ich8lan(hw);
4903 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
4904 * @hw: pointer to the HW structure
4906 * Sets/Clears required hardware bits necessary for correctly setting up the
4907 * hardware for transmit and receive.
4909 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
4913 /* Extended Device Control */
4914 reg = er32(CTRL_EXT);
4916 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
4917 if (hw->mac.type >= e1000_pchlan)
4918 reg |= E1000_CTRL_EXT_PHYPDEN;
4919 ew32(CTRL_EXT, reg);
4921 /* Transmit Descriptor Control 0 */
4922 reg = er32(TXDCTL(0));
4924 ew32(TXDCTL(0), reg);
4926 /* Transmit Descriptor Control 1 */
4927 reg = er32(TXDCTL(1));
4929 ew32(TXDCTL(1), reg);
4931 /* Transmit Arbitration Control 0 */
4932 reg = er32(TARC(0));
4933 if (hw->mac.type == e1000_ich8lan)
4934 reg |= BIT(28) | BIT(29);
4935 reg |= BIT(23) | BIT(24) | BIT(26) | BIT(27);
4938 /* Transmit Arbitration Control 1 */
4939 reg = er32(TARC(1));
4940 if (er32(TCTL) & E1000_TCTL_MULR)
4944 reg |= BIT(24) | BIT(26) | BIT(30);
4948 if (hw->mac.type == e1000_ich8lan) {
4954 /* work-around descriptor data corruption issue during nfs v2 udp
4955 * traffic, just disable the nfs filtering capability
4958 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
4960 /* Disable IPv6 extension header parsing because some malformed
4961 * IPv6 headers can hang the Rx.
4963 if (hw->mac.type == e1000_ich8lan)
4964 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
4967 /* Enable ECC on Lynxpoint */
4968 if (hw->mac.type >= e1000_pch_lpt) {
4969 reg = er32(PBECCSTS);
4970 reg |= E1000_PBECCSTS_ECC_ENABLE;
4971 ew32(PBECCSTS, reg);
4974 reg |= E1000_CTRL_MEHE;
4980 * e1000_setup_link_ich8lan - Setup flow control and link settings
4981 * @hw: pointer to the HW structure
4983 * Determines which flow control settings to use, then configures flow
4984 * control. Calls the appropriate media-specific link configuration
4985 * function. Assuming the adapter has a valid link partner, a valid link
4986 * should be established. Assumes the hardware has previously been reset
4987 * and the transmitter and receiver are not enabled.
4989 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
4993 if (hw->phy.ops.check_reset_block(hw))
4996 /* ICH parts do not have a word in the NVM to determine
4997 * the default flow control setting, so we explicitly
5000 if (hw->fc.requested_mode == e1000_fc_default) {
5001 /* Workaround h/w hang when Tx flow control enabled */
5002 if (hw->mac.type == e1000_pchlan)
5003 hw->fc.requested_mode = e1000_fc_rx_pause;
5005 hw->fc.requested_mode = e1000_fc_full;
5008 /* Save off the requested flow control mode for use later. Depending
5009 * on the link partner's capabilities, we may or may not use this mode.
5011 hw->fc.current_mode = hw->fc.requested_mode;
5013 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);
5015 /* Continue to configure the copper link. */
5016 ret_val = hw->mac.ops.setup_physical_interface(hw);
5020 ew32(FCTTV, hw->fc.pause_time);
5021 if ((hw->phy.type == e1000_phy_82578) ||
5022 (hw->phy.type == e1000_phy_82579) ||
5023 (hw->phy.type == e1000_phy_i217) ||
5024 (hw->phy.type == e1000_phy_82577)) {
5025 ew32(FCRTV_PCH, hw->fc.refresh_time);
5027 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
5033 return e1000e_set_fc_watermarks(hw);
5037 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
5038 * @hw: pointer to the HW structure
5040 * Configures the kumeran interface to the PHY to wait the appropriate time
5041 * when polling the PHY, then call the generic setup_copper_link to finish
5042 * configuring the copper link.
5044 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
5051 ctrl |= E1000_CTRL_SLU;
5052 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5055 /* Set the mac to wait the maximum time between each iteration
5056 * and increase the max iterations when polling the phy;
5057 * this fixes erroneous timeouts at 10Mbps.
5059 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
5062 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
5067 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
5072 switch (hw->phy.type) {
5073 case e1000_phy_igp_3:
5074 ret_val = e1000e_copper_link_setup_igp(hw);
5079 case e1000_phy_82578:
5080 ret_val = e1000e_copper_link_setup_m88(hw);
5084 case e1000_phy_82577:
5085 case e1000_phy_82579:
5086 ret_val = e1000_copper_link_setup_82577(hw);
5091 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, ®_data);
5095 reg_data &= ~IFE_PMC_AUTO_MDIX;
5097 switch (hw->phy.mdix) {
5099 reg_data &= ~IFE_PMC_FORCE_MDIX;
5102 reg_data |= IFE_PMC_FORCE_MDIX;
5106 reg_data |= IFE_PMC_AUTO_MDIX;
5109 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
5117 return e1000e_setup_copper_link(hw);
5121 * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
5122 * @hw: pointer to the HW structure
5124 * Calls the PHY specific link setup function and then calls the
5125 * generic setup_copper_link to finish configuring the link for
5126 * Lynxpoint PCH devices
5128 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
5134 ctrl |= E1000_CTRL_SLU;
5135 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5138 ret_val = e1000_copper_link_setup_82577(hw);
5142 return e1000e_setup_copper_link(hw);
5146 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
5147 * @hw: pointer to the HW structure
5148 * @speed: pointer to store current link speed
5149 * @duplex: pointer to store the current link duplex
5151 * Calls the generic get_speed_and_duplex to retrieve the current link
5152 * information and then calls the Kumeran lock loss workaround for links at
5155 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
5160 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
5164 if ((hw->mac.type == e1000_ich8lan) &&
5165 (hw->phy.type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
5166 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
5173 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
5174 * @hw: pointer to the HW structure
5176 * Work-around for 82566 Kumeran PCS lock loss:
5177 * On link status change (i.e. PCI reset, speed change) and link is up and
5179 * 0) if workaround is optionally disabled do nothing
5180 * 1) wait 1ms for Kumeran link to come up
5181 * 2) check Kumeran Diagnostic register PCS lock loss bit
5182 * 3) if not set the link is locked (all is good), otherwise...
5184 * 5) repeat up to 10 times
5185 * Note: this is only called for IGP3 copper when speed is 1gb.
5187 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
5189 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5195 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
5198 /* Make sure link is up before proceeding. If not just return.
5199 * Attempting this while link is negotiating fouled up link
5202 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
5206 for (i = 0; i < 10; i++) {
5207 /* read once to clear */
5208 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
5211 /* and again to get new status */
5212 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
5216 /* check for PCS lock */
5217 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
5220 /* Issue PHY reset */
5221 e1000_phy_hw_reset(hw);
5224 /* Disable GigE link negotiation */
5225 phy_ctrl = er32(PHY_CTRL);
5226 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
5227 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5228 ew32(PHY_CTRL, phy_ctrl);
5230 /* Call gig speed drop workaround on Gig disable before accessing
5233 e1000e_gig_downshift_workaround_ich8lan(hw);
5235 /* unable to acquire PCS lock */
5236 return -E1000_ERR_PHY;
5240 * e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
5241 * @hw: pointer to the HW structure
5242 * @state: boolean value used to set the current Kumeran workaround state
5244 * If ICH8, set the current Kumeran workaround state (enabled - true
5245 * /disabled - false).
5247 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
5250 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5252 if (hw->mac.type != e1000_ich8lan) {
5253 e_dbg("Workaround applies to ICH8 only.\n");
5257 dev_spec->kmrn_lock_loss_workaround_enabled = state;
5261 * e1000e_igp3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
5262 * @hw: pointer to the HW structure
5264 * Workaround for 82566 power-down on D3 entry:
5265 * 1) disable gigabit link
5266 * 2) write VR power-down enable
5268 * Continue if successful, else issue LCD reset and repeat
5270 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
5276 if (hw->phy.type != e1000_phy_igp_3)
5279 /* Try the workaround twice (if needed) */
5282 reg = er32(PHY_CTRL);
5283 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
5284 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5285 ew32(PHY_CTRL, reg);
5287 /* Call gig speed drop workaround on Gig disable before
5288 * accessing any PHY registers
5290 if (hw->mac.type == e1000_ich8lan)
5291 e1000e_gig_downshift_workaround_ich8lan(hw);
5293 /* Write VR power-down enable */
5294 e1e_rphy(hw, IGP3_VR_CTRL, &data);
5295 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5296 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
5298 /* Read it back and test */
5299 e1e_rphy(hw, IGP3_VR_CTRL, &data);
5300 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5301 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
5304 /* Issue PHY reset and repeat at most one more time */
5306 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
5312 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
5313 * @hw: pointer to the HW structure
5315 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
5316 * LPLU, Gig disable, MDIC PHY reset):
5317 * 1) Set Kumeran Near-end loopback
5318 * 2) Clear Kumeran Near-end loopback
5319 * Should only be called for ICH8[m] devices with any 1G Phy.
5321 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
5326 if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife))
5329 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5333 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
5334 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5338 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
5339 e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, reg_data);
5343 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
5344 * @hw: pointer to the HW structure
5346 * During S0 to Sx transition, it is possible the link remains at gig
5347 * instead of negotiating to a lower speed. Before going to Sx, set
5348 * 'Gig Disable' to force link speed negotiation to a lower speed based on
5349 * the LPLU setting in the NVM or custom setting. For PCH and newer parts,
5350 * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
5351 * needs to be written.
5352 * Parts that support (and are linked to a partner which support) EEE in
5353 * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
5354 * than 10Mbps w/o EEE.
5356 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
5358 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5362 phy_ctrl = er32(PHY_CTRL);
5363 phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
5365 if (hw->phy.type == e1000_phy_i217) {
5366 u16 phy_reg, device_id = hw->adapter->pdev->device;
5368 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
5369 (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
5370 (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
5371 (device_id == E1000_DEV_ID_PCH_I218_V3) ||
5372 (hw->mac.type >= e1000_pch_spt)) {
5373 u32 fextnvm6 = er32(FEXTNVM6);
5375 ew32(FEXTNVM6, fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
5378 ret_val = hw->phy.ops.acquire(hw);
5382 if (!dev_spec->eee_disable) {
5386 e1000_read_emi_reg_locked(hw,
5387 I217_EEE_ADVERTISEMENT,
5392 /* Disable LPLU if both link partners support 100BaseT
5393 * EEE and 100Full is advertised on both ends of the
5394 * link, and enable Auto Enable LPI since there will
5395 * be no driver to enable LPI while in Sx.
5397 if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
5398 (dev_spec->eee_lp_ability &
5399 I82579_EEE_100_SUPPORTED) &&
5400 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {
5401 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
5402 E1000_PHY_CTRL_NOND0A_LPLU);
5404 /* Set Auto Enable LPI after link up */
5406 I217_LPI_GPIO_CTRL, &phy_reg);
5407 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5409 I217_LPI_GPIO_CTRL, phy_reg);
5413 /* For i217 Intel Rapid Start Technology support,
5414 * when the system is going into Sx and no manageability engine
5415 * is present, the driver must configure proxy to reset only on
5416 * power good. LPI (Low Power Idle) state must also reset only
5417 * on power good, as well as the MTA (Multicast table array).
5418 * The SMBus release must also be disabled on LCD reset.
5420 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
5421 /* Enable proxy to reset only on power good. */
5422 e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg);
5423 phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
5424 e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg);
5426 /* Set bit enable LPI (EEE) to reset only on
5429 e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg);
5430 phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
5431 e1e_wphy_locked(hw, I217_SxCTRL, phy_reg);
5433 /* Disable the SMB release on LCD reset. */
5434 e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
5435 phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
5436 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
5439 /* Enable MTA to reset for Intel Rapid Start Technology
5442 e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
5443 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
5444 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
5447 hw->phy.ops.release(hw);
5450 ew32(PHY_CTRL, phy_ctrl);
5452 if (hw->mac.type == e1000_ich8lan)
5453 e1000e_gig_downshift_workaround_ich8lan(hw);
5455 if (hw->mac.type >= e1000_pchlan) {
5456 e1000_oem_bits_config_ich8lan(hw, false);
5458 /* Reset PHY to activate OEM bits on 82577/8 */
5459 if (hw->mac.type == e1000_pchlan)
5460 e1000e_phy_hw_reset_generic(hw);
5462 ret_val = hw->phy.ops.acquire(hw);
5465 e1000_write_smbus_addr(hw);
5466 hw->phy.ops.release(hw);
5471 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
5472 * @hw: pointer to the HW structure
5474 * During Sx to S0 transitions on non-managed devices or managed devices
5475 * on which PHY resets are not blocked, if the PHY registers cannot be
5476 * accessed properly by the s/w toggle the LANPHYPC value to power cycle
5478 * On i217, setup Intel Rapid Start Technology.
5480 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
5484 if (hw->mac.type < e1000_pch2lan)
5487 ret_val = e1000_init_phy_workarounds_pchlan(hw);
5489 e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val);
5493 /* For i217 Intel Rapid Start Technology support when the system
5494 * is transitioning from Sx and no manageability engine is present
5495 * configure SMBus to restore on reset, disable proxy, and enable
5496 * the reset on MTA (Multicast table array).
5498 if (hw->phy.type == e1000_phy_i217) {
5501 ret_val = hw->phy.ops.acquire(hw);
5503 e_dbg("Failed to setup iRST\n");
5507 /* Clear Auto Enable LPI after link up */
5508 e1e_rphy_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
5509 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5510 e1e_wphy_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
5512 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
5513 /* Restore clear on SMB if no manageability engine
5516 ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
5519 phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
5520 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
5523 e1e_wphy_locked(hw, I217_PROXY_CTRL, 0);
5525 /* Enable reset on MTA */
5526 ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
5529 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
5530 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
5533 e_dbg("Error %d in resume workarounds\n", ret_val);
5534 hw->phy.ops.release(hw);
5539 * e1000_cleanup_led_ich8lan - Restore the default LED operation
5540 * @hw: pointer to the HW structure
5542 * Return the LED back to the default configuration.
5544 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
5546 if (hw->phy.type == e1000_phy_ife)
5547 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
5549 ew32(LEDCTL, hw->mac.ledctl_default);
5554 * e1000_led_on_ich8lan - Turn LEDs on
5555 * @hw: pointer to the HW structure
5559 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
5561 if (hw->phy.type == e1000_phy_ife)
5562 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5563 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
5565 ew32(LEDCTL, hw->mac.ledctl_mode2);
5570 * e1000_led_off_ich8lan - Turn LEDs off
5571 * @hw: pointer to the HW structure
5573 * Turn off the LEDs.
5575 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
5577 if (hw->phy.type == e1000_phy_ife)
5578 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5579 (IFE_PSCL_PROBE_MODE |
5580 IFE_PSCL_PROBE_LEDS_OFF));
5582 ew32(LEDCTL, hw->mac.ledctl_mode1);
5587 * e1000_setup_led_pchlan - Configures SW controllable LED
5588 * @hw: pointer to the HW structure
5590 * This prepares the SW controllable LED for use.
5592 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
5594 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);
5598 * e1000_cleanup_led_pchlan - Restore the default LED operation
5599 * @hw: pointer to the HW structure
5601 * Return the LED back to the default configuration.
5603 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
5605 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);
5609 * e1000_led_on_pchlan - Turn LEDs on
5610 * @hw: pointer to the HW structure
5614 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
5616 u16 data = (u16)hw->mac.ledctl_mode2;
5619 /* If no link, then turn LED on by setting the invert bit
5620 * for each LED that's mode is "link_up" in ledctl_mode2.
5622 if (!(er32(STATUS) & E1000_STATUS_LU)) {
5623 for (i = 0; i < 3; i++) {
5624 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5625 if ((led & E1000_PHY_LED0_MODE_MASK) !=
5626 E1000_LEDCTL_MODE_LINK_UP)
5628 if (led & E1000_PHY_LED0_IVRT)
5629 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5631 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5635 return e1e_wphy(hw, HV_LED_CONFIG, data);
5639 * e1000_led_off_pchlan - Turn LEDs off
5640 * @hw: pointer to the HW structure
5642 * Turn off the LEDs.
5644 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
5646 u16 data = (u16)hw->mac.ledctl_mode1;
5649 /* If no link, then turn LED off by clearing the invert bit
5650 * for each LED that's mode is "link_up" in ledctl_mode1.
5652 if (!(er32(STATUS) & E1000_STATUS_LU)) {
5653 for (i = 0; i < 3; i++) {
5654 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5655 if ((led & E1000_PHY_LED0_MODE_MASK) !=
5656 E1000_LEDCTL_MODE_LINK_UP)
5658 if (led & E1000_PHY_LED0_IVRT)
5659 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5661 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5665 return e1e_wphy(hw, HV_LED_CONFIG, data);
5669 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
5670 * @hw: pointer to the HW structure
5672 * Read appropriate register for the config done bit for completion status
5673 * and configure the PHY through s/w for EEPROM-less parts.
5675 * NOTE: some silicon which is EEPROM-less will fail trying to read the
5676 * config done bit, so only an error is logged and continues. If we were
5677 * to return with error, EEPROM-less silicon would not be able to be reset
5680 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
5686 e1000e_get_cfg_done_generic(hw);
5688 /* Wait for indication from h/w that it has completed basic config */
5689 if (hw->mac.type >= e1000_ich10lan) {
5690 e1000_lan_init_done_ich8lan(hw);
5692 ret_val = e1000e_get_auto_rd_done(hw);
5694 /* When auto config read does not complete, do not
5695 * return with an error. This can happen in situations
5696 * where there is no eeprom and prevents getting link.
5698 e_dbg("Auto Read Done did not complete\n");
5703 /* Clear PHY Reset Asserted bit */
5704 status = er32(STATUS);
5705 if (status & E1000_STATUS_PHYRA)
5706 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
5708 e_dbg("PHY Reset Asserted not set - needs delay\n");
5710 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
5711 if (hw->mac.type <= e1000_ich9lan) {
5712 if (!(er32(EECD) & E1000_EECD_PRES) &&
5713 (hw->phy.type == e1000_phy_igp_3)) {
5714 e1000e_phy_init_script_igp3(hw);
5717 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
5718 /* Maybe we should do a basic PHY config */
5719 e_dbg("EEPROM not present\n");
5720 ret_val = -E1000_ERR_CONFIG;
5728 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
5729 * @hw: pointer to the HW structure
5731 * In the case of a PHY power down to save power, or to turn off link during a
5732 * driver unload, or wake on lan is not enabled, remove the link.
5734 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
5736 /* If the management interface is not enabled, then power down */
5737 if (!(hw->mac.ops.check_mng_mode(hw) ||
5738 hw->phy.ops.check_reset_block(hw)))
5739 e1000_power_down_phy_copper(hw);
5743 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
5744 * @hw: pointer to the HW structure
5746 * Clears hardware counters specific to the silicon family and calls
5747 * clear_hw_cntrs_generic to clear all general purpose counters.
5749 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
5754 e1000e_clear_hw_cntrs_base(hw);
5770 /* Clear PHY statistics registers */
5771 if ((hw->phy.type == e1000_phy_82578) ||
5772 (hw->phy.type == e1000_phy_82579) ||
5773 (hw->phy.type == e1000_phy_i217) ||
5774 (hw->phy.type == e1000_phy_82577)) {
5775 ret_val = hw->phy.ops.acquire(hw);
5778 ret_val = hw->phy.ops.set_page(hw,
5779 HV_STATS_PAGE << IGP_PAGE_SHIFT);
5782 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
5783 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
5784 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
5785 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
5786 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
5787 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
5788 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
5789 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
5790 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
5791 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
5792 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
5793 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
5794 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
5795 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
5797 hw->phy.ops.release(hw);
5801 static const struct e1000_mac_operations ich8_mac_ops = {
5802 /* check_mng_mode dependent on mac type */
5803 .check_for_link = e1000_check_for_copper_link_ich8lan,
5804 /* cleanup_led dependent on mac type */
5805 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan,
5806 .get_bus_info = e1000_get_bus_info_ich8lan,
5807 .set_lan_id = e1000_set_lan_id_single_port,
5808 .get_link_up_info = e1000_get_link_up_info_ich8lan,
5809 /* led_on dependent on mac type */
5810 /* led_off dependent on mac type */
5811 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
5812 .reset_hw = e1000_reset_hw_ich8lan,
5813 .init_hw = e1000_init_hw_ich8lan,
5814 .setup_link = e1000_setup_link_ich8lan,
5815 .setup_physical_interface = e1000_setup_copper_link_ich8lan,
5816 /* id_led_init dependent on mac type */
5817 .config_collision_dist = e1000e_config_collision_dist_generic,
5818 .rar_set = e1000e_rar_set_generic,
5819 .rar_get_count = e1000e_rar_get_count_generic,
5822 static const struct e1000_phy_operations ich8_phy_ops = {
5823 .acquire = e1000_acquire_swflag_ich8lan,
5824 .check_reset_block = e1000_check_reset_block_ich8lan,
5826 .get_cfg_done = e1000_get_cfg_done_ich8lan,
5827 .get_cable_length = e1000e_get_cable_length_igp_2,
5828 .read_reg = e1000e_read_phy_reg_igp,
5829 .release = e1000_release_swflag_ich8lan,
5830 .reset = e1000_phy_hw_reset_ich8lan,
5831 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan,
5832 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan,
5833 .write_reg = e1000e_write_phy_reg_igp,
5836 static const struct e1000_nvm_operations ich8_nvm_ops = {
5837 .acquire = e1000_acquire_nvm_ich8lan,
5838 .read = e1000_read_nvm_ich8lan,
5839 .release = e1000_release_nvm_ich8lan,
5840 .reload = e1000e_reload_nvm_generic,
5841 .update = e1000_update_nvm_checksum_ich8lan,
5842 .valid_led_default = e1000_valid_led_default_ich8lan,
5843 .validate = e1000_validate_nvm_checksum_ich8lan,
5844 .write = e1000_write_nvm_ich8lan,
5847 static const struct e1000_nvm_operations spt_nvm_ops = {
5848 .acquire = e1000_acquire_nvm_ich8lan,
5849 .release = e1000_release_nvm_ich8lan,
5850 .read = e1000_read_nvm_spt,
5851 .update = e1000_update_nvm_checksum_spt,
5852 .reload = e1000e_reload_nvm_generic,
5853 .valid_led_default = e1000_valid_led_default_ich8lan,
5854 .validate = e1000_validate_nvm_checksum_ich8lan,
5855 .write = e1000_write_nvm_ich8lan,
5858 const struct e1000_info e1000_ich8_info = {
5859 .mac = e1000_ich8lan,
5860 .flags = FLAG_HAS_WOL
5862 | FLAG_HAS_CTRLEXT_ON_LOAD
5867 .max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN,
5868 .get_variants = e1000_get_variants_ich8lan,
5869 .mac_ops = &ich8_mac_ops,
5870 .phy_ops = &ich8_phy_ops,
5871 .nvm_ops = &ich8_nvm_ops,
5874 const struct e1000_info e1000_ich9_info = {
5875 .mac = e1000_ich9lan,
5876 .flags = FLAG_HAS_JUMBO_FRAMES
5879 | FLAG_HAS_CTRLEXT_ON_LOAD
5884 .max_hw_frame_size = DEFAULT_JUMBO,
5885 .get_variants = e1000_get_variants_ich8lan,
5886 .mac_ops = &ich8_mac_ops,
5887 .phy_ops = &ich8_phy_ops,
5888 .nvm_ops = &ich8_nvm_ops,
5891 const struct e1000_info e1000_ich10_info = {
5892 .mac = e1000_ich10lan,
5893 .flags = FLAG_HAS_JUMBO_FRAMES
5896 | FLAG_HAS_CTRLEXT_ON_LOAD
5901 .max_hw_frame_size = DEFAULT_JUMBO,
5902 .get_variants = e1000_get_variants_ich8lan,
5903 .mac_ops = &ich8_mac_ops,
5904 .phy_ops = &ich8_phy_ops,
5905 .nvm_ops = &ich8_nvm_ops,
5908 const struct e1000_info e1000_pch_info = {
5909 .mac = e1000_pchlan,
5910 .flags = FLAG_IS_ICH
5912 | FLAG_HAS_CTRLEXT_ON_LOAD
5915 | FLAG_HAS_JUMBO_FRAMES
5916 | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
5918 .flags2 = FLAG2_HAS_PHY_STATS,
5920 .max_hw_frame_size = 4096,
5921 .get_variants = e1000_get_variants_ich8lan,
5922 .mac_ops = &ich8_mac_ops,
5923 .phy_ops = &ich8_phy_ops,
5924 .nvm_ops = &ich8_nvm_ops,
5927 const struct e1000_info e1000_pch2_info = {
5928 .mac = e1000_pch2lan,
5929 .flags = FLAG_IS_ICH
5931 | FLAG_HAS_HW_TIMESTAMP
5932 | FLAG_HAS_CTRLEXT_ON_LOAD
5935 | FLAG_HAS_JUMBO_FRAMES
5937 .flags2 = FLAG2_HAS_PHY_STATS
5939 | FLAG2_CHECK_SYSTIM_OVERFLOW,
5941 .max_hw_frame_size = 9022,
5942 .get_variants = e1000_get_variants_ich8lan,
5943 .mac_ops = &ich8_mac_ops,
5944 .phy_ops = &ich8_phy_ops,
5945 .nvm_ops = &ich8_nvm_ops,
5948 const struct e1000_info e1000_pch_lpt_info = {
5949 .mac = e1000_pch_lpt,
5950 .flags = FLAG_IS_ICH
5952 | FLAG_HAS_HW_TIMESTAMP
5953 | FLAG_HAS_CTRLEXT_ON_LOAD
5956 | FLAG_HAS_JUMBO_FRAMES
5958 .flags2 = FLAG2_HAS_PHY_STATS
5960 | FLAG2_CHECK_SYSTIM_OVERFLOW,
5962 .max_hw_frame_size = 9022,
5963 .get_variants = e1000_get_variants_ich8lan,
5964 .mac_ops = &ich8_mac_ops,
5965 .phy_ops = &ich8_phy_ops,
5966 .nvm_ops = &ich8_nvm_ops,
5969 const struct e1000_info e1000_pch_spt_info = {
5970 .mac = e1000_pch_spt,
5971 .flags = FLAG_IS_ICH
5973 | FLAG_HAS_HW_TIMESTAMP
5974 | FLAG_HAS_CTRLEXT_ON_LOAD
5977 | FLAG_HAS_JUMBO_FRAMES
5979 .flags2 = FLAG2_HAS_PHY_STATS
5982 .max_hw_frame_size = 9022,
5983 .get_variants = e1000_get_variants_ich8lan,
5984 .mac_ops = &ich8_mac_ops,
5985 .phy_ops = &ich8_phy_ops,
5986 .nvm_ops = &spt_nvm_ops,
5989 const struct e1000_info e1000_pch_cnp_info = {
5990 .mac = e1000_pch_cnp,
5991 .flags = FLAG_IS_ICH
5993 | FLAG_HAS_HW_TIMESTAMP
5994 | FLAG_HAS_CTRLEXT_ON_LOAD
5997 | FLAG_HAS_JUMBO_FRAMES
5999 .flags2 = FLAG2_HAS_PHY_STATS
6002 .max_hw_frame_size = 9022,
6003 .get_variants = e1000_get_variants_ich8lan,
6004 .mac_ops = &ich8_mac_ops,
6005 .phy_ops = &ich8_phy_ops,
6006 .nvm_ops = &spt_nvm_ops,
6009 const struct e1000_info e1000_pch_tgp_info = {
6010 .mac = e1000_pch_tgp,
6011 .flags = FLAG_IS_ICH
6013 | FLAG_HAS_HW_TIMESTAMP
6014 | FLAG_HAS_CTRLEXT_ON_LOAD
6017 | FLAG_HAS_JUMBO_FRAMES
6019 .flags2 = FLAG2_HAS_PHY_STATS
6022 .max_hw_frame_size = 9022,
6023 .get_variants = e1000_get_variants_ich8lan,
6024 .mac_ops = &ich8_mac_ops,
6025 .phy_ops = &ich8_phy_ops,
6026 .nvm_ops = &spt_nvm_ops,
6029 const struct e1000_info e1000_pch_adp_info = {
6030 .mac = e1000_pch_adp,
6031 .flags = FLAG_IS_ICH
6033 | FLAG_HAS_HW_TIMESTAMP
6034 | FLAG_HAS_CTRLEXT_ON_LOAD
6037 | FLAG_HAS_JUMBO_FRAMES
6039 .flags2 = FLAG2_HAS_PHY_STATS
6042 .max_hw_frame_size = 9022,
6043 .get_variants = e1000_get_variants_ich8lan,
6044 .mac_ops = &ich8_mac_ops,
6045 .phy_ops = &ich8_phy_ops,
6046 .nvm_ops = &spt_nvm_ops,