drivers/net/ethernet/intel/e1000e/ich8lan.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2013 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /* 82562G 10/100 Network Connection
  30  * 82562G-2 10/100 Network Connection
  31  * 82562GT 10/100 Network Connection
  32  * 82562GT-2 10/100 Network Connection
  33  * 82562V 10/100 Network Connection
  34  * 82562V-2 10/100 Network Connection
  35  * 82566DC-2 Gigabit Network Connection
  36  * 82566DC Gigabit Network Connection
  37  * 82566DM-2 Gigabit Network Connection
  38  * 82566DM Gigabit Network Connection
  39  * 82566MC Gigabit Network Connection
  40  * 82566MM Gigabit Network Connection
  41  * 82567LM Gigabit Network Connection
  42  * 82567LF Gigabit Network Connection
  43  * 82567V Gigabit Network Connection
  44  * 82567LM-2 Gigabit Network Connection
  45  * 82567LF-2 Gigabit Network Connection
  46  * 82567V-2 Gigabit Network Connection
  47  * 82567LF-3 Gigabit Network Connection
  48  * 82567LM-3 Gigabit Network Connection
  49  * 82567LM-4 Gigabit Network Connection
  50  * 82577LM Gigabit Network Connection
  51  * 82577LC Gigabit Network Connection
  52  * 82578DM Gigabit Network Connection
  53  * 82578DC Gigabit Network Connection
  54  * 82579LM Gigabit Network Connection
  55  * 82579V Gigabit Network Connection
  56  */
  57
  58 #include "e1000.h"
  59
  60 #define ICH_FLASH_GFPREG                0x0000
  61 #define ICH_FLASH_HSFSTS                0x0004
  62 #define ICH_FLASH_HSFCTL                0x0006
  63 #define ICH_FLASH_FADDR                 0x0008
  64 #define ICH_FLASH_FDATA0                0x0010
  65 #define ICH_FLASH_PR0                   0x0074
  66
  67 #define ICH_FLASH_READ_COMMAND_TIMEOUT  500
  68 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
  69 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
  70 #define ICH_FLASH_LINEAR_ADDR_MASK      0x00FFFFFF
  71 #define ICH_FLASH_CYCLE_REPEAT_COUNT    10
  72
  73 #define ICH_CYCLE_READ                  0
  74 #define ICH_CYCLE_WRITE                 2
  75 #define ICH_CYCLE_ERASE                 3
  76
  77 #define FLASH_GFPREG_BASE_MASK          0x1FFF
  78 #define FLASH_SECTOR_ADDR_SHIFT         12
  79
  80 #define ICH_FLASH_SEG_SIZE_256          256
  81 #define ICH_FLASH_SEG_SIZE_4K           4096
  82 #define ICH_FLASH_SEG_SIZE_8K           8192
  83 #define ICH_FLASH_SEG_SIZE_64K          65536
  84
  85
  86 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
  87 /* FW established a valid mode */
  88 #define E1000_ICH_FWSM_FW_VALID         0x00008000
  89
  90 #define E1000_ICH_MNG_IAMT_MODE         0x2
  91
  92 #define ID_LED_DEFAULT_ICH8LAN  ((ID_LED_DEF1_DEF2 << 12) | \
  93                                  (ID_LED_DEF1_OFF2 <<  8) | \
  94                                  (ID_LED_DEF1_ON2  <<  4) | \
  95                                  (ID_LED_DEF1_DEF2))
  96
  97 #define E1000_ICH_NVM_SIG_WORD          0x13
  98 #define E1000_ICH_NVM_SIG_MASK          0xC000
  99 #define E1000_ICH_NVM_VALID_SIG_MASK    0xC0
 100 #define E1000_ICH_NVM_SIG_VALUE         0x80
 101
 102 #define E1000_ICH8_LAN_INIT_TIMEOUT     1500
 103
 104 #define E1000_FEXTNVM_SW_CONFIG         1
 105 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
 106
 107 #define E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK    0x0C000000
 108 #define E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC  0x08000000
 109
 110 #define E1000_FEXTNVM4_BEACON_DURATION_MASK    0x7
 111 #define E1000_FEXTNVM4_BEACON_DURATION_8USEC   0x7
 112 #define E1000_FEXTNVM4_BEACON_DURATION_16USEC  0x3
 113
 114 #define PCIE_ICH8_SNOOP_ALL             PCIE_NO_SNOOP_ALL
 115
 116 #define E1000_ICH_RAR_ENTRIES           7
 117 #define E1000_PCH2_RAR_ENTRIES          5 /* RAR[0], SHRA[0-3] */
 118 #define E1000_PCH_LPT_RAR_ENTRIES       12 /* RAR[0], SHRA[0-10] */
 119
 120 #define PHY_PAGE_SHIFT 5
 121 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
 122                            ((reg) & MAX_PHY_REG_ADDRESS))
 123 #define IGP3_KMRN_DIAG  PHY_REG(770, 19) /* KMRN Diagnostic */
 124 #define IGP3_VR_CTRL    PHY_REG(776, 18) /* Voltage Regulator Control */
 125
 126 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS    0x0002
 127 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
 128 #define IGP3_VR_CTRL_MODE_SHUTDOWN      0x0200
 129
 130 #define HV_LED_CONFIG           PHY_REG(768, 30) /* LED Configuration */
 131
 132 #define SW_FLAG_TIMEOUT    1000 /* SW Semaphore flag timeout in milliseconds */
 133
 134 /* SMBus Control Phy Register */
 135 #define CV_SMB_CTRL             PHY_REG(769, 23)
 136 #define CV_SMB_CTRL_FORCE_SMBUS 0x0001
 137
 138 /* SMBus Address Phy Register */
 139 #define HV_SMB_ADDR            PHY_REG(768, 26)
 140 #define HV_SMB_ADDR_MASK       0x007F
 141 #define HV_SMB_ADDR_PEC_EN     0x0200
 142 #define HV_SMB_ADDR_VALID      0x0080
 143 #define HV_SMB_ADDR_FREQ_MASK           0x1100
 144 #define HV_SMB_ADDR_FREQ_LOW_SHIFT      8
 145 #define HV_SMB_ADDR_FREQ_HIGH_SHIFT     12
 146
 147 /* PHY Power Management Control */
 148 #define HV_PM_CTRL              PHY_REG(770, 17)
 149 #define HV_PM_CTRL_PLL_STOP_IN_K1_GIGA  0x100
 150
 151 /* Intel Rapid Start Technology Support */
 152 #define I217_PROXY_CTRL                 BM_PHY_REG(BM_WUC_PAGE, 70)
 153 #define I217_PROXY_CTRL_AUTO_DISABLE    0x0080
 154 #define I217_SxCTRL                     PHY_REG(BM_PORT_CTRL_PAGE, 28)
 155 #define I217_SxCTRL_ENABLE_LPI_RESET    0x1000
 156 #define I217_CGFREG                     PHY_REG(772, 29)
 157 #define I217_CGFREG_ENABLE_MTA_RESET    0x0002
 158 #define I217_MEMPWR                     PHY_REG(772, 26)
 159 #define I217_MEMPWR_DISABLE_SMB_RELEASE 0x0010
 160
 161 /* Strapping Option Register - RO */
 162 #define E1000_STRAP                     0x0000C
 163 #define E1000_STRAP_SMBUS_ADDRESS_MASK  0x00FE0000
 164 #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
 165 #define E1000_STRAP_SMT_FREQ_MASK       0x00003000
 166 #define E1000_STRAP_SMT_FREQ_SHIFT      12
 167
 168 /* OEM Bits Phy Register */
 169 #define HV_OEM_BITS            PHY_REG(768, 25)
 170 #define HV_OEM_BITS_LPLU       0x0004 /* Low Power Link Up */
 171 #define HV_OEM_BITS_GBE_DIS    0x0040 /* Gigabit Disable */
 172 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
 173
 174 #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
 175 #define E1000_NVM_K1_ENABLE 0x1  /* NVM Enable K1 bit */
 176
 177 /* KMRN Mode Control */
 178 #define HV_KMRN_MODE_CTRL      PHY_REG(769, 16)
 179 #define HV_KMRN_MDIO_SLOW      0x0400
 180
 181 /* KMRN FIFO Control and Status */
 182 #define HV_KMRN_FIFO_CTRLSTA                  PHY_REG(770, 16)
 183 #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK    0x7000
 184 #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT   12
 185
 186 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
 187 /* Offset 04h HSFSTS */
 188 union ich8_hws_flash_status {
 189         struct ich8_hsfsts {
 190                 u16 flcdone    :1; /* bit 0 Flash Cycle Done */
 191                 u16 flcerr     :1; /* bit 1 Flash Cycle Error */
 192                 u16 dael       :1; /* bit 2 Direct Access error Log */
 193                 u16 berasesz   :2; /* bit 4:3 Sector Erase Size */
 194                 u16 flcinprog  :1; /* bit 5 flash cycle in Progress */
 195                 u16 reserved1  :2; /* bit 13:6 Reserved */
 196                 u16 reserved2  :6; /* bit 13:6 Reserved */
 197                 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
 198                 u16 flockdn    :1; /* bit 15 Flash Config Lock-Down */
 199         } hsf_status;
 200         u16 regval;
 201 };
 202
 203 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
 204 /* Offset 06h FLCTL */
 205 union ich8_hws_flash_ctrl {
 206         struct ich8_hsflctl {
 207                 u16 flcgo      :1;   /* 0 Flash Cycle Go */
 208                 u16 flcycle    :2;   /* 2:1 Flash Cycle */
 209                 u16 reserved   :5;   /* 7:3 Reserved  */
 210                 u16 fldbcount  :2;   /* 9:8 Flash Data Byte Count */
 211                 u16 flockdn    :6;   /* 15:10 Reserved */
 212         } hsf_ctrl;
 213         u16 regval;
 214 };
 215
 216 /* ICH Flash Region Access Permissions */
 217 union ich8_hws_flash_regacc {
 218         struct ich8_flracc {
 219                 u32 grra      :8; /* 0:7 GbE region Read Access */
 220                 u32 grwa      :8; /* 8:15 GbE region Write Access */
 221                 u32 gmrag     :8; /* 23:16 GbE Master Read Access Grant */
 222                 u32 gmwag     :8; /* 31:24 GbE Master Write Access Grant */
 223         } hsf_flregacc;
 224         u16 regval;
 225 };
 226
 227 /* ICH Flash Protected Region */
 228 union ich8_flash_protected_range {
 229         struct ich8_pr {
 230                 u32 base:13;     /* 0:12 Protected Range Base */
 231                 u32 reserved1:2; /* 13:14 Reserved */
 232                 u32 rpe:1;       /* 15 Read Protection Enable */
 233                 u32 limit:13;    /* 16:28 Protected Range Limit */
 234                 u32 reserved2:2; /* 29:30 Reserved */
 235                 u32 wpe:1;       /* 31 Write Protection Enable */
 236         } range;
 237         u32 regval;
 238 };
 239
 240 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
 241 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
 242 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
 243 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 244 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 245                                                 u32 offset, u8 byte);
 246 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
 247                                          u8 *data);
 248 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
 249                                          u16 *data);
 250 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 251                                          u8 size, u16 *data);
 252 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
 253 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 254 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
 255 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
 256 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
 257 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
 258 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
 259 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
 260 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
 261 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
 262 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
 263 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
 264 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
 265 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
 266 static s32  e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
 267 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
 268 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
 269 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
 270 static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
 271 static void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
 272 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
 273 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
 274
 275 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
 276 {
 277         return readw(hw->flash_address + reg);
 278 }
 279
 280 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
 281 {
 282         return readl(hw->flash_address + reg);
 283 }
 284
 285 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
 286 {
 287         writew(val, hw->flash_address + reg);
 288 }
 289
 290 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
 291 {
 292         writel(val, hw->flash_address + reg);
 293 }
 294
 295 #define er16flash(reg)          __er16flash(hw, (reg))
 296 #define er32flash(reg)          __er32flash(hw, (reg))
 297 #define ew16flash(reg, val)     __ew16flash(hw, (reg), (val))
 298 #define ew32flash(reg, val)     __ew32flash(hw, (reg), (val))
 299
 300 /**
 301  *  e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
 302  *  @hw: pointer to the HW structure
 303  *
 304  *  Test access to the PHY registers by reading the PHY ID registers.  If
 305  *  the PHY ID is already known (e.g. resume path) compare it with known ID,
 306  *  otherwise assume the read PHY ID is correct if it is valid.
 307  *
 308  *  Assumes the sw/fw/hw semaphore is already acquired.
 309  **/
 310 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
 311 {
 312         u16 phy_reg = 0;
 313         u32 phy_id = 0;
 314         s32 ret_val;
 315         u16 retry_count;
 316
 317         for (retry_count = 0; retry_count < 2; retry_count++) {
 318                 ret_val = e1e_rphy_locked(hw, PHY_ID1, &phy_reg);
 319                 if (ret_val || (phy_reg == 0xFFFF))
 320                         continue;
 321                 phy_id = (u32)(phy_reg << 16);
 322
 323                 ret_val = e1e_rphy_locked(hw, PHY_ID2, &phy_reg);
 324                 if (ret_val || (phy_reg == 0xFFFF)) {
 325                         phy_id = 0;
 326                         continue;
 327                 }
 328                 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
 329                 break;
 330         }
 331
 332         if (hw->phy.id) {
 333                 if (hw->phy.id == phy_id)
 334                         return true;
 335         } else if (phy_id) {
 336                 hw->phy.id = phy_id;
 337                 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
 338                 return true;
 339         }
 340
 341         /* In case the PHY needs to be in mdio slow mode,
 342          * set slow mode and try to get the PHY id again.
 343          */
 344         hw->phy.ops.release(hw);
 345         ret_val = e1000_set_mdio_slow_mode_hv(hw);
 346         if (!ret_val)
 347                 ret_val = e1000e_get_phy_id(hw);
 348         hw->phy.ops.acquire(hw);
 349
 350         return !ret_val;
 351 }
 352
 353 /**
 354  *  e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
 355  *  @hw: pointer to the HW structure
 356  *
 357  *  Workarounds/flow necessary for PHY initialization during driver load
 358  *  and resume paths.
 359  **/
 360 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
 361 {
 362         u32 mac_reg, fwsm = er32(FWSM);
 363         s32 ret_val;
 364         u16 phy_reg;
 365
 366         /* Gate automatic PHY configuration by hardware on managed and
 367          * non-managed 82579 and newer adapters.
 368          */
 369         e1000_gate_hw_phy_config_ich8lan(hw, true);
 370
 371         ret_val = hw->phy.ops.acquire(hw);
 372         if (ret_val) {
 373                 e_dbg("Failed to initialize PHY flow\n");
 374                 goto out;
 375         }
 376
 377         /* The MAC-PHY interconnect may be in SMBus mode.  If the PHY is
 378          * inaccessible and resetting the PHY is not blocked, toggle the
 379          * LANPHYPC Value bit to force the interconnect to PCIe mode.
 380          */
 381         switch (hw->mac.type) {
 382         case e1000_pch_lpt:
 383                 if (e1000_phy_is_accessible_pchlan(hw))
 384                         break;
 385
 386                 /* Before toggling LANPHYPC, see if PHY is accessible by
 387                  * forcing MAC to SMBus mode first.
 388                  */
 389                 mac_reg = er32(CTRL_EXT);
 390                 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
 391                 ew32(CTRL_EXT, mac_reg);
 392
 393                 /* fall-through */
 394         case e1000_pch2lan:
 395                 if (e1000_phy_is_accessible_pchlan(hw)) {
 396                         if (hw->mac.type == e1000_pch_lpt) {
 397                                 /* Unforce SMBus mode in PHY */
 398                                 e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg);
 399                                 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
 400                                 e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg);
 401
 402                                 /* Unforce SMBus mode in MAC */
 403                                 mac_reg = er32(CTRL_EXT);
 404                                 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
 405                                 ew32(CTRL_EXT, mac_reg);
 406                         }
 407                         break;
 408                 }
 409
 410                 /* fall-through */
 411         case e1000_pchlan:
 412                 if ((hw->mac.type == e1000_pchlan) &&
 413                     (fwsm & E1000_ICH_FWSM_FW_VALID))
 414                         break;
 415
 416                 if (hw->phy.ops.check_reset_block(hw)) {
 417                         e_dbg("Required LANPHYPC toggle blocked by ME\n");
 418                         break;
 419                 }
 420
 421                 e_dbg("Toggling LANPHYPC\n");
 422
 423                 /* Set Phy Config Counter to 50msec */
 424                 mac_reg = er32(FEXTNVM3);
 425                 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
 426                 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
 427                 ew32(FEXTNVM3, mac_reg);
 428
 429                 /* Toggle LANPHYPC Value bit */
 430                 mac_reg = er32(CTRL);
 431                 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
 432                 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
 433                 ew32(CTRL, mac_reg);
 434                 e1e_flush();
 435                 udelay(10);
 436                 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
 437                 ew32(CTRL, mac_reg);
 438                 e1e_flush();
 439                 if (hw->mac.type < e1000_pch_lpt) {
 440                         msleep(50);
 441                 } else {
 442                         u16 count = 20;
 443                         do {
 444                                 usleep_range(5000, 10000);
 445                         } while (!(er32(CTRL_EXT) &
 446                                    E1000_CTRL_EXT_LPCD) && count--);
 447                 }
 448                 break;
 449         default:
 450                 break;
 451         }
 452
 453         hw->phy.ops.release(hw);
 454
 455         /* Reset the PHY before any access to it.  Doing so, ensures
 456          * that the PHY is in a known good state before we read/write
 457          * PHY registers.  The generic reset is sufficient here,
 458          * because we haven't determined the PHY type yet.
 459          */
 460         ret_val = e1000e_phy_hw_reset_generic(hw);
 461
 462 out:
 463         /* Ungate automatic PHY configuration on non-managed 82579 */
 464         if ((hw->mac.type == e1000_pch2lan) &&
 465             !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
 466                 usleep_range(10000, 20000);
 467                 e1000_gate_hw_phy_config_ich8lan(hw, false);
 468         }
 469
 470         return ret_val;
 471 }
 472
 473 /**
 474  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 475  *  @hw: pointer to the HW structure
 476  *
 477  *  Initialize family-specific PHY parameters and function pointers.
 478  **/
 479 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 480 {
 481         struct e1000_phy_info *phy = &hw->phy;
 482         s32 ret_val = 0;
 483
 484         phy->addr                     = 1;
 485         phy->reset_delay_us           = 100;
 486
 487         phy->ops.set_page             = e1000_set_page_igp;
 488         phy->ops.read_reg             = e1000_read_phy_reg_hv;
 489         phy->ops.read_reg_locked      = e1000_read_phy_reg_hv_locked;
 490         phy->ops.read_reg_page        = e1000_read_phy_reg_page_hv;
 491         phy->ops.set_d0_lplu_state    = e1000_set_lplu_state_pchlan;
 492         phy->ops.set_d3_lplu_state    = e1000_set_lplu_state_pchlan;
 493         phy->ops.write_reg            = e1000_write_phy_reg_hv;
 494         phy->ops.write_reg_locked     = e1000_write_phy_reg_hv_locked;
 495         phy->ops.write_reg_page       = e1000_write_phy_reg_page_hv;
 496         phy->ops.power_up             = e1000_power_up_phy_copper;
 497         phy->ops.power_down           = e1000_power_down_phy_copper_ich8lan;
 498         phy->autoneg_mask             = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 499
 500         phy->id = e1000_phy_unknown;
 501
 502         ret_val = e1000_init_phy_workarounds_pchlan(hw);
 503         if (ret_val)
 504                 return ret_val;
 505
 506         if (phy->id == e1000_phy_unknown)
 507                 switch (hw->mac.type) {
 508                 default:
 509                         ret_val = e1000e_get_phy_id(hw);
 510                         if (ret_val)
 511                                 return ret_val;
 512                         if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
 513                                 break;
 514                         /* fall-through */
 515                 case e1000_pch2lan:
 516                 case e1000_pch_lpt:
 517                         /* In case the PHY needs to be in mdio slow mode,
 518                          * set slow mode and try to get the PHY id again.
 519                          */
 520                         ret_val = e1000_set_mdio_slow_mode_hv(hw);
 521                         if (ret_val)
 522                                 return ret_val;
 523                         ret_val = e1000e_get_phy_id(hw);
 524                         if (ret_val)
 525                                 return ret_val;
 526                         break;
 527                 }
 528         phy->type = e1000e_get_phy_type_from_id(phy->id);
 529
 530         switch (phy->type) {
 531         case e1000_phy_82577:
 532         case e1000_phy_82579:
 533         case e1000_phy_i217:
 534                 phy->ops.check_polarity = e1000_check_polarity_82577;
 535                 phy->ops.force_speed_duplex =
 536                     e1000_phy_force_speed_duplex_82577;
 537                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 538                 phy->ops.get_info = e1000_get_phy_info_82577;
 539                 phy->ops.commit = e1000e_phy_sw_reset;
 540                 break;
 541         case e1000_phy_82578:
 542                 phy->ops.check_polarity = e1000_check_polarity_m88;
 543                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 544                 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
 545                 phy->ops.get_info = e1000e_get_phy_info_m88;
 546                 break;
 547         default:
 548                 ret_val = -E1000_ERR_PHY;
 549                 break;
 550         }
 551
 552         return ret_val;
 553 }
 554
 555 /**
 556  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 557  *  @hw: pointer to the HW structure
 558  *
 559  *  Initialize family-specific PHY parameters and function pointers.
 560  **/
 561 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 562 {
 563         struct e1000_phy_info *phy = &hw->phy;
 564         s32 ret_val;
 565         u16 i = 0;
 566
 567         phy->addr                       = 1;
 568         phy->reset_delay_us             = 100;
 569
 570         phy->ops.power_up               = e1000_power_up_phy_copper;
 571         phy->ops.power_down             = e1000_power_down_phy_copper_ich8lan;
 572
 573         /* We may need to do this twice - once for IGP and if that fails,
 574          * we'll set BM func pointers and try again
 575          */
 576         ret_val = e1000e_determine_phy_address(hw);
 577         if (ret_val) {
 578                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 579                 phy->ops.read_reg  = e1000e_read_phy_reg_bm;
 580                 ret_val = e1000e_determine_phy_address(hw);
 581                 if (ret_val) {
 582                         e_dbg("Cannot determine PHY addr. Erroring out\n");
 583                         return ret_val;
 584                 }
 585         }
 586
 587         phy->id = 0;
 588         while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
 589                (i++ < 100)) {
 590                 usleep_range(1000, 2000);
 591                 ret_val = e1000e_get_phy_id(hw);
 592                 if (ret_val)
 593                         return ret_val;
 594         }
 595
 596         /* Verify phy id */
 597         switch (phy->id) {
 598         case IGP03E1000_E_PHY_ID:
 599                 phy->type = e1000_phy_igp_3;
 600                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 601                 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
 602                 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
 603                 phy->ops.get_info = e1000e_get_phy_info_igp;
 604                 phy->ops.check_polarity = e1000_check_polarity_igp;
 605                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
 606                 break;
 607         case IFE_E_PHY_ID:
 608         case IFE_PLUS_E_PHY_ID:
 609         case IFE_C_E_PHY_ID:
 610                 phy->type = e1000_phy_ife;
 611                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 612                 phy->ops.get_info = e1000_get_phy_info_ife;
 613                 phy->ops.check_polarity = e1000_check_polarity_ife;
 614                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
 615                 break;
 616         case BME1000_E_PHY_ID:
 617                 phy->type = e1000_phy_bm;
 618                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 619                 phy->ops.read_reg = e1000e_read_phy_reg_bm;
 620                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 621                 phy->ops.commit = e1000e_phy_sw_reset;
 622                 phy->ops.get_info = e1000e_get_phy_info_m88;
 623                 phy->ops.check_polarity = e1000_check_polarity_m88;
 624                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 625                 break;
 626         default:
 627                 return -E1000_ERR_PHY;
 628                 break;
 629         }
 630
 631         return 0;
 632 }
 633
 634 /**
 635  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 636  *  @hw: pointer to the HW structure
 637  *
 638  *  Initialize family-specific NVM parameters and function
 639  *  pointers.
 640  **/
 641 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 642 {
 643         struct e1000_nvm_info *nvm = &hw->nvm;
 644         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 645         u32 gfpreg, sector_base_addr, sector_end_addr;
 646         u16 i;
 647
 648         /* Can't read flash registers if the register set isn't mapped. */
 649         if (!hw->flash_address) {
 650                 e_dbg("ERROR: Flash registers not mapped\n");
 651                 return -E1000_ERR_CONFIG;
 652         }
 653
 654         nvm->type = e1000_nvm_flash_sw;
 655
 656         gfpreg = er32flash(ICH_FLASH_GFPREG);
 657
 658         /* sector_X_addr is a "sector"-aligned address (4096 bytes)
 659          * Add 1 to sector_end_addr since this sector is included in
 660          * the overall size.
 661          */
 662         sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 663         sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 664
 665         /* flash_base_addr is byte-aligned */
 666         nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
 667
 668         /* find total size of the NVM, then cut in half since the total
 669          * size represents two separate NVM banks.
 670          */
 671         nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
 672                                 << FLASH_SECTOR_ADDR_SHIFT;
 673         nvm->flash_bank_size /= 2;
 674         /* Adjust to word count */
 675         nvm->flash_bank_size /= sizeof(u16);
 676
 677         nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
 678
 679         /* Clear shadow ram */
 680         for (i = 0; i < nvm->word_size; i++) {
 681                 dev_spec->shadow_ram[i].modified = false;
 682                 dev_spec->shadow_ram[i].value    = 0xFFFF;
 683         }
 684
 685         return 0;
 686 }
 687
 688 /**
 689  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 690  *  @hw: pointer to the HW structure
 691  *
 692  *  Initialize family-specific MAC parameters and function
 693  *  pointers.
 694  **/
 695 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
 696 {
 697         struct e1000_mac_info *mac = &hw->mac;
 698
 699         /* Set media type function pointer */
 700         hw->phy.media_type = e1000_media_type_copper;
 701
 702         /* Set mta register count */
 703         mac->mta_reg_count = 32;
 704         /* Set rar entry count */
 705         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 706         if (mac->type == e1000_ich8lan)
 707                 mac->rar_entry_count--;
 708         /* FWSM register */
 709         mac->has_fwsm = true;
 710         /* ARC subsystem not supported */
 711         mac->arc_subsystem_valid = false;
 712         /* Adaptive IFS supported */
 713         mac->adaptive_ifs = true;
 714
 715         /* LED and other operations */
 716         switch (mac->type) {
 717         case e1000_ich8lan:
 718         case e1000_ich9lan:
 719         case e1000_ich10lan:
 720                 /* check management mode */
 721                 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
 722                 /* ID LED init */
 723                 mac->ops.id_led_init = e1000e_id_led_init_generic;
 724                 /* blink LED */
 725                 mac->ops.blink_led = e1000e_blink_led_generic;
 726                 /* setup LED */
 727                 mac->ops.setup_led = e1000e_setup_led_generic;
 728                 /* cleanup LED */
 729                 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
 730                 /* turn on/off LED */
 731                 mac->ops.led_on = e1000_led_on_ich8lan;
 732                 mac->ops.led_off = e1000_led_off_ich8lan;
 733                 break;
 734         case e1000_pch2lan:
 735                 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
 736                 mac->ops.rar_set = e1000_rar_set_pch2lan;
 737                 /* fall-through */
 738         case e1000_pch_lpt:
 739         case e1000_pchlan:
 740                 /* check management mode */
 741                 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
 742                 /* ID LED init */
 743                 mac->ops.id_led_init = e1000_id_led_init_pchlan;
 744                 /* setup LED */
 745                 mac->ops.setup_led = e1000_setup_led_pchlan;
 746                 /* cleanup LED */
 747                 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
 748                 /* turn on/off LED */
 749                 mac->ops.led_on = e1000_led_on_pchlan;
 750                 mac->ops.led_off = e1000_led_off_pchlan;
 751                 break;
 752         default:
 753                 break;
 754         }
 755
 756         if (mac->type == e1000_pch_lpt) {
 757                 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
 758                 mac->ops.rar_set = e1000_rar_set_pch_lpt;
 759         }
 760
 761         /* Enable PCS Lock-loss workaround for ICH8 */
 762         if (mac->type == e1000_ich8lan)
 763                 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
 764
 765         return 0;
 766 }
 767
 768 /**
 769  *  __e1000_access_emi_reg_locked - Read/write EMI register
 770  *  @hw: pointer to the HW structure
 771  *  @addr: EMI address to program
 772  *  @data: pointer to value to read/write from/to the EMI address
 773  *  @read: boolean flag to indicate read or write
 774  *
 775  *  This helper function assumes the SW/FW/HW Semaphore is already acquired.
 776  **/
 777 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
 778                                          u16 *data, bool read)
 779 {
 780         s32 ret_val = 0;
 781
 782         ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address);
 783         if (ret_val)
 784                 return ret_val;
 785
 786         if (read)
 787                 ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data);
 788         else
 789                 ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data);
 790
 791         return ret_val;
 792 }
 793
 794 /**
 795  *  e1000_read_emi_reg_locked - Read Extended Management Interface register
 796  *  @hw: pointer to the HW structure
 797  *  @addr: EMI address to program
 798  *  @data: value to be read from the EMI address
 799  *
 800  *  Assumes the SW/FW/HW Semaphore is already acquired.
 801  **/
 802 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
 803 {
 804         return __e1000_access_emi_reg_locked(hw, addr, data, true);
 805 }
 806
 807 /**
 808  *  e1000_write_emi_reg_locked - Write Extended Management Interface register
 809  *  @hw: pointer to the HW structure
 810  *  @addr: EMI address to program
 811  *  @data: value to be written to the EMI address
 812  *
 813  *  Assumes the SW/FW/HW Semaphore is already acquired.
 814  **/
 815 static s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
 816 {
 817         return __e1000_access_emi_reg_locked(hw, addr, &data, false);
 818 }
 819
 820 /**
 821  *  e1000_set_eee_pchlan - Enable/disable EEE support
 822  *  @hw: pointer to the HW structure
 823  *
 824  *  Enable/disable EEE based on setting in dev_spec structure, the duplex of
 825  *  the link and the EEE capabilities of the link partner.  The LPI Control
 826  *  register bits will remain set only if/when link is up.
 827  **/
 828 static s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
 829 {
 830         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 831         s32 ret_val;
 832         u16 lpi_ctrl;
 833
 834         if ((hw->phy.type != e1000_phy_82579) &&
 835             (hw->phy.type != e1000_phy_i217))
 836                 return 0;
 837
 838         ret_val = hw->phy.ops.acquire(hw);
 839         if (ret_val)
 840                 return ret_val;
 841
 842         ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
 843         if (ret_val)
 844                 goto release;
 845
 846         /* Clear bits that enable EEE in various speeds */
 847         lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
 848
 849         /* Enable EEE if not disabled by user */
 850         if (!dev_spec->eee_disable) {
 851                 u16 lpa, pcs_status, data;
 852
 853                 /* Save off link partner's EEE ability */
 854                 switch (hw->phy.type) {
 855                 case e1000_phy_82579:
 856                         lpa = I82579_EEE_LP_ABILITY;
 857                         pcs_status = I82579_EEE_PCS_STATUS;
 858                         break;
 859                 case e1000_phy_i217:
 860                         lpa = I217_EEE_LP_ABILITY;
 861                         pcs_status = I217_EEE_PCS_STATUS;
 862                         break;
 863                 default:
 864                         ret_val = -E1000_ERR_PHY;
 865                         goto release;
 866                 }
 867                 ret_val = e1000_read_emi_reg_locked(hw, lpa,
 868                                                     &dev_spec->eee_lp_ability);
 869                 if (ret_val)
 870                         goto release;
 871
 872                 /* Enable EEE only for speeds in which the link partner is
 873                  * EEE capable.
 874                  */
 875                 if (dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
 876                         lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
 877
 878                 if (dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
 879                         e1e_rphy_locked(hw, PHY_LP_ABILITY, &data);
 880                         if (data & NWAY_LPAR_100TX_FD_CAPS)
 881                                 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
 882                         else
 883                                 /* EEE is not supported in 100Half, so ignore
 884                                  * partner's EEE in 100 ability if full-duplex
 885                                  * is not advertised.
 886                                  */
 887                                 dev_spec->eee_lp_ability &=
 888                                     ~I82579_EEE_100_SUPPORTED;
 889                 }
 890
 891                 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
 892                 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
 893                 if (ret_val)
 894                         goto release;
 895         }
 896
 897         ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
 898 release:
 899         hw->phy.ops.release(hw);
 900
 901         return ret_val;
 902 }
 903
 904 /**
 905  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
 906  *  @hw: pointer to the HW structure
 907  *
 908  *  Checks to see of the link status of the hardware has changed.  If a
 909  *  change in link status has been detected, then we read the PHY registers
 910  *  to get the current speed/duplex if link exists.
 911  **/
 912 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
 913 {
 914         struct e1000_mac_info *mac = &hw->mac;
 915         s32 ret_val;
 916         bool link;
 917         u16 phy_reg;
 918
 919         /* We only want to go out to the PHY registers to see if Auto-Neg
 920          * has completed and/or if our link status has changed.  The
 921          * get_link_status flag is set upon receiving a Link Status
 922          * Change or Rx Sequence Error interrupt.
 923          */
 924         if (!mac->get_link_status)
 925                 return 0;
 926
 927         /* First we want to see if the MII Status Register reports
 928          * link.  If so, then we want to get the current speed/duplex
 929          * of the PHY.
 930          */
 931         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
 932         if (ret_val)
 933                 return ret_val;
 934
 935         if (hw->mac.type == e1000_pchlan) {
 936                 ret_val = e1000_k1_gig_workaround_hv(hw, link);
 937                 if (ret_val)
 938                         return ret_val;
 939         }
 940
 941         /* Clear link partner's EEE ability */
 942         hw->dev_spec.ich8lan.eee_lp_ability = 0;
 943
 944         if (!link)
 945                 return 0; /* No link detected */
 946
 947         mac->get_link_status = false;
 948
 949         switch (hw->mac.type) {
 950         case e1000_pch2lan:
 951                 ret_val = e1000_k1_workaround_lv(hw);
 952                 if (ret_val)
 953                         return ret_val;
 954                 /* fall-thru */
 955         case e1000_pchlan:
 956                 if (hw->phy.type == e1000_phy_82578) {
 957                         ret_val = e1000_link_stall_workaround_hv(hw);
 958                         if (ret_val)
 959                                 return ret_val;
 960                 }
 961
 962                 /* Workaround for PCHx parts in half-duplex:
 963                  * Set the number of preambles removed from the packet
 964                  * when it is passed from the PHY to the MAC to prevent
 965                  * the MAC from misinterpreting the packet type.
 966                  */
 967                 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
 968                 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
 969
 970                 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD)
 971                         phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
 972
 973                 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
 974                 break;
 975         default:
 976                 break;
 977         }
 978
 979         /* Check if there was DownShift, must be checked
 980          * immediately after link-up
 981          */
 982         e1000e_check_downshift(hw);
 983
 984         /* Enable/Disable EEE after link up */
 985         ret_val = e1000_set_eee_pchlan(hw);
 986         if (ret_val)
 987                 return ret_val;
 988
 989         /* If we are forcing speed/duplex, then we simply return since
 990          * we have already determined whether we have link or not.
 991          */
 992         if (!mac->autoneg)
 993                 return -E1000_ERR_CONFIG;
 994
 995         /* Auto-Neg is enabled.  Auto Speed Detection takes care
 996          * of MAC speed/duplex configuration.  So we only need to
 997          * configure Collision Distance in the MAC.
 998          */
 999         mac->ops.config_collision_dist(hw);
1000
1001         /* Configure Flow Control now that Auto-Neg has completed.
1002          * First, we need to restore the desired flow control
1003          * settings because we may have had to re-autoneg with a
1004          * different link partner.
1005          */
1006         ret_val = e1000e_config_fc_after_link_up(hw);
1007         if (ret_val)
1008                 e_dbg("Error configuring flow control\n");
1009
1010         return ret_val;
1011 }
1012
1013 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
1014 {
1015         struct e1000_hw *hw = &adapter->hw;
1016         s32 rc;
1017
1018         rc = e1000_init_mac_params_ich8lan(hw);
1019         if (rc)
1020                 return rc;
1021
1022         rc = e1000_init_nvm_params_ich8lan(hw);
1023         if (rc)
1024                 return rc;
1025
1026         switch (hw->mac.type) {
1027         case e1000_ich8lan:
1028         case e1000_ich9lan:
1029         case e1000_ich10lan:
1030                 rc = e1000_init_phy_params_ich8lan(hw);
1031                 break;
1032         case e1000_pchlan:
1033         case e1000_pch2lan:
1034         case e1000_pch_lpt:
1035                 rc = e1000_init_phy_params_pchlan(hw);
1036                 break;
1037         default:
1038                 break;
1039         }
1040         if (rc)
1041                 return rc;
1042
1043         /* Disable Jumbo Frame support on parts with Intel 10/100 PHY or
1044          * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
1045          */
1046         if ((adapter->hw.phy.type == e1000_phy_ife) ||
1047             ((adapter->hw.mac.type >= e1000_pch2lan) &&
1048              (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) {
1049                 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
1050                 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
1051
1052                 hw->mac.ops.blink_led = NULL;
1053         }
1054
1055         if ((adapter->hw.mac.type == e1000_ich8lan) &&
1056             (adapter->hw.phy.type != e1000_phy_ife))
1057                 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
1058
1059         /* Enable workaround for 82579 w/ ME enabled */
1060         if ((adapter->hw.mac.type == e1000_pch2lan) &&
1061             (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
1062                 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA;
1063
1064         /* Disable EEE by default until IEEE802.3az spec is finalized */
1065         if (adapter->flags2 & FLAG2_HAS_EEE)
1066                 adapter->hw.dev_spec.ich8lan.eee_disable = true;
1067
1068         return 0;
1069 }
1070
1071 static DEFINE_MUTEX(nvm_mutex);
1072
1073 /**
1074  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1075  *  @hw: pointer to the HW structure
1076  *
1077  *  Acquires the mutex for performing NVM operations.
1078  **/
1079 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
1080 {
1081         mutex_lock(&nvm_mutex);
1082
1083         return 0;
1084 }
1085
1086 /**
1087  *  e1000_release_nvm_ich8lan - Release NVM mutex
1088  *  @hw: pointer to the HW structure
1089  *
1090  *  Releases the mutex used while performing NVM operations.
1091  **/
1092 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
1093 {
1094         mutex_unlock(&nvm_mutex);
1095 }
1096
1097 /**
1098  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
1099  *  @hw: pointer to the HW structure
1100  *
1101  *  Acquires the software control flag for performing PHY and select
1102  *  MAC CSR accesses.
1103  **/
1104 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1105 {
1106         u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1107         s32 ret_val = 0;
1108
1109         if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE,
1110                              &hw->adapter->state)) {
1111                 e_dbg("contention for Phy access\n");
1112                 return -E1000_ERR_PHY;
1113         }
1114
1115         while (timeout) {
1116                 extcnf_ctrl = er32(EXTCNF_CTRL);
1117                 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1118                         break;
1119
1120                 mdelay(1);
1121                 timeout--;
1122         }
1123
1124         if (!timeout) {
1125                 e_dbg("SW has already locked the resource.\n");
1126                 ret_val = -E1000_ERR_CONFIG;
1127                 goto out;
1128         }
1129
1130         timeout = SW_FLAG_TIMEOUT;
1131
1132         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1133         ew32(EXTCNF_CTRL, extcnf_ctrl);
1134
1135         while (timeout) {
1136                 extcnf_ctrl = er32(EXTCNF_CTRL);
1137                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1138                         break;
1139
1140                 mdelay(1);
1141                 timeout--;
1142         }
1143
1144         if (!timeout) {
1145                 e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1146                       er32(FWSM), extcnf_ctrl);
1147                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1148                 ew32(EXTCNF_CTRL, extcnf_ctrl);
1149                 ret_val = -E1000_ERR_CONFIG;
1150                 goto out;
1151         }
1152
1153 out:
1154         if (ret_val)
1155                 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1156
1157         return ret_val;
1158 }
1159
1160 /**
1161  *  e1000_release_swflag_ich8lan - Release software control flag
1162  *  @hw: pointer to the HW structure
1163  *
1164  *  Releases the software control flag for performing PHY and select
1165  *  MAC CSR accesses.
1166  **/
1167 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1168 {
1169         u32 extcnf_ctrl;
1170
1171         extcnf_ctrl = er32(EXTCNF_CTRL);
1172
1173         if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1174                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1175                 ew32(EXTCNF_CTRL, extcnf_ctrl);
1176         } else {
1177                 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");
1178         }
1179
1180         clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1181 }
1182
1183 /**
1184  *  e1000_check_mng_mode_ich8lan - Checks management mode
1185  *  @hw: pointer to the HW structure
1186  *
1187  *  This checks if the adapter has any manageability enabled.
1188  *  This is a function pointer entry point only called by read/write
1189  *  routines for the PHY and NVM parts.
1190  **/
1191 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1192 {
1193         u32 fwsm;
1194
1195         fwsm = er32(FWSM);
1196         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1197                ((fwsm & E1000_FWSM_MODE_MASK) ==
1198                 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1199 }
1200
1201 /**
1202  *  e1000_check_mng_mode_pchlan - Checks management mode
1203  *  @hw: pointer to the HW structure
1204  *
1205  *  This checks if the adapter has iAMT enabled.
1206  *  This is a function pointer entry point only called by read/write
1207  *  routines for the PHY and NVM parts.
1208  **/
1209 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1210 {
1211         u32 fwsm;
1212
1213         fwsm = er32(FWSM);
1214         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1215                (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1216 }
1217
1218 /**
1219  *  e1000_rar_set_pch2lan - Set receive address register
1220  *  @hw: pointer to the HW structure
1221  *  @addr: pointer to the receive address
1222  *  @index: receive address array register
1223  *
1224  *  Sets the receive address array register at index to the address passed
1225  *  in by addr.  For 82579, RAR[0] is the base address register that is to
1226  *  contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1227  *  Use SHRA[0-3] in place of those reserved for ME.
1228  **/
1229 static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1230 {
1231         u32 rar_low, rar_high;
1232
1233         /* HW expects these in little endian so we reverse the byte order
1234          * from network order (big endian) to little endian
1235          */
1236         rar_low = ((u32)addr[0] |
1237                    ((u32)addr[1] << 8) |
1238                    ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1239
1240         rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1241
1242         /* If MAC address zero, no need to set the AV bit */
1243         if (rar_low || rar_high)
1244                 rar_high |= E1000_RAH_AV;
1245
1246         if (index == 0) {
1247                 ew32(RAL(index), rar_low);
1248                 e1e_flush();
1249                 ew32(RAH(index), rar_high);
1250                 e1e_flush();
1251                 return;
1252         }
1253
1254         if (index < hw->mac.rar_entry_count) {
1255                 s32 ret_val;
1256
1257                 ret_val = e1000_acquire_swflag_ich8lan(hw);
1258                 if (ret_val)
1259                         goto out;
1260
1261                 ew32(SHRAL(index - 1), rar_low);
1262                 e1e_flush();
1263                 ew32(SHRAH(index - 1), rar_high);
1264                 e1e_flush();
1265
1266                 e1000_release_swflag_ich8lan(hw);
1267
1268                 /* verify the register updates */
1269                 if ((er32(SHRAL(index - 1)) == rar_low) &&
1270                     (er32(SHRAH(index - 1)) == rar_high))
1271                         return;
1272
1273                 e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1274                       (index - 1), er32(FWSM));
1275         }
1276
1277 out:
1278         e_dbg("Failed to write receive address at index %d\n", index);
1279 }
1280
1281 /**
1282  *  e1000_rar_set_pch_lpt - Set receive address registers
1283  *  @hw: pointer to the HW structure
1284  *  @addr: pointer to the receive address
1285  *  @index: receive address array register
1286  *
1287  *  Sets the receive address register array at index to the address passed
1288  *  in by addr. For LPT, RAR[0] is the base address register that is to
1289  *  contain the MAC address. SHRA[0-10] are the shared receive address
1290  *  registers that are shared between the Host and manageability engine (ME).
1291  **/
1292 static void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
1293 {
1294         u32 rar_low, rar_high;
1295         u32 wlock_mac;
1296
1297         /* HW expects these in little endian so we reverse the byte order
1298          * from network order (big endian) to little endian
1299          */
1300         rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
1301                    ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1302
1303         rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1304
1305         /* If MAC address zero, no need to set the AV bit */
1306         if (rar_low || rar_high)
1307                 rar_high |= E1000_RAH_AV;
1308
1309         if (index == 0) {
1310                 ew32(RAL(index), rar_low);
1311                 e1e_flush();
1312                 ew32(RAH(index), rar_high);
1313                 e1e_flush();
1314                 return;
1315         }
1316
1317         /* The manageability engine (ME) can lock certain SHRAR registers that
1318          * it is using - those registers are unavailable for use.
1319          */
1320         if (index < hw->mac.rar_entry_count) {
1321                 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
1322                 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1323
1324                 /* Check if all SHRAR registers are locked */
1325                 if (wlock_mac == 1)
1326                         goto out;
1327
1328                 if ((wlock_mac == 0) || (index <= wlock_mac)) {
1329                         s32 ret_val;
1330
1331                         ret_val = e1000_acquire_swflag_ich8lan(hw);
1332
1333                         if (ret_val)
1334                                 goto out;
1335
1336                         ew32(SHRAL_PCH_LPT(index - 1), rar_low);
1337                         e1e_flush();
1338                         ew32(SHRAH_PCH_LPT(index - 1), rar_high);
1339                         e1e_flush();
1340
1341                         e1000_release_swflag_ich8lan(hw);
1342
1343                         /* verify the register updates */
1344                         if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) &&
1345                             (er32(SHRAH_PCH_LPT(index - 1)) == rar_high))
1346                                 return;
1347                 }
1348         }
1349
1350 out:
1351         e_dbg("Failed to write receive address at index %d\n", index);
1352 }
1353
1354 /**
1355  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
1356  *  @hw: pointer to the HW structure
1357  *
1358  *  Checks if firmware is blocking the reset of the PHY.
1359  *  This is a function pointer entry point only called by
1360  *  reset routines.
1361  **/
1362 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
1363 {
1364         u32 fwsm;
1365
1366         fwsm = er32(FWSM);
1367
1368         return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
1369 }
1370
1371 /**
1372  *  e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
1373  *  @hw: pointer to the HW structure
1374  *
1375  *  Assumes semaphore already acquired.
1376  *
1377  **/
1378 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
1379 {
1380         u16 phy_data;
1381         u32 strap = er32(STRAP);
1382         u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
1383             E1000_STRAP_SMT_FREQ_SHIFT;
1384         s32 ret_val = 0;
1385
1386         strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
1387
1388         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
1389         if (ret_val)
1390                 return ret_val;
1391
1392         phy_data &= ~HV_SMB_ADDR_MASK;
1393         phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
1394         phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
1395
1396         if (hw->phy.type == e1000_phy_i217) {
1397                 /* Restore SMBus frequency */
1398                 if (freq--) {
1399                         phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
1400                         phy_data |= (freq & (1 << 0)) <<
1401                             HV_SMB_ADDR_FREQ_LOW_SHIFT;
1402                         phy_data |= (freq & (1 << 1)) <<
1403                             (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
1404                 } else {
1405                         e_dbg("Unsupported SMB frequency in PHY\n");
1406                 }
1407         }
1408
1409         return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
1410 }
1411
1412 /**
1413  *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
1414  *  @hw:   pointer to the HW structure
1415  *
1416  *  SW should configure the LCD from the NVM extended configuration region
1417  *  as a workaround for certain parts.
1418  **/
1419 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
1420 {
1421         struct e1000_phy_info *phy = &hw->phy;
1422         u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
1423         s32 ret_val = 0;
1424         u16 word_addr, reg_data, reg_addr, phy_page = 0;
1425
1426         /* Initialize the PHY from the NVM on ICH platforms.  This
1427          * is needed due to an issue where the NVM configuration is
1428          * not properly autoloaded after power transitions.
1429          * Therefore, after each PHY reset, we will load the
1430          * configuration data out of the NVM manually.
1431          */
1432         switch (hw->mac.type) {
1433         case e1000_ich8lan:
1434                 if (phy->type != e1000_phy_igp_3)
1435                         return ret_val;
1436
1437                 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
1438                     (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
1439                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
1440                         break;
1441                 }
1442                 /* Fall-thru */
1443         case e1000_pchlan:
1444         case e1000_pch2lan:
1445         case e1000_pch_lpt:
1446                 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
1447                 break;
1448         default:
1449                 return ret_val;
1450         }
1451
1452         ret_val = hw->phy.ops.acquire(hw);
1453         if (ret_val)
1454                 return ret_val;
1455
1456         data = er32(FEXTNVM);
1457         if (!(data & sw_cfg_mask))
1458                 goto release;
1459
1460         /* Make sure HW does not configure LCD from PHY
1461          * extended configuration before SW configuration
1462          */
1463         data = er32(EXTCNF_CTRL);
1464         if ((hw->mac.type < e1000_pch2lan) &&
1465             (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
1466                 goto release;
1467
1468         cnf_size = er32(EXTCNF_SIZE);
1469         cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
1470         cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
1471         if (!cnf_size)
1472                 goto release;
1473
1474         cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
1475         cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
1476
1477         if (((hw->mac.type == e1000_pchlan) &&
1478              !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
1479             (hw->mac.type > e1000_pchlan)) {
1480                 /* HW configures the SMBus address and LEDs when the
1481                  * OEM and LCD Write Enable bits are set in the NVM.
1482                  * When both NVM bits are cleared, SW will configure
1483                  * them instead.
1484                  */
1485                 ret_val = e1000_write_smbus_addr(hw);
1486                 if (ret_val)
1487                         goto release;
1488
1489                 data = er32(LEDCTL);
1490                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
1491                                                         (u16)data);
1492                 if (ret_val)
1493                         goto release;
1494         }
1495
1496         /* Configure LCD from extended configuration region. */
1497
1498         /* cnf_base_addr is in DWORD */
1499         word_addr = (u16)(cnf_base_addr << 1);
1500
1501         for (i = 0; i < cnf_size; i++) {
1502                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1,
1503                                          &reg_data);
1504                 if (ret_val)
1505                         goto release;
1506
1507                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
1508                                          1, &reg_addr);
1509                 if (ret_val)
1510                         goto release;
1511
1512                 /* Save off the PHY page for future writes. */
1513                 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
1514                         phy_page = reg_data;
1515                         continue;
1516                 }
1517
1518                 reg_addr &= PHY_REG_MASK;
1519                 reg_addr |= phy_page;
1520
1521                 ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data);
1522                 if (ret_val)
1523                         goto release;
1524         }
1525
1526 release:
1527         hw->phy.ops.release(hw);
1528         return ret_val;
1529 }
1530
1531 /**
1532  *  e1000_k1_gig_workaround_hv - K1 Si workaround
1533  *  @hw:   pointer to the HW structure
1534  *  @link: link up bool flag
1535  *
1536  *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
1537  *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
1538  *  If link is down, the function will restore the default K1 setting located
1539  *  in the NVM.
1540  **/
1541 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
1542 {
1543         s32 ret_val = 0;
1544         u16 status_reg = 0;
1545         bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
1546
1547         if (hw->mac.type != e1000_pchlan)
1548                 return 0;
1549
1550         /* Wrap the whole flow with the sw flag */
1551         ret_val = hw->phy.ops.acquire(hw);
1552         if (ret_val)
1553                 return ret_val;
1554
1555         /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
1556         if (link) {
1557                 if (hw->phy.type == e1000_phy_82578) {
1558                         ret_val = e1e_rphy_locked(hw, BM_CS_STATUS,
1559                                                   &status_reg);
1560                         if (ret_val)
1561                                 goto release;
1562
1563                         status_reg &= BM_CS_STATUS_LINK_UP |
1564                                       BM_CS_STATUS_RESOLVED |
1565                                       BM_CS_STATUS_SPEED_MASK;
1566
1567                         if (status_reg == (BM_CS_STATUS_LINK_UP |
1568                                            BM_CS_STATUS_RESOLVED |
1569                                            BM_CS_STATUS_SPEED_1000))
1570                                 k1_enable = false;
1571                 }
1572
1573                 if (hw->phy.type == e1000_phy_82577) {
1574                         ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg);
1575                         if (ret_val)
1576                                 goto release;
1577
1578                         status_reg &= HV_M_STATUS_LINK_UP |
1579                                       HV_M_STATUS_AUTONEG_COMPLETE |
1580                                       HV_M_STATUS_SPEED_MASK;
1581
1582                         if (status_reg == (HV_M_STATUS_LINK_UP |
1583                                            HV_M_STATUS_AUTONEG_COMPLETE |
1584                                            HV_M_STATUS_SPEED_1000))
1585                                 k1_enable = false;
1586                 }
1587
1588                 /* Link stall fix for link up */
1589                 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100);
1590                 if (ret_val)
1591                         goto release;
1592
1593         } else {
1594                 /* Link stall fix for link down */
1595                 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100);
1596                 if (ret_val)
1597                         goto release;
1598         }
1599
1600         ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
1601
1602 release:
1603         hw->phy.ops.release(hw);
1604
1605         return ret_val;
1606 }
1607
1608 /**
1609  *  e1000_configure_k1_ich8lan - Configure K1 power state
1610  *  @hw: pointer to the HW structure
1611  *  @enable: K1 state to configure
1612  *
1613  *  Configure the K1 power state based on the provided parameter.
1614  *  Assumes semaphore already acquired.
1615  *
1616  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1617  **/
1618 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
1619 {
1620         s32 ret_val = 0;
1621         u32 ctrl_reg = 0;
1622         u32 ctrl_ext = 0;
1623         u32 reg = 0;
1624         u16 kmrn_reg = 0;
1625
1626         ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
1627                                               &kmrn_reg);
1628         if (ret_val)
1629                 return ret_val;
1630
1631         if (k1_enable)
1632                 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
1633         else
1634                 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
1635
1636         ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
1637                                                kmrn_reg);
1638         if (ret_val)
1639                 return ret_val;
1640
1641         udelay(20);
1642         ctrl_ext = er32(CTRL_EXT);
1643         ctrl_reg = er32(CTRL);
1644
1645         reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1646         reg |= E1000_CTRL_FRCSPD;
1647         ew32(CTRL, reg);
1648
1649         ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
1650         e1e_flush();
1651         udelay(20);
1652         ew32(CTRL, ctrl_reg);
1653         ew32(CTRL_EXT, ctrl_ext);
1654         e1e_flush();
1655         udelay(20);
1656
1657         return 0;
1658 }
1659
1660 /**
1661  *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1662  *  @hw:       pointer to the HW structure
1663  *  @d0_state: boolean if entering d0 or d3 device state
1664  *
1665  *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1666  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
1667  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
1668  **/
1669 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1670 {
1671         s32 ret_val = 0;
1672         u32 mac_reg;
1673         u16 oem_reg;
1674
1675         if (hw->mac.type < e1000_pchlan)
1676                 return ret_val;
1677
1678         ret_val = hw->phy.ops.acquire(hw);
1679         if (ret_val)
1680                 return ret_val;
1681
1682         if (hw->mac.type == e1000_pchlan) {
1683                 mac_reg = er32(EXTCNF_CTRL);
1684                 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
1685                         goto release;
1686         }
1687
1688         mac_reg = er32(FEXTNVM);
1689         if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
1690                 goto release;
1691
1692         mac_reg = er32(PHY_CTRL);
1693
1694         ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg);
1695         if (ret_val)
1696                 goto release;
1697
1698         oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1699
1700         if (d0_state) {
1701                 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1702                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1703
1704                 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1705                         oem_reg |= HV_OEM_BITS_LPLU;
1706         } else {
1707                 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
1708                                E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
1709                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1710
1711                 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
1712                                E1000_PHY_CTRL_NOND0A_LPLU))
1713                         oem_reg |= HV_OEM_BITS_LPLU;
1714         }
1715
1716         /* Set Restart auto-neg to activate the bits */
1717         if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
1718             !hw->phy.ops.check_reset_block(hw))
1719                 oem_reg |= HV_OEM_BITS_RESTART_AN;
1720
1721         ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg);
1722
1723 release:
1724         hw->phy.ops.release(hw);
1725
1726         return ret_val;
1727 }
1728
1729
1730 /**
1731  *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
1732  *  @hw:   pointer to the HW structure
1733  **/
1734 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
1735 {
1736         s32 ret_val;
1737         u16 data;
1738
1739         ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
1740         if (ret_val)
1741                 return ret_val;
1742
1743         data |= HV_KMRN_MDIO_SLOW;
1744
1745         ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
1746
1747         return ret_val;
1748 }
1749
1750 /**
1751  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1752  *  done after every PHY reset.
1753  **/
1754 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1755 {
1756         s32 ret_val = 0;
1757         u16 phy_data;
1758
1759         if (hw->mac.type != e1000_pchlan)
1760                 return 0;
1761
1762         /* Set MDIO slow mode before any other MDIO access */
1763         if (hw->phy.type == e1000_phy_82577) {
1764                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1765                 if (ret_val)
1766                         return ret_val;
1767         }
1768
1769         if (((hw->phy.type == e1000_phy_82577) &&
1770              ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1771             ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1772                 /* Disable generation of early preamble */
1773                 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
1774                 if (ret_val)
1775                         return ret_val;
1776
1777                 /* Preamble tuning for SSC */
1778                 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204);
1779                 if (ret_val)
1780                         return ret_val;
1781         }
1782
1783         if (hw->phy.type == e1000_phy_82578) {
1784                 /* Return registers to default by doing a soft reset then
1785                  * writing 0x3140 to the control register.
1786                  */
1787                 if (hw->phy.revision < 2) {
1788                         e1000e_phy_sw_reset(hw);
1789                         ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140);
1790                 }
1791         }
1792
1793         /* Select page 0 */
1794         ret_val = hw->phy.ops.acquire(hw);
1795         if (ret_val)
1796                 return ret_val;
1797
1798         hw->phy.addr = 1;
1799         ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
1800         hw->phy.ops.release(hw);
1801         if (ret_val)
1802                 return ret_val;
1803
1804         /* Configure the K1 Si workaround during phy reset assuming there is
1805          * link so that it disables K1 if link is in 1Gbps.
1806          */
1807         ret_val = e1000_k1_gig_workaround_hv(hw, true);
1808         if (ret_val)
1809                 return ret_val;
1810
1811         /* Workaround for link disconnects on a busy hub in half duplex */
1812         ret_val = hw->phy.ops.acquire(hw);
1813         if (ret_val)
1814                 return ret_val;
1815         ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data);
1816         if (ret_val)
1817                 goto release;
1818         ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF);
1819         if (ret_val)
1820                 goto release;
1821
1822         /* set MSE higher to enable link to stay up when noise is high */
1823         ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
1824 release:
1825         hw->phy.ops.release(hw);
1826
1827         return ret_val;
1828 }
1829
1830 /**
1831  *  e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
1832  *  @hw:   pointer to the HW structure
1833  **/
1834 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
1835 {
1836         u32 mac_reg;
1837         u16 i, phy_reg = 0;
1838         s32 ret_val;
1839
1840         ret_val = hw->phy.ops.acquire(hw);
1841         if (ret_val)
1842                 return;
1843         ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1844         if (ret_val)
1845                 goto release;
1846
1847         /* Copy both RAL/H (rar_entry_count) and SHRAL/H (+4) to PHY */
1848         for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1849                 mac_reg = er32(RAL(i));
1850                 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
1851                                            (u16)(mac_reg & 0xFFFF));
1852                 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
1853                                            (u16)((mac_reg >> 16) & 0xFFFF));
1854
1855                 mac_reg = er32(RAH(i));
1856                 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
1857                                            (u16)(mac_reg & 0xFFFF));
1858                 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
1859                                            (u16)((mac_reg & E1000_RAH_AV)
1860                                                  >> 16));
1861         }
1862
1863         e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1864
1865 release:
1866         hw->phy.ops.release(hw);
1867 }
1868
1869 /**
1870  *  e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
1871  *  with 82579 PHY
1872  *  @hw: pointer to the HW structure
1873  *  @enable: flag to enable/disable workaround when enabling/disabling jumbos
1874  **/
1875 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
1876 {
1877         s32 ret_val = 0;
1878         u16 phy_reg, data;
1879         u32 mac_reg;
1880         u16 i;
1881
1882         if (hw->mac.type < e1000_pch2lan)
1883                 return 0;
1884
1885         /* disable Rx path while enabling/disabling workaround */
1886         e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
1887         ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14));
1888         if (ret_val)
1889                 return ret_val;
1890
1891         if (enable) {
1892                 /* Write Rx addresses (rar_entry_count for RAL/H, +4 for
1893                  * SHRAL/H) and initial CRC values to the MAC
1894                  */
1895                 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1896                         u8 mac_addr[ETH_ALEN] = {0};
1897                         u32 addr_high, addr_low;
1898
1899                         addr_high = er32(RAH(i));
1900                         if (!(addr_high & E1000_RAH_AV))
1901                                 continue;
1902                         addr_low = er32(RAL(i));
1903                         mac_addr[0] = (addr_low & 0xFF);
1904                         mac_addr[1] = ((addr_low >> 8) & 0xFF);
1905                         mac_addr[2] = ((addr_low >> 16) & 0xFF);
1906                         mac_addr[3] = ((addr_low >> 24) & 0xFF);
1907                         mac_addr[4] = (addr_high & 0xFF);
1908                         mac_addr[5] = ((addr_high >> 8) & 0xFF);
1909
1910                         ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr));
1911                 }
1912
1913                 /* Write Rx addresses to the PHY */
1914                 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
1915
1916                 /* Enable jumbo frame workaround in the MAC */
1917                 mac_reg = er32(FFLT_DBG);
1918                 mac_reg &= ~(1 << 14);
1919                 mac_reg |= (7 << 15);
1920                 ew32(FFLT_DBG, mac_reg);
1921
1922                 mac_reg = er32(RCTL);
1923                 mac_reg |= E1000_RCTL_SECRC;
1924                 ew32(RCTL, mac_reg);
1925
1926                 ret_val = e1000e_read_kmrn_reg(hw,
1927                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1928                                                 &data);
1929                 if (ret_val)
1930                         return ret_val;
1931                 ret_val = e1000e_write_kmrn_reg(hw,
1932                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1933                                                 data | (1 << 0));
1934                 if (ret_val)
1935                         return ret_val;
1936                 ret_val = e1000e_read_kmrn_reg(hw,
1937                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1938                                                 &data);
1939                 if (ret_val)
1940                         return ret_val;
1941                 data &= ~(0xF << 8);
1942                 data |= (0xB << 8);
1943                 ret_val = e1000e_write_kmrn_reg(hw,
1944                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1945                                                 data);
1946                 if (ret_val)
1947                         return ret_val;
1948
1949                 /* Enable jumbo frame workaround in the PHY */
1950                 e1e_rphy(hw, PHY_REG(769, 23), &data);
1951                 data &= ~(0x7F << 5);
1952                 data |= (0x37 << 5);
1953                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1954                 if (ret_val)
1955                         return ret_val;
1956                 e1e_rphy(hw, PHY_REG(769, 16), &data);
1957                 data &= ~(1 << 13);
1958                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1959                 if (ret_val)
1960                         return ret_val;
1961                 e1e_rphy(hw, PHY_REG(776, 20), &data);
1962                 data &= ~(0x3FF << 2);
1963                 data |= (0x1A << 2);
1964                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1965                 if (ret_val)
1966                         return ret_val;
1967                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100);
1968                 if (ret_val)
1969                         return ret_val;
1970                 e1e_rphy(hw, HV_PM_CTRL, &data);
1971                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10));
1972                 if (ret_val)
1973                         return ret_val;
1974         } else {
1975                 /* Write MAC register values back to h/w defaults */
1976                 mac_reg = er32(FFLT_DBG);
1977                 mac_reg &= ~(0xF << 14);
1978                 ew32(FFLT_DBG, mac_reg);
1979
1980                 mac_reg = er32(RCTL);
1981                 mac_reg &= ~E1000_RCTL_SECRC;
1982                 ew32(RCTL, mac_reg);
1983
1984                 ret_val = e1000e_read_kmrn_reg(hw,
1985                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1986                                                 &data);
1987                 if (ret_val)
1988                         return ret_val;
1989                 ret_val = e1000e_write_kmrn_reg(hw,
1990                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1991                                                 data & ~(1 << 0));
1992                 if (ret_val)
1993                         return ret_val;
1994                 ret_val = e1000e_read_kmrn_reg(hw,
1995                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1996                                                 &data);
1997                 if (ret_val)
1998                         return ret_val;
1999                 data &= ~(0xF << 8);
2000                 data |= (0xB << 8);
2001                 ret_val = e1000e_write_kmrn_reg(hw,
2002                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2003                                                 data);
2004                 if (ret_val)
2005                         return ret_val;
2006
2007                 /* Write PHY register values back to h/w defaults */
2008                 e1e_rphy(hw, PHY_REG(769, 23), &data);
2009                 data &= ~(0x7F << 5);
2010                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2011                 if (ret_val)
2012                         return ret_val;
2013                 e1e_rphy(hw, PHY_REG(769, 16), &data);
2014                 data |= (1 << 13);
2015                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2016                 if (ret_val)
2017                         return ret_val;
2018                 e1e_rphy(hw, PHY_REG(776, 20), &data);
2019                 data &= ~(0x3FF << 2);
2020                 data |= (0x8 << 2);
2021                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2022                 if (ret_val)
2023                         return ret_val;
2024                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
2025                 if (ret_val)
2026                         return ret_val;
2027                 e1e_rphy(hw, HV_PM_CTRL, &data);
2028                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10));
2029                 if (ret_val)
2030                         return ret_val;
2031         }
2032
2033         /* re-enable Rx path after enabling/disabling workaround */
2034         return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14));
2035 }
2036
2037 /**
2038  *  e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2039  *  done after every PHY reset.
2040  **/
2041 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2042 {
2043         s32 ret_val = 0;
2044
2045         if (hw->mac.type != e1000_pch2lan)
2046                 return 0;
2047
2048         /* Set MDIO slow mode before any other MDIO access */
2049         ret_val = e1000_set_mdio_slow_mode_hv(hw);
2050         if (ret_val)
2051                 return ret_val;
2052
2053         ret_val = hw->phy.ops.acquire(hw);
2054         if (ret_val)
2055                 return ret_val;
2056         /* set MSE higher to enable link to stay up when noise is high */
2057         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2058         if (ret_val)
2059                 goto release;
2060         /* drop link after 5 times MSE threshold was reached */
2061         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2062 release:
2063         hw->phy.ops.release(hw);
2064
2065         return ret_val;
2066 }
2067
2068 /**
2069  *  e1000_k1_gig_workaround_lv - K1 Si workaround
2070  *  @hw:   pointer to the HW structure
2071  *
2072  *  Workaround to set the K1 beacon duration for 82579 parts
2073  **/
2074 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2075 {
2076         s32 ret_val = 0;
2077         u16 status_reg = 0;
2078         u32 mac_reg;
2079         u16 phy_reg;
2080
2081         if (hw->mac.type != e1000_pch2lan)
2082                 return 0;
2083
2084         /* Set K1 beacon duration based on 1Gbps speed or otherwise */
2085         ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
2086         if (ret_val)
2087                 return ret_val;
2088
2089         if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2090             == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2091                 mac_reg = er32(FEXTNVM4);
2092                 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
2093
2094                 ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg);
2095                 if (ret_val)
2096                         return ret_val;
2097
2098                 if (status_reg & HV_M_STATUS_SPEED_1000) {
2099                         u16 pm_phy_reg;
2100
2101                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
2102                         phy_reg &= ~I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
2103                         /* LV 1G Packet drop issue wa  */
2104                         ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg);
2105                         if (ret_val)
2106                                 return ret_val;
2107                         pm_phy_reg &= ~HV_PM_CTRL_PLL_STOP_IN_K1_GIGA;
2108                         ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg);
2109                         if (ret_val)
2110                                 return ret_val;
2111                 } else {
2112                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
2113                         phy_reg |= I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
2114                 }
2115                 ew32(FEXTNVM4, mac_reg);
2116                 ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg);
2117         }
2118
2119         return ret_val;
2120 }
2121
2122 /**
2123  *  e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2124  *  @hw:   pointer to the HW structure
2125  *  @gate: boolean set to true to gate, false to ungate
2126  *
2127  *  Gate/ungate the automatic PHY configuration via hardware; perform
2128  *  the configuration via software instead.
2129  **/
2130 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2131 {
2132         u32 extcnf_ctrl;
2133
2134         if (hw->mac.type < e1000_pch2lan)
2135                 return;
2136
2137         extcnf_ctrl = er32(EXTCNF_CTRL);
2138
2139         if (gate)
2140                 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2141         else
2142                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2143
2144         ew32(EXTCNF_CTRL, extcnf_ctrl);
2145 }
2146
2147 /**
2148  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
2149  *  @hw: pointer to the HW structure
2150  *
2151  *  Check the appropriate indication the MAC has finished configuring the
2152  *  PHY after a software reset.
2153  **/
2154 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2155 {
2156         u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
2157
2158         /* Wait for basic configuration completes before proceeding */
2159         do {
2160                 data = er32(STATUS);
2161                 data &= E1000_STATUS_LAN_INIT_DONE;
2162                 udelay(100);
2163         } while ((!data) && --loop);
2164
2165         /* If basic configuration is incomplete before the above loop
2166          * count reaches 0, loading the configuration from NVM will
2167          * leave the PHY in a bad state possibly resulting in no link.
2168          */
2169         if (loop == 0)
2170                 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
2171
2172         /* Clear the Init Done bit for the next init event */
2173         data = er32(STATUS);
2174         data &= ~E1000_STATUS_LAN_INIT_DONE;
2175         ew32(STATUS, data);
2176 }
2177
2178 /**
2179  *  e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
2180  *  @hw: pointer to the HW structure
2181  **/
2182 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
2183 {
2184         s32 ret_val = 0;
2185         u16 reg;
2186
2187         if (hw->phy.ops.check_reset_block(hw))
2188                 return 0;
2189
2190         /* Allow time for h/w to get to quiescent state after reset */
2191         usleep_range(10000, 20000);
2192
2193         /* Perform any necessary post-reset workarounds */
2194         switch (hw->mac.type) {
2195         case e1000_pchlan:
2196                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2197                 if (ret_val)
2198                         return ret_val;
2199                 break;
2200         case e1000_pch2lan:
2201                 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
2202                 if (ret_val)
2203                         return ret_val;
2204                 break;
2205         default:
2206                 break;
2207         }
2208
2209         /* Clear the host wakeup bit after lcd reset */
2210         if (hw->mac.type >= e1000_pchlan) {
2211                 e1e_rphy(hw, BM_PORT_GEN_CFG, &reg);
2212                 reg &= ~BM_WUC_HOST_WU_BIT;
2213                 e1e_wphy(hw, BM_PORT_GEN_CFG, reg);
2214         }
2215
2216         /* Configure the LCD with the extended configuration region in NVM */
2217         ret_val = e1000_sw_lcd_config_ich8lan(hw);
2218         if (ret_val)
2219                 return ret_val;
2220
2221         /* Configure the LCD with the OEM bits in NVM */
2222         ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2223
2224         if (hw->mac.type == e1000_pch2lan) {
2225                 /* Ungate automatic PHY configuration on non-managed 82579 */
2226                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
2227                         usleep_range(10000, 20000);
2228                         e1000_gate_hw_phy_config_ich8lan(hw, false);
2229                 }
2230
2231                 /* Set EEE LPI Update Timer to 200usec */
2232                 ret_val = hw->phy.ops.acquire(hw);
2233                 if (ret_val)
2234                         return ret_val;
2235                 ret_val = e1000_write_emi_reg_locked(hw,
2236                                                      I82579_LPI_UPDATE_TIMER,
2237                                                      0x1387);
2238                 hw->phy.ops.release(hw);
2239         }
2240
2241         return ret_val;
2242 }
2243
2244 /**
2245  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
2246  *  @hw: pointer to the HW structure
2247  *
2248  *  Resets the PHY
2249  *  This is a function pointer entry point called by drivers
2250  *  or other shared routines.
2251  **/
2252 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
2253 {
2254         s32 ret_val = 0;
2255
2256         /* Gate automatic PHY configuration by hardware on non-managed 82579 */
2257         if ((hw->mac.type == e1000_pch2lan) &&
2258             !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
2259                 e1000_gate_hw_phy_config_ich8lan(hw, true);
2260
2261         ret_val = e1000e_phy_hw_reset_generic(hw);
2262         if (ret_val)
2263                 return ret_val;
2264
2265         return e1000_post_phy_reset_ich8lan(hw);
2266 }
2267
2268 /**
2269  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
2270  *  @hw: pointer to the HW structure
2271  *  @active: true to enable LPLU, false to disable
2272  *
2273  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
2274  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
2275  *  the phy speed. This function will manually set the LPLU bit and restart
2276  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
2277  *  since it configures the same bit.
2278  **/
2279 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
2280 {
2281         s32 ret_val = 0;
2282         u16 oem_reg;
2283
2284         ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
2285         if (ret_val)
2286                 return ret_val;
2287
2288         if (active)
2289                 oem_reg |= HV_OEM_BITS_LPLU;
2290         else
2291                 oem_reg &= ~HV_OEM_BITS_LPLU;
2292
2293         if (!hw->phy.ops.check_reset_block(hw))
2294                 oem_reg |= HV_OEM_BITS_RESTART_AN;
2295
2296         return e1e_wphy(hw, HV_OEM_BITS, oem_reg);
2297 }
2298
2299 /**
2300  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
2301  *  @hw: pointer to the HW structure
2302  *  @active: true to enable LPLU, false to disable
2303  *
2304  *  Sets the LPLU D0 state according to the active flag.  When
2305  *  activating LPLU this function also disables smart speed
2306  *  and vice versa.  LPLU will not be activated unless the
2307  *  device autonegotiation advertisement meets standards of
2308  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
2309  *  This is a function pointer entry point only called by
2310  *  PHY setup routines.
2311  **/
2312 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2313 {
2314         struct e1000_phy_info *phy = &hw->phy;
2315         u32 phy_ctrl;
2316         s32 ret_val = 0;
2317         u16 data;
2318
2319         if (phy->type == e1000_phy_ife)
2320                 return 0;
2321
2322         phy_ctrl = er32(PHY_CTRL);
2323
2324         if (active) {
2325                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2326                 ew32(PHY_CTRL, phy_ctrl);
2327
2328                 if (phy->type != e1000_phy_igp_3)
2329                         return 0;
2330
2331                 /* Call gig speed drop workaround on LPLU before accessing
2332                  * any PHY registers
2333                  */
2334                 if (hw->mac.type == e1000_ich8lan)
2335                         e1000e_gig_downshift_workaround_ich8lan(hw);
2336
2337                 /* When LPLU is enabled, we should disable SmartSpeed */
2338                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
2339                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2340                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
2341                 if (ret_val)
2342                         return ret_val;
2343         } else {
2344                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2345                 ew32(PHY_CTRL, phy_ctrl);
2346
2347                 if (phy->type != e1000_phy_igp_3)
2348                         return 0;
2349
2350                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
2351                  * during Dx states where the power conservation is most
2352                  * important.  During driver activity we should enable
2353                  * SmartSpeed, so performance is maintained.
2354                  */
2355                 if (phy->smart_speed == e1000_smart_speed_on) {
2356                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2357                                            &data);
2358                         if (ret_val)
2359                                 return ret_val;
2360
2361                         data |= IGP01E1000_PSCFR_SMART_SPEED;
2362                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2363                                            data);
2364                         if (ret_val)
2365                                 return ret_val;
2366                 } else if (phy->smart_speed == e1000_smart_speed_off) {
2367                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2368                                            &data);
2369                         if (ret_val)
2370                                 return ret_val;
2371
2372                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2373                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2374                                            data);
2375                         if (ret_val)
2376                                 return ret_val;
2377                 }
2378         }
2379
2380         return 0;
2381 }
2382
2383 /**
2384  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
2385  *  @hw: pointer to the HW structure
2386  *  @active: true to enable LPLU, false to disable
2387  *
2388  *  Sets the LPLU D3 state according to the active flag.  When
2389  *  activating LPLU this function also disables smart speed
2390  *  and vice versa.  LPLU will not be activated unless the
2391  *  device autonegotiation advertisement meets standards of
2392  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
2393  *  This is a function pointer entry point only called by
2394  *  PHY setup routines.
2395  **/
2396 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2397 {
2398         struct e1000_phy_info *phy = &hw->phy;
2399         u32 phy_ctrl;
2400         s32 ret_val = 0;
2401         u16 data;
2402
2403         phy_ctrl = er32(PHY_CTRL);
2404
2405         if (!active) {
2406                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
2407                 ew32(PHY_CTRL, phy_ctrl);
2408
2409                 if (phy->type != e1000_phy_igp_3)
2410                         return 0;
2411
2412                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
2413                  * during Dx states where the power conservation is most
2414                  * important.  During driver activity we should enable
2415                  * SmartSpeed, so performance is maintained.
2416                  */
2417                 if (phy->smart_speed == e1000_smart_speed_on) {
2418                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2419                                            &data);
2420                         if (ret_val)
2421                                 return ret_val;
2422
2423                         data |= IGP01E1000_PSCFR_SMART_SPEED;
2424                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2425                                            data);
2426                         if (ret_val)
2427                                 return ret_val;
2428                 } else if (phy->smart_speed == e1000_smart_speed_off) {
2429                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2430                                            &data);
2431                         if (ret_val)
2432                                 return ret_val;
2433
2434                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2435                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2436                                            data);
2437                         if (ret_val)
2438                                 return ret_val;
2439                 }
2440         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
2441                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
2442                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
2443                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
2444                 ew32(PHY_CTRL, phy_ctrl);
2445
2446                 if (phy->type != e1000_phy_igp_3)
2447                         return 0;
2448
2449                 /* Call gig speed drop workaround on LPLU before accessing
2450                  * any PHY registers
2451                  */
2452                 if (hw->mac.type == e1000_ich8lan)
2453                         e1000e_gig_downshift_workaround_ich8lan(hw);
2454
2455                 /* When LPLU is enabled, we should disable SmartSpeed */
2456                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
2457                 if (ret_val)
2458                         return ret_val;
2459
2460                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2461                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
2462         }
2463
2464         return ret_val;
2465 }
2466
2467 /**
2468  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
2469  *  @hw: pointer to the HW structure
2470  *  @bank:  pointer to the variable that returns the active bank
2471  *
2472  *  Reads signature byte from the NVM using the flash access registers.
2473  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
2474  **/
2475 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
2476 {
2477         u32 eecd;
2478         struct e1000_nvm_info *nvm = &hw->nvm;
2479         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
2480         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
2481         u8 sig_byte = 0;
2482         s32 ret_val;
2483
2484         switch (hw->mac.type) {
2485         case e1000_ich8lan:
2486         case e1000_ich9lan:
2487                 eecd = er32(EECD);
2488                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
2489                     E1000_EECD_SEC1VAL_VALID_MASK) {
2490                         if (eecd & E1000_EECD_SEC1VAL)
2491                                 *bank = 1;
2492                         else
2493                                 *bank = 0;
2494
2495                         return 0;
2496                 }
2497                 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n");
2498                 /* fall-thru */
2499         default:
2500                 /* set bank to 0 in case flash read fails */
2501                 *bank = 0;
2502
2503                 /* Check bank 0 */
2504                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
2505                                                         &sig_byte);
2506                 if (ret_val)
2507                         return ret_val;
2508                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2509                     E1000_ICH_NVM_SIG_VALUE) {
2510                         *bank = 0;
2511                         return 0;
2512                 }
2513
2514                 /* Check bank 1 */
2515                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
2516                                                         bank1_offset,
2517                                                         &sig_byte);
2518                 if (ret_val)
2519                         return ret_val;
2520                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2521                     E1000_ICH_NVM_SIG_VALUE) {
2522                         *bank = 1;
2523                         return 0;
2524                 }
2525
2526                 e_dbg("ERROR: No valid NVM bank present\n");
2527                 return -E1000_ERR_NVM;
2528         }
2529 }
2530
2531 /**
2532  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
2533  *  @hw: pointer to the HW structure
2534  *  @offset: The offset (in bytes) of the word(s) to read.
2535  *  @words: Size of data to read in words
2536  *  @data: Pointer to the word(s) to read at offset.
2537  *
2538  *  Reads a word(s) from the NVM using the flash access registers.
2539  **/
2540 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2541                                   u16 *data)
2542 {
2543         struct e1000_nvm_info *nvm = &hw->nvm;
2544         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2545         u32 act_offset;
2546         s32 ret_val = 0;
2547         u32 bank = 0;
2548         u16 i, word;
2549
2550         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2551             (words == 0)) {
2552                 e_dbg("nvm parameter(s) out of bounds\n");
2553                 ret_val = -E1000_ERR_NVM;
2554                 goto out;
2555         }
2556
2557         nvm->ops.acquire(hw);
2558
2559         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2560         if (ret_val) {
2561                 e_dbg("Could not detect valid bank, assuming bank 0\n");
2562                 bank = 0;
2563         }
2564
2565         act_offset = (bank) ? nvm->flash_bank_size : 0;
2566         act_offset += offset;
2567
2568         ret_val = 0;
2569         for (i = 0; i < words; i++) {
2570                 if (dev_spec->shadow_ram[offset+i].modified) {
2571                         data[i] = dev_spec->shadow_ram[offset+i].value;
2572                 } else {
2573                         ret_val = e1000_read_flash_word_ich8lan(hw,
2574                                                                 act_offset + i,
2575                                                                 &word);
2576                         if (ret_val)
2577                                 break;
2578                         data[i] = word;
2579                 }
2580         }
2581
2582         nvm->ops.release(hw);
2583
2584 out:
2585         if (ret_val)
2586                 e_dbg("NVM read error: %d\n", ret_val);
2587
2588         return ret_val;
2589 }
2590
2591 /**
2592  *  e1000_flash_cycle_init_ich8lan - Initialize flash
2593  *  @hw: pointer to the HW structure
2594  *
2595  *  This function does initial flash setup so that a new read/write/erase cycle
2596  *  can be started.
2597  **/
2598 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
2599 {
2600         union ich8_hws_flash_status hsfsts;
2601         s32 ret_val = -E1000_ERR_NVM;
2602
2603         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2604
2605         /* Check if the flash descriptor is valid */
2606         if (!hsfsts.hsf_status.fldesvalid) {
2607                 e_dbg("Flash descriptor invalid.  SW Sequencing must be used.\n");
2608                 return -E1000_ERR_NVM;
2609         }
2610
2611         /* Clear FCERR and DAEL in hw status by writing 1 */
2612         hsfsts.hsf_status.flcerr = 1;
2613         hsfsts.hsf_status.dael = 1;
2614
2615         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2616
2617         /* Either we should have a hardware SPI cycle in progress
2618          * bit to check against, in order to start a new cycle or
2619          * FDONE bit should be changed in the hardware so that it
2620          * is 1 after hardware reset, which can then be used as an
2621          * indication whether a cycle is in progress or has been
2622          * completed.
2623          */
2624
2625         if (!hsfsts.hsf_status.flcinprog) {
2626                 /* There is no cycle running at present,
2627                  * so we can start a cycle.
2628                  * Begin by setting Flash Cycle Done.
2629                  */
2630                 hsfsts.hsf_status.flcdone = 1;
2631                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2632                 ret_val = 0;
2633         } else {
2634                 s32 i;
2635
2636                 /* Otherwise poll for sometime so the current
2637                  * cycle has a chance to end before giving up.
2638                  */
2639                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
2640                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2641                         if (!hsfsts.hsf_status.flcinprog) {
2642                                 ret_val = 0;
2643                                 break;
2644                         }
2645                         udelay(1);
2646                 }
2647                 if (!ret_val) {
2648                         /* Successful in waiting for previous cycle to timeout,
2649                          * now set the Flash Cycle Done.
2650                          */
2651                         hsfsts.hsf_status.flcdone = 1;
2652                         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2653                 } else {
2654                         e_dbg("Flash controller busy, cannot get access\n");
2655                 }
2656         }
2657
2658         return ret_val;
2659 }
2660
2661 /**
2662  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
2663  *  @hw: pointer to the HW structure
2664  *  @timeout: maximum time to wait for completion
2665  *
2666  *  This function starts a flash cycle and waits for its completion.
2667  **/
2668 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
2669 {
2670         union ich8_hws_flash_ctrl hsflctl;
2671         union ich8_hws_flash_status hsfsts;
2672         u32 i = 0;
2673
2674         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
2675         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2676         hsflctl.hsf_ctrl.flcgo = 1;
2677         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2678
2679         /* wait till FDONE bit is set to 1 */
2680         do {
2681                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2682                 if (hsfsts.hsf_status.flcdone)
2683                         break;
2684                 udelay(1);
2685         } while (i++ < timeout);
2686
2687         if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
2688                 return 0;
2689
2690         return -E1000_ERR_NVM;
2691 }
2692
2693 /**
2694  *  e1000_read_flash_word_ich8lan - Read word from flash
2695  *  @hw: pointer to the HW structure
2696  *  @offset: offset to data location
2697  *  @data: pointer to the location for storing the data
2698  *
2699  *  Reads the flash word at offset into data.  Offset is converted
2700  *  to bytes before read.
2701  **/
2702 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
2703                                          u16 *data)
2704 {
2705         /* Must convert offset into bytes. */
2706         offset <<= 1;
2707
2708         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
2709 }
2710
2711 /**
2712  *  e1000_read_flash_byte_ich8lan - Read byte from flash
2713  *  @hw: pointer to the HW structure
2714  *  @offset: The offset of the byte to read.
2715  *  @data: Pointer to a byte to store the value read.
2716  *
2717  *  Reads a single byte from the NVM using the flash access registers.
2718  **/
2719 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2720                                          u8 *data)
2721 {
2722         s32 ret_val;
2723         u16 word = 0;
2724
2725         ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
2726         if (ret_val)
2727                 return ret_val;
2728
2729         *data = (u8)word;
2730
2731         return 0;
2732 }
2733
2734 /**
2735  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
2736  *  @hw: pointer to the HW structure
2737  *  @offset: The offset (in bytes) of the byte or word to read.
2738  *  @size: Size of data to read, 1=byte 2=word
2739  *  @data: Pointer to the word to store the value read.
2740  *
2741  *  Reads a byte or word from the NVM using the flash access registers.
2742  **/
2743 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2744                                          u8 size, u16 *data)
2745 {
2746         union ich8_hws_flash_status hsfsts;
2747         union ich8_hws_flash_ctrl hsflctl;
2748         u32 flash_linear_addr;
2749         u32 flash_data = 0;
2750         s32 ret_val = -E1000_ERR_NVM;
2751         u8 count = 0;
2752
2753         if (size < 1  || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
2754                 return -E1000_ERR_NVM;
2755
2756         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2757                             hw->nvm.flash_base_addr;
2758
2759         do {
2760                 udelay(1);
2761                 /* Steps */
2762                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2763                 if (ret_val)
2764                         break;
2765
2766                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2767                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2768                 hsflctl.hsf_ctrl.fldbcount = size - 1;
2769                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
2770                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2771
2772                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2773
2774                 ret_val = e1000_flash_cycle_ich8lan(hw,
2775                                                 ICH_FLASH_READ_COMMAND_TIMEOUT);
2776
2777                 /* Check if FCERR is set to 1, if set to 1, clear it
2778                  * and try the whole sequence a few more times, else
2779                  * read in (shift in) the Flash Data0, the order is
2780                  * least significant byte first msb to lsb
2781                  */
2782                 if (!ret_val) {
2783                         flash_data = er32flash(ICH_FLASH_FDATA0);
2784                         if (size == 1)
2785                                 *data = (u8)(flash_data & 0x000000FF);
2786                         else if (size == 2)
2787                                 *data = (u16)(flash_data & 0x0000FFFF);
2788                         break;
2789                 } else {
2790                         /* If we've gotten here, then things are probably
2791                          * completely hosed, but if the error condition is
2792                          * detected, it won't hurt to give it another try...
2793                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
2794                          */
2795                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2796                         if (hsfsts.hsf_status.flcerr) {
2797                                 /* Repeat for some time before giving up. */
2798                                 continue;
2799                         } else if (!hsfsts.hsf_status.flcdone) {
2800                                 e_dbg("Timeout error - flash cycle did not complete.\n");
2801                                 break;
2802                         }
2803                 }
2804         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2805
2806         return ret_val;
2807 }
2808
2809 /**
2810  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
2811  *  @hw: pointer to the HW structure
2812  *  @offset: The offset (in bytes) of the word(s) to write.
2813  *  @words: Size of data to write in words
2814  *  @data: Pointer to the word(s) to write at offset.
2815  *
2816  *  Writes a byte or word to the NVM using the flash access registers.
2817  **/
2818 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2819                                    u16 *data)
2820 {
2821         struct e1000_nvm_info *nvm = &hw->nvm;
2822         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2823         u16 i;
2824
2825         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2826             (words == 0)) {
2827                 e_dbg("nvm parameter(s) out of bounds\n");
2828                 return -E1000_ERR_NVM;
2829         }
2830
2831         nvm->ops.acquire(hw);
2832
2833         for (i = 0; i < words; i++) {
2834                 dev_spec->shadow_ram[offset+i].modified = true;
2835                 dev_spec->shadow_ram[offset+i].value = data[i];
2836         }
2837
2838         nvm->ops.release(hw);
2839
2840         return 0;
2841 }
2842
2843 /**
2844  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
2845  *  @hw: pointer to the HW structure
2846  *
2847  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
2848  *  which writes the checksum to the shadow ram.  The changes in the shadow
2849  *  ram are then committed to the EEPROM by processing each bank at a time
2850  *  checking for the modified bit and writing only the pending changes.
2851  *  After a successful commit, the shadow ram is cleared and is ready for
2852  *  future writes.
2853  **/
2854 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2855 {
2856         struct e1000_nvm_info *nvm = &hw->nvm;
2857         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2858         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
2859         s32 ret_val;
2860         u16 data;
2861
2862         ret_val = e1000e_update_nvm_checksum_generic(hw);
2863         if (ret_val)
2864                 goto out;
2865
2866         if (nvm->type != e1000_nvm_flash_sw)
2867                 goto out;
2868
2869         nvm->ops.acquire(hw);
2870
2871         /* We're writing to the opposite bank so if we're on bank 1,
2872          * write to bank 0 etc.  We also need to erase the segment that
2873          * is going to be written
2874          */
2875         ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2876         if (ret_val) {
2877                 e_dbg("Could not detect valid bank, assuming bank 0\n");
2878                 bank = 0;
2879         }
2880
2881         if (bank == 0) {
2882                 new_bank_offset = nvm->flash_bank_size;
2883                 old_bank_offset = 0;
2884                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
2885                 if (ret_val)
2886                         goto release;
2887         } else {
2888                 old_bank_offset = nvm->flash_bank_size;
2889                 new_bank_offset = 0;
2890                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
2891                 if (ret_val)
2892                         goto release;
2893         }
2894
2895         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2896                 /* Determine whether to write the value stored
2897                  * in the other NVM bank or a modified value stored
2898                  * in the shadow RAM
2899                  */
2900                 if (dev_spec->shadow_ram[i].modified) {
2901                         data = dev_spec->shadow_ram[i].value;
2902                 } else {
2903                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
2904                                                                 old_bank_offset,
2905                                                                 &data);
2906                         if (ret_val)
2907                                 break;
2908                 }
2909
2910                 /* If the word is 0x13, then make sure the signature bits
2911                  * (15:14) are 11b until the commit has completed.
2912                  * This will allow us to write 10b which indicates the
2913                  * signature is valid.  We want to do this after the write
2914                  * has completed so that we don't mark the segment valid
2915                  * while the write is still in progress
2916                  */
2917                 if (i == E1000_ICH_NVM_SIG_WORD)
2918                         data |= E1000_ICH_NVM_SIG_MASK;
2919
2920                 /* Convert offset to bytes. */
2921                 act_offset = (i + new_bank_offset) << 1;
2922
2923                 udelay(100);
2924                 /* Write the bytes to the new bank. */
2925                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2926                                                                act_offset,
2927                                                                (u8)data);
2928                 if (ret_val)
2929                         break;
2930
2931                 udelay(100);
2932                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2933                                                           act_offset + 1,
2934                                                           (u8)(data >> 8));
2935                 if (ret_val)
2936                         break;
2937         }
2938
2939         /* Don't bother writing the segment valid bits if sector
2940          * programming failed.
2941          */
2942         if (ret_val) {
2943                 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
2944                 e_dbg("Flash commit failed.\n");
2945                 goto release;
2946         }
2947
2948         /* Finally validate the new segment by setting bit 15:14
2949          * to 10b in word 0x13 , this can be done without an
2950          * erase as well since these bits are 11 to start with
2951          * and we need to change bit 14 to 0b
2952          */
2953         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
2954         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
2955         if (ret_val)
2956                 goto release;
2957
2958         data &= 0xBFFF;
2959         ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2960                                                        act_offset * 2 + 1,
2961                                                        (u8)(data >> 8));
2962         if (ret_val)
2963                 goto release;
2964
2965         /* And invalidate the previously valid segment by setting
2966          * its signature word (0x13) high_byte to 0b. This can be
2967          * done without an erase because flash erase sets all bits
2968          * to 1's. We can write 1's to 0's without an erase
2969          */
2970         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
2971         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
2972         if (ret_val)
2973                 goto release;
2974
2975         /* Great!  Everything worked, we can now clear the cached entries. */
2976         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2977                 dev_spec->shadow_ram[i].modified = false;
2978                 dev_spec->shadow_ram[i].value = 0xFFFF;
2979         }
2980
2981 release:
2982         nvm->ops.release(hw);
2983
2984         /* Reload the EEPROM, or else modifications will not appear
2985          * until after the next adapter reset.
2986          */
2987         if (!ret_val) {
2988                 nvm->ops.reload(hw);
2989                 usleep_range(10000, 20000);
2990         }
2991
2992 out:
2993         if (ret_val)
2994                 e_dbg("NVM update error: %d\n", ret_val);
2995
2996         return ret_val;
2997 }
2998
2999 /**
3000  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
3001  *  @hw: pointer to the HW structure
3002  *
3003  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
3004  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
3005  *  calculated, in which case we need to calculate the checksum and set bit 6.
3006  **/
3007 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
3008 {
3009         s32 ret_val;
3010         u16 data;
3011         u16 word;
3012         u16 valid_csum_mask;
3013
3014         /* Read NVM and check Invalid Image CSUM bit.  If this bit is 0,
3015          * the checksum needs to be fixed.  This bit is an indication that
3016          * the NVM was prepared by OEM software and did not calculate
3017          * the checksum...a likely scenario.
3018          */
3019         switch (hw->mac.type) {
3020         case e1000_pch_lpt:
3021                 word = NVM_COMPAT;
3022                 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
3023                 break;
3024         default:
3025                 word = NVM_FUTURE_INIT_WORD1;
3026                 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
3027                 break;
3028         }
3029
3030         ret_val = e1000_read_nvm(hw, word, 1, &data);
3031         if (ret_val)
3032                 return ret_val;
3033
3034         if (!(data & valid_csum_mask)) {
3035                 data |= valid_csum_mask;
3036                 ret_val = e1000_write_nvm(hw, word, 1, &data);
3037                 if (ret_val)
3038                         return ret_val;
3039                 ret_val = e1000e_update_nvm_checksum(hw);
3040                 if (ret_val)
3041                         return ret_val;
3042         }
3043
3044         return e1000e_validate_nvm_checksum_generic(hw);
3045 }
3046
3047 /**
3048  *  e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
3049  *  @hw: pointer to the HW structure
3050  *
3051  *  To prevent malicious write/erase of the NVM, set it to be read-only
3052  *  so that the hardware ignores all write/erase cycles of the NVM via
3053  *  the flash control registers.  The shadow-ram copy of the NVM will
3054  *  still be updated, however any updates to this copy will not stick
3055  *  across driver reloads.
3056  **/
3057 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
3058 {
3059         struct e1000_nvm_info *nvm = &hw->nvm;
3060         union ich8_flash_protected_range pr0;
3061         union ich8_hws_flash_status hsfsts;
3062         u32 gfpreg;
3063
3064         nvm->ops.acquire(hw);
3065
3066         gfpreg = er32flash(ICH_FLASH_GFPREG);
3067
3068         /* Write-protect GbE Sector of NVM */
3069         pr0.regval = er32flash(ICH_FLASH_PR0);
3070         pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
3071         pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
3072         pr0.range.wpe = true;
3073         ew32flash(ICH_FLASH_PR0, pr0.regval);
3074
3075         /* Lock down a subset of GbE Flash Control Registers, e.g.
3076          * PR0 to prevent the write-protection from being lifted.
3077          * Once FLOCKDN is set, the registers protected by it cannot
3078          * be written until FLOCKDN is cleared by a hardware reset.
3079          */
3080         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3081         hsfsts.hsf_status.flockdn = true;
3082         ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3083
3084         nvm->ops.release(hw);
3085 }
3086
3087 /**
3088  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
3089  *  @hw: pointer to the HW structure
3090  *  @offset: The offset (in bytes) of the byte/word to read.
3091  *  @size: Size of data to read, 1=byte 2=word
3092  *  @data: The byte(s) to write to the NVM.
3093  *
3094  *  Writes one/two bytes to the NVM using the flash access registers.
3095  **/
3096 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3097                                           u8 size, u16 data)
3098 {
3099         union ich8_hws_flash_status hsfsts;
3100         union ich8_hws_flash_ctrl hsflctl;
3101         u32 flash_linear_addr;
3102         u32 flash_data = 0;
3103         s32 ret_val;
3104         u8 count = 0;
3105
3106         if (size < 1 || size > 2 || data > size * 0xff ||
3107             offset > ICH_FLASH_LINEAR_ADDR_MASK)
3108                 return -E1000_ERR_NVM;
3109
3110         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3111                             hw->nvm.flash_base_addr;
3112
3113         do {
3114                 udelay(1);
3115                 /* Steps */
3116                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3117                 if (ret_val)
3118                         break;
3119
3120                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3121                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3122                 hsflctl.hsf_ctrl.fldbcount = size -1;
3123                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
3124                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3125
3126                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3127
3128                 if (size == 1)
3129                         flash_data = (u32)data & 0x00FF;
3130                 else
3131                         flash_data = (u32)data;
3132
3133                 ew32flash(ICH_FLASH_FDATA0, flash_data);
3134
3135                 /* check if FCERR is set to 1 , if set to 1, clear it
3136                  * and try the whole sequence a few more times else done
3137                  */
3138                 ret_val = e1000_flash_cycle_ich8lan(hw,
3139                                                ICH_FLASH_WRITE_COMMAND_TIMEOUT);
3140                 if (!ret_val)
3141                         break;
3142
3143                 /* If we're here, then things are most likely
3144                  * completely hosed, but if the error condition
3145                  * is detected, it won't hurt to give it another
3146                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
3147                  */
3148                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3149                 if (hsfsts.hsf_status.flcerr)
3150                         /* Repeat for some time before giving up. */
3151                         continue;
3152                 if (!hsfsts.hsf_status.flcdone) {
3153                         e_dbg("Timeout error - flash cycle did not complete.\n");
3154                         break;
3155                 }
3156         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3157
3158         return ret_val;
3159 }
3160
3161 /**
3162  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
3163  *  @hw: pointer to the HW structure
3164  *  @offset: The index of the byte to read.
3165  *  @data: The byte to write to the NVM.
3166  *
3167  *  Writes a single byte to the NVM using the flash access registers.
3168  **/
3169 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3170                                           u8 data)
3171 {
3172         u16 word = (u16)data;
3173
3174         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
3175 }
3176
3177 /**
3178  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
3179  *  @hw: pointer to the HW structure
3180  *  @offset: The offset of the byte to write.
3181  *  @byte: The byte to write to the NVM.
3182  *
3183  *  Writes a single byte to the NVM using the flash access registers.
3184  *  Goes through a retry algorithm before giving up.
3185  **/
3186 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
3187                                                 u32 offset, u8 byte)
3188 {
3189         s32 ret_val;
3190         u16 program_retries;
3191
3192         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3193         if (!ret_val)
3194                 return ret_val;
3195
3196         for (program_retries = 0; program_retries < 100; program_retries++) {
3197                 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
3198                 udelay(100);
3199                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3200                 if (!ret_val)
3201                         break;
3202         }
3203         if (program_retries == 100)
3204                 return -E1000_ERR_NVM;
3205
3206         return 0;
3207 }
3208
3209 /**
3210  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
3211  *  @hw: pointer to the HW structure
3212  *  @bank: 0 for first bank, 1 for second bank, etc.
3213  *
3214  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
3215  *  bank N is 4096 * N + flash_reg_addr.
3216  **/
3217 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
3218 {
3219         struct e1000_nvm_info *nvm = &hw->nvm;
3220         union ich8_hws_flash_status hsfsts;
3221         union ich8_hws_flash_ctrl hsflctl;
3222         u32 flash_linear_addr;
3223         /* bank size is in 16bit words - adjust to bytes */
3224         u32 flash_bank_size = nvm->flash_bank_size * 2;
3225         s32 ret_val;
3226         s32 count = 0;
3227         s32 j, iteration, sector_size;
3228
3229         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3230
3231         /* Determine HW Sector size: Read BERASE bits of hw flash status
3232          * register
3233          * 00: The Hw sector is 256 bytes, hence we need to erase 16
3234          *     consecutive sectors.  The start index for the nth Hw sector
3235          *     can be calculated as = bank * 4096 + n * 256
3236          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
3237          *     The start index for the nth Hw sector can be calculated
3238          *     as = bank * 4096
3239          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
3240          *     (ich9 only, otherwise error condition)
3241          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
3242          */
3243         switch (hsfsts.hsf_status.berasesz) {
3244         case 0:
3245                 /* Hw sector size 256 */
3246                 sector_size = ICH_FLASH_SEG_SIZE_256;
3247                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
3248                 break;
3249         case 1:
3250                 sector_size = ICH_FLASH_SEG_SIZE_4K;
3251                 iteration = 1;
3252                 break;
3253         case 2:
3254                 sector_size = ICH_FLASH_SEG_SIZE_8K;
3255                 iteration = 1;
3256                 break;
3257         case 3:
3258                 sector_size = ICH_FLASH_SEG_SIZE_64K;
3259                 iteration = 1;
3260                 break;
3261         default:
3262                 return -E1000_ERR_NVM;
3263         }
3264
3265         /* Start with the base address, then add the sector offset. */
3266         flash_linear_addr = hw->nvm.flash_base_addr;
3267         flash_linear_addr += (bank) ? flash_bank_size : 0;
3268
3269         for (j = 0; j < iteration ; j++) {
3270                 do {
3271                         /* Steps */
3272                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
3273                         if (ret_val)
3274                                 return ret_val;
3275
3276                         /* Write a value 11 (block Erase) in Flash
3277                          * Cycle field in hw flash control
3278                          */
3279                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3280                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
3281                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3282
3283                         /* Write the last 24 bits of an index within the
3284                          * block into Flash Linear address field in Flash
3285                          * Address.
3286                          */
3287                         flash_linear_addr += (j * sector_size);
3288                         ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3289
3290                         ret_val = e1000_flash_cycle_ich8lan(hw,
3291                                                ICH_FLASH_ERASE_COMMAND_TIMEOUT);
3292                         if (!ret_val)
3293                                 break;
3294
3295                         /* Check if FCERR is set to 1.  If 1,
3296                          * clear it and try the whole sequence
3297                          * a few more times else Done
3298                          */
3299                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3300                         if (hsfsts.hsf_status.flcerr)
3301                                 /* repeat for some time before giving up */
3302                                 continue;
3303                         else if (!hsfsts.hsf_status.flcdone)
3304                                 return ret_val;
3305                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
3306         }
3307
3308         return 0;
3309 }
3310
3311 /**
3312  *  e1000_valid_led_default_ich8lan - Set the default LED settings
3313  *  @hw: pointer to the HW structure
3314  *  @data: Pointer to the LED settings
3315  *
3316  *  Reads the LED default settings from the NVM to data.  If the NVM LED
3317  *  settings is all 0's or F's, set the LED default to a valid LED default
3318  *  setting.
3319  **/
3320 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
3321 {
3322         s32 ret_val;
3323
3324         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
3325         if (ret_val) {
3326                 e_dbg("NVM Read Error\n");
3327                 return ret_val;
3328         }
3329
3330         if (*data == ID_LED_RESERVED_0000 ||
3331             *data == ID_LED_RESERVED_FFFF)
3332                 *data = ID_LED_DEFAULT_ICH8LAN;
3333
3334         return 0;
3335 }
3336
3337 /**
3338  *  e1000_id_led_init_pchlan - store LED configurations
3339  *  @hw: pointer to the HW structure
3340  *
3341  *  PCH does not control LEDs via the LEDCTL register, rather it uses
3342  *  the PHY LED configuration register.
3343  *
3344  *  PCH also does not have an "always on" or "always off" mode which
3345  *  complicates the ID feature.  Instead of using the "on" mode to indicate
3346  *  in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()),
3347  *  use "link_up" mode.  The LEDs will still ID on request if there is no
3348  *  link based on logic in e1000_led_[on|off]_pchlan().
3349  **/
3350 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
3351 {
3352         struct e1000_mac_info *mac = &hw->mac;
3353         s32 ret_val;
3354         const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
3355         const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
3356         u16 data, i, temp, shift;
3357
3358         /* Get default ID LED modes */
3359         ret_val = hw->nvm.ops.valid_led_default(hw, &data);
3360         if (ret_val)
3361                 return ret_val;
3362
3363         mac->ledctl_default = er32(LEDCTL);
3364         mac->ledctl_mode1 = mac->ledctl_default;
3365         mac->ledctl_mode2 = mac->ledctl_default;
3366
3367         for (i = 0; i < 4; i++) {
3368                 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
3369                 shift = (i * 5);
3370                 switch (temp) {
3371                 case ID_LED_ON1_DEF2:
3372                 case ID_LED_ON1_ON2:
3373                 case ID_LED_ON1_OFF2:
3374                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
3375                         mac->ledctl_mode1 |= (ledctl_on << shift);
3376                         break;
3377                 case ID_LED_OFF1_DEF2:
3378                 case ID_LED_OFF1_ON2:
3379                 case ID_LED_OFF1_OFF2:
3380                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
3381                         mac->ledctl_mode1 |= (ledctl_off << shift);
3382                         break;
3383                 default:
3384                         /* Do nothing */
3385                         break;
3386                 }
3387                 switch (temp) {
3388                 case ID_LED_DEF1_ON2:
3389                 case ID_LED_ON1_ON2:
3390                 case ID_LED_OFF1_ON2:
3391                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
3392                         mac->ledctl_mode2 |= (ledctl_on << shift);
3393                         break;
3394                 case ID_LED_DEF1_OFF2:
3395                 case ID_LED_ON1_OFF2:
3396                 case ID_LED_OFF1_OFF2:
3397                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
3398                         mac->ledctl_mode2 |= (ledctl_off << shift);
3399                         break;
3400                 default:
3401                         /* Do nothing */
3402                         break;
3403                 }
3404         }
3405
3406         return 0;
3407 }
3408
3409 /**
3410  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
3411  *  @hw: pointer to the HW structure
3412  *
3413  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
3414  *  register, so the the bus width is hard coded.
3415  **/
3416 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
3417 {
3418         struct e1000_bus_info *bus = &hw->bus;
3419         s32 ret_val;
3420
3421         ret_val = e1000e_get_bus_info_pcie(hw);
3422
3423         /* ICH devices are "PCI Express"-ish.  They have
3424          * a configuration space, but do not contain
3425          * PCI Express Capability registers, so bus width
3426          * must be hardcoded.
3427          */
3428         if (bus->width == e1000_bus_width_unknown)
3429                 bus->width = e1000_bus_width_pcie_x1;
3430
3431         return ret_val;
3432 }
3433
3434 /**
3435  *  e1000_reset_hw_ich8lan - Reset the hardware
3436  *  @hw: pointer to the HW structure
3437  *
3438  *  Does a full reset of the hardware which includes a reset of the PHY and
3439  *  MAC.
3440  **/
3441 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
3442 {
3443         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3444         u16 kum_cfg;
3445         u32 ctrl, reg;
3446         s32 ret_val;
3447
3448         /* Prevent the PCI-E bus from sticking if there is no TLP connection
3449          * on the last TLP read/write transaction when MAC is reset.
3450          */
3451         ret_val = e1000e_disable_pcie_master(hw);
3452         if (ret_val)
3453                 e_dbg("PCI-E Master disable polling has failed.\n");
3454
3455         e_dbg("Masking off all interrupts\n");
3456         ew32(IMC, 0xffffffff);
3457
3458         /* Disable the Transmit and Receive units.  Then delay to allow
3459          * any pending transactions to complete before we hit the MAC
3460          * with the global reset.
3461          */
3462         ew32(RCTL, 0);
3463         ew32(TCTL, E1000_TCTL_PSP);
3464         e1e_flush();
3465
3466         usleep_range(10000, 20000);
3467
3468         /* Workaround for ICH8 bit corruption issue in FIFO memory */
3469         if (hw->mac.type == e1000_ich8lan) {
3470                 /* Set Tx and Rx buffer allocation to 8k apiece. */
3471                 ew32(PBA, E1000_PBA_8K);
3472                 /* Set Packet Buffer Size to 16k. */
3473                 ew32(PBS, E1000_PBS_16K);
3474         }
3475
3476         if (hw->mac.type == e1000_pchlan) {
3477                 /* Save the NVM K1 bit setting */
3478                 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
3479                 if (ret_val)
3480                         return ret_val;
3481
3482                 if (kum_cfg & E1000_NVM_K1_ENABLE)
3483                         dev_spec->nvm_k1_enabled = true;
3484                 else
3485                         dev_spec->nvm_k1_enabled = false;
3486         }
3487
3488         ctrl = er32(CTRL);
3489
3490         if (!hw->phy.ops.check_reset_block(hw)) {
3491                 /* Full-chip reset requires MAC and PHY reset at the same
3492                  * time to make sure the interface between MAC and the
3493                  * external PHY is reset.
3494                  */
3495                 ctrl |= E1000_CTRL_PHY_RST;
3496
3497                 /* Gate automatic PHY configuration by hardware on
3498                  * non-managed 82579
3499                  */
3500                 if ((hw->mac.type == e1000_pch2lan) &&
3501                     !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
3502                         e1000_gate_hw_phy_config_ich8lan(hw, true);
3503         }
3504         ret_val = e1000_acquire_swflag_ich8lan(hw);
3505         e_dbg("Issuing a global reset to ich8lan\n");
3506         ew32(CTRL, (ctrl | E1000_CTRL_RST));
3507         /* cannot issue a flush here because it hangs the hardware */
3508         msleep(20);
3509
3510         /* Set Phy Config Counter to 50msec */
3511         if (hw->mac.type == e1000_pch2lan) {
3512                 reg = er32(FEXTNVM3);
3513                 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
3514                 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
3515                 ew32(FEXTNVM3, reg);
3516         }
3517
3518         if (!ret_val)
3519                 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
3520
3521         if (ctrl & E1000_CTRL_PHY_RST) {
3522                 ret_val = hw->phy.ops.get_cfg_done(hw);
3523                 if (ret_val)
3524                         return ret_val;
3525
3526                 ret_val = e1000_post_phy_reset_ich8lan(hw);
3527                 if (ret_val)
3528                         return ret_val;
3529         }
3530
3531         /* For PCH, this write will make sure that any noise
3532          * will be detected as a CRC error and be dropped rather than show up
3533          * as a bad packet to the DMA engine.
3534          */
3535         if (hw->mac.type == e1000_pchlan)
3536                 ew32(CRC_OFFSET, 0x65656565);
3537
3538         ew32(IMC, 0xffffffff);
3539         er32(ICR);
3540
3541         reg = er32(KABGTXD);
3542         reg |= E1000_KABGTXD_BGSQLBIAS;
3543         ew32(KABGTXD, reg);
3544
3545         return 0;
3546 }
3547
3548 /**
3549  *  e1000_init_hw_ich8lan - Initialize the hardware
3550  *  @hw: pointer to the HW structure
3551  *
3552  *  Prepares the hardware for transmit and receive by doing the following:
3553  *   - initialize hardware bits
3554  *   - initialize LED identification
3555  *   - setup receive address registers
3556  *   - setup flow control
3557  *   - setup transmit descriptors
3558  *   - clear statistics
3559  **/
3560 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
3561 {
3562         struct e1000_mac_info *mac = &hw->mac;
3563         u32 ctrl_ext, txdctl, snoop;
3564         s32 ret_val;
3565         u16 i;
3566
3567         e1000_initialize_hw_bits_ich8lan(hw);
3568
3569         /* Initialize identification LED */
3570         ret_val = mac->ops.id_led_init(hw);
3571         if (ret_val)
3572                 e_dbg("Error initializing identification LED\n");
3573                 /* This is not fatal and we should not stop init due to this */
3574
3575         /* Setup the receive address. */
3576         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
3577
3578         /* Zero out the Multicast HASH table */
3579         e_dbg("Zeroing the MTA\n");
3580         for (i = 0; i < mac->mta_reg_count; i++)
3581                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
3582
3583         /* The 82578 Rx buffer will stall if wakeup is enabled in host and
3584          * the ME.  Disable wakeup by clearing the host wakeup bit.
3585          * Reset the phy after disabling host wakeup to reset the Rx buffer.
3586          */
3587         if (hw->phy.type == e1000_phy_82578) {
3588                 e1e_rphy(hw, BM_PORT_GEN_CFG, &i);
3589                 i &= ~BM_WUC_HOST_WU_BIT;
3590                 e1e_wphy(hw, BM_PORT_GEN_CFG, i);
3591                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
3592                 if (ret_val)
3593                         return ret_val;
3594         }
3595
3596         /* Setup link and flow control */
3597         ret_val = mac->ops.setup_link(hw);
3598
3599         /* Set the transmit descriptor write-back policy for both queues */
3600         txdctl = er32(TXDCTL(0));
3601         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3602                  E1000_TXDCTL_FULL_TX_DESC_WB;
3603         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3604                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
3605         ew32(TXDCTL(0), txdctl);
3606         txdctl = er32(TXDCTL(1));
3607         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3608                  E1000_TXDCTL_FULL_TX_DESC_WB;
3609         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3610                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
3611         ew32(TXDCTL(1), txdctl);
3612
3613         /* ICH8 has opposite polarity of no_snoop bits.
3614          * By default, we should use snoop behavior.
3615          */
3616         if (mac->type == e1000_ich8lan)
3617                 snoop = PCIE_ICH8_SNOOP_ALL;
3618         else
3619                 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
3620         e1000e_set_pcie_no_snoop(hw, snoop);
3621
3622         ctrl_ext = er32(CTRL_EXT);
3623         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
3624         ew32(CTRL_EXT, ctrl_ext);
3625
3626         /* Clear all of the statistics registers (clear on read).  It is
3627          * important that we do this after we have tried to establish link
3628          * because the symbol error count will increment wildly if there
3629          * is no link.
3630          */
3631         e1000_clear_hw_cntrs_ich8lan(hw);
3632
3633         return ret_val;
3634 }
3635 /**
3636  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
3637  *  @hw: pointer to the HW structure
3638  *
3639  *  Sets/Clears required hardware bits necessary for correctly setting up the
3640  *  hardware for transmit and receive.
3641  **/
3642 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
3643 {
3644         u32 reg;
3645
3646         /* Extended Device Control */
3647         reg = er32(CTRL_EXT);
3648         reg |= (1 << 22);
3649         /* Enable PHY low-power state when MAC is at D3 w/o WoL */
3650         if (hw->mac.type >= e1000_pchlan)
3651                 reg |= E1000_CTRL_EXT_PHYPDEN;
3652         ew32(CTRL_EXT, reg);
3653
3654         /* Transmit Descriptor Control 0 */
3655         reg = er32(TXDCTL(0));
3656         reg |= (1 << 22);
3657         ew32(TXDCTL(0), reg);
3658
3659         /* Transmit Descriptor Control 1 */
3660         reg = er32(TXDCTL(1));
3661         reg |= (1 << 22);
3662         ew32(TXDCTL(1), reg);
3663
3664         /* Transmit Arbitration Control 0 */
3665         reg = er32(TARC(0));
3666         if (hw->mac.type == e1000_ich8lan)
3667                 reg |= (1 << 28) | (1 << 29);
3668         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
3669         ew32(TARC(0), reg);
3670
3671         /* Transmit Arbitration Control 1 */
3672         reg = er32(TARC(1));
3673         if (er32(TCTL) & E1000_TCTL_MULR)
3674                 reg &= ~(1 << 28);
3675         else
3676                 reg |= (1 << 28);
3677         reg |= (1 << 24) | (1 << 26) | (1 << 30);
3678         ew32(TARC(1), reg);
3679
3680         /* Device Status */
3681         if (hw->mac.type == e1000_ich8lan) {
3682                 reg = er32(STATUS);
3683                 reg &= ~(1 << 31);
3684                 ew32(STATUS, reg);
3685         }
3686
3687         /* work-around descriptor data corruption issue during nfs v2 udp
3688          * traffic, just disable the nfs filtering capability
3689          */
3690         reg = er32(RFCTL);
3691         reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
3692
3693         /* Disable IPv6 extension header parsing because some malformed
3694          * IPv6 headers can hang the Rx.
3695          */
3696         if (hw->mac.type == e1000_ich8lan)
3697                 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
3698         ew32(RFCTL, reg);
3699
3700         /* Enable ECC on Lynxpoint */
3701         if (hw->mac.type == e1000_pch_lpt) {
3702                 reg = er32(PBECCSTS);
3703                 reg |= E1000_PBECCSTS_ECC_ENABLE;
3704                 ew32(PBECCSTS, reg);
3705
3706                 reg = er32(CTRL);
3707                 reg |= E1000_CTRL_MEHE;
3708                 ew32(CTRL, reg);
3709         }
3710 }
3711
3712 /**
3713  *  e1000_setup_link_ich8lan - Setup flow control and link settings
3714  *  @hw: pointer to the HW structure
3715  *
3716  *  Determines which flow control settings to use, then configures flow
3717  *  control.  Calls the appropriate media-specific link configuration
3718  *  function.  Assuming the adapter has a valid link partner, a valid link
3719  *  should be established.  Assumes the hardware has previously been reset
3720  *  and the transmitter and receiver are not enabled.
3721  **/
3722 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
3723 {
3724         s32 ret_val;
3725
3726         if (hw->phy.ops.check_reset_block(hw))
3727                 return 0;
3728
3729         /* ICH parts do not have a word in the NVM to determine
3730          * the default flow control setting, so we explicitly
3731          * set it to full.
3732          */
3733         if (hw->fc.requested_mode == e1000_fc_default) {
3734                 /* Workaround h/w hang when Tx flow control enabled */
3735                 if (hw->mac.type == e1000_pchlan)
3736                         hw->fc.requested_mode = e1000_fc_rx_pause;
3737                 else
3738                         hw->fc.requested_mode = e1000_fc_full;
3739         }
3740
3741         /* Save off the requested flow control mode for use later.  Depending
3742          * on the link partner's capabilities, we may or may not use this mode.
3743          */
3744         hw->fc.current_mode = hw->fc.requested_mode;
3745
3746         e_dbg("After fix-ups FlowControl is now = %x\n",
3747                 hw->fc.current_mode);
3748
3749         /* Continue to configure the copper link. */
3750         ret_val = hw->mac.ops.setup_physical_interface(hw);
3751         if (ret_val)
3752                 return ret_val;
3753
3754         ew32(FCTTV, hw->fc.pause_time);
3755         if ((hw->phy.type == e1000_phy_82578) ||
3756             (hw->phy.type == e1000_phy_82579) ||
3757             (hw->phy.type == e1000_phy_i217) ||
3758             (hw->phy.type == e1000_phy_82577)) {
3759                 ew32(FCRTV_PCH, hw->fc.refresh_time);
3760
3761                 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
3762                                    hw->fc.pause_time);
3763                 if (ret_val)
3764                         return ret_val;
3765         }
3766
3767         return e1000e_set_fc_watermarks(hw);
3768 }
3769
3770 /**
3771  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
3772  *  @hw: pointer to the HW structure
3773  *
3774  *  Configures the kumeran interface to the PHY to wait the appropriate time
3775  *  when polling the PHY, then call the generic setup_copper_link to finish
3776  *  configuring the copper link.
3777  **/
3778 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
3779 {
3780         u32 ctrl;
3781         s32 ret_val;
3782         u16 reg_data;
3783
3784         ctrl = er32(CTRL);
3785         ctrl |= E1000_CTRL_SLU;
3786         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3787         ew32(CTRL, ctrl);
3788
3789         /* Set the mac to wait the maximum time between each iteration
3790          * and increase the max iterations when polling the phy;
3791          * this fixes erroneous timeouts at 10Mbps.
3792          */
3793         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
3794         if (ret_val)
3795                 return ret_val;
3796         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3797                                        &reg_data);
3798         if (ret_val)
3799                 return ret_val;
3800         reg_data |= 0x3F;
3801         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3802                                         reg_data);
3803         if (ret_val)
3804                 return ret_val;
3805
3806         switch (hw->phy.type) {
3807         case e1000_phy_igp_3:
3808                 ret_val = e1000e_copper_link_setup_igp(hw);
3809                 if (ret_val)
3810                         return ret_val;
3811                 break;
3812         case e1000_phy_bm:
3813         case e1000_phy_82578:
3814                 ret_val = e1000e_copper_link_setup_m88(hw);
3815                 if (ret_val)
3816                         return ret_val;
3817                 break;
3818         case e1000_phy_82577:
3819         case e1000_phy_82579:
3820         case e1000_phy_i217:
3821                 ret_val = e1000_copper_link_setup_82577(hw);
3822                 if (ret_val)
3823                         return ret_val;
3824                 break;
3825         case e1000_phy_ife:
3826                 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
3827                 if (ret_val)
3828                         return ret_val;
3829
3830                 reg_data &= ~IFE_PMC_AUTO_MDIX;
3831
3832                 switch (hw->phy.mdix) {
3833                 case 1:
3834                         reg_data &= ~IFE_PMC_FORCE_MDIX;
3835                         break;
3836                 case 2:
3837                         reg_data |= IFE_PMC_FORCE_MDIX;
3838                         break;
3839                 case 0:
3840                 default:
3841                         reg_data |= IFE_PMC_AUTO_MDIX;
3842                         break;
3843                 }
3844                 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
3845                 if (ret_val)
3846                         return ret_val;
3847                 break;
3848         default:
3849                 break;
3850         }
3851
3852         return e1000e_setup_copper_link(hw);
3853 }
3854
3855 /**
3856  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
3857  *  @hw: pointer to the HW structure
3858  *  @speed: pointer to store current link speed
3859  *  @duplex: pointer to store the current link duplex
3860  *
3861  *  Calls the generic get_speed_and_duplex to retrieve the current link
3862  *  information and then calls the Kumeran lock loss workaround for links at
3863  *  gigabit speeds.
3864  **/
3865 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
3866                                           u16 *duplex)
3867 {
3868         s32 ret_val;
3869
3870         ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
3871         if (ret_val)
3872                 return ret_val;
3873
3874         if ((hw->mac.type == e1000_ich8lan) &&
3875             (hw->phy.type == e1000_phy_igp_3) &&
3876             (*speed == SPEED_1000)) {
3877                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
3878         }
3879
3880         return ret_val;
3881 }
3882
3883 /**
3884  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
3885  *  @hw: pointer to the HW structure
3886  *
3887  *  Work-around for 82566 Kumeran PCS lock loss:
3888  *  On link status change (i.e. PCI reset, speed change) and link is up and
3889  *  speed is gigabit-
3890  *    0) if workaround is optionally disabled do nothing
3891  *    1) wait 1ms for Kumeran link to come up
3892  *    2) check Kumeran Diagnostic register PCS lock loss bit
3893  *    3) if not set the link is locked (all is good), otherwise...
3894  *    4) reset the PHY
3895  *    5) repeat up to 10 times
3896  *  Note: this is only called for IGP3 copper when speed is 1gb.
3897  **/
3898 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
3899 {
3900         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3901         u32 phy_ctrl;
3902         s32 ret_val;
3903         u16 i, data;
3904         bool link;
3905
3906         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
3907                 return 0;
3908
3909         /* Make sure link is up before proceeding.  If not just return.
3910          * Attempting this while link is negotiating fouled up link
3911          * stability
3912          */
3913         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3914         if (!link)
3915                 return 0;
3916
3917         for (i = 0; i < 10; i++) {
3918                 /* read once to clear */
3919                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3920                 if (ret_val)
3921                         return ret_val;
3922                 /* and again to get new status */
3923                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3924                 if (ret_val)
3925                         return ret_val;
3926
3927                 /* check for PCS lock */
3928                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
3929                         return 0;
3930
3931                 /* Issue PHY reset */
3932                 e1000_phy_hw_reset(hw);
3933                 mdelay(5);
3934         }
3935         /* Disable GigE link negotiation */
3936         phy_ctrl = er32(PHY_CTRL);
3937         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
3938                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3939         ew32(PHY_CTRL, phy_ctrl);
3940
3941         /* Call gig speed drop workaround on Gig disable before accessing
3942          * any PHY registers
3943          */
3944         e1000e_gig_downshift_workaround_ich8lan(hw);
3945
3946         /* unable to acquire PCS lock */
3947         return -E1000_ERR_PHY;
3948 }
3949
3950 /**
3951  *  e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
3952  *  @hw: pointer to the HW structure
3953  *  @state: boolean value used to set the current Kumeran workaround state
3954  *
3955  *  If ICH8, set the current Kumeran workaround state (enabled - true
3956  *  /disabled - false).
3957  **/
3958 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
3959                                                  bool state)
3960 {
3961         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3962
3963         if (hw->mac.type != e1000_ich8lan) {
3964                 e_dbg("Workaround applies to ICH8 only.\n");
3965                 return;
3966         }
3967
3968         dev_spec->kmrn_lock_loss_workaround_enabled = state;
3969 }
3970
3971 /**
3972  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
3973  *  @hw: pointer to the HW structure
3974  *
3975  *  Workaround for 82566 power-down on D3 entry:
3976  *    1) disable gigabit link
3977  *    2) write VR power-down enable
3978  *    3) read it back
3979  *  Continue if successful, else issue LCD reset and repeat
3980  **/
3981 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
3982 {
3983         u32 reg;
3984         u16 data;
3985         u8  retry = 0;
3986
3987         if (hw->phy.type != e1000_phy_igp_3)
3988                 return;
3989
3990         /* Try the workaround twice (if needed) */
3991         do {
3992                 /* Disable link */
3993                 reg = er32(PHY_CTRL);
3994                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
3995                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3996                 ew32(PHY_CTRL, reg);
3997
3998                 /* Call gig speed drop workaround on Gig disable before
3999                  * accessing any PHY registers
4000                  */
4001                 if (hw->mac.type == e1000_ich8lan)
4002                         e1000e_gig_downshift_workaround_ich8lan(hw);
4003
4004                 /* Write VR power-down enable */
4005                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
4006                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
4007                 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
4008
4009                 /* Read it back and test */
4010                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
4011                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
4012                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
4013                         break;
4014
4015                 /* Issue PHY reset and repeat at most one more time */
4016                 reg = er32(CTRL);
4017                 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
4018                 retry++;
4019         } while (retry);
4020 }
4021
4022 /**
4023  *  e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
4024  *  @hw: pointer to the HW structure
4025  *
4026  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
4027  *  LPLU, Gig disable, MDIC PHY reset):
4028  *    1) Set Kumeran Near-end loopback
4029  *    2) Clear Kumeran Near-end loopback
4030  *  Should only be called for ICH8[m] devices with any 1G Phy.
4031  **/
4032 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
4033 {
4034         s32 ret_val;
4035         u16 reg_data;
4036
4037         if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife))
4038                 return;
4039
4040         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
4041                                       &reg_data);
4042         if (ret_val)
4043                 return;
4044         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
4045         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
4046                                        reg_data);
4047         if (ret_val)
4048                 return;
4049         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
4050         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
4051                                        reg_data);
4052 }
4053
4054 /**
4055  *  e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
4056  *  @hw: pointer to the HW structure
4057  *
4058  *  During S0 to Sx transition, it is possible the link remains at gig
4059  *  instead of negotiating to a lower speed.  Before going to Sx, set
4060  *  'Gig Disable' to force link speed negotiation to a lower speed based on
4061  *  the LPLU setting in the NVM or custom setting.  For PCH and newer parts,
4062  *  the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
4063  *  needs to be written.
4064  *  Parts that support (and are linked to a partner which support) EEE in
4065  *  100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
4066  *  than 10Mbps w/o EEE.
4067  **/
4068 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
4069 {
4070         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4071         u32 phy_ctrl;
4072         s32 ret_val;
4073
4074         phy_ctrl = er32(PHY_CTRL);
4075         phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
4076         if (hw->phy.type == e1000_phy_i217) {
4077                 u16 phy_reg;
4078
4079                 ret_val = hw->phy.ops.acquire(hw);
4080                 if (ret_val)
4081                         goto out;
4082
4083                 if (!dev_spec->eee_disable) {
4084                         u16 eee_advert;
4085
4086                         ret_val =
4087                             e1000_read_emi_reg_locked(hw,
4088                                                       I217_EEE_ADVERTISEMENT,
4089                                                       &eee_advert);
4090                         if (ret_val)
4091                                 goto release;
4092
4093                         /* Disable LPLU if both link partners support 100BaseT
4094                          * EEE and 100Full is advertised on both ends of the
4095                          * link.
4096                          */
4097                         if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
4098                             (dev_spec->eee_lp_ability &
4099                              I82579_EEE_100_SUPPORTED) &&
4100                             (hw->phy.autoneg_advertised & ADVERTISE_100_FULL))
4101                                 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
4102                                               E1000_PHY_CTRL_NOND0A_LPLU);
4103                 }
4104
4105                 /* For i217 Intel Rapid Start Technology support,
4106                  * when the system is going into Sx and no manageability engine
4107                  * is present, the driver must configure proxy to reset only on
4108                  * power good.  LPI (Low Power Idle) state must also reset only
4109                  * on power good, as well as the MTA (Multicast table array).
4110                  * The SMBus release must also be disabled on LCD reset.
4111                  */
4112                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
4113
4114                         /* Enable proxy to reset only on power good. */
4115                         e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg);
4116                         phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
4117                         e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg);
4118
4119                         /* Set bit enable LPI (EEE) to reset only on
4120                          * power good.
4121                          */
4122                         e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg);
4123                         phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
4124                         e1e_wphy_locked(hw, I217_SxCTRL, phy_reg);
4125
4126                         /* Disable the SMB release on LCD reset. */
4127                         e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
4128                         phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
4129                         e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
4130                 }
4131
4132                 /* Enable MTA to reset for Intel Rapid Start Technology
4133                  * Support
4134                  */
4135                 e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
4136                 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
4137                 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
4138
4139 release:
4140                 hw->phy.ops.release(hw);
4141         }
4142 out:
4143         ew32(PHY_CTRL, phy_ctrl);
4144
4145         if (hw->mac.type == e1000_ich8lan)
4146                 e1000e_gig_downshift_workaround_ich8lan(hw);
4147
4148         if (hw->mac.type >= e1000_pchlan) {
4149                 e1000_oem_bits_config_ich8lan(hw, false);
4150
4151                 /* Reset PHY to activate OEM bits on 82577/8 */
4152                 if (hw->mac.type == e1000_pchlan)
4153                         e1000e_phy_hw_reset_generic(hw);
4154
4155                 ret_val = hw->phy.ops.acquire(hw);
4156                 if (ret_val)
4157                         return;
4158                 e1000_write_smbus_addr(hw);
4159                 hw->phy.ops.release(hw);
4160         }
4161 }
4162
4163 /**
4164  *  e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
4165  *  @hw: pointer to the HW structure
4166  *
4167  *  During Sx to S0 transitions on non-managed devices or managed devices
4168  *  on which PHY resets are not blocked, if the PHY registers cannot be
4169  *  accessed properly by the s/w toggle the LANPHYPC value to power cycle
4170  *  the PHY.
4171  *  On i217, setup Intel Rapid Start Technology.
4172  **/
4173 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
4174 {
4175         s32 ret_val;
4176
4177         if (hw->mac.type < e1000_pch2lan)
4178                 return;
4179
4180         ret_val = e1000_init_phy_workarounds_pchlan(hw);
4181         if (ret_val) {
4182                 e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val);
4183                 return;
4184         }
4185
4186         /* For i217 Intel Rapid Start Technology support when the system
4187          * is transitioning from Sx and no manageability engine is present
4188          * configure SMBus to restore on reset, disable proxy, and enable
4189          * the reset on MTA (Multicast table array).
4190          */
4191         if (hw->phy.type == e1000_phy_i217) {
4192                 u16 phy_reg;
4193
4194                 ret_val = hw->phy.ops.acquire(hw);
4195                 if (ret_val) {
4196                         e_dbg("Failed to setup iRST\n");
4197                         return;
4198                 }
4199
4200                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
4201                         /* Restore clear on SMB if no manageability engine
4202                          * is present
4203                          */
4204                         ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
4205                         if (ret_val)
4206                                 goto release;
4207                         phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
4208                         e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
4209
4210                         /* Disable Proxy */
4211                         e1e_wphy_locked(hw, I217_PROXY_CTRL, 0);
4212                 }
4213                 /* Enable reset on MTA */
4214                 ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
4215                 if (ret_val)
4216                         goto release;
4217                 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
4218                 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
4219 release:
4220                 if (ret_val)
4221                         e_dbg("Error %d in resume workarounds\n", ret_val);
4222                 hw->phy.ops.release(hw);
4223         }
4224 }
4225
4226 /**
4227  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
4228  *  @hw: pointer to the HW structure
4229  *
4230  *  Return the LED back to the default configuration.
4231  **/
4232 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
4233 {
4234         if (hw->phy.type == e1000_phy_ife)
4235                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
4236
4237         ew32(LEDCTL, hw->mac.ledctl_default);
4238         return 0;
4239 }
4240
4241 /**
4242  *  e1000_led_on_ich8lan - Turn LEDs on
4243  *  @hw: pointer to the HW structure
4244  *
4245  *  Turn on the LEDs.
4246  **/
4247 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
4248 {
4249         if (hw->phy.type == e1000_phy_ife)
4250                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
4251                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
4252
4253         ew32(LEDCTL, hw->mac.ledctl_mode2);
4254         return 0;
4255 }
4256
4257 /**
4258  *  e1000_led_off_ich8lan - Turn LEDs off
4259  *  @hw: pointer to the HW structure
4260  *
4261  *  Turn off the LEDs.
4262  **/
4263 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
4264 {
4265         if (hw->phy.type == e1000_phy_ife)
4266                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
4267                                 (IFE_PSCL_PROBE_MODE |
4268                                  IFE_PSCL_PROBE_LEDS_OFF));
4269
4270         ew32(LEDCTL, hw->mac.ledctl_mode1);
4271         return 0;
4272 }
4273
4274 /**
4275  *  e1000_setup_led_pchlan - Configures SW controllable LED
4276  *  @hw: pointer to the HW structure
4277  *
4278  *  This prepares the SW controllable LED for use.
4279  **/
4280 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
4281 {
4282         return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);
4283 }
4284
4285 /**
4286  *  e1000_cleanup_led_pchlan - Restore the default LED operation
4287  *  @hw: pointer to the HW structure
4288  *
4289  *  Return the LED back to the default configuration.
4290  **/
4291 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
4292 {
4293         return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);
4294 }
4295
4296 /**
4297  *  e1000_led_on_pchlan - Turn LEDs on
4298  *  @hw: pointer to the HW structure
4299  *
4300  *  Turn on the LEDs.
4301  **/
4302 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
4303 {
4304         u16 data = (u16)hw->mac.ledctl_mode2;
4305         u32 i, led;
4306
4307         /* If no link, then turn LED on by setting the invert bit
4308          * for each LED that's mode is "link_up" in ledctl_mode2.
4309          */
4310         if (!(er32(STATUS) & E1000_STATUS_LU)) {
4311                 for (i = 0; i < 3; i++) {
4312                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
4313                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
4314                             E1000_LEDCTL_MODE_LINK_UP)
4315                                 continue;
4316                         if (led & E1000_PHY_LED0_IVRT)
4317                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
4318                         else
4319                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
4320                 }
4321         }
4322
4323         return e1e_wphy(hw, HV_LED_CONFIG, data);
4324 }
4325
4326 /**
4327  *  e1000_led_off_pchlan - Turn LEDs off
4328  *  @hw: pointer to the HW structure
4329  *
4330  *  Turn off the LEDs.
4331  **/
4332 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
4333 {
4334         u16 data = (u16)hw->mac.ledctl_mode1;
4335         u32 i, led;
4336
4337         /* If no link, then turn LED off by clearing the invert bit
4338          * for each LED that's mode is "link_up" in ledctl_mode1.
4339          */
4340         if (!(er32(STATUS) & E1000_STATUS_LU)) {
4341                 for (i = 0; i < 3; i++) {
4342                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
4343                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
4344                             E1000_LEDCTL_MODE_LINK_UP)
4345                                 continue;
4346                         if (led & E1000_PHY_LED0_IVRT)
4347                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
4348                         else
4349                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
4350                 }
4351         }
4352
4353         return e1e_wphy(hw, HV_LED_CONFIG, data);
4354 }
4355
4356 /**
4357  *  e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
4358  *  @hw: pointer to the HW structure
4359  *
4360  *  Read appropriate register for the config done bit for completion status
4361  *  and configure the PHY through s/w for EEPROM-less parts.
4362  *
4363  *  NOTE: some silicon which is EEPROM-less will fail trying to read the
4364  *  config done bit, so only an error is logged and continues.  If we were
4365  *  to return with error, EEPROM-less silicon would not be able to be reset
4366  *  or change link.
4367  **/
4368 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
4369 {
4370         s32 ret_val = 0;
4371         u32 bank = 0;
4372         u32 status;
4373
4374         e1000e_get_cfg_done(hw);
4375
4376         /* Wait for indication from h/w that it has completed basic config */
4377         if (hw->mac.type >= e1000_ich10lan) {
4378                 e1000_lan_init_done_ich8lan(hw);
4379         } else {
4380                 ret_val = e1000e_get_auto_rd_done(hw);
4381                 if (ret_val) {
4382                         /* When auto config read does not complete, do not
4383                          * return with an error. This can happen in situations
4384                          * where there is no eeprom and prevents getting link.
4385                          */
4386                         e_dbg("Auto Read Done did not complete\n");
4387                         ret_val = 0;
4388                 }
4389         }
4390
4391         /* Clear PHY Reset Asserted bit */
4392         status = er32(STATUS);
4393         if (status & E1000_STATUS_PHYRA)
4394                 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
4395         else
4396                 e_dbg("PHY Reset Asserted not set - needs delay\n");
4397
4398         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
4399         if (hw->mac.type <= e1000_ich9lan) {
4400                 if (!(er32(EECD) & E1000_EECD_PRES) &&
4401                     (hw->phy.type == e1000_phy_igp_3)) {
4402                         e1000e_phy_init_script_igp3(hw);
4403                 }
4404         } else {
4405                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
4406                         /* Maybe we should do a basic PHY config */
4407                         e_dbg("EEPROM not present\n");
4408                         ret_val = -E1000_ERR_CONFIG;
4409                 }
4410         }
4411
4412         return ret_val;
4413 }
4414
4415 /**
4416  * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
4417  * @hw: pointer to the HW structure
4418  *
4419  * In the case of a PHY power down to save power, or to turn off link during a
4420  * driver unload, or wake on lan is not enabled, remove the link.
4421  **/
4422 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
4423 {
4424         /* If the management interface is not enabled, then power down */
4425         if (!(hw->mac.ops.check_mng_mode(hw) ||
4426               hw->phy.ops.check_reset_block(hw)))
4427                 e1000_power_down_phy_copper(hw);
4428 }
4429
4430 /**
4431  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
4432  *  @hw: pointer to the HW structure
4433  *
4434  *  Clears hardware counters specific to the silicon family and calls
4435  *  clear_hw_cntrs_generic to clear all general purpose counters.
4436  **/
4437 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
4438 {
4439         u16 phy_data;
4440         s32 ret_val;
4441
4442         e1000e_clear_hw_cntrs_base(hw);
4443
4444         er32(ALGNERRC);
4445         er32(RXERRC);
4446         er32(TNCRS);
4447         er32(CEXTERR);
4448         er32(TSCTC);
4449         er32(TSCTFC);
4450
4451         er32(MGTPRC);
4452         er32(MGTPDC);
4453         er32(MGTPTC);
4454
4455         er32(IAC);
4456         er32(ICRXOC);
4457
4458         /* Clear PHY statistics registers */
4459         if ((hw->phy.type == e1000_phy_82578) ||
4460             (hw->phy.type == e1000_phy_82579) ||
4461             (hw->phy.type == e1000_phy_i217) ||
4462             (hw->phy.type == e1000_phy_82577)) {
4463                 ret_val = hw->phy.ops.acquire(hw);
4464                 if (ret_val)
4465                         return;
4466                 ret_val = hw->phy.ops.set_page(hw,
4467                                                HV_STATS_PAGE << IGP_PAGE_SHIFT);
4468                 if (ret_val)
4469                         goto release;
4470                 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4471                 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
4472                 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4473                 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
4474                 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4475                 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
4476                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4477                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
4478                 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4479                 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
4480                 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4481                 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
4482                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4483                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
4484 release:
4485                 hw->phy.ops.release(hw);
4486         }
4487 }
4488
4489 static const struct e1000_mac_operations ich8_mac_ops = {
4490         /* check_mng_mode dependent on mac type */
4491         .check_for_link         = e1000_check_for_copper_link_ich8lan,
4492         /* cleanup_led dependent on mac type */
4493         .clear_hw_cntrs         = e1000_clear_hw_cntrs_ich8lan,
4494         .get_bus_info           = e1000_get_bus_info_ich8lan,
4495         .set_lan_id             = e1000_set_lan_id_single_port,
4496         .get_link_up_info       = e1000_get_link_up_info_ich8lan,
4497         /* led_on dependent on mac type */
4498         /* led_off dependent on mac type */
4499         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
4500         .reset_hw               = e1000_reset_hw_ich8lan,
4501         .init_hw                = e1000_init_hw_ich8lan,
4502         .setup_link             = e1000_setup_link_ich8lan,
4503         .setup_physical_interface= e1000_setup_copper_link_ich8lan,
4504         /* id_led_init dependent on mac type */
4505         .config_collision_dist  = e1000e_config_collision_dist_generic,
4506         .rar_set                = e1000e_rar_set_generic,
4507 };
4508
4509 static const struct e1000_phy_operations ich8_phy_ops = {
4510         .acquire                = e1000_acquire_swflag_ich8lan,
4511         .check_reset_block      = e1000_check_reset_block_ich8lan,
4512         .commit                 = NULL,
4513         .get_cfg_done           = e1000_get_cfg_done_ich8lan,
4514         .get_cable_length       = e1000e_get_cable_length_igp_2,
4515         .read_reg               = e1000e_read_phy_reg_igp,
4516         .release                = e1000_release_swflag_ich8lan,
4517         .reset                  = e1000_phy_hw_reset_ich8lan,
4518         .set_d0_lplu_state      = e1000_set_d0_lplu_state_ich8lan,
4519         .set_d3_lplu_state      = e1000_set_d3_lplu_state_ich8lan,
4520         .write_reg              = e1000e_write_phy_reg_igp,
4521 };
4522
4523 static const struct e1000_nvm_operations ich8_nvm_ops = {
4524         .acquire                = e1000_acquire_nvm_ich8lan,
4525         .read                   = e1000_read_nvm_ich8lan,
4526         .release                = e1000_release_nvm_ich8lan,
4527         .reload                 = e1000e_reload_nvm_generic,
4528         .update                 = e1000_update_nvm_checksum_ich8lan,
4529         .valid_led_default      = e1000_valid_led_default_ich8lan,
4530         .validate               = e1000_validate_nvm_checksum_ich8lan,
4531         .write                  = e1000_write_nvm_ich8lan,
4532 };
4533
4534 const struct e1000_info e1000_ich8_info = {
4535         .mac                    = e1000_ich8lan,
4536         .flags                  = FLAG_HAS_WOL
4537                                   | FLAG_IS_ICH
4538                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4539                                   | FLAG_HAS_AMT
4540                                   | FLAG_HAS_FLASH
4541                                   | FLAG_APME_IN_WUC,
4542         .pba                    = 8,
4543         .max_hw_frame_size      = ETH_FRAME_LEN + ETH_FCS_LEN,
4544         .get_variants           = e1000_get_variants_ich8lan,
4545         .mac_ops                = &ich8_mac_ops,
4546         .phy_ops                = &ich8_phy_ops,
4547         .nvm_ops                = &ich8_nvm_ops,
4548 };
4549
4550 const struct e1000_info e1000_ich9_info = {
4551         .mac                    = e1000_ich9lan,
4552         .flags                  = FLAG_HAS_JUMBO_FRAMES
4553                                   | FLAG_IS_ICH
4554                                   | FLAG_HAS_WOL
4555                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4556                                   | FLAG_HAS_AMT
4557                                   | FLAG_HAS_FLASH
4558                                   | FLAG_APME_IN_WUC,
4559         .pba                    = 18,
4560         .max_hw_frame_size      = DEFAULT_JUMBO,
4561         .get_variants           = e1000_get_variants_ich8lan,
4562         .mac_ops                = &ich8_mac_ops,
4563         .phy_ops                = &ich8_phy_ops,
4564         .nvm_ops                = &ich8_nvm_ops,
4565 };
4566
4567 const struct e1000_info e1000_ich10_info = {
4568         .mac                    = e1000_ich10lan,
4569         .flags                  = FLAG_HAS_JUMBO_FRAMES
4570                                   | FLAG_IS_ICH
4571                                   | FLAG_HAS_WOL
4572                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4573                                   | FLAG_HAS_AMT
4574                                   | FLAG_HAS_FLASH
4575                                   | FLAG_APME_IN_WUC,
4576         .pba                    = 18,
4577         .max_hw_frame_size      = DEFAULT_JUMBO,
4578         .get_variants           = e1000_get_variants_ich8lan,
4579         .mac_ops                = &ich8_mac_ops,
4580         .phy_ops                = &ich8_phy_ops,
4581         .nvm_ops                = &ich8_nvm_ops,
4582 };
4583
4584 const struct e1000_info e1000_pch_info = {
4585         .mac                    = e1000_pchlan,
4586         .flags                  = FLAG_IS_ICH
4587                                   | FLAG_HAS_WOL
4588                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4589                                   | FLAG_HAS_AMT
4590                                   | FLAG_HAS_FLASH
4591                                   | FLAG_HAS_JUMBO_FRAMES
4592                                   | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
4593                                   | FLAG_APME_IN_WUC,
4594         .flags2                 = FLAG2_HAS_PHY_STATS,
4595         .pba                    = 26,
4596         .max_hw_frame_size      = 4096,
4597         .get_variants           = e1000_get_variants_ich8lan,
4598         .mac_ops                = &ich8_mac_ops,
4599         .phy_ops                = &ich8_phy_ops,
4600         .nvm_ops                = &ich8_nvm_ops,
4601 };
4602
4603 const struct e1000_info e1000_pch2_info = {
4604         .mac                    = e1000_pch2lan,
4605         .flags                  = FLAG_IS_ICH
4606                                   | FLAG_HAS_WOL
4607                                   | FLAG_HAS_HW_TIMESTAMP
4608                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4609                                   | FLAG_HAS_AMT
4610                                   | FLAG_HAS_FLASH
4611                                   | FLAG_HAS_JUMBO_FRAMES
4612                                   | FLAG_APME_IN_WUC,
4613         .flags2                 = FLAG2_HAS_PHY_STATS
4614                                   | FLAG2_HAS_EEE,
4615         .pba                    = 26,
4616         .max_hw_frame_size      = DEFAULT_JUMBO,
4617         .get_variants           = e1000_get_variants_ich8lan,
4618         .mac_ops                = &ich8_mac_ops,
4619         .phy_ops                = &ich8_phy_ops,
4620         .nvm_ops                = &ich8_nvm_ops,
4621 };
4622
4623 const struct e1000_info e1000_pch_lpt_info = {
4624         .mac                    = e1000_pch_lpt,
4625         .flags                  = FLAG_IS_ICH
4626                                   | FLAG_HAS_WOL
4627                                   | FLAG_HAS_HW_TIMESTAMP
4628                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4629                                   | FLAG_HAS_AMT
4630                                   | FLAG_HAS_FLASH
4631                                   | FLAG_HAS_JUMBO_FRAMES
4632                                   | FLAG_APME_IN_WUC,
4633         .flags2                 = FLAG2_HAS_PHY_STATS
4634                                   | FLAG2_HAS_EEE,
4635         .pba                    = 26,
4636         .max_hw_frame_size      = 9018,
4637         .get_variants           = e1000_get_variants_ich8lan,
4638         .mac_ops                = &ich8_mac_ops,
4639         .phy_ops                = &ich8_phy_ops,
4640         .nvm_ops                = &ich8_nvm_ops,
4641 };