drivers/net/ethernet/intel/e1000e/ich8lan.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
   3
   4 /* 82562G 10/100 Network Connection
   5  * 82562G-2 10/100 Network Connection
   6  * 82562GT 10/100 Network Connection
   7  * 82562GT-2 10/100 Network Connection
   8  * 82562V 10/100 Network Connection
   9  * 82562V-2 10/100 Network Connection
  10  * 82566DC-2 Gigabit Network Connection
  11  * 82566DC Gigabit Network Connection
  12  * 82566DM-2 Gigabit Network Connection
  13  * 82566DM Gigabit Network Connection
  14  * 82566MC Gigabit Network Connection
  15  * 82566MM Gigabit Network Connection
  16  * 82567LM Gigabit Network Connection
  17  * 82567LF Gigabit Network Connection
  18  * 82567V Gigabit Network Connection
  19  * 82567LM-2 Gigabit Network Connection
  20  * 82567LF-2 Gigabit Network Connection
  21  * 82567V-2 Gigabit Network Connection
  22  * 82567LF-3 Gigabit Network Connection
  23  * 82567LM-3 Gigabit Network Connection
  24  * 82567LM-4 Gigabit Network Connection
  25  * 82577LM Gigabit Network Connection
  26  * 82577LC Gigabit Network Connection
  27  * 82578DM Gigabit Network Connection
  28  * 82578DC Gigabit Network Connection
  29  * 82579LM Gigabit Network Connection
  30  * 82579V Gigabit Network Connection
  31  * Ethernet Connection I217-LM
  32  * Ethernet Connection I217-V
  33  * Ethernet Connection I218-V
  34  * Ethernet Connection I218-LM
  35  * Ethernet Connection (2) I218-LM
  36  * Ethernet Connection (2) I218-V
  37  * Ethernet Connection (3) I218-LM
  38  * Ethernet Connection (3) I218-V
  39  */
  40
  41 #include "e1000.h"
  42
  43 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
  44 /* Offset 04h HSFSTS */
  45 union ich8_hws_flash_status {
  46         struct ich8_hsfsts {
  47                 u16 flcdone:1;  /* bit 0 Flash Cycle Done */
  48                 u16 flcerr:1;   /* bit 1 Flash Cycle Error */
  49                 u16 dael:1;     /* bit 2 Direct Access error Log */
  50                 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
  51                 u16 flcinprog:1;        /* bit 5 flash cycle in Progress */
  52                 u16 reserved1:2;        /* bit 13:6 Reserved */
  53                 u16 reserved2:6;        /* bit 13:6 Reserved */
  54                 u16 fldesvalid:1;       /* bit 14 Flash Descriptor Valid */
  55                 u16 flockdn:1;  /* bit 15 Flash Config Lock-Down */
  56         } hsf_status;
  57         u16 regval;
  58 };
  59
  60 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
  61 /* Offset 06h FLCTL */
  62 union ich8_hws_flash_ctrl {
  63         struct ich8_hsflctl {
  64                 u16 flcgo:1;    /* 0 Flash Cycle Go */
  65                 u16 flcycle:2;  /* 2:1 Flash Cycle */
  66                 u16 reserved:5; /* 7:3 Reserved  */
  67                 u16 fldbcount:2;        /* 9:8 Flash Data Byte Count */
  68                 u16 flockdn:6;  /* 15:10 Reserved */
  69         } hsf_ctrl;
  70         u16 regval;
  71 };
  72
  73 /* ICH Flash Region Access Permissions */
  74 union ich8_hws_flash_regacc {
  75         struct ich8_flracc {
  76                 u32 grra:8;     /* 0:7 GbE region Read Access */
  77                 u32 grwa:8;     /* 8:15 GbE region Write Access */
  78                 u32 gmrag:8;    /* 23:16 GbE Master Read Access Grant */
  79                 u32 gmwag:8;    /* 31:24 GbE Master Write Access Grant */
  80         } hsf_flregacc;
  81         u16 regval;
  82 };
  83
  84 /* ICH Flash Protected Region */
  85 union ich8_flash_protected_range {
  86         struct ich8_pr {
  87                 u32 base:13;    /* 0:12 Protected Range Base */
  88                 u32 reserved1:2;        /* 13:14 Reserved */
  89                 u32 rpe:1;      /* 15 Read Protection Enable */
  90                 u32 limit:13;   /* 16:28 Protected Range Limit */
  91                 u32 reserved2:2;        /* 29:30 Reserved */
  92                 u32 wpe:1;      /* 31 Write Protection Enable */
  93         } range;
  94         u32 regval;
  95 };
  96
  97 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
  98 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
  99 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 100 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 101                                                 u32 offset, u8 byte);
 102 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
 103                                          u8 *data);
 104 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
 105                                          u16 *data);
 106 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 107                                          u8 size, u16 *data);
 108 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
 109                                            u32 *data);
 110 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw,
 111                                           u32 offset, u32 *data);
 112 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw,
 113                                             u32 offset, u32 data);
 114 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
 115                                                  u32 offset, u32 dword);
 116 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 117 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
 118 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
 119 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
 120 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
 121 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
 122 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
 123 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
 124 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
 125 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
 126 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
 127 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
 128 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
 129 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
 130 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
 131 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
 132 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
 133 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
 134 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw);
 135 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
 136 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
 137 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force);
 138 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
 139 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state);
 140
 141 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
 142 {
 143         return readw(hw->flash_address + reg);
 144 }
 145
 146 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
 147 {
 148         return readl(hw->flash_address + reg);
 149 }
 150
 151 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
 152 {
 153         writew(val, hw->flash_address + reg);
 154 }
 155
 156 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
 157 {
 158         writel(val, hw->flash_address + reg);
 159 }
 160
 161 #define er16flash(reg)          __er16flash(hw, (reg))
 162 #define er32flash(reg)          __er32flash(hw, (reg))
 163 #define ew16flash(reg, val)     __ew16flash(hw, (reg), (val))
 164 #define ew32flash(reg, val)     __ew32flash(hw, (reg), (val))
 165
 166 /**
 167  *  e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
 168  *  @hw: pointer to the HW structure
 169  *
 170  *  Test access to the PHY registers by reading the PHY ID registers.  If
 171  *  the PHY ID is already known (e.g. resume path) compare it with known ID,
 172  *  otherwise assume the read PHY ID is correct if it is valid.
 173  *
 174  *  Assumes the sw/fw/hw semaphore is already acquired.
 175  **/
 176 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
 177 {
 178         u16 phy_reg = 0;
 179         u32 phy_id = 0;
 180         s32 ret_val = 0;
 181         u16 retry_count;
 182         u32 mac_reg = 0;
 183
 184         for (retry_count = 0; retry_count < 2; retry_count++) {
 185                 ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg);
 186                 if (ret_val || (phy_reg == 0xFFFF))
 187                         continue;
 188                 phy_id = (u32)(phy_reg << 16);
 189
 190                 ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg);
 191                 if (ret_val || (phy_reg == 0xFFFF)) {
 192                         phy_id = 0;
 193                         continue;
 194                 }
 195                 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
 196                 break;
 197         }
 198
 199         if (hw->phy.id) {
 200                 if (hw->phy.id == phy_id)
 201                         goto out;
 202         } else if (phy_id) {
 203                 hw->phy.id = phy_id;
 204                 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
 205                 goto out;
 206         }
 207
 208         /* In case the PHY needs to be in mdio slow mode,
 209          * set slow mode and try to get the PHY id again.
 210          */
 211         if (hw->mac.type < e1000_pch_lpt) {
 212                 hw->phy.ops.release(hw);
 213                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
 214                 if (!ret_val)
 215                         ret_val = e1000e_get_phy_id(hw);
 216                 hw->phy.ops.acquire(hw);
 217         }
 218
 219         if (ret_val)
 220                 return false;
 221 out:
 222         if (hw->mac.type >= e1000_pch_lpt) {
 223                 /* Only unforce SMBus if ME is not active */
 224                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
 225                         /* Unforce SMBus mode in PHY */
 226                         e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg);
 227                         phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
 228                         e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg);
 229
 230                         /* Unforce SMBus mode in MAC */
 231                         mac_reg = er32(CTRL_EXT);
 232                         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
 233                         ew32(CTRL_EXT, mac_reg);
 234                 }
 235         }
 236
 237         return true;
 238 }
 239
 240 /**
 241  *  e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
 242  *  @hw: pointer to the HW structure
 243  *
 244  *  Toggling the LANPHYPC pin value fully power-cycles the PHY and is
 245  *  used to reset the PHY to a quiescent state when necessary.
 246  **/
 247 static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
 248 {
 249         u32 mac_reg;
 250
 251         /* Set Phy Config Counter to 50msec */
 252         mac_reg = er32(FEXTNVM3);
 253         mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
 254         mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
 255         ew32(FEXTNVM3, mac_reg);
 256
 257         /* Toggle LANPHYPC Value bit */
 258         mac_reg = er32(CTRL);
 259         mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
 260         mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
 261         ew32(CTRL, mac_reg);
 262         e1e_flush();
 263         usleep_range(10, 20);
 264         mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
 265         ew32(CTRL, mac_reg);
 266         e1e_flush();
 267
 268         if (hw->mac.type < e1000_pch_lpt) {
 269                 msleep(50);
 270         } else {
 271                 u16 count = 20;
 272
 273                 do {
 274                         usleep_range(5000, 6000);
 275                 } while (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LPCD) && count--);
 276
 277                 msleep(30);
 278         }
 279 }
 280
 281 /**
 282  *  e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
 283  *  @hw: pointer to the HW structure
 284  *
 285  *  Workarounds/flow necessary for PHY initialization during driver load
 286  *  and resume paths.
 287  **/
 288 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
 289 {
 290         struct e1000_adapter *adapter = hw->adapter;
 291         u32 mac_reg, fwsm = er32(FWSM);
 292         s32 ret_val;
 293
 294         /* Gate automatic PHY configuration by hardware on managed and
 295          * non-managed 82579 and newer adapters.
 296          */
 297         e1000_gate_hw_phy_config_ich8lan(hw, true);
 298
 299         /* It is not possible to be certain of the current state of ULP
 300          * so forcibly disable it.
 301          */
 302         hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
 303         ret_val = e1000_disable_ulp_lpt_lp(hw, true);
 304         if (ret_val)
 305                 e_warn("Failed to disable ULP\n");
 306
 307         ret_val = hw->phy.ops.acquire(hw);
 308         if (ret_val) {
 309                 e_dbg("Failed to initialize PHY flow\n");
 310                 goto out;
 311         }
 312
 313         /* The MAC-PHY interconnect may be in SMBus mode.  If the PHY is
 314          * inaccessible and resetting the PHY is not blocked, toggle the
 315          * LANPHYPC Value bit to force the interconnect to PCIe mode.
 316          */
 317         switch (hw->mac.type) {
 318         case e1000_pch_lpt:
 319         case e1000_pch_spt:
 320         case e1000_pch_cnp:
 321         case e1000_pch_tgp:
 322         case e1000_pch_adp:
 323         case e1000_pch_mtp:
 324         case e1000_pch_lnp:
 325                 if (e1000_phy_is_accessible_pchlan(hw))
 326                         break;
 327
 328                 /* Before toggling LANPHYPC, see if PHY is accessible by
 329                  * forcing MAC to SMBus mode first.
 330                  */
 331                 mac_reg = er32(CTRL_EXT);
 332                 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
 333                 ew32(CTRL_EXT, mac_reg);
 334
 335                 /* Wait 50 milliseconds for MAC to finish any retries
 336                  * that it might be trying to perform from previous
 337                  * attempts to acknowledge any phy read requests.
 338                  */
 339                 msleep(50);
 340
 341                 fallthrough;
 342         case e1000_pch2lan:
 343                 if (e1000_phy_is_accessible_pchlan(hw))
 344                         break;
 345
 346                 fallthrough;
 347         case e1000_pchlan:
 348                 if ((hw->mac.type == e1000_pchlan) &&
 349                     (fwsm & E1000_ICH_FWSM_FW_VALID))
 350                         break;
 351
 352                 if (hw->phy.ops.check_reset_block(hw)) {
 353                         e_dbg("Required LANPHYPC toggle blocked by ME\n");
 354                         ret_val = -E1000_ERR_PHY;
 355                         break;
 356                 }
 357
 358                 /* Toggle LANPHYPC Value bit */
 359                 e1000_toggle_lanphypc_pch_lpt(hw);
 360                 if (hw->mac.type >= e1000_pch_lpt) {
 361                         if (e1000_phy_is_accessible_pchlan(hw))
 362                                 break;
 363
 364                         /* Toggling LANPHYPC brings the PHY out of SMBus mode
 365                          * so ensure that the MAC is also out of SMBus mode
 366                          */
 367                         mac_reg = er32(CTRL_EXT);
 368                         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
 369                         ew32(CTRL_EXT, mac_reg);
 370
 371                         if (e1000_phy_is_accessible_pchlan(hw))
 372                                 break;
 373
 374                         ret_val = -E1000_ERR_PHY;
 375                 }
 376                 break;
 377         default:
 378                 break;
 379         }
 380
 381         hw->phy.ops.release(hw);
 382         if (!ret_val) {
 383
 384                 /* Check to see if able to reset PHY.  Print error if not */
 385                 if (hw->phy.ops.check_reset_block(hw)) {
 386                         e_err("Reset blocked by ME\n");
 387                         goto out;
 388                 }
 389
 390                 /* Reset the PHY before any access to it.  Doing so, ensures
 391                  * that the PHY is in a known good state before we read/write
 392                  * PHY registers.  The generic reset is sufficient here,
 393                  * because we haven't determined the PHY type yet.
 394                  */
 395                 ret_val = e1000e_phy_hw_reset_generic(hw);
 396                 if (ret_val)
 397                         goto out;
 398
 399                 /* On a successful reset, possibly need to wait for the PHY
 400                  * to quiesce to an accessible state before returning control
 401                  * to the calling function.  If the PHY does not quiesce, then
 402                  * return E1000E_BLK_PHY_RESET, as this is the condition that
 403                  *  the PHY is in.
 404                  */
 405                 ret_val = hw->phy.ops.check_reset_block(hw);
 406                 if (ret_val)
 407                         e_err("ME blocked access to PHY after reset\n");
 408         }
 409
 410 out:
 411         /* Ungate automatic PHY configuration on non-managed 82579 */
 412         if ((hw->mac.type == e1000_pch2lan) &&
 413             !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
 414                 usleep_range(10000, 11000);
 415                 e1000_gate_hw_phy_config_ich8lan(hw, false);
 416         }
 417
 418         return ret_val;
 419 }
 420
 421 /**
 422  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 423  *  @hw: pointer to the HW structure
 424  *
 425  *  Initialize family-specific PHY parameters and function pointers.
 426  **/
 427 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 428 {
 429         struct e1000_phy_info *phy = &hw->phy;
 430         s32 ret_val;
 431
 432         phy->addr = 1;
 433         phy->reset_delay_us = 100;
 434
 435         phy->ops.set_page = e1000_set_page_igp;
 436         phy->ops.read_reg = e1000_read_phy_reg_hv;
 437         phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
 438         phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;
 439         phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
 440         phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
 441         phy->ops.write_reg = e1000_write_phy_reg_hv;
 442         phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
 443         phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
 444         phy->ops.power_up = e1000_power_up_phy_copper;
 445         phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
 446         phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 447
 448         phy->id = e1000_phy_unknown;
 449
 450         ret_val = e1000_init_phy_workarounds_pchlan(hw);
 451         if (ret_val)
 452                 return ret_val;
 453
 454         if (phy->id == e1000_phy_unknown)
 455                 switch (hw->mac.type) {
 456                 default:
 457                         ret_val = e1000e_get_phy_id(hw);
 458                         if (ret_val)
 459                                 return ret_val;
 460                         if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
 461                                 break;
 462                         fallthrough;
 463                 case e1000_pch2lan:
 464                 case e1000_pch_lpt:
 465                 case e1000_pch_spt:
 466                 case e1000_pch_cnp:
 467                 case e1000_pch_tgp:
 468                 case e1000_pch_adp:
 469                 case e1000_pch_mtp:
 470                 case e1000_pch_lnp:
 471                         /* In case the PHY needs to be in mdio slow mode,
 472                          * set slow mode and try to get the PHY id again.
 473                          */
 474                         ret_val = e1000_set_mdio_slow_mode_hv(hw);
 475                         if (ret_val)
 476                                 return ret_val;
 477                         ret_val = e1000e_get_phy_id(hw);
 478                         if (ret_val)
 479                                 return ret_val;
 480                         break;
 481                 }
 482         phy->type = e1000e_get_phy_type_from_id(phy->id);
 483
 484         switch (phy->type) {
 485         case e1000_phy_82577:
 486         case e1000_phy_82579:
 487         case e1000_phy_i217:
 488                 phy->ops.check_polarity = e1000_check_polarity_82577;
 489                 phy->ops.force_speed_duplex =
 490                     e1000_phy_force_speed_duplex_82577;
 491                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 492                 phy->ops.get_info = e1000_get_phy_info_82577;
 493                 phy->ops.commit = e1000e_phy_sw_reset;
 494                 break;
 495         case e1000_phy_82578:
 496                 phy->ops.check_polarity = e1000_check_polarity_m88;
 497                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 498                 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
 499                 phy->ops.get_info = e1000e_get_phy_info_m88;
 500                 break;
 501         default:
 502                 ret_val = -E1000_ERR_PHY;
 503                 break;
 504         }
 505
 506         return ret_val;
 507 }
 508
 509 /**
 510  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 511  *  @hw: pointer to the HW structure
 512  *
 513  *  Initialize family-specific PHY parameters and function pointers.
 514  **/
 515 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 516 {
 517         struct e1000_phy_info *phy = &hw->phy;
 518         s32 ret_val;
 519         u16 i = 0;
 520
 521         phy->addr = 1;
 522         phy->reset_delay_us = 100;
 523
 524         phy->ops.power_up = e1000_power_up_phy_copper;
 525         phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
 526
 527         /* We may need to do this twice - once for IGP and if that fails,
 528          * we'll set BM func pointers and try again
 529          */
 530         ret_val = e1000e_determine_phy_address(hw);
 531         if (ret_val) {
 532                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 533                 phy->ops.read_reg = e1000e_read_phy_reg_bm;
 534                 ret_val = e1000e_determine_phy_address(hw);
 535                 if (ret_val) {
 536                         e_dbg("Cannot determine PHY addr. Erroring out\n");
 537                         return ret_val;
 538                 }
 539         }
 540
 541         phy->id = 0;
 542         while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
 543                (i++ < 100)) {
 544                 usleep_range(1000, 1100);
 545                 ret_val = e1000e_get_phy_id(hw);
 546                 if (ret_val)
 547                         return ret_val;
 548         }
 549
 550         /* Verify phy id */
 551         switch (phy->id) {
 552         case IGP03E1000_E_PHY_ID:
 553                 phy->type = e1000_phy_igp_3;
 554                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 555                 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
 556                 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
 557                 phy->ops.get_info = e1000e_get_phy_info_igp;
 558                 phy->ops.check_polarity = e1000_check_polarity_igp;
 559                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
 560                 break;
 561         case IFE_E_PHY_ID:
 562         case IFE_PLUS_E_PHY_ID:
 563         case IFE_C_E_PHY_ID:
 564                 phy->type = e1000_phy_ife;
 565                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 566                 phy->ops.get_info = e1000_get_phy_info_ife;
 567                 phy->ops.check_polarity = e1000_check_polarity_ife;
 568                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
 569                 break;
 570         case BME1000_E_PHY_ID:
 571                 phy->type = e1000_phy_bm;
 572                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 573                 phy->ops.read_reg = e1000e_read_phy_reg_bm;
 574                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 575                 phy->ops.commit = e1000e_phy_sw_reset;
 576                 phy->ops.get_info = e1000e_get_phy_info_m88;
 577                 phy->ops.check_polarity = e1000_check_polarity_m88;
 578                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 579                 break;
 580         default:
 581                 return -E1000_ERR_PHY;
 582         }
 583
 584         return 0;
 585 }
 586
 587 /**
 588  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 589  *  @hw: pointer to the HW structure
 590  *
 591  *  Initialize family-specific NVM parameters and function
 592  *  pointers.
 593  **/
 594 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 595 {
 596         struct e1000_nvm_info *nvm = &hw->nvm;
 597         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 598         u32 gfpreg, sector_base_addr, sector_end_addr;
 599         u16 i;
 600         u32 nvm_size;
 601
 602         nvm->type = e1000_nvm_flash_sw;
 603
 604         if (hw->mac.type >= e1000_pch_spt) {
 605                 /* in SPT, gfpreg doesn't exist. NVM size is taken from the
 606                  * STRAP register. This is because in SPT the GbE Flash region
 607                  * is no longer accessed through the flash registers. Instead,
 608                  * the mechanism has changed, and the Flash region access
 609                  * registers are now implemented in GbE memory space.
 610                  */
 611                 nvm->flash_base_addr = 0;
 612                 nvm_size = (((er32(STRAP) >> 1) & 0x1F) + 1)
 613                     * NVM_SIZE_MULTIPLIER;
 614                 nvm->flash_bank_size = nvm_size / 2;
 615                 /* Adjust to word count */
 616                 nvm->flash_bank_size /= sizeof(u16);
 617                 /* Set the base address for flash register access */
 618                 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR;
 619         } else {
 620                 /* Can't read flash registers if register set isn't mapped. */
 621                 if (!hw->flash_address) {
 622                         e_dbg("ERROR: Flash registers not mapped\n");
 623                         return -E1000_ERR_CONFIG;
 624                 }
 625
 626                 gfpreg = er32flash(ICH_FLASH_GFPREG);
 627
 628                 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
 629                  * Add 1 to sector_end_addr since this sector is included in
 630                  * the overall size.
 631                  */
 632                 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 633                 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 634
 635                 /* flash_base_addr is byte-aligned */
 636                 nvm->flash_base_addr = sector_base_addr
 637                     << FLASH_SECTOR_ADDR_SHIFT;
 638
 639                 /* find total size of the NVM, then cut in half since the total
 640                  * size represents two separate NVM banks.
 641                  */
 642                 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
 643                                         << FLASH_SECTOR_ADDR_SHIFT);
 644                 nvm->flash_bank_size /= 2;
 645                 /* Adjust to word count */
 646                 nvm->flash_bank_size /= sizeof(u16);
 647         }
 648
 649         nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
 650
 651         /* Clear shadow ram */
 652         for (i = 0; i < nvm->word_size; i++) {
 653                 dev_spec->shadow_ram[i].modified = false;
 654                 dev_spec->shadow_ram[i].value = 0xFFFF;
 655         }
 656
 657         return 0;
 658 }
 659
 660 /**
 661  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 662  *  @hw: pointer to the HW structure
 663  *
 664  *  Initialize family-specific MAC parameters and function
 665  *  pointers.
 666  **/
 667 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
 668 {
 669         struct e1000_mac_info *mac = &hw->mac;
 670
 671         /* Set media type function pointer */
 672         hw->phy.media_type = e1000_media_type_copper;
 673
 674         /* Set mta register count */
 675         mac->mta_reg_count = 32;
 676         /* Set rar entry count */
 677         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 678         if (mac->type == e1000_ich8lan)
 679                 mac->rar_entry_count--;
 680         /* FWSM register */
 681         mac->has_fwsm = true;
 682         /* ARC subsystem not supported */
 683         mac->arc_subsystem_valid = false;
 684         /* Adaptive IFS supported */
 685         mac->adaptive_ifs = true;
 686
 687         /* LED and other operations */
 688         switch (mac->type) {
 689         case e1000_ich8lan:
 690         case e1000_ich9lan:
 691         case e1000_ich10lan:
 692                 /* check management mode */
 693                 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
 694                 /* ID LED init */
 695                 mac->ops.id_led_init = e1000e_id_led_init_generic;
 696                 /* blink LED */
 697                 mac->ops.blink_led = e1000e_blink_led_generic;
 698                 /* setup LED */
 699                 mac->ops.setup_led = e1000e_setup_led_generic;
 700                 /* cleanup LED */
 701                 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
 702                 /* turn on/off LED */
 703                 mac->ops.led_on = e1000_led_on_ich8lan;
 704                 mac->ops.led_off = e1000_led_off_ich8lan;
 705                 break;
 706         case e1000_pch2lan:
 707                 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
 708                 mac->ops.rar_set = e1000_rar_set_pch2lan;
 709                 fallthrough;
 710         case e1000_pch_lpt:
 711         case e1000_pch_spt:
 712         case e1000_pch_cnp:
 713         case e1000_pch_tgp:
 714         case e1000_pch_adp:
 715         case e1000_pch_mtp:
 716         case e1000_pch_lnp:
 717         case e1000_pchlan:
 718                 /* check management mode */
 719                 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
 720                 /* ID LED init */
 721                 mac->ops.id_led_init = e1000_id_led_init_pchlan;
 722                 /* setup LED */
 723                 mac->ops.setup_led = e1000_setup_led_pchlan;
 724                 /* cleanup LED */
 725                 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
 726                 /* turn on/off LED */
 727                 mac->ops.led_on = e1000_led_on_pchlan;
 728                 mac->ops.led_off = e1000_led_off_pchlan;
 729                 break;
 730         default:
 731                 break;
 732         }
 733
 734         if (mac->type >= e1000_pch_lpt) {
 735                 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
 736                 mac->ops.rar_set = e1000_rar_set_pch_lpt;
 737                 mac->ops.setup_physical_interface =
 738                     e1000_setup_copper_link_pch_lpt;
 739                 mac->ops.rar_get_count = e1000_rar_get_count_pch_lpt;
 740         }
 741
 742         /* Enable PCS Lock-loss workaround for ICH8 */
 743         if (mac->type == e1000_ich8lan)
 744                 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
 745
 746         return 0;
 747 }
 748
 749 /**
 750  *  __e1000_access_emi_reg_locked - Read/write EMI register
 751  *  @hw: pointer to the HW structure
 752  *  @address: EMI address to program
 753  *  @data: pointer to value to read/write from/to the EMI address
 754  *  @read: boolean flag to indicate read or write
 755  *
 756  *  This helper function assumes the SW/FW/HW Semaphore is already acquired.
 757  **/
 758 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
 759                                          u16 *data, bool read)
 760 {
 761         s32 ret_val;
 762
 763         ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address);
 764         if (ret_val)
 765                 return ret_val;
 766
 767         if (read)
 768                 ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data);
 769         else
 770                 ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data);
 771
 772         return ret_val;
 773 }
 774
 775 /**
 776  *  e1000_read_emi_reg_locked - Read Extended Management Interface register
 777  *  @hw: pointer to the HW structure
 778  *  @addr: EMI address to program
 779  *  @data: value to be read from the EMI address
 780  *
 781  *  Assumes the SW/FW/HW Semaphore is already acquired.
 782  **/
 783 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
 784 {
 785         return __e1000_access_emi_reg_locked(hw, addr, data, true);
 786 }
 787
 788 /**
 789  *  e1000_write_emi_reg_locked - Write Extended Management Interface register
 790  *  @hw: pointer to the HW structure
 791  *  @addr: EMI address to program
 792  *  @data: value to be written to the EMI address
 793  *
 794  *  Assumes the SW/FW/HW Semaphore is already acquired.
 795  **/
 796 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
 797 {
 798         return __e1000_access_emi_reg_locked(hw, addr, &data, false);
 799 }
 800
 801 /**
 802  *  e1000_set_eee_pchlan - Enable/disable EEE support
 803  *  @hw: pointer to the HW structure
 804  *
 805  *  Enable/disable EEE based on setting in dev_spec structure, the duplex of
 806  *  the link and the EEE capabilities of the link partner.  The LPI Control
 807  *  register bits will remain set only if/when link is up.
 808  *
 809  *  EEE LPI must not be asserted earlier than one second after link is up.
 810  *  On 82579, EEE LPI should not be enabled until such time otherwise there
 811  *  can be link issues with some switches.  Other devices can have EEE LPI
 812  *  enabled immediately upon link up since they have a timer in hardware which
 813  *  prevents LPI from being asserted too early.
 814  **/
 815 s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
 816 {
 817         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 818         s32 ret_val;
 819         u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
 820
 821         switch (hw->phy.type) {
 822         case e1000_phy_82579:
 823                 lpa = I82579_EEE_LP_ABILITY;
 824                 pcs_status = I82579_EEE_PCS_STATUS;
 825                 adv_addr = I82579_EEE_ADVERTISEMENT;
 826                 break;
 827         case e1000_phy_i217:
 828                 lpa = I217_EEE_LP_ABILITY;
 829                 pcs_status = I217_EEE_PCS_STATUS;
 830                 adv_addr = I217_EEE_ADVERTISEMENT;
 831                 break;
 832         default:
 833                 return 0;
 834         }
 835
 836         ret_val = hw->phy.ops.acquire(hw);
 837         if (ret_val)
 838                 return ret_val;
 839
 840         ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
 841         if (ret_val)
 842                 goto release;
 843
 844         /* Clear bits that enable EEE in various speeds */
 845         lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
 846
 847         /* Enable EEE if not disabled by user */
 848         if (!dev_spec->eee_disable) {
 849                 /* Save off link partner's EEE ability */
 850                 ret_val = e1000_read_emi_reg_locked(hw, lpa,
 851                                                     &dev_spec->eee_lp_ability);
 852                 if (ret_val)
 853                         goto release;
 854
 855                 /* Read EEE advertisement */
 856                 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
 857                 if (ret_val)
 858                         goto release;
 859
 860                 /* Enable EEE only for speeds in which the link partner is
 861                  * EEE capable and for which we advertise EEE.
 862                  */
 863                 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
 864                         lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
 865
 866                 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
 867                         e1e_rphy_locked(hw, MII_LPA, &data);
 868                         if (data & LPA_100FULL)
 869                                 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
 870                         else
 871                                 /* EEE is not supported in 100Half, so ignore
 872                                  * partner's EEE in 100 ability if full-duplex
 873                                  * is not advertised.
 874                                  */
 875                                 dev_spec->eee_lp_ability &=
 876                                     ~I82579_EEE_100_SUPPORTED;
 877                 }
 878         }
 879
 880         if (hw->phy.type == e1000_phy_82579) {
 881                 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
 882                                                     &data);
 883                 if (ret_val)
 884                         goto release;
 885
 886                 data &= ~I82579_LPI_100_PLL_SHUT;
 887                 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
 888                                                      data);
 889         }
 890
 891         /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
 892         ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
 893         if (ret_val)
 894                 goto release;
 895
 896         ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
 897 release:
 898         hw->phy.ops.release(hw);
 899
 900         return ret_val;
 901 }
 902
 903 /**
 904  *  e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
 905  *  @hw:   pointer to the HW structure
 906  *  @link: link up bool flag
 907  *
 908  *  When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
 909  *  preventing further DMA write requests.  Workaround the issue by disabling
 910  *  the de-assertion of the clock request when in 1Gpbs mode.
 911  *  Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
 912  *  speeds in order to avoid Tx hangs.
 913  **/
 914 static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
 915 {
 916         u32 fextnvm6 = er32(FEXTNVM6);
 917         u32 status = er32(STATUS);
 918         s32 ret_val = 0;
 919         u16 reg;
 920
 921         if (link && (status & E1000_STATUS_SPEED_1000)) {
 922                 ret_val = hw->phy.ops.acquire(hw);
 923                 if (ret_val)
 924                         return ret_val;
 925
 926                 ret_val =
 927                     e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
 928                                                 &reg);
 929                 if (ret_val)
 930                         goto release;
 931
 932                 ret_val =
 933                     e1000e_write_kmrn_reg_locked(hw,
 934                                                  E1000_KMRNCTRLSTA_K1_CONFIG,
 935                                                  reg &
 936                                                  ~E1000_KMRNCTRLSTA_K1_ENABLE);
 937                 if (ret_val)
 938                         goto release;
 939
 940                 usleep_range(10, 20);
 941
 942                 ew32(FEXTNVM6, fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
 943
 944                 ret_val =
 945                     e1000e_write_kmrn_reg_locked(hw,
 946                                                  E1000_KMRNCTRLSTA_K1_CONFIG,
 947                                                  reg);
 948 release:
 949                 hw->phy.ops.release(hw);
 950         } else {
 951                 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
 952                 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
 953
 954                 if ((hw->phy.revision > 5) || !link ||
 955                     ((status & E1000_STATUS_SPEED_100) &&
 956                      (status & E1000_STATUS_FD)))
 957                         goto update_fextnvm6;
 958
 959                 ret_val = e1e_rphy(hw, I217_INBAND_CTRL, &reg);
 960                 if (ret_val)
 961                         return ret_val;
 962
 963                 /* Clear link status transmit timeout */
 964                 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
 965
 966                 if (status & E1000_STATUS_SPEED_100) {
 967                         /* Set inband Tx timeout to 5x10us for 100Half */
 968                         reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
 969
 970                         /* Do not extend the K1 entry latency for 100Half */
 971                         fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
 972                 } else {
 973                         /* Set inband Tx timeout to 50x10us for 10Full/Half */
 974                         reg |= 50 <<
 975                             I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
 976
 977                         /* Extend the K1 entry latency for 10 Mbps */
 978                         fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
 979                 }
 980
 981                 ret_val = e1e_wphy(hw, I217_INBAND_CTRL, reg);
 982                 if (ret_val)
 983                         return ret_val;
 984
 985 update_fextnvm6:
 986                 ew32(FEXTNVM6, fextnvm6);
 987         }
 988
 989         return ret_val;
 990 }
 991
 992 /**
 993  *  e1000_platform_pm_pch_lpt - Set platform power management values
 994  *  @hw: pointer to the HW structure
 995  *  @link: bool indicating link status
 996  *
 997  *  Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like"
 998  *  GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed
 999  *  when link is up (which must not exceed the maximum latency supported
1000  *  by the platform), otherwise specify there is no LTR requirement.
1001  *  Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop
1002  *  latencies in the LTR Extended Capability Structure in the PCIe Extended
1003  *  Capability register set, on this device LTR is set by writing the
1004  *  equivalent snoop/no-snoop latencies in the LTRV register in the MAC and
1005  *  set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB)
1006  *  message to the PMC.
1007  **/
1008 static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)
1009 {
1010         u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) |
1011             link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND;
1012         u32 max_ltr_enc_d = 0;  /* maximum LTR decoded by platform */
1013         u32 lat_enc_d = 0;      /* latency decoded */
1014         u16 lat_enc = 0;        /* latency encoded */
1015
1016         if (link) {
1017                 u16 speed, duplex, scale = 0;
1018                 u16 max_snoop, max_nosnoop;
1019                 u16 max_ltr_enc;        /* max LTR latency encoded */
1020                 u64 value;
1021                 u32 rxa;
1022
1023                 if (!hw->adapter->max_frame_size) {
1024                         e_dbg("max_frame_size not set.\n");
1025                         return -E1000_ERR_CONFIG;
1026                 }
1027
1028                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1029                 if (!speed) {
1030                         e_dbg("Speed not set.\n");
1031                         return -E1000_ERR_CONFIG;
1032                 }
1033
1034                 /* Rx Packet Buffer Allocation size (KB) */
1035                 rxa = er32(PBA) & E1000_PBA_RXA_MASK;
1036
1037                 /* Determine the maximum latency tolerated by the device.
1038                  *
1039                  * Per the PCIe spec, the tolerated latencies are encoded as
1040                  * a 3-bit encoded scale (only 0-5 are valid) multiplied by
1041                  * a 10-bit value (0-1023) to provide a range from 1 ns to
1042                  * 2^25*(2^10-1) ns.  The scale is encoded as 0=2^0ns,
1043                  * 1=2^5ns, 2=2^10ns,...5=2^25ns.
1044                  */
1045                 rxa *= 512;
1046                 value = (rxa > hw->adapter->max_frame_size) ?
1047                         (rxa - hw->adapter->max_frame_size) * (16000 / speed) :
1048                         0;
1049
1050                 while (value > PCI_LTR_VALUE_MASK) {
1051                         scale++;
1052                         value = DIV_ROUND_UP(value, BIT(5));
1053                 }
1054                 if (scale > E1000_LTRV_SCALE_MAX) {
1055                         e_dbg("Invalid LTR latency scale %d\n", scale);
1056                         return -E1000_ERR_CONFIG;
1057                 }
1058                 lat_enc = (u16)((scale << PCI_LTR_SCALE_SHIFT) | value);
1059
1060                 /* Determine the maximum latency tolerated by the platform */
1061                 pci_read_config_word(hw->adapter->pdev, E1000_PCI_LTR_CAP_LPT,
1062                                      &max_snoop);
1063                 pci_read_config_word(hw->adapter->pdev,
1064                                      E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop);
1065                 max_ltr_enc = max_t(u16, max_snoop, max_nosnoop);
1066
1067                 lat_enc_d = (lat_enc & E1000_LTRV_VALUE_MASK) *
1068                              (1U << (E1000_LTRV_SCALE_FACTOR *
1069                              ((lat_enc & E1000_LTRV_SCALE_MASK)
1070                              >> E1000_LTRV_SCALE_SHIFT)));
1071
1072                 max_ltr_enc_d = (max_ltr_enc & E1000_LTRV_VALUE_MASK) *
1073                                  (1U << (E1000_LTRV_SCALE_FACTOR *
1074                                  ((max_ltr_enc & E1000_LTRV_SCALE_MASK)
1075                                  >> E1000_LTRV_SCALE_SHIFT)));
1076
1077                 if (lat_enc_d > max_ltr_enc_d)
1078                         lat_enc = max_ltr_enc;
1079         }
1080
1081         /* Set Snoop and No-Snoop latencies the same */
1082         reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT);
1083         ew32(LTRV, reg);
1084
1085         return 0;
1086 }
1087
1088 /**
1089  *  e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1090  *  @hw: pointer to the HW structure
1091  *  @to_sx: boolean indicating a system power state transition to Sx
1092  *
1093  *  When link is down, configure ULP mode to significantly reduce the power
1094  *  to the PHY.  If on a Manageability Engine (ME) enabled system, tell the
1095  *  ME firmware to start the ULP configuration.  If not on an ME enabled
1096  *  system, configure the ULP mode by software.
1097  */
1098 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1099 {
1100         u32 mac_reg;
1101         s32 ret_val = 0;
1102         u16 phy_reg;
1103         u16 oem_reg = 0;
1104
1105         if ((hw->mac.type < e1000_pch_lpt) ||
1106             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1107             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) ||
1108             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) ||
1109             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) ||
1110             (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1111                 return 0;
1112
1113         if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
1114                 /* Request ME configure ULP mode in the PHY */
1115                 mac_reg = er32(H2ME);
1116                 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
1117                 ew32(H2ME, mac_reg);
1118
1119                 goto out;
1120         }
1121
1122         if (!to_sx) {
1123                 int i = 0;
1124
1125                 /* Poll up to 5 seconds for Cable Disconnected indication */
1126                 while (!(er32(FEXT) & E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
1127                         /* Bail if link is re-acquired */
1128                         if (er32(STATUS) & E1000_STATUS_LU)
1129                                 return -E1000_ERR_PHY;
1130
1131                         if (i++ == 100)
1132                                 break;
1133
1134                         msleep(50);
1135                 }
1136                 e_dbg("CABLE_DISCONNECTED %s set after %dmsec\n",
1137                       (er32(FEXT) &
1138                        E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not", i * 50);
1139         }
1140
1141         ret_val = hw->phy.ops.acquire(hw);
1142         if (ret_val)
1143                 goto out;
1144
1145         /* Force SMBus mode in PHY */
1146         ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1147         if (ret_val)
1148                 goto release;
1149         phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1150         e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1151
1152         /* Force SMBus mode in MAC */
1153         mac_reg = er32(CTRL_EXT);
1154         mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1155         ew32(CTRL_EXT, mac_reg);
1156
1157         /* Si workaround for ULP entry flow on i127/rev6 h/w.  Enable
1158          * LPLU and disable Gig speed when entering ULP
1159          */
1160         if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) {
1161                 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS,
1162                                                        &oem_reg);
1163                 if (ret_val)
1164                         goto release;
1165
1166                 phy_reg = oem_reg;
1167                 phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS;
1168
1169                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1170                                                         phy_reg);
1171
1172                 if (ret_val)
1173                         goto release;
1174         }
1175
1176         /* Set Inband ULP Exit, Reset to SMBus mode and
1177          * Disable SMBus Release on PERST# in PHY
1178          */
1179         ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1180         if (ret_val)
1181                 goto release;
1182         phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1183                     I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1184         if (to_sx) {
1185                 if (er32(WUFC) & E1000_WUFC_LNKC)
1186                         phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1187                 else
1188                         phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1189
1190                 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1191                 phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT;
1192         } else {
1193                 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1194                 phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP;
1195                 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1196         }
1197         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1198
1199         /* Set Disable SMBus Release on PERST# in MAC */
1200         mac_reg = er32(FEXTNVM7);
1201         mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1202         ew32(FEXTNVM7, mac_reg);
1203
1204         /* Commit ULP changes in PHY by starting auto ULP configuration */
1205         phy_reg |= I218_ULP_CONFIG1_START;
1206         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1207
1208         if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) &&
1209             to_sx && (er32(STATUS) & E1000_STATUS_LU)) {
1210                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1211                                                         oem_reg);
1212                 if (ret_val)
1213                         goto release;
1214         }
1215
1216 release:
1217         hw->phy.ops.release(hw);
1218 out:
1219         if (ret_val)
1220                 e_dbg("Error in ULP enable flow: %d\n", ret_val);
1221         else
1222                 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1223
1224         return ret_val;
1225 }
1226
1227 /**
1228  *  e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1229  *  @hw: pointer to the HW structure
1230  *  @force: boolean indicating whether or not to force disabling ULP
1231  *
1232  *  Un-configure ULP mode when link is up, the system is transitioned from
1233  *  Sx or the driver is unloaded.  If on a Manageability Engine (ME) enabled
1234  *  system, poll for an indication from ME that ULP has been un-configured.
1235  *  If not on an ME enabled system, un-configure the ULP mode by software.
1236  *
1237  *  During nominal operation, this function is called when link is acquired
1238  *  to disable ULP mode (force=false); otherwise, for example when unloading
1239  *  the driver or during Sx->S0 transitions, this is called with force=true
1240  *  to forcibly disable ULP.
1241  */
1242 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1243 {
1244         s32 ret_val = 0;
1245         u32 mac_reg;
1246         u16 phy_reg;
1247         int i = 0;
1248
1249         if ((hw->mac.type < e1000_pch_lpt) ||
1250             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1251             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) ||
1252             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) ||
1253             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) ||
1254             (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
1255                 return 0;
1256
1257         if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
1258                 struct e1000_adapter *adapter = hw->adapter;
1259                 bool firmware_bug = false;
1260
1261                 if (force) {
1262                         /* Request ME un-configure ULP mode in the PHY */
1263                         mac_reg = er32(H2ME);
1264                         mac_reg &= ~E1000_H2ME_ULP;
1265                         mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1266                         ew32(H2ME, mac_reg);
1267                 }
1268
1269                 /* Poll up to 2.5 seconds for ME to clear ULP_CFG_DONE.
1270                  * If this takes more than 1 second, show a warning indicating a
1271                  * firmware bug
1272                  */
1273                 while (er32(FWSM) & E1000_FWSM_ULP_CFG_DONE) {
1274                         if (i++ == 250) {
1275                                 ret_val = -E1000_ERR_PHY;
1276                                 goto out;
1277                         }
1278                         if (i > 100 && !firmware_bug)
1279                                 firmware_bug = true;
1280
1281                         usleep_range(10000, 11000);
1282                 }
1283                 if (firmware_bug)
1284                         e_warn("ULP_CONFIG_DONE took %d msec. This is a firmware bug\n",
1285                                i * 10);
1286                 else
1287                         e_dbg("ULP_CONFIG_DONE cleared after %d msec\n",
1288                               i * 10);
1289
1290                 if (force) {
1291                         mac_reg = er32(H2ME);
1292                         mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
1293                         ew32(H2ME, mac_reg);
1294                 } else {
1295                         /* Clear H2ME.ULP after ME ULP configuration */
1296                         mac_reg = er32(H2ME);
1297                         mac_reg &= ~E1000_H2ME_ULP;
1298                         ew32(H2ME, mac_reg);
1299                 }
1300
1301                 goto out;
1302         }
1303
1304         ret_val = hw->phy.ops.acquire(hw);
1305         if (ret_val)
1306                 goto out;
1307
1308         if (force)
1309                 /* Toggle LANPHYPC Value bit */
1310                 e1000_toggle_lanphypc_pch_lpt(hw);
1311
1312         /* Unforce SMBus mode in PHY */
1313         ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1314         if (ret_val) {
1315                 /* The MAC might be in PCIe mode, so temporarily force to
1316                  * SMBus mode in order to access the PHY.
1317                  */
1318                 mac_reg = er32(CTRL_EXT);
1319                 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1320                 ew32(CTRL_EXT, mac_reg);
1321
1322                 msleep(50);
1323
1324                 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1325                                                        &phy_reg);
1326                 if (ret_val)
1327                         goto release;
1328         }
1329         phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1330         e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1331
1332         /* Unforce SMBus mode in MAC */
1333         mac_reg = er32(CTRL_EXT);
1334         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
1335         ew32(CTRL_EXT, mac_reg);
1336
1337         /* When ULP mode was previously entered, K1 was disabled by the
1338          * hardware.  Re-Enable K1 in the PHY when exiting ULP.
1339          */
1340         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1341         if (ret_val)
1342                 goto release;
1343         phy_reg |= HV_PM_CTRL_K1_ENABLE;
1344         e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
1345
1346         /* Clear ULP enabled configuration */
1347         ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1348         if (ret_val)
1349                 goto release;
1350         phy_reg &= ~(I218_ULP_CONFIG1_IND |
1351                      I218_ULP_CONFIG1_STICKY_ULP |
1352                      I218_ULP_CONFIG1_RESET_TO_SMBUS |
1353                      I218_ULP_CONFIG1_WOL_HOST |
1354                      I218_ULP_CONFIG1_INBAND_EXIT |
1355                      I218_ULP_CONFIG1_EN_ULP_LANPHYPC |
1356                      I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST |
1357                      I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1358         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1359
1360         /* Commit ULP changes by starting auto ULP configuration */
1361         phy_reg |= I218_ULP_CONFIG1_START;
1362         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1363
1364         /* Clear Disable SMBus Release on PERST# in MAC */
1365         mac_reg = er32(FEXTNVM7);
1366         mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
1367         ew32(FEXTNVM7, mac_reg);
1368
1369 release:
1370         hw->phy.ops.release(hw);
1371         if (force) {
1372                 e1000_phy_hw_reset(hw);
1373                 msleep(50);
1374         }
1375 out:
1376         if (ret_val)
1377                 e_dbg("Error in ULP disable flow: %d\n", ret_val);
1378         else
1379                 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
1380
1381         return ret_val;
1382 }
1383
1384 /**
1385  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1386  *  @hw: pointer to the HW structure
1387  *
1388  *  Checks to see of the link status of the hardware has changed.  If a
1389  *  change in link status has been detected, then we read the PHY registers
1390  *  to get the current speed/duplex if link exists.
1391  **/
1392 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1393 {
1394         struct e1000_mac_info *mac = &hw->mac;
1395         s32 ret_val, tipg_reg = 0;
1396         u16 emi_addr, emi_val = 0;
1397         bool link;
1398         u16 phy_reg;
1399
1400         /* We only want to go out to the PHY registers to see if Auto-Neg
1401          * has completed and/or if our link status has changed.  The
1402          * get_link_status flag is set upon receiving a Link Status
1403          * Change or Rx Sequence Error interrupt.
1404          */
1405         if (!mac->get_link_status)
1406                 return 0;
1407         mac->get_link_status = false;
1408
1409         /* First we want to see if the MII Status Register reports
1410          * link.  If so, then we want to get the current speed/duplex
1411          * of the PHY.
1412          */
1413         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1414         if (ret_val)
1415                 goto out;
1416
1417         if (hw->mac.type == e1000_pchlan) {
1418                 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1419                 if (ret_val)
1420                         goto out;
1421         }
1422
1423         /* When connected at 10Mbps half-duplex, some parts are excessively
1424          * aggressive resulting in many collisions. To avoid this, increase
1425          * the IPG and reduce Rx latency in the PHY.
1426          */
1427         if ((hw->mac.type >= e1000_pch2lan) && link) {
1428                 u16 speed, duplex;
1429
1430                 e1000e_get_speed_and_duplex_copper(hw, &speed, &duplex);
1431                 tipg_reg = er32(TIPG);
1432                 tipg_reg &= ~E1000_TIPG_IPGT_MASK;
1433
1434                 if (duplex == HALF_DUPLEX && speed == SPEED_10) {
1435                         tipg_reg |= 0xFF;
1436                         /* Reduce Rx latency in analog PHY */
1437                         emi_val = 0;
1438                 } else if (hw->mac.type >= e1000_pch_spt &&
1439                            duplex == FULL_DUPLEX && speed != SPEED_1000) {
1440                         tipg_reg |= 0xC;
1441                         emi_val = 1;
1442                 } else {
1443
1444                         /* Roll back the default values */
1445                         tipg_reg |= 0x08;
1446                         emi_val = 1;
1447                 }
1448
1449                 ew32(TIPG, tipg_reg);
1450
1451                 ret_val = hw->phy.ops.acquire(hw);
1452                 if (ret_val)
1453                         goto out;
1454
1455                 if (hw->mac.type == e1000_pch2lan)
1456                         emi_addr = I82579_RX_CONFIG;
1457                 else
1458                         emi_addr = I217_RX_CONFIG;
1459                 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val);
1460
1461                 if (hw->mac.type >= e1000_pch_lpt) {
1462                         u16 phy_reg;
1463
1464                         e1e_rphy_locked(hw, I217_PLL_CLOCK_GATE_REG, &phy_reg);
1465                         phy_reg &= ~I217_PLL_CLOCK_GATE_MASK;
1466                         if (speed == SPEED_100 || speed == SPEED_10)
1467                                 phy_reg |= 0x3E8;
1468                         else
1469                                 phy_reg |= 0xFA;
1470                         e1e_wphy_locked(hw, I217_PLL_CLOCK_GATE_REG, phy_reg);
1471
1472                         if (speed == SPEED_1000) {
1473                                 hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL,
1474                                                             &phy_reg);
1475
1476                                 phy_reg |= HV_PM_CTRL_K1_CLK_REQ;
1477
1478                                 hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL,
1479                                                              phy_reg);
1480                         }
1481                 }
1482                 hw->phy.ops.release(hw);
1483
1484                 if (ret_val)
1485                         goto out;
1486
1487                 if (hw->mac.type >= e1000_pch_spt) {
1488                         u16 data;
1489                         u16 ptr_gap;
1490
1491                         if (speed == SPEED_1000) {
1492                                 ret_val = hw->phy.ops.acquire(hw);
1493                                 if (ret_val)
1494                                         goto out;
1495
1496                                 ret_val = e1e_rphy_locked(hw,
1497                                                           PHY_REG(776, 20),
1498                                                           &data);
1499                                 if (ret_val) {
1500                                         hw->phy.ops.release(hw);
1501                                         goto out;
1502                                 }
1503
1504                                 ptr_gap = (data & (0x3FF << 2)) >> 2;
1505                                 if (ptr_gap < 0x18) {
1506                                         data &= ~(0x3FF << 2);
1507                                         data |= (0x18 << 2);
1508                                         ret_val =
1509                                             e1e_wphy_locked(hw,
1510                                                             PHY_REG(776, 20),
1511                                                             data);
1512                                 }
1513                                 hw->phy.ops.release(hw);
1514                                 if (ret_val)
1515                                         goto out;
1516                         } else {
1517                                 ret_val = hw->phy.ops.acquire(hw);
1518                                 if (ret_val)
1519                                         goto out;
1520
1521                                 ret_val = e1e_wphy_locked(hw,
1522                                                           PHY_REG(776, 20),
1523                                                           0xC023);
1524                                 hw->phy.ops.release(hw);
1525                                 if (ret_val)
1526                                         goto out;
1527
1528                         }
1529                 }
1530         }
1531
1532         /* I217 Packet Loss issue:
1533          * ensure that FEXTNVM4 Beacon Duration is set correctly
1534          * on power up.
1535          * Set the Beacon Duration for I217 to 8 usec
1536          */
1537         if (hw->mac.type >= e1000_pch_lpt) {
1538                 u32 mac_reg;
1539
1540                 mac_reg = er32(FEXTNVM4);
1541                 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1542                 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1543                 ew32(FEXTNVM4, mac_reg);
1544         }
1545
1546         /* Work-around I218 hang issue */
1547         if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1548             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1549             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM3) ||
1550             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V3)) {
1551                 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1552                 if (ret_val)
1553                         goto out;
1554         }
1555         if (hw->mac.type >= e1000_pch_lpt) {
1556                 /* Set platform power management values for
1557                  * Latency Tolerance Reporting (LTR)
1558                  */
1559                 ret_val = e1000_platform_pm_pch_lpt(hw, link);
1560                 if (ret_val)
1561                         goto out;
1562         }
1563
1564         /* Clear link partner's EEE ability */
1565         hw->dev_spec.ich8lan.eee_lp_ability = 0;
1566
1567         if (hw->mac.type >= e1000_pch_lpt) {
1568                 u32 fextnvm6 = er32(FEXTNVM6);
1569
1570                 if (hw->mac.type == e1000_pch_spt) {
1571                         /* FEXTNVM6 K1-off workaround - for SPT only */
1572                         u32 pcieanacfg = er32(PCIEANACFG);
1573
1574                         if (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE)
1575                                 fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE;
1576                         else
1577                                 fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
1578                 }
1579
1580                 ew32(FEXTNVM6, fextnvm6);
1581         }
1582
1583         if (!link)
1584                 goto out;
1585
1586         switch (hw->mac.type) {
1587         case e1000_pch2lan:
1588                 ret_val = e1000_k1_workaround_lv(hw);
1589                 if (ret_val)
1590                         return ret_val;
1591                 fallthrough;
1592         case e1000_pchlan:
1593                 if (hw->phy.type == e1000_phy_82578) {
1594                         ret_val = e1000_link_stall_workaround_hv(hw);
1595                         if (ret_val)
1596                                 return ret_val;
1597                 }
1598
1599                 /* Workaround for PCHx parts in half-duplex:
1600                  * Set the number of preambles removed from the packet
1601                  * when it is passed from the PHY to the MAC to prevent
1602                  * the MAC from misinterpreting the packet type.
1603                  */
1604                 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1605                 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1606
1607                 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD)
1608                         phy_reg |= BIT(HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1609
1610                 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1611                 break;
1612         default:
1613                 break;
1614         }
1615
1616         /* Check if there was DownShift, must be checked
1617          * immediately after link-up
1618          */
1619         e1000e_check_downshift(hw);
1620
1621         /* Enable/Disable EEE after link up */
1622         if (hw->phy.type > e1000_phy_82579) {
1623                 ret_val = e1000_set_eee_pchlan(hw);
1624                 if (ret_val)
1625                         return ret_val;
1626         }
1627
1628         /* If we are forcing speed/duplex, then we simply return since
1629          * we have already determined whether we have link or not.
1630          */
1631         if (!mac->autoneg)
1632                 return -E1000_ERR_CONFIG;
1633
1634         /* Auto-Neg is enabled.  Auto Speed Detection takes care
1635          * of MAC speed/duplex configuration.  So we only need to
1636          * configure Collision Distance in the MAC.
1637          */
1638         mac->ops.config_collision_dist(hw);
1639
1640         /* Configure Flow Control now that Auto-Neg has completed.
1641          * First, we need to restore the desired flow control
1642          * settings because we may have had to re-autoneg with a
1643          * different link partner.
1644          */
1645         ret_val = e1000e_config_fc_after_link_up(hw);
1646         if (ret_val)
1647                 e_dbg("Error configuring flow control\n");
1648
1649         return ret_val;
1650
1651 out:
1652         mac->get_link_status = true;
1653         return ret_val;
1654 }
1655
1656 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
1657 {
1658         struct e1000_hw *hw = &adapter->hw;
1659         s32 rc;
1660
1661         rc = e1000_init_mac_params_ich8lan(hw);
1662         if (rc)
1663                 return rc;
1664
1665         rc = e1000_init_nvm_params_ich8lan(hw);
1666         if (rc)
1667                 return rc;
1668
1669         switch (hw->mac.type) {
1670         case e1000_ich8lan:
1671         case e1000_ich9lan:
1672         case e1000_ich10lan:
1673                 rc = e1000_init_phy_params_ich8lan(hw);
1674                 break;
1675         case e1000_pchlan:
1676         case e1000_pch2lan:
1677         case e1000_pch_lpt:
1678         case e1000_pch_spt:
1679         case e1000_pch_cnp:
1680         case e1000_pch_tgp:
1681         case e1000_pch_adp:
1682         case e1000_pch_mtp:
1683         case e1000_pch_lnp:
1684                 rc = e1000_init_phy_params_pchlan(hw);
1685                 break;
1686         default:
1687                 break;
1688         }
1689         if (rc)
1690                 return rc;
1691
1692         /* Disable Jumbo Frame support on parts with Intel 10/100 PHY or
1693          * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
1694          */
1695         if ((adapter->hw.phy.type == e1000_phy_ife) ||
1696             ((adapter->hw.mac.type >= e1000_pch2lan) &&
1697              (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) {
1698                 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
1699                 adapter->max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
1700
1701                 hw->mac.ops.blink_led = NULL;
1702         }
1703
1704         if ((adapter->hw.mac.type == e1000_ich8lan) &&
1705             (adapter->hw.phy.type != e1000_phy_ife))
1706                 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
1707
1708         /* Enable workaround for 82579 w/ ME enabled */
1709         if ((adapter->hw.mac.type == e1000_pch2lan) &&
1710             (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
1711                 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA;
1712
1713         return 0;
1714 }
1715
1716 static DEFINE_MUTEX(nvm_mutex);
1717
1718 /**
1719  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1720  *  @hw: pointer to the HW structure
1721  *
1722  *  Acquires the mutex for performing NVM operations.
1723  **/
1724 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1725 {
1726         mutex_lock(&nvm_mutex);
1727
1728         return 0;
1729 }
1730
1731 /**
1732  *  e1000_release_nvm_ich8lan - Release NVM mutex
1733  *  @hw: pointer to the HW structure
1734  *
1735  *  Releases the mutex used while performing NVM operations.
1736  **/
1737 static void e1000_release_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1738 {
1739         mutex_unlock(&nvm_mutex);
1740 }
1741
1742 /**
1743  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
1744  *  @hw: pointer to the HW structure
1745  *
1746  *  Acquires the software control flag for performing PHY and select
1747  *  MAC CSR accesses.
1748  **/
1749 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1750 {
1751         u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1752         s32 ret_val = 0;
1753
1754         if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE,
1755                              &hw->adapter->state)) {
1756                 e_dbg("contention for Phy access\n");
1757                 return -E1000_ERR_PHY;
1758         }
1759
1760         while (timeout) {
1761                 extcnf_ctrl = er32(EXTCNF_CTRL);
1762                 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1763                         break;
1764
1765                 mdelay(1);
1766                 timeout--;
1767         }
1768
1769         if (!timeout) {
1770                 e_dbg("SW has already locked the resource.\n");
1771                 ret_val = -E1000_ERR_CONFIG;
1772                 goto out;
1773         }
1774
1775         timeout = SW_FLAG_TIMEOUT;
1776
1777         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1778         ew32(EXTCNF_CTRL, extcnf_ctrl);
1779
1780         while (timeout) {
1781                 extcnf_ctrl = er32(EXTCNF_CTRL);
1782                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1783                         break;
1784
1785                 mdelay(1);
1786                 timeout--;
1787         }
1788
1789         if (!timeout) {
1790                 e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1791                       er32(FWSM), extcnf_ctrl);
1792                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1793                 ew32(EXTCNF_CTRL, extcnf_ctrl);
1794                 ret_val = -E1000_ERR_CONFIG;
1795                 goto out;
1796         }
1797
1798 out:
1799         if (ret_val)
1800                 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1801
1802         return ret_val;
1803 }
1804
1805 /**
1806  *  e1000_release_swflag_ich8lan - Release software control flag
1807  *  @hw: pointer to the HW structure
1808  *
1809  *  Releases the software control flag for performing PHY and select
1810  *  MAC CSR accesses.
1811  **/
1812 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1813 {
1814         u32 extcnf_ctrl;
1815
1816         extcnf_ctrl = er32(EXTCNF_CTRL);
1817
1818         if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1819                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1820                 ew32(EXTCNF_CTRL, extcnf_ctrl);
1821         } else {
1822                 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");
1823         }
1824
1825         clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1826 }
1827
1828 /**
1829  *  e1000_check_mng_mode_ich8lan - Checks management mode
1830  *  @hw: pointer to the HW structure
1831  *
1832  *  This checks if the adapter has any manageability enabled.
1833  *  This is a function pointer entry point only called by read/write
1834  *  routines for the PHY and NVM parts.
1835  **/
1836 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1837 {
1838         u32 fwsm;
1839
1840         fwsm = er32(FWSM);
1841         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1842                 ((fwsm & E1000_FWSM_MODE_MASK) ==
1843                  (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1844 }
1845
1846 /**
1847  *  e1000_check_mng_mode_pchlan - Checks management mode
1848  *  @hw: pointer to the HW structure
1849  *
1850  *  This checks if the adapter has iAMT enabled.
1851  *  This is a function pointer entry point only called by read/write
1852  *  routines for the PHY and NVM parts.
1853  **/
1854 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1855 {
1856         u32 fwsm;
1857
1858         fwsm = er32(FWSM);
1859         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1860             (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1861 }
1862
1863 /**
1864  *  e1000_rar_set_pch2lan - Set receive address register
1865  *  @hw: pointer to the HW structure
1866  *  @addr: pointer to the receive address
1867  *  @index: receive address array register
1868  *
1869  *  Sets the receive address array register at index to the address passed
1870  *  in by addr.  For 82579, RAR[0] is the base address register that is to
1871  *  contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1872  *  Use SHRA[0-3] in place of those reserved for ME.
1873  **/
1874 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1875 {
1876         u32 rar_low, rar_high;
1877
1878         /* HW expects these in little endian so we reverse the byte order
1879          * from network order (big endian) to little endian
1880          */
1881         rar_low = ((u32)addr[0] |
1882                    ((u32)addr[1] << 8) |
1883                    ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1884
1885         rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1886
1887         /* If MAC address zero, no need to set the AV bit */
1888         if (rar_low || rar_high)
1889                 rar_high |= E1000_RAH_AV;
1890
1891         if (index == 0) {
1892                 ew32(RAL(index), rar_low);
1893                 e1e_flush();
1894                 ew32(RAH(index), rar_high);
1895                 e1e_flush();
1896                 return 0;
1897         }
1898
1899         /* RAR[1-6] are owned by manageability.  Skip those and program the
1900          * next address into the SHRA register array.
1901          */
1902         if (index < (u32)(hw->mac.rar_entry_count)) {
1903                 s32 ret_val;
1904
1905                 ret_val = e1000_acquire_swflag_ich8lan(hw);
1906                 if (ret_val)
1907                         goto out;
1908
1909                 ew32(SHRAL(index - 1), rar_low);
1910                 e1e_flush();
1911                 ew32(SHRAH(index - 1), rar_high);
1912                 e1e_flush();
1913
1914                 e1000_release_swflag_ich8lan(hw);
1915
1916                 /* verify the register updates */
1917                 if ((er32(SHRAL(index - 1)) == rar_low) &&
1918                     (er32(SHRAH(index - 1)) == rar_high))
1919                         return 0;
1920
1921                 e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1922                       (index - 1), er32(FWSM));
1923         }
1924
1925 out:
1926         e_dbg("Failed to write receive address at index %d\n", index);
1927         return -E1000_ERR_CONFIG;
1928 }
1929
1930 /**
1931  *  e1000_rar_get_count_pch_lpt - Get the number of available SHRA
1932  *  @hw: pointer to the HW structure
1933  *
1934  *  Get the number of available receive registers that the Host can
1935  *  program. SHRA[0-10] are the shared receive address registers
1936  *  that are shared between the Host and manageability engine (ME).
1937  *  ME can reserve any number of addresses and the host needs to be
1938  *  able to tell how many available registers it has access to.
1939  **/
1940 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw)
1941 {
1942         u32 wlock_mac;
1943         u32 num_entries;
1944
1945         wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
1946         wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1947
1948         switch (wlock_mac) {
1949         case 0:
1950                 /* All SHRA[0..10] and RAR[0] available */
1951                 num_entries = hw->mac.rar_entry_count;
1952                 break;
1953         case 1:
1954                 /* Only RAR[0] available */
1955                 num_entries = 1;
1956                 break;
1957         default:
1958                 /* SHRA[0..(wlock_mac - 1)] available + RAR[0] */
1959                 num_entries = wlock_mac + 1;
1960                 break;
1961         }
1962
1963         return num_entries;
1964 }
1965
1966 /**
1967  *  e1000_rar_set_pch_lpt - Set receive address registers
1968  *  @hw: pointer to the HW structure
1969  *  @addr: pointer to the receive address
1970  *  @index: receive address array register
1971  *
1972  *  Sets the receive address register array at index to the address passed
1973  *  in by addr. For LPT, RAR[0] is the base address register that is to
1974  *  contain the MAC address. SHRA[0-10] are the shared receive address
1975  *  registers that are shared between the Host and manageability engine (ME).
1976  **/
1977 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
1978 {
1979         u32 rar_low, rar_high;
1980         u32 wlock_mac;
1981
1982         /* HW expects these in little endian so we reverse the byte order
1983          * from network order (big endian) to little endian
1984          */
1985         rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
1986                    ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1987
1988         rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1989
1990         /* If MAC address zero, no need to set the AV bit */
1991         if (rar_low || rar_high)
1992                 rar_high |= E1000_RAH_AV;
1993
1994         if (index == 0) {
1995                 ew32(RAL(index), rar_low);
1996                 e1e_flush();
1997                 ew32(RAH(index), rar_high);
1998                 e1e_flush();
1999                 return 0;
2000         }
2001
2002         /* The manageability engine (ME) can lock certain SHRAR registers that
2003          * it is using - those registers are unavailable for use.
2004          */
2005         if (index < hw->mac.rar_entry_count) {
2006                 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
2007                 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
2008
2009                 /* Check if all SHRAR registers are locked */
2010                 if (wlock_mac == 1)
2011                         goto out;
2012
2013                 if ((wlock_mac == 0) || (index <= wlock_mac)) {
2014                         s32 ret_val;
2015
2016                         ret_val = e1000_acquire_swflag_ich8lan(hw);
2017
2018                         if (ret_val)
2019                                 goto out;
2020
2021                         ew32(SHRAL_PCH_LPT(index - 1), rar_low);
2022                         e1e_flush();
2023                         ew32(SHRAH_PCH_LPT(index - 1), rar_high);
2024                         e1e_flush();
2025
2026                         e1000_release_swflag_ich8lan(hw);
2027
2028                         /* verify the register updates */
2029                         if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) &&
2030                             (er32(SHRAH_PCH_LPT(index - 1)) == rar_high))
2031                                 return 0;
2032                 }
2033         }
2034
2035 out:
2036         e_dbg("Failed to write receive address at index %d\n", index);
2037         return -E1000_ERR_CONFIG;
2038 }
2039
2040 /**
2041  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
2042  *  @hw: pointer to the HW structure
2043  *
2044  *  Checks if firmware is blocking the reset of the PHY.
2045  *  This is a function pointer entry point only called by
2046  *  reset routines.
2047  **/
2048 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
2049 {
2050         bool blocked = false;
2051         int i = 0;
2052
2053         /* Check the PHY (LCD) reset flag */
2054         if (hw->phy.reset_disable)
2055                 return true;
2056
2057         while ((blocked = !(er32(FWSM) & E1000_ICH_FWSM_RSPCIPHY)) &&
2058                (i++ < 30))
2059                 usleep_range(10000, 11000);
2060         return blocked ? E1000_BLK_PHY_RESET : 0;
2061 }
2062
2063 /**
2064  *  e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
2065  *  @hw: pointer to the HW structure
2066  *
2067  *  Assumes semaphore already acquired.
2068  *
2069  **/
2070 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
2071 {
2072         u16 phy_data;
2073         u32 strap = er32(STRAP);
2074         u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
2075             E1000_STRAP_SMT_FREQ_SHIFT;
2076         s32 ret_val;
2077
2078         strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
2079
2080         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
2081         if (ret_val)
2082                 return ret_val;
2083
2084         phy_data &= ~HV_SMB_ADDR_MASK;
2085         phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
2086         phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
2087
2088         if (hw->phy.type == e1000_phy_i217) {
2089                 /* Restore SMBus frequency */
2090                 if (freq--) {
2091                         phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
2092                         phy_data |= (freq & BIT(0)) <<
2093                             HV_SMB_ADDR_FREQ_LOW_SHIFT;
2094                         phy_data |= (freq & BIT(1)) <<
2095                             (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
2096                 } else {
2097                         e_dbg("Unsupported SMB frequency in PHY\n");
2098                 }
2099         }
2100
2101         return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
2102 }
2103
2104 /**
2105  *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
2106  *  @hw:   pointer to the HW structure
2107  *
2108  *  SW should configure the LCD from the NVM extended configuration region
2109  *  as a workaround for certain parts.
2110  **/
2111 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
2112 {
2113         struct e1000_phy_info *phy = &hw->phy;
2114         u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
2115         s32 ret_val = 0;
2116         u16 word_addr, reg_data, reg_addr, phy_page = 0;
2117
2118         /* Initialize the PHY from the NVM on ICH platforms.  This
2119          * is needed due to an issue where the NVM configuration is
2120          * not properly autoloaded after power transitions.
2121          * Therefore, after each PHY reset, we will load the
2122          * configuration data out of the NVM manually.
2123          */
2124         switch (hw->mac.type) {
2125         case e1000_ich8lan:
2126                 if (phy->type != e1000_phy_igp_3)
2127                         return ret_val;
2128
2129                 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
2130                     (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
2131                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
2132                         break;
2133                 }
2134                 fallthrough;
2135         case e1000_pchlan:
2136         case e1000_pch2lan:
2137         case e1000_pch_lpt:
2138         case e1000_pch_spt:
2139         case e1000_pch_cnp:
2140         case e1000_pch_tgp:
2141         case e1000_pch_adp:
2142         case e1000_pch_mtp:
2143         case e1000_pch_lnp:
2144                 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
2145                 break;
2146         default:
2147                 return ret_val;
2148         }
2149
2150         ret_val = hw->phy.ops.acquire(hw);
2151         if (ret_val)
2152                 return ret_val;
2153
2154         data = er32(FEXTNVM);
2155         if (!(data & sw_cfg_mask))
2156                 goto release;
2157
2158         /* Make sure HW does not configure LCD from PHY
2159          * extended configuration before SW configuration
2160          */
2161         data = er32(EXTCNF_CTRL);
2162         if ((hw->mac.type < e1000_pch2lan) &&
2163             (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
2164                 goto release;
2165
2166         cnf_size = er32(EXTCNF_SIZE);
2167         cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
2168         cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
2169         if (!cnf_size)
2170                 goto release;
2171
2172         cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
2173         cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
2174
2175         if (((hw->mac.type == e1000_pchlan) &&
2176              !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
2177             (hw->mac.type > e1000_pchlan)) {
2178                 /* HW configures the SMBus address and LEDs when the
2179                  * OEM and LCD Write Enable bits are set in the NVM.
2180                  * When both NVM bits are cleared, SW will configure
2181                  * them instead.
2182                  */
2183                 ret_val = e1000_write_smbus_addr(hw);
2184                 if (ret_val)
2185                         goto release;
2186
2187                 data = er32(LEDCTL);
2188                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
2189                                                         (u16)data);
2190                 if (ret_val)
2191                         goto release;
2192         }
2193
2194         /* Configure LCD from extended configuration region. */
2195
2196         /* cnf_base_addr is in DWORD */
2197         word_addr = (u16)(cnf_base_addr << 1);
2198
2199         for (i = 0; i < cnf_size; i++) {
2200                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, &reg_data);
2201                 if (ret_val)
2202                         goto release;
2203
2204                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
2205                                          1, &reg_addr);
2206                 if (ret_val)
2207                         goto release;
2208
2209                 /* Save off the PHY page for future writes. */
2210                 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
2211                         phy_page = reg_data;
2212                         continue;
2213                 }
2214
2215                 reg_addr &= PHY_REG_MASK;
2216                 reg_addr |= phy_page;
2217
2218                 ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data);
2219                 if (ret_val)
2220                         goto release;
2221         }
2222
2223 release:
2224         hw->phy.ops.release(hw);
2225         return ret_val;
2226 }
2227
2228 /**
2229  *  e1000_k1_gig_workaround_hv - K1 Si workaround
2230  *  @hw:   pointer to the HW structure
2231  *  @link: link up bool flag
2232  *
2233  *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
2234  *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
2235  *  If link is down, the function will restore the default K1 setting located
2236  *  in the NVM.
2237  **/
2238 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
2239 {
2240         s32 ret_val = 0;
2241         u16 status_reg = 0;
2242         bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
2243
2244         if (hw->mac.type != e1000_pchlan)
2245                 return 0;
2246
2247         /* Wrap the whole flow with the sw flag */
2248         ret_val = hw->phy.ops.acquire(hw);
2249         if (ret_val)
2250                 return ret_val;
2251
2252         /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
2253         if (link) {
2254                 if (hw->phy.type == e1000_phy_82578) {
2255                         ret_val = e1e_rphy_locked(hw, BM_CS_STATUS,
2256                                                   &status_reg);
2257                         if (ret_val)
2258                                 goto release;
2259
2260                         status_reg &= (BM_CS_STATUS_LINK_UP |
2261                                        BM_CS_STATUS_RESOLVED |
2262                                        BM_CS_STATUS_SPEED_MASK);
2263
2264                         if (status_reg == (BM_CS_STATUS_LINK_UP |
2265                                            BM_CS_STATUS_RESOLVED |
2266                                            BM_CS_STATUS_SPEED_1000))
2267                                 k1_enable = false;
2268                 }
2269
2270                 if (hw->phy.type == e1000_phy_82577) {
2271                         ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg);
2272                         if (ret_val)
2273                                 goto release;
2274
2275                         status_reg &= (HV_M_STATUS_LINK_UP |
2276                                        HV_M_STATUS_AUTONEG_COMPLETE |
2277                                        HV_M_STATUS_SPEED_MASK);
2278
2279                         if (status_reg == (HV_M_STATUS_LINK_UP |
2280                                            HV_M_STATUS_AUTONEG_COMPLETE |
2281                                            HV_M_STATUS_SPEED_1000))
2282                                 k1_enable = false;
2283                 }
2284
2285                 /* Link stall fix for link up */
2286                 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100);
2287                 if (ret_val)
2288                         goto release;
2289
2290         } else {
2291                 /* Link stall fix for link down */
2292                 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100);
2293                 if (ret_val)
2294                         goto release;
2295         }
2296
2297         ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2298
2299 release:
2300         hw->phy.ops.release(hw);
2301
2302         return ret_val;
2303 }
2304
2305 /**
2306  *  e1000_configure_k1_ich8lan - Configure K1 power state
2307  *  @hw: pointer to the HW structure
2308  *  @k1_enable: K1 state to configure
2309  *
2310  *  Configure the K1 power state based on the provided parameter.
2311  *  Assumes semaphore already acquired.
2312  *
2313  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2314  **/
2315 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
2316 {
2317         s32 ret_val;
2318         u32 ctrl_reg = 0;
2319         u32 ctrl_ext = 0;
2320         u32 reg = 0;
2321         u16 kmrn_reg = 0;
2322
2323         ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2324                                               &kmrn_reg);
2325         if (ret_val)
2326                 return ret_val;
2327
2328         if (k1_enable)
2329                 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
2330         else
2331                 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
2332
2333         ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2334                                                kmrn_reg);
2335         if (ret_val)
2336                 return ret_val;
2337
2338         usleep_range(20, 40);
2339         ctrl_ext = er32(CTRL_EXT);
2340         ctrl_reg = er32(CTRL);
2341
2342         reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2343         reg |= E1000_CTRL_FRCSPD;
2344         ew32(CTRL, reg);
2345
2346         ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
2347         e1e_flush();
2348         usleep_range(20, 40);
2349         ew32(CTRL, ctrl_reg);
2350         ew32(CTRL_EXT, ctrl_ext);
2351         e1e_flush();
2352         usleep_range(20, 40);
2353
2354         return 0;
2355 }
2356
2357 /**
2358  *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2359  *  @hw:       pointer to the HW structure
2360  *  @d0_state: boolean if entering d0 or d3 device state
2361  *
2362  *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
2363  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
2364  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
2365  **/
2366 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
2367 {
2368         s32 ret_val = 0;
2369         u32 mac_reg;
2370         u16 oem_reg;
2371
2372         if (hw->mac.type < e1000_pchlan)
2373                 return ret_val;
2374
2375         ret_val = hw->phy.ops.acquire(hw);
2376         if (ret_val)
2377                 return ret_val;
2378
2379         if (hw->mac.type == e1000_pchlan) {
2380                 mac_reg = er32(EXTCNF_CTRL);
2381                 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
2382                         goto release;
2383         }
2384
2385         mac_reg = er32(FEXTNVM);
2386         if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
2387                 goto release;
2388
2389         mac_reg = er32(PHY_CTRL);
2390
2391         ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg);
2392         if (ret_val)
2393                 goto release;
2394
2395         oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
2396
2397         if (d0_state) {
2398                 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
2399                         oem_reg |= HV_OEM_BITS_GBE_DIS;
2400
2401                 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
2402                         oem_reg |= HV_OEM_BITS_LPLU;
2403         } else {
2404                 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
2405                                E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
2406                         oem_reg |= HV_OEM_BITS_GBE_DIS;
2407
2408                 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
2409                                E1000_PHY_CTRL_NOND0A_LPLU))
2410                         oem_reg |= HV_OEM_BITS_LPLU;
2411         }
2412
2413         /* Set Restart auto-neg to activate the bits */
2414         if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
2415             !hw->phy.ops.check_reset_block(hw))
2416                 oem_reg |= HV_OEM_BITS_RESTART_AN;
2417
2418         ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg);
2419
2420 release:
2421         hw->phy.ops.release(hw);
2422
2423         return ret_val;
2424 }
2425
2426 /**
2427  *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2428  *  @hw:   pointer to the HW structure
2429  **/
2430 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
2431 {
2432         s32 ret_val;
2433         u16 data;
2434
2435         ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
2436         if (ret_val)
2437                 return ret_val;
2438
2439         data |= HV_KMRN_MDIO_SLOW;
2440
2441         ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
2442
2443         return ret_val;
2444 }
2445
2446 /**
2447  *  e1000_hv_phy_workarounds_ich8lan - apply PHY workarounds
2448  *  @hw: pointer to the HW structure
2449  *
2450  *  A series of PHY workarounds to be done after every PHY reset.
2451  **/
2452 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2453 {
2454         s32 ret_val = 0;
2455         u16 phy_data;
2456
2457         if (hw->mac.type != e1000_pchlan)
2458                 return 0;
2459
2460         /* Set MDIO slow mode before any other MDIO access */
2461         if (hw->phy.type == e1000_phy_82577) {
2462                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2463                 if (ret_val)
2464                         return ret_val;
2465         }
2466
2467         if (((hw->phy.type == e1000_phy_82577) &&
2468              ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
2469             ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
2470                 /* Disable generation of early preamble */
2471                 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
2472                 if (ret_val)
2473                         return ret_val;
2474
2475                 /* Preamble tuning for SSC */
2476                 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204);
2477                 if (ret_val)
2478                         return ret_val;
2479         }
2480
2481         if (hw->phy.type == e1000_phy_82578) {
2482                 /* Return registers to default by doing a soft reset then
2483                  * writing 0x3140 to the control register.
2484                  */
2485                 if (hw->phy.revision < 2) {
2486                         e1000e_phy_sw_reset(hw);
2487                         ret_val = e1e_wphy(hw, MII_BMCR, 0x3140);
2488                         if (ret_val)
2489                                 return ret_val;
2490                 }
2491         }
2492
2493         /* Select page 0 */
2494         ret_val = hw->phy.ops.acquire(hw);
2495         if (ret_val)
2496                 return ret_val;
2497
2498         hw->phy.addr = 1;
2499         ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2500         hw->phy.ops.release(hw);
2501         if (ret_val)
2502                 return ret_val;
2503
2504         /* Configure the K1 Si workaround during phy reset assuming there is
2505          * link so that it disables K1 if link is in 1Gbps.
2506          */
2507         ret_val = e1000_k1_gig_workaround_hv(hw, true);
2508         if (ret_val)
2509                 return ret_val;
2510
2511         /* Workaround for link disconnects on a busy hub in half duplex */
2512         ret_val = hw->phy.ops.acquire(hw);
2513         if (ret_val)
2514                 return ret_val;
2515         ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2516         if (ret_val)
2517                 goto release;
2518         ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF);
2519         if (ret_val)
2520                 goto release;
2521
2522         /* set MSE higher to enable link to stay up when noise is high */
2523         ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2524 release:
2525         hw->phy.ops.release(hw);
2526
2527         return ret_val;
2528 }
2529
2530 /**
2531  *  e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2532  *  @hw:   pointer to the HW structure
2533  **/
2534 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
2535 {
2536         u32 mac_reg;
2537         u16 i, phy_reg = 0;
2538         s32 ret_val;
2539
2540         ret_val = hw->phy.ops.acquire(hw);
2541         if (ret_val)
2542                 return;
2543         ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2544         if (ret_val)
2545                 goto release;
2546
2547         /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
2548         for (i = 0; i < (hw->mac.rar_entry_count); i++) {
2549                 mac_reg = er32(RAL(i));
2550                 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
2551                                            (u16)(mac_reg & 0xFFFF));
2552                 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
2553                                            (u16)((mac_reg >> 16) & 0xFFFF));
2554
2555                 mac_reg = er32(RAH(i));
2556                 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
2557                                            (u16)(mac_reg & 0xFFFF));
2558                 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
2559                                            (u16)((mac_reg & E1000_RAH_AV)
2560                                                  >> 16));
2561         }
2562
2563         e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2564
2565 release:
2566         hw->phy.ops.release(hw);
2567 }
2568
2569 /**
2570  *  e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2571  *  with 82579 PHY
2572  *  @hw: pointer to the HW structure
2573  *  @enable: flag to enable/disable workaround when enabling/disabling jumbos
2574  **/
2575 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2576 {
2577         s32 ret_val = 0;
2578         u16 phy_reg, data;
2579         u32 mac_reg;
2580         u16 i;
2581
2582         if (hw->mac.type < e1000_pch2lan)
2583                 return 0;
2584
2585         /* disable Rx path while enabling/disabling workaround */
2586         e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
2587         ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | BIT(14));
2588         if (ret_val)
2589                 return ret_val;
2590
2591         if (enable) {
2592                 /* Write Rx addresses (rar_entry_count for RAL/H, and
2593                  * SHRAL/H) and initial CRC values to the MAC
2594                  */
2595                 for (i = 0; i < hw->mac.rar_entry_count; i++) {
2596                         u8 mac_addr[ETH_ALEN] = { 0 };
2597                         u32 addr_high, addr_low;
2598
2599                         addr_high = er32(RAH(i));
2600                         if (!(addr_high & E1000_RAH_AV))
2601                                 continue;
2602                         addr_low = er32(RAL(i));
2603                         mac_addr[0] = (addr_low & 0xFF);
2604                         mac_addr[1] = ((addr_low >> 8) & 0xFF);
2605                         mac_addr[2] = ((addr_low >> 16) & 0xFF);
2606                         mac_addr[3] = ((addr_low >> 24) & 0xFF);
2607                         mac_addr[4] = (addr_high & 0xFF);
2608                         mac_addr[5] = ((addr_high >> 8) & 0xFF);
2609
2610                         ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr));
2611                 }
2612
2613                 /* Write Rx addresses to the PHY */
2614                 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2615
2616                 /* Enable jumbo frame workaround in the MAC */
2617                 mac_reg = er32(FFLT_DBG);
2618                 mac_reg &= ~BIT(14);
2619                 mac_reg |= (7 << 15);
2620                 ew32(FFLT_DBG, mac_reg);
2621
2622                 mac_reg = er32(RCTL);
2623                 mac_reg |= E1000_RCTL_SECRC;
2624                 ew32(RCTL, mac_reg);
2625
2626                 ret_val = e1000e_read_kmrn_reg(hw,
2627                                                E1000_KMRNCTRLSTA_CTRL_OFFSET,
2628                                                &data);
2629                 if (ret_val)
2630                         return ret_val;
2631                 ret_val = e1000e_write_kmrn_reg(hw,
2632                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2633                                                 data | BIT(0));
2634                 if (ret_val)
2635                         return ret_val;
2636                 ret_val = e1000e_read_kmrn_reg(hw,
2637                                                E1000_KMRNCTRLSTA_HD_CTRL,
2638                                                &data);
2639                 if (ret_val)
2640                         return ret_val;
2641                 data &= ~(0xF << 8);
2642                 data |= (0xB << 8);
2643                 ret_val = e1000e_write_kmrn_reg(hw,
2644                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2645                                                 data);
2646                 if (ret_val)
2647                         return ret_val;
2648
2649                 /* Enable jumbo frame workaround in the PHY */
2650                 e1e_rphy(hw, PHY_REG(769, 23), &data);
2651                 data &= ~(0x7F << 5);
2652                 data |= (0x37 << 5);
2653                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2654                 if (ret_val)
2655                         return ret_val;
2656                 e1e_rphy(hw, PHY_REG(769, 16), &data);
2657                 data &= ~BIT(13);
2658                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2659                 if (ret_val)
2660                         return ret_val;
2661                 e1e_rphy(hw, PHY_REG(776, 20), &data);
2662                 data &= ~(0x3FF << 2);
2663                 data |= (E1000_TX_PTR_GAP << 2);
2664                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2665                 if (ret_val)
2666                         return ret_val;
2667                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100);
2668                 if (ret_val)
2669                         return ret_val;
2670                 e1e_rphy(hw, HV_PM_CTRL, &data);
2671                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | BIT(10));
2672                 if (ret_val)
2673                         return ret_val;
2674         } else {
2675                 /* Write MAC register values back to h/w defaults */
2676                 mac_reg = er32(FFLT_DBG);
2677                 mac_reg &= ~(0xF << 14);
2678                 ew32(FFLT_DBG, mac_reg);
2679
2680                 mac_reg = er32(RCTL);
2681                 mac_reg &= ~E1000_RCTL_SECRC;
2682                 ew32(RCTL, mac_reg);
2683
2684                 ret_val = e1000e_read_kmrn_reg(hw,
2685                                                E1000_KMRNCTRLSTA_CTRL_OFFSET,
2686                                                &data);
2687                 if (ret_val)
2688                         return ret_val;
2689                 ret_val = e1000e_write_kmrn_reg(hw,
2690                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2691                                                 data & ~BIT(0));
2692                 if (ret_val)
2693                         return ret_val;
2694                 ret_val = e1000e_read_kmrn_reg(hw,
2695                                                E1000_KMRNCTRLSTA_HD_CTRL,
2696                                                &data);
2697                 if (ret_val)
2698                         return ret_val;
2699                 data &= ~(0xF << 8);
2700                 data |= (0xB << 8);
2701                 ret_val = e1000e_write_kmrn_reg(hw,
2702                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2703                                                 data);
2704                 if (ret_val)
2705                         return ret_val;
2706
2707                 /* Write PHY register values back to h/w defaults */
2708                 e1e_rphy(hw, PHY_REG(769, 23), &data);
2709                 data &= ~(0x7F << 5);
2710                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2711                 if (ret_val)
2712                         return ret_val;
2713                 e1e_rphy(hw, PHY_REG(769, 16), &data);
2714                 data |= BIT(13);
2715                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2716                 if (ret_val)
2717                         return ret_val;
2718                 e1e_rphy(hw, PHY_REG(776, 20), &data);
2719                 data &= ~(0x3FF << 2);
2720                 data |= (0x8 << 2);
2721                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2722                 if (ret_val)
2723                         return ret_val;
2724                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
2725                 if (ret_val)
2726                         return ret_val;
2727                 e1e_rphy(hw, HV_PM_CTRL, &data);
2728                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~BIT(10));
2729                 if (ret_val)
2730                         return ret_val;
2731         }
2732
2733         /* re-enable Rx path after enabling/disabling workaround */
2734         return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~BIT(14));
2735 }
2736
2737 /**
2738  *  e1000_lv_phy_workarounds_ich8lan - apply ich8 specific workarounds
2739  *  @hw: pointer to the HW structure
2740  *
2741  *  A series of PHY workarounds to be done after every PHY reset.
2742  **/
2743 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2744 {
2745         s32 ret_val = 0;
2746
2747         if (hw->mac.type != e1000_pch2lan)
2748                 return 0;
2749
2750         /* Set MDIO slow mode before any other MDIO access */
2751         ret_val = e1000_set_mdio_slow_mode_hv(hw);
2752         if (ret_val)
2753                 return ret_val;
2754
2755         ret_val = hw->phy.ops.acquire(hw);
2756         if (ret_val)
2757                 return ret_val;
2758         /* set MSE higher to enable link to stay up when noise is high */
2759         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2760         if (ret_val)
2761                 goto release;
2762         /* drop link after 5 times MSE threshold was reached */
2763         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2764 release:
2765         hw->phy.ops.release(hw);
2766
2767         return ret_val;
2768 }
2769
2770 /**
2771  *  e1000_k1_workaround_lv - K1 Si workaround
2772  *  @hw:   pointer to the HW structure
2773  *
2774  *  Workaround to set the K1 beacon duration for 82579 parts in 10Mbps
2775  *  Disable K1 in 1000Mbps and 100Mbps
2776  **/
2777 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2778 {
2779         s32 ret_val = 0;
2780         u16 status_reg = 0;
2781
2782         if (hw->mac.type != e1000_pch2lan)
2783                 return 0;
2784
2785         /* Set K1 beacon duration based on 10Mbs speed */
2786         ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
2787         if (ret_val)
2788                 return ret_val;
2789
2790         if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2791             == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2792                 if (status_reg &
2793                     (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) {
2794                         u16 pm_phy_reg;
2795
2796                         /* LV 1G/100 Packet drop issue wa  */
2797                         ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg);
2798                         if (ret_val)
2799                                 return ret_val;
2800                         pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE;
2801                         ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg);
2802                         if (ret_val)
2803                                 return ret_val;
2804                 } else {
2805                         u32 mac_reg;
2806
2807                         mac_reg = er32(FEXTNVM4);
2808                         mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
2809                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
2810                         ew32(FEXTNVM4, mac_reg);
2811                 }
2812         }
2813
2814         return ret_val;
2815 }
2816
2817 /**
2818  *  e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2819  *  @hw:   pointer to the HW structure
2820  *  @gate: boolean set to true to gate, false to ungate
2821  *
2822  *  Gate/ungate the automatic PHY configuration via hardware; perform
2823  *  the configuration via software instead.
2824  **/
2825 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2826 {
2827         u32 extcnf_ctrl;
2828
2829         if (hw->mac.type < e1000_pch2lan)
2830                 return;
2831
2832         extcnf_ctrl = er32(EXTCNF_CTRL);
2833
2834         if (gate)
2835                 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2836         else
2837                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2838
2839         ew32(EXTCNF_CTRL, extcnf_ctrl);
2840 }
2841
2842 /**
2843  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
2844  *  @hw: pointer to the HW structure
2845  *
2846  *  Check the appropriate indication the MAC has finished configuring the
2847  *  PHY after a software reset.
2848  **/
2849 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2850 {
2851         u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
2852
2853         /* Wait for basic configuration completes before proceeding */
2854         do {
2855                 data = er32(STATUS);
2856                 data &= E1000_STATUS_LAN_INIT_DONE;
2857                 usleep_range(100, 200);
2858         } while ((!data) && --loop);
2859
2860         /* If basic configuration is incomplete before the above loop
2861          * count reaches 0, loading the configuration from NVM will
2862          * leave the PHY in a bad state possibly resulting in no link.
2863          */
2864         if (loop == 0)
2865                 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
2866
2867         /* Clear the Init Done bit for the next init event */
2868         data = er32(STATUS);
2869         data &= ~E1000_STATUS_LAN_INIT_DONE;
2870         ew32(STATUS, data);
2871 }
2872
2873 /**
2874  *  e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
2875  *  @hw: pointer to the HW structure
2876  **/
2877 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
2878 {
2879         s32 ret_val = 0;
2880         u16 reg;
2881
2882         if (hw->phy.ops.check_reset_block(hw))
2883                 return 0;
2884
2885         /* Allow time for h/w to get to quiescent state after reset */
2886         usleep_range(10000, 11000);
2887
2888         /* Perform any necessary post-reset workarounds */
2889         switch (hw->mac.type) {
2890         case e1000_pchlan:
2891                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2892                 if (ret_val)
2893                         return ret_val;
2894                 break;
2895         case e1000_pch2lan:
2896                 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
2897                 if (ret_val)
2898                         return ret_val;
2899                 break;
2900         default:
2901                 break;
2902         }
2903
2904         /* Clear the host wakeup bit after lcd reset */
2905         if (hw->mac.type >= e1000_pchlan) {
2906                 e1e_rphy(hw, BM_PORT_GEN_CFG, &reg);
2907                 reg &= ~BM_WUC_HOST_WU_BIT;
2908                 e1e_wphy(hw, BM_PORT_GEN_CFG, reg);
2909         }
2910
2911         /* Configure the LCD with the extended configuration region in NVM */
2912         ret_val = e1000_sw_lcd_config_ich8lan(hw);
2913         if (ret_val)
2914                 return ret_val;
2915
2916         /* Configure the LCD with the OEM bits in NVM */
2917         ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2918
2919         if (hw->mac.type == e1000_pch2lan) {
2920                 /* Ungate automatic PHY configuration on non-managed 82579 */
2921                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
2922                         usleep_range(10000, 11000);
2923                         e1000_gate_hw_phy_config_ich8lan(hw, false);
2924                 }
2925
2926                 /* Set EEE LPI Update Timer to 200usec */
2927                 ret_val = hw->phy.ops.acquire(hw);
2928                 if (ret_val)
2929                         return ret_val;
2930                 ret_val = e1000_write_emi_reg_locked(hw,
2931                                                      I82579_LPI_UPDATE_TIMER,
2932                                                      0x1387);
2933                 hw->phy.ops.release(hw);
2934         }
2935
2936         return ret_val;
2937 }
2938
2939 /**
2940  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
2941  *  @hw: pointer to the HW structure
2942  *
2943  *  Resets the PHY
2944  *  This is a function pointer entry point called by drivers
2945  *  or other shared routines.
2946  **/
2947 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
2948 {
2949         s32 ret_val = 0;
2950
2951         /* Gate automatic PHY configuration by hardware on non-managed 82579 */
2952         if ((hw->mac.type == e1000_pch2lan) &&
2953             !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
2954                 e1000_gate_hw_phy_config_ich8lan(hw, true);
2955
2956         ret_val = e1000e_phy_hw_reset_generic(hw);
2957         if (ret_val)
2958                 return ret_val;
2959
2960         return e1000_post_phy_reset_ich8lan(hw);
2961 }
2962
2963 /**
2964  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
2965  *  @hw: pointer to the HW structure
2966  *  @active: true to enable LPLU, false to disable
2967  *
2968  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
2969  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
2970  *  the phy speed. This function will manually set the LPLU bit and restart
2971  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
2972  *  since it configures the same bit.
2973  **/
2974 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
2975 {
2976         s32 ret_val;
2977         u16 oem_reg;
2978
2979         ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
2980         if (ret_val)
2981                 return ret_val;
2982
2983         if (active)
2984                 oem_reg |= HV_OEM_BITS_LPLU;
2985         else
2986                 oem_reg &= ~HV_OEM_BITS_LPLU;
2987
2988         if (!hw->phy.ops.check_reset_block(hw))
2989                 oem_reg |= HV_OEM_BITS_RESTART_AN;
2990
2991         return e1e_wphy(hw, HV_OEM_BITS, oem_reg);
2992 }
2993
2994 /**
2995  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
2996  *  @hw: pointer to the HW structure
2997  *  @active: true to enable LPLU, false to disable
2998  *
2999  *  Sets the LPLU D0 state according to the active flag.  When
3000  *  activating LPLU this function also disables smart speed
3001  *  and vice versa.  LPLU will not be activated unless the
3002  *  device autonegotiation advertisement meets standards of
3003  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
3004  *  This is a function pointer entry point only called by
3005  *  PHY setup routines.
3006  **/
3007 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3008 {
3009         struct e1000_phy_info *phy = &hw->phy;
3010         u32 phy_ctrl;
3011         s32 ret_val = 0;
3012         u16 data;
3013
3014         if (phy->type == e1000_phy_ife)
3015                 return 0;
3016
3017         phy_ctrl = er32(PHY_CTRL);
3018
3019         if (active) {
3020                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
3021                 ew32(PHY_CTRL, phy_ctrl);
3022
3023                 if (phy->type != e1000_phy_igp_3)
3024                         return 0;
3025
3026                 /* Call gig speed drop workaround on LPLU before accessing
3027                  * any PHY registers
3028                  */
3029                 if (hw->mac.type == e1000_ich8lan)
3030                         e1000e_gig_downshift_workaround_ich8lan(hw);
3031
3032                 /* When LPLU is enabled, we should disable SmartSpeed */
3033                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
3034                 if (ret_val)
3035                         return ret_val;
3036                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3037                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
3038                 if (ret_val)
3039                         return ret_val;
3040         } else {
3041                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
3042                 ew32(PHY_CTRL, phy_ctrl);
3043
3044                 if (phy->type != e1000_phy_igp_3)
3045                         return 0;
3046
3047                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
3048                  * during Dx states where the power conservation is most
3049                  * important.  During driver activity we should enable
3050                  * SmartSpeed, so performance is maintained.
3051                  */
3052                 if (phy->smart_speed == e1000_smart_speed_on) {
3053                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3054                                            &data);
3055                         if (ret_val)
3056                                 return ret_val;
3057
3058                         data |= IGP01E1000_PSCFR_SMART_SPEED;
3059                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3060                                            data);
3061                         if (ret_val)
3062                                 return ret_val;
3063                 } else if (phy->smart_speed == e1000_smart_speed_off) {
3064                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3065                                            &data);
3066                         if (ret_val)
3067                                 return ret_val;
3068
3069                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3070                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3071                                            data);
3072                         if (ret_val)
3073                                 return ret_val;
3074                 }
3075         }
3076
3077         return 0;
3078 }
3079
3080 /**
3081  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
3082  *  @hw: pointer to the HW structure
3083  *  @active: true to enable LPLU, false to disable
3084  *
3085  *  Sets the LPLU D3 state according to the active flag.  When
3086  *  activating LPLU this function also disables smart speed
3087  *  and vice versa.  LPLU will not be activated unless the
3088  *  device autonegotiation advertisement meets standards of
3089  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
3090  *  This is a function pointer entry point only called by
3091  *  PHY setup routines.
3092  **/
3093 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3094 {
3095         struct e1000_phy_info *phy = &hw->phy;
3096         u32 phy_ctrl;
3097         s32 ret_val = 0;
3098         u16 data;
3099
3100         phy_ctrl = er32(PHY_CTRL);
3101
3102         if (!active) {
3103                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
3104                 ew32(PHY_CTRL, phy_ctrl);
3105
3106                 if (phy->type != e1000_phy_igp_3)
3107                         return 0;
3108
3109                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
3110                  * during Dx states where the power conservation is most
3111                  * important.  During driver activity we should enable
3112                  * SmartSpeed, so performance is maintained.
3113                  */
3114                 if (phy->smart_speed == e1000_smart_speed_on) {
3115                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3116                                            &data);
3117                         if (ret_val)
3118                                 return ret_val;
3119
3120                         data |= IGP01E1000_PSCFR_SMART_SPEED;
3121                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3122                                            data);
3123                         if (ret_val)
3124                                 return ret_val;
3125                 } else if (phy->smart_speed == e1000_smart_speed_off) {
3126                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3127                                            &data);
3128                         if (ret_val)
3129                                 return ret_val;
3130
3131                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3132                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3133                                            data);
3134                         if (ret_val)
3135                                 return ret_val;
3136                 }
3137         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
3138                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
3139                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
3140                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
3141                 ew32(PHY_CTRL, phy_ctrl);
3142
3143                 if (phy->type != e1000_phy_igp_3)
3144                         return 0;
3145
3146                 /* Call gig speed drop workaround on LPLU before accessing
3147                  * any PHY registers
3148                  */
3149                 if (hw->mac.type == e1000_ich8lan)
3150                         e1000e_gig_downshift_workaround_ich8lan(hw);
3151
3152                 /* When LPLU is enabled, we should disable SmartSpeed */
3153                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
3154                 if (ret_val)
3155                         return ret_val;
3156
3157                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3158                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
3159         }
3160
3161         return ret_val;
3162 }
3163
3164 /**
3165  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
3166  *  @hw: pointer to the HW structure
3167  *  @bank:  pointer to the variable that returns the active bank
3168  *
3169  *  Reads signature byte from the NVM using the flash access registers.
3170  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
3171  **/
3172 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
3173 {
3174         u32 eecd;
3175         struct e1000_nvm_info *nvm = &hw->nvm;
3176         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
3177         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
3178         u32 nvm_dword = 0;
3179         u8 sig_byte = 0;
3180         s32 ret_val;
3181
3182         switch (hw->mac.type) {
3183         case e1000_pch_spt:
3184         case e1000_pch_cnp:
3185         case e1000_pch_tgp:
3186         case e1000_pch_adp:
3187         case e1000_pch_mtp:
3188         case e1000_pch_lnp:
3189                 bank1_offset = nvm->flash_bank_size;
3190                 act_offset = E1000_ICH_NVM_SIG_WORD;
3191
3192                 /* set bank to 0 in case flash read fails */
3193                 *bank = 0;
3194
3195                 /* Check bank 0 */
3196                 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset,
3197                                                          &nvm_dword);
3198                 if (ret_val)
3199                         return ret_val;
3200                 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3201                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3202                     E1000_ICH_NVM_SIG_VALUE) {
3203                         *bank = 0;
3204                         return 0;
3205                 }
3206
3207                 /* Check bank 1 */
3208                 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset +
3209                                                          bank1_offset,
3210                                                          &nvm_dword);
3211                 if (ret_val)
3212                         return ret_val;
3213                 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3214                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3215                     E1000_ICH_NVM_SIG_VALUE) {
3216                         *bank = 1;
3217                         return 0;
3218                 }
3219
3220                 e_dbg("ERROR: No valid NVM bank present\n");
3221                 return -E1000_ERR_NVM;
3222         case e1000_ich8lan:
3223         case e1000_ich9lan:
3224                 eecd = er32(EECD);
3225                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
3226                     E1000_EECD_SEC1VAL_VALID_MASK) {
3227                         if (eecd & E1000_EECD_SEC1VAL)
3228                                 *bank = 1;
3229                         else
3230                                 *bank = 0;
3231
3232                         return 0;
3233                 }
3234                 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n");
3235                 fallthrough;
3236         default:
3237                 /* set bank to 0 in case flash read fails */
3238                 *bank = 0;
3239
3240                 /* Check bank 0 */
3241                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
3242                                                         &sig_byte);
3243                 if (ret_val)
3244                         return ret_val;
3245                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3246                     E1000_ICH_NVM_SIG_VALUE) {
3247                         *bank = 0;
3248                         return 0;
3249                 }
3250
3251                 /* Check bank 1 */
3252                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
3253                                                         bank1_offset,
3254                                                         &sig_byte);
3255                 if (ret_val)
3256                         return ret_val;
3257                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3258                     E1000_ICH_NVM_SIG_VALUE) {
3259                         *bank = 1;
3260                         return 0;
3261                 }
3262
3263                 e_dbg("ERROR: No valid NVM bank present\n");
3264                 return -E1000_ERR_NVM;
3265         }
3266 }
3267
3268 /**
3269  *  e1000_read_nvm_spt - NVM access for SPT
3270  *  @hw: pointer to the HW structure
3271  *  @offset: The offset (in bytes) of the word(s) to read.
3272  *  @words: Size of data to read in words.
3273  *  @data: pointer to the word(s) to read at offset.
3274  *
3275  *  Reads a word(s) from the NVM
3276  **/
3277 static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
3278                               u16 *data)
3279 {
3280         struct e1000_nvm_info *nvm = &hw->nvm;
3281         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3282         u32 act_offset;
3283         s32 ret_val = 0;
3284         u32 bank = 0;
3285         u32 dword = 0;
3286         u16 offset_to_read;
3287         u16 i;
3288
3289         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3290             (words == 0)) {
3291                 e_dbg("nvm parameter(s) out of bounds\n");
3292                 ret_val = -E1000_ERR_NVM;
3293                 goto out;
3294         }
3295
3296         nvm->ops.acquire(hw);
3297
3298         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3299         if (ret_val) {
3300                 e_dbg("Could not detect valid bank, assuming bank 0\n");
3301                 bank = 0;
3302         }
3303
3304         act_offset = (bank) ? nvm->flash_bank_size : 0;
3305         act_offset += offset;
3306
3307         ret_val = 0;
3308
3309         for (i = 0; i < words; i += 2) {
3310                 if (words - i == 1) {
3311                         if (dev_spec->shadow_ram[offset + i].modified) {
3312                                 data[i] =
3313                                     dev_spec->shadow_ram[offset + i].value;
3314                         } else {
3315                                 offset_to_read = act_offset + i -
3316                                     ((act_offset + i) % 2);
3317                                 ret_val =
3318                                   e1000_read_flash_dword_ich8lan(hw,
3319                                                                  offset_to_read,
3320                                                                  &dword);
3321                                 if (ret_val)
3322                                         break;
3323                                 if ((act_offset + i) % 2 == 0)
3324                                         data[i] = (u16)(dword & 0xFFFF);
3325                                 else
3326                                         data[i] = (u16)((dword >> 16) & 0xFFFF);
3327                         }
3328                 } else {
3329                         offset_to_read = act_offset + i;
3330                         if (!(dev_spec->shadow_ram[offset + i].modified) ||
3331                             !(dev_spec->shadow_ram[offset + i + 1].modified)) {
3332                                 ret_val =
3333                                   e1000_read_flash_dword_ich8lan(hw,
3334                                                                  offset_to_read,
3335                                                                  &dword);
3336                                 if (ret_val)
3337                                         break;
3338                         }
3339                         if (dev_spec->shadow_ram[offset + i].modified)
3340                                 data[i] =
3341                                     dev_spec->shadow_ram[offset + i].value;
3342                         else
3343                                 data[i] = (u16)(dword & 0xFFFF);
3344                         if (dev_spec->shadow_ram[offset + i].modified)
3345                                 data[i + 1] =
3346                                     dev_spec->shadow_ram[offset + i + 1].value;
3347                         else
3348                                 data[i + 1] = (u16)(dword >> 16 & 0xFFFF);
3349                 }
3350         }
3351
3352         nvm->ops.release(hw);
3353
3354 out:
3355         if (ret_val)
3356                 e_dbg("NVM read error: %d\n", ret_val);
3357
3358         return ret_val;
3359 }
3360
3361 /**
3362  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
3363  *  @hw: pointer to the HW structure
3364  *  @offset: The offset (in bytes) of the word(s) to read.
3365  *  @words: Size of data to read in words
3366  *  @data: Pointer to the word(s) to read at offset.
3367  *
3368  *  Reads a word(s) from the NVM using the flash access registers.
3369  **/
3370 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3371                                   u16 *data)
3372 {
3373         struct e1000_nvm_info *nvm = &hw->nvm;
3374         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3375         u32 act_offset;
3376         s32 ret_val = 0;
3377         u32 bank = 0;
3378         u16 i, word;
3379
3380         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3381             (words == 0)) {
3382                 e_dbg("nvm parameter(s) out of bounds\n");
3383                 ret_val = -E1000_ERR_NVM;
3384                 goto out;
3385         }
3386
3387         nvm->ops.acquire(hw);
3388
3389         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3390         if (ret_val) {
3391                 e_dbg("Could not detect valid bank, assuming bank 0\n");
3392                 bank = 0;
3393         }
3394
3395         act_offset = (bank) ? nvm->flash_bank_size : 0;
3396         act_offset += offset;
3397
3398         ret_val = 0;
3399         for (i = 0; i < words; i++) {
3400                 if (dev_spec->shadow_ram[offset + i].modified) {
3401                         data[i] = dev_spec->shadow_ram[offset + i].value;
3402                 } else {
3403                         ret_val = e1000_read_flash_word_ich8lan(hw,
3404                                                                 act_offset + i,
3405                                                                 &word);
3406                         if (ret_val)
3407                                 break;
3408                         data[i] = word;
3409                 }
3410         }
3411
3412         nvm->ops.release(hw);
3413
3414 out:
3415         if (ret_val)
3416                 e_dbg("NVM read error: %d\n", ret_val);
3417
3418         return ret_val;
3419 }
3420
3421 /**
3422  *  e1000_flash_cycle_init_ich8lan - Initialize flash
3423  *  @hw: pointer to the HW structure
3424  *
3425  *  This function does initial flash setup so that a new read/write/erase cycle
3426  *  can be started.
3427  **/
3428 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3429 {
3430         union ich8_hws_flash_status hsfsts;
3431         s32 ret_val = -E1000_ERR_NVM;
3432
3433         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3434
3435         /* Check if the flash descriptor is valid */
3436         if (!hsfsts.hsf_status.fldesvalid) {
3437                 e_dbg("Flash descriptor invalid.  SW Sequencing must be used.\n");
3438                 return -E1000_ERR_NVM;
3439         }
3440
3441         /* Clear FCERR and DAEL in hw status by writing 1 */
3442         hsfsts.hsf_status.flcerr = 1;
3443         hsfsts.hsf_status.dael = 1;
3444         if (hw->mac.type >= e1000_pch_spt)
3445                 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF);
3446         else
3447                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3448
3449         /* Either we should have a hardware SPI cycle in progress
3450          * bit to check against, in order to start a new cycle or
3451          * FDONE bit should be changed in the hardware so that it
3452          * is 1 after hardware reset, which can then be used as an
3453          * indication whether a cycle is in progress or has been
3454          * completed.
3455          */
3456
3457         if (!hsfsts.hsf_status.flcinprog) {
3458                 /* There is no cycle running at present,
3459                  * so we can start a cycle.
3460                  * Begin by setting Flash Cycle Done.
3461                  */
3462                 hsfsts.hsf_status.flcdone = 1;
3463                 if (hw->mac.type >= e1000_pch_spt)
3464                         ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF);
3465                 else
3466                         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3467                 ret_val = 0;
3468         } else {
3469                 s32 i;
3470
3471                 /* Otherwise poll for sometime so the current
3472                  * cycle has a chance to end before giving up.
3473                  */
3474                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
3475                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3476                         if (!hsfsts.hsf_status.flcinprog) {
3477                                 ret_val = 0;
3478                                 break;
3479                         }
3480                         udelay(1);
3481                 }
3482                 if (!ret_val) {
3483                         /* Successful in waiting for previous cycle to timeout,
3484                          * now set the Flash Cycle Done.
3485                          */
3486                         hsfsts.hsf_status.flcdone = 1;
3487                         if (hw->mac.type >= e1000_pch_spt)
3488                                 ew32flash(ICH_FLASH_HSFSTS,
3489                                           hsfsts.regval & 0xFFFF);
3490                         else
3491                                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3492                 } else {
3493                         e_dbg("Flash controller busy, cannot get access\n");
3494                 }
3495         }
3496
3497         return ret_val;
3498 }
3499
3500 /**
3501  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3502  *  @hw: pointer to the HW structure
3503  *  @timeout: maximum time to wait for completion
3504  *
3505  *  This function starts a flash cycle and waits for its completion.
3506  **/
3507 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3508 {
3509         union ich8_hws_flash_ctrl hsflctl;
3510         union ich8_hws_flash_status hsfsts;
3511         u32 i = 0;
3512
3513         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3514         if (hw->mac.type >= e1000_pch_spt)
3515                 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
3516         else
3517                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3518         hsflctl.hsf_ctrl.flcgo = 1;
3519
3520         if (hw->mac.type >= e1000_pch_spt)
3521                 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
3522         else
3523                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3524
3525         /* wait till FDONE bit is set to 1 */
3526         do {
3527                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3528                 if (hsfsts.hsf_status.flcdone)
3529                         break;
3530                 udelay(1);
3531         } while (i++ < timeout);
3532
3533         if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
3534                 return 0;
3535
3536         return -E1000_ERR_NVM;
3537 }
3538
3539 /**
3540  *  e1000_read_flash_dword_ich8lan - Read dword from flash
3541  *  @hw: pointer to the HW structure
3542  *  @offset: offset to data location
3543  *  @data: pointer to the location for storing the data
3544  *
3545  *  Reads the flash dword at offset into data.  Offset is converted
3546  *  to bytes before read.
3547  **/
3548 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset,
3549                                           u32 *data)
3550 {
3551         /* Must convert word offset into bytes. */
3552         offset <<= 1;
3553         return e1000_read_flash_data32_ich8lan(hw, offset, data);
3554 }
3555
3556 /**
3557  *  e1000_read_flash_word_ich8lan - Read word from flash
3558  *  @hw: pointer to the HW structure
3559  *  @offset: offset to data location
3560  *  @data: pointer to the location for storing the data
3561  *
3562  *  Reads the flash word at offset into data.  Offset is converted
3563  *  to bytes before read.
3564  **/
3565 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
3566                                          u16 *data)
3567 {
3568         /* Must convert offset into bytes. */
3569         offset <<= 1;
3570
3571         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
3572 }
3573
3574 /**
3575  *  e1000_read_flash_byte_ich8lan - Read byte from flash
3576  *  @hw: pointer to the HW structure
3577  *  @offset: The offset of the byte to read.
3578  *  @data: Pointer to a byte to store the value read.
3579  *
3580  *  Reads a single byte from the NVM using the flash access registers.
3581  **/
3582 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3583                                          u8 *data)
3584 {
3585         s32 ret_val;
3586         u16 word = 0;
3587
3588         /* In SPT, only 32 bits access is supported,
3589          * so this function should not be called.
3590          */
3591         if (hw->mac.type >= e1000_pch_spt)
3592                 return -E1000_ERR_NVM;
3593         else
3594                 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3595
3596         if (ret_val)
3597                 return ret_val;
3598
3599         *data = (u8)word;
3600
3601         return 0;
3602 }
3603
3604 /**
3605  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
3606  *  @hw: pointer to the HW structure
3607  *  @offset: The offset (in bytes) of the byte or word to read.
3608  *  @size: Size of data to read, 1=byte 2=word
3609  *  @data: Pointer to the word to store the value read.
3610  *
3611  *  Reads a byte or word from the NVM using the flash access registers.
3612  **/
3613 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3614                                          u8 size, u16 *data)
3615 {
3616         union ich8_hws_flash_status hsfsts;
3617         union ich8_hws_flash_ctrl hsflctl;
3618         u32 flash_linear_addr;
3619         u32 flash_data = 0;
3620         s32 ret_val = -E1000_ERR_NVM;
3621         u8 count = 0;
3622
3623         if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3624                 return -E1000_ERR_NVM;
3625
3626         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3627                              hw->nvm.flash_base_addr);
3628
3629         do {
3630                 udelay(1);
3631                 /* Steps */
3632                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3633                 if (ret_val)
3634                         break;
3635
3636                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3637                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3638                 hsflctl.hsf_ctrl.fldbcount = size - 1;
3639                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3640                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3641
3642                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3643
3644                 ret_val =
3645                     e1000_flash_cycle_ich8lan(hw,
3646                                               ICH_FLASH_READ_COMMAND_TIMEOUT);
3647
3648                 /* Check if FCERR is set to 1, if set to 1, clear it
3649                  * and try the whole sequence a few more times, else
3650                  * read in (shift in) the Flash Data0, the order is
3651                  * least significant byte first msb to lsb
3652                  */
3653                 if (!ret_val) {
3654                         flash_data = er32flash(ICH_FLASH_FDATA0);
3655                         if (size == 1)
3656                                 *data = (u8)(flash_data & 0x000000FF);
3657                         else if (size == 2)
3658                                 *data = (u16)(flash_data & 0x0000FFFF);
3659                         break;
3660                 } else {
3661                         /* If we've gotten here, then things are probably
3662                          * completely hosed, but if the error condition is
3663                          * detected, it won't hurt to give it another try...
3664                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3665                          */
3666                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3667                         if (hsfsts.hsf_status.flcerr) {
3668                                 /* Repeat for some time before giving up. */
3669                                 continue;
3670                         } else if (!hsfsts.hsf_status.flcdone) {
3671                                 e_dbg("Timeout error - flash cycle did not complete.\n");
3672                                 break;
3673                         }
3674                 }
3675         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3676
3677         return ret_val;
3678 }
3679
3680 /**
3681  *  e1000_read_flash_data32_ich8lan - Read dword from NVM
3682  *  @hw: pointer to the HW structure
3683  *  @offset: The offset (in bytes) of the dword to read.
3684  *  @data: Pointer to the dword to store the value read.
3685  *
3686  *  Reads a byte or word from the NVM using the flash access registers.
3687  **/
3688
3689 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
3690                                            u32 *data)
3691 {
3692         union ich8_hws_flash_status hsfsts;
3693         union ich8_hws_flash_ctrl hsflctl;
3694         u32 flash_linear_addr;
3695         s32 ret_val = -E1000_ERR_NVM;
3696         u8 count = 0;
3697
3698         if (offset > ICH_FLASH_LINEAR_ADDR_MASK || hw->mac.type < e1000_pch_spt)
3699                 return -E1000_ERR_NVM;
3700         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3701                              hw->nvm.flash_base_addr);
3702
3703         do {
3704                 udelay(1);
3705                 /* Steps */
3706                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3707                 if (ret_val)
3708                         break;
3709                 /* In SPT, This register is in Lan memory space, not flash.
3710                  * Therefore, only 32 bit access is supported
3711                  */
3712                 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
3713
3714                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3715                 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
3716                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3717                 /* In SPT, This register is in Lan memory space, not flash.
3718                  * Therefore, only 32 bit access is supported
3719                  */
3720                 ew32flash(ICH_FLASH_HSFSTS, (u32)hsflctl.regval << 16);
3721                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3722
3723                 ret_val =
3724                    e1000_flash_cycle_ich8lan(hw,
3725                                              ICH_FLASH_READ_COMMAND_TIMEOUT);
3726
3727                 /* Check if FCERR is set to 1, if set to 1, clear it
3728                  * and try the whole sequence a few more times, else
3729                  * read in (shift in) the Flash Data0, the order is
3730                  * least significant byte first msb to lsb
3731                  */
3732                 if (!ret_val) {
3733                         *data = er32flash(ICH_FLASH_FDATA0);
3734                         break;
3735                 } else {
3736                         /* If we've gotten here, then things are probably
3737                          * completely hosed, but if the error condition is
3738                          * detected, it won't hurt to give it another try...
3739                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3740                          */
3741                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3742                         if (hsfsts.hsf_status.flcerr) {
3743                                 /* Repeat for some time before giving up. */
3744                                 continue;
3745                         } else if (!hsfsts.hsf_status.flcdone) {
3746                                 e_dbg("Timeout error - flash cycle did not complete.\n");
3747                                 break;
3748                         }
3749                 }
3750         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3751
3752         return ret_val;
3753 }
3754
3755 /**
3756  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
3757  *  @hw: pointer to the HW structure
3758  *  @offset: The offset (in bytes) of the word(s) to write.
3759  *  @words: Size of data to write in words
3760  *  @data: Pointer to the word(s) to write at offset.
3761  *
3762  *  Writes a byte or word to the NVM using the flash access registers.
3763  **/
3764 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3765                                    u16 *data)
3766 {
3767         struct e1000_nvm_info *nvm = &hw->nvm;
3768         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3769         u16 i;
3770
3771         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3772             (words == 0)) {
3773                 e_dbg("nvm parameter(s) out of bounds\n");
3774                 return -E1000_ERR_NVM;
3775         }
3776
3777         nvm->ops.acquire(hw);
3778
3779         for (i = 0; i < words; i++) {
3780                 dev_spec->shadow_ram[offset + i].modified = true;
3781                 dev_spec->shadow_ram[offset + i].value = data[i];
3782         }
3783
3784         nvm->ops.release(hw);
3785
3786         return 0;
3787 }
3788
3789 /**
3790  *  e1000_update_nvm_checksum_spt - Update the checksum for NVM
3791  *  @hw: pointer to the HW structure
3792  *
3793  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
3794  *  which writes the checksum to the shadow ram.  The changes in the shadow
3795  *  ram are then committed to the EEPROM by processing each bank at a time
3796  *  checking for the modified bit and writing only the pending changes.
3797  *  After a successful commit, the shadow ram is cleared and is ready for
3798  *  future writes.
3799  **/
3800 static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw)
3801 {
3802         struct e1000_nvm_info *nvm = &hw->nvm;
3803         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3804         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3805         s32 ret_val;
3806         u32 dword = 0;
3807
3808         ret_val = e1000e_update_nvm_checksum_generic(hw);
3809         if (ret_val)
3810                 goto out;
3811
3812         if (nvm->type != e1000_nvm_flash_sw)
3813                 goto out;
3814
3815         nvm->ops.acquire(hw);
3816
3817         /* We're writing to the opposite bank so if we're on bank 1,
3818          * write to bank 0 etc.  We also need to erase the segment that
3819          * is going to be written
3820          */
3821         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3822         if (ret_val) {
3823                 e_dbg("Could not detect valid bank, assuming bank 0\n");
3824                 bank = 0;
3825         }
3826
3827         if (bank == 0) {
3828                 new_bank_offset = nvm->flash_bank_size;
3829                 old_bank_offset = 0;
3830                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3831                 if (ret_val)
3832                         goto release;
3833         } else {
3834                 old_bank_offset = nvm->flash_bank_size;
3835                 new_bank_offset = 0;
3836                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3837                 if (ret_val)
3838                         goto release;
3839         }
3840         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i += 2) {
3841                 /* Determine whether to write the value stored
3842                  * in the other NVM bank or a modified value stored
3843                  * in the shadow RAM
3844                  */
3845                 ret_val = e1000_read_flash_dword_ich8lan(hw,
3846                                                          i + old_bank_offset,
3847                                                          &dword);
3848
3849                 if (dev_spec->shadow_ram[i].modified) {
3850                         dword &= 0xffff0000;
3851                         dword |= (dev_spec->shadow_ram[i].value & 0xffff);
3852                 }
3853                 if (dev_spec->shadow_ram[i + 1].modified) {
3854                         dword &= 0x0000ffff;
3855                         dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff)
3856                                   << 16);
3857                 }
3858                 if (ret_val)
3859                         break;
3860
3861                 /* If the word is 0x13, then make sure the signature bits
3862                  * (15:14) are 11b until the commit has completed.
3863                  * This will allow us to write 10b which indicates the
3864                  * signature is valid.  We want to do this after the write
3865                  * has completed so that we don't mark the segment valid
3866                  * while the write is still in progress
3867                  */
3868                 if (i == E1000_ICH_NVM_SIG_WORD - 1)
3869                         dword |= E1000_ICH_NVM_SIG_MASK << 16;
3870
3871                 /* Convert offset to bytes. */
3872                 act_offset = (i + new_bank_offset) << 1;
3873
3874                 usleep_range(100, 200);
3875
3876                 /* Write the data to the new bank. Offset in words */
3877                 act_offset = i + new_bank_offset;
3878                 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset,
3879                                                                 dword);
3880                 if (ret_val)
3881                         break;
3882         }
3883
3884         /* Don't bother writing the segment valid bits if sector
3885          * programming failed.
3886          */
3887         if (ret_val) {
3888                 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
3889                 e_dbg("Flash commit failed.\n");
3890                 goto release;
3891         }
3892
3893         /* Finally validate the new segment by setting bit 15:14
3894          * to 10b in word 0x13 , this can be done without an
3895          * erase as well since these bits are 11 to start with
3896          * and we need to change bit 14 to 0b
3897          */
3898         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
3899
3900         /*offset in words but we read dword */
3901         --act_offset;
3902         ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
3903
3904         if (ret_val)
3905                 goto release;
3906
3907         dword &= 0xBFFFFFFF;
3908         ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
3909
3910         if (ret_val)
3911                 goto release;
3912
3913         /* offset in words but we read dword */
3914         act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1;
3915         ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
3916
3917         if (ret_val)
3918                 goto release;
3919
3920         dword &= 0x00FFFFFF;
3921         ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
3922
3923         if (ret_val)
3924                 goto release;
3925
3926         /* Great!  Everything worked, we can now clear the cached entries. */
3927         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
3928                 dev_spec->shadow_ram[i].modified = false;
3929                 dev_spec->shadow_ram[i].value = 0xFFFF;
3930         }
3931
3932 release:
3933         nvm->ops.release(hw);
3934
3935         /* Reload the EEPROM, or else modifications will not appear
3936          * until after the next adapter reset.
3937          */
3938         if (!ret_val) {
3939                 nvm->ops.reload(hw);
3940                 usleep_range(10000, 11000);
3941         }
3942
3943 out:
3944         if (ret_val)
3945                 e_dbg("NVM update error: %d\n", ret_val);
3946
3947         return ret_val;
3948 }
3949
3950 /**
3951  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
3952  *  @hw: pointer to the HW structure
3953  *
3954  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
3955  *  which writes the checksum to the shadow ram.  The changes in the shadow
3956  *  ram are then committed to the EEPROM by processing each bank at a time
3957  *  checking for the modified bit and writing only the pending changes.
3958  *  After a successful commit, the shadow ram is cleared and is ready for
3959  *  future writes.
3960  **/
3961 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
3962 {
3963         struct e1000_nvm_info *nvm = &hw->nvm;
3964         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3965         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3966         s32 ret_val;
3967         u16 data = 0;
3968
3969         ret_val = e1000e_update_nvm_checksum_generic(hw);
3970         if (ret_val)
3971                 goto out;
3972
3973         if (nvm->type != e1000_nvm_flash_sw)
3974                 goto out;
3975
3976         nvm->ops.acquire(hw);
3977
3978         /* We're writing to the opposite bank so if we're on bank 1,
3979          * write to bank 0 etc.  We also need to erase the segment that
3980          * is going to be written
3981          */
3982         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3983         if (ret_val) {
3984                 e_dbg("Could not detect valid bank, assuming bank 0\n");
3985                 bank = 0;
3986         }
3987
3988         if (bank == 0) {
3989                 new_bank_offset = nvm->flash_bank_size;
3990                 old_bank_offset = 0;
3991                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3992                 if (ret_val)
3993                         goto release;
3994         } else {
3995                 old_bank_offset = nvm->flash_bank_size;
3996                 new_bank_offset = 0;
3997                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3998                 if (ret_val)
3999                         goto release;
4000         }
4001         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
4002                 if (dev_spec->shadow_ram[i].modified) {
4003                         data = dev_spec->shadow_ram[i].value;
4004                 } else {
4005                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
4006                                                                 old_bank_offset,
4007                                                                 &data);
4008                         if (ret_val)
4009                                 break;
4010                 }
4011
4012                 /* If the word is 0x13, then make sure the signature bits
4013                  * (15:14) are 11b until the commit has completed.
4014                  * This will allow us to write 10b which indicates the
4015                  * signature is valid.  We want to do this after the write
4016                  * has completed so that we don't mark the segment valid
4017                  * while the write is still in progress
4018                  */
4019                 if (i == E1000_ICH_NVM_SIG_WORD)
4020                         data |= E1000_ICH_NVM_SIG_MASK;
4021
4022                 /* Convert offset to bytes. */
4023                 act_offset = (i + new_bank_offset) << 1;
4024
4025                 usleep_range(100, 200);
4026                 /* Write the bytes to the new bank. */
4027                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4028                                                                act_offset,
4029                                                                (u8)data);
4030                 if (ret_val)
4031                         break;
4032
4033                 usleep_range(100, 200);
4034                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4035                                                                act_offset + 1,
4036                                                                (u8)(data >> 8));
4037                 if (ret_val)
4038                         break;
4039         }
4040
4041         /* Don't bother writing the segment valid bits if sector
4042          * programming failed.
4043          */
4044         if (ret_val) {
4045                 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
4046                 e_dbg("Flash commit failed.\n");
4047                 goto release;
4048         }
4049
4050         /* Finally validate the new segment by setting bit 15:14
4051          * to 10b in word 0x13 , this can be done without an
4052          * erase as well since these bits are 11 to start with
4053          * and we need to change bit 14 to 0b
4054          */
4055         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
4056         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
4057         if (ret_val)
4058                 goto release;
4059
4060         data &= 0xBFFF;
4061         ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4062                                                        act_offset * 2 + 1,
4063                                                        (u8)(data >> 8));
4064         if (ret_val)
4065                 goto release;
4066
4067         /* And invalidate the previously valid segment by setting
4068          * its signature word (0x13) high_byte to 0b. This can be
4069          * done without an erase because flash erase sets all bits
4070          * to 1's. We can write 1's to 0's without an erase
4071          */
4072         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
4073         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
4074         if (ret_val)
4075                 goto release;
4076
4077         /* Great!  Everything worked, we can now clear the cached entries. */
4078         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
4079                 dev_spec->shadow_ram[i].modified = false;
4080                 dev_spec->shadow_ram[i].value = 0xFFFF;
4081         }
4082
4083 release:
4084         nvm->ops.release(hw);
4085
4086         /* Reload the EEPROM, or else modifications will not appear
4087          * until after the next adapter reset.
4088          */
4089         if (!ret_val) {
4090                 nvm->ops.reload(hw);
4091                 usleep_range(10000, 11000);
4092         }
4093
4094 out:
4095         if (ret_val)
4096                 e_dbg("NVM update error: %d\n", ret_val);
4097
4098         return ret_val;
4099 }
4100
4101 /**
4102  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
4103  *  @hw: pointer to the HW structure
4104  *
4105  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
4106  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
4107  *  calculated, in which case we need to calculate the checksum and set bit 6.
4108  **/
4109 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
4110 {
4111         s32 ret_val;
4112         u16 data;
4113         u16 word;
4114         u16 valid_csum_mask;
4115
4116         /* Read NVM and check Invalid Image CSUM bit.  If this bit is 0,
4117          * the checksum needs to be fixed.  This bit is an indication that
4118          * the NVM was prepared by OEM software and did not calculate
4119          * the checksum...a likely scenario.
4120          */
4121         switch (hw->mac.type) {
4122         case e1000_pch_lpt:
4123         case e1000_pch_spt:
4124         case e1000_pch_cnp:
4125         case e1000_pch_tgp:
4126         case e1000_pch_adp:
4127         case e1000_pch_mtp:
4128         case e1000_pch_lnp:
4129                 word = NVM_COMPAT;
4130                 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
4131                 break;
4132         default:
4133                 word = NVM_FUTURE_INIT_WORD1;
4134                 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
4135                 break;
4136         }
4137
4138         ret_val = e1000_read_nvm(hw, word, 1, &data);
4139         if (ret_val)
4140                 return ret_val;
4141
4142         if (!(data & valid_csum_mask)) {
4143                 e_dbg("NVM Checksum valid bit not set\n");
4144
4145                 if (hw->mac.type < e1000_pch_tgp) {
4146                         data |= valid_csum_mask;
4147                         ret_val = e1000_write_nvm(hw, word, 1, &data);
4148                         if (ret_val)
4149                                 return ret_val;
4150                         ret_val = e1000e_update_nvm_checksum(hw);
4151                         if (ret_val)
4152                                 return ret_val;
4153                 }
4154         }
4155
4156         return e1000e_validate_nvm_checksum_generic(hw);
4157 }
4158
4159 /**
4160  *  e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
4161  *  @hw: pointer to the HW structure
4162  *
4163  *  To prevent malicious write/erase of the NVM, set it to be read-only
4164  *  so that the hardware ignores all write/erase cycles of the NVM via
4165  *  the flash control registers.  The shadow-ram copy of the NVM will
4166  *  still be updated, however any updates to this copy will not stick
4167  *  across driver reloads.
4168  **/
4169 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
4170 {
4171         struct e1000_nvm_info *nvm = &hw->nvm;
4172         union ich8_flash_protected_range pr0;
4173         union ich8_hws_flash_status hsfsts;
4174         u32 gfpreg;
4175
4176         nvm->ops.acquire(hw);
4177
4178         gfpreg = er32flash(ICH_FLASH_GFPREG);
4179
4180         /* Write-protect GbE Sector of NVM */
4181         pr0.regval = er32flash(ICH_FLASH_PR0);
4182         pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
4183         pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
4184         pr0.range.wpe = true;
4185         ew32flash(ICH_FLASH_PR0, pr0.regval);
4186
4187         /* Lock down a subset of GbE Flash Control Registers, e.g.
4188          * PR0 to prevent the write-protection from being lifted.
4189          * Once FLOCKDN is set, the registers protected by it cannot
4190          * be written until FLOCKDN is cleared by a hardware reset.
4191          */
4192         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4193         hsfsts.hsf_status.flockdn = true;
4194         ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
4195
4196         nvm->ops.release(hw);
4197 }
4198
4199 /**
4200  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
4201  *  @hw: pointer to the HW structure
4202  *  @offset: The offset (in bytes) of the byte/word to read.
4203  *  @size: Size of data to read, 1=byte 2=word
4204  *  @data: The byte(s) to write to the NVM.
4205  *
4206  *  Writes one/two bytes to the NVM using the flash access registers.
4207  **/
4208 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
4209                                           u8 size, u16 data)
4210 {
4211         union ich8_hws_flash_status hsfsts;
4212         union ich8_hws_flash_ctrl hsflctl;
4213         u32 flash_linear_addr;
4214         u32 flash_data = 0;
4215         s32 ret_val;
4216         u8 count = 0;
4217
4218         if (hw->mac.type >= e1000_pch_spt) {
4219                 if (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4220                         return -E1000_ERR_NVM;
4221         } else {
4222                 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4223                         return -E1000_ERR_NVM;
4224         }
4225
4226         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4227                              hw->nvm.flash_base_addr);
4228
4229         do {
4230                 udelay(1);
4231                 /* Steps */
4232                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4233                 if (ret_val)
4234                         break;
4235                 /* In SPT, This register is in Lan memory space, not
4236                  * flash.  Therefore, only 32 bit access is supported
4237                  */
4238                 if (hw->mac.type >= e1000_pch_spt)
4239                         hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
4240                 else
4241                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4242
4243                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
4244                 hsflctl.hsf_ctrl.fldbcount = size - 1;
4245                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4246                 /* In SPT, This register is in Lan memory space,
4247                  * not flash.  Therefore, only 32 bit access is
4248                  * supported
4249                  */
4250                 if (hw->mac.type >= e1000_pch_spt)
4251                         ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
4252                 else
4253                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4254
4255                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4256
4257                 if (size == 1)
4258                         flash_data = (u32)data & 0x00FF;
4259                 else
4260                         flash_data = (u32)data;
4261
4262                 ew32flash(ICH_FLASH_FDATA0, flash_data);
4263
4264                 /* check if FCERR is set to 1 , if set to 1, clear it
4265                  * and try the whole sequence a few more times else done
4266                  */
4267                 ret_val =
4268                     e1000_flash_cycle_ich8lan(hw,
4269                                               ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4270                 if (!ret_val)
4271                         break;
4272
4273                 /* If we're here, then things are most likely
4274                  * completely hosed, but if the error condition
4275                  * is detected, it won't hurt to give it another
4276                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4277                  */
4278                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4279                 if (hsfsts.hsf_status.flcerr)
4280                         /* Repeat for some time before giving up. */
4281                         continue;
4282                 if (!hsfsts.hsf_status.flcdone) {
4283                         e_dbg("Timeout error - flash cycle did not complete.\n");
4284                         break;
4285                 }
4286         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4287
4288         return ret_val;
4289 }
4290
4291 /**
4292 *  e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM
4293 *  @hw: pointer to the HW structure
4294 *  @offset: The offset (in bytes) of the dwords to read.
4295 *  @data: The 4 bytes to write to the NVM.
4296 *
4297 *  Writes one/two/four bytes to the NVM using the flash access registers.
4298 **/
4299 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
4300                                             u32 data)
4301 {
4302         union ich8_hws_flash_status hsfsts;
4303         union ich8_hws_flash_ctrl hsflctl;
4304         u32 flash_linear_addr;
4305         s32 ret_val;
4306         u8 count = 0;
4307
4308         if (hw->mac.type >= e1000_pch_spt) {
4309                 if (offset > ICH_FLASH_LINEAR_ADDR_MASK)
4310                         return -E1000_ERR_NVM;
4311         }
4312         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4313                              hw->nvm.flash_base_addr);
4314         do {
4315                 udelay(1);
4316                 /* Steps */
4317                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4318                 if (ret_val)
4319                         break;
4320
4321                 /* In SPT, This register is in Lan memory space, not
4322                  * flash.  Therefore, only 32 bit access is supported
4323                  */
4324                 if (hw->mac.type >= e1000_pch_spt)
4325                         hsflctl.regval = er32flash(ICH_FLASH_HSFSTS)
4326                             >> 16;
4327                 else
4328                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4329
4330                 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
4331                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4332
4333                 /* In SPT, This register is in Lan memory space,
4334                  * not flash.  Therefore, only 32 bit access is
4335                  * supported
4336                  */
4337                 if (hw->mac.type >= e1000_pch_spt)
4338                         ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
4339                 else
4340                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4341
4342                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4343
4344                 ew32flash(ICH_FLASH_FDATA0, data);
4345
4346                 /* check if FCERR is set to 1 , if set to 1, clear it
4347                  * and try the whole sequence a few more times else done
4348                  */
4349                 ret_val =
4350                    e1000_flash_cycle_ich8lan(hw,
4351                                              ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4352
4353                 if (!ret_val)
4354                         break;
4355
4356                 /* If we're here, then things are most likely
4357                  * completely hosed, but if the error condition
4358                  * is detected, it won't hurt to give it another
4359                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4360                  */
4361                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4362
4363                 if (hsfsts.hsf_status.flcerr)
4364                         /* Repeat for some time before giving up. */
4365                         continue;
4366                 if (!hsfsts.hsf_status.flcdone) {
4367                         e_dbg("Timeout error - flash cycle did not complete.\n");
4368                         break;
4369                 }
4370         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4371
4372         return ret_val;
4373 }
4374
4375 /**
4376  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
4377  *  @hw: pointer to the HW structure
4378  *  @offset: The index of the byte to read.
4379  *  @data: The byte to write to the NVM.
4380  *
4381  *  Writes a single byte to the NVM using the flash access registers.
4382  **/
4383 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
4384                                           u8 data)
4385 {
4386         u16 word = (u16)data;
4387
4388         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
4389 }
4390
4391 /**
4392 *  e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM
4393 *  @hw: pointer to the HW structure
4394 *  @offset: The offset of the word to write.
4395 *  @dword: The dword to write to the NVM.
4396 *
4397 *  Writes a single dword to the NVM using the flash access registers.
4398 *  Goes through a retry algorithm before giving up.
4399 **/
4400 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
4401                                                  u32 offset, u32 dword)
4402 {
4403         s32 ret_val;
4404         u16 program_retries;
4405
4406         /* Must convert word offset into bytes. */
4407         offset <<= 1;
4408         ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4409
4410         if (!ret_val)
4411                 return ret_val;
4412         for (program_retries = 0; program_retries < 100; program_retries++) {
4413                 e_dbg("Retrying Byte %8.8X at offset %u\n", dword, offset);
4414                 usleep_range(100, 200);
4415                 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4416                 if (!ret_val)
4417                         break;
4418         }
4419         if (program_retries == 100)
4420                 return -E1000_ERR_NVM;
4421
4422         return 0;
4423 }
4424
4425 /**
4426  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
4427  *  @hw: pointer to the HW structure
4428  *  @offset: The offset of the byte to write.
4429  *  @byte: The byte to write to the NVM.
4430  *
4431  *  Writes a single byte to the NVM using the flash access registers.
4432  *  Goes through a retry algorithm before giving up.
4433  **/
4434 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
4435                                                 u32 offset, u8 byte)
4436 {
4437         s32 ret_val;
4438         u16 program_retries;
4439
4440         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4441         if (!ret_val)
4442                 return ret_val;
4443
4444         for (program_retries = 0; program_retries < 100; program_retries++) {
4445                 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
4446                 usleep_range(100, 200);
4447                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4448                 if (!ret_val)
4449                         break;
4450         }
4451         if (program_retries == 100)
4452                 return -E1000_ERR_NVM;
4453
4454         return 0;
4455 }
4456
4457 /**
4458  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
4459  *  @hw: pointer to the HW structure
4460  *  @bank: 0 for first bank, 1 for second bank, etc.
4461  *
4462  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
4463  *  bank N is 4096 * N + flash_reg_addr.
4464  **/
4465 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
4466 {
4467         struct e1000_nvm_info *nvm = &hw->nvm;
4468         union ich8_hws_flash_status hsfsts;
4469         union ich8_hws_flash_ctrl hsflctl;
4470         u32 flash_linear_addr;
4471         /* bank size is in 16bit words - adjust to bytes */
4472         u32 flash_bank_size = nvm->flash_bank_size * 2;
4473         s32 ret_val;
4474         s32 count = 0;
4475         s32 j, iteration, sector_size;
4476
4477         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4478
4479         /* Determine HW Sector size: Read BERASE bits of hw flash status
4480          * register
4481          * 00: The Hw sector is 256 bytes, hence we need to erase 16
4482          *     consecutive sectors.  The start index for the nth Hw sector
4483          *     can be calculated as = bank * 4096 + n * 256
4484          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
4485          *     The start index for the nth Hw sector can be calculated
4486          *     as = bank * 4096
4487          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
4488          *     (ich9 only, otherwise error condition)
4489          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
4490          */
4491         switch (hsfsts.hsf_status.berasesz) {
4492         case 0:
4493                 /* Hw sector size 256 */
4494                 sector_size = ICH_FLASH_SEG_SIZE_256;
4495                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
4496                 break;
4497         case 1:
4498                 sector_size = ICH_FLASH_SEG_SIZE_4K;
4499                 iteration = 1;
4500                 break;
4501         case 2:
4502                 sector_size = ICH_FLASH_SEG_SIZE_8K;
4503                 iteration = 1;
4504                 break;
4505         case 3:
4506                 sector_size = ICH_FLASH_SEG_SIZE_64K;
4507                 iteration = 1;
4508                 break;
4509         default:
4510                 return -E1000_ERR_NVM;
4511         }
4512
4513         /* Start with the base address, then add the sector offset. */
4514         flash_linear_addr = hw->nvm.flash_base_addr;
4515         flash_linear_addr += (bank) ? flash_bank_size : 0;
4516
4517         for (j = 0; j < iteration; j++) {
4518                 do {
4519                         u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
4520
4521                         /* Steps */
4522                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
4523                         if (ret_val)
4524                                 return ret_val;
4525
4526                         /* Write a value 11 (block Erase) in Flash
4527                          * Cycle field in hw flash control
4528                          */
4529                         if (hw->mac.type >= e1000_pch_spt)
4530                                 hsflctl.regval =
4531                                     er32flash(ICH_FLASH_HSFSTS) >> 16;
4532                         else
4533                                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4534
4535                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
4536                         if (hw->mac.type >= e1000_pch_spt)
4537                                 ew32flash(ICH_FLASH_HSFSTS,
4538                                           hsflctl.regval << 16);
4539                         else
4540                                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4541
4542                         /* Write the last 24 bits of an index within the
4543                          * block into Flash Linear address field in Flash
4544                          * Address.
4545                          */
4546                         flash_linear_addr += (j * sector_size);
4547                         ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4548
4549                         ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
4550                         if (!ret_val)
4551                                 break;
4552
4553                         /* Check if FCERR is set to 1.  If 1,
4554                          * clear it and try the whole sequence
4555                          * a few more times else Done
4556                          */
4557                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4558                         if (hsfsts.hsf_status.flcerr)
4559                                 /* repeat for some time before giving up */
4560                                 continue;
4561                         else if (!hsfsts.hsf_status.flcdone)
4562                                 return ret_val;
4563                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
4564         }
4565
4566         return 0;
4567 }
4568
4569 /**
4570  *  e1000_valid_led_default_ich8lan - Set the default LED settings
4571  *  @hw: pointer to the HW structure
4572  *  @data: Pointer to the LED settings
4573  *
4574  *  Reads the LED default settings from the NVM to data.  If the NVM LED
4575  *  settings is all 0's or F's, set the LED default to a valid LED default
4576  *  setting.
4577  **/
4578 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
4579 {
4580         s32 ret_val;
4581
4582         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
4583         if (ret_val) {
4584                 e_dbg("NVM Read Error\n");
4585                 return ret_val;
4586         }
4587
4588         if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
4589                 *data = ID_LED_DEFAULT_ICH8LAN;
4590
4591         return 0;
4592 }
4593
4594 /**
4595  *  e1000_id_led_init_pchlan - store LED configurations
4596  *  @hw: pointer to the HW structure
4597  *
4598  *  PCH does not control LEDs via the LEDCTL register, rather it uses
4599  *  the PHY LED configuration register.
4600  *
4601  *  PCH also does not have an "always on" or "always off" mode which
4602  *  complicates the ID feature.  Instead of using the "on" mode to indicate
4603  *  in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()),
4604  *  use "link_up" mode.  The LEDs will still ID on request if there is no
4605  *  link based on logic in e1000_led_[on|off]_pchlan().
4606  **/
4607 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
4608 {
4609         struct e1000_mac_info *mac = &hw->mac;
4610         s32 ret_val;
4611         const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
4612         const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
4613         u16 data, i, temp, shift;
4614
4615         /* Get default ID LED modes */
4616         ret_val = hw->nvm.ops.valid_led_default(hw, &data);
4617         if (ret_val)
4618                 return ret_val;
4619
4620         mac->ledctl_default = er32(LEDCTL);
4621         mac->ledctl_mode1 = mac->ledctl_default;
4622         mac->ledctl_mode2 = mac->ledctl_default;
4623
4624         for (i = 0; i < 4; i++) {
4625                 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
4626                 shift = (i * 5);
4627                 switch (temp) {
4628                 case ID_LED_ON1_DEF2:
4629                 case ID_LED_ON1_ON2:
4630                 case ID_LED_ON1_OFF2:
4631                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4632                         mac->ledctl_mode1 |= (ledctl_on << shift);
4633                         break;
4634                 case ID_LED_OFF1_DEF2:
4635                 case ID_LED_OFF1_ON2:
4636                 case ID_LED_OFF1_OFF2:
4637                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4638                         mac->ledctl_mode1 |= (ledctl_off << shift);
4639                         break;
4640                 default:
4641                         /* Do nothing */
4642                         break;
4643                 }
4644                 switch (temp) {
4645                 case ID_LED_DEF1_ON2:
4646                 case ID_LED_ON1_ON2:
4647                 case ID_LED_OFF1_ON2:
4648                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4649                         mac->ledctl_mode2 |= (ledctl_on << shift);
4650                         break;
4651                 case ID_LED_DEF1_OFF2:
4652                 case ID_LED_ON1_OFF2:
4653                 case ID_LED_OFF1_OFF2:
4654                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4655                         mac->ledctl_mode2 |= (ledctl_off << shift);
4656                         break;
4657                 default:
4658                         /* Do nothing */
4659                         break;
4660                 }
4661         }
4662
4663         return 0;
4664 }
4665
4666 /**
4667  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
4668  *  @hw: pointer to the HW structure
4669  *
4670  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
4671  *  register, so the bus width is hard coded.
4672  **/
4673 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
4674 {
4675         struct e1000_bus_info *bus = &hw->bus;
4676         s32 ret_val;
4677
4678         ret_val = e1000e_get_bus_info_pcie(hw);
4679
4680         /* ICH devices are "PCI Express"-ish.  They have
4681          * a configuration space, but do not contain
4682          * PCI Express Capability registers, so bus width
4683          * must be hardcoded.
4684          */
4685         if (bus->width == e1000_bus_width_unknown)
4686                 bus->width = e1000_bus_width_pcie_x1;
4687
4688         return ret_val;
4689 }
4690
4691 /**
4692  *  e1000_reset_hw_ich8lan - Reset the hardware
4693  *  @hw: pointer to the HW structure
4694  *
4695  *  Does a full reset of the hardware which includes a reset of the PHY and
4696  *  MAC.
4697  **/
4698 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
4699 {
4700         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4701         u16 kum_cfg;
4702         u32 ctrl, reg;
4703         s32 ret_val;
4704
4705         /* Prevent the PCI-E bus from sticking if there is no TLP connection
4706          * on the last TLP read/write transaction when MAC is reset.
4707          */
4708         ret_val = e1000e_disable_pcie_master(hw);
4709         if (ret_val)
4710                 e_dbg("PCI-E Master disable polling has failed.\n");
4711
4712         e_dbg("Masking off all interrupts\n");
4713         ew32(IMC, 0xffffffff);
4714
4715         /* Disable the Transmit and Receive units.  Then delay to allow
4716          * any pending transactions to complete before we hit the MAC
4717          * with the global reset.
4718          */
4719         ew32(RCTL, 0);
4720         ew32(TCTL, E1000_TCTL_PSP);
4721         e1e_flush();
4722
4723         usleep_range(10000, 11000);
4724
4725         /* Workaround for ICH8 bit corruption issue in FIFO memory */
4726         if (hw->mac.type == e1000_ich8lan) {
4727                 /* Set Tx and Rx buffer allocation to 8k apiece. */
4728                 ew32(PBA, E1000_PBA_8K);
4729                 /* Set Packet Buffer Size to 16k. */
4730                 ew32(PBS, E1000_PBS_16K);
4731         }
4732
4733         if (hw->mac.type == e1000_pchlan) {
4734                 /* Save the NVM K1 bit setting */
4735                 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
4736                 if (ret_val)
4737                         return ret_val;
4738
4739                 if (kum_cfg & E1000_NVM_K1_ENABLE)
4740                         dev_spec->nvm_k1_enabled = true;
4741                 else
4742                         dev_spec->nvm_k1_enabled = false;
4743         }
4744
4745         ctrl = er32(CTRL);
4746
4747         if (!hw->phy.ops.check_reset_block(hw)) {
4748                 /* Full-chip reset requires MAC and PHY reset at the same
4749                  * time to make sure the interface between MAC and the
4750                  * external PHY is reset.
4751                  */
4752                 ctrl |= E1000_CTRL_PHY_RST;
4753
4754                 /* Gate automatic PHY configuration by hardware on
4755                  * non-managed 82579
4756                  */
4757                 if ((hw->mac.type == e1000_pch2lan) &&
4758                     !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
4759                         e1000_gate_hw_phy_config_ich8lan(hw, true);
4760         }
4761         ret_val = e1000_acquire_swflag_ich8lan(hw);
4762         e_dbg("Issuing a global reset to ich8lan\n");
4763         ew32(CTRL, (ctrl | E1000_CTRL_RST));
4764         /* cannot issue a flush here because it hangs the hardware */
4765         msleep(20);
4766
4767         /* Set Phy Config Counter to 50msec */
4768         if (hw->mac.type == e1000_pch2lan) {
4769                 reg = er32(FEXTNVM3);
4770                 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
4771                 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
4772                 ew32(FEXTNVM3, reg);
4773         }
4774
4775         if (!ret_val)
4776                 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
4777
4778         if (ctrl & E1000_CTRL_PHY_RST) {
4779                 ret_val = hw->phy.ops.get_cfg_done(hw);
4780                 if (ret_val)
4781                         return ret_val;
4782
4783                 ret_val = e1000_post_phy_reset_ich8lan(hw);
4784                 if (ret_val)
4785                         return ret_val;
4786         }
4787
4788         /* For PCH, this write will make sure that any noise
4789          * will be detected as a CRC error and be dropped rather than show up
4790          * as a bad packet to the DMA engine.
4791          */
4792         if (hw->mac.type == e1000_pchlan)
4793                 ew32(CRC_OFFSET, 0x65656565);
4794
4795         ew32(IMC, 0xffffffff);
4796         er32(ICR);
4797
4798         reg = er32(KABGTXD);
4799         reg |= E1000_KABGTXD_BGSQLBIAS;
4800         ew32(KABGTXD, reg);
4801
4802         return 0;
4803 }
4804
4805 /**
4806  *  e1000_init_hw_ich8lan - Initialize the hardware
4807  *  @hw: pointer to the HW structure
4808  *
4809  *  Prepares the hardware for transmit and receive by doing the following:
4810  *   - initialize hardware bits
4811  *   - initialize LED identification
4812  *   - setup receive address registers
4813  *   - setup flow control
4814  *   - setup transmit descriptors
4815  *   - clear statistics
4816  **/
4817 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
4818 {
4819         struct e1000_mac_info *mac = &hw->mac;
4820         u32 ctrl_ext, txdctl, snoop, fflt_dbg;
4821         s32 ret_val;
4822         u16 i;
4823
4824         e1000_initialize_hw_bits_ich8lan(hw);
4825
4826         /* Initialize identification LED */
4827         ret_val = mac->ops.id_led_init(hw);
4828         /* An error is not fatal and we should not stop init due to this */
4829         if (ret_val)
4830                 e_dbg("Error initializing identification LED\n");
4831
4832         /* Setup the receive address. */
4833         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
4834
4835         /* Zero out the Multicast HASH table */
4836         e_dbg("Zeroing the MTA\n");
4837         for (i = 0; i < mac->mta_reg_count; i++)
4838                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
4839
4840         /* The 82578 Rx buffer will stall if wakeup is enabled in host and
4841          * the ME.  Disable wakeup by clearing the host wakeup bit.
4842          * Reset the phy after disabling host wakeup to reset the Rx buffer.
4843          */
4844         if (hw->phy.type == e1000_phy_82578) {
4845                 e1e_rphy(hw, BM_PORT_GEN_CFG, &i);
4846                 i &= ~BM_WUC_HOST_WU_BIT;
4847                 e1e_wphy(hw, BM_PORT_GEN_CFG, i);
4848                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
4849                 if (ret_val)
4850                         return ret_val;
4851         }
4852
4853         /* Setup link and flow control */
4854         ret_val = mac->ops.setup_link(hw);
4855
4856         /* Set the transmit descriptor write-back policy for both queues */
4857         txdctl = er32(TXDCTL(0));
4858         txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4859                   E1000_TXDCTL_FULL_TX_DESC_WB);
4860         txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4861                   E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4862         ew32(TXDCTL(0), txdctl);
4863         txdctl = er32(TXDCTL(1));
4864         txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4865                   E1000_TXDCTL_FULL_TX_DESC_WB);
4866         txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4867                   E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4868         ew32(TXDCTL(1), txdctl);
4869
4870         /* ICH8 has opposite polarity of no_snoop bits.
4871          * By default, we should use snoop behavior.
4872          */
4873         if (mac->type == e1000_ich8lan)
4874                 snoop = PCIE_ICH8_SNOOP_ALL;
4875         else
4876                 snoop = (u32)~(PCIE_NO_SNOOP_ALL);
4877         e1000e_set_pcie_no_snoop(hw, snoop);
4878
4879         /* Enable workaround for packet loss issue on TGP PCH
4880          * Do not gate DMA clock from the modPHY block
4881          */
4882         if (mac->type >= e1000_pch_tgp) {
4883                 fflt_dbg = er32(FFLT_DBG);
4884                 fflt_dbg |= E1000_FFLT_DBG_DONT_GATE_WAKE_DMA_CLK;
4885                 ew32(FFLT_DBG, fflt_dbg);
4886         }
4887
4888         ctrl_ext = er32(CTRL_EXT);
4889         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
4890         ew32(CTRL_EXT, ctrl_ext);
4891
4892         /* Clear all of the statistics registers (clear on read).  It is
4893          * important that we do this after we have tried to establish link
4894          * because the symbol error count will increment wildly if there
4895          * is no link.
4896          */
4897         e1000_clear_hw_cntrs_ich8lan(hw);
4898
4899         return ret_val;
4900 }
4901
4902 /**
4903  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
4904  *  @hw: pointer to the HW structure
4905  *
4906  *  Sets/Clears required hardware bits necessary for correctly setting up the
4907  *  hardware for transmit and receive.
4908  **/
4909 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
4910 {
4911         u32 reg;
4912
4913         /* Extended Device Control */
4914         reg = er32(CTRL_EXT);
4915         reg |= BIT(22);
4916         /* Enable PHY low-power state when MAC is at D3 w/o WoL */
4917         if (hw->mac.type >= e1000_pchlan)
4918                 reg |= E1000_CTRL_EXT_PHYPDEN;
4919         ew32(CTRL_EXT, reg);
4920
4921         /* Transmit Descriptor Control 0 */
4922         reg = er32(TXDCTL(0));
4923         reg |= BIT(22);
4924         ew32(TXDCTL(0), reg);
4925
4926         /* Transmit Descriptor Control 1 */
4927         reg = er32(TXDCTL(1));
4928         reg |= BIT(22);
4929         ew32(TXDCTL(1), reg);
4930
4931         /* Transmit Arbitration Control 0 */
4932         reg = er32(TARC(0));
4933         if (hw->mac.type == e1000_ich8lan)
4934                 reg |= BIT(28) | BIT(29);
4935         reg |= BIT(23) | BIT(24) | BIT(26) | BIT(27);
4936         ew32(TARC(0), reg);
4937
4938         /* Transmit Arbitration Control 1 */
4939         reg = er32(TARC(1));
4940         if (er32(TCTL) & E1000_TCTL_MULR)
4941                 reg &= ~BIT(28);
4942         else
4943                 reg |= BIT(28);
4944         reg |= BIT(24) | BIT(26) | BIT(30);
4945         ew32(TARC(1), reg);
4946
4947         /* Device Status */
4948         if (hw->mac.type == e1000_ich8lan) {
4949                 reg = er32(STATUS);
4950                 reg &= ~BIT(31);
4951                 ew32(STATUS, reg);
4952         }
4953
4954         /* work-around descriptor data corruption issue during nfs v2 udp
4955          * traffic, just disable the nfs filtering capability
4956          */
4957         reg = er32(RFCTL);
4958         reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
4959
4960         /* Disable IPv6 extension header parsing because some malformed
4961          * IPv6 headers can hang the Rx.
4962          */
4963         if (hw->mac.type == e1000_ich8lan)
4964                 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
4965         ew32(RFCTL, reg);
4966
4967         /* Enable ECC on Lynxpoint */
4968         if (hw->mac.type >= e1000_pch_lpt) {
4969                 reg = er32(PBECCSTS);
4970                 reg |= E1000_PBECCSTS_ECC_ENABLE;
4971                 ew32(PBECCSTS, reg);
4972
4973                 reg = er32(CTRL);
4974                 reg |= E1000_CTRL_MEHE;
4975                 ew32(CTRL, reg);
4976         }
4977 }
4978
4979 /**
4980  *  e1000_setup_link_ich8lan - Setup flow control and link settings
4981  *  @hw: pointer to the HW structure
4982  *
4983  *  Determines which flow control settings to use, then configures flow
4984  *  control.  Calls the appropriate media-specific link configuration
4985  *  function.  Assuming the adapter has a valid link partner, a valid link
4986  *  should be established.  Assumes the hardware has previously been reset
4987  *  and the transmitter and receiver are not enabled.
4988  **/
4989 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
4990 {
4991         s32 ret_val;
4992
4993         if (hw->phy.ops.check_reset_block(hw))
4994                 return 0;
4995
4996         /* ICH parts do not have a word in the NVM to determine
4997          * the default flow control setting, so we explicitly
4998          * set it to full.
4999          */
5000         if (hw->fc.requested_mode == e1000_fc_default) {
5001                 /* Workaround h/w hang when Tx flow control enabled */
5002                 if (hw->mac.type == e1000_pchlan)
5003                         hw->fc.requested_mode = e1000_fc_rx_pause;
5004                 else
5005                         hw->fc.requested_mode = e1000_fc_full;
5006         }
5007
5008         /* Save off the requested flow control mode for use later.  Depending
5009          * on the link partner's capabilities, we may or may not use this mode.
5010          */
5011         hw->fc.current_mode = hw->fc.requested_mode;
5012
5013         e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);
5014
5015         /* Continue to configure the copper link. */
5016         ret_val = hw->mac.ops.setup_physical_interface(hw);
5017         if (ret_val)
5018                 return ret_val;
5019
5020         ew32(FCTTV, hw->fc.pause_time);
5021         if ((hw->phy.type == e1000_phy_82578) ||
5022             (hw->phy.type == e1000_phy_82579) ||
5023             (hw->phy.type == e1000_phy_i217) ||
5024             (hw->phy.type == e1000_phy_82577)) {
5025                 ew32(FCRTV_PCH, hw->fc.refresh_time);
5026
5027                 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
5028                                    hw->fc.pause_time);
5029                 if (ret_val)
5030                         return ret_val;
5031         }
5032
5033         return e1000e_set_fc_watermarks(hw);
5034 }
5035
5036 /**
5037  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
5038  *  @hw: pointer to the HW structure
5039  *
5040  *  Configures the kumeran interface to the PHY to wait the appropriate time
5041  *  when polling the PHY, then call the generic setup_copper_link to finish
5042  *  configuring the copper link.
5043  **/
5044 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
5045 {
5046         u32 ctrl;
5047         s32 ret_val;
5048         u16 reg_data;
5049
5050         ctrl = er32(CTRL);
5051         ctrl |= E1000_CTRL_SLU;
5052         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5053         ew32(CTRL, ctrl);
5054
5055         /* Set the mac to wait the maximum time between each iteration
5056          * and increase the max iterations when polling the phy;
5057          * this fixes erroneous timeouts at 10Mbps.
5058          */
5059         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
5060         if (ret_val)
5061                 return ret_val;
5062         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
5063                                        &reg_data);
5064         if (ret_val)
5065                 return ret_val;
5066         reg_data |= 0x3F;
5067         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
5068                                         reg_data);
5069         if (ret_val)
5070                 return ret_val;
5071
5072         switch (hw->phy.type) {
5073         case e1000_phy_igp_3:
5074                 ret_val = e1000e_copper_link_setup_igp(hw);
5075                 if (ret_val)
5076                         return ret_val;
5077                 break;
5078         case e1000_phy_bm:
5079         case e1000_phy_82578:
5080                 ret_val = e1000e_copper_link_setup_m88(hw);
5081                 if (ret_val)
5082                         return ret_val;
5083                 break;
5084         case e1000_phy_82577:
5085         case e1000_phy_82579:
5086                 ret_val = e1000_copper_link_setup_82577(hw);
5087                 if (ret_val)
5088                         return ret_val;
5089                 break;
5090         case e1000_phy_ife:
5091                 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
5092                 if (ret_val)
5093                         return ret_val;
5094
5095                 reg_data &= ~IFE_PMC_AUTO_MDIX;
5096
5097                 switch (hw->phy.mdix) {
5098                 case 1:
5099                         reg_data &= ~IFE_PMC_FORCE_MDIX;
5100                         break;
5101                 case 2:
5102                         reg_data |= IFE_PMC_FORCE_MDIX;
5103                         break;
5104                 case 0:
5105                 default:
5106                         reg_data |= IFE_PMC_AUTO_MDIX;
5107                         break;
5108                 }
5109                 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
5110                 if (ret_val)
5111                         return ret_val;
5112                 break;
5113         default:
5114                 break;
5115         }
5116
5117         return e1000e_setup_copper_link(hw);
5118 }
5119
5120 /**
5121  *  e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
5122  *  @hw: pointer to the HW structure
5123  *
5124  *  Calls the PHY specific link setup function and then calls the
5125  *  generic setup_copper_link to finish configuring the link for
5126  *  Lynxpoint PCH devices
5127  **/
5128 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
5129 {
5130         u32 ctrl;
5131         s32 ret_val;
5132
5133         ctrl = er32(CTRL);
5134         ctrl |= E1000_CTRL_SLU;
5135         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5136         ew32(CTRL, ctrl);
5137
5138         ret_val = e1000_copper_link_setup_82577(hw);
5139         if (ret_val)
5140                 return ret_val;
5141
5142         return e1000e_setup_copper_link(hw);
5143 }
5144
5145 /**
5146  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
5147  *  @hw: pointer to the HW structure
5148  *  @speed: pointer to store current link speed
5149  *  @duplex: pointer to store the current link duplex
5150  *
5151  *  Calls the generic get_speed_and_duplex to retrieve the current link
5152  *  information and then calls the Kumeran lock loss workaround for links at
5153  *  gigabit speeds.
5154  **/
5155 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
5156                                           u16 *duplex)
5157 {
5158         s32 ret_val;
5159
5160         ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
5161         if (ret_val)
5162                 return ret_val;
5163
5164         if ((hw->mac.type == e1000_ich8lan) &&
5165             (hw->phy.type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
5166                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
5167         }
5168
5169         return ret_val;
5170 }
5171
5172 /**
5173  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
5174  *  @hw: pointer to the HW structure
5175  *
5176  *  Work-around for 82566 Kumeran PCS lock loss:
5177  *  On link status change (i.e. PCI reset, speed change) and link is up and
5178  *  speed is gigabit-
5179  *    0) if workaround is optionally disabled do nothing
5180  *    1) wait 1ms for Kumeran link to come up
5181  *    2) check Kumeran Diagnostic register PCS lock loss bit
5182  *    3) if not set the link is locked (all is good), otherwise...
5183  *    4) reset the PHY
5184  *    5) repeat up to 10 times
5185  *  Note: this is only called for IGP3 copper when speed is 1gb.
5186  **/
5187 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
5188 {
5189         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5190         u32 phy_ctrl;
5191         s32 ret_val;
5192         u16 i, data;
5193         bool link;
5194
5195         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
5196                 return 0;
5197
5198         /* Make sure link is up before proceeding.  If not just return.
5199          * Attempting this while link is negotiating fouled up link
5200          * stability
5201          */
5202         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
5203         if (!link)
5204                 return 0;
5205
5206         for (i = 0; i < 10; i++) {
5207                 /* read once to clear */
5208                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
5209                 if (ret_val)
5210                         return ret_val;
5211                 /* and again to get new status */
5212                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
5213                 if (ret_val)
5214                         return ret_val;
5215
5216                 /* check for PCS lock */
5217                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
5218                         return 0;
5219
5220                 /* Issue PHY reset */
5221                 e1000_phy_hw_reset(hw);
5222                 mdelay(5);
5223         }
5224         /* Disable GigE link negotiation */
5225         phy_ctrl = er32(PHY_CTRL);
5226         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
5227                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5228         ew32(PHY_CTRL, phy_ctrl);
5229
5230         /* Call gig speed drop workaround on Gig disable before accessing
5231          * any PHY registers
5232          */
5233         e1000e_gig_downshift_workaround_ich8lan(hw);
5234
5235         /* unable to acquire PCS lock */
5236         return -E1000_ERR_PHY;
5237 }
5238
5239 /**
5240  *  e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
5241  *  @hw: pointer to the HW structure
5242  *  @state: boolean value used to set the current Kumeran workaround state
5243  *
5244  *  If ICH8, set the current Kumeran workaround state (enabled - true
5245  *  /disabled - false).
5246  **/
5247 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
5248                                                   bool state)
5249 {
5250         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5251
5252         if (hw->mac.type != e1000_ich8lan) {
5253                 e_dbg("Workaround applies to ICH8 only.\n");
5254                 return;
5255         }
5256
5257         dev_spec->kmrn_lock_loss_workaround_enabled = state;
5258 }
5259
5260 /**
5261  *  e1000e_igp3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
5262  *  @hw: pointer to the HW structure
5263  *
5264  *  Workaround for 82566 power-down on D3 entry:
5265  *    1) disable gigabit link
5266  *    2) write VR power-down enable
5267  *    3) read it back
5268  *  Continue if successful, else issue LCD reset and repeat
5269  **/
5270 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
5271 {
5272         u32 reg;
5273         u16 data;
5274         u8 retry = 0;
5275
5276         if (hw->phy.type != e1000_phy_igp_3)
5277                 return;
5278
5279         /* Try the workaround twice (if needed) */
5280         do {
5281                 /* Disable link */
5282                 reg = er32(PHY_CTRL);
5283                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
5284                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5285                 ew32(PHY_CTRL, reg);
5286
5287                 /* Call gig speed drop workaround on Gig disable before
5288                  * accessing any PHY registers
5289                  */
5290                 if (hw->mac.type == e1000_ich8lan)
5291                         e1000e_gig_downshift_workaround_ich8lan(hw);
5292
5293                 /* Write VR power-down enable */
5294                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
5295                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5296                 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
5297
5298                 /* Read it back and test */
5299                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
5300                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5301                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
5302                         break;
5303
5304                 /* Issue PHY reset and repeat at most one more time */
5305                 reg = er32(CTRL);
5306                 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
5307                 retry++;
5308         } while (retry);
5309 }
5310
5311 /**
5312  *  e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
5313  *  @hw: pointer to the HW structure
5314  *
5315  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
5316  *  LPLU, Gig disable, MDIC PHY reset):
5317  *    1) Set Kumeran Near-end loopback
5318  *    2) Clear Kumeran Near-end loopback
5319  *  Should only be called for ICH8[m] devices with any 1G Phy.
5320  **/
5321 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
5322 {
5323         s32 ret_val;
5324         u16 reg_data;
5325
5326         if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife))
5327                 return;
5328
5329         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5330                                        &reg_data);
5331         if (ret_val)
5332                 return;
5333         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
5334         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5335                                         reg_data);
5336         if (ret_val)
5337                 return;
5338         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
5339         e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, reg_data);
5340 }
5341
5342 /**
5343  *  e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
5344  *  @hw: pointer to the HW structure
5345  *
5346  *  During S0 to Sx transition, it is possible the link remains at gig
5347  *  instead of negotiating to a lower speed.  Before going to Sx, set
5348  *  'Gig Disable' to force link speed negotiation to a lower speed based on
5349  *  the LPLU setting in the NVM or custom setting.  For PCH and newer parts,
5350  *  the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
5351  *  needs to be written.
5352  *  Parts that support (and are linked to a partner which support) EEE in
5353  *  100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
5354  *  than 10Mbps w/o EEE.
5355  **/
5356 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
5357 {
5358         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5359         u32 phy_ctrl;
5360         s32 ret_val;
5361
5362         phy_ctrl = er32(PHY_CTRL);
5363         phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
5364
5365         if (hw->phy.type == e1000_phy_i217) {
5366                 u16 phy_reg, device_id = hw->adapter->pdev->device;
5367
5368                 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
5369                     (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
5370                     (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
5371                     (device_id == E1000_DEV_ID_PCH_I218_V3) ||
5372                     (hw->mac.type >= e1000_pch_spt)) {
5373                         u32 fextnvm6 = er32(FEXTNVM6);
5374
5375                         ew32(FEXTNVM6, fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
5376                 }
5377
5378                 ret_val = hw->phy.ops.acquire(hw);
5379                 if (ret_val)
5380                         goto out;
5381
5382                 if (!dev_spec->eee_disable) {
5383                         u16 eee_advert;
5384
5385                         ret_val =
5386                             e1000_read_emi_reg_locked(hw,
5387                                                       I217_EEE_ADVERTISEMENT,
5388                                                       &eee_advert);
5389                         if (ret_val)
5390                                 goto release;
5391
5392                         /* Disable LPLU if both link partners support 100BaseT
5393                          * EEE and 100Full is advertised on both ends of the
5394                          * link, and enable Auto Enable LPI since there will
5395                          * be no driver to enable LPI while in Sx.
5396                          */
5397                         if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
5398                             (dev_spec->eee_lp_ability &
5399                              I82579_EEE_100_SUPPORTED) &&
5400                             (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {
5401                                 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
5402                                               E1000_PHY_CTRL_NOND0A_LPLU);
5403
5404                                 /* Set Auto Enable LPI after link up */
5405                                 e1e_rphy_locked(hw,
5406                                                 I217_LPI_GPIO_CTRL, &phy_reg);
5407                                 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5408                                 e1e_wphy_locked(hw,
5409                                                 I217_LPI_GPIO_CTRL, phy_reg);
5410                         }
5411                 }
5412
5413                 /* For i217 Intel Rapid Start Technology support,
5414                  * when the system is going into Sx and no manageability engine
5415                  * is present, the driver must configure proxy to reset only on
5416                  * power good.  LPI (Low Power Idle) state must also reset only
5417                  * on power good, as well as the MTA (Multicast table array).
5418                  * The SMBus release must also be disabled on LCD reset.
5419                  */
5420                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
5421                         /* Enable proxy to reset only on power good. */
5422                         e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg);
5423                         phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
5424                         e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg);
5425
5426                         /* Set bit enable LPI (EEE) to reset only on
5427                          * power good.
5428                          */
5429                         e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg);
5430                         phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
5431                         e1e_wphy_locked(hw, I217_SxCTRL, phy_reg);
5432
5433                         /* Disable the SMB release on LCD reset. */
5434                         e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
5435                         phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
5436                         e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
5437                 }
5438
5439                 /* Enable MTA to reset for Intel Rapid Start Technology
5440                  * Support
5441                  */
5442                 e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
5443                 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
5444                 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
5445
5446 release:
5447                 hw->phy.ops.release(hw);
5448         }
5449 out:
5450         ew32(PHY_CTRL, phy_ctrl);
5451
5452         if (hw->mac.type == e1000_ich8lan)
5453                 e1000e_gig_downshift_workaround_ich8lan(hw);
5454
5455         if (hw->mac.type >= e1000_pchlan) {
5456                 e1000_oem_bits_config_ich8lan(hw, false);
5457
5458                 /* Reset PHY to activate OEM bits on 82577/8 */
5459                 if (hw->mac.type == e1000_pchlan)
5460                         e1000e_phy_hw_reset_generic(hw);
5461
5462                 ret_val = hw->phy.ops.acquire(hw);
5463                 if (ret_val)
5464                         return;
5465                 e1000_write_smbus_addr(hw);
5466                 hw->phy.ops.release(hw);
5467         }
5468 }
5469
5470 /**
5471  *  e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
5472  *  @hw: pointer to the HW structure
5473  *
5474  *  During Sx to S0 transitions on non-managed devices or managed devices
5475  *  on which PHY resets are not blocked, if the PHY registers cannot be
5476  *  accessed properly by the s/w toggle the LANPHYPC value to power cycle
5477  *  the PHY.
5478  *  On i217, setup Intel Rapid Start Technology.
5479  **/
5480 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
5481 {
5482         s32 ret_val;
5483
5484         if (hw->mac.type < e1000_pch2lan)
5485                 return;
5486
5487         ret_val = e1000_init_phy_workarounds_pchlan(hw);
5488         if (ret_val) {
5489                 e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val);
5490                 return;
5491         }
5492
5493         /* For i217 Intel Rapid Start Technology support when the system
5494          * is transitioning from Sx and no manageability engine is present
5495          * configure SMBus to restore on reset, disable proxy, and enable
5496          * the reset on MTA (Multicast table array).
5497          */
5498         if (hw->phy.type == e1000_phy_i217) {
5499                 u16 phy_reg;
5500
5501                 ret_val = hw->phy.ops.acquire(hw);
5502                 if (ret_val) {
5503                         e_dbg("Failed to setup iRST\n");
5504                         return;
5505                 }
5506
5507                 /* Clear Auto Enable LPI after link up */
5508                 e1e_rphy_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
5509                 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5510                 e1e_wphy_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
5511
5512                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
5513                         /* Restore clear on SMB if no manageability engine
5514                          * is present
5515                          */
5516                         ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
5517                         if (ret_val)
5518                                 goto release;
5519                         phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
5520                         e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
5521
5522                         /* Disable Proxy */
5523                         e1e_wphy_locked(hw, I217_PROXY_CTRL, 0);
5524                 }
5525                 /* Enable reset on MTA */
5526                 ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
5527                 if (ret_val)
5528                         goto release;
5529                 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
5530                 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
5531 release:
5532                 if (ret_val)
5533                         e_dbg("Error %d in resume workarounds\n", ret_val);
5534                 hw->phy.ops.release(hw);
5535         }
5536 }
5537
5538 /**
5539  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
5540  *  @hw: pointer to the HW structure
5541  *
5542  *  Return the LED back to the default configuration.
5543  **/
5544 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
5545 {
5546         if (hw->phy.type == e1000_phy_ife)
5547                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
5548
5549         ew32(LEDCTL, hw->mac.ledctl_default);
5550         return 0;
5551 }
5552
5553 /**
5554  *  e1000_led_on_ich8lan - Turn LEDs on
5555  *  @hw: pointer to the HW structure
5556  *
5557  *  Turn on the LEDs.
5558  **/
5559 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
5560 {
5561         if (hw->phy.type == e1000_phy_ife)
5562                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5563                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
5564
5565         ew32(LEDCTL, hw->mac.ledctl_mode2);
5566         return 0;
5567 }
5568
5569 /**
5570  *  e1000_led_off_ich8lan - Turn LEDs off
5571  *  @hw: pointer to the HW structure
5572  *
5573  *  Turn off the LEDs.
5574  **/
5575 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
5576 {
5577         if (hw->phy.type == e1000_phy_ife)
5578                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5579                                 (IFE_PSCL_PROBE_MODE |
5580                                  IFE_PSCL_PROBE_LEDS_OFF));
5581
5582         ew32(LEDCTL, hw->mac.ledctl_mode1);
5583         return 0;
5584 }
5585
5586 /**
5587  *  e1000_setup_led_pchlan - Configures SW controllable LED
5588  *  @hw: pointer to the HW structure
5589  *
5590  *  This prepares the SW controllable LED for use.
5591  **/
5592 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
5593 {
5594         return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);
5595 }
5596
5597 /**
5598  *  e1000_cleanup_led_pchlan - Restore the default LED operation
5599  *  @hw: pointer to the HW structure
5600  *
5601  *  Return the LED back to the default configuration.
5602  **/
5603 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
5604 {
5605         return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);
5606 }
5607
5608 /**
5609  *  e1000_led_on_pchlan - Turn LEDs on
5610  *  @hw: pointer to the HW structure
5611  *
5612  *  Turn on the LEDs.
5613  **/
5614 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
5615 {
5616         u16 data = (u16)hw->mac.ledctl_mode2;
5617         u32 i, led;
5618
5619         /* If no link, then turn LED on by setting the invert bit
5620          * for each LED that's mode is "link_up" in ledctl_mode2.
5621          */
5622         if (!(er32(STATUS) & E1000_STATUS_LU)) {
5623                 for (i = 0; i < 3; i++) {
5624                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5625                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
5626                             E1000_LEDCTL_MODE_LINK_UP)
5627                                 continue;
5628                         if (led & E1000_PHY_LED0_IVRT)
5629                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5630                         else
5631                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5632                 }
5633         }
5634
5635         return e1e_wphy(hw, HV_LED_CONFIG, data);
5636 }
5637
5638 /**
5639  *  e1000_led_off_pchlan - Turn LEDs off
5640  *  @hw: pointer to the HW structure
5641  *
5642  *  Turn off the LEDs.
5643  **/
5644 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
5645 {
5646         u16 data = (u16)hw->mac.ledctl_mode1;
5647         u32 i, led;
5648
5649         /* If no link, then turn LED off by clearing the invert bit
5650          * for each LED that's mode is "link_up" in ledctl_mode1.
5651          */
5652         if (!(er32(STATUS) & E1000_STATUS_LU)) {
5653                 for (i = 0; i < 3; i++) {
5654                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5655                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
5656                             E1000_LEDCTL_MODE_LINK_UP)
5657                                 continue;
5658                         if (led & E1000_PHY_LED0_IVRT)
5659                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5660                         else
5661                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5662                 }
5663         }
5664
5665         return e1e_wphy(hw, HV_LED_CONFIG, data);
5666 }
5667
5668 /**
5669  *  e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
5670  *  @hw: pointer to the HW structure
5671  *
5672  *  Read appropriate register for the config done bit for completion status
5673  *  and configure the PHY through s/w for EEPROM-less parts.
5674  *
5675  *  NOTE: some silicon which is EEPROM-less will fail trying to read the
5676  *  config done bit, so only an error is logged and continues.  If we were
5677  *  to return with error, EEPROM-less silicon would not be able to be reset
5678  *  or change link.
5679  **/
5680 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
5681 {
5682         s32 ret_val = 0;
5683         u32 bank = 0;
5684         u32 status;
5685
5686         e1000e_get_cfg_done_generic(hw);
5687
5688         /* Wait for indication from h/w that it has completed basic config */
5689         if (hw->mac.type >= e1000_ich10lan) {
5690                 e1000_lan_init_done_ich8lan(hw);
5691         } else {
5692                 ret_val = e1000e_get_auto_rd_done(hw);
5693                 if (ret_val) {
5694                         /* When auto config read does not complete, do not
5695                          * return with an error. This can happen in situations
5696                          * where there is no eeprom and prevents getting link.
5697                          */
5698                         e_dbg("Auto Read Done did not complete\n");
5699                         ret_val = 0;
5700                 }
5701         }
5702
5703         /* Clear PHY Reset Asserted bit */
5704         status = er32(STATUS);
5705         if (status & E1000_STATUS_PHYRA)
5706                 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
5707         else
5708                 e_dbg("PHY Reset Asserted not set - needs delay\n");
5709
5710         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
5711         if (hw->mac.type <= e1000_ich9lan) {
5712                 if (!(er32(EECD) & E1000_EECD_PRES) &&
5713                     (hw->phy.type == e1000_phy_igp_3)) {
5714                         e1000e_phy_init_script_igp3(hw);
5715                 }
5716         } else {
5717                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
5718                         /* Maybe we should do a basic PHY config */
5719                         e_dbg("EEPROM not present\n");
5720                         ret_val = -E1000_ERR_CONFIG;
5721                 }
5722         }
5723
5724         return ret_val;
5725 }
5726
5727 /**
5728  * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
5729  * @hw: pointer to the HW structure
5730  *
5731  * In the case of a PHY power down to save power, or to turn off link during a
5732  * driver unload, or wake on lan is not enabled, remove the link.
5733  **/
5734 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
5735 {
5736         /* If the management interface is not enabled, then power down */
5737         if (!(hw->mac.ops.check_mng_mode(hw) ||
5738               hw->phy.ops.check_reset_block(hw)))
5739                 e1000_power_down_phy_copper(hw);
5740 }
5741
5742 /**
5743  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
5744  *  @hw: pointer to the HW structure
5745  *
5746  *  Clears hardware counters specific to the silicon family and calls
5747  *  clear_hw_cntrs_generic to clear all general purpose counters.
5748  **/
5749 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
5750 {
5751         u16 phy_data;
5752         s32 ret_val;
5753
5754         e1000e_clear_hw_cntrs_base(hw);
5755
5756         er32(ALGNERRC);
5757         er32(RXERRC);
5758         er32(TNCRS);
5759         er32(CEXTERR);
5760         er32(TSCTC);
5761         er32(TSCTFC);
5762
5763         er32(MGTPRC);
5764         er32(MGTPDC);
5765         er32(MGTPTC);
5766
5767         er32(IAC);
5768         er32(ICRXOC);
5769
5770         /* Clear PHY statistics registers */
5771         if ((hw->phy.type == e1000_phy_82578) ||
5772             (hw->phy.type == e1000_phy_82579) ||
5773             (hw->phy.type == e1000_phy_i217) ||
5774             (hw->phy.type == e1000_phy_82577)) {
5775                 ret_val = hw->phy.ops.acquire(hw);
5776                 if (ret_val)
5777                         return;
5778                 ret_val = hw->phy.ops.set_page(hw,
5779                                                HV_STATS_PAGE << IGP_PAGE_SHIFT);
5780                 if (ret_val)
5781                         goto release;
5782                 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
5783                 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
5784                 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
5785                 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
5786                 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
5787                 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
5788                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
5789                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
5790                 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
5791                 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
5792                 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
5793                 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
5794                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
5795                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
5796 release:
5797                 hw->phy.ops.release(hw);
5798         }
5799 }
5800
5801 static const struct e1000_mac_operations ich8_mac_ops = {
5802         /* check_mng_mode dependent on mac type */
5803         .check_for_link         = e1000_check_for_copper_link_ich8lan,
5804         /* cleanup_led dependent on mac type */
5805         .clear_hw_cntrs         = e1000_clear_hw_cntrs_ich8lan,
5806         .get_bus_info           = e1000_get_bus_info_ich8lan,
5807         .set_lan_id             = e1000_set_lan_id_single_port,
5808         .get_link_up_info       = e1000_get_link_up_info_ich8lan,
5809         /* led_on dependent on mac type */
5810         /* led_off dependent on mac type */
5811         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
5812         .reset_hw               = e1000_reset_hw_ich8lan,
5813         .init_hw                = e1000_init_hw_ich8lan,
5814         .setup_link             = e1000_setup_link_ich8lan,
5815         .setup_physical_interface = e1000_setup_copper_link_ich8lan,
5816         /* id_led_init dependent on mac type */
5817         .config_collision_dist  = e1000e_config_collision_dist_generic,
5818         .rar_set                = e1000e_rar_set_generic,
5819         .rar_get_count          = e1000e_rar_get_count_generic,
5820 };
5821
5822 static const struct e1000_phy_operations ich8_phy_ops = {
5823         .acquire                = e1000_acquire_swflag_ich8lan,
5824         .check_reset_block      = e1000_check_reset_block_ich8lan,
5825         .commit                 = NULL,
5826         .get_cfg_done           = e1000_get_cfg_done_ich8lan,
5827         .get_cable_length       = e1000e_get_cable_length_igp_2,
5828         .read_reg               = e1000e_read_phy_reg_igp,
5829         .release                = e1000_release_swflag_ich8lan,
5830         .reset                  = e1000_phy_hw_reset_ich8lan,
5831         .set_d0_lplu_state      = e1000_set_d0_lplu_state_ich8lan,
5832         .set_d3_lplu_state      = e1000_set_d3_lplu_state_ich8lan,
5833         .write_reg              = e1000e_write_phy_reg_igp,
5834 };
5835
5836 static const struct e1000_nvm_operations ich8_nvm_ops = {
5837         .acquire                = e1000_acquire_nvm_ich8lan,
5838         .read                   = e1000_read_nvm_ich8lan,
5839         .release                = e1000_release_nvm_ich8lan,
5840         .reload                 = e1000e_reload_nvm_generic,
5841         .update                 = e1000_update_nvm_checksum_ich8lan,
5842         .valid_led_default      = e1000_valid_led_default_ich8lan,
5843         .validate               = e1000_validate_nvm_checksum_ich8lan,
5844         .write                  = e1000_write_nvm_ich8lan,
5845 };
5846
5847 static const struct e1000_nvm_operations spt_nvm_ops = {
5848         .acquire                = e1000_acquire_nvm_ich8lan,
5849         .release                = e1000_release_nvm_ich8lan,
5850         .read                   = e1000_read_nvm_spt,
5851         .update                 = e1000_update_nvm_checksum_spt,
5852         .reload                 = e1000e_reload_nvm_generic,
5853         .valid_led_default      = e1000_valid_led_default_ich8lan,
5854         .validate               = e1000_validate_nvm_checksum_ich8lan,
5855         .write                  = e1000_write_nvm_ich8lan,
5856 };
5857
5858 const struct e1000_info e1000_ich8_info = {
5859         .mac                    = e1000_ich8lan,
5860         .flags                  = FLAG_HAS_WOL
5861                                   | FLAG_IS_ICH
5862                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5863                                   | FLAG_HAS_AMT
5864                                   | FLAG_HAS_FLASH
5865                                   | FLAG_APME_IN_WUC,
5866         .pba                    = 8,
5867         .max_hw_frame_size      = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN,
5868         .get_variants           = e1000_get_variants_ich8lan,
5869         .mac_ops                = &ich8_mac_ops,
5870         .phy_ops                = &ich8_phy_ops,
5871         .nvm_ops                = &ich8_nvm_ops,
5872 };
5873
5874 const struct e1000_info e1000_ich9_info = {
5875         .mac                    = e1000_ich9lan,
5876         .flags                  = FLAG_HAS_JUMBO_FRAMES
5877                                   | FLAG_IS_ICH
5878                                   | FLAG_HAS_WOL
5879                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5880                                   | FLAG_HAS_AMT
5881                                   | FLAG_HAS_FLASH
5882                                   | FLAG_APME_IN_WUC,
5883         .pba                    = 18,
5884         .max_hw_frame_size      = DEFAULT_JUMBO,
5885         .get_variants           = e1000_get_variants_ich8lan,
5886         .mac_ops                = &ich8_mac_ops,
5887         .phy_ops                = &ich8_phy_ops,
5888         .nvm_ops                = &ich8_nvm_ops,
5889 };
5890
5891 const struct e1000_info e1000_ich10_info = {
5892         .mac                    = e1000_ich10lan,
5893         .flags                  = FLAG_HAS_JUMBO_FRAMES
5894                                   | FLAG_IS_ICH
5895                                   | FLAG_HAS_WOL
5896                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5897                                   | FLAG_HAS_AMT
5898                                   | FLAG_HAS_FLASH
5899                                   | FLAG_APME_IN_WUC,
5900         .pba                    = 18,
5901         .max_hw_frame_size      = DEFAULT_JUMBO,
5902         .get_variants           = e1000_get_variants_ich8lan,
5903         .mac_ops                = &ich8_mac_ops,
5904         .phy_ops                = &ich8_phy_ops,
5905         .nvm_ops                = &ich8_nvm_ops,
5906 };
5907
5908 const struct e1000_info e1000_pch_info = {
5909         .mac                    = e1000_pchlan,
5910         .flags                  = FLAG_IS_ICH
5911                                   | FLAG_HAS_WOL
5912                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5913                                   | FLAG_HAS_AMT
5914                                   | FLAG_HAS_FLASH
5915                                   | FLAG_HAS_JUMBO_FRAMES
5916                                   | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
5917                                   | FLAG_APME_IN_WUC,
5918         .flags2                 = FLAG2_HAS_PHY_STATS,
5919         .pba                    = 26,
5920         .max_hw_frame_size      = 4096,
5921         .get_variants           = e1000_get_variants_ich8lan,
5922         .mac_ops                = &ich8_mac_ops,
5923         .phy_ops                = &ich8_phy_ops,
5924         .nvm_ops                = &ich8_nvm_ops,
5925 };
5926
5927 const struct e1000_info e1000_pch2_info = {
5928         .mac                    = e1000_pch2lan,
5929         .flags                  = FLAG_IS_ICH
5930                                   | FLAG_HAS_WOL
5931                                   | FLAG_HAS_HW_TIMESTAMP
5932                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5933                                   | FLAG_HAS_AMT
5934                                   | FLAG_HAS_FLASH
5935                                   | FLAG_HAS_JUMBO_FRAMES
5936                                   | FLAG_APME_IN_WUC,
5937         .flags2                 = FLAG2_HAS_PHY_STATS
5938                                   | FLAG2_HAS_EEE
5939                                   | FLAG2_CHECK_SYSTIM_OVERFLOW,
5940         .pba                    = 26,
5941         .max_hw_frame_size      = 9022,
5942         .get_variants           = e1000_get_variants_ich8lan,
5943         .mac_ops                = &ich8_mac_ops,
5944         .phy_ops                = &ich8_phy_ops,
5945         .nvm_ops                = &ich8_nvm_ops,
5946 };
5947
5948 const struct e1000_info e1000_pch_lpt_info = {
5949         .mac                    = e1000_pch_lpt,
5950         .flags                  = FLAG_IS_ICH
5951                                   | FLAG_HAS_WOL
5952                                   | FLAG_HAS_HW_TIMESTAMP
5953                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5954                                   | FLAG_HAS_AMT
5955                                   | FLAG_HAS_FLASH
5956                                   | FLAG_HAS_JUMBO_FRAMES
5957                                   | FLAG_APME_IN_WUC,
5958         .flags2                 = FLAG2_HAS_PHY_STATS
5959                                   | FLAG2_HAS_EEE
5960                                   | FLAG2_CHECK_SYSTIM_OVERFLOW,
5961         .pba                    = 26,
5962         .max_hw_frame_size      = 9022,
5963         .get_variants           = e1000_get_variants_ich8lan,
5964         .mac_ops                = &ich8_mac_ops,
5965         .phy_ops                = &ich8_phy_ops,
5966         .nvm_ops                = &ich8_nvm_ops,
5967 };
5968
5969 const struct e1000_info e1000_pch_spt_info = {
5970         .mac                    = e1000_pch_spt,
5971         .flags                  = FLAG_IS_ICH
5972                                   | FLAG_HAS_WOL
5973                                   | FLAG_HAS_HW_TIMESTAMP
5974                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5975                                   | FLAG_HAS_AMT
5976                                   | FLAG_HAS_FLASH
5977                                   | FLAG_HAS_JUMBO_FRAMES
5978                                   | FLAG_APME_IN_WUC,
5979         .flags2                 = FLAG2_HAS_PHY_STATS
5980                                   | FLAG2_HAS_EEE,
5981         .pba                    = 26,
5982         .max_hw_frame_size      = 9022,
5983         .get_variants           = e1000_get_variants_ich8lan,
5984         .mac_ops                = &ich8_mac_ops,
5985         .phy_ops                = &ich8_phy_ops,
5986         .nvm_ops                = &spt_nvm_ops,
5987 };
5988
5989 const struct e1000_info e1000_pch_cnp_info = {
5990         .mac                    = e1000_pch_cnp,
5991         .flags                  = FLAG_IS_ICH
5992                                   | FLAG_HAS_WOL
5993                                   | FLAG_HAS_HW_TIMESTAMP
5994                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5995                                   | FLAG_HAS_AMT
5996                                   | FLAG_HAS_FLASH
5997                                   | FLAG_HAS_JUMBO_FRAMES
5998                                   | FLAG_APME_IN_WUC,
5999         .flags2                 = FLAG2_HAS_PHY_STATS
6000                                   | FLAG2_HAS_EEE,
6001         .pba                    = 26,
6002         .max_hw_frame_size      = 9022,
6003         .get_variants           = e1000_get_variants_ich8lan,
6004         .mac_ops                = &ich8_mac_ops,
6005         .phy_ops                = &ich8_phy_ops,
6006         .nvm_ops                = &spt_nvm_ops,
6007 };
6008
6009 const struct e1000_info e1000_pch_tgp_info = {
6010         .mac                    = e1000_pch_tgp,
6011         .flags                  = FLAG_IS_ICH
6012                                   | FLAG_HAS_WOL
6013                                   | FLAG_HAS_HW_TIMESTAMP
6014                                   | FLAG_HAS_CTRLEXT_ON_LOAD
6015                                   | FLAG_HAS_AMT
6016                                   | FLAG_HAS_FLASH
6017                                   | FLAG_HAS_JUMBO_FRAMES
6018                                   | FLAG_APME_IN_WUC,
6019         .flags2                 = FLAG2_HAS_PHY_STATS
6020                                   | FLAG2_HAS_EEE,
6021         .pba                    = 26,
6022         .max_hw_frame_size      = 9022,
6023         .get_variants           = e1000_get_variants_ich8lan,
6024         .mac_ops                = &ich8_mac_ops,
6025         .phy_ops                = &ich8_phy_ops,
6026         .nvm_ops                = &spt_nvm_ops,
6027 };
6028
6029 const struct e1000_info e1000_pch_adp_info = {
6030         .mac                    = e1000_pch_adp,
6031         .flags                  = FLAG_IS_ICH
6032                                   | FLAG_HAS_WOL
6033                                   | FLAG_HAS_HW_TIMESTAMP
6034                                   | FLAG_HAS_CTRLEXT_ON_LOAD
6035                                   | FLAG_HAS_AMT
6036                                   | FLAG_HAS_FLASH
6037                                   | FLAG_HAS_JUMBO_FRAMES
6038                                   | FLAG_APME_IN_WUC,
6039         .flags2                 = FLAG2_HAS_PHY_STATS
6040                                   | FLAG2_HAS_EEE,
6041         .pba                    = 26,
6042         .max_hw_frame_size      = 9022,
6043         .get_variants           = e1000_get_variants_ich8lan,
6044         .mac_ops                = &ich8_mac_ops,
6045         .phy_ops                = &ich8_phy_ops,
6046         .nvm_ops                = &spt_nvm_ops,
6047 };