drivers/net/ethernet/intel/e1000e/ich8lan.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
   3
   4 /* 82562G 10/100 Network Connection
   5  * 82562G-2 10/100 Network Connection
   6  * 82562GT 10/100 Network Connection
   7  * 82562GT-2 10/100 Network Connection
   8  * 82562V 10/100 Network Connection
   9  * 82562V-2 10/100 Network Connection
  10  * 82566DC-2 Gigabit Network Connection
  11  * 82566DC Gigabit Network Connection
  12  * 82566DM-2 Gigabit Network Connection
  13  * 82566DM Gigabit Network Connection
  14  * 82566MC Gigabit Network Connection
  15  * 82566MM Gigabit Network Connection
  16  * 82567LM Gigabit Network Connection
  17  * 82567LF Gigabit Network Connection
  18  * 82567V Gigabit Network Connection
  19  * 82567LM-2 Gigabit Network Connection
  20  * 82567LF-2 Gigabit Network Connection
  21  * 82567V-2 Gigabit Network Connection
  22  * 82567LF-3 Gigabit Network Connection
  23  * 82567LM-3 Gigabit Network Connection
  24  * 82567LM-4 Gigabit Network Connection
  25  * 82577LM Gigabit Network Connection
  26  * 82577LC Gigabit Network Connection
  27  * 82578DM Gigabit Network Connection
  28  * 82578DC Gigabit Network Connection
  29  * 82579LM Gigabit Network Connection
  30  * 82579V Gigabit Network Connection
  31  * Ethernet Connection I217-LM
  32  * Ethernet Connection I217-V
  33  * Ethernet Connection I218-V
  34  * Ethernet Connection I218-LM
  35  * Ethernet Connection (2) I218-LM
  36  * Ethernet Connection (2) I218-V
  37  * Ethernet Connection (3) I218-LM
  38  * Ethernet Connection (3) I218-V
  39  */
  40
  41 #include "e1000.h"
  42
  43 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
  44 /* Offset 04h HSFSTS */
  45 union ich8_hws_flash_status {
  46         struct ich8_hsfsts {
  47                 u16 flcdone:1;  /* bit 0 Flash Cycle Done */
  48                 u16 flcerr:1;   /* bit 1 Flash Cycle Error */
  49                 u16 dael:1;     /* bit 2 Direct Access error Log */
  50                 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
  51                 u16 flcinprog:1;        /* bit 5 flash cycle in Progress */
  52                 u16 reserved1:2;        /* bit 13:6 Reserved */
  53                 u16 reserved2:6;        /* bit 13:6 Reserved */
  54                 u16 fldesvalid:1;       /* bit 14 Flash Descriptor Valid */
  55                 u16 flockdn:1;  /* bit 15 Flash Config Lock-Down */
  56         } hsf_status;
  57         u16 regval;
  58 };
  59
  60 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
  61 /* Offset 06h FLCTL */
  62 union ich8_hws_flash_ctrl {
  63         struct ich8_hsflctl {
  64                 u16 flcgo:1;    /* 0 Flash Cycle Go */
  65                 u16 flcycle:2;  /* 2:1 Flash Cycle */
  66                 u16 reserved:5; /* 7:3 Reserved  */
  67                 u16 fldbcount:2;        /* 9:8 Flash Data Byte Count */
  68                 u16 flockdn:6;  /* 15:10 Reserved */
  69         } hsf_ctrl;
  70         u16 regval;
  71 };
  72
  73 /* ICH Flash Region Access Permissions */
  74 union ich8_hws_flash_regacc {
  75         struct ich8_flracc {
  76                 u32 grra:8;     /* 0:7 GbE region Read Access */
  77                 u32 grwa:8;     /* 8:15 GbE region Write Access */
  78                 u32 gmrag:8;    /* 23:16 GbE Master Read Access Grant */
  79                 u32 gmwag:8;    /* 31:24 GbE Master Write Access Grant */
  80         } hsf_flregacc;
  81         u16 regval;
  82 };
  83
  84 /* ICH Flash Protected Region */
  85 union ich8_flash_protected_range {
  86         struct ich8_pr {
  87                 u32 base:13;    /* 0:12 Protected Range Base */
  88                 u32 reserved1:2;        /* 13:14 Reserved */
  89                 u32 rpe:1;      /* 15 Read Protection Enable */
  90                 u32 limit:13;   /* 16:28 Protected Range Limit */
  91                 u32 reserved2:2;        /* 29:30 Reserved */
  92                 u32 wpe:1;      /* 31 Write Protection Enable */
  93         } range;
  94         u32 regval;
  95 };
  96
  97 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
  98 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
  99 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 100 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 101                                                 u32 offset, u8 byte);
 102 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
 103                                          u8 *data);
 104 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
 105                                          u16 *data);
 106 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 107                                          u8 size, u16 *data);
 108 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
 109                                            u32 *data);
 110 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw,
 111                                           u32 offset, u32 *data);
 112 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw,
 113                                             u32 offset, u32 data);
 114 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
 115                                                  u32 offset, u32 dword);
 116 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 117 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
 118 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
 119 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
 120 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
 121 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
 122 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
 123 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
 124 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
 125 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
 126 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
 127 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
 128 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
 129 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
 130 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
 131 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
 132 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
 133 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
 134 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw);
 135 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
 136 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
 137 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force);
 138 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
 139 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state);
 140
 141 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
 142 {
 143         return readw(hw->flash_address + reg);
 144 }
 145
 146 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
 147 {
 148         return readl(hw->flash_address + reg);
 149 }
 150
 151 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
 152 {
 153         writew(val, hw->flash_address + reg);
 154 }
 155
 156 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
 157 {
 158         writel(val, hw->flash_address + reg);
 159 }
 160
 161 #define er16flash(reg)          __er16flash(hw, (reg))
 162 #define er32flash(reg)          __er32flash(hw, (reg))
 163 #define ew16flash(reg, val)     __ew16flash(hw, (reg), (val))
 164 #define ew32flash(reg, val)     __ew32flash(hw, (reg), (val))
 165
 166 /**
 167  *  e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
 168  *  @hw: pointer to the HW structure
 169  *
 170  *  Test access to the PHY registers by reading the PHY ID registers.  If
 171  *  the PHY ID is already known (e.g. resume path) compare it with known ID,
 172  *  otherwise assume the read PHY ID is correct if it is valid.
 173  *
 174  *  Assumes the sw/fw/hw semaphore is already acquired.
 175  **/
 176 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
 177 {
 178         u16 phy_reg = 0;
 179         u32 phy_id = 0;
 180         s32 ret_val = 0;
 181         u16 retry_count;
 182         u32 mac_reg = 0;
 183
 184         for (retry_count = 0; retry_count < 2; retry_count++) {
 185                 ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg);
 186                 if (ret_val || (phy_reg == 0xFFFF))
 187                         continue;
 188                 phy_id = (u32)(phy_reg << 16);
 189
 190                 ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg);
 191                 if (ret_val || (phy_reg == 0xFFFF)) {
 192                         phy_id = 0;
 193                         continue;
 194                 }
 195                 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
 196                 break;
 197         }
 198
 199         if (hw->phy.id) {
 200                 if (hw->phy.id == phy_id)
 201                         goto out;
 202         } else if (phy_id) {
 203                 hw->phy.id = phy_id;
 204                 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
 205                 goto out;
 206         }
 207
 208         /* In case the PHY needs to be in mdio slow mode,
 209          * set slow mode and try to get the PHY id again.
 210          */
 211         if (hw->mac.type < e1000_pch_lpt) {
 212                 hw->phy.ops.release(hw);
 213                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
 214                 if (!ret_val)
 215                         ret_val = e1000e_get_phy_id(hw);
 216                 hw->phy.ops.acquire(hw);
 217         }
 218
 219         if (ret_val)
 220                 return false;
 221 out:
 222         if (hw->mac.type >= e1000_pch_lpt) {
 223                 /* Only unforce SMBus if ME is not active */
 224                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
 225                         /* Unforce SMBus mode in PHY */
 226                         e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg);
 227                         phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
 228                         e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg);
 229
 230                         /* Unforce SMBus mode in MAC */
 231                         mac_reg = er32(CTRL_EXT);
 232                         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
 233                         ew32(CTRL_EXT, mac_reg);
 234                 }
 235         }
 236
 237         return true;
 238 }
 239
 240 /**
 241  *  e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
 242  *  @hw: pointer to the HW structure
 243  *
 244  *  Toggling the LANPHYPC pin value fully power-cycles the PHY and is
 245  *  used to reset the PHY to a quiescent state when necessary.
 246  **/
 247 static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
 248 {
 249         u32 mac_reg;
 250
 251         /* Set Phy Config Counter to 50msec */
 252         mac_reg = er32(FEXTNVM3);
 253         mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
 254         mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
 255         ew32(FEXTNVM3, mac_reg);
 256
 257         /* Toggle LANPHYPC Value bit */
 258         mac_reg = er32(CTRL);
 259         mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
 260         mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
 261         ew32(CTRL, mac_reg);
 262         e1e_flush();
 263         usleep_range(10, 20);
 264         mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
 265         ew32(CTRL, mac_reg);
 266         e1e_flush();
 267
 268         if (hw->mac.type < e1000_pch_lpt) {
 269                 msleep(50);
 270         } else {
 271                 u16 count = 20;
 272
 273                 do {
 274                         usleep_range(5000, 10000);
 275                 } while (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LPCD) && count--);
 276
 277                 msleep(30);
 278         }
 279 }
 280
 281 /**
 282  *  e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
 283  *  @hw: pointer to the HW structure
 284  *
 285  *  Workarounds/flow necessary for PHY initialization during driver load
 286  *  and resume paths.
 287  **/
 288 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
 289 {
 290         struct e1000_adapter *adapter = hw->adapter;
 291         u32 mac_reg, fwsm = er32(FWSM);
 292         s32 ret_val;
 293
 294         /* Gate automatic PHY configuration by hardware on managed and
 295          * non-managed 82579 and newer adapters.
 296          */
 297         e1000_gate_hw_phy_config_ich8lan(hw, true);
 298
 299         /* It is not possible to be certain of the current state of ULP
 300          * so forcibly disable it.
 301          */
 302         hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
 303         e1000_disable_ulp_lpt_lp(hw, true);
 304
 305         ret_val = hw->phy.ops.acquire(hw);
 306         if (ret_val) {
 307                 e_dbg("Failed to initialize PHY flow\n");
 308                 goto out;
 309         }
 310
 311         /* The MAC-PHY interconnect may be in SMBus mode.  If the PHY is
 312          * inaccessible and resetting the PHY is not blocked, toggle the
 313          * LANPHYPC Value bit to force the interconnect to PCIe mode.
 314          */
 315         switch (hw->mac.type) {
 316         case e1000_pch_lpt:
 317         case e1000_pch_spt:
 318         case e1000_pch_cnp:
 319                 if (e1000_phy_is_accessible_pchlan(hw))
 320                         break;
 321
 322                 /* Before toggling LANPHYPC, see if PHY is accessible by
 323                  * forcing MAC to SMBus mode first.
 324                  */
 325                 mac_reg = er32(CTRL_EXT);
 326                 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
 327                 ew32(CTRL_EXT, mac_reg);
 328
 329                 /* Wait 50 milliseconds for MAC to finish any retries
 330                  * that it might be trying to perform from previous
 331                  * attempts to acknowledge any phy read requests.
 332                  */
 333                 msleep(50);
 334
 335                 /* fall-through */
 336         case e1000_pch2lan:
 337                 if (e1000_phy_is_accessible_pchlan(hw))
 338                         break;
 339
 340                 /* fall-through */
 341         case e1000_pchlan:
 342                 if ((hw->mac.type == e1000_pchlan) &&
 343                     (fwsm & E1000_ICH_FWSM_FW_VALID))
 344                         break;
 345
 346                 if (hw->phy.ops.check_reset_block(hw)) {
 347                         e_dbg("Required LANPHYPC toggle blocked by ME\n");
 348                         ret_val = -E1000_ERR_PHY;
 349                         break;
 350                 }
 351
 352                 /* Toggle LANPHYPC Value bit */
 353                 e1000_toggle_lanphypc_pch_lpt(hw);
 354                 if (hw->mac.type >= e1000_pch_lpt) {
 355                         if (e1000_phy_is_accessible_pchlan(hw))
 356                                 break;
 357
 358                         /* Toggling LANPHYPC brings the PHY out of SMBus mode
 359                          * so ensure that the MAC is also out of SMBus mode
 360                          */
 361                         mac_reg = er32(CTRL_EXT);
 362                         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
 363                         ew32(CTRL_EXT, mac_reg);
 364
 365                         if (e1000_phy_is_accessible_pchlan(hw))
 366                                 break;
 367
 368                         ret_val = -E1000_ERR_PHY;
 369                 }
 370                 break;
 371         default:
 372                 break;
 373         }
 374
 375         hw->phy.ops.release(hw);
 376         if (!ret_val) {
 377
 378                 /* Check to see if able to reset PHY.  Print error if not */
 379                 if (hw->phy.ops.check_reset_block(hw)) {
 380                         e_err("Reset blocked by ME\n");
 381                         goto out;
 382                 }
 383
 384                 /* Reset the PHY before any access to it.  Doing so, ensures
 385                  * that the PHY is in a known good state before we read/write
 386                  * PHY registers.  The generic reset is sufficient here,
 387                  * because we haven't determined the PHY type yet.
 388                  */
 389                 ret_val = e1000e_phy_hw_reset_generic(hw);
 390                 if (ret_val)
 391                         goto out;
 392
 393                 /* On a successful reset, possibly need to wait for the PHY
 394                  * to quiesce to an accessible state before returning control
 395                  * to the calling function.  If the PHY does not quiesce, then
 396                  * return E1000E_BLK_PHY_RESET, as this is the condition that
 397                  *  the PHY is in.
 398                  */
 399                 ret_val = hw->phy.ops.check_reset_block(hw);
 400                 if (ret_val)
 401                         e_err("ME blocked access to PHY after reset\n");
 402         }
 403
 404 out:
 405         /* Ungate automatic PHY configuration on non-managed 82579 */
 406         if ((hw->mac.type == e1000_pch2lan) &&
 407             !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
 408                 usleep_range(10000, 20000);
 409                 e1000_gate_hw_phy_config_ich8lan(hw, false);
 410         }
 411
 412         return ret_val;
 413 }
 414
 415 /**
 416  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 417  *  @hw: pointer to the HW structure
 418  *
 419  *  Initialize family-specific PHY parameters and function pointers.
 420  **/
 421 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 422 {
 423         struct e1000_phy_info *phy = &hw->phy;
 424         s32 ret_val;
 425
 426         phy->addr = 1;
 427         phy->reset_delay_us = 100;
 428
 429         phy->ops.set_page = e1000_set_page_igp;
 430         phy->ops.read_reg = e1000_read_phy_reg_hv;
 431         phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
 432         phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;
 433         phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
 434         phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
 435         phy->ops.write_reg = e1000_write_phy_reg_hv;
 436         phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
 437         phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
 438         phy->ops.power_up = e1000_power_up_phy_copper;
 439         phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
 440         phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 441
 442         phy->id = e1000_phy_unknown;
 443
 444         ret_val = e1000_init_phy_workarounds_pchlan(hw);
 445         if (ret_val)
 446                 return ret_val;
 447
 448         if (phy->id == e1000_phy_unknown)
 449                 switch (hw->mac.type) {
 450                 default:
 451                         ret_val = e1000e_get_phy_id(hw);
 452                         if (ret_val)
 453                                 return ret_val;
 454                         if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
 455                                 break;
 456                         /* fall-through */
 457                 case e1000_pch2lan:
 458                 case e1000_pch_lpt:
 459                 case e1000_pch_spt:
 460                 case e1000_pch_cnp:
 461                         /* In case the PHY needs to be in mdio slow mode,
 462                          * set slow mode and try to get the PHY id again.
 463                          */
 464                         ret_val = e1000_set_mdio_slow_mode_hv(hw);
 465                         if (ret_val)
 466                                 return ret_val;
 467                         ret_val = e1000e_get_phy_id(hw);
 468                         if (ret_val)
 469                                 return ret_val;
 470                         break;
 471                 }
 472         phy->type = e1000e_get_phy_type_from_id(phy->id);
 473
 474         switch (phy->type) {
 475         case e1000_phy_82577:
 476         case e1000_phy_82579:
 477         case e1000_phy_i217:
 478                 phy->ops.check_polarity = e1000_check_polarity_82577;
 479                 phy->ops.force_speed_duplex =
 480                     e1000_phy_force_speed_duplex_82577;
 481                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 482                 phy->ops.get_info = e1000_get_phy_info_82577;
 483                 phy->ops.commit = e1000e_phy_sw_reset;
 484                 break;
 485         case e1000_phy_82578:
 486                 phy->ops.check_polarity = e1000_check_polarity_m88;
 487                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 488                 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
 489                 phy->ops.get_info = e1000e_get_phy_info_m88;
 490                 break;
 491         default:
 492                 ret_val = -E1000_ERR_PHY;
 493                 break;
 494         }
 495
 496         return ret_val;
 497 }
 498
 499 /**
 500  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 501  *  @hw: pointer to the HW structure
 502  *
 503  *  Initialize family-specific PHY parameters and function pointers.
 504  **/
 505 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 506 {
 507         struct e1000_phy_info *phy = &hw->phy;
 508         s32 ret_val;
 509         u16 i = 0;
 510
 511         phy->addr = 1;
 512         phy->reset_delay_us = 100;
 513
 514         phy->ops.power_up = e1000_power_up_phy_copper;
 515         phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
 516
 517         /* We may need to do this twice - once for IGP and if that fails,
 518          * we'll set BM func pointers and try again
 519          */
 520         ret_val = e1000e_determine_phy_address(hw);
 521         if (ret_val) {
 522                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 523                 phy->ops.read_reg = e1000e_read_phy_reg_bm;
 524                 ret_val = e1000e_determine_phy_address(hw);
 525                 if (ret_val) {
 526                         e_dbg("Cannot determine PHY addr. Erroring out\n");
 527                         return ret_val;
 528                 }
 529         }
 530
 531         phy->id = 0;
 532         while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
 533                (i++ < 100)) {
 534                 usleep_range(1000, 2000);
 535                 ret_val = e1000e_get_phy_id(hw);
 536                 if (ret_val)
 537                         return ret_val;
 538         }
 539
 540         /* Verify phy id */
 541         switch (phy->id) {
 542         case IGP03E1000_E_PHY_ID:
 543                 phy->type = e1000_phy_igp_3;
 544                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 545                 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
 546                 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
 547                 phy->ops.get_info = e1000e_get_phy_info_igp;
 548                 phy->ops.check_polarity = e1000_check_polarity_igp;
 549                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
 550                 break;
 551         case IFE_E_PHY_ID:
 552         case IFE_PLUS_E_PHY_ID:
 553         case IFE_C_E_PHY_ID:
 554                 phy->type = e1000_phy_ife;
 555                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 556                 phy->ops.get_info = e1000_get_phy_info_ife;
 557                 phy->ops.check_polarity = e1000_check_polarity_ife;
 558                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
 559                 break;
 560         case BME1000_E_PHY_ID:
 561                 phy->type = e1000_phy_bm;
 562                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 563                 phy->ops.read_reg = e1000e_read_phy_reg_bm;
 564                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 565                 phy->ops.commit = e1000e_phy_sw_reset;
 566                 phy->ops.get_info = e1000e_get_phy_info_m88;
 567                 phy->ops.check_polarity = e1000_check_polarity_m88;
 568                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 569                 break;
 570         default:
 571                 return -E1000_ERR_PHY;
 572         }
 573
 574         return 0;
 575 }
 576
 577 /**
 578  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 579  *  @hw: pointer to the HW structure
 580  *
 581  *  Initialize family-specific NVM parameters and function
 582  *  pointers.
 583  **/
 584 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 585 {
 586         struct e1000_nvm_info *nvm = &hw->nvm;
 587         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 588         u32 gfpreg, sector_base_addr, sector_end_addr;
 589         u16 i;
 590         u32 nvm_size;
 591
 592         nvm->type = e1000_nvm_flash_sw;
 593
 594         if (hw->mac.type >= e1000_pch_spt) {
 595                 /* in SPT, gfpreg doesn't exist. NVM size is taken from the
 596                  * STRAP register. This is because in SPT the GbE Flash region
 597                  * is no longer accessed through the flash registers. Instead,
 598                  * the mechanism has changed, and the Flash region access
 599                  * registers are now implemented in GbE memory space.
 600                  */
 601                 nvm->flash_base_addr = 0;
 602                 nvm_size = (((er32(STRAP) >> 1) & 0x1F) + 1)
 603                     * NVM_SIZE_MULTIPLIER;
 604                 nvm->flash_bank_size = nvm_size / 2;
 605                 /* Adjust to word count */
 606                 nvm->flash_bank_size /= sizeof(u16);
 607                 /* Set the base address for flash register access */
 608                 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR;
 609         } else {
 610                 /* Can't read flash registers if register set isn't mapped. */
 611                 if (!hw->flash_address) {
 612                         e_dbg("ERROR: Flash registers not mapped\n");
 613                         return -E1000_ERR_CONFIG;
 614                 }
 615
 616                 gfpreg = er32flash(ICH_FLASH_GFPREG);
 617
 618                 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
 619                  * Add 1 to sector_end_addr since this sector is included in
 620                  * the overall size.
 621                  */
 622                 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 623                 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 624
 625                 /* flash_base_addr is byte-aligned */
 626                 nvm->flash_base_addr = sector_base_addr
 627                     << FLASH_SECTOR_ADDR_SHIFT;
 628
 629                 /* find total size of the NVM, then cut in half since the total
 630                  * size represents two separate NVM banks.
 631                  */
 632                 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
 633                                         << FLASH_SECTOR_ADDR_SHIFT);
 634                 nvm->flash_bank_size /= 2;
 635                 /* Adjust to word count */
 636                 nvm->flash_bank_size /= sizeof(u16);
 637         }
 638
 639         nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
 640
 641         /* Clear shadow ram */
 642         for (i = 0; i < nvm->word_size; i++) {
 643                 dev_spec->shadow_ram[i].modified = false;
 644                 dev_spec->shadow_ram[i].value = 0xFFFF;
 645         }
 646
 647         return 0;
 648 }
 649
 650 /**
 651  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 652  *  @hw: pointer to the HW structure
 653  *
 654  *  Initialize family-specific MAC parameters and function
 655  *  pointers.
 656  **/
 657 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
 658 {
 659         struct e1000_mac_info *mac = &hw->mac;
 660
 661         /* Set media type function pointer */
 662         hw->phy.media_type = e1000_media_type_copper;
 663
 664         /* Set mta register count */
 665         mac->mta_reg_count = 32;
 666         /* Set rar entry count */
 667         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 668         if (mac->type == e1000_ich8lan)
 669                 mac->rar_entry_count--;
 670         /* FWSM register */
 671         mac->has_fwsm = true;
 672         /* ARC subsystem not supported */
 673         mac->arc_subsystem_valid = false;
 674         /* Adaptive IFS supported */
 675         mac->adaptive_ifs = true;
 676
 677         /* LED and other operations */
 678         switch (mac->type) {
 679         case e1000_ich8lan:
 680         case e1000_ich9lan:
 681         case e1000_ich10lan:
 682                 /* check management mode */
 683                 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
 684                 /* ID LED init */
 685                 mac->ops.id_led_init = e1000e_id_led_init_generic;
 686                 /* blink LED */
 687                 mac->ops.blink_led = e1000e_blink_led_generic;
 688                 /* setup LED */
 689                 mac->ops.setup_led = e1000e_setup_led_generic;
 690                 /* cleanup LED */
 691                 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
 692                 /* turn on/off LED */
 693                 mac->ops.led_on = e1000_led_on_ich8lan;
 694                 mac->ops.led_off = e1000_led_off_ich8lan;
 695                 break;
 696         case e1000_pch2lan:
 697                 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
 698                 mac->ops.rar_set = e1000_rar_set_pch2lan;
 699                 /* fall-through */
 700         case e1000_pch_lpt:
 701         case e1000_pch_spt:
 702         case e1000_pch_cnp:
 703         case e1000_pchlan:
 704                 /* check management mode */
 705                 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
 706                 /* ID LED init */
 707                 mac->ops.id_led_init = e1000_id_led_init_pchlan;
 708                 /* setup LED */
 709                 mac->ops.setup_led = e1000_setup_led_pchlan;
 710                 /* cleanup LED */
 711                 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
 712                 /* turn on/off LED */
 713                 mac->ops.led_on = e1000_led_on_pchlan;
 714                 mac->ops.led_off = e1000_led_off_pchlan;
 715                 break;
 716         default:
 717                 break;
 718         }
 719
 720         if (mac->type >= e1000_pch_lpt) {
 721                 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
 722                 mac->ops.rar_set = e1000_rar_set_pch_lpt;
 723                 mac->ops.setup_physical_interface =
 724                     e1000_setup_copper_link_pch_lpt;
 725                 mac->ops.rar_get_count = e1000_rar_get_count_pch_lpt;
 726         }
 727
 728         /* Enable PCS Lock-loss workaround for ICH8 */
 729         if (mac->type == e1000_ich8lan)
 730                 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
 731
 732         return 0;
 733 }
 734
 735 /**
 736  *  __e1000_access_emi_reg_locked - Read/write EMI register
 737  *  @hw: pointer to the HW structure
 738  *  @addr: EMI address to program
 739  *  @data: pointer to value to read/write from/to the EMI address
 740  *  @read: boolean flag to indicate read or write
 741  *
 742  *  This helper function assumes the SW/FW/HW Semaphore is already acquired.
 743  **/
 744 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
 745                                          u16 *data, bool read)
 746 {
 747         s32 ret_val;
 748
 749         ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address);
 750         if (ret_val)
 751                 return ret_val;
 752
 753         if (read)
 754                 ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data);
 755         else
 756                 ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data);
 757
 758         return ret_val;
 759 }
 760
 761 /**
 762  *  e1000_read_emi_reg_locked - Read Extended Management Interface register
 763  *  @hw: pointer to the HW structure
 764  *  @addr: EMI address to program
 765  *  @data: value to be read from the EMI address
 766  *
 767  *  Assumes the SW/FW/HW Semaphore is already acquired.
 768  **/
 769 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
 770 {
 771         return __e1000_access_emi_reg_locked(hw, addr, data, true);
 772 }
 773
 774 /**
 775  *  e1000_write_emi_reg_locked - Write Extended Management Interface register
 776  *  @hw: pointer to the HW structure
 777  *  @addr: EMI address to program
 778  *  @data: value to be written to the EMI address
 779  *
 780  *  Assumes the SW/FW/HW Semaphore is already acquired.
 781  **/
 782 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
 783 {
 784         return __e1000_access_emi_reg_locked(hw, addr, &data, false);
 785 }
 786
 787 /**
 788  *  e1000_set_eee_pchlan - Enable/disable EEE support
 789  *  @hw: pointer to the HW structure
 790  *
 791  *  Enable/disable EEE based on setting in dev_spec structure, the duplex of
 792  *  the link and the EEE capabilities of the link partner.  The LPI Control
 793  *  register bits will remain set only if/when link is up.
 794  *
 795  *  EEE LPI must not be asserted earlier than one second after link is up.
 796  *  On 82579, EEE LPI should not be enabled until such time otherwise there
 797  *  can be link issues with some switches.  Other devices can have EEE LPI
 798  *  enabled immediately upon link up since they have a timer in hardware which
 799  *  prevents LPI from being asserted too early.
 800  **/
 801 s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
 802 {
 803         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 804         s32 ret_val;
 805         u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
 806
 807         switch (hw->phy.type) {
 808         case e1000_phy_82579:
 809                 lpa = I82579_EEE_LP_ABILITY;
 810                 pcs_status = I82579_EEE_PCS_STATUS;
 811                 adv_addr = I82579_EEE_ADVERTISEMENT;
 812                 break;
 813         case e1000_phy_i217:
 814                 lpa = I217_EEE_LP_ABILITY;
 815                 pcs_status = I217_EEE_PCS_STATUS;
 816                 adv_addr = I217_EEE_ADVERTISEMENT;
 817                 break;
 818         default:
 819                 return 0;
 820         }
 821
 822         ret_val = hw->phy.ops.acquire(hw);
 823         if (ret_val)
 824                 return ret_val;
 825
 826         ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
 827         if (ret_val)
 828                 goto release;
 829
 830         /* Clear bits that enable EEE in various speeds */
 831         lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
 832
 833         /* Enable EEE if not disabled by user */
 834         if (!dev_spec->eee_disable) {
 835                 /* Save off link partner's EEE ability */
 836                 ret_val = e1000_read_emi_reg_locked(hw, lpa,
 837                                                     &dev_spec->eee_lp_ability);
 838                 if (ret_val)
 839                         goto release;
 840
 841                 /* Read EEE advertisement */
 842                 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
 843                 if (ret_val)
 844                         goto release;
 845
 846                 /* Enable EEE only for speeds in which the link partner is
 847                  * EEE capable and for which we advertise EEE.
 848                  */
 849                 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
 850                         lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
 851
 852                 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
 853                         e1e_rphy_locked(hw, MII_LPA, &data);
 854                         if (data & LPA_100FULL)
 855                                 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
 856                         else
 857                                 /* EEE is not supported in 100Half, so ignore
 858                                  * partner's EEE in 100 ability if full-duplex
 859                                  * is not advertised.
 860                                  */
 861                                 dev_spec->eee_lp_ability &=
 862                                     ~I82579_EEE_100_SUPPORTED;
 863                 }
 864         }
 865
 866         if (hw->phy.type == e1000_phy_82579) {
 867                 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
 868                                                     &data);
 869                 if (ret_val)
 870                         goto release;
 871
 872                 data &= ~I82579_LPI_100_PLL_SHUT;
 873                 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
 874                                                      data);
 875         }
 876
 877         /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
 878         ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
 879         if (ret_val)
 880                 goto release;
 881
 882         ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
 883 release:
 884         hw->phy.ops.release(hw);
 885
 886         return ret_val;
 887 }
 888
 889 /**
 890  *  e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
 891  *  @hw:   pointer to the HW structure
 892  *  @link: link up bool flag
 893  *
 894  *  When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
 895  *  preventing further DMA write requests.  Workaround the issue by disabling
 896  *  the de-assertion of the clock request when in 1Gpbs mode.
 897  *  Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
 898  *  speeds in order to avoid Tx hangs.
 899  **/
 900 static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
 901 {
 902         u32 fextnvm6 = er32(FEXTNVM6);
 903         u32 status = er32(STATUS);
 904         s32 ret_val = 0;
 905         u16 reg;
 906
 907         if (link && (status & E1000_STATUS_SPEED_1000)) {
 908                 ret_val = hw->phy.ops.acquire(hw);
 909                 if (ret_val)
 910                         return ret_val;
 911
 912                 ret_val =
 913                     e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
 914                                                 &reg);
 915                 if (ret_val)
 916                         goto release;
 917
 918                 ret_val =
 919                     e1000e_write_kmrn_reg_locked(hw,
 920                                                  E1000_KMRNCTRLSTA_K1_CONFIG,
 921                                                  reg &
 922                                                  ~E1000_KMRNCTRLSTA_K1_ENABLE);
 923                 if (ret_val)
 924                         goto release;
 925
 926                 usleep_range(10, 20);
 927
 928                 ew32(FEXTNVM6, fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
 929
 930                 ret_val =
 931                     e1000e_write_kmrn_reg_locked(hw,
 932                                                  E1000_KMRNCTRLSTA_K1_CONFIG,
 933                                                  reg);
 934 release:
 935                 hw->phy.ops.release(hw);
 936         } else {
 937                 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
 938                 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
 939
 940                 if ((hw->phy.revision > 5) || !link ||
 941                     ((status & E1000_STATUS_SPEED_100) &&
 942                      (status & E1000_STATUS_FD)))
 943                         goto update_fextnvm6;
 944
 945                 ret_val = e1e_rphy(hw, I217_INBAND_CTRL, &reg);
 946                 if (ret_val)
 947                         return ret_val;
 948
 949                 /* Clear link status transmit timeout */
 950                 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
 951
 952                 if (status & E1000_STATUS_SPEED_100) {
 953                         /* Set inband Tx timeout to 5x10us for 100Half */
 954                         reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
 955
 956                         /* Do not extend the K1 entry latency for 100Half */
 957                         fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
 958                 } else {
 959                         /* Set inband Tx timeout to 50x10us for 10Full/Half */
 960                         reg |= 50 <<
 961                             I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
 962
 963                         /* Extend the K1 entry latency for 10 Mbps */
 964                         fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
 965                 }
 966
 967                 ret_val = e1e_wphy(hw, I217_INBAND_CTRL, reg);
 968                 if (ret_val)
 969                         return ret_val;
 970
 971 update_fextnvm6:
 972                 ew32(FEXTNVM6, fextnvm6);
 973         }
 974
 975         return ret_val;
 976 }
 977
 978 /**
 979  *  e1000_platform_pm_pch_lpt - Set platform power management values
 980  *  @hw: pointer to the HW structure
 981  *  @link: bool indicating link status
 982  *
 983  *  Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like"
 984  *  GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed
 985  *  when link is up (which must not exceed the maximum latency supported
 986  *  by the platform), otherwise specify there is no LTR requirement.
 987  *  Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop
 988  *  latencies in the LTR Extended Capability Structure in the PCIe Extended
 989  *  Capability register set, on this device LTR is set by writing the
 990  *  equivalent snoop/no-snoop latencies in the LTRV register in the MAC and
 991  *  set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB)
 992  *  message to the PMC.
 993  **/
 994 static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)
 995 {
 996         u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) |
 997             link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND;
 998         u16 lat_enc = 0;        /* latency encoded */
 999
1000         if (link) {
1001                 u16 speed, duplex, scale = 0;
1002                 u16 max_snoop, max_nosnoop;
1003                 u16 max_ltr_enc;        /* max LTR latency encoded */
1004                 u64 value;
1005                 u32 rxa;
1006
1007                 if (!hw->adapter->max_frame_size) {
1008                         e_dbg("max_frame_size not set.\n");
1009                         return -E1000_ERR_CONFIG;
1010                 }
1011
1012                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1013                 if (!speed) {
1014                         e_dbg("Speed not set.\n");
1015                         return -E1000_ERR_CONFIG;
1016                 }
1017
1018                 /* Rx Packet Buffer Allocation size (KB) */
1019                 rxa = er32(PBA) & E1000_PBA_RXA_MASK;
1020
1021                 /* Determine the maximum latency tolerated by the device.
1022                  *
1023                  * Per the PCIe spec, the tolerated latencies are encoded as
1024                  * a 3-bit encoded scale (only 0-5 are valid) multiplied by
1025                  * a 10-bit value (0-1023) to provide a range from 1 ns to
1026                  * 2^25*(2^10-1) ns.  The scale is encoded as 0=2^0ns,
1027                  * 1=2^5ns, 2=2^10ns,...5=2^25ns.
1028                  */
1029                 rxa *= 512;
1030                 value = (rxa > hw->adapter->max_frame_size) ?
1031                         (rxa - hw->adapter->max_frame_size) * (16000 / speed) :
1032                         0;
1033
1034                 while (value > PCI_LTR_VALUE_MASK) {
1035                         scale++;
1036                         value = DIV_ROUND_UP(value, BIT(5));
1037                 }
1038                 if (scale > E1000_LTRV_SCALE_MAX) {
1039                         e_dbg("Invalid LTR latency scale %d\n", scale);
1040                         return -E1000_ERR_CONFIG;
1041                 }
1042                 lat_enc = (u16)((scale << PCI_LTR_SCALE_SHIFT) | value);
1043
1044                 /* Determine the maximum latency tolerated by the platform */
1045                 pci_read_config_word(hw->adapter->pdev, E1000_PCI_LTR_CAP_LPT,
1046                                      &max_snoop);
1047                 pci_read_config_word(hw->adapter->pdev,
1048                                      E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop);
1049                 max_ltr_enc = max_t(u16, max_snoop, max_nosnoop);
1050
1051                 if (lat_enc > max_ltr_enc)
1052                         lat_enc = max_ltr_enc;
1053         }
1054
1055         /* Set Snoop and No-Snoop latencies the same */
1056         reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT);
1057         ew32(LTRV, reg);
1058
1059         return 0;
1060 }
1061
1062 /**
1063  *  e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1064  *  @hw: pointer to the HW structure
1065  *  @to_sx: boolean indicating a system power state transition to Sx
1066  *
1067  *  When link is down, configure ULP mode to significantly reduce the power
1068  *  to the PHY.  If on a Manageability Engine (ME) enabled system, tell the
1069  *  ME firmware to start the ULP configuration.  If not on an ME enabled
1070  *  system, configure the ULP mode by software.
1071  */
1072 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1073 {
1074         u32 mac_reg;
1075         s32 ret_val = 0;
1076         u16 phy_reg;
1077         u16 oem_reg = 0;
1078
1079         if ((hw->mac.type < e1000_pch_lpt) ||
1080             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1081             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) ||
1082             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) ||
1083             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) ||
1084             (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1085                 return 0;
1086
1087         if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
1088                 /* Request ME configure ULP mode in the PHY */
1089                 mac_reg = er32(H2ME);
1090                 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
1091                 ew32(H2ME, mac_reg);
1092
1093                 goto out;
1094         }
1095
1096         if (!to_sx) {
1097                 int i = 0;
1098
1099                 /* Poll up to 5 seconds for Cable Disconnected indication */
1100                 while (!(er32(FEXT) & E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
1101                         /* Bail if link is re-acquired */
1102                         if (er32(STATUS) & E1000_STATUS_LU)
1103                                 return -E1000_ERR_PHY;
1104
1105                         if (i++ == 100)
1106                                 break;
1107
1108                         msleep(50);
1109                 }
1110                 e_dbg("CABLE_DISCONNECTED %s set after %dmsec\n",
1111                       (er32(FEXT) &
1112                        E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not", i * 50);
1113         }
1114
1115         ret_val = hw->phy.ops.acquire(hw);
1116         if (ret_val)
1117                 goto out;
1118
1119         /* Force SMBus mode in PHY */
1120         ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1121         if (ret_val)
1122                 goto release;
1123         phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1124         e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1125
1126         /* Force SMBus mode in MAC */
1127         mac_reg = er32(CTRL_EXT);
1128         mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1129         ew32(CTRL_EXT, mac_reg);
1130
1131         /* Si workaround for ULP entry flow on i127/rev6 h/w.  Enable
1132          * LPLU and disable Gig speed when entering ULP
1133          */
1134         if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) {
1135                 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS,
1136                                                        &oem_reg);
1137                 if (ret_val)
1138                         goto release;
1139
1140                 phy_reg = oem_reg;
1141                 phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS;
1142
1143                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1144                                                         phy_reg);
1145
1146                 if (ret_val)
1147                         goto release;
1148         }
1149
1150         /* Set Inband ULP Exit, Reset to SMBus mode and
1151          * Disable SMBus Release on PERST# in PHY
1152          */
1153         ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1154         if (ret_val)
1155                 goto release;
1156         phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1157                     I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1158         if (to_sx) {
1159                 if (er32(WUFC) & E1000_WUFC_LNKC)
1160                         phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1161                 else
1162                         phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1163
1164                 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1165                 phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT;
1166         } else {
1167                 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1168                 phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP;
1169                 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1170         }
1171         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1172
1173         /* Set Disable SMBus Release on PERST# in MAC */
1174         mac_reg = er32(FEXTNVM7);
1175         mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1176         ew32(FEXTNVM7, mac_reg);
1177
1178         /* Commit ULP changes in PHY by starting auto ULP configuration */
1179         phy_reg |= I218_ULP_CONFIG1_START;
1180         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1181
1182         if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) &&
1183             to_sx && (er32(STATUS) & E1000_STATUS_LU)) {
1184                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1185                                                         oem_reg);
1186                 if (ret_val)
1187                         goto release;
1188         }
1189
1190 release:
1191         hw->phy.ops.release(hw);
1192 out:
1193         if (ret_val)
1194                 e_dbg("Error in ULP enable flow: %d\n", ret_val);
1195         else
1196                 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1197
1198         return ret_val;
1199 }
1200
1201 /**
1202  *  e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1203  *  @hw: pointer to the HW structure
1204  *  @force: boolean indicating whether or not to force disabling ULP
1205  *
1206  *  Un-configure ULP mode when link is up, the system is transitioned from
1207  *  Sx or the driver is unloaded.  If on a Manageability Engine (ME) enabled
1208  *  system, poll for an indication from ME that ULP has been un-configured.
1209  *  If not on an ME enabled system, un-configure the ULP mode by software.
1210  *
1211  *  During nominal operation, this function is called when link is acquired
1212  *  to disable ULP mode (force=false); otherwise, for example when unloading
1213  *  the driver or during Sx->S0 transitions, this is called with force=true
1214  *  to forcibly disable ULP.
1215  */
1216 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1217 {
1218         s32 ret_val = 0;
1219         u32 mac_reg;
1220         u16 phy_reg;
1221         int i = 0;
1222
1223         if ((hw->mac.type < e1000_pch_lpt) ||
1224             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1225             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) ||
1226             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) ||
1227             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) ||
1228             (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
1229                 return 0;
1230
1231         if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
1232                 if (force) {
1233                         /* Request ME un-configure ULP mode in the PHY */
1234                         mac_reg = er32(H2ME);
1235                         mac_reg &= ~E1000_H2ME_ULP;
1236                         mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1237                         ew32(H2ME, mac_reg);
1238                 }
1239
1240                 /* Poll up to 300msec for ME to clear ULP_CFG_DONE. */
1241                 while (er32(FWSM) & E1000_FWSM_ULP_CFG_DONE) {
1242                         if (i++ == 30) {
1243                                 ret_val = -E1000_ERR_PHY;
1244                                 goto out;
1245                         }
1246
1247                         usleep_range(10000, 20000);
1248                 }
1249                 e_dbg("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
1250
1251                 if (force) {
1252                         mac_reg = er32(H2ME);
1253                         mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
1254                         ew32(H2ME, mac_reg);
1255                 } else {
1256                         /* Clear H2ME.ULP after ME ULP configuration */
1257                         mac_reg = er32(H2ME);
1258                         mac_reg &= ~E1000_H2ME_ULP;
1259                         ew32(H2ME, mac_reg);
1260                 }
1261
1262                 goto out;
1263         }
1264
1265         ret_val = hw->phy.ops.acquire(hw);
1266         if (ret_val)
1267                 goto out;
1268
1269         if (force)
1270                 /* Toggle LANPHYPC Value bit */
1271                 e1000_toggle_lanphypc_pch_lpt(hw);
1272
1273         /* Unforce SMBus mode in PHY */
1274         ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1275         if (ret_val) {
1276                 /* The MAC might be in PCIe mode, so temporarily force to
1277                  * SMBus mode in order to access the PHY.
1278                  */
1279                 mac_reg = er32(CTRL_EXT);
1280                 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1281                 ew32(CTRL_EXT, mac_reg);
1282
1283                 msleep(50);
1284
1285                 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1286                                                        &phy_reg);
1287                 if (ret_val)
1288                         goto release;
1289         }
1290         phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1291         e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1292
1293         /* Unforce SMBus mode in MAC */
1294         mac_reg = er32(CTRL_EXT);
1295         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
1296         ew32(CTRL_EXT, mac_reg);
1297
1298         /* When ULP mode was previously entered, K1 was disabled by the
1299          * hardware.  Re-Enable K1 in the PHY when exiting ULP.
1300          */
1301         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1302         if (ret_val)
1303                 goto release;
1304         phy_reg |= HV_PM_CTRL_K1_ENABLE;
1305         e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
1306
1307         /* Clear ULP enabled configuration */
1308         ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1309         if (ret_val)
1310                 goto release;
1311         phy_reg &= ~(I218_ULP_CONFIG1_IND |
1312                      I218_ULP_CONFIG1_STICKY_ULP |
1313                      I218_ULP_CONFIG1_RESET_TO_SMBUS |
1314                      I218_ULP_CONFIG1_WOL_HOST |
1315                      I218_ULP_CONFIG1_INBAND_EXIT |
1316                      I218_ULP_CONFIG1_EN_ULP_LANPHYPC |
1317                      I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST |
1318                      I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1319         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1320
1321         /* Commit ULP changes by starting auto ULP configuration */
1322         phy_reg |= I218_ULP_CONFIG1_START;
1323         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1324
1325         /* Clear Disable SMBus Release on PERST# in MAC */
1326         mac_reg = er32(FEXTNVM7);
1327         mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
1328         ew32(FEXTNVM7, mac_reg);
1329
1330 release:
1331         hw->phy.ops.release(hw);
1332         if (force) {
1333                 e1000_phy_hw_reset(hw);
1334                 msleep(50);
1335         }
1336 out:
1337         if (ret_val)
1338                 e_dbg("Error in ULP disable flow: %d\n", ret_val);
1339         else
1340                 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
1341
1342         return ret_val;
1343 }
1344
1345 /**
1346  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1347  *  @hw: pointer to the HW structure
1348  *
1349  *  Checks to see of the link status of the hardware has changed.  If a
1350  *  change in link status has been detected, then we read the PHY registers
1351  *  to get the current speed/duplex if link exists.
1352  **/
1353 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1354 {
1355         struct e1000_mac_info *mac = &hw->mac;
1356         s32 ret_val, tipg_reg = 0;
1357         u16 emi_addr, emi_val = 0;
1358         bool link;
1359         u16 phy_reg;
1360
1361         /* We only want to go out to the PHY registers to see if Auto-Neg
1362          * has completed and/or if our link status has changed.  The
1363          * get_link_status flag is set upon receiving a Link Status
1364          * Change or Rx Sequence Error interrupt.
1365          */
1366         if (!mac->get_link_status)
1367                 return 0;
1368         mac->get_link_status = false;
1369
1370         /* First we want to see if the MII Status Register reports
1371          * link.  If so, then we want to get the current speed/duplex
1372          * of the PHY.
1373          */
1374         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1375         if (ret_val)
1376                 goto out;
1377
1378         if (hw->mac.type == e1000_pchlan) {
1379                 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1380                 if (ret_val)
1381                         goto out;
1382         }
1383
1384         /* When connected at 10Mbps half-duplex, some parts are excessively
1385          * aggressive resulting in many collisions. To avoid this, increase
1386          * the IPG and reduce Rx latency in the PHY.
1387          */
1388         if ((hw->mac.type >= e1000_pch2lan) && link) {
1389                 u16 speed, duplex;
1390
1391                 e1000e_get_speed_and_duplex_copper(hw, &speed, &duplex);
1392                 tipg_reg = er32(TIPG);
1393                 tipg_reg &= ~E1000_TIPG_IPGT_MASK;
1394
1395                 if (duplex == HALF_DUPLEX && speed == SPEED_10) {
1396                         tipg_reg |= 0xFF;
1397                         /* Reduce Rx latency in analog PHY */
1398                         emi_val = 0;
1399                 } else if (hw->mac.type >= e1000_pch_spt &&
1400                            duplex == FULL_DUPLEX && speed != SPEED_1000) {
1401                         tipg_reg |= 0xC;
1402                         emi_val = 1;
1403                 } else {
1404
1405                         /* Roll back the default values */
1406                         tipg_reg |= 0x08;
1407                         emi_val = 1;
1408                 }
1409
1410                 ew32(TIPG, tipg_reg);
1411
1412                 ret_val = hw->phy.ops.acquire(hw);
1413                 if (ret_val)
1414                         goto out;
1415
1416                 if (hw->mac.type == e1000_pch2lan)
1417                         emi_addr = I82579_RX_CONFIG;
1418                 else
1419                         emi_addr = I217_RX_CONFIG;
1420                 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val);
1421
1422                 if (hw->mac.type >= e1000_pch_lpt) {
1423                         u16 phy_reg;
1424
1425                         e1e_rphy_locked(hw, I217_PLL_CLOCK_GATE_REG, &phy_reg);
1426                         phy_reg &= ~I217_PLL_CLOCK_GATE_MASK;
1427                         if (speed == SPEED_100 || speed == SPEED_10)
1428                                 phy_reg |= 0x3E8;
1429                         else
1430                                 phy_reg |= 0xFA;
1431                         e1e_wphy_locked(hw, I217_PLL_CLOCK_GATE_REG, phy_reg);
1432                 }
1433                 hw->phy.ops.release(hw);
1434
1435                 if (ret_val)
1436                         goto out;
1437
1438                 if (hw->mac.type >= e1000_pch_spt) {
1439                         u16 data;
1440                         u16 ptr_gap;
1441
1442                         if (speed == SPEED_1000) {
1443                                 ret_val = hw->phy.ops.acquire(hw);
1444                                 if (ret_val)
1445                                         goto out;
1446
1447                                 ret_val = e1e_rphy_locked(hw,
1448                                                           PHY_REG(776, 20),
1449                                                           &data);
1450                                 if (ret_val) {
1451                                         hw->phy.ops.release(hw);
1452                                         goto out;
1453                                 }
1454
1455                                 ptr_gap = (data & (0x3FF << 2)) >> 2;
1456                                 if (ptr_gap < 0x18) {
1457                                         data &= ~(0x3FF << 2);
1458                                         data |= (0x18 << 2);
1459                                         ret_val =
1460                                             e1e_wphy_locked(hw,
1461                                                             PHY_REG(776, 20),
1462                                                             data);
1463                                 }
1464                                 hw->phy.ops.release(hw);
1465                                 if (ret_val)
1466                                         goto out;
1467                         } else {
1468                                 ret_val = hw->phy.ops.acquire(hw);
1469                                 if (ret_val)
1470                                         goto out;
1471
1472                                 ret_val = e1e_wphy_locked(hw,
1473                                                           PHY_REG(776, 20),
1474                                                           0xC023);
1475                                 hw->phy.ops.release(hw);
1476                                 if (ret_val)
1477                                         goto out;
1478
1479                         }
1480                 }
1481         }
1482
1483         /* I217 Packet Loss issue:
1484          * ensure that FEXTNVM4 Beacon Duration is set correctly
1485          * on power up.
1486          * Set the Beacon Duration for I217 to 8 usec
1487          */
1488         if (hw->mac.type >= e1000_pch_lpt) {
1489                 u32 mac_reg;
1490
1491                 mac_reg = er32(FEXTNVM4);
1492                 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1493                 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1494                 ew32(FEXTNVM4, mac_reg);
1495         }
1496
1497         /* Work-around I218 hang issue */
1498         if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1499             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1500             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM3) ||
1501             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V3)) {
1502                 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1503                 if (ret_val)
1504                         goto out;
1505         }
1506         if (hw->mac.type >= e1000_pch_lpt) {
1507                 /* Set platform power management values for
1508                  * Latency Tolerance Reporting (LTR)
1509                  */
1510                 ret_val = e1000_platform_pm_pch_lpt(hw, link);
1511                 if (ret_val)
1512                         goto out;
1513         }
1514
1515         /* Clear link partner's EEE ability */
1516         hw->dev_spec.ich8lan.eee_lp_ability = 0;
1517
1518         if (hw->mac.type >= e1000_pch_lpt) {
1519                 u32 fextnvm6 = er32(FEXTNVM6);
1520
1521                 if (hw->mac.type == e1000_pch_spt) {
1522                         /* FEXTNVM6 K1-off workaround - for SPT only */
1523                         u32 pcieanacfg = er32(PCIEANACFG);
1524
1525                         if (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE)
1526                                 fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE;
1527                         else
1528                                 fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
1529                 }
1530
1531                 ew32(FEXTNVM6, fextnvm6);
1532         }
1533
1534         if (!link)
1535                 goto out;
1536
1537         switch (hw->mac.type) {
1538         case e1000_pch2lan:
1539                 ret_val = e1000_k1_workaround_lv(hw);
1540                 if (ret_val)
1541                         return ret_val;
1542                 /* fall-thru */
1543         case e1000_pchlan:
1544                 if (hw->phy.type == e1000_phy_82578) {
1545                         ret_val = e1000_link_stall_workaround_hv(hw);
1546                         if (ret_val)
1547                                 return ret_val;
1548                 }
1549
1550                 /* Workaround for PCHx parts in half-duplex:
1551                  * Set the number of preambles removed from the packet
1552                  * when it is passed from the PHY to the MAC to prevent
1553                  * the MAC from misinterpreting the packet type.
1554                  */
1555                 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1556                 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1557
1558                 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD)
1559                         phy_reg |= BIT(HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1560
1561                 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1562                 break;
1563         default:
1564                 break;
1565         }
1566
1567         /* Check if there was DownShift, must be checked
1568          * immediately after link-up
1569          */
1570         e1000e_check_downshift(hw);
1571
1572         /* Enable/Disable EEE after link up */
1573         if (hw->phy.type > e1000_phy_82579) {
1574                 ret_val = e1000_set_eee_pchlan(hw);
1575                 if (ret_val)
1576                         return ret_val;
1577         }
1578
1579         /* If we are forcing speed/duplex, then we simply return since
1580          * we have already determined whether we have link or not.
1581          */
1582         if (!mac->autoneg)
1583                 return -E1000_ERR_CONFIG;
1584
1585         /* Auto-Neg is enabled.  Auto Speed Detection takes care
1586          * of MAC speed/duplex configuration.  So we only need to
1587          * configure Collision Distance in the MAC.
1588          */
1589         mac->ops.config_collision_dist(hw);
1590
1591         /* Configure Flow Control now that Auto-Neg has completed.
1592          * First, we need to restore the desired flow control
1593          * settings because we may have had to re-autoneg with a
1594          * different link partner.
1595          */
1596         ret_val = e1000e_config_fc_after_link_up(hw);
1597         if (ret_val)
1598                 e_dbg("Error configuring flow control\n");
1599
1600         return ret_val;
1601
1602 out:
1603         mac->get_link_status = true;
1604         return ret_val;
1605 }
1606
1607 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
1608 {
1609         struct e1000_hw *hw = &adapter->hw;
1610         s32 rc;
1611
1612         rc = e1000_init_mac_params_ich8lan(hw);
1613         if (rc)
1614                 return rc;
1615
1616         rc = e1000_init_nvm_params_ich8lan(hw);
1617         if (rc)
1618                 return rc;
1619
1620         switch (hw->mac.type) {
1621         case e1000_ich8lan:
1622         case e1000_ich9lan:
1623         case e1000_ich10lan:
1624                 rc = e1000_init_phy_params_ich8lan(hw);
1625                 break;
1626         case e1000_pchlan:
1627         case e1000_pch2lan:
1628         case e1000_pch_lpt:
1629         case e1000_pch_spt:
1630         case e1000_pch_cnp:
1631                 rc = e1000_init_phy_params_pchlan(hw);
1632                 break;
1633         default:
1634                 break;
1635         }
1636         if (rc)
1637                 return rc;
1638
1639         /* Disable Jumbo Frame support on parts with Intel 10/100 PHY or
1640          * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
1641          */
1642         if ((adapter->hw.phy.type == e1000_phy_ife) ||
1643             ((adapter->hw.mac.type >= e1000_pch2lan) &&
1644              (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) {
1645                 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
1646                 adapter->max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
1647
1648                 hw->mac.ops.blink_led = NULL;
1649         }
1650
1651         if ((adapter->hw.mac.type == e1000_ich8lan) &&
1652             (adapter->hw.phy.type != e1000_phy_ife))
1653                 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
1654
1655         /* Enable workaround for 82579 w/ ME enabled */
1656         if ((adapter->hw.mac.type == e1000_pch2lan) &&
1657             (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
1658                 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA;
1659
1660         return 0;
1661 }
1662
1663 static DEFINE_MUTEX(nvm_mutex);
1664
1665 /**
1666  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1667  *  @hw: pointer to the HW structure
1668  *
1669  *  Acquires the mutex for performing NVM operations.
1670  **/
1671 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1672 {
1673         mutex_lock(&nvm_mutex);
1674
1675         return 0;
1676 }
1677
1678 /**
1679  *  e1000_release_nvm_ich8lan - Release NVM mutex
1680  *  @hw: pointer to the HW structure
1681  *
1682  *  Releases the mutex used while performing NVM operations.
1683  **/
1684 static void e1000_release_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1685 {
1686         mutex_unlock(&nvm_mutex);
1687 }
1688
1689 /**
1690  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
1691  *  @hw: pointer to the HW structure
1692  *
1693  *  Acquires the software control flag for performing PHY and select
1694  *  MAC CSR accesses.
1695  **/
1696 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1697 {
1698         u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1699         s32 ret_val = 0;
1700
1701         if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE,
1702                              &hw->adapter->state)) {
1703                 e_dbg("contention for Phy access\n");
1704                 return -E1000_ERR_PHY;
1705         }
1706
1707         while (timeout) {
1708                 extcnf_ctrl = er32(EXTCNF_CTRL);
1709                 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1710                         break;
1711
1712                 mdelay(1);
1713                 timeout--;
1714         }
1715
1716         if (!timeout) {
1717                 e_dbg("SW has already locked the resource.\n");
1718                 ret_val = -E1000_ERR_CONFIG;
1719                 goto out;
1720         }
1721
1722         timeout = SW_FLAG_TIMEOUT;
1723
1724         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1725         ew32(EXTCNF_CTRL, extcnf_ctrl);
1726
1727         while (timeout) {
1728                 extcnf_ctrl = er32(EXTCNF_CTRL);
1729                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1730                         break;
1731
1732                 mdelay(1);
1733                 timeout--;
1734         }
1735
1736         if (!timeout) {
1737                 e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1738                       er32(FWSM), extcnf_ctrl);
1739                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1740                 ew32(EXTCNF_CTRL, extcnf_ctrl);
1741                 ret_val = -E1000_ERR_CONFIG;
1742                 goto out;
1743         }
1744
1745 out:
1746         if (ret_val)
1747                 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1748
1749         return ret_val;
1750 }
1751
1752 /**
1753  *  e1000_release_swflag_ich8lan - Release software control flag
1754  *  @hw: pointer to the HW structure
1755  *
1756  *  Releases the software control flag for performing PHY and select
1757  *  MAC CSR accesses.
1758  **/
1759 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1760 {
1761         u32 extcnf_ctrl;
1762
1763         extcnf_ctrl = er32(EXTCNF_CTRL);
1764
1765         if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1766                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1767                 ew32(EXTCNF_CTRL, extcnf_ctrl);
1768         } else {
1769                 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");
1770         }
1771
1772         clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1773 }
1774
1775 /**
1776  *  e1000_check_mng_mode_ich8lan - Checks management mode
1777  *  @hw: pointer to the HW structure
1778  *
1779  *  This checks if the adapter has any manageability enabled.
1780  *  This is a function pointer entry point only called by read/write
1781  *  routines for the PHY and NVM parts.
1782  **/
1783 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1784 {
1785         u32 fwsm;
1786
1787         fwsm = er32(FWSM);
1788         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1789                 ((fwsm & E1000_FWSM_MODE_MASK) ==
1790                  (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1791 }
1792
1793 /**
1794  *  e1000_check_mng_mode_pchlan - Checks management mode
1795  *  @hw: pointer to the HW structure
1796  *
1797  *  This checks if the adapter has iAMT enabled.
1798  *  This is a function pointer entry point only called by read/write
1799  *  routines for the PHY and NVM parts.
1800  **/
1801 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1802 {
1803         u32 fwsm;
1804
1805         fwsm = er32(FWSM);
1806         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1807             (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1808 }
1809
1810 /**
1811  *  e1000_rar_set_pch2lan - Set receive address register
1812  *  @hw: pointer to the HW structure
1813  *  @addr: pointer to the receive address
1814  *  @index: receive address array register
1815  *
1816  *  Sets the receive address array register at index to the address passed
1817  *  in by addr.  For 82579, RAR[0] is the base address register that is to
1818  *  contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1819  *  Use SHRA[0-3] in place of those reserved for ME.
1820  **/
1821 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1822 {
1823         u32 rar_low, rar_high;
1824
1825         /* HW expects these in little endian so we reverse the byte order
1826          * from network order (big endian) to little endian
1827          */
1828         rar_low = ((u32)addr[0] |
1829                    ((u32)addr[1] << 8) |
1830                    ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1831
1832         rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1833
1834         /* If MAC address zero, no need to set the AV bit */
1835         if (rar_low || rar_high)
1836                 rar_high |= E1000_RAH_AV;
1837
1838         if (index == 0) {
1839                 ew32(RAL(index), rar_low);
1840                 e1e_flush();
1841                 ew32(RAH(index), rar_high);
1842                 e1e_flush();
1843                 return 0;
1844         }
1845
1846         /* RAR[1-6] are owned by manageability.  Skip those and program the
1847          * next address into the SHRA register array.
1848          */
1849         if (index < (u32)(hw->mac.rar_entry_count)) {
1850                 s32 ret_val;
1851
1852                 ret_val = e1000_acquire_swflag_ich8lan(hw);
1853                 if (ret_val)
1854                         goto out;
1855
1856                 ew32(SHRAL(index - 1), rar_low);
1857                 e1e_flush();
1858                 ew32(SHRAH(index - 1), rar_high);
1859                 e1e_flush();
1860
1861                 e1000_release_swflag_ich8lan(hw);
1862
1863                 /* verify the register updates */
1864                 if ((er32(SHRAL(index - 1)) == rar_low) &&
1865                     (er32(SHRAH(index - 1)) == rar_high))
1866                         return 0;
1867
1868                 e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1869                       (index - 1), er32(FWSM));
1870         }
1871
1872 out:
1873         e_dbg("Failed to write receive address at index %d\n", index);
1874         return -E1000_ERR_CONFIG;
1875 }
1876
1877 /**
1878  *  e1000_rar_get_count_pch_lpt - Get the number of available SHRA
1879  *  @hw: pointer to the HW structure
1880  *
1881  *  Get the number of available receive registers that the Host can
1882  *  program. SHRA[0-10] are the shared receive address registers
1883  *  that are shared between the Host and manageability engine (ME).
1884  *  ME can reserve any number of addresses and the host needs to be
1885  *  able to tell how many available registers it has access to.
1886  **/
1887 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw)
1888 {
1889         u32 wlock_mac;
1890         u32 num_entries;
1891
1892         wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
1893         wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1894
1895         switch (wlock_mac) {
1896         case 0:
1897                 /* All SHRA[0..10] and RAR[0] available */
1898                 num_entries = hw->mac.rar_entry_count;
1899                 break;
1900         case 1:
1901                 /* Only RAR[0] available */
1902                 num_entries = 1;
1903                 break;
1904         default:
1905                 /* SHRA[0..(wlock_mac - 1)] available + RAR[0] */
1906                 num_entries = wlock_mac + 1;
1907                 break;
1908         }
1909
1910         return num_entries;
1911 }
1912
1913 /**
1914  *  e1000_rar_set_pch_lpt - Set receive address registers
1915  *  @hw: pointer to the HW structure
1916  *  @addr: pointer to the receive address
1917  *  @index: receive address array register
1918  *
1919  *  Sets the receive address register array at index to the address passed
1920  *  in by addr. For LPT, RAR[0] is the base address register that is to
1921  *  contain the MAC address. SHRA[0-10] are the shared receive address
1922  *  registers that are shared between the Host and manageability engine (ME).
1923  **/
1924 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
1925 {
1926         u32 rar_low, rar_high;
1927         u32 wlock_mac;
1928
1929         /* HW expects these in little endian so we reverse the byte order
1930          * from network order (big endian) to little endian
1931          */
1932         rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
1933                    ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1934
1935         rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1936
1937         /* If MAC address zero, no need to set the AV bit */
1938         if (rar_low || rar_high)
1939                 rar_high |= E1000_RAH_AV;
1940
1941         if (index == 0) {
1942                 ew32(RAL(index), rar_low);
1943                 e1e_flush();
1944                 ew32(RAH(index), rar_high);
1945                 e1e_flush();
1946                 return 0;
1947         }
1948
1949         /* The manageability engine (ME) can lock certain SHRAR registers that
1950          * it is using - those registers are unavailable for use.
1951          */
1952         if (index < hw->mac.rar_entry_count) {
1953                 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
1954                 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1955
1956                 /* Check if all SHRAR registers are locked */
1957                 if (wlock_mac == 1)
1958                         goto out;
1959
1960                 if ((wlock_mac == 0) || (index <= wlock_mac)) {
1961                         s32 ret_val;
1962
1963                         ret_val = e1000_acquire_swflag_ich8lan(hw);
1964
1965                         if (ret_val)
1966                                 goto out;
1967
1968                         ew32(SHRAL_PCH_LPT(index - 1), rar_low);
1969                         e1e_flush();
1970                         ew32(SHRAH_PCH_LPT(index - 1), rar_high);
1971                         e1e_flush();
1972
1973                         e1000_release_swflag_ich8lan(hw);
1974
1975                         /* verify the register updates */
1976                         if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) &&
1977                             (er32(SHRAH_PCH_LPT(index - 1)) == rar_high))
1978                                 return 0;
1979                 }
1980         }
1981
1982 out:
1983         e_dbg("Failed to write receive address at index %d\n", index);
1984         return -E1000_ERR_CONFIG;
1985 }
1986
1987 /**
1988  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
1989  *  @hw: pointer to the HW structure
1990  *
1991  *  Checks if firmware is blocking the reset of the PHY.
1992  *  This is a function pointer entry point only called by
1993  *  reset routines.
1994  **/
1995 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
1996 {
1997         bool blocked = false;
1998         int i = 0;
1999
2000         while ((blocked = !(er32(FWSM) & E1000_ICH_FWSM_RSPCIPHY)) &&
2001                (i++ < 30))
2002                 usleep_range(10000, 20000);
2003         return blocked ? E1000_BLK_PHY_RESET : 0;
2004 }
2005
2006 /**
2007  *  e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
2008  *  @hw: pointer to the HW structure
2009  *
2010  *  Assumes semaphore already acquired.
2011  *
2012  **/
2013 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
2014 {
2015         u16 phy_data;
2016         u32 strap = er32(STRAP);
2017         u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
2018             E1000_STRAP_SMT_FREQ_SHIFT;
2019         s32 ret_val;
2020
2021         strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
2022
2023         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
2024         if (ret_val)
2025                 return ret_val;
2026
2027         phy_data &= ~HV_SMB_ADDR_MASK;
2028         phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
2029         phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
2030
2031         if (hw->phy.type == e1000_phy_i217) {
2032                 /* Restore SMBus frequency */
2033                 if (freq--) {
2034                         phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
2035                         phy_data |= (freq & BIT(0)) <<
2036                             HV_SMB_ADDR_FREQ_LOW_SHIFT;
2037                         phy_data |= (freq & BIT(1)) <<
2038                             (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
2039                 } else {
2040                         e_dbg("Unsupported SMB frequency in PHY\n");
2041                 }
2042         }
2043
2044         return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
2045 }
2046
2047 /**
2048  *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
2049  *  @hw:   pointer to the HW structure
2050  *
2051  *  SW should configure the LCD from the NVM extended configuration region
2052  *  as a workaround for certain parts.
2053  **/
2054 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
2055 {
2056         struct e1000_phy_info *phy = &hw->phy;
2057         u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
2058         s32 ret_val = 0;
2059         u16 word_addr, reg_data, reg_addr, phy_page = 0;
2060
2061         /* Initialize the PHY from the NVM on ICH platforms.  This
2062          * is needed due to an issue where the NVM configuration is
2063          * not properly autoloaded after power transitions.
2064          * Therefore, after each PHY reset, we will load the
2065          * configuration data out of the NVM manually.
2066          */
2067         switch (hw->mac.type) {
2068         case e1000_ich8lan:
2069                 if (phy->type != e1000_phy_igp_3)
2070                         return ret_val;
2071
2072                 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
2073                     (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
2074                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
2075                         break;
2076                 }
2077                 /* Fall-thru */
2078         case e1000_pchlan:
2079         case e1000_pch2lan:
2080         case e1000_pch_lpt:
2081         case e1000_pch_spt:
2082         case e1000_pch_cnp:
2083                 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
2084                 break;
2085         default:
2086                 return ret_val;
2087         }
2088
2089         ret_val = hw->phy.ops.acquire(hw);
2090         if (ret_val)
2091                 return ret_val;
2092
2093         data = er32(FEXTNVM);
2094         if (!(data & sw_cfg_mask))
2095                 goto release;
2096
2097         /* Make sure HW does not configure LCD from PHY
2098          * extended configuration before SW configuration
2099          */
2100         data = er32(EXTCNF_CTRL);
2101         if ((hw->mac.type < e1000_pch2lan) &&
2102             (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
2103                 goto release;
2104
2105         cnf_size = er32(EXTCNF_SIZE);
2106         cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
2107         cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
2108         if (!cnf_size)
2109                 goto release;
2110
2111         cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
2112         cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
2113
2114         if (((hw->mac.type == e1000_pchlan) &&
2115              !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
2116             (hw->mac.type > e1000_pchlan)) {
2117                 /* HW configures the SMBus address and LEDs when the
2118                  * OEM and LCD Write Enable bits are set in the NVM.
2119                  * When both NVM bits are cleared, SW will configure
2120                  * them instead.
2121                  */
2122                 ret_val = e1000_write_smbus_addr(hw);
2123                 if (ret_val)
2124                         goto release;
2125
2126                 data = er32(LEDCTL);
2127                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
2128                                                         (u16)data);
2129                 if (ret_val)
2130                         goto release;
2131         }
2132
2133         /* Configure LCD from extended configuration region. */
2134
2135         /* cnf_base_addr is in DWORD */
2136         word_addr = (u16)(cnf_base_addr << 1);
2137
2138         for (i = 0; i < cnf_size; i++) {
2139                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, &reg_data);
2140                 if (ret_val)
2141                         goto release;
2142
2143                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
2144                                          1, &reg_addr);
2145                 if (ret_val)
2146                         goto release;
2147
2148                 /* Save off the PHY page for future writes. */
2149                 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
2150                         phy_page = reg_data;
2151                         continue;
2152                 }
2153
2154                 reg_addr &= PHY_REG_MASK;
2155                 reg_addr |= phy_page;
2156
2157                 ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data);
2158                 if (ret_val)
2159                         goto release;
2160         }
2161
2162 release:
2163         hw->phy.ops.release(hw);
2164         return ret_val;
2165 }
2166
2167 /**
2168  *  e1000_k1_gig_workaround_hv - K1 Si workaround
2169  *  @hw:   pointer to the HW structure
2170  *  @link: link up bool flag
2171  *
2172  *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
2173  *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
2174  *  If link is down, the function will restore the default K1 setting located
2175  *  in the NVM.
2176  **/
2177 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
2178 {
2179         s32 ret_val = 0;
2180         u16 status_reg = 0;
2181         bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
2182
2183         if (hw->mac.type != e1000_pchlan)
2184                 return 0;
2185
2186         /* Wrap the whole flow with the sw flag */
2187         ret_val = hw->phy.ops.acquire(hw);
2188         if (ret_val)
2189                 return ret_val;
2190
2191         /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
2192         if (link) {
2193                 if (hw->phy.type == e1000_phy_82578) {
2194                         ret_val = e1e_rphy_locked(hw, BM_CS_STATUS,
2195                                                   &status_reg);
2196                         if (ret_val)
2197                                 goto release;
2198
2199                         status_reg &= (BM_CS_STATUS_LINK_UP |
2200                                        BM_CS_STATUS_RESOLVED |
2201                                        BM_CS_STATUS_SPEED_MASK);
2202
2203                         if (status_reg == (BM_CS_STATUS_LINK_UP |
2204                                            BM_CS_STATUS_RESOLVED |
2205                                            BM_CS_STATUS_SPEED_1000))
2206                                 k1_enable = false;
2207                 }
2208
2209                 if (hw->phy.type == e1000_phy_82577) {
2210                         ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg);
2211                         if (ret_val)
2212                                 goto release;
2213
2214                         status_reg &= (HV_M_STATUS_LINK_UP |
2215                                        HV_M_STATUS_AUTONEG_COMPLETE |
2216                                        HV_M_STATUS_SPEED_MASK);
2217
2218                         if (status_reg == (HV_M_STATUS_LINK_UP |
2219                                            HV_M_STATUS_AUTONEG_COMPLETE |
2220                                            HV_M_STATUS_SPEED_1000))
2221                                 k1_enable = false;
2222                 }
2223
2224                 /* Link stall fix for link up */
2225                 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100);
2226                 if (ret_val)
2227                         goto release;
2228
2229         } else {
2230                 /* Link stall fix for link down */
2231                 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100);
2232                 if (ret_val)
2233                         goto release;
2234         }
2235
2236         ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2237
2238 release:
2239         hw->phy.ops.release(hw);
2240
2241         return ret_val;
2242 }
2243
2244 /**
2245  *  e1000_configure_k1_ich8lan - Configure K1 power state
2246  *  @hw: pointer to the HW structure
2247  *  @enable: K1 state to configure
2248  *
2249  *  Configure the K1 power state based on the provided parameter.
2250  *  Assumes semaphore already acquired.
2251  *
2252  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2253  **/
2254 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
2255 {
2256         s32 ret_val;
2257         u32 ctrl_reg = 0;
2258         u32 ctrl_ext = 0;
2259         u32 reg = 0;
2260         u16 kmrn_reg = 0;
2261
2262         ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2263                                               &kmrn_reg);
2264         if (ret_val)
2265                 return ret_val;
2266
2267         if (k1_enable)
2268                 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
2269         else
2270                 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
2271
2272         ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2273                                                kmrn_reg);
2274         if (ret_val)
2275                 return ret_val;
2276
2277         usleep_range(20, 40);
2278         ctrl_ext = er32(CTRL_EXT);
2279         ctrl_reg = er32(CTRL);
2280
2281         reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2282         reg |= E1000_CTRL_FRCSPD;
2283         ew32(CTRL, reg);
2284
2285         ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
2286         e1e_flush();
2287         usleep_range(20, 40);
2288         ew32(CTRL, ctrl_reg);
2289         ew32(CTRL_EXT, ctrl_ext);
2290         e1e_flush();
2291         usleep_range(20, 40);
2292
2293         return 0;
2294 }
2295
2296 /**
2297  *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2298  *  @hw:       pointer to the HW structure
2299  *  @d0_state: boolean if entering d0 or d3 device state
2300  *
2301  *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
2302  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
2303  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
2304  **/
2305 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
2306 {
2307         s32 ret_val = 0;
2308         u32 mac_reg;
2309         u16 oem_reg;
2310
2311         if (hw->mac.type < e1000_pchlan)
2312                 return ret_val;
2313
2314         ret_val = hw->phy.ops.acquire(hw);
2315         if (ret_val)
2316                 return ret_val;
2317
2318         if (hw->mac.type == e1000_pchlan) {
2319                 mac_reg = er32(EXTCNF_CTRL);
2320                 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
2321                         goto release;
2322         }
2323
2324         mac_reg = er32(FEXTNVM);
2325         if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
2326                 goto release;
2327
2328         mac_reg = er32(PHY_CTRL);
2329
2330         ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg);
2331         if (ret_val)
2332                 goto release;
2333
2334         oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
2335
2336         if (d0_state) {
2337                 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
2338                         oem_reg |= HV_OEM_BITS_GBE_DIS;
2339
2340                 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
2341                         oem_reg |= HV_OEM_BITS_LPLU;
2342         } else {
2343                 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
2344                                E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
2345                         oem_reg |= HV_OEM_BITS_GBE_DIS;
2346
2347                 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
2348                                E1000_PHY_CTRL_NOND0A_LPLU))
2349                         oem_reg |= HV_OEM_BITS_LPLU;
2350         }
2351
2352         /* Set Restart auto-neg to activate the bits */
2353         if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
2354             !hw->phy.ops.check_reset_block(hw))
2355                 oem_reg |= HV_OEM_BITS_RESTART_AN;
2356
2357         ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg);
2358
2359 release:
2360         hw->phy.ops.release(hw);
2361
2362         return ret_val;
2363 }
2364
2365 /**
2366  *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2367  *  @hw:   pointer to the HW structure
2368  **/
2369 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
2370 {
2371         s32 ret_val;
2372         u16 data;
2373
2374         ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
2375         if (ret_val)
2376                 return ret_val;
2377
2378         data |= HV_KMRN_MDIO_SLOW;
2379
2380         ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
2381
2382         return ret_val;
2383 }
2384
2385 /**
2386  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2387  *  done after every PHY reset.
2388  **/
2389 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2390 {
2391         s32 ret_val = 0;
2392         u16 phy_data;
2393
2394         if (hw->mac.type != e1000_pchlan)
2395                 return 0;
2396
2397         /* Set MDIO slow mode before any other MDIO access */
2398         if (hw->phy.type == e1000_phy_82577) {
2399                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2400                 if (ret_val)
2401                         return ret_val;
2402         }
2403
2404         if (((hw->phy.type == e1000_phy_82577) &&
2405              ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
2406             ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
2407                 /* Disable generation of early preamble */
2408                 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
2409                 if (ret_val)
2410                         return ret_val;
2411
2412                 /* Preamble tuning for SSC */
2413                 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204);
2414                 if (ret_val)
2415                         return ret_val;
2416         }
2417
2418         if (hw->phy.type == e1000_phy_82578) {
2419                 /* Return registers to default by doing a soft reset then
2420                  * writing 0x3140 to the control register.
2421                  */
2422                 if (hw->phy.revision < 2) {
2423                         e1000e_phy_sw_reset(hw);
2424                         ret_val = e1e_wphy(hw, MII_BMCR, 0x3140);
2425                         if (ret_val)
2426                                 return ret_val;
2427                 }
2428         }
2429
2430         /* Select page 0 */
2431         ret_val = hw->phy.ops.acquire(hw);
2432         if (ret_val)
2433                 return ret_val;
2434
2435         hw->phy.addr = 1;
2436         ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2437         hw->phy.ops.release(hw);
2438         if (ret_val)
2439                 return ret_val;
2440
2441         /* Configure the K1 Si workaround during phy reset assuming there is
2442          * link so that it disables K1 if link is in 1Gbps.
2443          */
2444         ret_val = e1000_k1_gig_workaround_hv(hw, true);
2445         if (ret_val)
2446                 return ret_val;
2447
2448         /* Workaround for link disconnects on a busy hub in half duplex */
2449         ret_val = hw->phy.ops.acquire(hw);
2450         if (ret_val)
2451                 return ret_val;
2452         ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2453         if (ret_val)
2454                 goto release;
2455         ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF);
2456         if (ret_val)
2457                 goto release;
2458
2459         /* set MSE higher to enable link to stay up when noise is high */
2460         ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2461 release:
2462         hw->phy.ops.release(hw);
2463
2464         return ret_val;
2465 }
2466
2467 /**
2468  *  e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2469  *  @hw:   pointer to the HW structure
2470  **/
2471 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
2472 {
2473         u32 mac_reg;
2474         u16 i, phy_reg = 0;
2475         s32 ret_val;
2476
2477         ret_val = hw->phy.ops.acquire(hw);
2478         if (ret_val)
2479                 return;
2480         ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2481         if (ret_val)
2482                 goto release;
2483
2484         /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
2485         for (i = 0; i < (hw->mac.rar_entry_count); i++) {
2486                 mac_reg = er32(RAL(i));
2487                 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
2488                                            (u16)(mac_reg & 0xFFFF));
2489                 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
2490                                            (u16)((mac_reg >> 16) & 0xFFFF));
2491
2492                 mac_reg = er32(RAH(i));
2493                 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
2494                                            (u16)(mac_reg & 0xFFFF));
2495                 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
2496                                            (u16)((mac_reg & E1000_RAH_AV)
2497                                                  >> 16));
2498         }
2499
2500         e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2501
2502 release:
2503         hw->phy.ops.release(hw);
2504 }
2505
2506 /**
2507  *  e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2508  *  with 82579 PHY
2509  *  @hw: pointer to the HW structure
2510  *  @enable: flag to enable/disable workaround when enabling/disabling jumbos
2511  **/
2512 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2513 {
2514         s32 ret_val = 0;
2515         u16 phy_reg, data;
2516         u32 mac_reg;
2517         u16 i;
2518
2519         if (hw->mac.type < e1000_pch2lan)
2520                 return 0;
2521
2522         /* disable Rx path while enabling/disabling workaround */
2523         e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
2524         ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | BIT(14));
2525         if (ret_val)
2526                 return ret_val;
2527
2528         if (enable) {
2529                 /* Write Rx addresses (rar_entry_count for RAL/H, and
2530                  * SHRAL/H) and initial CRC values to the MAC
2531                  */
2532                 for (i = 0; i < hw->mac.rar_entry_count; i++) {
2533                         u8 mac_addr[ETH_ALEN] = { 0 };
2534                         u32 addr_high, addr_low;
2535
2536                         addr_high = er32(RAH(i));
2537                         if (!(addr_high & E1000_RAH_AV))
2538                                 continue;
2539                         addr_low = er32(RAL(i));
2540                         mac_addr[0] = (addr_low & 0xFF);
2541                         mac_addr[1] = ((addr_low >> 8) & 0xFF);
2542                         mac_addr[2] = ((addr_low >> 16) & 0xFF);
2543                         mac_addr[3] = ((addr_low >> 24) & 0xFF);
2544                         mac_addr[4] = (addr_high & 0xFF);
2545                         mac_addr[5] = ((addr_high >> 8) & 0xFF);
2546
2547                         ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr));
2548                 }
2549
2550                 /* Write Rx addresses to the PHY */
2551                 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2552
2553                 /* Enable jumbo frame workaround in the MAC */
2554                 mac_reg = er32(FFLT_DBG);
2555                 mac_reg &= ~BIT(14);
2556                 mac_reg |= (7 << 15);
2557                 ew32(FFLT_DBG, mac_reg);
2558
2559                 mac_reg = er32(RCTL);
2560                 mac_reg |= E1000_RCTL_SECRC;
2561                 ew32(RCTL, mac_reg);
2562
2563                 ret_val = e1000e_read_kmrn_reg(hw,
2564                                                E1000_KMRNCTRLSTA_CTRL_OFFSET,
2565                                                &data);
2566                 if (ret_val)
2567                         return ret_val;
2568                 ret_val = e1000e_write_kmrn_reg(hw,
2569                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2570                                                 data | BIT(0));
2571                 if (ret_val)
2572                         return ret_val;
2573                 ret_val = e1000e_read_kmrn_reg(hw,
2574                                                E1000_KMRNCTRLSTA_HD_CTRL,
2575                                                &data);
2576                 if (ret_val)
2577                         return ret_val;
2578                 data &= ~(0xF << 8);
2579                 data |= (0xB << 8);
2580                 ret_val = e1000e_write_kmrn_reg(hw,
2581                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2582                                                 data);
2583                 if (ret_val)
2584                         return ret_val;
2585
2586                 /* Enable jumbo frame workaround in the PHY */
2587                 e1e_rphy(hw, PHY_REG(769, 23), &data);
2588                 data &= ~(0x7F << 5);
2589                 data |= (0x37 << 5);
2590                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2591                 if (ret_val)
2592                         return ret_val;
2593                 e1e_rphy(hw, PHY_REG(769, 16), &data);
2594                 data &= ~BIT(13);
2595                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2596                 if (ret_val)
2597                         return ret_val;
2598                 e1e_rphy(hw, PHY_REG(776, 20), &data);
2599                 data &= ~(0x3FF << 2);
2600                 data |= (E1000_TX_PTR_GAP << 2);
2601                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2602                 if (ret_val)
2603                         return ret_val;
2604                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100);
2605                 if (ret_val)
2606                         return ret_val;
2607                 e1e_rphy(hw, HV_PM_CTRL, &data);
2608                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | BIT(10));
2609                 if (ret_val)
2610                         return ret_val;
2611         } else {
2612                 /* Write MAC register values back to h/w defaults */
2613                 mac_reg = er32(FFLT_DBG);
2614                 mac_reg &= ~(0xF << 14);
2615                 ew32(FFLT_DBG, mac_reg);
2616
2617                 mac_reg = er32(RCTL);
2618                 mac_reg &= ~E1000_RCTL_SECRC;
2619                 ew32(RCTL, mac_reg);
2620
2621                 ret_val = e1000e_read_kmrn_reg(hw,
2622                                                E1000_KMRNCTRLSTA_CTRL_OFFSET,
2623                                                &data);
2624                 if (ret_val)
2625                         return ret_val;
2626                 ret_val = e1000e_write_kmrn_reg(hw,
2627                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2628                                                 data & ~BIT(0));
2629                 if (ret_val)
2630                         return ret_val;
2631                 ret_val = e1000e_read_kmrn_reg(hw,
2632                                                E1000_KMRNCTRLSTA_HD_CTRL,
2633                                                &data);
2634                 if (ret_val)
2635                         return ret_val;
2636                 data &= ~(0xF << 8);
2637                 data |= (0xB << 8);
2638                 ret_val = e1000e_write_kmrn_reg(hw,
2639                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2640                                                 data);
2641                 if (ret_val)
2642                         return ret_val;
2643
2644                 /* Write PHY register values back to h/w defaults */
2645                 e1e_rphy(hw, PHY_REG(769, 23), &data);
2646                 data &= ~(0x7F << 5);
2647                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2648                 if (ret_val)
2649                         return ret_val;
2650                 e1e_rphy(hw, PHY_REG(769, 16), &data);
2651                 data |= BIT(13);
2652                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2653                 if (ret_val)
2654                         return ret_val;
2655                 e1e_rphy(hw, PHY_REG(776, 20), &data);
2656                 data &= ~(0x3FF << 2);
2657                 data |= (0x8 << 2);
2658                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2659                 if (ret_val)
2660                         return ret_val;
2661                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
2662                 if (ret_val)
2663                         return ret_val;
2664                 e1e_rphy(hw, HV_PM_CTRL, &data);
2665                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~BIT(10));
2666                 if (ret_val)
2667                         return ret_val;
2668         }
2669
2670         /* re-enable Rx path after enabling/disabling workaround */
2671         return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~BIT(14));
2672 }
2673
2674 /**
2675  *  e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2676  *  done after every PHY reset.
2677  **/
2678 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2679 {
2680         s32 ret_val = 0;
2681
2682         if (hw->mac.type != e1000_pch2lan)
2683                 return 0;
2684
2685         /* Set MDIO slow mode before any other MDIO access */
2686         ret_val = e1000_set_mdio_slow_mode_hv(hw);
2687         if (ret_val)
2688                 return ret_val;
2689
2690         ret_val = hw->phy.ops.acquire(hw);
2691         if (ret_val)
2692                 return ret_val;
2693         /* set MSE higher to enable link to stay up when noise is high */
2694         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2695         if (ret_val)
2696                 goto release;
2697         /* drop link after 5 times MSE threshold was reached */
2698         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2699 release:
2700         hw->phy.ops.release(hw);
2701
2702         return ret_val;
2703 }
2704
2705 /**
2706  *  e1000_k1_gig_workaround_lv - K1 Si workaround
2707  *  @hw:   pointer to the HW structure
2708  *
2709  *  Workaround to set the K1 beacon duration for 82579 parts in 10Mbps
2710  *  Disable K1 in 1000Mbps and 100Mbps
2711  **/
2712 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2713 {
2714         s32 ret_val = 0;
2715         u16 status_reg = 0;
2716
2717         if (hw->mac.type != e1000_pch2lan)
2718                 return 0;
2719
2720         /* Set K1 beacon duration based on 10Mbs speed */
2721         ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
2722         if (ret_val)
2723                 return ret_val;
2724
2725         if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2726             == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2727                 if (status_reg &
2728                     (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) {
2729                         u16 pm_phy_reg;
2730
2731                         /* LV 1G/100 Packet drop issue wa  */
2732                         ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg);
2733                         if (ret_val)
2734                                 return ret_val;
2735                         pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE;
2736                         ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg);
2737                         if (ret_val)
2738                                 return ret_val;
2739                 } else {
2740                         u32 mac_reg;
2741
2742                         mac_reg = er32(FEXTNVM4);
2743                         mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
2744                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
2745                         ew32(FEXTNVM4, mac_reg);
2746                 }
2747         }
2748
2749         return ret_val;
2750 }
2751
2752 /**
2753  *  e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2754  *  @hw:   pointer to the HW structure
2755  *  @gate: boolean set to true to gate, false to ungate
2756  *
2757  *  Gate/ungate the automatic PHY configuration via hardware; perform
2758  *  the configuration via software instead.
2759  **/
2760 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2761 {
2762         u32 extcnf_ctrl;
2763
2764         if (hw->mac.type < e1000_pch2lan)
2765                 return;
2766
2767         extcnf_ctrl = er32(EXTCNF_CTRL);
2768
2769         if (gate)
2770                 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2771         else
2772                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2773
2774         ew32(EXTCNF_CTRL, extcnf_ctrl);
2775 }
2776
2777 /**
2778  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
2779  *  @hw: pointer to the HW structure
2780  *
2781  *  Check the appropriate indication the MAC has finished configuring the
2782  *  PHY after a software reset.
2783  **/
2784 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2785 {
2786         u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
2787
2788         /* Wait for basic configuration completes before proceeding */
2789         do {
2790                 data = er32(STATUS);
2791                 data &= E1000_STATUS_LAN_INIT_DONE;
2792                 usleep_range(100, 200);
2793         } while ((!data) && --loop);
2794
2795         /* If basic configuration is incomplete before the above loop
2796          * count reaches 0, loading the configuration from NVM will
2797          * leave the PHY in a bad state possibly resulting in no link.
2798          */
2799         if (loop == 0)
2800                 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
2801
2802         /* Clear the Init Done bit for the next init event */
2803         data = er32(STATUS);
2804         data &= ~E1000_STATUS_LAN_INIT_DONE;
2805         ew32(STATUS, data);
2806 }
2807
2808 /**
2809  *  e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
2810  *  @hw: pointer to the HW structure
2811  **/
2812 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
2813 {
2814         s32 ret_val = 0;
2815         u16 reg;
2816
2817         if (hw->phy.ops.check_reset_block(hw))
2818                 return 0;
2819
2820         /* Allow time for h/w to get to quiescent state after reset */
2821         usleep_range(10000, 20000);
2822
2823         /* Perform any necessary post-reset workarounds */
2824         switch (hw->mac.type) {
2825         case e1000_pchlan:
2826                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2827                 if (ret_val)
2828                         return ret_val;
2829                 break;
2830         case e1000_pch2lan:
2831                 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
2832                 if (ret_val)
2833                         return ret_val;
2834                 break;
2835         default:
2836                 break;
2837         }
2838
2839         /* Clear the host wakeup bit after lcd reset */
2840         if (hw->mac.type >= e1000_pchlan) {
2841                 e1e_rphy(hw, BM_PORT_GEN_CFG, &reg);
2842                 reg &= ~BM_WUC_HOST_WU_BIT;
2843                 e1e_wphy(hw, BM_PORT_GEN_CFG, reg);
2844         }
2845
2846         /* Configure the LCD with the extended configuration region in NVM */
2847         ret_val = e1000_sw_lcd_config_ich8lan(hw);
2848         if (ret_val)
2849                 return ret_val;
2850
2851         /* Configure the LCD with the OEM bits in NVM */
2852         ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2853
2854         if (hw->mac.type == e1000_pch2lan) {
2855                 /* Ungate automatic PHY configuration on non-managed 82579 */
2856                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
2857                         usleep_range(10000, 20000);
2858                         e1000_gate_hw_phy_config_ich8lan(hw, false);
2859                 }
2860
2861                 /* Set EEE LPI Update Timer to 200usec */
2862                 ret_val = hw->phy.ops.acquire(hw);
2863                 if (ret_val)
2864                         return ret_val;
2865                 ret_val = e1000_write_emi_reg_locked(hw,
2866                                                      I82579_LPI_UPDATE_TIMER,
2867                                                      0x1387);
2868                 hw->phy.ops.release(hw);
2869         }
2870
2871         return ret_val;
2872 }
2873
2874 /**
2875  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
2876  *  @hw: pointer to the HW structure
2877  *
2878  *  Resets the PHY
2879  *  This is a function pointer entry point called by drivers
2880  *  or other shared routines.
2881  **/
2882 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
2883 {
2884         s32 ret_val = 0;
2885
2886         /* Gate automatic PHY configuration by hardware on non-managed 82579 */
2887         if ((hw->mac.type == e1000_pch2lan) &&
2888             !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
2889                 e1000_gate_hw_phy_config_ich8lan(hw, true);
2890
2891         ret_val = e1000e_phy_hw_reset_generic(hw);
2892         if (ret_val)
2893                 return ret_val;
2894
2895         return e1000_post_phy_reset_ich8lan(hw);
2896 }
2897
2898 /**
2899  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
2900  *  @hw: pointer to the HW structure
2901  *  @active: true to enable LPLU, false to disable
2902  *
2903  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
2904  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
2905  *  the phy speed. This function will manually set the LPLU bit and restart
2906  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
2907  *  since it configures the same bit.
2908  **/
2909 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
2910 {
2911         s32 ret_val;
2912         u16 oem_reg;
2913
2914         ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
2915         if (ret_val)
2916                 return ret_val;
2917
2918         if (active)
2919                 oem_reg |= HV_OEM_BITS_LPLU;
2920         else
2921                 oem_reg &= ~HV_OEM_BITS_LPLU;
2922
2923         if (!hw->phy.ops.check_reset_block(hw))
2924                 oem_reg |= HV_OEM_BITS_RESTART_AN;
2925
2926         return e1e_wphy(hw, HV_OEM_BITS, oem_reg);
2927 }
2928
2929 /**
2930  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
2931  *  @hw: pointer to the HW structure
2932  *  @active: true to enable LPLU, false to disable
2933  *
2934  *  Sets the LPLU D0 state according to the active flag.  When
2935  *  activating LPLU this function also disables smart speed
2936  *  and vice versa.  LPLU will not be activated unless the
2937  *  device autonegotiation advertisement meets standards of
2938  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
2939  *  This is a function pointer entry point only called by
2940  *  PHY setup routines.
2941  **/
2942 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2943 {
2944         struct e1000_phy_info *phy = &hw->phy;
2945         u32 phy_ctrl;
2946         s32 ret_val = 0;
2947         u16 data;
2948
2949         if (phy->type == e1000_phy_ife)
2950                 return 0;
2951
2952         phy_ctrl = er32(PHY_CTRL);
2953
2954         if (active) {
2955                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2956                 ew32(PHY_CTRL, phy_ctrl);
2957
2958                 if (phy->type != e1000_phy_igp_3)
2959                         return 0;
2960
2961                 /* Call gig speed drop workaround on LPLU before accessing
2962                  * any PHY registers
2963                  */
2964                 if (hw->mac.type == e1000_ich8lan)
2965                         e1000e_gig_downshift_workaround_ich8lan(hw);
2966
2967                 /* When LPLU is enabled, we should disable SmartSpeed */
2968                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
2969                 if (ret_val)
2970                         return ret_val;
2971                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2972                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
2973                 if (ret_val)
2974                         return ret_val;
2975         } else {
2976                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2977                 ew32(PHY_CTRL, phy_ctrl);
2978
2979                 if (phy->type != e1000_phy_igp_3)
2980                         return 0;
2981
2982                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
2983                  * during Dx states where the power conservation is most
2984                  * important.  During driver activity we should enable
2985                  * SmartSpeed, so performance is maintained.
2986                  */
2987                 if (phy->smart_speed == e1000_smart_speed_on) {
2988                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2989                                            &data);
2990                         if (ret_val)
2991                                 return ret_val;
2992
2993                         data |= IGP01E1000_PSCFR_SMART_SPEED;
2994                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2995                                            data);
2996                         if (ret_val)
2997                                 return ret_val;
2998                 } else if (phy->smart_speed == e1000_smart_speed_off) {
2999                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3000                                            &data);
3001                         if (ret_val)
3002                                 return ret_val;
3003
3004                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3005                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3006                                            data);
3007                         if (ret_val)
3008                                 return ret_val;
3009                 }
3010         }
3011
3012         return 0;
3013 }
3014
3015 /**
3016  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
3017  *  @hw: pointer to the HW structure
3018  *  @active: true to enable LPLU, false to disable
3019  *
3020  *  Sets the LPLU D3 state according to the active flag.  When
3021  *  activating LPLU this function also disables smart speed
3022  *  and vice versa.  LPLU will not be activated unless the
3023  *  device autonegotiation advertisement meets standards of
3024  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
3025  *  This is a function pointer entry point only called by
3026  *  PHY setup routines.
3027  **/
3028 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3029 {
3030         struct e1000_phy_info *phy = &hw->phy;
3031         u32 phy_ctrl;
3032         s32 ret_val = 0;
3033         u16 data;
3034
3035         phy_ctrl = er32(PHY_CTRL);
3036
3037         if (!active) {
3038                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
3039                 ew32(PHY_CTRL, phy_ctrl);
3040
3041                 if (phy->type != e1000_phy_igp_3)
3042                         return 0;
3043
3044                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
3045                  * during Dx states where the power conservation is most
3046                  * important.  During driver activity we should enable
3047                  * SmartSpeed, so performance is maintained.
3048                  */
3049                 if (phy->smart_speed == e1000_smart_speed_on) {
3050                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3051                                            &data);
3052                         if (ret_val)
3053                                 return ret_val;
3054
3055                         data |= IGP01E1000_PSCFR_SMART_SPEED;
3056                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3057                                            data);
3058                         if (ret_val)
3059                                 return ret_val;
3060                 } else if (phy->smart_speed == e1000_smart_speed_off) {
3061                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3062                                            &data);
3063                         if (ret_val)
3064                                 return ret_val;
3065
3066                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3067                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3068                                            data);
3069                         if (ret_val)
3070                                 return ret_val;
3071                 }
3072         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
3073                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
3074                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
3075                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
3076                 ew32(PHY_CTRL, phy_ctrl);
3077
3078                 if (phy->type != e1000_phy_igp_3)
3079                         return 0;
3080
3081                 /* Call gig speed drop workaround on LPLU before accessing
3082                  * any PHY registers
3083                  */
3084                 if (hw->mac.type == e1000_ich8lan)
3085                         e1000e_gig_downshift_workaround_ich8lan(hw);
3086
3087                 /* When LPLU is enabled, we should disable SmartSpeed */
3088                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
3089                 if (ret_val)
3090                         return ret_val;
3091
3092                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3093                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
3094         }
3095
3096         return ret_val;
3097 }
3098
3099 /**
3100  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
3101  *  @hw: pointer to the HW structure
3102  *  @bank:  pointer to the variable that returns the active bank
3103  *
3104  *  Reads signature byte from the NVM using the flash access registers.
3105  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
3106  **/
3107 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
3108 {
3109         u32 eecd;
3110         struct e1000_nvm_info *nvm = &hw->nvm;
3111         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
3112         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
3113         u32 nvm_dword = 0;
3114         u8 sig_byte = 0;
3115         s32 ret_val;
3116
3117         switch (hw->mac.type) {
3118         case e1000_pch_spt:
3119         case e1000_pch_cnp:
3120                 bank1_offset = nvm->flash_bank_size;
3121                 act_offset = E1000_ICH_NVM_SIG_WORD;
3122
3123                 /* set bank to 0 in case flash read fails */
3124                 *bank = 0;
3125
3126                 /* Check bank 0 */
3127                 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset,
3128                                                          &nvm_dword);
3129                 if (ret_val)
3130                         return ret_val;
3131                 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3132                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3133                     E1000_ICH_NVM_SIG_VALUE) {
3134                         *bank = 0;
3135                         return 0;
3136                 }
3137
3138                 /* Check bank 1 */
3139                 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset +
3140                                                          bank1_offset,
3141                                                          &nvm_dword);
3142                 if (ret_val)
3143                         return ret_val;
3144                 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3145                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3146                     E1000_ICH_NVM_SIG_VALUE) {
3147                         *bank = 1;
3148                         return 0;
3149                 }
3150
3151                 e_dbg("ERROR: No valid NVM bank present\n");
3152                 return -E1000_ERR_NVM;
3153         case e1000_ich8lan:
3154         case e1000_ich9lan:
3155                 eecd = er32(EECD);
3156                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
3157                     E1000_EECD_SEC1VAL_VALID_MASK) {
3158                         if (eecd & E1000_EECD_SEC1VAL)
3159                                 *bank = 1;
3160                         else
3161                                 *bank = 0;
3162
3163                         return 0;
3164                 }
3165                 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n");
3166                 /* fall-thru */
3167         default:
3168                 /* set bank to 0 in case flash read fails */
3169                 *bank = 0;
3170
3171                 /* Check bank 0 */
3172                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
3173                                                         &sig_byte);
3174                 if (ret_val)
3175                         return ret_val;
3176                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3177                     E1000_ICH_NVM_SIG_VALUE) {
3178                         *bank = 0;
3179                         return 0;
3180                 }
3181
3182                 /* Check bank 1 */
3183                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
3184                                                         bank1_offset,
3185                                                         &sig_byte);
3186                 if (ret_val)
3187                         return ret_val;
3188                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3189                     E1000_ICH_NVM_SIG_VALUE) {
3190                         *bank = 1;
3191                         return 0;
3192                 }
3193
3194                 e_dbg("ERROR: No valid NVM bank present\n");
3195                 return -E1000_ERR_NVM;
3196         }
3197 }
3198
3199 /**
3200  *  e1000_read_nvm_spt - NVM access for SPT
3201  *  @hw: pointer to the HW structure
3202  *  @offset: The offset (in bytes) of the word(s) to read.
3203  *  @words: Size of data to read in words.
3204  *  @data: pointer to the word(s) to read at offset.
3205  *
3206  *  Reads a word(s) from the NVM
3207  **/
3208 static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
3209                               u16 *data)
3210 {
3211         struct e1000_nvm_info *nvm = &hw->nvm;
3212         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3213         u32 act_offset;
3214         s32 ret_val = 0;
3215         u32 bank = 0;
3216         u32 dword = 0;
3217         u16 offset_to_read;
3218         u16 i;
3219
3220         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3221             (words == 0)) {
3222                 e_dbg("nvm parameter(s) out of bounds\n");
3223                 ret_val = -E1000_ERR_NVM;
3224                 goto out;
3225         }
3226
3227         nvm->ops.acquire(hw);
3228
3229         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3230         if (ret_val) {
3231                 e_dbg("Could not detect valid bank, assuming bank 0\n");
3232                 bank = 0;
3233         }
3234
3235         act_offset = (bank) ? nvm->flash_bank_size : 0;
3236         act_offset += offset;
3237
3238         ret_val = 0;
3239
3240         for (i = 0; i < words; i += 2) {
3241                 if (words - i == 1) {
3242                         if (dev_spec->shadow_ram[offset + i].modified) {
3243                                 data[i] =
3244                                     dev_spec->shadow_ram[offset + i].value;
3245                         } else {
3246                                 offset_to_read = act_offset + i -
3247                                     ((act_offset + i) % 2);
3248                                 ret_val =
3249                                   e1000_read_flash_dword_ich8lan(hw,
3250                                                                  offset_to_read,
3251                                                                  &dword);
3252                                 if (ret_val)
3253                                         break;
3254                                 if ((act_offset + i) % 2 == 0)
3255                                         data[i] = (u16)(dword & 0xFFFF);
3256                                 else
3257                                         data[i] = (u16)((dword >> 16) & 0xFFFF);
3258                         }
3259                 } else {
3260                         offset_to_read = act_offset + i;
3261                         if (!(dev_spec->shadow_ram[offset + i].modified) ||
3262                             !(dev_spec->shadow_ram[offset + i + 1].modified)) {
3263                                 ret_val =
3264                                   e1000_read_flash_dword_ich8lan(hw,
3265                                                                  offset_to_read,
3266                                                                  &dword);
3267                                 if (ret_val)
3268                                         break;
3269                         }
3270                         if (dev_spec->shadow_ram[offset + i].modified)
3271                                 data[i] =
3272                                     dev_spec->shadow_ram[offset + i].value;
3273                         else
3274                                 data[i] = (u16)(dword & 0xFFFF);
3275                         if (dev_spec->shadow_ram[offset + i].modified)
3276                                 data[i + 1] =
3277                                     dev_spec->shadow_ram[offset + i + 1].value;
3278                         else
3279                                 data[i + 1] = (u16)(dword >> 16 & 0xFFFF);
3280                 }
3281         }
3282
3283         nvm->ops.release(hw);
3284
3285 out:
3286         if (ret_val)
3287                 e_dbg("NVM read error: %d\n", ret_val);
3288
3289         return ret_val;
3290 }
3291
3292 /**
3293  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
3294  *  @hw: pointer to the HW structure
3295  *  @offset: The offset (in bytes) of the word(s) to read.
3296  *  @words: Size of data to read in words
3297  *  @data: Pointer to the word(s) to read at offset.
3298  *
3299  *  Reads a word(s) from the NVM using the flash access registers.
3300  **/
3301 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3302                                   u16 *data)
3303 {
3304         struct e1000_nvm_info *nvm = &hw->nvm;
3305         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3306         u32 act_offset;
3307         s32 ret_val = 0;
3308         u32 bank = 0;
3309         u16 i, word;
3310
3311         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3312             (words == 0)) {
3313                 e_dbg("nvm parameter(s) out of bounds\n");
3314                 ret_val = -E1000_ERR_NVM;
3315                 goto out;
3316         }
3317
3318         nvm->ops.acquire(hw);
3319
3320         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3321         if (ret_val) {
3322                 e_dbg("Could not detect valid bank, assuming bank 0\n");
3323                 bank = 0;
3324         }
3325
3326         act_offset = (bank) ? nvm->flash_bank_size : 0;
3327         act_offset += offset;
3328
3329         ret_val = 0;
3330         for (i = 0; i < words; i++) {
3331                 if (dev_spec->shadow_ram[offset + i].modified) {
3332                         data[i] = dev_spec->shadow_ram[offset + i].value;
3333                 } else {
3334                         ret_val = e1000_read_flash_word_ich8lan(hw,
3335                                                                 act_offset + i,
3336                                                                 &word);
3337                         if (ret_val)
3338                                 break;
3339                         data[i] = word;
3340                 }
3341         }
3342
3343         nvm->ops.release(hw);
3344
3345 out:
3346         if (ret_val)
3347                 e_dbg("NVM read error: %d\n", ret_val);
3348
3349         return ret_val;
3350 }
3351
3352 /**
3353  *  e1000_flash_cycle_init_ich8lan - Initialize flash
3354  *  @hw: pointer to the HW structure
3355  *
3356  *  This function does initial flash setup so that a new read/write/erase cycle
3357  *  can be started.
3358  **/
3359 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3360 {
3361         union ich8_hws_flash_status hsfsts;
3362         s32 ret_val = -E1000_ERR_NVM;
3363
3364         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3365
3366         /* Check if the flash descriptor is valid */
3367         if (!hsfsts.hsf_status.fldesvalid) {
3368                 e_dbg("Flash descriptor invalid.  SW Sequencing must be used.\n");
3369                 return -E1000_ERR_NVM;
3370         }
3371
3372         /* Clear FCERR and DAEL in hw status by writing 1 */
3373         hsfsts.hsf_status.flcerr = 1;
3374         hsfsts.hsf_status.dael = 1;
3375         if (hw->mac.type >= e1000_pch_spt)
3376                 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF);
3377         else
3378                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3379
3380         /* Either we should have a hardware SPI cycle in progress
3381          * bit to check against, in order to start a new cycle or
3382          * FDONE bit should be changed in the hardware so that it
3383          * is 1 after hardware reset, which can then be used as an
3384          * indication whether a cycle is in progress or has been
3385          * completed.
3386          */
3387
3388         if (!hsfsts.hsf_status.flcinprog) {
3389                 /* There is no cycle running at present,
3390                  * so we can start a cycle.
3391                  * Begin by setting Flash Cycle Done.
3392                  */
3393                 hsfsts.hsf_status.flcdone = 1;
3394                 if (hw->mac.type >= e1000_pch_spt)
3395                         ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF);
3396                 else
3397                         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3398                 ret_val = 0;
3399         } else {
3400                 s32 i;
3401
3402                 /* Otherwise poll for sometime so the current
3403                  * cycle has a chance to end before giving up.
3404                  */
3405                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
3406                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3407                         if (!hsfsts.hsf_status.flcinprog) {
3408                                 ret_val = 0;
3409                                 break;
3410                         }
3411                         udelay(1);
3412                 }
3413                 if (!ret_val) {
3414                         /* Successful in waiting for previous cycle to timeout,
3415                          * now set the Flash Cycle Done.
3416                          */
3417                         hsfsts.hsf_status.flcdone = 1;
3418                         if (hw->mac.type >= e1000_pch_spt)
3419                                 ew32flash(ICH_FLASH_HSFSTS,
3420                                           hsfsts.regval & 0xFFFF);
3421                         else
3422                                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3423                 } else {
3424                         e_dbg("Flash controller busy, cannot get access\n");
3425                 }
3426         }
3427
3428         return ret_val;
3429 }
3430
3431 /**
3432  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3433  *  @hw: pointer to the HW structure
3434  *  @timeout: maximum time to wait for completion
3435  *
3436  *  This function starts a flash cycle and waits for its completion.
3437  **/
3438 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3439 {
3440         union ich8_hws_flash_ctrl hsflctl;
3441         union ich8_hws_flash_status hsfsts;
3442         u32 i = 0;
3443
3444         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3445         if (hw->mac.type >= e1000_pch_spt)
3446                 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
3447         else
3448                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3449         hsflctl.hsf_ctrl.flcgo = 1;
3450
3451         if (hw->mac.type >= e1000_pch_spt)
3452                 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
3453         else
3454                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3455
3456         /* wait till FDONE bit is set to 1 */
3457         do {
3458                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3459                 if (hsfsts.hsf_status.flcdone)
3460                         break;
3461                 udelay(1);
3462         } while (i++ < timeout);
3463
3464         if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
3465                 return 0;
3466
3467         return -E1000_ERR_NVM;
3468 }
3469
3470 /**
3471  *  e1000_read_flash_dword_ich8lan - Read dword from flash
3472  *  @hw: pointer to the HW structure
3473  *  @offset: offset to data location
3474  *  @data: pointer to the location for storing the data
3475  *
3476  *  Reads the flash dword at offset into data.  Offset is converted
3477  *  to bytes before read.
3478  **/
3479 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset,
3480                                           u32 *data)
3481 {
3482         /* Must convert word offset into bytes. */
3483         offset <<= 1;
3484         return e1000_read_flash_data32_ich8lan(hw, offset, data);
3485 }
3486
3487 /**
3488  *  e1000_read_flash_word_ich8lan - Read word from flash
3489  *  @hw: pointer to the HW structure
3490  *  @offset: offset to data location
3491  *  @data: pointer to the location for storing the data
3492  *
3493  *  Reads the flash word at offset into data.  Offset is converted
3494  *  to bytes before read.
3495  **/
3496 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
3497                                          u16 *data)
3498 {
3499         /* Must convert offset into bytes. */
3500         offset <<= 1;
3501
3502         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
3503 }
3504
3505 /**
3506  *  e1000_read_flash_byte_ich8lan - Read byte from flash
3507  *  @hw: pointer to the HW structure
3508  *  @offset: The offset of the byte to read.
3509  *  @data: Pointer to a byte to store the value read.
3510  *
3511  *  Reads a single byte from the NVM using the flash access registers.
3512  **/
3513 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3514                                          u8 *data)
3515 {
3516         s32 ret_val;
3517         u16 word = 0;
3518
3519         /* In SPT, only 32 bits access is supported,
3520          * so this function should not be called.
3521          */
3522         if (hw->mac.type >= e1000_pch_spt)
3523                 return -E1000_ERR_NVM;
3524         else
3525                 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3526
3527         if (ret_val)
3528                 return ret_val;
3529
3530         *data = (u8)word;
3531
3532         return 0;
3533 }
3534
3535 /**
3536  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
3537  *  @hw: pointer to the HW structure
3538  *  @offset: The offset (in bytes) of the byte or word to read.
3539  *  @size: Size of data to read, 1=byte 2=word
3540  *  @data: Pointer to the word to store the value read.
3541  *
3542  *  Reads a byte or word from the NVM using the flash access registers.
3543  **/
3544 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3545                                          u8 size, u16 *data)
3546 {
3547         union ich8_hws_flash_status hsfsts;
3548         union ich8_hws_flash_ctrl hsflctl;
3549         u32 flash_linear_addr;
3550         u32 flash_data = 0;
3551         s32 ret_val = -E1000_ERR_NVM;
3552         u8 count = 0;
3553
3554         if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3555                 return -E1000_ERR_NVM;
3556
3557         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3558                              hw->nvm.flash_base_addr);
3559
3560         do {
3561                 udelay(1);
3562                 /* Steps */
3563                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3564                 if (ret_val)
3565                         break;
3566
3567                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3568                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3569                 hsflctl.hsf_ctrl.fldbcount = size - 1;
3570                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3571                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3572
3573                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3574
3575                 ret_val =
3576                     e1000_flash_cycle_ich8lan(hw,
3577                                               ICH_FLASH_READ_COMMAND_TIMEOUT);
3578
3579                 /* Check if FCERR is set to 1, if set to 1, clear it
3580                  * and try the whole sequence a few more times, else
3581                  * read in (shift in) the Flash Data0, the order is
3582                  * least significant byte first msb to lsb
3583                  */
3584                 if (!ret_val) {
3585                         flash_data = er32flash(ICH_FLASH_FDATA0);
3586                         if (size == 1)
3587                                 *data = (u8)(flash_data & 0x000000FF);
3588                         else if (size == 2)
3589                                 *data = (u16)(flash_data & 0x0000FFFF);
3590                         break;
3591                 } else {
3592                         /* If we've gotten here, then things are probably
3593                          * completely hosed, but if the error condition is
3594                          * detected, it won't hurt to give it another try...
3595                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3596                          */
3597                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3598                         if (hsfsts.hsf_status.flcerr) {
3599                                 /* Repeat for some time before giving up. */
3600                                 continue;
3601                         } else if (!hsfsts.hsf_status.flcdone) {
3602                                 e_dbg("Timeout error - flash cycle did not complete.\n");
3603                                 break;
3604                         }
3605                 }
3606         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3607
3608         return ret_val;
3609 }
3610
3611 /**
3612  *  e1000_read_flash_data32_ich8lan - Read dword from NVM
3613  *  @hw: pointer to the HW structure
3614  *  @offset: The offset (in bytes) of the dword to read.
3615  *  @data: Pointer to the dword to store the value read.
3616  *
3617  *  Reads a byte or word from the NVM using the flash access registers.
3618  **/
3619
3620 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
3621                                            u32 *data)
3622 {
3623         union ich8_hws_flash_status hsfsts;
3624         union ich8_hws_flash_ctrl hsflctl;
3625         u32 flash_linear_addr;
3626         s32 ret_val = -E1000_ERR_NVM;
3627         u8 count = 0;
3628
3629         if (offset > ICH_FLASH_LINEAR_ADDR_MASK || hw->mac.type < e1000_pch_spt)
3630                 return -E1000_ERR_NVM;
3631         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3632                              hw->nvm.flash_base_addr);
3633
3634         do {
3635                 udelay(1);
3636                 /* Steps */
3637                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3638                 if (ret_val)
3639                         break;
3640                 /* In SPT, This register is in Lan memory space, not flash.
3641                  * Therefore, only 32 bit access is supported
3642                  */
3643                 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
3644
3645                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3646                 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
3647                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3648                 /* In SPT, This register is in Lan memory space, not flash.
3649                  * Therefore, only 32 bit access is supported
3650                  */
3651                 ew32flash(ICH_FLASH_HSFSTS, (u32)hsflctl.regval << 16);
3652                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3653
3654                 ret_val =
3655                    e1000_flash_cycle_ich8lan(hw,
3656                                              ICH_FLASH_READ_COMMAND_TIMEOUT);
3657
3658                 /* Check if FCERR is set to 1, if set to 1, clear it
3659                  * and try the whole sequence a few more times, else
3660                  * read in (shift in) the Flash Data0, the order is
3661                  * least significant byte first msb to lsb
3662                  */
3663                 if (!ret_val) {
3664                         *data = er32flash(ICH_FLASH_FDATA0);
3665                         break;
3666                 } else {
3667                         /* If we've gotten here, then things are probably
3668                          * completely hosed, but if the error condition is
3669                          * detected, it won't hurt to give it another try...
3670                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3671                          */
3672                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3673                         if (hsfsts.hsf_status.flcerr) {
3674                                 /* Repeat for some time before giving up. */
3675                                 continue;
3676                         } else if (!hsfsts.hsf_status.flcdone) {
3677                                 e_dbg("Timeout error - flash cycle did not complete.\n");
3678                                 break;
3679                         }
3680                 }
3681         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3682
3683         return ret_val;
3684 }
3685
3686 /**
3687  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
3688  *  @hw: pointer to the HW structure
3689  *  @offset: The offset (in bytes) of the word(s) to write.
3690  *  @words: Size of data to write in words
3691  *  @data: Pointer to the word(s) to write at offset.
3692  *
3693  *  Writes a byte or word to the NVM using the flash access registers.
3694  **/
3695 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3696                                    u16 *data)
3697 {
3698         struct e1000_nvm_info *nvm = &hw->nvm;
3699         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3700         u16 i;
3701
3702         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3703             (words == 0)) {
3704                 e_dbg("nvm parameter(s) out of bounds\n");
3705                 return -E1000_ERR_NVM;
3706         }
3707
3708         nvm->ops.acquire(hw);
3709
3710         for (i = 0; i < words; i++) {
3711                 dev_spec->shadow_ram[offset + i].modified = true;
3712                 dev_spec->shadow_ram[offset + i].value = data[i];
3713         }
3714
3715         nvm->ops.release(hw);
3716
3717         return 0;
3718 }
3719
3720 /**
3721  *  e1000_update_nvm_checksum_spt - Update the checksum for NVM
3722  *  @hw: pointer to the HW structure
3723  *
3724  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
3725  *  which writes the checksum to the shadow ram.  The changes in the shadow
3726  *  ram are then committed to the EEPROM by processing each bank at a time
3727  *  checking for the modified bit and writing only the pending changes.
3728  *  After a successful commit, the shadow ram is cleared and is ready for
3729  *  future writes.
3730  **/
3731 static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw)
3732 {
3733         struct e1000_nvm_info *nvm = &hw->nvm;
3734         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3735         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3736         s32 ret_val;
3737         u32 dword = 0;
3738
3739         ret_val = e1000e_update_nvm_checksum_generic(hw);
3740         if (ret_val)
3741                 goto out;
3742
3743         if (nvm->type != e1000_nvm_flash_sw)
3744                 goto out;
3745
3746         nvm->ops.acquire(hw);
3747
3748         /* We're writing to the opposite bank so if we're on bank 1,
3749          * write to bank 0 etc.  We also need to erase the segment that
3750          * is going to be written
3751          */
3752         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3753         if (ret_val) {
3754                 e_dbg("Could not detect valid bank, assuming bank 0\n");
3755                 bank = 0;
3756         }
3757
3758         if (bank == 0) {
3759                 new_bank_offset = nvm->flash_bank_size;
3760                 old_bank_offset = 0;
3761                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3762                 if (ret_val)
3763                         goto release;
3764         } else {
3765                 old_bank_offset = nvm->flash_bank_size;
3766                 new_bank_offset = 0;
3767                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3768                 if (ret_val)
3769                         goto release;
3770         }
3771         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i += 2) {
3772                 /* Determine whether to write the value stored
3773                  * in the other NVM bank or a modified value stored
3774                  * in the shadow RAM
3775                  */
3776                 ret_val = e1000_read_flash_dword_ich8lan(hw,
3777                                                          i + old_bank_offset,
3778                                                          &dword);
3779
3780                 if (dev_spec->shadow_ram[i].modified) {
3781                         dword &= 0xffff0000;
3782                         dword |= (dev_spec->shadow_ram[i].value & 0xffff);
3783                 }
3784                 if (dev_spec->shadow_ram[i + 1].modified) {
3785                         dword &= 0x0000ffff;
3786                         dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff)
3787                                   << 16);
3788                 }
3789                 if (ret_val)
3790                         break;
3791
3792                 /* If the word is 0x13, then make sure the signature bits
3793                  * (15:14) are 11b until the commit has completed.
3794                  * This will allow us to write 10b which indicates the
3795                  * signature is valid.  We want to do this after the write
3796                  * has completed so that we don't mark the segment valid
3797                  * while the write is still in progress
3798                  */
3799                 if (i == E1000_ICH_NVM_SIG_WORD - 1)
3800                         dword |= E1000_ICH_NVM_SIG_MASK << 16;
3801
3802                 /* Convert offset to bytes. */
3803                 act_offset = (i + new_bank_offset) << 1;
3804
3805                 usleep_range(100, 200);
3806
3807                 /* Write the data to the new bank. Offset in words */
3808                 act_offset = i + new_bank_offset;
3809                 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset,
3810                                                                 dword);
3811                 if (ret_val)
3812                         break;
3813         }
3814
3815         /* Don't bother writing the segment valid bits if sector
3816          * programming failed.
3817          */
3818         if (ret_val) {
3819                 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
3820                 e_dbg("Flash commit failed.\n");
3821                 goto release;
3822         }
3823
3824         /* Finally validate the new segment by setting bit 15:14
3825          * to 10b in word 0x13 , this can be done without an
3826          * erase as well since these bits are 11 to start with
3827          * and we need to change bit 14 to 0b
3828          */
3829         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
3830
3831         /*offset in words but we read dword */
3832         --act_offset;
3833         ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
3834
3835         if (ret_val)
3836                 goto release;
3837
3838         dword &= 0xBFFFFFFF;
3839         ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
3840
3841         if (ret_val)
3842                 goto release;
3843
3844         /* And invalidate the previously valid segment by setting
3845          * its signature word (0x13) high_byte to 0b. This can be
3846          * done without an erase because flash erase sets all bits
3847          * to 1's. We can write 1's to 0's without an erase
3848          */
3849         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
3850
3851         /* offset in words but we read dword */
3852         act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1;
3853         ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
3854
3855         if (ret_val)
3856                 goto release;
3857
3858         dword &= 0x00FFFFFF;
3859         ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
3860
3861         if (ret_val)
3862                 goto release;
3863
3864         /* Great!  Everything worked, we can now clear the cached entries. */
3865         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
3866                 dev_spec->shadow_ram[i].modified = false;
3867                 dev_spec->shadow_ram[i].value = 0xFFFF;
3868         }
3869
3870 release:
3871         nvm->ops.release(hw);
3872
3873         /* Reload the EEPROM, or else modifications will not appear
3874          * until after the next adapter reset.
3875          */
3876         if (!ret_val) {
3877                 nvm->ops.reload(hw);
3878                 usleep_range(10000, 20000);
3879         }
3880
3881 out:
3882         if (ret_val)
3883                 e_dbg("NVM update error: %d\n", ret_val);
3884
3885         return ret_val;
3886 }
3887
3888 /**
3889  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
3890  *  @hw: pointer to the HW structure
3891  *
3892  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
3893  *  which writes the checksum to the shadow ram.  The changes in the shadow
3894  *  ram are then committed to the EEPROM by processing each bank at a time
3895  *  checking for the modified bit and writing only the pending changes.
3896  *  After a successful commit, the shadow ram is cleared and is ready for
3897  *  future writes.
3898  **/
3899 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
3900 {
3901         struct e1000_nvm_info *nvm = &hw->nvm;
3902         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3903         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3904         s32 ret_val;
3905         u16 data = 0;
3906
3907         ret_val = e1000e_update_nvm_checksum_generic(hw);
3908         if (ret_val)
3909                 goto out;
3910
3911         if (nvm->type != e1000_nvm_flash_sw)
3912                 goto out;
3913
3914         nvm->ops.acquire(hw);
3915
3916         /* We're writing to the opposite bank so if we're on bank 1,
3917          * write to bank 0 etc.  We also need to erase the segment that
3918          * is going to be written
3919          */
3920         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3921         if (ret_val) {
3922                 e_dbg("Could not detect valid bank, assuming bank 0\n");
3923                 bank = 0;
3924         }
3925
3926         if (bank == 0) {
3927                 new_bank_offset = nvm->flash_bank_size;
3928                 old_bank_offset = 0;
3929                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3930                 if (ret_val)
3931                         goto release;
3932         } else {
3933                 old_bank_offset = nvm->flash_bank_size;
3934                 new_bank_offset = 0;
3935                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3936                 if (ret_val)
3937                         goto release;
3938         }
3939         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
3940                 if (dev_spec->shadow_ram[i].modified) {
3941                         data = dev_spec->shadow_ram[i].value;
3942                 } else {
3943                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
3944                                                                 old_bank_offset,
3945                                                                 &data);
3946                         if (ret_val)
3947                                 break;
3948                 }
3949
3950                 /* If the word is 0x13, then make sure the signature bits
3951                  * (15:14) are 11b until the commit has completed.
3952                  * This will allow us to write 10b which indicates the
3953                  * signature is valid.  We want to do this after the write
3954                  * has completed so that we don't mark the segment valid
3955                  * while the write is still in progress
3956                  */
3957                 if (i == E1000_ICH_NVM_SIG_WORD)
3958                         data |= E1000_ICH_NVM_SIG_MASK;
3959
3960                 /* Convert offset to bytes. */
3961                 act_offset = (i + new_bank_offset) << 1;
3962
3963                 usleep_range(100, 200);
3964                 /* Write the bytes to the new bank. */
3965                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3966                                                                act_offset,
3967                                                                (u8)data);
3968                 if (ret_val)
3969                         break;
3970
3971                 usleep_range(100, 200);
3972                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3973                                                                act_offset + 1,
3974                                                                (u8)(data >> 8));
3975                 if (ret_val)
3976                         break;
3977         }
3978
3979         /* Don't bother writing the segment valid bits if sector
3980          * programming failed.
3981          */
3982         if (ret_val) {
3983                 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
3984                 e_dbg("Flash commit failed.\n");
3985                 goto release;
3986         }
3987
3988         /* Finally validate the new segment by setting bit 15:14
3989          * to 10b in word 0x13 , this can be done without an
3990          * erase as well since these bits are 11 to start with
3991          * and we need to change bit 14 to 0b
3992          */
3993         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
3994         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
3995         if (ret_val)
3996                 goto release;
3997
3998         data &= 0xBFFF;
3999         ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4000                                                        act_offset * 2 + 1,
4001                                                        (u8)(data >> 8));
4002         if (ret_val)
4003                 goto release;
4004
4005         /* And invalidate the previously valid segment by setting
4006          * its signature word (0x13) high_byte to 0b. This can be
4007          * done without an erase because flash erase sets all bits
4008          * to 1's. We can write 1's to 0's without an erase
4009          */
4010         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
4011         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
4012         if (ret_val)
4013                 goto release;
4014
4015         /* Great!  Everything worked, we can now clear the cached entries. */
4016         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
4017                 dev_spec->shadow_ram[i].modified = false;
4018                 dev_spec->shadow_ram[i].value = 0xFFFF;
4019         }
4020
4021 release:
4022         nvm->ops.release(hw);
4023
4024         /* Reload the EEPROM, or else modifications will not appear
4025          * until after the next adapter reset.
4026          */
4027         if (!ret_val) {
4028                 nvm->ops.reload(hw);
4029                 usleep_range(10000, 20000);
4030         }
4031
4032 out:
4033         if (ret_val)
4034                 e_dbg("NVM update error: %d\n", ret_val);
4035
4036         return ret_val;
4037 }
4038
4039 /**
4040  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
4041  *  @hw: pointer to the HW structure
4042  *
4043  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
4044  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
4045  *  calculated, in which case we need to calculate the checksum and set bit 6.
4046  **/
4047 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
4048 {
4049         s32 ret_val;
4050         u16 data;
4051         u16 word;
4052         u16 valid_csum_mask;
4053
4054         /* Read NVM and check Invalid Image CSUM bit.  If this bit is 0,
4055          * the checksum needs to be fixed.  This bit is an indication that
4056          * the NVM was prepared by OEM software and did not calculate
4057          * the checksum...a likely scenario.
4058          */
4059         switch (hw->mac.type) {
4060         case e1000_pch_lpt:
4061         case e1000_pch_spt:
4062         case e1000_pch_cnp:
4063                 word = NVM_COMPAT;
4064                 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
4065                 break;
4066         default:
4067                 word = NVM_FUTURE_INIT_WORD1;
4068                 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
4069                 break;
4070         }
4071
4072         ret_val = e1000_read_nvm(hw, word, 1, &data);
4073         if (ret_val)
4074                 return ret_val;
4075
4076         if (!(data & valid_csum_mask)) {
4077                 data |= valid_csum_mask;
4078                 ret_val = e1000_write_nvm(hw, word, 1, &data);
4079                 if (ret_val)
4080                         return ret_val;
4081                 ret_val = e1000e_update_nvm_checksum(hw);
4082                 if (ret_val)
4083                         return ret_val;
4084         }
4085
4086         return e1000e_validate_nvm_checksum_generic(hw);
4087 }
4088
4089 /**
4090  *  e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
4091  *  @hw: pointer to the HW structure
4092  *
4093  *  To prevent malicious write/erase of the NVM, set it to be read-only
4094  *  so that the hardware ignores all write/erase cycles of the NVM via
4095  *  the flash control registers.  The shadow-ram copy of the NVM will
4096  *  still be updated, however any updates to this copy will not stick
4097  *  across driver reloads.
4098  **/
4099 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
4100 {
4101         struct e1000_nvm_info *nvm = &hw->nvm;
4102         union ich8_flash_protected_range pr0;
4103         union ich8_hws_flash_status hsfsts;
4104         u32 gfpreg;
4105
4106         nvm->ops.acquire(hw);
4107
4108         gfpreg = er32flash(ICH_FLASH_GFPREG);
4109
4110         /* Write-protect GbE Sector of NVM */
4111         pr0.regval = er32flash(ICH_FLASH_PR0);
4112         pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
4113         pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
4114         pr0.range.wpe = true;
4115         ew32flash(ICH_FLASH_PR0, pr0.regval);
4116
4117         /* Lock down a subset of GbE Flash Control Registers, e.g.
4118          * PR0 to prevent the write-protection from being lifted.
4119          * Once FLOCKDN is set, the registers protected by it cannot
4120          * be written until FLOCKDN is cleared by a hardware reset.
4121          */
4122         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4123         hsfsts.hsf_status.flockdn = true;
4124         ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
4125
4126         nvm->ops.release(hw);
4127 }
4128
4129 /**
4130  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
4131  *  @hw: pointer to the HW structure
4132  *  @offset: The offset (in bytes) of the byte/word to read.
4133  *  @size: Size of data to read, 1=byte 2=word
4134  *  @data: The byte(s) to write to the NVM.
4135  *
4136  *  Writes one/two bytes to the NVM using the flash access registers.
4137  **/
4138 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
4139                                           u8 size, u16 data)
4140 {
4141         union ich8_hws_flash_status hsfsts;
4142         union ich8_hws_flash_ctrl hsflctl;
4143         u32 flash_linear_addr;
4144         u32 flash_data = 0;
4145         s32 ret_val;
4146         u8 count = 0;
4147
4148         if (hw->mac.type >= e1000_pch_spt) {
4149                 if (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4150                         return -E1000_ERR_NVM;
4151         } else {
4152                 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4153                         return -E1000_ERR_NVM;
4154         }
4155
4156         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4157                              hw->nvm.flash_base_addr);
4158
4159         do {
4160                 udelay(1);
4161                 /* Steps */
4162                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4163                 if (ret_val)
4164                         break;
4165                 /* In SPT, This register is in Lan memory space, not
4166                  * flash.  Therefore, only 32 bit access is supported
4167                  */
4168                 if (hw->mac.type >= e1000_pch_spt)
4169                         hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
4170                 else
4171                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4172
4173                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
4174                 hsflctl.hsf_ctrl.fldbcount = size - 1;
4175                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4176                 /* In SPT, This register is in Lan memory space,
4177                  * not flash.  Therefore, only 32 bit access is
4178                  * supported
4179                  */
4180                 if (hw->mac.type >= e1000_pch_spt)
4181                         ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
4182                 else
4183                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4184
4185                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4186
4187                 if (size == 1)
4188                         flash_data = (u32)data & 0x00FF;
4189                 else
4190                         flash_data = (u32)data;
4191
4192                 ew32flash(ICH_FLASH_FDATA0, flash_data);
4193
4194                 /* check if FCERR is set to 1 , if set to 1, clear it
4195                  * and try the whole sequence a few more times else done
4196                  */
4197                 ret_val =
4198                     e1000_flash_cycle_ich8lan(hw,
4199                                               ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4200                 if (!ret_val)
4201                         break;
4202
4203                 /* If we're here, then things are most likely
4204                  * completely hosed, but if the error condition
4205                  * is detected, it won't hurt to give it another
4206                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4207                  */
4208                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4209                 if (hsfsts.hsf_status.flcerr)
4210                         /* Repeat for some time before giving up. */
4211                         continue;
4212                 if (!hsfsts.hsf_status.flcdone) {
4213                         e_dbg("Timeout error - flash cycle did not complete.\n");
4214                         break;
4215                 }
4216         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4217
4218         return ret_val;
4219 }
4220
4221 /**
4222 *  e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM
4223 *  @hw: pointer to the HW structure
4224 *  @offset: The offset (in bytes) of the dwords to read.
4225 *  @data: The 4 bytes to write to the NVM.
4226 *
4227 *  Writes one/two/four bytes to the NVM using the flash access registers.
4228 **/
4229 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
4230                                             u32 data)
4231 {
4232         union ich8_hws_flash_status hsfsts;
4233         union ich8_hws_flash_ctrl hsflctl;
4234         u32 flash_linear_addr;
4235         s32 ret_val;
4236         u8 count = 0;
4237
4238         if (hw->mac.type >= e1000_pch_spt) {
4239                 if (offset > ICH_FLASH_LINEAR_ADDR_MASK)
4240                         return -E1000_ERR_NVM;
4241         }
4242         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4243                              hw->nvm.flash_base_addr);
4244         do {
4245                 udelay(1);
4246                 /* Steps */
4247                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4248                 if (ret_val)
4249                         break;
4250
4251                 /* In SPT, This register is in Lan memory space, not
4252                  * flash.  Therefore, only 32 bit access is supported
4253                  */
4254                 if (hw->mac.type >= e1000_pch_spt)
4255                         hsflctl.regval = er32flash(ICH_FLASH_HSFSTS)
4256                             >> 16;
4257                 else
4258                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4259
4260                 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
4261                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4262
4263                 /* In SPT, This register is in Lan memory space,
4264                  * not flash.  Therefore, only 32 bit access is
4265                  * supported
4266                  */
4267                 if (hw->mac.type >= e1000_pch_spt)
4268                         ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
4269                 else
4270                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4271
4272                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4273
4274                 ew32flash(ICH_FLASH_FDATA0, data);
4275
4276                 /* check if FCERR is set to 1 , if set to 1, clear it
4277                  * and try the whole sequence a few more times else done
4278                  */
4279                 ret_val =
4280                    e1000_flash_cycle_ich8lan(hw,
4281                                              ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4282
4283                 if (!ret_val)
4284                         break;
4285
4286                 /* If we're here, then things are most likely
4287                  * completely hosed, but if the error condition
4288                  * is detected, it won't hurt to give it another
4289                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4290                  */
4291                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4292
4293                 if (hsfsts.hsf_status.flcerr)
4294                         /* Repeat for some time before giving up. */
4295                         continue;
4296                 if (!hsfsts.hsf_status.flcdone) {
4297                         e_dbg("Timeout error - flash cycle did not complete.\n");
4298                         break;
4299                 }
4300         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4301
4302         return ret_val;
4303 }
4304
4305 /**
4306  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
4307  *  @hw: pointer to the HW structure
4308  *  @offset: The index of the byte to read.
4309  *  @data: The byte to write to the NVM.
4310  *
4311  *  Writes a single byte to the NVM using the flash access registers.
4312  **/
4313 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
4314                                           u8 data)
4315 {
4316         u16 word = (u16)data;
4317
4318         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
4319 }
4320
4321 /**
4322 *  e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM
4323 *  @hw: pointer to the HW structure
4324 *  @offset: The offset of the word to write.
4325 *  @dword: The dword to write to the NVM.
4326 *
4327 *  Writes a single dword to the NVM using the flash access registers.
4328 *  Goes through a retry algorithm before giving up.
4329 **/
4330 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
4331                                                  u32 offset, u32 dword)
4332 {
4333         s32 ret_val;
4334         u16 program_retries;
4335
4336         /* Must convert word offset into bytes. */
4337         offset <<= 1;
4338         ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4339
4340         if (!ret_val)
4341                 return ret_val;
4342         for (program_retries = 0; program_retries < 100; program_retries++) {
4343                 e_dbg("Retrying Byte %8.8X at offset %u\n", dword, offset);
4344                 usleep_range(100, 200);
4345                 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4346                 if (!ret_val)
4347                         break;
4348         }
4349         if (program_retries == 100)
4350                 return -E1000_ERR_NVM;
4351
4352         return 0;
4353 }
4354
4355 /**
4356  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
4357  *  @hw: pointer to the HW structure
4358  *  @offset: The offset of the byte to write.
4359  *  @byte: The byte to write to the NVM.
4360  *
4361  *  Writes a single byte to the NVM using the flash access registers.
4362  *  Goes through a retry algorithm before giving up.
4363  **/
4364 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
4365                                                 u32 offset, u8 byte)
4366 {
4367         s32 ret_val;
4368         u16 program_retries;
4369
4370         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4371         if (!ret_val)
4372                 return ret_val;
4373
4374         for (program_retries = 0; program_retries < 100; program_retries++) {
4375                 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
4376                 usleep_range(100, 200);
4377                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4378                 if (!ret_val)
4379                         break;
4380         }
4381         if (program_retries == 100)
4382                 return -E1000_ERR_NVM;
4383
4384         return 0;
4385 }
4386
4387 /**
4388  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
4389  *  @hw: pointer to the HW structure
4390  *  @bank: 0 for first bank, 1 for second bank, etc.
4391  *
4392  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
4393  *  bank N is 4096 * N + flash_reg_addr.
4394  **/
4395 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
4396 {
4397         struct e1000_nvm_info *nvm = &hw->nvm;
4398         union ich8_hws_flash_status hsfsts;
4399         union ich8_hws_flash_ctrl hsflctl;
4400         u32 flash_linear_addr;
4401         /* bank size is in 16bit words - adjust to bytes */
4402         u32 flash_bank_size = nvm->flash_bank_size * 2;
4403         s32 ret_val;
4404         s32 count = 0;
4405         s32 j, iteration, sector_size;
4406
4407         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4408
4409         /* Determine HW Sector size: Read BERASE bits of hw flash status
4410          * register
4411          * 00: The Hw sector is 256 bytes, hence we need to erase 16
4412          *     consecutive sectors.  The start index for the nth Hw sector
4413          *     can be calculated as = bank * 4096 + n * 256
4414          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
4415          *     The start index for the nth Hw sector can be calculated
4416          *     as = bank * 4096
4417          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
4418          *     (ich9 only, otherwise error condition)
4419          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
4420          */
4421         switch (hsfsts.hsf_status.berasesz) {
4422         case 0:
4423                 /* Hw sector size 256 */
4424                 sector_size = ICH_FLASH_SEG_SIZE_256;
4425                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
4426                 break;
4427         case 1:
4428                 sector_size = ICH_FLASH_SEG_SIZE_4K;
4429                 iteration = 1;
4430                 break;
4431         case 2:
4432                 sector_size = ICH_FLASH_SEG_SIZE_8K;
4433                 iteration = 1;
4434                 break;
4435         case 3:
4436                 sector_size = ICH_FLASH_SEG_SIZE_64K;
4437                 iteration = 1;
4438                 break;
4439         default:
4440                 return -E1000_ERR_NVM;
4441         }
4442
4443         /* Start with the base address, then add the sector offset. */
4444         flash_linear_addr = hw->nvm.flash_base_addr;
4445         flash_linear_addr += (bank) ? flash_bank_size : 0;
4446
4447         for (j = 0; j < iteration; j++) {
4448                 do {
4449                         u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
4450
4451                         /* Steps */
4452                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
4453                         if (ret_val)
4454                                 return ret_val;
4455
4456                         /* Write a value 11 (block Erase) in Flash
4457                          * Cycle field in hw flash control
4458                          */
4459                         if (hw->mac.type >= e1000_pch_spt)
4460                                 hsflctl.regval =
4461                                     er32flash(ICH_FLASH_HSFSTS) >> 16;
4462                         else
4463                                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4464
4465                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
4466                         if (hw->mac.type >= e1000_pch_spt)
4467                                 ew32flash(ICH_FLASH_HSFSTS,
4468                                           hsflctl.regval << 16);
4469                         else
4470                                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4471
4472                         /* Write the last 24 bits of an index within the
4473                          * block into Flash Linear address field in Flash
4474                          * Address.
4475                          */
4476                         flash_linear_addr += (j * sector_size);
4477                         ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4478
4479                         ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
4480                         if (!ret_val)
4481                                 break;
4482
4483                         /* Check if FCERR is set to 1.  If 1,
4484                          * clear it and try the whole sequence
4485                          * a few more times else Done
4486                          */
4487                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4488                         if (hsfsts.hsf_status.flcerr)
4489                                 /* repeat for some time before giving up */
4490                                 continue;
4491                         else if (!hsfsts.hsf_status.flcdone)
4492                                 return ret_val;
4493                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
4494         }
4495
4496         return 0;
4497 }
4498
4499 /**
4500  *  e1000_valid_led_default_ich8lan - Set the default LED settings
4501  *  @hw: pointer to the HW structure
4502  *  @data: Pointer to the LED settings
4503  *
4504  *  Reads the LED default settings from the NVM to data.  If the NVM LED
4505  *  settings is all 0's or F's, set the LED default to a valid LED default
4506  *  setting.
4507  **/
4508 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
4509 {
4510         s32 ret_val;
4511
4512         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
4513         if (ret_val) {
4514                 e_dbg("NVM Read Error\n");
4515                 return ret_val;
4516         }
4517
4518         if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
4519                 *data = ID_LED_DEFAULT_ICH8LAN;
4520
4521         return 0;
4522 }
4523
4524 /**
4525  *  e1000_id_led_init_pchlan - store LED configurations
4526  *  @hw: pointer to the HW structure
4527  *
4528  *  PCH does not control LEDs via the LEDCTL register, rather it uses
4529  *  the PHY LED configuration register.
4530  *
4531  *  PCH also does not have an "always on" or "always off" mode which
4532  *  complicates the ID feature.  Instead of using the "on" mode to indicate
4533  *  in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()),
4534  *  use "link_up" mode.  The LEDs will still ID on request if there is no
4535  *  link based on logic in e1000_led_[on|off]_pchlan().
4536  **/
4537 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
4538 {
4539         struct e1000_mac_info *mac = &hw->mac;
4540         s32 ret_val;
4541         const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
4542         const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
4543         u16 data, i, temp, shift;
4544
4545         /* Get default ID LED modes */
4546         ret_val = hw->nvm.ops.valid_led_default(hw, &data);
4547         if (ret_val)
4548                 return ret_val;
4549
4550         mac->ledctl_default = er32(LEDCTL);
4551         mac->ledctl_mode1 = mac->ledctl_default;
4552         mac->ledctl_mode2 = mac->ledctl_default;
4553
4554         for (i = 0; i < 4; i++) {
4555                 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
4556                 shift = (i * 5);
4557                 switch (temp) {
4558                 case ID_LED_ON1_DEF2:
4559                 case ID_LED_ON1_ON2:
4560                 case ID_LED_ON1_OFF2:
4561                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4562                         mac->ledctl_mode1 |= (ledctl_on << shift);
4563                         break;
4564                 case ID_LED_OFF1_DEF2:
4565                 case ID_LED_OFF1_ON2:
4566                 case ID_LED_OFF1_OFF2:
4567                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4568                         mac->ledctl_mode1 |= (ledctl_off << shift);
4569                         break;
4570                 default:
4571                         /* Do nothing */
4572                         break;
4573                 }
4574                 switch (temp) {
4575                 case ID_LED_DEF1_ON2:
4576                 case ID_LED_ON1_ON2:
4577                 case ID_LED_OFF1_ON2:
4578                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4579                         mac->ledctl_mode2 |= (ledctl_on << shift);
4580                         break;
4581                 case ID_LED_DEF1_OFF2:
4582                 case ID_LED_ON1_OFF2:
4583                 case ID_LED_OFF1_OFF2:
4584                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4585                         mac->ledctl_mode2 |= (ledctl_off << shift);
4586                         break;
4587                 default:
4588                         /* Do nothing */
4589                         break;
4590                 }
4591         }
4592
4593         return 0;
4594 }
4595
4596 /**
4597  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
4598  *  @hw: pointer to the HW structure
4599  *
4600  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
4601  *  register, so the the bus width is hard coded.
4602  **/
4603 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
4604 {
4605         struct e1000_bus_info *bus = &hw->bus;
4606         s32 ret_val;
4607
4608         ret_val = e1000e_get_bus_info_pcie(hw);
4609
4610         /* ICH devices are "PCI Express"-ish.  They have
4611          * a configuration space, but do not contain
4612          * PCI Express Capability registers, so bus width
4613          * must be hardcoded.
4614          */
4615         if (bus->width == e1000_bus_width_unknown)
4616                 bus->width = e1000_bus_width_pcie_x1;
4617
4618         return ret_val;
4619 }
4620
4621 /**
4622  *  e1000_reset_hw_ich8lan - Reset the hardware
4623  *  @hw: pointer to the HW structure
4624  *
4625  *  Does a full reset of the hardware which includes a reset of the PHY and
4626  *  MAC.
4627  **/
4628 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
4629 {
4630         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4631         u16 kum_cfg;
4632         u32 ctrl, reg;
4633         s32 ret_val;
4634
4635         /* Prevent the PCI-E bus from sticking if there is no TLP connection
4636          * on the last TLP read/write transaction when MAC is reset.
4637          */
4638         ret_val = e1000e_disable_pcie_master(hw);
4639         if (ret_val)
4640                 e_dbg("PCI-E Master disable polling has failed.\n");
4641
4642         e_dbg("Masking off all interrupts\n");
4643         ew32(IMC, 0xffffffff);
4644
4645         /* Disable the Transmit and Receive units.  Then delay to allow
4646          * any pending transactions to complete before we hit the MAC
4647          * with the global reset.
4648          */
4649         ew32(RCTL, 0);
4650         ew32(TCTL, E1000_TCTL_PSP);
4651         e1e_flush();
4652
4653         usleep_range(10000, 20000);
4654
4655         /* Workaround for ICH8 bit corruption issue in FIFO memory */
4656         if (hw->mac.type == e1000_ich8lan) {
4657                 /* Set Tx and Rx buffer allocation to 8k apiece. */
4658                 ew32(PBA, E1000_PBA_8K);
4659                 /* Set Packet Buffer Size to 16k. */
4660                 ew32(PBS, E1000_PBS_16K);
4661         }
4662
4663         if (hw->mac.type == e1000_pchlan) {
4664                 /* Save the NVM K1 bit setting */
4665                 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
4666                 if (ret_val)
4667                         return ret_val;
4668
4669                 if (kum_cfg & E1000_NVM_K1_ENABLE)
4670                         dev_spec->nvm_k1_enabled = true;
4671                 else
4672                         dev_spec->nvm_k1_enabled = false;
4673         }
4674
4675         ctrl = er32(CTRL);
4676
4677         if (!hw->phy.ops.check_reset_block(hw)) {
4678                 /* Full-chip reset requires MAC and PHY reset at the same
4679                  * time to make sure the interface between MAC and the
4680                  * external PHY is reset.
4681                  */
4682                 ctrl |= E1000_CTRL_PHY_RST;
4683
4684                 /* Gate automatic PHY configuration by hardware on
4685                  * non-managed 82579
4686                  */
4687                 if ((hw->mac.type == e1000_pch2lan) &&
4688                     !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
4689                         e1000_gate_hw_phy_config_ich8lan(hw, true);
4690         }
4691         ret_val = e1000_acquire_swflag_ich8lan(hw);
4692         e_dbg("Issuing a global reset to ich8lan\n");
4693         ew32(CTRL, (ctrl | E1000_CTRL_RST));
4694         /* cannot issue a flush here because it hangs the hardware */
4695         msleep(20);
4696
4697         /* Set Phy Config Counter to 50msec */
4698         if (hw->mac.type == e1000_pch2lan) {
4699                 reg = er32(FEXTNVM3);
4700                 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
4701                 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
4702                 ew32(FEXTNVM3, reg);
4703         }
4704
4705         if (!ret_val)
4706                 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
4707
4708         if (ctrl & E1000_CTRL_PHY_RST) {
4709                 ret_val = hw->phy.ops.get_cfg_done(hw);
4710                 if (ret_val)
4711                         return ret_val;
4712
4713                 ret_val = e1000_post_phy_reset_ich8lan(hw);
4714                 if (ret_val)
4715                         return ret_val;
4716         }
4717
4718         /* For PCH, this write will make sure that any noise
4719          * will be detected as a CRC error and be dropped rather than show up
4720          * as a bad packet to the DMA engine.
4721          */
4722         if (hw->mac.type == e1000_pchlan)
4723                 ew32(CRC_OFFSET, 0x65656565);
4724
4725         ew32(IMC, 0xffffffff);
4726         er32(ICR);
4727
4728         reg = er32(KABGTXD);
4729         reg |= E1000_KABGTXD_BGSQLBIAS;
4730         ew32(KABGTXD, reg);
4731
4732         return 0;
4733 }
4734
4735 /**
4736  *  e1000_init_hw_ich8lan - Initialize the hardware
4737  *  @hw: pointer to the HW structure
4738  *
4739  *  Prepares the hardware for transmit and receive by doing the following:
4740  *   - initialize hardware bits
4741  *   - initialize LED identification
4742  *   - setup receive address registers
4743  *   - setup flow control
4744  *   - setup transmit descriptors
4745  *   - clear statistics
4746  **/
4747 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
4748 {
4749         struct e1000_mac_info *mac = &hw->mac;
4750         u32 ctrl_ext, txdctl, snoop;
4751         s32 ret_val;
4752         u16 i;
4753
4754         e1000_initialize_hw_bits_ich8lan(hw);
4755
4756         /* Initialize identification LED */
4757         ret_val = mac->ops.id_led_init(hw);
4758         /* An error is not fatal and we should not stop init due to this */
4759         if (ret_val)
4760                 e_dbg("Error initializing identification LED\n");
4761
4762         /* Setup the receive address. */
4763         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
4764
4765         /* Zero out the Multicast HASH table */
4766         e_dbg("Zeroing the MTA\n");
4767         for (i = 0; i < mac->mta_reg_count; i++)
4768                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
4769
4770         /* The 82578 Rx buffer will stall if wakeup is enabled in host and
4771          * the ME.  Disable wakeup by clearing the host wakeup bit.
4772          * Reset the phy after disabling host wakeup to reset the Rx buffer.
4773          */
4774         if (hw->phy.type == e1000_phy_82578) {
4775                 e1e_rphy(hw, BM_PORT_GEN_CFG, &i);
4776                 i &= ~BM_WUC_HOST_WU_BIT;
4777                 e1e_wphy(hw, BM_PORT_GEN_CFG, i);
4778                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
4779                 if (ret_val)
4780                         return ret_val;
4781         }
4782
4783         /* Setup link and flow control */
4784         ret_val = mac->ops.setup_link(hw);
4785
4786         /* Set the transmit descriptor write-back policy for both queues */
4787         txdctl = er32(TXDCTL(0));
4788         txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4789                   E1000_TXDCTL_FULL_TX_DESC_WB);
4790         txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4791                   E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4792         ew32(TXDCTL(0), txdctl);
4793         txdctl = er32(TXDCTL(1));
4794         txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4795                   E1000_TXDCTL_FULL_TX_DESC_WB);
4796         txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4797                   E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4798         ew32(TXDCTL(1), txdctl);
4799
4800         /* ICH8 has opposite polarity of no_snoop bits.
4801          * By default, we should use snoop behavior.
4802          */
4803         if (mac->type == e1000_ich8lan)
4804                 snoop = PCIE_ICH8_SNOOP_ALL;
4805         else
4806                 snoop = (u32)~(PCIE_NO_SNOOP_ALL);
4807         e1000e_set_pcie_no_snoop(hw, snoop);
4808
4809         ctrl_ext = er32(CTRL_EXT);
4810         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
4811         ew32(CTRL_EXT, ctrl_ext);
4812
4813         /* Clear all of the statistics registers (clear on read).  It is
4814          * important that we do this after we have tried to establish link
4815          * because the symbol error count will increment wildly if there
4816          * is no link.
4817          */
4818         e1000_clear_hw_cntrs_ich8lan(hw);
4819
4820         return ret_val;
4821 }
4822
4823 /**
4824  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
4825  *  @hw: pointer to the HW structure
4826  *
4827  *  Sets/Clears required hardware bits necessary for correctly setting up the
4828  *  hardware for transmit and receive.
4829  **/
4830 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
4831 {
4832         u32 reg;
4833
4834         /* Extended Device Control */
4835         reg = er32(CTRL_EXT);
4836         reg |= BIT(22);
4837         /* Enable PHY low-power state when MAC is at D3 w/o WoL */
4838         if (hw->mac.type >= e1000_pchlan)
4839                 reg |= E1000_CTRL_EXT_PHYPDEN;
4840         ew32(CTRL_EXT, reg);
4841
4842         /* Transmit Descriptor Control 0 */
4843         reg = er32(TXDCTL(0));
4844         reg |= BIT(22);
4845         ew32(TXDCTL(0), reg);
4846
4847         /* Transmit Descriptor Control 1 */
4848         reg = er32(TXDCTL(1));
4849         reg |= BIT(22);
4850         ew32(TXDCTL(1), reg);
4851
4852         /* Transmit Arbitration Control 0 */
4853         reg = er32(TARC(0));
4854         if (hw->mac.type == e1000_ich8lan)
4855                 reg |= BIT(28) | BIT(29);
4856         reg |= BIT(23) | BIT(24) | BIT(26) | BIT(27);
4857         ew32(TARC(0), reg);
4858
4859         /* Transmit Arbitration Control 1 */
4860         reg = er32(TARC(1));
4861         if (er32(TCTL) & E1000_TCTL_MULR)
4862                 reg &= ~BIT(28);
4863         else
4864                 reg |= BIT(28);
4865         reg |= BIT(24) | BIT(26) | BIT(30);
4866         ew32(TARC(1), reg);
4867
4868         /* Device Status */
4869         if (hw->mac.type == e1000_ich8lan) {
4870                 reg = er32(STATUS);
4871                 reg &= ~BIT(31);
4872                 ew32(STATUS, reg);
4873         }
4874
4875         /* work-around descriptor data corruption issue during nfs v2 udp
4876          * traffic, just disable the nfs filtering capability
4877          */
4878         reg = er32(RFCTL);
4879         reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
4880
4881         /* Disable IPv6 extension header parsing because some malformed
4882          * IPv6 headers can hang the Rx.
4883          */
4884         if (hw->mac.type == e1000_ich8lan)
4885                 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
4886         ew32(RFCTL, reg);
4887
4888         /* Enable ECC on Lynxpoint */
4889         if (hw->mac.type >= e1000_pch_lpt) {
4890                 reg = er32(PBECCSTS);
4891                 reg |= E1000_PBECCSTS_ECC_ENABLE;
4892                 ew32(PBECCSTS, reg);
4893
4894                 reg = er32(CTRL);
4895                 reg |= E1000_CTRL_MEHE;
4896                 ew32(CTRL, reg);
4897         }
4898 }
4899
4900 /**
4901  *  e1000_setup_link_ich8lan - Setup flow control and link settings
4902  *  @hw: pointer to the HW structure
4903  *
4904  *  Determines which flow control settings to use, then configures flow
4905  *  control.  Calls the appropriate media-specific link configuration
4906  *  function.  Assuming the adapter has a valid link partner, a valid link
4907  *  should be established.  Assumes the hardware has previously been reset
4908  *  and the transmitter and receiver are not enabled.
4909  **/
4910 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
4911 {
4912         s32 ret_val;
4913
4914         if (hw->phy.ops.check_reset_block(hw))
4915                 return 0;
4916
4917         /* ICH parts do not have a word in the NVM to determine
4918          * the default flow control setting, so we explicitly
4919          * set it to full.
4920          */
4921         if (hw->fc.requested_mode == e1000_fc_default) {
4922                 /* Workaround h/w hang when Tx flow control enabled */
4923                 if (hw->mac.type == e1000_pchlan)
4924                         hw->fc.requested_mode = e1000_fc_rx_pause;
4925                 else
4926                         hw->fc.requested_mode = e1000_fc_full;
4927         }
4928
4929         /* Save off the requested flow control mode for use later.  Depending
4930          * on the link partner's capabilities, we may or may not use this mode.
4931          */
4932         hw->fc.current_mode = hw->fc.requested_mode;
4933
4934         e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);
4935
4936         /* Continue to configure the copper link. */
4937         ret_val = hw->mac.ops.setup_physical_interface(hw);
4938         if (ret_val)
4939                 return ret_val;
4940
4941         ew32(FCTTV, hw->fc.pause_time);
4942         if ((hw->phy.type == e1000_phy_82578) ||
4943             (hw->phy.type == e1000_phy_82579) ||
4944             (hw->phy.type == e1000_phy_i217) ||
4945             (hw->phy.type == e1000_phy_82577)) {
4946                 ew32(FCRTV_PCH, hw->fc.refresh_time);
4947
4948                 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
4949                                    hw->fc.pause_time);
4950                 if (ret_val)
4951                         return ret_val;
4952         }
4953
4954         return e1000e_set_fc_watermarks(hw);
4955 }
4956
4957 /**
4958  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
4959  *  @hw: pointer to the HW structure
4960  *
4961  *  Configures the kumeran interface to the PHY to wait the appropriate time
4962  *  when polling the PHY, then call the generic setup_copper_link to finish
4963  *  configuring the copper link.
4964  **/
4965 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
4966 {
4967         u32 ctrl;
4968         s32 ret_val;
4969         u16 reg_data;
4970
4971         ctrl = er32(CTRL);
4972         ctrl |= E1000_CTRL_SLU;
4973         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
4974         ew32(CTRL, ctrl);
4975
4976         /* Set the mac to wait the maximum time between each iteration
4977          * and increase the max iterations when polling the phy;
4978          * this fixes erroneous timeouts at 10Mbps.
4979          */
4980         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
4981         if (ret_val)
4982                 return ret_val;
4983         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
4984                                        &reg_data);
4985         if (ret_val)
4986                 return ret_val;
4987         reg_data |= 0x3F;
4988         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
4989                                         reg_data);
4990         if (ret_val)
4991                 return ret_val;
4992
4993         switch (hw->phy.type) {
4994         case e1000_phy_igp_3:
4995                 ret_val = e1000e_copper_link_setup_igp(hw);
4996                 if (ret_val)
4997                         return ret_val;
4998                 break;
4999         case e1000_phy_bm:
5000         case e1000_phy_82578:
5001                 ret_val = e1000e_copper_link_setup_m88(hw);
5002                 if (ret_val)
5003                         return ret_val;
5004                 break;
5005         case e1000_phy_82577:
5006         case e1000_phy_82579:
5007                 ret_val = e1000_copper_link_setup_82577(hw);
5008                 if (ret_val)
5009                         return ret_val;
5010                 break;
5011         case e1000_phy_ife:
5012                 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
5013                 if (ret_val)
5014                         return ret_val;
5015
5016                 reg_data &= ~IFE_PMC_AUTO_MDIX;
5017
5018                 switch (hw->phy.mdix) {
5019                 case 1:
5020                         reg_data &= ~IFE_PMC_FORCE_MDIX;
5021                         break;
5022                 case 2:
5023                         reg_data |= IFE_PMC_FORCE_MDIX;
5024                         break;
5025                 case 0:
5026                 default:
5027                         reg_data |= IFE_PMC_AUTO_MDIX;
5028                         break;
5029                 }
5030                 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
5031                 if (ret_val)
5032                         return ret_val;
5033                 break;
5034         default:
5035                 break;
5036         }
5037
5038         return e1000e_setup_copper_link(hw);
5039 }
5040
5041 /**
5042  *  e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
5043  *  @hw: pointer to the HW structure
5044  *
5045  *  Calls the PHY specific link setup function and then calls the
5046  *  generic setup_copper_link to finish configuring the link for
5047  *  Lynxpoint PCH devices
5048  **/
5049 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
5050 {
5051         u32 ctrl;
5052         s32 ret_val;
5053
5054         ctrl = er32(CTRL);
5055         ctrl |= E1000_CTRL_SLU;
5056         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5057         ew32(CTRL, ctrl);
5058
5059         ret_val = e1000_copper_link_setup_82577(hw);
5060         if (ret_val)
5061                 return ret_val;
5062
5063         return e1000e_setup_copper_link(hw);
5064 }
5065
5066 /**
5067  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
5068  *  @hw: pointer to the HW structure
5069  *  @speed: pointer to store current link speed
5070  *  @duplex: pointer to store the current link duplex
5071  *
5072  *  Calls the generic get_speed_and_duplex to retrieve the current link
5073  *  information and then calls the Kumeran lock loss workaround for links at
5074  *  gigabit speeds.
5075  **/
5076 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
5077                                           u16 *duplex)
5078 {
5079         s32 ret_val;
5080
5081         ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
5082         if (ret_val)
5083                 return ret_val;
5084
5085         if ((hw->mac.type == e1000_ich8lan) &&
5086             (hw->phy.type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
5087                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
5088         }
5089
5090         return ret_val;
5091 }
5092
5093 /**
5094  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
5095  *  @hw: pointer to the HW structure
5096  *
5097  *  Work-around for 82566 Kumeran PCS lock loss:
5098  *  On link status change (i.e. PCI reset, speed change) and link is up and
5099  *  speed is gigabit-
5100  *    0) if workaround is optionally disabled do nothing
5101  *    1) wait 1ms for Kumeran link to come up
5102  *    2) check Kumeran Diagnostic register PCS lock loss bit
5103  *    3) if not set the link is locked (all is good), otherwise...
5104  *    4) reset the PHY
5105  *    5) repeat up to 10 times
5106  *  Note: this is only called for IGP3 copper when speed is 1gb.
5107  **/
5108 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
5109 {
5110         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5111         u32 phy_ctrl;
5112         s32 ret_val;
5113         u16 i, data;
5114         bool link;
5115
5116         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
5117                 return 0;
5118
5119         /* Make sure link is up before proceeding.  If not just return.
5120          * Attempting this while link is negotiating fouled up link
5121          * stability
5122          */
5123         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
5124         if (!link)
5125                 return 0;
5126
5127         for (i = 0; i < 10; i++) {
5128                 /* read once to clear */
5129                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
5130                 if (ret_val)
5131                         return ret_val;
5132                 /* and again to get new status */
5133                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
5134                 if (ret_val)
5135                         return ret_val;
5136
5137                 /* check for PCS lock */
5138                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
5139                         return 0;
5140
5141                 /* Issue PHY reset */
5142                 e1000_phy_hw_reset(hw);
5143                 mdelay(5);
5144         }
5145         /* Disable GigE link negotiation */
5146         phy_ctrl = er32(PHY_CTRL);
5147         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
5148                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5149         ew32(PHY_CTRL, phy_ctrl);
5150
5151         /* Call gig speed drop workaround on Gig disable before accessing
5152          * any PHY registers
5153          */
5154         e1000e_gig_downshift_workaround_ich8lan(hw);
5155
5156         /* unable to acquire PCS lock */
5157         return -E1000_ERR_PHY;
5158 }
5159
5160 /**
5161  *  e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
5162  *  @hw: pointer to the HW structure
5163  *  @state: boolean value used to set the current Kumeran workaround state
5164  *
5165  *  If ICH8, set the current Kumeran workaround state (enabled - true
5166  *  /disabled - false).
5167  **/
5168 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
5169                                                   bool state)
5170 {
5171         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5172
5173         if (hw->mac.type != e1000_ich8lan) {
5174                 e_dbg("Workaround applies to ICH8 only.\n");
5175                 return;
5176         }
5177
5178         dev_spec->kmrn_lock_loss_workaround_enabled = state;
5179 }
5180
5181 /**
5182  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
5183  *  @hw: pointer to the HW structure
5184  *
5185  *  Workaround for 82566 power-down on D3 entry:
5186  *    1) disable gigabit link
5187  *    2) write VR power-down enable
5188  *    3) read it back
5189  *  Continue if successful, else issue LCD reset and repeat
5190  **/
5191 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
5192 {
5193         u32 reg;
5194         u16 data;
5195         u8 retry = 0;
5196
5197         if (hw->phy.type != e1000_phy_igp_3)
5198                 return;
5199
5200         /* Try the workaround twice (if needed) */
5201         do {
5202                 /* Disable link */
5203                 reg = er32(PHY_CTRL);
5204                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
5205                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5206                 ew32(PHY_CTRL, reg);
5207
5208                 /* Call gig speed drop workaround on Gig disable before
5209                  * accessing any PHY registers
5210                  */
5211                 if (hw->mac.type == e1000_ich8lan)
5212                         e1000e_gig_downshift_workaround_ich8lan(hw);
5213
5214                 /* Write VR power-down enable */
5215                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
5216                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5217                 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
5218
5219                 /* Read it back and test */
5220                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
5221                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5222                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
5223                         break;
5224
5225                 /* Issue PHY reset and repeat at most one more time */
5226                 reg = er32(CTRL);
5227                 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
5228                 retry++;
5229         } while (retry);
5230 }
5231
5232 /**
5233  *  e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
5234  *  @hw: pointer to the HW structure
5235  *
5236  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
5237  *  LPLU, Gig disable, MDIC PHY reset):
5238  *    1) Set Kumeran Near-end loopback
5239  *    2) Clear Kumeran Near-end loopback
5240  *  Should only be called for ICH8[m] devices with any 1G Phy.
5241  **/
5242 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
5243 {
5244         s32 ret_val;
5245         u16 reg_data;
5246
5247         if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife))
5248                 return;
5249
5250         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5251                                        &reg_data);
5252         if (ret_val)
5253                 return;
5254         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
5255         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5256                                         reg_data);
5257         if (ret_val)
5258                 return;
5259         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
5260         e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, reg_data);
5261 }
5262
5263 /**
5264  *  e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
5265  *  @hw: pointer to the HW structure
5266  *
5267  *  During S0 to Sx transition, it is possible the link remains at gig
5268  *  instead of negotiating to a lower speed.  Before going to Sx, set
5269  *  'Gig Disable' to force link speed negotiation to a lower speed based on
5270  *  the LPLU setting in the NVM or custom setting.  For PCH and newer parts,
5271  *  the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
5272  *  needs to be written.
5273  *  Parts that support (and are linked to a partner which support) EEE in
5274  *  100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
5275  *  than 10Mbps w/o EEE.
5276  **/
5277 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
5278 {
5279         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5280         u32 phy_ctrl;
5281         s32 ret_val;
5282
5283         phy_ctrl = er32(PHY_CTRL);
5284         phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
5285
5286         if (hw->phy.type == e1000_phy_i217) {
5287                 u16 phy_reg, device_id = hw->adapter->pdev->device;
5288
5289                 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
5290                     (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
5291                     (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
5292                     (device_id == E1000_DEV_ID_PCH_I218_V3) ||
5293                     (hw->mac.type >= e1000_pch_spt)) {
5294                         u32 fextnvm6 = er32(FEXTNVM6);
5295
5296                         ew32(FEXTNVM6, fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
5297                 }
5298
5299                 ret_val = hw->phy.ops.acquire(hw);
5300                 if (ret_val)
5301                         goto out;
5302
5303                 if (!dev_spec->eee_disable) {
5304                         u16 eee_advert;
5305
5306                         ret_val =
5307                             e1000_read_emi_reg_locked(hw,
5308                                                       I217_EEE_ADVERTISEMENT,
5309                                                       &eee_advert);
5310                         if (ret_val)
5311                                 goto release;
5312
5313                         /* Disable LPLU if both link partners support 100BaseT
5314                          * EEE and 100Full is advertised on both ends of the
5315                          * link, and enable Auto Enable LPI since there will
5316                          * be no driver to enable LPI while in Sx.
5317                          */
5318                         if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
5319                             (dev_spec->eee_lp_ability &
5320                              I82579_EEE_100_SUPPORTED) &&
5321                             (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {
5322                                 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
5323                                               E1000_PHY_CTRL_NOND0A_LPLU);
5324
5325                                 /* Set Auto Enable LPI after link up */
5326                                 e1e_rphy_locked(hw,
5327                                                 I217_LPI_GPIO_CTRL, &phy_reg);
5328                                 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5329                                 e1e_wphy_locked(hw,
5330                                                 I217_LPI_GPIO_CTRL, phy_reg);
5331                         }
5332                 }
5333
5334                 /* For i217 Intel Rapid Start Technology support,
5335                  * when the system is going into Sx and no manageability engine
5336                  * is present, the driver must configure proxy to reset only on
5337                  * power good.  LPI (Low Power Idle) state must also reset only
5338                  * on power good, as well as the MTA (Multicast table array).
5339                  * The SMBus release must also be disabled on LCD reset.
5340                  */
5341                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
5342                         /* Enable proxy to reset only on power good. */
5343                         e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg);
5344                         phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
5345                         e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg);
5346
5347                         /* Set bit enable LPI (EEE) to reset only on
5348                          * power good.
5349                          */
5350                         e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg);
5351                         phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
5352                         e1e_wphy_locked(hw, I217_SxCTRL, phy_reg);
5353
5354                         /* Disable the SMB release on LCD reset. */
5355                         e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
5356                         phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
5357                         e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
5358                 }
5359
5360                 /* Enable MTA to reset for Intel Rapid Start Technology
5361                  * Support
5362                  */
5363                 e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
5364                 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
5365                 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
5366
5367 release:
5368                 hw->phy.ops.release(hw);
5369         }
5370 out:
5371         ew32(PHY_CTRL, phy_ctrl);
5372
5373         if (hw->mac.type == e1000_ich8lan)
5374                 e1000e_gig_downshift_workaround_ich8lan(hw);
5375
5376         if (hw->mac.type >= e1000_pchlan) {
5377                 e1000_oem_bits_config_ich8lan(hw, false);
5378
5379                 /* Reset PHY to activate OEM bits on 82577/8 */
5380                 if (hw->mac.type == e1000_pchlan)
5381                         e1000e_phy_hw_reset_generic(hw);
5382
5383                 ret_val = hw->phy.ops.acquire(hw);
5384                 if (ret_val)
5385                         return;
5386                 e1000_write_smbus_addr(hw);
5387                 hw->phy.ops.release(hw);
5388         }
5389 }
5390
5391 /**
5392  *  e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
5393  *  @hw: pointer to the HW structure
5394  *
5395  *  During Sx to S0 transitions on non-managed devices or managed devices
5396  *  on which PHY resets are not blocked, if the PHY registers cannot be
5397  *  accessed properly by the s/w toggle the LANPHYPC value to power cycle
5398  *  the PHY.
5399  *  On i217, setup Intel Rapid Start Technology.
5400  **/
5401 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
5402 {
5403         s32 ret_val;
5404
5405         if (hw->mac.type < e1000_pch2lan)
5406                 return;
5407
5408         ret_val = e1000_init_phy_workarounds_pchlan(hw);
5409         if (ret_val) {
5410                 e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val);
5411                 return;
5412         }
5413
5414         /* For i217 Intel Rapid Start Technology support when the system
5415          * is transitioning from Sx and no manageability engine is present
5416          * configure SMBus to restore on reset, disable proxy, and enable
5417          * the reset on MTA (Multicast table array).
5418          */
5419         if (hw->phy.type == e1000_phy_i217) {
5420                 u16 phy_reg;
5421
5422                 ret_val = hw->phy.ops.acquire(hw);
5423                 if (ret_val) {
5424                         e_dbg("Failed to setup iRST\n");
5425                         return;
5426                 }
5427
5428                 /* Clear Auto Enable LPI after link up */
5429                 e1e_rphy_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
5430                 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5431                 e1e_wphy_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
5432
5433                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
5434                         /* Restore clear on SMB if no manageability engine
5435                          * is present
5436                          */
5437                         ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
5438                         if (ret_val)
5439                                 goto release;
5440                         phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
5441                         e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
5442
5443                         /* Disable Proxy */
5444                         e1e_wphy_locked(hw, I217_PROXY_CTRL, 0);
5445                 }
5446                 /* Enable reset on MTA */
5447                 ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
5448                 if (ret_val)
5449                         goto release;
5450                 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
5451                 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
5452 release:
5453                 if (ret_val)
5454                         e_dbg("Error %d in resume workarounds\n", ret_val);
5455                 hw->phy.ops.release(hw);
5456         }
5457 }
5458
5459 /**
5460  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
5461  *  @hw: pointer to the HW structure
5462  *
5463  *  Return the LED back to the default configuration.
5464  **/
5465 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
5466 {
5467         if (hw->phy.type == e1000_phy_ife)
5468                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
5469
5470         ew32(LEDCTL, hw->mac.ledctl_default);
5471         return 0;
5472 }
5473
5474 /**
5475  *  e1000_led_on_ich8lan - Turn LEDs on
5476  *  @hw: pointer to the HW structure
5477  *
5478  *  Turn on the LEDs.
5479  **/
5480 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
5481 {
5482         if (hw->phy.type == e1000_phy_ife)
5483                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5484                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
5485
5486         ew32(LEDCTL, hw->mac.ledctl_mode2);
5487         return 0;
5488 }
5489
5490 /**
5491  *  e1000_led_off_ich8lan - Turn LEDs off
5492  *  @hw: pointer to the HW structure
5493  *
5494  *  Turn off the LEDs.
5495  **/
5496 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
5497 {
5498         if (hw->phy.type == e1000_phy_ife)
5499                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5500                                 (IFE_PSCL_PROBE_MODE |
5501                                  IFE_PSCL_PROBE_LEDS_OFF));
5502
5503         ew32(LEDCTL, hw->mac.ledctl_mode1);
5504         return 0;
5505 }
5506
5507 /**
5508  *  e1000_setup_led_pchlan - Configures SW controllable LED
5509  *  @hw: pointer to the HW structure
5510  *
5511  *  This prepares the SW controllable LED for use.
5512  **/
5513 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
5514 {
5515         return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);
5516 }
5517
5518 /**
5519  *  e1000_cleanup_led_pchlan - Restore the default LED operation
5520  *  @hw: pointer to the HW structure
5521  *
5522  *  Return the LED back to the default configuration.
5523  **/
5524 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
5525 {
5526         return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);
5527 }
5528
5529 /**
5530  *  e1000_led_on_pchlan - Turn LEDs on
5531  *  @hw: pointer to the HW structure
5532  *
5533  *  Turn on the LEDs.
5534  **/
5535 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
5536 {
5537         u16 data = (u16)hw->mac.ledctl_mode2;
5538         u32 i, led;
5539
5540         /* If no link, then turn LED on by setting the invert bit
5541          * for each LED that's mode is "link_up" in ledctl_mode2.
5542          */
5543         if (!(er32(STATUS) & E1000_STATUS_LU)) {
5544                 for (i = 0; i < 3; i++) {
5545                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5546                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
5547                             E1000_LEDCTL_MODE_LINK_UP)
5548                                 continue;
5549                         if (led & E1000_PHY_LED0_IVRT)
5550                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5551                         else
5552                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5553                 }
5554         }
5555
5556         return e1e_wphy(hw, HV_LED_CONFIG, data);
5557 }
5558
5559 /**
5560  *  e1000_led_off_pchlan - Turn LEDs off
5561  *  @hw: pointer to the HW structure
5562  *
5563  *  Turn off the LEDs.
5564  **/
5565 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
5566 {
5567         u16 data = (u16)hw->mac.ledctl_mode1;
5568         u32 i, led;
5569
5570         /* If no link, then turn LED off by clearing the invert bit
5571          * for each LED that's mode is "link_up" in ledctl_mode1.
5572          */
5573         if (!(er32(STATUS) & E1000_STATUS_LU)) {
5574                 for (i = 0; i < 3; i++) {
5575                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5576                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
5577                             E1000_LEDCTL_MODE_LINK_UP)
5578                                 continue;
5579                         if (led & E1000_PHY_LED0_IVRT)
5580                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5581                         else
5582                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5583                 }
5584         }
5585
5586         return e1e_wphy(hw, HV_LED_CONFIG, data);
5587 }
5588
5589 /**
5590  *  e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
5591  *  @hw: pointer to the HW structure
5592  *
5593  *  Read appropriate register for the config done bit for completion status
5594  *  and configure the PHY through s/w for EEPROM-less parts.
5595  *
5596  *  NOTE: some silicon which is EEPROM-less will fail trying to read the
5597  *  config done bit, so only an error is logged and continues.  If we were
5598  *  to return with error, EEPROM-less silicon would not be able to be reset
5599  *  or change link.
5600  **/
5601 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
5602 {
5603         s32 ret_val = 0;
5604         u32 bank = 0;
5605         u32 status;
5606
5607         e1000e_get_cfg_done_generic(hw);
5608
5609         /* Wait for indication from h/w that it has completed basic config */
5610         if (hw->mac.type >= e1000_ich10lan) {
5611                 e1000_lan_init_done_ich8lan(hw);
5612         } else {
5613                 ret_val = e1000e_get_auto_rd_done(hw);
5614                 if (ret_val) {
5615                         /* When auto config read does not complete, do not
5616                          * return with an error. This can happen in situations
5617                          * where there is no eeprom and prevents getting link.
5618                          */
5619                         e_dbg("Auto Read Done did not complete\n");
5620                         ret_val = 0;
5621                 }
5622         }
5623
5624         /* Clear PHY Reset Asserted bit */
5625         status = er32(STATUS);
5626         if (status & E1000_STATUS_PHYRA)
5627                 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
5628         else
5629                 e_dbg("PHY Reset Asserted not set - needs delay\n");
5630
5631         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
5632         if (hw->mac.type <= e1000_ich9lan) {
5633                 if (!(er32(EECD) & E1000_EECD_PRES) &&
5634                     (hw->phy.type == e1000_phy_igp_3)) {
5635                         e1000e_phy_init_script_igp3(hw);
5636                 }
5637         } else {
5638                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
5639                         /* Maybe we should do a basic PHY config */
5640                         e_dbg("EEPROM not present\n");
5641                         ret_val = -E1000_ERR_CONFIG;
5642                 }
5643         }
5644
5645         return ret_val;
5646 }
5647
5648 /**
5649  * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
5650  * @hw: pointer to the HW structure
5651  *
5652  * In the case of a PHY power down to save power, or to turn off link during a
5653  * driver unload, or wake on lan is not enabled, remove the link.
5654  **/
5655 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
5656 {
5657         /* If the management interface is not enabled, then power down */
5658         if (!(hw->mac.ops.check_mng_mode(hw) ||
5659               hw->phy.ops.check_reset_block(hw)))
5660                 e1000_power_down_phy_copper(hw);
5661 }
5662
5663 /**
5664  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
5665  *  @hw: pointer to the HW structure
5666  *
5667  *  Clears hardware counters specific to the silicon family and calls
5668  *  clear_hw_cntrs_generic to clear all general purpose counters.
5669  **/
5670 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
5671 {
5672         u16 phy_data;
5673         s32 ret_val;
5674
5675         e1000e_clear_hw_cntrs_base(hw);
5676
5677         er32(ALGNERRC);
5678         er32(RXERRC);
5679         er32(TNCRS);
5680         er32(CEXTERR);
5681         er32(TSCTC);
5682         er32(TSCTFC);
5683
5684         er32(MGTPRC);
5685         er32(MGTPDC);
5686         er32(MGTPTC);
5687
5688         er32(IAC);
5689         er32(ICRXOC);
5690
5691         /* Clear PHY statistics registers */
5692         if ((hw->phy.type == e1000_phy_82578) ||
5693             (hw->phy.type == e1000_phy_82579) ||
5694             (hw->phy.type == e1000_phy_i217) ||
5695             (hw->phy.type == e1000_phy_82577)) {
5696                 ret_val = hw->phy.ops.acquire(hw);
5697                 if (ret_val)
5698                         return;
5699                 ret_val = hw->phy.ops.set_page(hw,
5700                                                HV_STATS_PAGE << IGP_PAGE_SHIFT);
5701                 if (ret_val)
5702                         goto release;
5703                 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
5704                 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
5705                 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
5706                 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
5707                 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
5708                 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
5709                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
5710                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
5711                 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
5712                 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
5713                 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
5714                 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
5715                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
5716                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
5717 release:
5718                 hw->phy.ops.release(hw);
5719         }
5720 }
5721
5722 static const struct e1000_mac_operations ich8_mac_ops = {
5723         /* check_mng_mode dependent on mac type */
5724         .check_for_link         = e1000_check_for_copper_link_ich8lan,
5725         /* cleanup_led dependent on mac type */
5726         .clear_hw_cntrs         = e1000_clear_hw_cntrs_ich8lan,
5727         .get_bus_info           = e1000_get_bus_info_ich8lan,
5728         .set_lan_id             = e1000_set_lan_id_single_port,
5729         .get_link_up_info       = e1000_get_link_up_info_ich8lan,
5730         /* led_on dependent on mac type */
5731         /* led_off dependent on mac type */
5732         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
5733         .reset_hw               = e1000_reset_hw_ich8lan,
5734         .init_hw                = e1000_init_hw_ich8lan,
5735         .setup_link             = e1000_setup_link_ich8lan,
5736         .setup_physical_interface = e1000_setup_copper_link_ich8lan,
5737         /* id_led_init dependent on mac type */
5738         .config_collision_dist  = e1000e_config_collision_dist_generic,
5739         .rar_set                = e1000e_rar_set_generic,
5740         .rar_get_count          = e1000e_rar_get_count_generic,
5741 };
5742
5743 static const struct e1000_phy_operations ich8_phy_ops = {
5744         .acquire                = e1000_acquire_swflag_ich8lan,
5745         .check_reset_block      = e1000_check_reset_block_ich8lan,
5746         .commit                 = NULL,
5747         .get_cfg_done           = e1000_get_cfg_done_ich8lan,
5748         .get_cable_length       = e1000e_get_cable_length_igp_2,
5749         .read_reg               = e1000e_read_phy_reg_igp,
5750         .release                = e1000_release_swflag_ich8lan,
5751         .reset                  = e1000_phy_hw_reset_ich8lan,
5752         .set_d0_lplu_state      = e1000_set_d0_lplu_state_ich8lan,
5753         .set_d3_lplu_state      = e1000_set_d3_lplu_state_ich8lan,
5754         .write_reg              = e1000e_write_phy_reg_igp,
5755 };
5756
5757 static const struct e1000_nvm_operations ich8_nvm_ops = {
5758         .acquire                = e1000_acquire_nvm_ich8lan,
5759         .read                   = e1000_read_nvm_ich8lan,
5760         .release                = e1000_release_nvm_ich8lan,
5761         .reload                 = e1000e_reload_nvm_generic,
5762         .update                 = e1000_update_nvm_checksum_ich8lan,
5763         .valid_led_default      = e1000_valid_led_default_ich8lan,
5764         .validate               = e1000_validate_nvm_checksum_ich8lan,
5765         .write                  = e1000_write_nvm_ich8lan,
5766 };
5767
5768 static const struct e1000_nvm_operations spt_nvm_ops = {
5769         .acquire                = e1000_acquire_nvm_ich8lan,
5770         .release                = e1000_release_nvm_ich8lan,
5771         .read                   = e1000_read_nvm_spt,
5772         .update                 = e1000_update_nvm_checksum_spt,
5773         .reload                 = e1000e_reload_nvm_generic,
5774         .valid_led_default      = e1000_valid_led_default_ich8lan,
5775         .validate               = e1000_validate_nvm_checksum_ich8lan,
5776         .write                  = e1000_write_nvm_ich8lan,
5777 };
5778
5779 const struct e1000_info e1000_ich8_info = {
5780         .mac                    = e1000_ich8lan,
5781         .flags                  = FLAG_HAS_WOL
5782                                   | FLAG_IS_ICH
5783                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5784                                   | FLAG_HAS_AMT
5785                                   | FLAG_HAS_FLASH
5786                                   | FLAG_APME_IN_WUC,
5787         .pba                    = 8,
5788         .max_hw_frame_size      = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN,
5789         .get_variants           = e1000_get_variants_ich8lan,
5790         .mac_ops                = &ich8_mac_ops,
5791         .phy_ops                = &ich8_phy_ops,
5792         .nvm_ops                = &ich8_nvm_ops,
5793 };
5794
5795 const struct e1000_info e1000_ich9_info = {
5796         .mac                    = e1000_ich9lan,
5797         .flags                  = FLAG_HAS_JUMBO_FRAMES
5798                                   | FLAG_IS_ICH
5799                                   | FLAG_HAS_WOL
5800                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5801                                   | FLAG_HAS_AMT
5802                                   | FLAG_HAS_FLASH
5803                                   | FLAG_APME_IN_WUC,
5804         .pba                    = 18,
5805         .max_hw_frame_size      = DEFAULT_JUMBO,
5806         .get_variants           = e1000_get_variants_ich8lan,
5807         .mac_ops                = &ich8_mac_ops,
5808         .phy_ops                = &ich8_phy_ops,
5809         .nvm_ops                = &ich8_nvm_ops,
5810 };
5811
5812 const struct e1000_info e1000_ich10_info = {
5813         .mac                    = e1000_ich10lan,
5814         .flags                  = FLAG_HAS_JUMBO_FRAMES
5815                                   | FLAG_IS_ICH
5816                                   | FLAG_HAS_WOL
5817                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5818                                   | FLAG_HAS_AMT
5819                                   | FLAG_HAS_FLASH
5820                                   | FLAG_APME_IN_WUC,
5821         .pba                    = 18,
5822         .max_hw_frame_size      = DEFAULT_JUMBO,
5823         .get_variants           = e1000_get_variants_ich8lan,
5824         .mac_ops                = &ich8_mac_ops,
5825         .phy_ops                = &ich8_phy_ops,
5826         .nvm_ops                = &ich8_nvm_ops,
5827 };
5828
5829 const struct e1000_info e1000_pch_info = {
5830         .mac                    = e1000_pchlan,
5831         .flags                  = FLAG_IS_ICH
5832                                   | FLAG_HAS_WOL
5833                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5834                                   | FLAG_HAS_AMT
5835                                   | FLAG_HAS_FLASH
5836                                   | FLAG_HAS_JUMBO_FRAMES
5837                                   | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
5838                                   | FLAG_APME_IN_WUC,
5839         .flags2                 = FLAG2_HAS_PHY_STATS,
5840         .pba                    = 26,
5841         .max_hw_frame_size      = 4096,
5842         .get_variants           = e1000_get_variants_ich8lan,
5843         .mac_ops                = &ich8_mac_ops,
5844         .phy_ops                = &ich8_phy_ops,
5845         .nvm_ops                = &ich8_nvm_ops,
5846 };
5847
5848 const struct e1000_info e1000_pch2_info = {
5849         .mac                    = e1000_pch2lan,
5850         .flags                  = FLAG_IS_ICH
5851                                   | FLAG_HAS_WOL
5852                                   | FLAG_HAS_HW_TIMESTAMP
5853                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5854                                   | FLAG_HAS_AMT
5855                                   | FLAG_HAS_FLASH
5856                                   | FLAG_HAS_JUMBO_FRAMES
5857                                   | FLAG_APME_IN_WUC,
5858         .flags2                 = FLAG2_HAS_PHY_STATS
5859                                   | FLAG2_HAS_EEE
5860                                   | FLAG2_CHECK_SYSTIM_OVERFLOW,
5861         .pba                    = 26,
5862         .max_hw_frame_size      = 9022,
5863         .get_variants           = e1000_get_variants_ich8lan,
5864         .mac_ops                = &ich8_mac_ops,
5865         .phy_ops                = &ich8_phy_ops,
5866         .nvm_ops                = &ich8_nvm_ops,
5867 };
5868
5869 const struct e1000_info e1000_pch_lpt_info = {
5870         .mac                    = e1000_pch_lpt,
5871         .flags                  = FLAG_IS_ICH
5872                                   | FLAG_HAS_WOL
5873                                   | FLAG_HAS_HW_TIMESTAMP
5874                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5875                                   | FLAG_HAS_AMT
5876                                   | FLAG_HAS_FLASH
5877                                   | FLAG_HAS_JUMBO_FRAMES
5878                                   | FLAG_APME_IN_WUC,
5879         .flags2                 = FLAG2_HAS_PHY_STATS
5880                                   | FLAG2_HAS_EEE
5881                                   | FLAG2_CHECK_SYSTIM_OVERFLOW,
5882         .pba                    = 26,
5883         .max_hw_frame_size      = 9022,
5884         .get_variants           = e1000_get_variants_ich8lan,
5885         .mac_ops                = &ich8_mac_ops,
5886         .phy_ops                = &ich8_phy_ops,
5887         .nvm_ops                = &ich8_nvm_ops,
5888 };
5889
5890 const struct e1000_info e1000_pch_spt_info = {
5891         .mac                    = e1000_pch_spt,
5892         .flags                  = FLAG_IS_ICH
5893                                   | FLAG_HAS_WOL
5894                                   | FLAG_HAS_HW_TIMESTAMP
5895                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5896                                   | FLAG_HAS_AMT
5897                                   | FLAG_HAS_FLASH
5898                                   | FLAG_HAS_JUMBO_FRAMES
5899                                   | FLAG_APME_IN_WUC,
5900         .flags2                 = FLAG2_HAS_PHY_STATS
5901                                   | FLAG2_HAS_EEE,
5902         .pba                    = 26,
5903         .max_hw_frame_size      = 9022,
5904         .get_variants           = e1000_get_variants_ich8lan,
5905         .mac_ops                = &ich8_mac_ops,
5906         .phy_ops                = &ich8_phy_ops,
5907         .nvm_ops                = &spt_nvm_ops,
5908 };
5909
5910 const struct e1000_info e1000_pch_cnp_info = {
5911         .mac                    = e1000_pch_cnp,
5912         .flags                  = FLAG_IS_ICH
5913                                   | FLAG_HAS_WOL
5914                                   | FLAG_HAS_HW_TIMESTAMP
5915                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5916                                   | FLAG_HAS_AMT
5917                                   | FLAG_HAS_FLASH
5918                                   | FLAG_HAS_JUMBO_FRAMES
5919                                   | FLAG_APME_IN_WUC,
5920         .flags2                 = FLAG2_HAS_PHY_STATS
5921                                   | FLAG2_HAS_EEE,
5922         .pba                    = 26,
5923         .max_hw_frame_size      = 9022,
5924         .get_variants           = e1000_get_variants_ich8lan,
5925         .mac_ops                = &ich8_mac_ops,
5926         .phy_ops                = &ich8_phy_ops,
5927         .nvm_ops                = &spt_nvm_ops,
5928 };