drivers/net/ethernet/intel/e1000e/ich8lan.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
   3
   4 /* 82562G 10/100 Network Connection
   5  * 82562G-2 10/100 Network Connection
   6  * 82562GT 10/100 Network Connection
   7  * 82562GT-2 10/100 Network Connection
   8  * 82562V 10/100 Network Connection
   9  * 82562V-2 10/100 Network Connection
  10  * 82566DC-2 Gigabit Network Connection
  11  * 82566DC Gigabit Network Connection
  12  * 82566DM-2 Gigabit Network Connection
  13  * 82566DM Gigabit Network Connection
  14  * 82566MC Gigabit Network Connection
  15  * 82566MM Gigabit Network Connection
  16  * 82567LM Gigabit Network Connection
  17  * 82567LF Gigabit Network Connection
  18  * 82567V Gigabit Network Connection
  19  * 82567LM-2 Gigabit Network Connection
  20  * 82567LF-2 Gigabit Network Connection
  21  * 82567V-2 Gigabit Network Connection
  22  * 82567LF-3 Gigabit Network Connection
  23  * 82567LM-3 Gigabit Network Connection
  24  * 82567LM-4 Gigabit Network Connection
  25  * 82577LM Gigabit Network Connection
  26  * 82577LC Gigabit Network Connection
  27  * 82578DM Gigabit Network Connection
  28  * 82578DC Gigabit Network Connection
  29  * 82579LM Gigabit Network Connection
  30  * 82579V Gigabit Network Connection
  31  * Ethernet Connection I217-LM
  32  * Ethernet Connection I217-V
  33  * Ethernet Connection I218-V
  34  * Ethernet Connection I218-LM
  35  * Ethernet Connection (2) I218-LM
  36  * Ethernet Connection (2) I218-V
  37  * Ethernet Connection (3) I218-LM
  38  * Ethernet Connection (3) I218-V
  39  */
  40
  41 #include "e1000.h"
  42
  43 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
  44 /* Offset 04h HSFSTS */
  45 union ich8_hws_flash_status {
  46         struct ich8_hsfsts {
  47                 u16 flcdone:1;  /* bit 0 Flash Cycle Done */
  48                 u16 flcerr:1;   /* bit 1 Flash Cycle Error */
  49                 u16 dael:1;     /* bit 2 Direct Access error Log */
  50                 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
  51                 u16 flcinprog:1;        /* bit 5 flash cycle in Progress */
  52                 u16 reserved1:2;        /* bit 13:6 Reserved */
  53                 u16 reserved2:6;        /* bit 13:6 Reserved */
  54                 u16 fldesvalid:1;       /* bit 14 Flash Descriptor Valid */
  55                 u16 flockdn:1;  /* bit 15 Flash Config Lock-Down */
  56         } hsf_status;
  57         u16 regval;
  58 };
  59
  60 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
  61 /* Offset 06h FLCTL */
  62 union ich8_hws_flash_ctrl {
  63         struct ich8_hsflctl {
  64                 u16 flcgo:1;    /* 0 Flash Cycle Go */
  65                 u16 flcycle:2;  /* 2:1 Flash Cycle */
  66                 u16 reserved:5; /* 7:3 Reserved  */
  67                 u16 fldbcount:2;        /* 9:8 Flash Data Byte Count */
  68                 u16 flockdn:6;  /* 15:10 Reserved */
  69         } hsf_ctrl;
  70         u16 regval;
  71 };
  72
  73 /* ICH Flash Region Access Permissions */
  74 union ich8_hws_flash_regacc {
  75         struct ich8_flracc {
  76                 u32 grra:8;     /* 0:7 GbE region Read Access */
  77                 u32 grwa:8;     /* 8:15 GbE region Write Access */
  78                 u32 gmrag:8;    /* 23:16 GbE Master Read Access Grant */
  79                 u32 gmwag:8;    /* 31:24 GbE Master Write Access Grant */
  80         } hsf_flregacc;
  81         u16 regval;
  82 };
  83
  84 /* ICH Flash Protected Region */
  85 union ich8_flash_protected_range {
  86         struct ich8_pr {
  87                 u32 base:13;    /* 0:12 Protected Range Base */
  88                 u32 reserved1:2;        /* 13:14 Reserved */
  89                 u32 rpe:1;      /* 15 Read Protection Enable */
  90                 u32 limit:13;   /* 16:28 Protected Range Limit */
  91                 u32 reserved2:2;        /* 29:30 Reserved */
  92                 u32 wpe:1;      /* 31 Write Protection Enable */
  93         } range;
  94         u32 regval;
  95 };
  96
  97 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
  98 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
  99 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 100 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 101                                                 u32 offset, u8 byte);
 102 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
 103                                          u8 *data);
 104 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
 105                                          u16 *data);
 106 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 107                                          u8 size, u16 *data);
 108 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
 109                                            u32 *data);
 110 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw,
 111                                           u32 offset, u32 *data);
 112 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw,
 113                                             u32 offset, u32 data);
 114 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
 115                                                  u32 offset, u32 dword);
 116 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 117 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
 118 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
 119 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
 120 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
 121 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
 122 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
 123 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
 124 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
 125 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
 126 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
 127 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
 128 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
 129 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
 130 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
 131 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
 132 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
 133 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
 134 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw);
 135 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
 136 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
 137 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force);
 138 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
 139 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state);
 140
 141 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
 142 {
 143         return readw(hw->flash_address + reg);
 144 }
 145
 146 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
 147 {
 148         return readl(hw->flash_address + reg);
 149 }
 150
 151 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
 152 {
 153         writew(val, hw->flash_address + reg);
 154 }
 155
 156 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
 157 {
 158         writel(val, hw->flash_address + reg);
 159 }
 160
 161 #define er16flash(reg)          __er16flash(hw, (reg))
 162 #define er32flash(reg)          __er32flash(hw, (reg))
 163 #define ew16flash(reg, val)     __ew16flash(hw, (reg), (val))
 164 #define ew32flash(reg, val)     __ew32flash(hw, (reg), (val))
 165
 166 /**
 167  *  e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
 168  *  @hw: pointer to the HW structure
 169  *
 170  *  Test access to the PHY registers by reading the PHY ID registers.  If
 171  *  the PHY ID is already known (e.g. resume path) compare it with known ID,
 172  *  otherwise assume the read PHY ID is correct if it is valid.
 173  *
 174  *  Assumes the sw/fw/hw semaphore is already acquired.
 175  **/
 176 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
 177 {
 178         u16 phy_reg = 0;
 179         u32 phy_id = 0;
 180         s32 ret_val = 0;
 181         u16 retry_count;
 182         u32 mac_reg = 0;
 183
 184         for (retry_count = 0; retry_count < 2; retry_count++) {
 185                 ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg);
 186                 if (ret_val || (phy_reg == 0xFFFF))
 187                         continue;
 188                 phy_id = (u32)(phy_reg << 16);
 189
 190                 ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg);
 191                 if (ret_val || (phy_reg == 0xFFFF)) {
 192                         phy_id = 0;
 193                         continue;
 194                 }
 195                 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
 196                 break;
 197         }
 198
 199         if (hw->phy.id) {
 200                 if (hw->phy.id == phy_id)
 201                         goto out;
 202         } else if (phy_id) {
 203                 hw->phy.id = phy_id;
 204                 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
 205                 goto out;
 206         }
 207
 208         /* In case the PHY needs to be in mdio slow mode,
 209          * set slow mode and try to get the PHY id again.
 210          */
 211         if (hw->mac.type < e1000_pch_lpt) {
 212                 hw->phy.ops.release(hw);
 213                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
 214                 if (!ret_val)
 215                         ret_val = e1000e_get_phy_id(hw);
 216                 hw->phy.ops.acquire(hw);
 217         }
 218
 219         if (ret_val)
 220                 return false;
 221 out:
 222         if (hw->mac.type >= e1000_pch_lpt) {
 223                 /* Only unforce SMBus if ME is not active */
 224                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
 225                         /* Unforce SMBus mode in PHY */
 226                         e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg);
 227                         phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
 228                         e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg);
 229
 230                         /* Unforce SMBus mode in MAC */
 231                         mac_reg = er32(CTRL_EXT);
 232                         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
 233                         ew32(CTRL_EXT, mac_reg);
 234                 }
 235         }
 236
 237         return true;
 238 }
 239
 240 /**
 241  *  e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
 242  *  @hw: pointer to the HW structure
 243  *
 244  *  Toggling the LANPHYPC pin value fully power-cycles the PHY and is
 245  *  used to reset the PHY to a quiescent state when necessary.
 246  **/
 247 static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
 248 {
 249         u32 mac_reg;
 250
 251         /* Set Phy Config Counter to 50msec */
 252         mac_reg = er32(FEXTNVM3);
 253         mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
 254         mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
 255         ew32(FEXTNVM3, mac_reg);
 256
 257         /* Toggle LANPHYPC Value bit */
 258         mac_reg = er32(CTRL);
 259         mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
 260         mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
 261         ew32(CTRL, mac_reg);
 262         e1e_flush();
 263         usleep_range(10, 20);
 264         mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
 265         ew32(CTRL, mac_reg);
 266         e1e_flush();
 267
 268         if (hw->mac.type < e1000_pch_lpt) {
 269                 msleep(50);
 270         } else {
 271                 u16 count = 20;
 272
 273                 do {
 274                         usleep_range(5000, 6000);
 275                 } while (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LPCD) && count--);
 276
 277                 msleep(30);
 278         }
 279 }
 280
 281 /**
 282  *  e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
 283  *  @hw: pointer to the HW structure
 284  *
 285  *  Workarounds/flow necessary for PHY initialization during driver load
 286  *  and resume paths.
 287  **/
 288 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
 289 {
 290         struct e1000_adapter *adapter = hw->adapter;
 291         u32 mac_reg, fwsm = er32(FWSM);
 292         s32 ret_val;
 293
 294         /* Gate automatic PHY configuration by hardware on managed and
 295          * non-managed 82579 and newer adapters.
 296          */
 297         e1000_gate_hw_phy_config_ich8lan(hw, true);
 298
 299         /* It is not possible to be certain of the current state of ULP
 300          * so forcibly disable it.
 301          */
 302         hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
 303         ret_val = e1000_disable_ulp_lpt_lp(hw, true);
 304         if (ret_val)
 305                 e_warn("Failed to disable ULP\n");
 306
 307         ret_val = hw->phy.ops.acquire(hw);
 308         if (ret_val) {
 309                 e_dbg("Failed to initialize PHY flow\n");
 310                 goto out;
 311         }
 312
 313         /* The MAC-PHY interconnect may be in SMBus mode.  If the PHY is
 314          * inaccessible and resetting the PHY is not blocked, toggle the
 315          * LANPHYPC Value bit to force the interconnect to PCIe mode.
 316          */
 317         switch (hw->mac.type) {
 318         case e1000_pch_lpt:
 319         case e1000_pch_spt:
 320         case e1000_pch_cnp:
 321         case e1000_pch_tgp:
 322         case e1000_pch_adp:
 323                 if (e1000_phy_is_accessible_pchlan(hw))
 324                         break;
 325
 326                 /* Before toggling LANPHYPC, see if PHY is accessible by
 327                  * forcing MAC to SMBus mode first.
 328                  */
 329                 mac_reg = er32(CTRL_EXT);
 330                 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
 331                 ew32(CTRL_EXT, mac_reg);
 332
 333                 /* Wait 50 milliseconds for MAC to finish any retries
 334                  * that it might be trying to perform from previous
 335                  * attempts to acknowledge any phy read requests.
 336                  */
 337                 msleep(50);
 338
 339                 fallthrough;
 340         case e1000_pch2lan:
 341                 if (e1000_phy_is_accessible_pchlan(hw))
 342                         break;
 343
 344                 fallthrough;
 345         case e1000_pchlan:
 346                 if ((hw->mac.type == e1000_pchlan) &&
 347                     (fwsm & E1000_ICH_FWSM_FW_VALID))
 348                         break;
 349
 350                 if (hw->phy.ops.check_reset_block(hw)) {
 351                         e_dbg("Required LANPHYPC toggle blocked by ME\n");
 352                         ret_val = -E1000_ERR_PHY;
 353                         break;
 354                 }
 355
 356                 /* Toggle LANPHYPC Value bit */
 357                 e1000_toggle_lanphypc_pch_lpt(hw);
 358                 if (hw->mac.type >= e1000_pch_lpt) {
 359                         if (e1000_phy_is_accessible_pchlan(hw))
 360                                 break;
 361
 362                         /* Toggling LANPHYPC brings the PHY out of SMBus mode
 363                          * so ensure that the MAC is also out of SMBus mode
 364                          */
 365                         mac_reg = er32(CTRL_EXT);
 366                         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
 367                         ew32(CTRL_EXT, mac_reg);
 368
 369                         if (e1000_phy_is_accessible_pchlan(hw))
 370                                 break;
 371
 372                         ret_val = -E1000_ERR_PHY;
 373                 }
 374                 break;
 375         default:
 376                 break;
 377         }
 378
 379         hw->phy.ops.release(hw);
 380         if (!ret_val) {
 381
 382                 /* Check to see if able to reset PHY.  Print error if not */
 383                 if (hw->phy.ops.check_reset_block(hw)) {
 384                         e_err("Reset blocked by ME\n");
 385                         goto out;
 386                 }
 387
 388                 /* Reset the PHY before any access to it.  Doing so, ensures
 389                  * that the PHY is in a known good state before we read/write
 390                  * PHY registers.  The generic reset is sufficient here,
 391                  * because we haven't determined the PHY type yet.
 392                  */
 393                 ret_val = e1000e_phy_hw_reset_generic(hw);
 394                 if (ret_val)
 395                         goto out;
 396
 397                 /* On a successful reset, possibly need to wait for the PHY
 398                  * to quiesce to an accessible state before returning control
 399                  * to the calling function.  If the PHY does not quiesce, then
 400                  * return E1000E_BLK_PHY_RESET, as this is the condition that
 401                  *  the PHY is in.
 402                  */
 403                 ret_val = hw->phy.ops.check_reset_block(hw);
 404                 if (ret_val)
 405                         e_err("ME blocked access to PHY after reset\n");
 406         }
 407
 408 out:
 409         /* Ungate automatic PHY configuration on non-managed 82579 */
 410         if ((hw->mac.type == e1000_pch2lan) &&
 411             !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
 412                 usleep_range(10000, 11000);
 413                 e1000_gate_hw_phy_config_ich8lan(hw, false);
 414         }
 415
 416         return ret_val;
 417 }
 418
 419 /**
 420  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 421  *  @hw: pointer to the HW structure
 422  *
 423  *  Initialize family-specific PHY parameters and function pointers.
 424  **/
 425 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 426 {
 427         struct e1000_phy_info *phy = &hw->phy;
 428         s32 ret_val;
 429
 430         phy->addr = 1;
 431         phy->reset_delay_us = 100;
 432
 433         phy->ops.set_page = e1000_set_page_igp;
 434         phy->ops.read_reg = e1000_read_phy_reg_hv;
 435         phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
 436         phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;
 437         phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
 438         phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
 439         phy->ops.write_reg = e1000_write_phy_reg_hv;
 440         phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
 441         phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
 442         phy->ops.power_up = e1000_power_up_phy_copper;
 443         phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
 444         phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 445
 446         phy->id = e1000_phy_unknown;
 447
 448         ret_val = e1000_init_phy_workarounds_pchlan(hw);
 449         if (ret_val)
 450                 return ret_val;
 451
 452         if (phy->id == e1000_phy_unknown)
 453                 switch (hw->mac.type) {
 454                 default:
 455                         ret_val = e1000e_get_phy_id(hw);
 456                         if (ret_val)
 457                                 return ret_val;
 458                         if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
 459                                 break;
 460                         fallthrough;
 461                 case e1000_pch2lan:
 462                 case e1000_pch_lpt:
 463                 case e1000_pch_spt:
 464                 case e1000_pch_cnp:
 465                 case e1000_pch_tgp:
 466                 case e1000_pch_adp:
 467                         /* In case the PHY needs to be in mdio slow mode,
 468                          * set slow mode and try to get the PHY id again.
 469                          */
 470                         ret_val = e1000_set_mdio_slow_mode_hv(hw);
 471                         if (ret_val)
 472                                 return ret_val;
 473                         ret_val = e1000e_get_phy_id(hw);
 474                         if (ret_val)
 475                                 return ret_val;
 476                         break;
 477                 }
 478         phy->type = e1000e_get_phy_type_from_id(phy->id);
 479
 480         switch (phy->type) {
 481         case e1000_phy_82577:
 482         case e1000_phy_82579:
 483         case e1000_phy_i217:
 484                 phy->ops.check_polarity = e1000_check_polarity_82577;
 485                 phy->ops.force_speed_duplex =
 486                     e1000_phy_force_speed_duplex_82577;
 487                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 488                 phy->ops.get_info = e1000_get_phy_info_82577;
 489                 phy->ops.commit = e1000e_phy_sw_reset;
 490                 break;
 491         case e1000_phy_82578:
 492                 phy->ops.check_polarity = e1000_check_polarity_m88;
 493                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 494                 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
 495                 phy->ops.get_info = e1000e_get_phy_info_m88;
 496                 break;
 497         default:
 498                 ret_val = -E1000_ERR_PHY;
 499                 break;
 500         }
 501
 502         return ret_val;
 503 }
 504
 505 /**
 506  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 507  *  @hw: pointer to the HW structure
 508  *
 509  *  Initialize family-specific PHY parameters and function pointers.
 510  **/
 511 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 512 {
 513         struct e1000_phy_info *phy = &hw->phy;
 514         s32 ret_val;
 515         u16 i = 0;
 516
 517         phy->addr = 1;
 518         phy->reset_delay_us = 100;
 519
 520         phy->ops.power_up = e1000_power_up_phy_copper;
 521         phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
 522
 523         /* We may need to do this twice - once for IGP and if that fails,
 524          * we'll set BM func pointers and try again
 525          */
 526         ret_val = e1000e_determine_phy_address(hw);
 527         if (ret_val) {
 528                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 529                 phy->ops.read_reg = e1000e_read_phy_reg_bm;
 530                 ret_val = e1000e_determine_phy_address(hw);
 531                 if (ret_val) {
 532                         e_dbg("Cannot determine PHY addr. Erroring out\n");
 533                         return ret_val;
 534                 }
 535         }
 536
 537         phy->id = 0;
 538         while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
 539                (i++ < 100)) {
 540                 usleep_range(1000, 1100);
 541                 ret_val = e1000e_get_phy_id(hw);
 542                 if (ret_val)
 543                         return ret_val;
 544         }
 545
 546         /* Verify phy id */
 547         switch (phy->id) {
 548         case IGP03E1000_E_PHY_ID:
 549                 phy->type = e1000_phy_igp_3;
 550                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 551                 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
 552                 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
 553                 phy->ops.get_info = e1000e_get_phy_info_igp;
 554                 phy->ops.check_polarity = e1000_check_polarity_igp;
 555                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
 556                 break;
 557         case IFE_E_PHY_ID:
 558         case IFE_PLUS_E_PHY_ID:
 559         case IFE_C_E_PHY_ID:
 560                 phy->type = e1000_phy_ife;
 561                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 562                 phy->ops.get_info = e1000_get_phy_info_ife;
 563                 phy->ops.check_polarity = e1000_check_polarity_ife;
 564                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
 565                 break;
 566         case BME1000_E_PHY_ID:
 567                 phy->type = e1000_phy_bm;
 568                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 569                 phy->ops.read_reg = e1000e_read_phy_reg_bm;
 570                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 571                 phy->ops.commit = e1000e_phy_sw_reset;
 572                 phy->ops.get_info = e1000e_get_phy_info_m88;
 573                 phy->ops.check_polarity = e1000_check_polarity_m88;
 574                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 575                 break;
 576         default:
 577                 return -E1000_ERR_PHY;
 578         }
 579
 580         return 0;
 581 }
 582
 583 /**
 584  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 585  *  @hw: pointer to the HW structure
 586  *
 587  *  Initialize family-specific NVM parameters and function
 588  *  pointers.
 589  **/
 590 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 591 {
 592         struct e1000_nvm_info *nvm = &hw->nvm;
 593         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 594         u32 gfpreg, sector_base_addr, sector_end_addr;
 595         u16 i;
 596         u32 nvm_size;
 597
 598         nvm->type = e1000_nvm_flash_sw;
 599
 600         if (hw->mac.type >= e1000_pch_spt) {
 601                 /* in SPT, gfpreg doesn't exist. NVM size is taken from the
 602                  * STRAP register. This is because in SPT the GbE Flash region
 603                  * is no longer accessed through the flash registers. Instead,
 604                  * the mechanism has changed, and the Flash region access
 605                  * registers are now implemented in GbE memory space.
 606                  */
 607                 nvm->flash_base_addr = 0;
 608                 nvm_size = (((er32(STRAP) >> 1) & 0x1F) + 1)
 609                     * NVM_SIZE_MULTIPLIER;
 610                 nvm->flash_bank_size = nvm_size / 2;
 611                 /* Adjust to word count */
 612                 nvm->flash_bank_size /= sizeof(u16);
 613                 /* Set the base address for flash register access */
 614                 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR;
 615         } else {
 616                 /* Can't read flash registers if register set isn't mapped. */
 617                 if (!hw->flash_address) {
 618                         e_dbg("ERROR: Flash registers not mapped\n");
 619                         return -E1000_ERR_CONFIG;
 620                 }
 621
 622                 gfpreg = er32flash(ICH_FLASH_GFPREG);
 623
 624                 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
 625                  * Add 1 to sector_end_addr since this sector is included in
 626                  * the overall size.
 627                  */
 628                 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 629                 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 630
 631                 /* flash_base_addr is byte-aligned */
 632                 nvm->flash_base_addr = sector_base_addr
 633                     << FLASH_SECTOR_ADDR_SHIFT;
 634
 635                 /* find total size of the NVM, then cut in half since the total
 636                  * size represents two separate NVM banks.
 637                  */
 638                 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
 639                                         << FLASH_SECTOR_ADDR_SHIFT);
 640                 nvm->flash_bank_size /= 2;
 641                 /* Adjust to word count */
 642                 nvm->flash_bank_size /= sizeof(u16);
 643         }
 644
 645         nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
 646
 647         /* Clear shadow ram */
 648         for (i = 0; i < nvm->word_size; i++) {
 649                 dev_spec->shadow_ram[i].modified = false;
 650                 dev_spec->shadow_ram[i].value = 0xFFFF;
 651         }
 652
 653         return 0;
 654 }
 655
 656 /**
 657  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 658  *  @hw: pointer to the HW structure
 659  *
 660  *  Initialize family-specific MAC parameters and function
 661  *  pointers.
 662  **/
 663 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
 664 {
 665         struct e1000_mac_info *mac = &hw->mac;
 666
 667         /* Set media type function pointer */
 668         hw->phy.media_type = e1000_media_type_copper;
 669
 670         /* Set mta register count */
 671         mac->mta_reg_count = 32;
 672         /* Set rar entry count */
 673         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 674         if (mac->type == e1000_ich8lan)
 675                 mac->rar_entry_count--;
 676         /* FWSM register */
 677         mac->has_fwsm = true;
 678         /* ARC subsystem not supported */
 679         mac->arc_subsystem_valid = false;
 680         /* Adaptive IFS supported */
 681         mac->adaptive_ifs = true;
 682
 683         /* LED and other operations */
 684         switch (mac->type) {
 685         case e1000_ich8lan:
 686         case e1000_ich9lan:
 687         case e1000_ich10lan:
 688                 /* check management mode */
 689                 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
 690                 /* ID LED init */
 691                 mac->ops.id_led_init = e1000e_id_led_init_generic;
 692                 /* blink LED */
 693                 mac->ops.blink_led = e1000e_blink_led_generic;
 694                 /* setup LED */
 695                 mac->ops.setup_led = e1000e_setup_led_generic;
 696                 /* cleanup LED */
 697                 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
 698                 /* turn on/off LED */
 699                 mac->ops.led_on = e1000_led_on_ich8lan;
 700                 mac->ops.led_off = e1000_led_off_ich8lan;
 701                 break;
 702         case e1000_pch2lan:
 703                 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
 704                 mac->ops.rar_set = e1000_rar_set_pch2lan;
 705                 fallthrough;
 706         case e1000_pch_lpt:
 707         case e1000_pch_spt:
 708         case e1000_pch_cnp:
 709         case e1000_pch_tgp:
 710         case e1000_pch_adp:
 711         case e1000_pchlan:
 712                 /* check management mode */
 713                 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
 714                 /* ID LED init */
 715                 mac->ops.id_led_init = e1000_id_led_init_pchlan;
 716                 /* setup LED */
 717                 mac->ops.setup_led = e1000_setup_led_pchlan;
 718                 /* cleanup LED */
 719                 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
 720                 /* turn on/off LED */
 721                 mac->ops.led_on = e1000_led_on_pchlan;
 722                 mac->ops.led_off = e1000_led_off_pchlan;
 723                 break;
 724         default:
 725                 break;
 726         }
 727
 728         if (mac->type >= e1000_pch_lpt) {
 729                 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
 730                 mac->ops.rar_set = e1000_rar_set_pch_lpt;
 731                 mac->ops.setup_physical_interface =
 732                     e1000_setup_copper_link_pch_lpt;
 733                 mac->ops.rar_get_count = e1000_rar_get_count_pch_lpt;
 734         }
 735
 736         /* Enable PCS Lock-loss workaround for ICH8 */
 737         if (mac->type == e1000_ich8lan)
 738                 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
 739
 740         return 0;
 741 }
 742
 743 /**
 744  *  __e1000_access_emi_reg_locked - Read/write EMI register
 745  *  @hw: pointer to the HW structure
 746  *  @addr: EMI address to program
 747  *  @data: pointer to value to read/write from/to the EMI address
 748  *  @read: boolean flag to indicate read or write
 749  *
 750  *  This helper function assumes the SW/FW/HW Semaphore is already acquired.
 751  **/
 752 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
 753                                          u16 *data, bool read)
 754 {
 755         s32 ret_val;
 756
 757         ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address);
 758         if (ret_val)
 759                 return ret_val;
 760
 761         if (read)
 762                 ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data);
 763         else
 764                 ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data);
 765
 766         return ret_val;
 767 }
 768
 769 /**
 770  *  e1000_read_emi_reg_locked - Read Extended Management Interface register
 771  *  @hw: pointer to the HW structure
 772  *  @addr: EMI address to program
 773  *  @data: value to be read from the EMI address
 774  *
 775  *  Assumes the SW/FW/HW Semaphore is already acquired.
 776  **/
 777 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
 778 {
 779         return __e1000_access_emi_reg_locked(hw, addr, data, true);
 780 }
 781
 782 /**
 783  *  e1000_write_emi_reg_locked - Write Extended Management Interface register
 784  *  @hw: pointer to the HW structure
 785  *  @addr: EMI address to program
 786  *  @data: value to be written to the EMI address
 787  *
 788  *  Assumes the SW/FW/HW Semaphore is already acquired.
 789  **/
 790 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
 791 {
 792         return __e1000_access_emi_reg_locked(hw, addr, &data, false);
 793 }
 794
 795 /**
 796  *  e1000_set_eee_pchlan - Enable/disable EEE support
 797  *  @hw: pointer to the HW structure
 798  *
 799  *  Enable/disable EEE based on setting in dev_spec structure, the duplex of
 800  *  the link and the EEE capabilities of the link partner.  The LPI Control
 801  *  register bits will remain set only if/when link is up.
 802  *
 803  *  EEE LPI must not be asserted earlier than one second after link is up.
 804  *  On 82579, EEE LPI should not be enabled until such time otherwise there
 805  *  can be link issues with some switches.  Other devices can have EEE LPI
 806  *  enabled immediately upon link up since they have a timer in hardware which
 807  *  prevents LPI from being asserted too early.
 808  **/
 809 s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
 810 {
 811         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 812         s32 ret_val;
 813         u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
 814
 815         switch (hw->phy.type) {
 816         case e1000_phy_82579:
 817                 lpa = I82579_EEE_LP_ABILITY;
 818                 pcs_status = I82579_EEE_PCS_STATUS;
 819                 adv_addr = I82579_EEE_ADVERTISEMENT;
 820                 break;
 821         case e1000_phy_i217:
 822                 lpa = I217_EEE_LP_ABILITY;
 823                 pcs_status = I217_EEE_PCS_STATUS;
 824                 adv_addr = I217_EEE_ADVERTISEMENT;
 825                 break;
 826         default:
 827                 return 0;
 828         }
 829
 830         ret_val = hw->phy.ops.acquire(hw);
 831         if (ret_val)
 832                 return ret_val;
 833
 834         ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
 835         if (ret_val)
 836                 goto release;
 837
 838         /* Clear bits that enable EEE in various speeds */
 839         lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
 840
 841         /* Enable EEE if not disabled by user */
 842         if (!dev_spec->eee_disable) {
 843                 /* Save off link partner's EEE ability */
 844                 ret_val = e1000_read_emi_reg_locked(hw, lpa,
 845                                                     &dev_spec->eee_lp_ability);
 846                 if (ret_val)
 847                         goto release;
 848
 849                 /* Read EEE advertisement */
 850                 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
 851                 if (ret_val)
 852                         goto release;
 853
 854                 /* Enable EEE only for speeds in which the link partner is
 855                  * EEE capable and for which we advertise EEE.
 856                  */
 857                 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
 858                         lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
 859
 860                 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
 861                         e1e_rphy_locked(hw, MII_LPA, &data);
 862                         if (data & LPA_100FULL)
 863                                 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
 864                         else
 865                                 /* EEE is not supported in 100Half, so ignore
 866                                  * partner's EEE in 100 ability if full-duplex
 867                                  * is not advertised.
 868                                  */
 869                                 dev_spec->eee_lp_ability &=
 870                                     ~I82579_EEE_100_SUPPORTED;
 871                 }
 872         }
 873
 874         if (hw->phy.type == e1000_phy_82579) {
 875                 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
 876                                                     &data);
 877                 if (ret_val)
 878                         goto release;
 879
 880                 data &= ~I82579_LPI_100_PLL_SHUT;
 881                 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
 882                                                      data);
 883         }
 884
 885         /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
 886         ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
 887         if (ret_val)
 888                 goto release;
 889
 890         ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
 891 release:
 892         hw->phy.ops.release(hw);
 893
 894         return ret_val;
 895 }
 896
 897 /**
 898  *  e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
 899  *  @hw:   pointer to the HW structure
 900  *  @link: link up bool flag
 901  *
 902  *  When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
 903  *  preventing further DMA write requests.  Workaround the issue by disabling
 904  *  the de-assertion of the clock request when in 1Gpbs mode.
 905  *  Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
 906  *  speeds in order to avoid Tx hangs.
 907  **/
 908 static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
 909 {
 910         u32 fextnvm6 = er32(FEXTNVM6);
 911         u32 status = er32(STATUS);
 912         s32 ret_val = 0;
 913         u16 reg;
 914
 915         if (link && (status & E1000_STATUS_SPEED_1000)) {
 916                 ret_val = hw->phy.ops.acquire(hw);
 917                 if (ret_val)
 918                         return ret_val;
 919
 920                 ret_val =
 921                     e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
 922                                                 &reg);
 923                 if (ret_val)
 924                         goto release;
 925
 926                 ret_val =
 927                     e1000e_write_kmrn_reg_locked(hw,
 928                                                  E1000_KMRNCTRLSTA_K1_CONFIG,
 929                                                  reg &
 930                                                  ~E1000_KMRNCTRLSTA_K1_ENABLE);
 931                 if (ret_val)
 932                         goto release;
 933
 934                 usleep_range(10, 20);
 935
 936                 ew32(FEXTNVM6, fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
 937
 938                 ret_val =
 939                     e1000e_write_kmrn_reg_locked(hw,
 940                                                  E1000_KMRNCTRLSTA_K1_CONFIG,
 941                                                  reg);
 942 release:
 943                 hw->phy.ops.release(hw);
 944         } else {
 945                 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
 946                 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
 947
 948                 if ((hw->phy.revision > 5) || !link ||
 949                     ((status & E1000_STATUS_SPEED_100) &&
 950                      (status & E1000_STATUS_FD)))
 951                         goto update_fextnvm6;
 952
 953                 ret_val = e1e_rphy(hw, I217_INBAND_CTRL, &reg);
 954                 if (ret_val)
 955                         return ret_val;
 956
 957                 /* Clear link status transmit timeout */
 958                 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
 959
 960                 if (status & E1000_STATUS_SPEED_100) {
 961                         /* Set inband Tx timeout to 5x10us for 100Half */
 962                         reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
 963
 964                         /* Do not extend the K1 entry latency for 100Half */
 965                         fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
 966                 } else {
 967                         /* Set inband Tx timeout to 50x10us for 10Full/Half */
 968                         reg |= 50 <<
 969                             I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
 970
 971                         /* Extend the K1 entry latency for 10 Mbps */
 972                         fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
 973                 }
 974
 975                 ret_val = e1e_wphy(hw, I217_INBAND_CTRL, reg);
 976                 if (ret_val)
 977                         return ret_val;
 978
 979 update_fextnvm6:
 980                 ew32(FEXTNVM6, fextnvm6);
 981         }
 982
 983         return ret_val;
 984 }
 985
 986 /**
 987  *  e1000_platform_pm_pch_lpt - Set platform power management values
 988  *  @hw: pointer to the HW structure
 989  *  @link: bool indicating link status
 990  *
 991  *  Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like"
 992  *  GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed
 993  *  when link is up (which must not exceed the maximum latency supported
 994  *  by the platform), otherwise specify there is no LTR requirement.
 995  *  Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop
 996  *  latencies in the LTR Extended Capability Structure in the PCIe Extended
 997  *  Capability register set, on this device LTR is set by writing the
 998  *  equivalent snoop/no-snoop latencies in the LTRV register in the MAC and
 999  *  set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB)
1000  *  message to the PMC.
1001  **/
1002 static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)
1003 {
1004         u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) |
1005             link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND;
1006         u16 lat_enc = 0;        /* latency encoded */
1007
1008         if (link) {
1009                 u16 speed, duplex, scale = 0;
1010                 u16 max_snoop, max_nosnoop;
1011                 u16 max_ltr_enc;        /* max LTR latency encoded */
1012                 u64 value;
1013                 u32 rxa;
1014
1015                 if (!hw->adapter->max_frame_size) {
1016                         e_dbg("max_frame_size not set.\n");
1017                         return -E1000_ERR_CONFIG;
1018                 }
1019
1020                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1021                 if (!speed) {
1022                         e_dbg("Speed not set.\n");
1023                         return -E1000_ERR_CONFIG;
1024                 }
1025
1026                 /* Rx Packet Buffer Allocation size (KB) */
1027                 rxa = er32(PBA) & E1000_PBA_RXA_MASK;
1028
1029                 /* Determine the maximum latency tolerated by the device.
1030                  *
1031                  * Per the PCIe spec, the tolerated latencies are encoded as
1032                  * a 3-bit encoded scale (only 0-5 are valid) multiplied by
1033                  * a 10-bit value (0-1023) to provide a range from 1 ns to
1034                  * 2^25*(2^10-1) ns.  The scale is encoded as 0=2^0ns,
1035                  * 1=2^5ns, 2=2^10ns,...5=2^25ns.
1036                  */
1037                 rxa *= 512;
1038                 value = (rxa > hw->adapter->max_frame_size) ?
1039                         (rxa - hw->adapter->max_frame_size) * (16000 / speed) :
1040                         0;
1041
1042                 while (value > PCI_LTR_VALUE_MASK) {
1043                         scale++;
1044                         value = DIV_ROUND_UP(value, BIT(5));
1045                 }
1046                 if (scale > E1000_LTRV_SCALE_MAX) {
1047                         e_dbg("Invalid LTR latency scale %d\n", scale);
1048                         return -E1000_ERR_CONFIG;
1049                 }
1050                 lat_enc = (u16)((scale << PCI_LTR_SCALE_SHIFT) | value);
1051
1052                 /* Determine the maximum latency tolerated by the platform */
1053                 pci_read_config_word(hw->adapter->pdev, E1000_PCI_LTR_CAP_LPT,
1054                                      &max_snoop);
1055                 pci_read_config_word(hw->adapter->pdev,
1056                                      E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop);
1057                 max_ltr_enc = max_t(u16, max_snoop, max_nosnoop);
1058
1059                 if (lat_enc > max_ltr_enc)
1060                         lat_enc = max_ltr_enc;
1061         }
1062
1063         /* Set Snoop and No-Snoop latencies the same */
1064         reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT);
1065         ew32(LTRV, reg);
1066
1067         return 0;
1068 }
1069
1070 /**
1071  *  e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1072  *  @hw: pointer to the HW structure
1073  *  @to_sx: boolean indicating a system power state transition to Sx
1074  *
1075  *  When link is down, configure ULP mode to significantly reduce the power
1076  *  to the PHY.  If on a Manageability Engine (ME) enabled system, tell the
1077  *  ME firmware to start the ULP configuration.  If not on an ME enabled
1078  *  system, configure the ULP mode by software.
1079  */
1080 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1081 {
1082         u32 mac_reg;
1083         s32 ret_val = 0;
1084         u16 phy_reg;
1085         u16 oem_reg = 0;
1086
1087         if ((hw->mac.type < e1000_pch_lpt) ||
1088             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1089             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) ||
1090             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) ||
1091             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) ||
1092             (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1093                 return 0;
1094
1095         if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
1096                 /* Request ME configure ULP mode in the PHY */
1097                 mac_reg = er32(H2ME);
1098                 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
1099                 ew32(H2ME, mac_reg);
1100
1101                 goto out;
1102         }
1103
1104         if (!to_sx) {
1105                 int i = 0;
1106
1107                 /* Poll up to 5 seconds for Cable Disconnected indication */
1108                 while (!(er32(FEXT) & E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
1109                         /* Bail if link is re-acquired */
1110                         if (er32(STATUS) & E1000_STATUS_LU)
1111                                 return -E1000_ERR_PHY;
1112
1113                         if (i++ == 100)
1114                                 break;
1115
1116                         msleep(50);
1117                 }
1118                 e_dbg("CABLE_DISCONNECTED %s set after %dmsec\n",
1119                       (er32(FEXT) &
1120                        E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not", i * 50);
1121         }
1122
1123         ret_val = hw->phy.ops.acquire(hw);
1124         if (ret_val)
1125                 goto out;
1126
1127         /* Force SMBus mode in PHY */
1128         ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1129         if (ret_val)
1130                 goto release;
1131         phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1132         e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1133
1134         /* Force SMBus mode in MAC */
1135         mac_reg = er32(CTRL_EXT);
1136         mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1137         ew32(CTRL_EXT, mac_reg);
1138
1139         /* Si workaround for ULP entry flow on i127/rev6 h/w.  Enable
1140          * LPLU and disable Gig speed when entering ULP
1141          */
1142         if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) {
1143                 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS,
1144                                                        &oem_reg);
1145                 if (ret_val)
1146                         goto release;
1147
1148                 phy_reg = oem_reg;
1149                 phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS;
1150
1151                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1152                                                         phy_reg);
1153
1154                 if (ret_val)
1155                         goto release;
1156         }
1157
1158         /* Set Inband ULP Exit, Reset to SMBus mode and
1159          * Disable SMBus Release on PERST# in PHY
1160          */
1161         ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1162         if (ret_val)
1163                 goto release;
1164         phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1165                     I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1166         if (to_sx) {
1167                 if (er32(WUFC) & E1000_WUFC_LNKC)
1168                         phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1169                 else
1170                         phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1171
1172                 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1173                 phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT;
1174         } else {
1175                 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1176                 phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP;
1177                 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1178         }
1179         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1180
1181         /* Set Disable SMBus Release on PERST# in MAC */
1182         mac_reg = er32(FEXTNVM7);
1183         mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1184         ew32(FEXTNVM7, mac_reg);
1185
1186         /* Commit ULP changes in PHY by starting auto ULP configuration */
1187         phy_reg |= I218_ULP_CONFIG1_START;
1188         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1189
1190         if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) &&
1191             to_sx && (er32(STATUS) & E1000_STATUS_LU)) {
1192                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1193                                                         oem_reg);
1194                 if (ret_val)
1195                         goto release;
1196         }
1197
1198 release:
1199         hw->phy.ops.release(hw);
1200 out:
1201         if (ret_val)
1202                 e_dbg("Error in ULP enable flow: %d\n", ret_val);
1203         else
1204                 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1205
1206         return ret_val;
1207 }
1208
1209 /**
1210  *  e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1211  *  @hw: pointer to the HW structure
1212  *  @force: boolean indicating whether or not to force disabling ULP
1213  *
1214  *  Un-configure ULP mode when link is up, the system is transitioned from
1215  *  Sx or the driver is unloaded.  If on a Manageability Engine (ME) enabled
1216  *  system, poll for an indication from ME that ULP has been un-configured.
1217  *  If not on an ME enabled system, un-configure the ULP mode by software.
1218  *
1219  *  During nominal operation, this function is called when link is acquired
1220  *  to disable ULP mode (force=false); otherwise, for example when unloading
1221  *  the driver or during Sx->S0 transitions, this is called with force=true
1222  *  to forcibly disable ULP.
1223  */
1224 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1225 {
1226         s32 ret_val = 0;
1227         u32 mac_reg;
1228         u16 phy_reg;
1229         int i = 0;
1230
1231         if ((hw->mac.type < e1000_pch_lpt) ||
1232             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1233             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) ||
1234             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) ||
1235             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) ||
1236             (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
1237                 return 0;
1238
1239         if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
1240                 if (force) {
1241                         /* Request ME un-configure ULP mode in the PHY */
1242                         mac_reg = er32(H2ME);
1243                         mac_reg &= ~E1000_H2ME_ULP;
1244                         mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1245                         ew32(H2ME, mac_reg);
1246                 }
1247
1248                 /* Poll up to 300msec for ME to clear ULP_CFG_DONE. */
1249                 while (er32(FWSM) & E1000_FWSM_ULP_CFG_DONE) {
1250                         if (i++ == 30) {
1251                                 ret_val = -E1000_ERR_PHY;
1252                                 goto out;
1253                         }
1254
1255                         usleep_range(10000, 11000);
1256                 }
1257                 e_dbg("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
1258
1259                 if (force) {
1260                         mac_reg = er32(H2ME);
1261                         mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
1262                         ew32(H2ME, mac_reg);
1263                 } else {
1264                         /* Clear H2ME.ULP after ME ULP configuration */
1265                         mac_reg = er32(H2ME);
1266                         mac_reg &= ~E1000_H2ME_ULP;
1267                         ew32(H2ME, mac_reg);
1268                 }
1269
1270                 goto out;
1271         }
1272
1273         ret_val = hw->phy.ops.acquire(hw);
1274         if (ret_val)
1275                 goto out;
1276
1277         if (force)
1278                 /* Toggle LANPHYPC Value bit */
1279                 e1000_toggle_lanphypc_pch_lpt(hw);
1280
1281         /* Unforce SMBus mode in PHY */
1282         ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1283         if (ret_val) {
1284                 /* The MAC might be in PCIe mode, so temporarily force to
1285                  * SMBus mode in order to access the PHY.
1286                  */
1287                 mac_reg = er32(CTRL_EXT);
1288                 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1289                 ew32(CTRL_EXT, mac_reg);
1290
1291                 msleep(50);
1292
1293                 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1294                                                        &phy_reg);
1295                 if (ret_val)
1296                         goto release;
1297         }
1298         phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1299         e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1300
1301         /* Unforce SMBus mode in MAC */
1302         mac_reg = er32(CTRL_EXT);
1303         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
1304         ew32(CTRL_EXT, mac_reg);
1305
1306         /* When ULP mode was previously entered, K1 was disabled by the
1307          * hardware.  Re-Enable K1 in the PHY when exiting ULP.
1308          */
1309         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1310         if (ret_val)
1311                 goto release;
1312         phy_reg |= HV_PM_CTRL_K1_ENABLE;
1313         e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
1314
1315         /* Clear ULP enabled configuration */
1316         ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1317         if (ret_val)
1318                 goto release;
1319         phy_reg &= ~(I218_ULP_CONFIG1_IND |
1320                      I218_ULP_CONFIG1_STICKY_ULP |
1321                      I218_ULP_CONFIG1_RESET_TO_SMBUS |
1322                      I218_ULP_CONFIG1_WOL_HOST |
1323                      I218_ULP_CONFIG1_INBAND_EXIT |
1324                      I218_ULP_CONFIG1_EN_ULP_LANPHYPC |
1325                      I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST |
1326                      I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1327         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1328
1329         /* Commit ULP changes by starting auto ULP configuration */
1330         phy_reg |= I218_ULP_CONFIG1_START;
1331         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1332
1333         /* Clear Disable SMBus Release on PERST# in MAC */
1334         mac_reg = er32(FEXTNVM7);
1335         mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
1336         ew32(FEXTNVM7, mac_reg);
1337
1338 release:
1339         hw->phy.ops.release(hw);
1340         if (force) {
1341                 e1000_phy_hw_reset(hw);
1342                 msleep(50);
1343         }
1344 out:
1345         if (ret_val)
1346                 e_dbg("Error in ULP disable flow: %d\n", ret_val);
1347         else
1348                 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
1349
1350         return ret_val;
1351 }
1352
1353 /**
1354  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1355  *  @hw: pointer to the HW structure
1356  *
1357  *  Checks to see of the link status of the hardware has changed.  If a
1358  *  change in link status has been detected, then we read the PHY registers
1359  *  to get the current speed/duplex if link exists.
1360  **/
1361 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1362 {
1363         struct e1000_mac_info *mac = &hw->mac;
1364         s32 ret_val, tipg_reg = 0;
1365         u16 emi_addr, emi_val = 0;
1366         bool link;
1367         u16 phy_reg;
1368
1369         /* We only want to go out to the PHY registers to see if Auto-Neg
1370          * has completed and/or if our link status has changed.  The
1371          * get_link_status flag is set upon receiving a Link Status
1372          * Change or Rx Sequence Error interrupt.
1373          */
1374         if (!mac->get_link_status)
1375                 return 0;
1376         mac->get_link_status = false;
1377
1378         /* First we want to see if the MII Status Register reports
1379          * link.  If so, then we want to get the current speed/duplex
1380          * of the PHY.
1381          */
1382         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1383         if (ret_val)
1384                 goto out;
1385
1386         if (hw->mac.type == e1000_pchlan) {
1387                 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1388                 if (ret_val)
1389                         goto out;
1390         }
1391
1392         /* When connected at 10Mbps half-duplex, some parts are excessively
1393          * aggressive resulting in many collisions. To avoid this, increase
1394          * the IPG and reduce Rx latency in the PHY.
1395          */
1396         if ((hw->mac.type >= e1000_pch2lan) && link) {
1397                 u16 speed, duplex;
1398
1399                 e1000e_get_speed_and_duplex_copper(hw, &speed, &duplex);
1400                 tipg_reg = er32(TIPG);
1401                 tipg_reg &= ~E1000_TIPG_IPGT_MASK;
1402
1403                 if (duplex == HALF_DUPLEX && speed == SPEED_10) {
1404                         tipg_reg |= 0xFF;
1405                         /* Reduce Rx latency in analog PHY */
1406                         emi_val = 0;
1407                 } else if (hw->mac.type >= e1000_pch_spt &&
1408                            duplex == FULL_DUPLEX && speed != SPEED_1000) {
1409                         tipg_reg |= 0xC;
1410                         emi_val = 1;
1411                 } else {
1412
1413                         /* Roll back the default values */
1414                         tipg_reg |= 0x08;
1415                         emi_val = 1;
1416                 }
1417
1418                 ew32(TIPG, tipg_reg);
1419
1420                 ret_val = hw->phy.ops.acquire(hw);
1421                 if (ret_val)
1422                         goto out;
1423
1424                 if (hw->mac.type == e1000_pch2lan)
1425                         emi_addr = I82579_RX_CONFIG;
1426                 else
1427                         emi_addr = I217_RX_CONFIG;
1428                 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val);
1429
1430                 if (hw->mac.type >= e1000_pch_lpt) {
1431                         u16 phy_reg;
1432
1433                         e1e_rphy_locked(hw, I217_PLL_CLOCK_GATE_REG, &phy_reg);
1434                         phy_reg &= ~I217_PLL_CLOCK_GATE_MASK;
1435                         if (speed == SPEED_100 || speed == SPEED_10)
1436                                 phy_reg |= 0x3E8;
1437                         else
1438                                 phy_reg |= 0xFA;
1439                         e1e_wphy_locked(hw, I217_PLL_CLOCK_GATE_REG, phy_reg);
1440
1441                         if (speed == SPEED_1000) {
1442                                 hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL,
1443                                                             &phy_reg);
1444
1445                                 phy_reg |= HV_PM_CTRL_K1_CLK_REQ;
1446
1447                                 hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL,
1448                                                              phy_reg);
1449                         }
1450                 }
1451                 hw->phy.ops.release(hw);
1452
1453                 if (ret_val)
1454                         goto out;
1455
1456                 if (hw->mac.type >= e1000_pch_spt) {
1457                         u16 data;
1458                         u16 ptr_gap;
1459
1460                         if (speed == SPEED_1000) {
1461                                 ret_val = hw->phy.ops.acquire(hw);
1462                                 if (ret_val)
1463                                         goto out;
1464
1465                                 ret_val = e1e_rphy_locked(hw,
1466                                                           PHY_REG(776, 20),
1467                                                           &data);
1468                                 if (ret_val) {
1469                                         hw->phy.ops.release(hw);
1470                                         goto out;
1471                                 }
1472
1473                                 ptr_gap = (data & (0x3FF << 2)) >> 2;
1474                                 if (ptr_gap < 0x18) {
1475                                         data &= ~(0x3FF << 2);
1476                                         data |= (0x18 << 2);
1477                                         ret_val =
1478                                             e1e_wphy_locked(hw,
1479                                                             PHY_REG(776, 20),
1480                                                             data);
1481                                 }
1482                                 hw->phy.ops.release(hw);
1483                                 if (ret_val)
1484                                         goto out;
1485                         } else {
1486                                 ret_val = hw->phy.ops.acquire(hw);
1487                                 if (ret_val)
1488                                         goto out;
1489
1490                                 ret_val = e1e_wphy_locked(hw,
1491                                                           PHY_REG(776, 20),
1492                                                           0xC023);
1493                                 hw->phy.ops.release(hw);
1494                                 if (ret_val)
1495                                         goto out;
1496
1497                         }
1498                 }
1499         }
1500
1501         /* I217 Packet Loss issue:
1502          * ensure that FEXTNVM4 Beacon Duration is set correctly
1503          * on power up.
1504          * Set the Beacon Duration for I217 to 8 usec
1505          */
1506         if (hw->mac.type >= e1000_pch_lpt) {
1507                 u32 mac_reg;
1508
1509                 mac_reg = er32(FEXTNVM4);
1510                 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1511                 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1512                 ew32(FEXTNVM4, mac_reg);
1513         }
1514
1515         /* Work-around I218 hang issue */
1516         if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1517             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1518             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM3) ||
1519             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V3)) {
1520                 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1521                 if (ret_val)
1522                         goto out;
1523         }
1524         if (hw->mac.type >= e1000_pch_lpt) {
1525                 /* Set platform power management values for
1526                  * Latency Tolerance Reporting (LTR)
1527                  */
1528                 ret_val = e1000_platform_pm_pch_lpt(hw, link);
1529                 if (ret_val)
1530                         goto out;
1531         }
1532
1533         /* Clear link partner's EEE ability */
1534         hw->dev_spec.ich8lan.eee_lp_ability = 0;
1535
1536         if (hw->mac.type >= e1000_pch_lpt) {
1537                 u32 fextnvm6 = er32(FEXTNVM6);
1538
1539                 if (hw->mac.type == e1000_pch_spt) {
1540                         /* FEXTNVM6 K1-off workaround - for SPT only */
1541                         u32 pcieanacfg = er32(PCIEANACFG);
1542
1543                         if (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE)
1544                                 fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE;
1545                         else
1546                                 fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
1547                 }
1548
1549                 ew32(FEXTNVM6, fextnvm6);
1550         }
1551
1552         if (!link)
1553                 goto out;
1554
1555         switch (hw->mac.type) {
1556         case e1000_pch2lan:
1557                 ret_val = e1000_k1_workaround_lv(hw);
1558                 if (ret_val)
1559                         return ret_val;
1560                 fallthrough;
1561         case e1000_pchlan:
1562                 if (hw->phy.type == e1000_phy_82578) {
1563                         ret_val = e1000_link_stall_workaround_hv(hw);
1564                         if (ret_val)
1565                                 return ret_val;
1566                 }
1567
1568                 /* Workaround for PCHx parts in half-duplex:
1569                  * Set the number of preambles removed from the packet
1570                  * when it is passed from the PHY to the MAC to prevent
1571                  * the MAC from misinterpreting the packet type.
1572                  */
1573                 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1574                 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1575
1576                 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD)
1577                         phy_reg |= BIT(HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1578
1579                 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1580                 break;
1581         default:
1582                 break;
1583         }
1584
1585         /* Check if there was DownShift, must be checked
1586          * immediately after link-up
1587          */
1588         e1000e_check_downshift(hw);
1589
1590         /* Enable/Disable EEE after link up */
1591         if (hw->phy.type > e1000_phy_82579) {
1592                 ret_val = e1000_set_eee_pchlan(hw);
1593                 if (ret_val)
1594                         return ret_val;
1595         }
1596
1597         /* If we are forcing speed/duplex, then we simply return since
1598          * we have already determined whether we have link or not.
1599          */
1600         if (!mac->autoneg)
1601                 return -E1000_ERR_CONFIG;
1602
1603         /* Auto-Neg is enabled.  Auto Speed Detection takes care
1604          * of MAC speed/duplex configuration.  So we only need to
1605          * configure Collision Distance in the MAC.
1606          */
1607         mac->ops.config_collision_dist(hw);
1608
1609         /* Configure Flow Control now that Auto-Neg has completed.
1610          * First, we need to restore the desired flow control
1611          * settings because we may have had to re-autoneg with a
1612          * different link partner.
1613          */
1614         ret_val = e1000e_config_fc_after_link_up(hw);
1615         if (ret_val)
1616                 e_dbg("Error configuring flow control\n");
1617
1618         return ret_val;
1619
1620 out:
1621         mac->get_link_status = true;
1622         return ret_val;
1623 }
1624
1625 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
1626 {
1627         struct e1000_hw *hw = &adapter->hw;
1628         s32 rc;
1629
1630         rc = e1000_init_mac_params_ich8lan(hw);
1631         if (rc)
1632                 return rc;
1633
1634         rc = e1000_init_nvm_params_ich8lan(hw);
1635         if (rc)
1636                 return rc;
1637
1638         switch (hw->mac.type) {
1639         case e1000_ich8lan:
1640         case e1000_ich9lan:
1641         case e1000_ich10lan:
1642                 rc = e1000_init_phy_params_ich8lan(hw);
1643                 break;
1644         case e1000_pchlan:
1645         case e1000_pch2lan:
1646         case e1000_pch_lpt:
1647         case e1000_pch_spt:
1648         case e1000_pch_cnp:
1649         case e1000_pch_tgp:
1650         case e1000_pch_adp:
1651                 rc = e1000_init_phy_params_pchlan(hw);
1652                 break;
1653         default:
1654                 break;
1655         }
1656         if (rc)
1657                 return rc;
1658
1659         /* Disable Jumbo Frame support on parts with Intel 10/100 PHY or
1660          * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
1661          */
1662         if ((adapter->hw.phy.type == e1000_phy_ife) ||
1663             ((adapter->hw.mac.type >= e1000_pch2lan) &&
1664              (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) {
1665                 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
1666                 adapter->max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
1667
1668                 hw->mac.ops.blink_led = NULL;
1669         }
1670
1671         if ((adapter->hw.mac.type == e1000_ich8lan) &&
1672             (adapter->hw.phy.type != e1000_phy_ife))
1673                 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
1674
1675         /* Enable workaround for 82579 w/ ME enabled */
1676         if ((adapter->hw.mac.type == e1000_pch2lan) &&
1677             (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
1678                 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA;
1679
1680         return 0;
1681 }
1682
1683 static DEFINE_MUTEX(nvm_mutex);
1684
1685 /**
1686  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1687  *  @hw: pointer to the HW structure
1688  *
1689  *  Acquires the mutex for performing NVM operations.
1690  **/
1691 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1692 {
1693         mutex_lock(&nvm_mutex);
1694
1695         return 0;
1696 }
1697
1698 /**
1699  *  e1000_release_nvm_ich8lan - Release NVM mutex
1700  *  @hw: pointer to the HW structure
1701  *
1702  *  Releases the mutex used while performing NVM operations.
1703  **/
1704 static void e1000_release_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1705 {
1706         mutex_unlock(&nvm_mutex);
1707 }
1708
1709 /**
1710  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
1711  *  @hw: pointer to the HW structure
1712  *
1713  *  Acquires the software control flag for performing PHY and select
1714  *  MAC CSR accesses.
1715  **/
1716 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1717 {
1718         u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1719         s32 ret_val = 0;
1720
1721         if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE,
1722                              &hw->adapter->state)) {
1723                 e_dbg("contention for Phy access\n");
1724                 return -E1000_ERR_PHY;
1725         }
1726
1727         while (timeout) {
1728                 extcnf_ctrl = er32(EXTCNF_CTRL);
1729                 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1730                         break;
1731
1732                 mdelay(1);
1733                 timeout--;
1734         }
1735
1736         if (!timeout) {
1737                 e_dbg("SW has already locked the resource.\n");
1738                 ret_val = -E1000_ERR_CONFIG;
1739                 goto out;
1740         }
1741
1742         timeout = SW_FLAG_TIMEOUT;
1743
1744         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1745         ew32(EXTCNF_CTRL, extcnf_ctrl);
1746
1747         while (timeout) {
1748                 extcnf_ctrl = er32(EXTCNF_CTRL);
1749                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1750                         break;
1751
1752                 mdelay(1);
1753                 timeout--;
1754         }
1755
1756         if (!timeout) {
1757                 e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1758                       er32(FWSM), extcnf_ctrl);
1759                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1760                 ew32(EXTCNF_CTRL, extcnf_ctrl);
1761                 ret_val = -E1000_ERR_CONFIG;
1762                 goto out;
1763         }
1764
1765 out:
1766         if (ret_val)
1767                 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1768
1769         return ret_val;
1770 }
1771
1772 /**
1773  *  e1000_release_swflag_ich8lan - Release software control flag
1774  *  @hw: pointer to the HW structure
1775  *
1776  *  Releases the software control flag for performing PHY and select
1777  *  MAC CSR accesses.
1778  **/
1779 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1780 {
1781         u32 extcnf_ctrl;
1782
1783         extcnf_ctrl = er32(EXTCNF_CTRL);
1784
1785         if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1786                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1787                 ew32(EXTCNF_CTRL, extcnf_ctrl);
1788         } else {
1789                 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");
1790         }
1791
1792         clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1793 }
1794
1795 /**
1796  *  e1000_check_mng_mode_ich8lan - Checks management mode
1797  *  @hw: pointer to the HW structure
1798  *
1799  *  This checks if the adapter has any manageability enabled.
1800  *  This is a function pointer entry point only called by read/write
1801  *  routines for the PHY and NVM parts.
1802  **/
1803 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1804 {
1805         u32 fwsm;
1806
1807         fwsm = er32(FWSM);
1808         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1809                 ((fwsm & E1000_FWSM_MODE_MASK) ==
1810                  (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1811 }
1812
1813 /**
1814  *  e1000_check_mng_mode_pchlan - Checks management mode
1815  *  @hw: pointer to the HW structure
1816  *
1817  *  This checks if the adapter has iAMT enabled.
1818  *  This is a function pointer entry point only called by read/write
1819  *  routines for the PHY and NVM parts.
1820  **/
1821 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1822 {
1823         u32 fwsm;
1824
1825         fwsm = er32(FWSM);
1826         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1827             (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1828 }
1829
1830 /**
1831  *  e1000_rar_set_pch2lan - Set receive address register
1832  *  @hw: pointer to the HW structure
1833  *  @addr: pointer to the receive address
1834  *  @index: receive address array register
1835  *
1836  *  Sets the receive address array register at index to the address passed
1837  *  in by addr.  For 82579, RAR[0] is the base address register that is to
1838  *  contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1839  *  Use SHRA[0-3] in place of those reserved for ME.
1840  **/
1841 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1842 {
1843         u32 rar_low, rar_high;
1844
1845         /* HW expects these in little endian so we reverse the byte order
1846          * from network order (big endian) to little endian
1847          */
1848         rar_low = ((u32)addr[0] |
1849                    ((u32)addr[1] << 8) |
1850                    ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1851
1852         rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1853
1854         /* If MAC address zero, no need to set the AV bit */
1855         if (rar_low || rar_high)
1856                 rar_high |= E1000_RAH_AV;
1857
1858         if (index == 0) {
1859                 ew32(RAL(index), rar_low);
1860                 e1e_flush();
1861                 ew32(RAH(index), rar_high);
1862                 e1e_flush();
1863                 return 0;
1864         }
1865
1866         /* RAR[1-6] are owned by manageability.  Skip those and program the
1867          * next address into the SHRA register array.
1868          */
1869         if (index < (u32)(hw->mac.rar_entry_count)) {
1870                 s32 ret_val;
1871
1872                 ret_val = e1000_acquire_swflag_ich8lan(hw);
1873                 if (ret_val)
1874                         goto out;
1875
1876                 ew32(SHRAL(index - 1), rar_low);
1877                 e1e_flush();
1878                 ew32(SHRAH(index - 1), rar_high);
1879                 e1e_flush();
1880
1881                 e1000_release_swflag_ich8lan(hw);
1882
1883                 /* verify the register updates */
1884                 if ((er32(SHRAL(index - 1)) == rar_low) &&
1885                     (er32(SHRAH(index - 1)) == rar_high))
1886                         return 0;
1887
1888                 e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1889                       (index - 1), er32(FWSM));
1890         }
1891
1892 out:
1893         e_dbg("Failed to write receive address at index %d\n", index);
1894         return -E1000_ERR_CONFIG;
1895 }
1896
1897 /**
1898  *  e1000_rar_get_count_pch_lpt - Get the number of available SHRA
1899  *  @hw: pointer to the HW structure
1900  *
1901  *  Get the number of available receive registers that the Host can
1902  *  program. SHRA[0-10] are the shared receive address registers
1903  *  that are shared between the Host and manageability engine (ME).
1904  *  ME can reserve any number of addresses and the host needs to be
1905  *  able to tell how many available registers it has access to.
1906  **/
1907 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw)
1908 {
1909         u32 wlock_mac;
1910         u32 num_entries;
1911
1912         wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
1913         wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1914
1915         switch (wlock_mac) {
1916         case 0:
1917                 /* All SHRA[0..10] and RAR[0] available */
1918                 num_entries = hw->mac.rar_entry_count;
1919                 break;
1920         case 1:
1921                 /* Only RAR[0] available */
1922                 num_entries = 1;
1923                 break;
1924         default:
1925                 /* SHRA[0..(wlock_mac - 1)] available + RAR[0] */
1926                 num_entries = wlock_mac + 1;
1927                 break;
1928         }
1929
1930         return num_entries;
1931 }
1932
1933 /**
1934  *  e1000_rar_set_pch_lpt - Set receive address registers
1935  *  @hw: pointer to the HW structure
1936  *  @addr: pointer to the receive address
1937  *  @index: receive address array register
1938  *
1939  *  Sets the receive address register array at index to the address passed
1940  *  in by addr. For LPT, RAR[0] is the base address register that is to
1941  *  contain the MAC address. SHRA[0-10] are the shared receive address
1942  *  registers that are shared between the Host and manageability engine (ME).
1943  **/
1944 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
1945 {
1946         u32 rar_low, rar_high;
1947         u32 wlock_mac;
1948
1949         /* HW expects these in little endian so we reverse the byte order
1950          * from network order (big endian) to little endian
1951          */
1952         rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
1953                    ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1954
1955         rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1956
1957         /* If MAC address zero, no need to set the AV bit */
1958         if (rar_low || rar_high)
1959                 rar_high |= E1000_RAH_AV;
1960
1961         if (index == 0) {
1962                 ew32(RAL(index), rar_low);
1963                 e1e_flush();
1964                 ew32(RAH(index), rar_high);
1965                 e1e_flush();
1966                 return 0;
1967         }
1968
1969         /* The manageability engine (ME) can lock certain SHRAR registers that
1970          * it is using - those registers are unavailable for use.
1971          */
1972         if (index < hw->mac.rar_entry_count) {
1973                 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
1974                 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1975
1976                 /* Check if all SHRAR registers are locked */
1977                 if (wlock_mac == 1)
1978                         goto out;
1979
1980                 if ((wlock_mac == 0) || (index <= wlock_mac)) {
1981                         s32 ret_val;
1982
1983                         ret_val = e1000_acquire_swflag_ich8lan(hw);
1984
1985                         if (ret_val)
1986                                 goto out;
1987
1988                         ew32(SHRAL_PCH_LPT(index - 1), rar_low);
1989                         e1e_flush();
1990                         ew32(SHRAH_PCH_LPT(index - 1), rar_high);
1991                         e1e_flush();
1992
1993                         e1000_release_swflag_ich8lan(hw);
1994
1995                         /* verify the register updates */
1996                         if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) &&
1997                             (er32(SHRAH_PCH_LPT(index - 1)) == rar_high))
1998                                 return 0;
1999                 }
2000         }
2001
2002 out:
2003         e_dbg("Failed to write receive address at index %d\n", index);
2004         return -E1000_ERR_CONFIG;
2005 }
2006
2007 /**
2008  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
2009  *  @hw: pointer to the HW structure
2010  *
2011  *  Checks if firmware is blocking the reset of the PHY.
2012  *  This is a function pointer entry point only called by
2013  *  reset routines.
2014  **/
2015 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
2016 {
2017         bool blocked = false;
2018         int i = 0;
2019
2020         while ((blocked = !(er32(FWSM) & E1000_ICH_FWSM_RSPCIPHY)) &&
2021                (i++ < 30))
2022                 usleep_range(10000, 11000);
2023         return blocked ? E1000_BLK_PHY_RESET : 0;
2024 }
2025
2026 /**
2027  *  e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
2028  *  @hw: pointer to the HW structure
2029  *
2030  *  Assumes semaphore already acquired.
2031  *
2032  **/
2033 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
2034 {
2035         u16 phy_data;
2036         u32 strap = er32(STRAP);
2037         u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
2038             E1000_STRAP_SMT_FREQ_SHIFT;
2039         s32 ret_val;
2040
2041         strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
2042
2043         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
2044         if (ret_val)
2045                 return ret_val;
2046
2047         phy_data &= ~HV_SMB_ADDR_MASK;
2048         phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
2049         phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
2050
2051         if (hw->phy.type == e1000_phy_i217) {
2052                 /* Restore SMBus frequency */
2053                 if (freq--) {
2054                         phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
2055                         phy_data |= (freq & BIT(0)) <<
2056                             HV_SMB_ADDR_FREQ_LOW_SHIFT;
2057                         phy_data |= (freq & BIT(1)) <<
2058                             (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
2059                 } else {
2060                         e_dbg("Unsupported SMB frequency in PHY\n");
2061                 }
2062         }
2063
2064         return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
2065 }
2066
2067 /**
2068  *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
2069  *  @hw:   pointer to the HW structure
2070  *
2071  *  SW should configure the LCD from the NVM extended configuration region
2072  *  as a workaround for certain parts.
2073  **/
2074 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
2075 {
2076         struct e1000_phy_info *phy = &hw->phy;
2077         u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
2078         s32 ret_val = 0;
2079         u16 word_addr, reg_data, reg_addr, phy_page = 0;
2080
2081         /* Initialize the PHY from the NVM on ICH platforms.  This
2082          * is needed due to an issue where the NVM configuration is
2083          * not properly autoloaded after power transitions.
2084          * Therefore, after each PHY reset, we will load the
2085          * configuration data out of the NVM manually.
2086          */
2087         switch (hw->mac.type) {
2088         case e1000_ich8lan:
2089                 if (phy->type != e1000_phy_igp_3)
2090                         return ret_val;
2091
2092                 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
2093                     (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
2094                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
2095                         break;
2096                 }
2097                 fallthrough;
2098         case e1000_pchlan:
2099         case e1000_pch2lan:
2100         case e1000_pch_lpt:
2101         case e1000_pch_spt:
2102         case e1000_pch_cnp:
2103         case e1000_pch_tgp:
2104         case e1000_pch_adp:
2105                 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
2106                 break;
2107         default:
2108                 return ret_val;
2109         }
2110
2111         ret_val = hw->phy.ops.acquire(hw);
2112         if (ret_val)
2113                 return ret_val;
2114
2115         data = er32(FEXTNVM);
2116         if (!(data & sw_cfg_mask))
2117                 goto release;
2118
2119         /* Make sure HW does not configure LCD from PHY
2120          * extended configuration before SW configuration
2121          */
2122         data = er32(EXTCNF_CTRL);
2123         if ((hw->mac.type < e1000_pch2lan) &&
2124             (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
2125                 goto release;
2126
2127         cnf_size = er32(EXTCNF_SIZE);
2128         cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
2129         cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
2130         if (!cnf_size)
2131                 goto release;
2132
2133         cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
2134         cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
2135
2136         if (((hw->mac.type == e1000_pchlan) &&
2137              !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
2138             (hw->mac.type > e1000_pchlan)) {
2139                 /* HW configures the SMBus address and LEDs when the
2140                  * OEM and LCD Write Enable bits are set in the NVM.
2141                  * When both NVM bits are cleared, SW will configure
2142                  * them instead.
2143                  */
2144                 ret_val = e1000_write_smbus_addr(hw);
2145                 if (ret_val)
2146                         goto release;
2147
2148                 data = er32(LEDCTL);
2149                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
2150                                                         (u16)data);
2151                 if (ret_val)
2152                         goto release;
2153         }
2154
2155         /* Configure LCD from extended configuration region. */
2156
2157         /* cnf_base_addr is in DWORD */
2158         word_addr = (u16)(cnf_base_addr << 1);
2159
2160         for (i = 0; i < cnf_size; i++) {
2161                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, &reg_data);
2162                 if (ret_val)
2163                         goto release;
2164
2165                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
2166                                          1, &reg_addr);
2167                 if (ret_val)
2168                         goto release;
2169
2170                 /* Save off the PHY page for future writes. */
2171                 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
2172                         phy_page = reg_data;
2173                         continue;
2174                 }
2175
2176                 reg_addr &= PHY_REG_MASK;
2177                 reg_addr |= phy_page;
2178
2179                 ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data);
2180                 if (ret_val)
2181                         goto release;
2182         }
2183
2184 release:
2185         hw->phy.ops.release(hw);
2186         return ret_val;
2187 }
2188
2189 /**
2190  *  e1000_k1_gig_workaround_hv - K1 Si workaround
2191  *  @hw:   pointer to the HW structure
2192  *  @link: link up bool flag
2193  *
2194  *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
2195  *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
2196  *  If link is down, the function will restore the default K1 setting located
2197  *  in the NVM.
2198  **/
2199 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
2200 {
2201         s32 ret_val = 0;
2202         u16 status_reg = 0;
2203         bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
2204
2205         if (hw->mac.type != e1000_pchlan)
2206                 return 0;
2207
2208         /* Wrap the whole flow with the sw flag */
2209         ret_val = hw->phy.ops.acquire(hw);
2210         if (ret_val)
2211                 return ret_val;
2212
2213         /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
2214         if (link) {
2215                 if (hw->phy.type == e1000_phy_82578) {
2216                         ret_val = e1e_rphy_locked(hw, BM_CS_STATUS,
2217                                                   &status_reg);
2218                         if (ret_val)
2219                                 goto release;
2220
2221                         status_reg &= (BM_CS_STATUS_LINK_UP |
2222                                        BM_CS_STATUS_RESOLVED |
2223                                        BM_CS_STATUS_SPEED_MASK);
2224
2225                         if (status_reg == (BM_CS_STATUS_LINK_UP |
2226                                            BM_CS_STATUS_RESOLVED |
2227                                            BM_CS_STATUS_SPEED_1000))
2228                                 k1_enable = false;
2229                 }
2230
2231                 if (hw->phy.type == e1000_phy_82577) {
2232                         ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg);
2233                         if (ret_val)
2234                                 goto release;
2235
2236                         status_reg &= (HV_M_STATUS_LINK_UP |
2237                                        HV_M_STATUS_AUTONEG_COMPLETE |
2238                                        HV_M_STATUS_SPEED_MASK);
2239
2240                         if (status_reg == (HV_M_STATUS_LINK_UP |
2241                                            HV_M_STATUS_AUTONEG_COMPLETE |
2242                                            HV_M_STATUS_SPEED_1000))
2243                                 k1_enable = false;
2244                 }
2245
2246                 /* Link stall fix for link up */
2247                 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100);
2248                 if (ret_val)
2249                         goto release;
2250
2251         } else {
2252                 /* Link stall fix for link down */
2253                 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100);
2254                 if (ret_val)
2255                         goto release;
2256         }
2257
2258         ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2259
2260 release:
2261         hw->phy.ops.release(hw);
2262
2263         return ret_val;
2264 }
2265
2266 /**
2267  *  e1000_configure_k1_ich8lan - Configure K1 power state
2268  *  @hw: pointer to the HW structure
2269  *  @enable: K1 state to configure
2270  *
2271  *  Configure the K1 power state based on the provided parameter.
2272  *  Assumes semaphore already acquired.
2273  *
2274  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2275  **/
2276 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
2277 {
2278         s32 ret_val;
2279         u32 ctrl_reg = 0;
2280         u32 ctrl_ext = 0;
2281         u32 reg = 0;
2282         u16 kmrn_reg = 0;
2283
2284         ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2285                                               &kmrn_reg);
2286         if (ret_val)
2287                 return ret_val;
2288
2289         if (k1_enable)
2290                 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
2291         else
2292                 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
2293
2294         ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2295                                                kmrn_reg);
2296         if (ret_val)
2297                 return ret_val;
2298
2299         usleep_range(20, 40);
2300         ctrl_ext = er32(CTRL_EXT);
2301         ctrl_reg = er32(CTRL);
2302
2303         reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2304         reg |= E1000_CTRL_FRCSPD;
2305         ew32(CTRL, reg);
2306
2307         ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
2308         e1e_flush();
2309         usleep_range(20, 40);
2310         ew32(CTRL, ctrl_reg);
2311         ew32(CTRL_EXT, ctrl_ext);
2312         e1e_flush();
2313         usleep_range(20, 40);
2314
2315         return 0;
2316 }
2317
2318 /**
2319  *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2320  *  @hw:       pointer to the HW structure
2321  *  @d0_state: boolean if entering d0 or d3 device state
2322  *
2323  *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
2324  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
2325  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
2326  **/
2327 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
2328 {
2329         s32 ret_val = 0;
2330         u32 mac_reg;
2331         u16 oem_reg;
2332
2333         if (hw->mac.type < e1000_pchlan)
2334                 return ret_val;
2335
2336         ret_val = hw->phy.ops.acquire(hw);
2337         if (ret_val)
2338                 return ret_val;
2339
2340         if (hw->mac.type == e1000_pchlan) {
2341                 mac_reg = er32(EXTCNF_CTRL);
2342                 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
2343                         goto release;
2344         }
2345
2346         mac_reg = er32(FEXTNVM);
2347         if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
2348                 goto release;
2349
2350         mac_reg = er32(PHY_CTRL);
2351
2352         ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg);
2353         if (ret_val)
2354                 goto release;
2355
2356         oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
2357
2358         if (d0_state) {
2359                 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
2360                         oem_reg |= HV_OEM_BITS_GBE_DIS;
2361
2362                 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
2363                         oem_reg |= HV_OEM_BITS_LPLU;
2364         } else {
2365                 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
2366                                E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
2367                         oem_reg |= HV_OEM_BITS_GBE_DIS;
2368
2369                 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
2370                                E1000_PHY_CTRL_NOND0A_LPLU))
2371                         oem_reg |= HV_OEM_BITS_LPLU;
2372         }
2373
2374         /* Set Restart auto-neg to activate the bits */
2375         if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
2376             !hw->phy.ops.check_reset_block(hw))
2377                 oem_reg |= HV_OEM_BITS_RESTART_AN;
2378
2379         ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg);
2380
2381 release:
2382         hw->phy.ops.release(hw);
2383
2384         return ret_val;
2385 }
2386
2387 /**
2388  *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2389  *  @hw:   pointer to the HW structure
2390  **/
2391 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
2392 {
2393         s32 ret_val;
2394         u16 data;
2395
2396         ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
2397         if (ret_val)
2398                 return ret_val;
2399
2400         data |= HV_KMRN_MDIO_SLOW;
2401
2402         ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
2403
2404         return ret_val;
2405 }
2406
2407 /**
2408  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2409  *  done after every PHY reset.
2410  **/
2411 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2412 {
2413         s32 ret_val = 0;
2414         u16 phy_data;
2415
2416         if (hw->mac.type != e1000_pchlan)
2417                 return 0;
2418
2419         /* Set MDIO slow mode before any other MDIO access */
2420         if (hw->phy.type == e1000_phy_82577) {
2421                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2422                 if (ret_val)
2423                         return ret_val;
2424         }
2425
2426         if (((hw->phy.type == e1000_phy_82577) &&
2427              ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
2428             ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
2429                 /* Disable generation of early preamble */
2430                 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
2431                 if (ret_val)
2432                         return ret_val;
2433
2434                 /* Preamble tuning for SSC */
2435                 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204);
2436                 if (ret_val)
2437                         return ret_val;
2438         }
2439
2440         if (hw->phy.type == e1000_phy_82578) {
2441                 /* Return registers to default by doing a soft reset then
2442                  * writing 0x3140 to the control register.
2443                  */
2444                 if (hw->phy.revision < 2) {
2445                         e1000e_phy_sw_reset(hw);
2446                         ret_val = e1e_wphy(hw, MII_BMCR, 0x3140);
2447                         if (ret_val)
2448                                 return ret_val;
2449                 }
2450         }
2451
2452         /* Select page 0 */
2453         ret_val = hw->phy.ops.acquire(hw);
2454         if (ret_val)
2455                 return ret_val;
2456
2457         hw->phy.addr = 1;
2458         ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2459         hw->phy.ops.release(hw);
2460         if (ret_val)
2461                 return ret_val;
2462
2463         /* Configure the K1 Si workaround during phy reset assuming there is
2464          * link so that it disables K1 if link is in 1Gbps.
2465          */
2466         ret_val = e1000_k1_gig_workaround_hv(hw, true);
2467         if (ret_val)
2468                 return ret_val;
2469
2470         /* Workaround for link disconnects on a busy hub in half duplex */
2471         ret_val = hw->phy.ops.acquire(hw);
2472         if (ret_val)
2473                 return ret_val;
2474         ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2475         if (ret_val)
2476                 goto release;
2477         ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF);
2478         if (ret_val)
2479                 goto release;
2480
2481         /* set MSE higher to enable link to stay up when noise is high */
2482         ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2483 release:
2484         hw->phy.ops.release(hw);
2485
2486         return ret_val;
2487 }
2488
2489 /**
2490  *  e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2491  *  @hw:   pointer to the HW structure
2492  **/
2493 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
2494 {
2495         u32 mac_reg;
2496         u16 i, phy_reg = 0;
2497         s32 ret_val;
2498
2499         ret_val = hw->phy.ops.acquire(hw);
2500         if (ret_val)
2501                 return;
2502         ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2503         if (ret_val)
2504                 goto release;
2505
2506         /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
2507         for (i = 0; i < (hw->mac.rar_entry_count); i++) {
2508                 mac_reg = er32(RAL(i));
2509                 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
2510                                            (u16)(mac_reg & 0xFFFF));
2511                 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
2512                                            (u16)((mac_reg >> 16) & 0xFFFF));
2513
2514                 mac_reg = er32(RAH(i));
2515                 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
2516                                            (u16)(mac_reg & 0xFFFF));
2517                 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
2518                                            (u16)((mac_reg & E1000_RAH_AV)
2519                                                  >> 16));
2520         }
2521
2522         e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2523
2524 release:
2525         hw->phy.ops.release(hw);
2526 }
2527
2528 /**
2529  *  e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2530  *  with 82579 PHY
2531  *  @hw: pointer to the HW structure
2532  *  @enable: flag to enable/disable workaround when enabling/disabling jumbos
2533  **/
2534 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2535 {
2536         s32 ret_val = 0;
2537         u16 phy_reg, data;
2538         u32 mac_reg;
2539         u16 i;
2540
2541         if (hw->mac.type < e1000_pch2lan)
2542                 return 0;
2543
2544         /* disable Rx path while enabling/disabling workaround */
2545         e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
2546         ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | BIT(14));
2547         if (ret_val)
2548                 return ret_val;
2549
2550         if (enable) {
2551                 /* Write Rx addresses (rar_entry_count for RAL/H, and
2552                  * SHRAL/H) and initial CRC values to the MAC
2553                  */
2554                 for (i = 0; i < hw->mac.rar_entry_count; i++) {
2555                         u8 mac_addr[ETH_ALEN] = { 0 };
2556                         u32 addr_high, addr_low;
2557
2558                         addr_high = er32(RAH(i));
2559                         if (!(addr_high & E1000_RAH_AV))
2560                                 continue;
2561                         addr_low = er32(RAL(i));
2562                         mac_addr[0] = (addr_low & 0xFF);
2563                         mac_addr[1] = ((addr_low >> 8) & 0xFF);
2564                         mac_addr[2] = ((addr_low >> 16) & 0xFF);
2565                         mac_addr[3] = ((addr_low >> 24) & 0xFF);
2566                         mac_addr[4] = (addr_high & 0xFF);
2567                         mac_addr[5] = ((addr_high >> 8) & 0xFF);
2568
2569                         ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr));
2570                 }
2571
2572                 /* Write Rx addresses to the PHY */
2573                 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2574
2575                 /* Enable jumbo frame workaround in the MAC */
2576                 mac_reg = er32(FFLT_DBG);
2577                 mac_reg &= ~BIT(14);
2578                 mac_reg |= (7 << 15);
2579                 ew32(FFLT_DBG, mac_reg);
2580
2581                 mac_reg = er32(RCTL);
2582                 mac_reg |= E1000_RCTL_SECRC;
2583                 ew32(RCTL, mac_reg);
2584
2585                 ret_val = e1000e_read_kmrn_reg(hw,
2586                                                E1000_KMRNCTRLSTA_CTRL_OFFSET,
2587                                                &data);
2588                 if (ret_val)
2589                         return ret_val;
2590                 ret_val = e1000e_write_kmrn_reg(hw,
2591                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2592                                                 data | BIT(0));
2593                 if (ret_val)
2594                         return ret_val;
2595                 ret_val = e1000e_read_kmrn_reg(hw,
2596                                                E1000_KMRNCTRLSTA_HD_CTRL,
2597                                                &data);
2598                 if (ret_val)
2599                         return ret_val;
2600                 data &= ~(0xF << 8);
2601                 data |= (0xB << 8);
2602                 ret_val = e1000e_write_kmrn_reg(hw,
2603                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2604                                                 data);
2605                 if (ret_val)
2606                         return ret_val;
2607
2608                 /* Enable jumbo frame workaround in the PHY */
2609                 e1e_rphy(hw, PHY_REG(769, 23), &data);
2610                 data &= ~(0x7F << 5);
2611                 data |= (0x37 << 5);
2612                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2613                 if (ret_val)
2614                         return ret_val;
2615                 e1e_rphy(hw, PHY_REG(769, 16), &data);
2616                 data &= ~BIT(13);
2617                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2618                 if (ret_val)
2619                         return ret_val;
2620                 e1e_rphy(hw, PHY_REG(776, 20), &data);
2621                 data &= ~(0x3FF << 2);
2622                 data |= (E1000_TX_PTR_GAP << 2);
2623                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2624                 if (ret_val)
2625                         return ret_val;
2626                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100);
2627                 if (ret_val)
2628                         return ret_val;
2629                 e1e_rphy(hw, HV_PM_CTRL, &data);
2630                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | BIT(10));
2631                 if (ret_val)
2632                         return ret_val;
2633         } else {
2634                 /* Write MAC register values back to h/w defaults */
2635                 mac_reg = er32(FFLT_DBG);
2636                 mac_reg &= ~(0xF << 14);
2637                 ew32(FFLT_DBG, mac_reg);
2638
2639                 mac_reg = er32(RCTL);
2640                 mac_reg &= ~E1000_RCTL_SECRC;
2641                 ew32(RCTL, mac_reg);
2642
2643                 ret_val = e1000e_read_kmrn_reg(hw,
2644                                                E1000_KMRNCTRLSTA_CTRL_OFFSET,
2645                                                &data);
2646                 if (ret_val)
2647                         return ret_val;
2648                 ret_val = e1000e_write_kmrn_reg(hw,
2649                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2650                                                 data & ~BIT(0));
2651                 if (ret_val)
2652                         return ret_val;
2653                 ret_val = e1000e_read_kmrn_reg(hw,
2654                                                E1000_KMRNCTRLSTA_HD_CTRL,
2655                                                &data);
2656                 if (ret_val)
2657                         return ret_val;
2658                 data &= ~(0xF << 8);
2659                 data |= (0xB << 8);
2660                 ret_val = e1000e_write_kmrn_reg(hw,
2661                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2662                                                 data);
2663                 if (ret_val)
2664                         return ret_val;
2665
2666                 /* Write PHY register values back to h/w defaults */
2667                 e1e_rphy(hw, PHY_REG(769, 23), &data);
2668                 data &= ~(0x7F << 5);
2669                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2670                 if (ret_val)
2671                         return ret_val;
2672                 e1e_rphy(hw, PHY_REG(769, 16), &data);
2673                 data |= BIT(13);
2674                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2675                 if (ret_val)
2676                         return ret_val;
2677                 e1e_rphy(hw, PHY_REG(776, 20), &data);
2678                 data &= ~(0x3FF << 2);
2679                 data |= (0x8 << 2);
2680                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2681                 if (ret_val)
2682                         return ret_val;
2683                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
2684                 if (ret_val)
2685                         return ret_val;
2686                 e1e_rphy(hw, HV_PM_CTRL, &data);
2687                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~BIT(10));
2688                 if (ret_val)
2689                         return ret_val;
2690         }
2691
2692         /* re-enable Rx path after enabling/disabling workaround */
2693         return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~BIT(14));
2694 }
2695
2696 /**
2697  *  e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2698  *  done after every PHY reset.
2699  **/
2700 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2701 {
2702         s32 ret_val = 0;
2703
2704         if (hw->mac.type != e1000_pch2lan)
2705                 return 0;
2706
2707         /* Set MDIO slow mode before any other MDIO access */
2708         ret_val = e1000_set_mdio_slow_mode_hv(hw);
2709         if (ret_val)
2710                 return ret_val;
2711
2712         ret_val = hw->phy.ops.acquire(hw);
2713         if (ret_val)
2714                 return ret_val;
2715         /* set MSE higher to enable link to stay up when noise is high */
2716         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2717         if (ret_val)
2718                 goto release;
2719         /* drop link after 5 times MSE threshold was reached */
2720         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2721 release:
2722         hw->phy.ops.release(hw);
2723
2724         return ret_val;
2725 }
2726
2727 /**
2728  *  e1000_k1_gig_workaround_lv - K1 Si workaround
2729  *  @hw:   pointer to the HW structure
2730  *
2731  *  Workaround to set the K1 beacon duration for 82579 parts in 10Mbps
2732  *  Disable K1 in 1000Mbps and 100Mbps
2733  **/
2734 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2735 {
2736         s32 ret_val = 0;
2737         u16 status_reg = 0;
2738
2739         if (hw->mac.type != e1000_pch2lan)
2740                 return 0;
2741
2742         /* Set K1 beacon duration based on 10Mbs speed */
2743         ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
2744         if (ret_val)
2745                 return ret_val;
2746
2747         if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2748             == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2749                 if (status_reg &
2750                     (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) {
2751                         u16 pm_phy_reg;
2752
2753                         /* LV 1G/100 Packet drop issue wa  */
2754                         ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg);
2755                         if (ret_val)
2756                                 return ret_val;
2757                         pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE;
2758                         ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg);
2759                         if (ret_val)
2760                                 return ret_val;
2761                 } else {
2762                         u32 mac_reg;
2763
2764                         mac_reg = er32(FEXTNVM4);
2765                         mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
2766                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
2767                         ew32(FEXTNVM4, mac_reg);
2768                 }
2769         }
2770
2771         return ret_val;
2772 }
2773
2774 /**
2775  *  e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2776  *  @hw:   pointer to the HW structure
2777  *  @gate: boolean set to true to gate, false to ungate
2778  *
2779  *  Gate/ungate the automatic PHY configuration via hardware; perform
2780  *  the configuration via software instead.
2781  **/
2782 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2783 {
2784         u32 extcnf_ctrl;
2785
2786         if (hw->mac.type < e1000_pch2lan)
2787                 return;
2788
2789         extcnf_ctrl = er32(EXTCNF_CTRL);
2790
2791         if (gate)
2792                 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2793         else
2794                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2795
2796         ew32(EXTCNF_CTRL, extcnf_ctrl);
2797 }
2798
2799 /**
2800  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
2801  *  @hw: pointer to the HW structure
2802  *
2803  *  Check the appropriate indication the MAC has finished configuring the
2804  *  PHY after a software reset.
2805  **/
2806 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2807 {
2808         u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
2809
2810         /* Wait for basic configuration completes before proceeding */
2811         do {
2812                 data = er32(STATUS);
2813                 data &= E1000_STATUS_LAN_INIT_DONE;
2814                 usleep_range(100, 200);
2815         } while ((!data) && --loop);
2816
2817         /* If basic configuration is incomplete before the above loop
2818          * count reaches 0, loading the configuration from NVM will
2819          * leave the PHY in a bad state possibly resulting in no link.
2820          */
2821         if (loop == 0)
2822                 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
2823
2824         /* Clear the Init Done bit for the next init event */
2825         data = er32(STATUS);
2826         data &= ~E1000_STATUS_LAN_INIT_DONE;
2827         ew32(STATUS, data);
2828 }
2829
2830 /**
2831  *  e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
2832  *  @hw: pointer to the HW structure
2833  **/
2834 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
2835 {
2836         s32 ret_val = 0;
2837         u16 reg;
2838
2839         if (hw->phy.ops.check_reset_block(hw))
2840                 return 0;
2841
2842         /* Allow time for h/w to get to quiescent state after reset */
2843         usleep_range(10000, 11000);
2844
2845         /* Perform any necessary post-reset workarounds */
2846         switch (hw->mac.type) {
2847         case e1000_pchlan:
2848                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2849                 if (ret_val)
2850                         return ret_val;
2851                 break;
2852         case e1000_pch2lan:
2853                 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
2854                 if (ret_val)
2855                         return ret_val;
2856                 break;
2857         default:
2858                 break;
2859         }
2860
2861         /* Clear the host wakeup bit after lcd reset */
2862         if (hw->mac.type >= e1000_pchlan) {
2863                 e1e_rphy(hw, BM_PORT_GEN_CFG, &reg);
2864                 reg &= ~BM_WUC_HOST_WU_BIT;
2865                 e1e_wphy(hw, BM_PORT_GEN_CFG, reg);
2866         }
2867
2868         /* Configure the LCD with the extended configuration region in NVM */
2869         ret_val = e1000_sw_lcd_config_ich8lan(hw);
2870         if (ret_val)
2871                 return ret_val;
2872
2873         /* Configure the LCD with the OEM bits in NVM */
2874         ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2875
2876         if (hw->mac.type == e1000_pch2lan) {
2877                 /* Ungate automatic PHY configuration on non-managed 82579 */
2878                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
2879                         usleep_range(10000, 11000);
2880                         e1000_gate_hw_phy_config_ich8lan(hw, false);
2881                 }
2882
2883                 /* Set EEE LPI Update Timer to 200usec */
2884                 ret_val = hw->phy.ops.acquire(hw);
2885                 if (ret_val)
2886                         return ret_val;
2887                 ret_val = e1000_write_emi_reg_locked(hw,
2888                                                      I82579_LPI_UPDATE_TIMER,
2889                                                      0x1387);
2890                 hw->phy.ops.release(hw);
2891         }
2892
2893         return ret_val;
2894 }
2895
2896 /**
2897  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
2898  *  @hw: pointer to the HW structure
2899  *
2900  *  Resets the PHY
2901  *  This is a function pointer entry point called by drivers
2902  *  or other shared routines.
2903  **/
2904 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
2905 {
2906         s32 ret_val = 0;
2907
2908         /* Gate automatic PHY configuration by hardware on non-managed 82579 */
2909         if ((hw->mac.type == e1000_pch2lan) &&
2910             !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
2911                 e1000_gate_hw_phy_config_ich8lan(hw, true);
2912
2913         ret_val = e1000e_phy_hw_reset_generic(hw);
2914         if (ret_val)
2915                 return ret_val;
2916
2917         return e1000_post_phy_reset_ich8lan(hw);
2918 }
2919
2920 /**
2921  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
2922  *  @hw: pointer to the HW structure
2923  *  @active: true to enable LPLU, false to disable
2924  *
2925  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
2926  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
2927  *  the phy speed. This function will manually set the LPLU bit and restart
2928  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
2929  *  since it configures the same bit.
2930  **/
2931 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
2932 {
2933         s32 ret_val;
2934         u16 oem_reg;
2935
2936         ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
2937         if (ret_val)
2938                 return ret_val;
2939
2940         if (active)
2941                 oem_reg |= HV_OEM_BITS_LPLU;
2942         else
2943                 oem_reg &= ~HV_OEM_BITS_LPLU;
2944
2945         if (!hw->phy.ops.check_reset_block(hw))
2946                 oem_reg |= HV_OEM_BITS_RESTART_AN;
2947
2948         return e1e_wphy(hw, HV_OEM_BITS, oem_reg);
2949 }
2950
2951 /**
2952  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
2953  *  @hw: pointer to the HW structure
2954  *  @active: true to enable LPLU, false to disable
2955  *
2956  *  Sets the LPLU D0 state according to the active flag.  When
2957  *  activating LPLU this function also disables smart speed
2958  *  and vice versa.  LPLU will not be activated unless the
2959  *  device autonegotiation advertisement meets standards of
2960  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
2961  *  This is a function pointer entry point only called by
2962  *  PHY setup routines.
2963  **/
2964 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2965 {
2966         struct e1000_phy_info *phy = &hw->phy;
2967         u32 phy_ctrl;
2968         s32 ret_val = 0;
2969         u16 data;
2970
2971         if (phy->type == e1000_phy_ife)
2972                 return 0;
2973
2974         phy_ctrl = er32(PHY_CTRL);
2975
2976         if (active) {
2977                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2978                 ew32(PHY_CTRL, phy_ctrl);
2979
2980                 if (phy->type != e1000_phy_igp_3)
2981                         return 0;
2982
2983                 /* Call gig speed drop workaround on LPLU before accessing
2984                  * any PHY registers
2985                  */
2986                 if (hw->mac.type == e1000_ich8lan)
2987                         e1000e_gig_downshift_workaround_ich8lan(hw);
2988
2989                 /* When LPLU is enabled, we should disable SmartSpeed */
2990                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
2991                 if (ret_val)
2992                         return ret_val;
2993                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2994                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
2995                 if (ret_val)
2996                         return ret_val;
2997         } else {
2998                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2999                 ew32(PHY_CTRL, phy_ctrl);
3000
3001                 if (phy->type != e1000_phy_igp_3)
3002                         return 0;
3003
3004                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
3005                  * during Dx states where the power conservation is most
3006                  * important.  During driver activity we should enable
3007                  * SmartSpeed, so performance is maintained.
3008                  */
3009                 if (phy->smart_speed == e1000_smart_speed_on) {
3010                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3011                                            &data);
3012                         if (ret_val)
3013                                 return ret_val;
3014
3015                         data |= IGP01E1000_PSCFR_SMART_SPEED;
3016                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3017                                            data);
3018                         if (ret_val)
3019                                 return ret_val;
3020                 } else if (phy->smart_speed == e1000_smart_speed_off) {
3021                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3022                                            &data);
3023                         if (ret_val)
3024                                 return ret_val;
3025
3026                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3027                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3028                                            data);
3029                         if (ret_val)
3030                                 return ret_val;
3031                 }
3032         }
3033
3034         return 0;
3035 }
3036
3037 /**
3038  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
3039  *  @hw: pointer to the HW structure
3040  *  @active: true to enable LPLU, false to disable
3041  *
3042  *  Sets the LPLU D3 state according to the active flag.  When
3043  *  activating LPLU this function also disables smart speed
3044  *  and vice versa.  LPLU will not be activated unless the
3045  *  device autonegotiation advertisement meets standards of
3046  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
3047  *  This is a function pointer entry point only called by
3048  *  PHY setup routines.
3049  **/
3050 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3051 {
3052         struct e1000_phy_info *phy = &hw->phy;
3053         u32 phy_ctrl;
3054         s32 ret_val = 0;
3055         u16 data;
3056
3057         phy_ctrl = er32(PHY_CTRL);
3058
3059         if (!active) {
3060                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
3061                 ew32(PHY_CTRL, phy_ctrl);
3062
3063                 if (phy->type != e1000_phy_igp_3)
3064                         return 0;
3065
3066                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
3067                  * during Dx states where the power conservation is most
3068                  * important.  During driver activity we should enable
3069                  * SmartSpeed, so performance is maintained.
3070                  */
3071                 if (phy->smart_speed == e1000_smart_speed_on) {
3072                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3073                                            &data);
3074                         if (ret_val)
3075                                 return ret_val;
3076
3077                         data |= IGP01E1000_PSCFR_SMART_SPEED;
3078                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3079                                            data);
3080                         if (ret_val)
3081                                 return ret_val;
3082                 } else if (phy->smart_speed == e1000_smart_speed_off) {
3083                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3084                                            &data);
3085                         if (ret_val)
3086                                 return ret_val;
3087
3088                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3089                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3090                                            data);
3091                         if (ret_val)
3092                                 return ret_val;
3093                 }
3094         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
3095                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
3096                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
3097                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
3098                 ew32(PHY_CTRL, phy_ctrl);
3099
3100                 if (phy->type != e1000_phy_igp_3)
3101                         return 0;
3102
3103                 /* Call gig speed drop workaround on LPLU before accessing
3104                  * any PHY registers
3105                  */
3106                 if (hw->mac.type == e1000_ich8lan)
3107                         e1000e_gig_downshift_workaround_ich8lan(hw);
3108
3109                 /* When LPLU is enabled, we should disable SmartSpeed */
3110                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
3111                 if (ret_val)
3112                         return ret_val;
3113
3114                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3115                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
3116         }
3117
3118         return ret_val;
3119 }
3120
3121 /**
3122  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
3123  *  @hw: pointer to the HW structure
3124  *  @bank:  pointer to the variable that returns the active bank
3125  *
3126  *  Reads signature byte from the NVM using the flash access registers.
3127  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
3128  **/
3129 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
3130 {
3131         u32 eecd;
3132         struct e1000_nvm_info *nvm = &hw->nvm;
3133         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
3134         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
3135         u32 nvm_dword = 0;
3136         u8 sig_byte = 0;
3137         s32 ret_val;
3138
3139         switch (hw->mac.type) {
3140         case e1000_pch_spt:
3141         case e1000_pch_cnp:
3142         case e1000_pch_tgp:
3143         case e1000_pch_adp:
3144                 bank1_offset = nvm->flash_bank_size;
3145                 act_offset = E1000_ICH_NVM_SIG_WORD;
3146
3147                 /* set bank to 0 in case flash read fails */
3148                 *bank = 0;
3149
3150                 /* Check bank 0 */
3151                 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset,
3152                                                          &nvm_dword);
3153                 if (ret_val)
3154                         return ret_val;
3155                 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3156                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3157                     E1000_ICH_NVM_SIG_VALUE) {
3158                         *bank = 0;
3159                         return 0;
3160                 }
3161
3162                 /* Check bank 1 */
3163                 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset +
3164                                                          bank1_offset,
3165                                                          &nvm_dword);
3166                 if (ret_val)
3167                         return ret_val;
3168                 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3169                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3170                     E1000_ICH_NVM_SIG_VALUE) {
3171                         *bank = 1;
3172                         return 0;
3173                 }
3174
3175                 e_dbg("ERROR: No valid NVM bank present\n");
3176                 return -E1000_ERR_NVM;
3177         case e1000_ich8lan:
3178         case e1000_ich9lan:
3179                 eecd = er32(EECD);
3180                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
3181                     E1000_EECD_SEC1VAL_VALID_MASK) {
3182                         if (eecd & E1000_EECD_SEC1VAL)
3183                                 *bank = 1;
3184                         else
3185                                 *bank = 0;
3186
3187                         return 0;
3188                 }
3189                 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n");
3190                 fallthrough;
3191         default:
3192                 /* set bank to 0 in case flash read fails */
3193                 *bank = 0;
3194
3195                 /* Check bank 0 */
3196                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
3197                                                         &sig_byte);
3198                 if (ret_val)
3199                         return ret_val;
3200                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3201                     E1000_ICH_NVM_SIG_VALUE) {
3202                         *bank = 0;
3203                         return 0;
3204                 }
3205
3206                 /* Check bank 1 */
3207                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
3208                                                         bank1_offset,
3209                                                         &sig_byte);
3210                 if (ret_val)
3211                         return ret_val;
3212                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3213                     E1000_ICH_NVM_SIG_VALUE) {
3214                         *bank = 1;
3215                         return 0;
3216                 }
3217
3218                 e_dbg("ERROR: No valid NVM bank present\n");
3219                 return -E1000_ERR_NVM;
3220         }
3221 }
3222
3223 /**
3224  *  e1000_read_nvm_spt - NVM access for SPT
3225  *  @hw: pointer to the HW structure
3226  *  @offset: The offset (in bytes) of the word(s) to read.
3227  *  @words: Size of data to read in words.
3228  *  @data: pointer to the word(s) to read at offset.
3229  *
3230  *  Reads a word(s) from the NVM
3231  **/
3232 static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
3233                               u16 *data)
3234 {
3235         struct e1000_nvm_info *nvm = &hw->nvm;
3236         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3237         u32 act_offset;
3238         s32 ret_val = 0;
3239         u32 bank = 0;
3240         u32 dword = 0;
3241         u16 offset_to_read;
3242         u16 i;
3243
3244         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3245             (words == 0)) {
3246                 e_dbg("nvm parameter(s) out of bounds\n");
3247                 ret_val = -E1000_ERR_NVM;
3248                 goto out;
3249         }
3250
3251         nvm->ops.acquire(hw);
3252
3253         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3254         if (ret_val) {
3255                 e_dbg("Could not detect valid bank, assuming bank 0\n");
3256                 bank = 0;
3257         }
3258
3259         act_offset = (bank) ? nvm->flash_bank_size : 0;
3260         act_offset += offset;
3261
3262         ret_val = 0;
3263
3264         for (i = 0; i < words; i += 2) {
3265                 if (words - i == 1) {
3266                         if (dev_spec->shadow_ram[offset + i].modified) {
3267                                 data[i] =
3268                                     dev_spec->shadow_ram[offset + i].value;
3269                         } else {
3270                                 offset_to_read = act_offset + i -
3271                                     ((act_offset + i) % 2);
3272                                 ret_val =
3273                                   e1000_read_flash_dword_ich8lan(hw,
3274                                                                  offset_to_read,
3275                                                                  &dword);
3276                                 if (ret_val)
3277                                         break;
3278                                 if ((act_offset + i) % 2 == 0)
3279                                         data[i] = (u16)(dword & 0xFFFF);
3280                                 else
3281                                         data[i] = (u16)((dword >> 16) & 0xFFFF);
3282                         }
3283                 } else {
3284                         offset_to_read = act_offset + i;
3285                         if (!(dev_spec->shadow_ram[offset + i].modified) ||
3286                             !(dev_spec->shadow_ram[offset + i + 1].modified)) {
3287                                 ret_val =
3288                                   e1000_read_flash_dword_ich8lan(hw,
3289                                                                  offset_to_read,
3290                                                                  &dword);
3291                                 if (ret_val)
3292                                         break;
3293                         }
3294                         if (dev_spec->shadow_ram[offset + i].modified)
3295                                 data[i] =
3296                                     dev_spec->shadow_ram[offset + i].value;
3297                         else
3298                                 data[i] = (u16)(dword & 0xFFFF);
3299                         if (dev_spec->shadow_ram[offset + i].modified)
3300                                 data[i + 1] =
3301                                     dev_spec->shadow_ram[offset + i + 1].value;
3302                         else
3303                                 data[i + 1] = (u16)(dword >> 16 & 0xFFFF);
3304                 }
3305         }
3306
3307         nvm->ops.release(hw);
3308
3309 out:
3310         if (ret_val)
3311                 e_dbg("NVM read error: %d\n", ret_val);
3312
3313         return ret_val;
3314 }
3315
3316 /**
3317  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
3318  *  @hw: pointer to the HW structure
3319  *  @offset: The offset (in bytes) of the word(s) to read.
3320  *  @words: Size of data to read in words
3321  *  @data: Pointer to the word(s) to read at offset.
3322  *
3323  *  Reads a word(s) from the NVM using the flash access registers.
3324  **/
3325 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3326                                   u16 *data)
3327 {
3328         struct e1000_nvm_info *nvm = &hw->nvm;
3329         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3330         u32 act_offset;
3331         s32 ret_val = 0;
3332         u32 bank = 0;
3333         u16 i, word;
3334
3335         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3336             (words == 0)) {
3337                 e_dbg("nvm parameter(s) out of bounds\n");
3338                 ret_val = -E1000_ERR_NVM;
3339                 goto out;
3340         }
3341
3342         nvm->ops.acquire(hw);
3343
3344         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3345         if (ret_val) {
3346                 e_dbg("Could not detect valid bank, assuming bank 0\n");
3347                 bank = 0;
3348         }
3349
3350         act_offset = (bank) ? nvm->flash_bank_size : 0;
3351         act_offset += offset;
3352
3353         ret_val = 0;
3354         for (i = 0; i < words; i++) {
3355                 if (dev_spec->shadow_ram[offset + i].modified) {
3356                         data[i] = dev_spec->shadow_ram[offset + i].value;
3357                 } else {
3358                         ret_val = e1000_read_flash_word_ich8lan(hw,
3359                                                                 act_offset + i,
3360                                                                 &word);
3361                         if (ret_val)
3362                                 break;
3363                         data[i] = word;
3364                 }
3365         }
3366
3367         nvm->ops.release(hw);
3368
3369 out:
3370         if (ret_val)
3371                 e_dbg("NVM read error: %d\n", ret_val);
3372
3373         return ret_val;
3374 }
3375
3376 /**
3377  *  e1000_flash_cycle_init_ich8lan - Initialize flash
3378  *  @hw: pointer to the HW structure
3379  *
3380  *  This function does initial flash setup so that a new read/write/erase cycle
3381  *  can be started.
3382  **/
3383 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3384 {
3385         union ich8_hws_flash_status hsfsts;
3386         s32 ret_val = -E1000_ERR_NVM;
3387
3388         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3389
3390         /* Check if the flash descriptor is valid */
3391         if (!hsfsts.hsf_status.fldesvalid) {
3392                 e_dbg("Flash descriptor invalid.  SW Sequencing must be used.\n");
3393                 return -E1000_ERR_NVM;
3394         }
3395
3396         /* Clear FCERR and DAEL in hw status by writing 1 */
3397         hsfsts.hsf_status.flcerr = 1;
3398         hsfsts.hsf_status.dael = 1;
3399         if (hw->mac.type >= e1000_pch_spt)
3400                 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF);
3401         else
3402                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3403
3404         /* Either we should have a hardware SPI cycle in progress
3405          * bit to check against, in order to start a new cycle or
3406          * FDONE bit should be changed in the hardware so that it
3407          * is 1 after hardware reset, which can then be used as an
3408          * indication whether a cycle is in progress or has been
3409          * completed.
3410          */
3411
3412         if (!hsfsts.hsf_status.flcinprog) {
3413                 /* There is no cycle running at present,
3414                  * so we can start a cycle.
3415                  * Begin by setting Flash Cycle Done.
3416                  */
3417                 hsfsts.hsf_status.flcdone = 1;
3418                 if (hw->mac.type >= e1000_pch_spt)
3419                         ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF);
3420                 else
3421                         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3422                 ret_val = 0;
3423         } else {
3424                 s32 i;
3425
3426                 /* Otherwise poll for sometime so the current
3427                  * cycle has a chance to end before giving up.
3428                  */
3429                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
3430                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3431                         if (!hsfsts.hsf_status.flcinprog) {
3432                                 ret_val = 0;
3433                                 break;
3434                         }
3435                         udelay(1);
3436                 }
3437                 if (!ret_val) {
3438                         /* Successful in waiting for previous cycle to timeout,
3439                          * now set the Flash Cycle Done.
3440                          */
3441                         hsfsts.hsf_status.flcdone = 1;
3442                         if (hw->mac.type >= e1000_pch_spt)
3443                                 ew32flash(ICH_FLASH_HSFSTS,
3444                                           hsfsts.regval & 0xFFFF);
3445                         else
3446                                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3447                 } else {
3448                         e_dbg("Flash controller busy, cannot get access\n");
3449                 }
3450         }
3451
3452         return ret_val;
3453 }
3454
3455 /**
3456  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3457  *  @hw: pointer to the HW structure
3458  *  @timeout: maximum time to wait for completion
3459  *
3460  *  This function starts a flash cycle and waits for its completion.
3461  **/
3462 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3463 {
3464         union ich8_hws_flash_ctrl hsflctl;
3465         union ich8_hws_flash_status hsfsts;
3466         u32 i = 0;
3467
3468         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3469         if (hw->mac.type >= e1000_pch_spt)
3470                 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
3471         else
3472                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3473         hsflctl.hsf_ctrl.flcgo = 1;
3474
3475         if (hw->mac.type >= e1000_pch_spt)
3476                 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
3477         else
3478                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3479
3480         /* wait till FDONE bit is set to 1 */
3481         do {
3482                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3483                 if (hsfsts.hsf_status.flcdone)
3484                         break;
3485                 udelay(1);
3486         } while (i++ < timeout);
3487
3488         if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
3489                 return 0;
3490
3491         return -E1000_ERR_NVM;
3492 }
3493
3494 /**
3495  *  e1000_read_flash_dword_ich8lan - Read dword from flash
3496  *  @hw: pointer to the HW structure
3497  *  @offset: offset to data location
3498  *  @data: pointer to the location for storing the data
3499  *
3500  *  Reads the flash dword at offset into data.  Offset is converted
3501  *  to bytes before read.
3502  **/
3503 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset,
3504                                           u32 *data)
3505 {
3506         /* Must convert word offset into bytes. */
3507         offset <<= 1;
3508         return e1000_read_flash_data32_ich8lan(hw, offset, data);
3509 }
3510
3511 /**
3512  *  e1000_read_flash_word_ich8lan - Read word from flash
3513  *  @hw: pointer to the HW structure
3514  *  @offset: offset to data location
3515  *  @data: pointer to the location for storing the data
3516  *
3517  *  Reads the flash word at offset into data.  Offset is converted
3518  *  to bytes before read.
3519  **/
3520 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
3521                                          u16 *data)
3522 {
3523         /* Must convert offset into bytes. */
3524         offset <<= 1;
3525
3526         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
3527 }
3528
3529 /**
3530  *  e1000_read_flash_byte_ich8lan - Read byte from flash
3531  *  @hw: pointer to the HW structure
3532  *  @offset: The offset of the byte to read.
3533  *  @data: Pointer to a byte to store the value read.
3534  *
3535  *  Reads a single byte from the NVM using the flash access registers.
3536  **/
3537 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3538                                          u8 *data)
3539 {
3540         s32 ret_val;
3541         u16 word = 0;
3542
3543         /* In SPT, only 32 bits access is supported,
3544          * so this function should not be called.
3545          */
3546         if (hw->mac.type >= e1000_pch_spt)
3547                 return -E1000_ERR_NVM;
3548         else
3549                 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3550
3551         if (ret_val)
3552                 return ret_val;
3553
3554         *data = (u8)word;
3555
3556         return 0;
3557 }
3558
3559 /**
3560  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
3561  *  @hw: pointer to the HW structure
3562  *  @offset: The offset (in bytes) of the byte or word to read.
3563  *  @size: Size of data to read, 1=byte 2=word
3564  *  @data: Pointer to the word to store the value read.
3565  *
3566  *  Reads a byte or word from the NVM using the flash access registers.
3567  **/
3568 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3569                                          u8 size, u16 *data)
3570 {
3571         union ich8_hws_flash_status hsfsts;
3572         union ich8_hws_flash_ctrl hsflctl;
3573         u32 flash_linear_addr;
3574         u32 flash_data = 0;
3575         s32 ret_val = -E1000_ERR_NVM;
3576         u8 count = 0;
3577
3578         if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3579                 return -E1000_ERR_NVM;
3580
3581         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3582                              hw->nvm.flash_base_addr);
3583
3584         do {
3585                 udelay(1);
3586                 /* Steps */
3587                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3588                 if (ret_val)
3589                         break;
3590
3591                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3592                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3593                 hsflctl.hsf_ctrl.fldbcount = size - 1;
3594                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3595                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3596
3597                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3598
3599                 ret_val =
3600                     e1000_flash_cycle_ich8lan(hw,
3601                                               ICH_FLASH_READ_COMMAND_TIMEOUT);
3602
3603                 /* Check if FCERR is set to 1, if set to 1, clear it
3604                  * and try the whole sequence a few more times, else
3605                  * read in (shift in) the Flash Data0, the order is
3606                  * least significant byte first msb to lsb
3607                  */
3608                 if (!ret_val) {
3609                         flash_data = er32flash(ICH_FLASH_FDATA0);
3610                         if (size == 1)
3611                                 *data = (u8)(flash_data & 0x000000FF);
3612                         else if (size == 2)
3613                                 *data = (u16)(flash_data & 0x0000FFFF);
3614                         break;
3615                 } else {
3616                         /* If we've gotten here, then things are probably
3617                          * completely hosed, but if the error condition is
3618                          * detected, it won't hurt to give it another try...
3619                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3620                          */
3621                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3622                         if (hsfsts.hsf_status.flcerr) {
3623                                 /* Repeat for some time before giving up. */
3624                                 continue;
3625                         } else if (!hsfsts.hsf_status.flcdone) {
3626                                 e_dbg("Timeout error - flash cycle did not complete.\n");
3627                                 break;
3628                         }
3629                 }
3630         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3631
3632         return ret_val;
3633 }
3634
3635 /**
3636  *  e1000_read_flash_data32_ich8lan - Read dword from NVM
3637  *  @hw: pointer to the HW structure
3638  *  @offset: The offset (in bytes) of the dword to read.
3639  *  @data: Pointer to the dword to store the value read.
3640  *
3641  *  Reads a byte or word from the NVM using the flash access registers.
3642  **/
3643
3644 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
3645                                            u32 *data)
3646 {
3647         union ich8_hws_flash_status hsfsts;
3648         union ich8_hws_flash_ctrl hsflctl;
3649         u32 flash_linear_addr;
3650         s32 ret_val = -E1000_ERR_NVM;
3651         u8 count = 0;
3652
3653         if (offset > ICH_FLASH_LINEAR_ADDR_MASK || hw->mac.type < e1000_pch_spt)
3654                 return -E1000_ERR_NVM;
3655         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3656                              hw->nvm.flash_base_addr);
3657
3658         do {
3659                 udelay(1);
3660                 /* Steps */
3661                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3662                 if (ret_val)
3663                         break;
3664                 /* In SPT, This register is in Lan memory space, not flash.
3665                  * Therefore, only 32 bit access is supported
3666                  */
3667                 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
3668
3669                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3670                 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
3671                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3672                 /* In SPT, This register is in Lan memory space, not flash.
3673                  * Therefore, only 32 bit access is supported
3674                  */
3675                 ew32flash(ICH_FLASH_HSFSTS, (u32)hsflctl.regval << 16);
3676                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3677
3678                 ret_val =
3679                    e1000_flash_cycle_ich8lan(hw,
3680                                              ICH_FLASH_READ_COMMAND_TIMEOUT);
3681
3682                 /* Check if FCERR is set to 1, if set to 1, clear it
3683                  * and try the whole sequence a few more times, else
3684                  * read in (shift in) the Flash Data0, the order is
3685                  * least significant byte first msb to lsb
3686                  */
3687                 if (!ret_val) {
3688                         *data = er32flash(ICH_FLASH_FDATA0);
3689                         break;
3690                 } else {
3691                         /* If we've gotten here, then things are probably
3692                          * completely hosed, but if the error condition is
3693                          * detected, it won't hurt to give it another try...
3694                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3695                          */
3696                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3697                         if (hsfsts.hsf_status.flcerr) {
3698                                 /* Repeat for some time before giving up. */
3699                                 continue;
3700                         } else if (!hsfsts.hsf_status.flcdone) {
3701                                 e_dbg("Timeout error - flash cycle did not complete.\n");
3702                                 break;
3703                         }
3704                 }
3705         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3706
3707         return ret_val;
3708 }
3709
3710 /**
3711  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
3712  *  @hw: pointer to the HW structure
3713  *  @offset: The offset (in bytes) of the word(s) to write.
3714  *  @words: Size of data to write in words
3715  *  @data: Pointer to the word(s) to write at offset.
3716  *
3717  *  Writes a byte or word to the NVM using the flash access registers.
3718  **/
3719 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3720                                    u16 *data)
3721 {
3722         struct e1000_nvm_info *nvm = &hw->nvm;
3723         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3724         u16 i;
3725
3726         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3727             (words == 0)) {
3728                 e_dbg("nvm parameter(s) out of bounds\n");
3729                 return -E1000_ERR_NVM;
3730         }
3731
3732         nvm->ops.acquire(hw);
3733
3734         for (i = 0; i < words; i++) {
3735                 dev_spec->shadow_ram[offset + i].modified = true;
3736                 dev_spec->shadow_ram[offset + i].value = data[i];
3737         }
3738
3739         nvm->ops.release(hw);
3740
3741         return 0;
3742 }
3743
3744 /**
3745  *  e1000_update_nvm_checksum_spt - Update the checksum for NVM
3746  *  @hw: pointer to the HW structure
3747  *
3748  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
3749  *  which writes the checksum to the shadow ram.  The changes in the shadow
3750  *  ram are then committed to the EEPROM by processing each bank at a time
3751  *  checking for the modified bit and writing only the pending changes.
3752  *  After a successful commit, the shadow ram is cleared and is ready for
3753  *  future writes.
3754  **/
3755 static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw)
3756 {
3757         struct e1000_nvm_info *nvm = &hw->nvm;
3758         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3759         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3760         s32 ret_val;
3761         u32 dword = 0;
3762
3763         ret_val = e1000e_update_nvm_checksum_generic(hw);
3764         if (ret_val)
3765                 goto out;
3766
3767         if (nvm->type != e1000_nvm_flash_sw)
3768                 goto out;
3769
3770         nvm->ops.acquire(hw);
3771
3772         /* We're writing to the opposite bank so if we're on bank 1,
3773          * write to bank 0 etc.  We also need to erase the segment that
3774          * is going to be written
3775          */
3776         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3777         if (ret_val) {
3778                 e_dbg("Could not detect valid bank, assuming bank 0\n");
3779                 bank = 0;
3780         }
3781
3782         if (bank == 0) {
3783                 new_bank_offset = nvm->flash_bank_size;
3784                 old_bank_offset = 0;
3785                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3786                 if (ret_val)
3787                         goto release;
3788         } else {
3789                 old_bank_offset = nvm->flash_bank_size;
3790                 new_bank_offset = 0;
3791                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3792                 if (ret_val)
3793                         goto release;
3794         }
3795         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i += 2) {
3796                 /* Determine whether to write the value stored
3797                  * in the other NVM bank or a modified value stored
3798                  * in the shadow RAM
3799                  */
3800                 ret_val = e1000_read_flash_dword_ich8lan(hw,
3801                                                          i + old_bank_offset,
3802                                                          &dword);
3803
3804                 if (dev_spec->shadow_ram[i].modified) {
3805                         dword &= 0xffff0000;
3806                         dword |= (dev_spec->shadow_ram[i].value & 0xffff);
3807                 }
3808                 if (dev_spec->shadow_ram[i + 1].modified) {
3809                         dword &= 0x0000ffff;
3810                         dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff)
3811                                   << 16);
3812                 }
3813                 if (ret_val)
3814                         break;
3815
3816                 /* If the word is 0x13, then make sure the signature bits
3817                  * (15:14) are 11b until the commit has completed.
3818                  * This will allow us to write 10b which indicates the
3819                  * signature is valid.  We want to do this after the write
3820                  * has completed so that we don't mark the segment valid
3821                  * while the write is still in progress
3822                  */
3823                 if (i == E1000_ICH_NVM_SIG_WORD - 1)
3824                         dword |= E1000_ICH_NVM_SIG_MASK << 16;
3825
3826                 /* Convert offset to bytes. */
3827                 act_offset = (i + new_bank_offset) << 1;
3828
3829                 usleep_range(100, 200);
3830
3831                 /* Write the data to the new bank. Offset in words */
3832                 act_offset = i + new_bank_offset;
3833                 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset,
3834                                                                 dword);
3835                 if (ret_val)
3836                         break;
3837         }
3838
3839         /* Don't bother writing the segment valid bits if sector
3840          * programming failed.
3841          */
3842         if (ret_val) {
3843                 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
3844                 e_dbg("Flash commit failed.\n");
3845                 goto release;
3846         }
3847
3848         /* Finally validate the new segment by setting bit 15:14
3849          * to 10b in word 0x13 , this can be done without an
3850          * erase as well since these bits are 11 to start with
3851          * and we need to change bit 14 to 0b
3852          */
3853         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
3854
3855         /*offset in words but we read dword */
3856         --act_offset;
3857         ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
3858
3859         if (ret_val)
3860                 goto release;
3861
3862         dword &= 0xBFFFFFFF;
3863         ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
3864
3865         if (ret_val)
3866                 goto release;
3867
3868         /* And invalidate the previously valid segment by setting
3869          * its signature word (0x13) high_byte to 0b. This can be
3870          * done without an erase because flash erase sets all bits
3871          * to 1's. We can write 1's to 0's without an erase
3872          */
3873         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
3874
3875         /* offset in words but we read dword */
3876         act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1;
3877         ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
3878
3879         if (ret_val)
3880                 goto release;
3881
3882         dword &= 0x00FFFFFF;
3883         ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
3884
3885         if (ret_val)
3886                 goto release;
3887
3888         /* Great!  Everything worked, we can now clear the cached entries. */
3889         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
3890                 dev_spec->shadow_ram[i].modified = false;
3891                 dev_spec->shadow_ram[i].value = 0xFFFF;
3892         }
3893
3894 release:
3895         nvm->ops.release(hw);
3896
3897         /* Reload the EEPROM, or else modifications will not appear
3898          * until after the next adapter reset.
3899          */
3900         if (!ret_val) {
3901                 nvm->ops.reload(hw);
3902                 usleep_range(10000, 11000);
3903         }
3904
3905 out:
3906         if (ret_val)
3907                 e_dbg("NVM update error: %d\n", ret_val);
3908
3909         return ret_val;
3910 }
3911
3912 /**
3913  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
3914  *  @hw: pointer to the HW structure
3915  *
3916  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
3917  *  which writes the checksum to the shadow ram.  The changes in the shadow
3918  *  ram are then committed to the EEPROM by processing each bank at a time
3919  *  checking for the modified bit and writing only the pending changes.
3920  *  After a successful commit, the shadow ram is cleared and is ready for
3921  *  future writes.
3922  **/
3923 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
3924 {
3925         struct e1000_nvm_info *nvm = &hw->nvm;
3926         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3927         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3928         s32 ret_val;
3929         u16 data = 0;
3930
3931         ret_val = e1000e_update_nvm_checksum_generic(hw);
3932         if (ret_val)
3933                 goto out;
3934
3935         if (nvm->type != e1000_nvm_flash_sw)
3936                 goto out;
3937
3938         nvm->ops.acquire(hw);
3939
3940         /* We're writing to the opposite bank so if we're on bank 1,
3941          * write to bank 0 etc.  We also need to erase the segment that
3942          * is going to be written
3943          */
3944         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3945         if (ret_val) {
3946                 e_dbg("Could not detect valid bank, assuming bank 0\n");
3947                 bank = 0;
3948         }
3949
3950         if (bank == 0) {
3951                 new_bank_offset = nvm->flash_bank_size;
3952                 old_bank_offset = 0;
3953                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3954                 if (ret_val)
3955                         goto release;
3956         } else {
3957                 old_bank_offset = nvm->flash_bank_size;
3958                 new_bank_offset = 0;
3959                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3960                 if (ret_val)
3961                         goto release;
3962         }
3963         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
3964                 if (dev_spec->shadow_ram[i].modified) {
3965                         data = dev_spec->shadow_ram[i].value;
3966                 } else {
3967                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
3968                                                                 old_bank_offset,
3969                                                                 &data);
3970                         if (ret_val)
3971                                 break;
3972                 }
3973
3974                 /* If the word is 0x13, then make sure the signature bits
3975                  * (15:14) are 11b until the commit has completed.
3976                  * This will allow us to write 10b which indicates the
3977                  * signature is valid.  We want to do this after the write
3978                  * has completed so that we don't mark the segment valid
3979                  * while the write is still in progress
3980                  */
3981                 if (i == E1000_ICH_NVM_SIG_WORD)
3982                         data |= E1000_ICH_NVM_SIG_MASK;
3983
3984                 /* Convert offset to bytes. */
3985                 act_offset = (i + new_bank_offset) << 1;
3986
3987                 usleep_range(100, 200);
3988                 /* Write the bytes to the new bank. */
3989                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3990                                                                act_offset,
3991                                                                (u8)data);
3992                 if (ret_val)
3993                         break;
3994
3995                 usleep_range(100, 200);
3996                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3997                                                                act_offset + 1,
3998                                                                (u8)(data >> 8));
3999                 if (ret_val)
4000                         break;
4001         }
4002
4003         /* Don't bother writing the segment valid bits if sector
4004          * programming failed.
4005          */
4006         if (ret_val) {
4007                 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
4008                 e_dbg("Flash commit failed.\n");
4009                 goto release;
4010         }
4011
4012         /* Finally validate the new segment by setting bit 15:14
4013          * to 10b in word 0x13 , this can be done without an
4014          * erase as well since these bits are 11 to start with
4015          * and we need to change bit 14 to 0b
4016          */
4017         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
4018         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
4019         if (ret_val)
4020                 goto release;
4021
4022         data &= 0xBFFF;
4023         ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4024                                                        act_offset * 2 + 1,
4025                                                        (u8)(data >> 8));
4026         if (ret_val)
4027                 goto release;
4028
4029         /* And invalidate the previously valid segment by setting
4030          * its signature word (0x13) high_byte to 0b. This can be
4031          * done without an erase because flash erase sets all bits
4032          * to 1's. We can write 1's to 0's without an erase
4033          */
4034         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
4035         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
4036         if (ret_val)
4037                 goto release;
4038
4039         /* Great!  Everything worked, we can now clear the cached entries. */
4040         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
4041                 dev_spec->shadow_ram[i].modified = false;
4042                 dev_spec->shadow_ram[i].value = 0xFFFF;
4043         }
4044
4045 release:
4046         nvm->ops.release(hw);
4047
4048         /* Reload the EEPROM, or else modifications will not appear
4049          * until after the next adapter reset.
4050          */
4051         if (!ret_val) {
4052                 nvm->ops.reload(hw);
4053                 usleep_range(10000, 11000);
4054         }
4055
4056 out:
4057         if (ret_val)
4058                 e_dbg("NVM update error: %d\n", ret_val);
4059
4060         return ret_val;
4061 }
4062
4063 /**
4064  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
4065  *  @hw: pointer to the HW structure
4066  *
4067  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
4068  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
4069  *  calculated, in which case we need to calculate the checksum and set bit 6.
4070  **/
4071 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
4072 {
4073         s32 ret_val;
4074         u16 data;
4075         u16 word;
4076         u16 valid_csum_mask;
4077
4078         /* Read NVM and check Invalid Image CSUM bit.  If this bit is 0,
4079          * the checksum needs to be fixed.  This bit is an indication that
4080          * the NVM was prepared by OEM software and did not calculate
4081          * the checksum...a likely scenario.
4082          */
4083         switch (hw->mac.type) {
4084         case e1000_pch_lpt:
4085         case e1000_pch_spt:
4086         case e1000_pch_cnp:
4087         case e1000_pch_tgp:
4088         case e1000_pch_adp:
4089                 word = NVM_COMPAT;
4090                 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
4091                 break;
4092         default:
4093                 word = NVM_FUTURE_INIT_WORD1;
4094                 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
4095                 break;
4096         }
4097
4098         ret_val = e1000_read_nvm(hw, word, 1, &data);
4099         if (ret_val)
4100                 return ret_val;
4101
4102         if (!(data & valid_csum_mask)) {
4103                 data |= valid_csum_mask;
4104                 ret_val = e1000_write_nvm(hw, word, 1, &data);
4105                 if (ret_val)
4106                         return ret_val;
4107                 ret_val = e1000e_update_nvm_checksum(hw);
4108                 if (ret_val)
4109                         return ret_val;
4110         }
4111
4112         return e1000e_validate_nvm_checksum_generic(hw);
4113 }
4114
4115 /**
4116  *  e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
4117  *  @hw: pointer to the HW structure
4118  *
4119  *  To prevent malicious write/erase of the NVM, set it to be read-only
4120  *  so that the hardware ignores all write/erase cycles of the NVM via
4121  *  the flash control registers.  The shadow-ram copy of the NVM will
4122  *  still be updated, however any updates to this copy will not stick
4123  *  across driver reloads.
4124  **/
4125 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
4126 {
4127         struct e1000_nvm_info *nvm = &hw->nvm;
4128         union ich8_flash_protected_range pr0;
4129         union ich8_hws_flash_status hsfsts;
4130         u32 gfpreg;
4131
4132         nvm->ops.acquire(hw);
4133
4134         gfpreg = er32flash(ICH_FLASH_GFPREG);
4135
4136         /* Write-protect GbE Sector of NVM */
4137         pr0.regval = er32flash(ICH_FLASH_PR0);
4138         pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
4139         pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
4140         pr0.range.wpe = true;
4141         ew32flash(ICH_FLASH_PR0, pr0.regval);
4142
4143         /* Lock down a subset of GbE Flash Control Registers, e.g.
4144          * PR0 to prevent the write-protection from being lifted.
4145          * Once FLOCKDN is set, the registers protected by it cannot
4146          * be written until FLOCKDN is cleared by a hardware reset.
4147          */
4148         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4149         hsfsts.hsf_status.flockdn = true;
4150         ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
4151
4152         nvm->ops.release(hw);
4153 }
4154
4155 /**
4156  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
4157  *  @hw: pointer to the HW structure
4158  *  @offset: The offset (in bytes) of the byte/word to read.
4159  *  @size: Size of data to read, 1=byte 2=word
4160  *  @data: The byte(s) to write to the NVM.
4161  *
4162  *  Writes one/two bytes to the NVM using the flash access registers.
4163  **/
4164 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
4165                                           u8 size, u16 data)
4166 {
4167         union ich8_hws_flash_status hsfsts;
4168         union ich8_hws_flash_ctrl hsflctl;
4169         u32 flash_linear_addr;
4170         u32 flash_data = 0;
4171         s32 ret_val;
4172         u8 count = 0;
4173
4174         if (hw->mac.type >= e1000_pch_spt) {
4175                 if (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4176                         return -E1000_ERR_NVM;
4177         } else {
4178                 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4179                         return -E1000_ERR_NVM;
4180         }
4181
4182         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4183                              hw->nvm.flash_base_addr);
4184
4185         do {
4186                 udelay(1);
4187                 /* Steps */
4188                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4189                 if (ret_val)
4190                         break;
4191                 /* In SPT, This register is in Lan memory space, not
4192                  * flash.  Therefore, only 32 bit access is supported
4193                  */
4194                 if (hw->mac.type >= e1000_pch_spt)
4195                         hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
4196                 else
4197                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4198
4199                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
4200                 hsflctl.hsf_ctrl.fldbcount = size - 1;
4201                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4202                 /* In SPT, This register is in Lan memory space,
4203                  * not flash.  Therefore, only 32 bit access is
4204                  * supported
4205                  */
4206                 if (hw->mac.type >= e1000_pch_spt)
4207                         ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
4208                 else
4209                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4210
4211                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4212
4213                 if (size == 1)
4214                         flash_data = (u32)data & 0x00FF;
4215                 else
4216                         flash_data = (u32)data;
4217
4218                 ew32flash(ICH_FLASH_FDATA0, flash_data);
4219
4220                 /* check if FCERR is set to 1 , if set to 1, clear it
4221                  * and try the whole sequence a few more times else done
4222                  */
4223                 ret_val =
4224                     e1000_flash_cycle_ich8lan(hw,
4225                                               ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4226                 if (!ret_val)
4227                         break;
4228
4229                 /* If we're here, then things are most likely
4230                  * completely hosed, but if the error condition
4231                  * is detected, it won't hurt to give it another
4232                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4233                  */
4234                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4235                 if (hsfsts.hsf_status.flcerr)
4236                         /* Repeat for some time before giving up. */
4237                         continue;
4238                 if (!hsfsts.hsf_status.flcdone) {
4239                         e_dbg("Timeout error - flash cycle did not complete.\n");
4240                         break;
4241                 }
4242         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4243
4244         return ret_val;
4245 }
4246
4247 /**
4248 *  e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM
4249 *  @hw: pointer to the HW structure
4250 *  @offset: The offset (in bytes) of the dwords to read.
4251 *  @data: The 4 bytes to write to the NVM.
4252 *
4253 *  Writes one/two/four bytes to the NVM using the flash access registers.
4254 **/
4255 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
4256                                             u32 data)
4257 {
4258         union ich8_hws_flash_status hsfsts;
4259         union ich8_hws_flash_ctrl hsflctl;
4260         u32 flash_linear_addr;
4261         s32 ret_val;
4262         u8 count = 0;
4263
4264         if (hw->mac.type >= e1000_pch_spt) {
4265                 if (offset > ICH_FLASH_LINEAR_ADDR_MASK)
4266                         return -E1000_ERR_NVM;
4267         }
4268         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4269                              hw->nvm.flash_base_addr);
4270         do {
4271                 udelay(1);
4272                 /* Steps */
4273                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4274                 if (ret_val)
4275                         break;
4276
4277                 /* In SPT, This register is in Lan memory space, not
4278                  * flash.  Therefore, only 32 bit access is supported
4279                  */
4280                 if (hw->mac.type >= e1000_pch_spt)
4281                         hsflctl.regval = er32flash(ICH_FLASH_HSFSTS)
4282                             >> 16;
4283                 else
4284                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4285
4286                 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
4287                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4288
4289                 /* In SPT, This register is in Lan memory space,
4290                  * not flash.  Therefore, only 32 bit access is
4291                  * supported
4292                  */
4293                 if (hw->mac.type >= e1000_pch_spt)
4294                         ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
4295                 else
4296                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4297
4298                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4299
4300                 ew32flash(ICH_FLASH_FDATA0, data);
4301
4302                 /* check if FCERR is set to 1 , if set to 1, clear it
4303                  * and try the whole sequence a few more times else done
4304                  */
4305                 ret_val =
4306                    e1000_flash_cycle_ich8lan(hw,
4307                                              ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4308
4309                 if (!ret_val)
4310                         break;
4311
4312                 /* If we're here, then things are most likely
4313                  * completely hosed, but if the error condition
4314                  * is detected, it won't hurt to give it another
4315                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4316                  */
4317                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4318
4319                 if (hsfsts.hsf_status.flcerr)
4320                         /* Repeat for some time before giving up. */
4321                         continue;
4322                 if (!hsfsts.hsf_status.flcdone) {
4323                         e_dbg("Timeout error - flash cycle did not complete.\n");
4324                         break;
4325                 }
4326         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4327
4328         return ret_val;
4329 }
4330
4331 /**
4332  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
4333  *  @hw: pointer to the HW structure
4334  *  @offset: The index of the byte to read.
4335  *  @data: The byte to write to the NVM.
4336  *
4337  *  Writes a single byte to the NVM using the flash access registers.
4338  **/
4339 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
4340                                           u8 data)
4341 {
4342         u16 word = (u16)data;
4343
4344         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
4345 }
4346
4347 /**
4348 *  e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM
4349 *  @hw: pointer to the HW structure
4350 *  @offset: The offset of the word to write.
4351 *  @dword: The dword to write to the NVM.
4352 *
4353 *  Writes a single dword to the NVM using the flash access registers.
4354 *  Goes through a retry algorithm before giving up.
4355 **/
4356 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
4357                                                  u32 offset, u32 dword)
4358 {
4359         s32 ret_val;
4360         u16 program_retries;
4361
4362         /* Must convert word offset into bytes. */
4363         offset <<= 1;
4364         ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4365
4366         if (!ret_val)
4367                 return ret_val;
4368         for (program_retries = 0; program_retries < 100; program_retries++) {
4369                 e_dbg("Retrying Byte %8.8X at offset %u\n", dword, offset);
4370                 usleep_range(100, 200);
4371                 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4372                 if (!ret_val)
4373                         break;
4374         }
4375         if (program_retries == 100)
4376                 return -E1000_ERR_NVM;
4377
4378         return 0;
4379 }
4380
4381 /**
4382  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
4383  *  @hw: pointer to the HW structure
4384  *  @offset: The offset of the byte to write.
4385  *  @byte: The byte to write to the NVM.
4386  *
4387  *  Writes a single byte to the NVM using the flash access registers.
4388  *  Goes through a retry algorithm before giving up.
4389  **/
4390 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
4391                                                 u32 offset, u8 byte)
4392 {
4393         s32 ret_val;
4394         u16 program_retries;
4395
4396         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4397         if (!ret_val)
4398                 return ret_val;
4399
4400         for (program_retries = 0; program_retries < 100; program_retries++) {
4401                 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
4402                 usleep_range(100, 200);
4403                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4404                 if (!ret_val)
4405                         break;
4406         }
4407         if (program_retries == 100)
4408                 return -E1000_ERR_NVM;
4409
4410         return 0;
4411 }
4412
4413 /**
4414  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
4415  *  @hw: pointer to the HW structure
4416  *  @bank: 0 for first bank, 1 for second bank, etc.
4417  *
4418  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
4419  *  bank N is 4096 * N + flash_reg_addr.
4420  **/
4421 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
4422 {
4423         struct e1000_nvm_info *nvm = &hw->nvm;
4424         union ich8_hws_flash_status hsfsts;
4425         union ich8_hws_flash_ctrl hsflctl;
4426         u32 flash_linear_addr;
4427         /* bank size is in 16bit words - adjust to bytes */
4428         u32 flash_bank_size = nvm->flash_bank_size * 2;
4429         s32 ret_val;
4430         s32 count = 0;
4431         s32 j, iteration, sector_size;
4432
4433         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4434
4435         /* Determine HW Sector size: Read BERASE bits of hw flash status
4436          * register
4437          * 00: The Hw sector is 256 bytes, hence we need to erase 16
4438          *     consecutive sectors.  The start index for the nth Hw sector
4439          *     can be calculated as = bank * 4096 + n * 256
4440          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
4441          *     The start index for the nth Hw sector can be calculated
4442          *     as = bank * 4096
4443          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
4444          *     (ich9 only, otherwise error condition)
4445          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
4446          */
4447         switch (hsfsts.hsf_status.berasesz) {
4448         case 0:
4449                 /* Hw sector size 256 */
4450                 sector_size = ICH_FLASH_SEG_SIZE_256;
4451                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
4452                 break;
4453         case 1:
4454                 sector_size = ICH_FLASH_SEG_SIZE_4K;
4455                 iteration = 1;
4456                 break;
4457         case 2:
4458                 sector_size = ICH_FLASH_SEG_SIZE_8K;
4459                 iteration = 1;
4460                 break;
4461         case 3:
4462                 sector_size = ICH_FLASH_SEG_SIZE_64K;
4463                 iteration = 1;
4464                 break;
4465         default:
4466                 return -E1000_ERR_NVM;
4467         }
4468
4469         /* Start with the base address, then add the sector offset. */
4470         flash_linear_addr = hw->nvm.flash_base_addr;
4471         flash_linear_addr += (bank) ? flash_bank_size : 0;
4472
4473         for (j = 0; j < iteration; j++) {
4474                 do {
4475                         u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
4476
4477                         /* Steps */
4478                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
4479                         if (ret_val)
4480                                 return ret_val;
4481
4482                         /* Write a value 11 (block Erase) in Flash
4483                          * Cycle field in hw flash control
4484                          */
4485                         if (hw->mac.type >= e1000_pch_spt)
4486                                 hsflctl.regval =
4487                                     er32flash(ICH_FLASH_HSFSTS) >> 16;
4488                         else
4489                                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4490
4491                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
4492                         if (hw->mac.type >= e1000_pch_spt)
4493                                 ew32flash(ICH_FLASH_HSFSTS,
4494                                           hsflctl.regval << 16);
4495                         else
4496                                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4497
4498                         /* Write the last 24 bits of an index within the
4499                          * block into Flash Linear address field in Flash
4500                          * Address.
4501                          */
4502                         flash_linear_addr += (j * sector_size);
4503                         ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4504
4505                         ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
4506                         if (!ret_val)
4507                                 break;
4508
4509                         /* Check if FCERR is set to 1.  If 1,
4510                          * clear it and try the whole sequence
4511                          * a few more times else Done
4512                          */
4513                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4514                         if (hsfsts.hsf_status.flcerr)
4515                                 /* repeat for some time before giving up */
4516                                 continue;
4517                         else if (!hsfsts.hsf_status.flcdone)
4518                                 return ret_val;
4519                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
4520         }
4521
4522         return 0;
4523 }
4524
4525 /**
4526  *  e1000_valid_led_default_ich8lan - Set the default LED settings
4527  *  @hw: pointer to the HW structure
4528  *  @data: Pointer to the LED settings
4529  *
4530  *  Reads the LED default settings from the NVM to data.  If the NVM LED
4531  *  settings is all 0's or F's, set the LED default to a valid LED default
4532  *  setting.
4533  **/
4534 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
4535 {
4536         s32 ret_val;
4537
4538         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
4539         if (ret_val) {
4540                 e_dbg("NVM Read Error\n");
4541                 return ret_val;
4542         }
4543
4544         if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
4545                 *data = ID_LED_DEFAULT_ICH8LAN;
4546
4547         return 0;
4548 }
4549
4550 /**
4551  *  e1000_id_led_init_pchlan - store LED configurations
4552  *  @hw: pointer to the HW structure
4553  *
4554  *  PCH does not control LEDs via the LEDCTL register, rather it uses
4555  *  the PHY LED configuration register.
4556  *
4557  *  PCH also does not have an "always on" or "always off" mode which
4558  *  complicates the ID feature.  Instead of using the "on" mode to indicate
4559  *  in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()),
4560  *  use "link_up" mode.  The LEDs will still ID on request if there is no
4561  *  link based on logic in e1000_led_[on|off]_pchlan().
4562  **/
4563 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
4564 {
4565         struct e1000_mac_info *mac = &hw->mac;
4566         s32 ret_val;
4567         const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
4568         const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
4569         u16 data, i, temp, shift;
4570
4571         /* Get default ID LED modes */
4572         ret_val = hw->nvm.ops.valid_led_default(hw, &data);
4573         if (ret_val)
4574                 return ret_val;
4575
4576         mac->ledctl_default = er32(LEDCTL);
4577         mac->ledctl_mode1 = mac->ledctl_default;
4578         mac->ledctl_mode2 = mac->ledctl_default;
4579
4580         for (i = 0; i < 4; i++) {
4581                 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
4582                 shift = (i * 5);
4583                 switch (temp) {
4584                 case ID_LED_ON1_DEF2:
4585                 case ID_LED_ON1_ON2:
4586                 case ID_LED_ON1_OFF2:
4587                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4588                         mac->ledctl_mode1 |= (ledctl_on << shift);
4589                         break;
4590                 case ID_LED_OFF1_DEF2:
4591                 case ID_LED_OFF1_ON2:
4592                 case ID_LED_OFF1_OFF2:
4593                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4594                         mac->ledctl_mode1 |= (ledctl_off << shift);
4595                         break;
4596                 default:
4597                         /* Do nothing */
4598                         break;
4599                 }
4600                 switch (temp) {
4601                 case ID_LED_DEF1_ON2:
4602                 case ID_LED_ON1_ON2:
4603                 case ID_LED_OFF1_ON2:
4604                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4605                         mac->ledctl_mode2 |= (ledctl_on << shift);
4606                         break;
4607                 case ID_LED_DEF1_OFF2:
4608                 case ID_LED_ON1_OFF2:
4609                 case ID_LED_OFF1_OFF2:
4610                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4611                         mac->ledctl_mode2 |= (ledctl_off << shift);
4612                         break;
4613                 default:
4614                         /* Do nothing */
4615                         break;
4616                 }
4617         }
4618
4619         return 0;
4620 }
4621
4622 /**
4623  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
4624  *  @hw: pointer to the HW structure
4625  *
4626  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
4627  *  register, so the the bus width is hard coded.
4628  **/
4629 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
4630 {
4631         struct e1000_bus_info *bus = &hw->bus;
4632         s32 ret_val;
4633
4634         ret_val = e1000e_get_bus_info_pcie(hw);
4635
4636         /* ICH devices are "PCI Express"-ish.  They have
4637          * a configuration space, but do not contain
4638          * PCI Express Capability registers, so bus width
4639          * must be hardcoded.
4640          */
4641         if (bus->width == e1000_bus_width_unknown)
4642                 bus->width = e1000_bus_width_pcie_x1;
4643
4644         return ret_val;
4645 }
4646
4647 /**
4648  *  e1000_reset_hw_ich8lan - Reset the hardware
4649  *  @hw: pointer to the HW structure
4650  *
4651  *  Does a full reset of the hardware which includes a reset of the PHY and
4652  *  MAC.
4653  **/
4654 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
4655 {
4656         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4657         u16 kum_cfg;
4658         u32 ctrl, reg;
4659         s32 ret_val;
4660
4661         /* Prevent the PCI-E bus from sticking if there is no TLP connection
4662          * on the last TLP read/write transaction when MAC is reset.
4663          */
4664         ret_val = e1000e_disable_pcie_master(hw);
4665         if (ret_val)
4666                 e_dbg("PCI-E Master disable polling has failed.\n");
4667
4668         e_dbg("Masking off all interrupts\n");
4669         ew32(IMC, 0xffffffff);
4670
4671         /* Disable the Transmit and Receive units.  Then delay to allow
4672          * any pending transactions to complete before we hit the MAC
4673          * with the global reset.
4674          */
4675         ew32(RCTL, 0);
4676         ew32(TCTL, E1000_TCTL_PSP);
4677         e1e_flush();
4678
4679         usleep_range(10000, 11000);
4680
4681         /* Workaround for ICH8 bit corruption issue in FIFO memory */
4682         if (hw->mac.type == e1000_ich8lan) {
4683                 /* Set Tx and Rx buffer allocation to 8k apiece. */
4684                 ew32(PBA, E1000_PBA_8K);
4685                 /* Set Packet Buffer Size to 16k. */
4686                 ew32(PBS, E1000_PBS_16K);
4687         }
4688
4689         if (hw->mac.type == e1000_pchlan) {
4690                 /* Save the NVM K1 bit setting */
4691                 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
4692                 if (ret_val)
4693                         return ret_val;
4694
4695                 if (kum_cfg & E1000_NVM_K1_ENABLE)
4696                         dev_spec->nvm_k1_enabled = true;
4697                 else
4698                         dev_spec->nvm_k1_enabled = false;
4699         }
4700
4701         ctrl = er32(CTRL);
4702
4703         if (!hw->phy.ops.check_reset_block(hw)) {
4704                 /* Full-chip reset requires MAC and PHY reset at the same
4705                  * time to make sure the interface between MAC and the
4706                  * external PHY is reset.
4707                  */
4708                 ctrl |= E1000_CTRL_PHY_RST;
4709
4710                 /* Gate automatic PHY configuration by hardware on
4711                  * non-managed 82579
4712                  */
4713                 if ((hw->mac.type == e1000_pch2lan) &&
4714                     !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
4715                         e1000_gate_hw_phy_config_ich8lan(hw, true);
4716         }
4717         ret_val = e1000_acquire_swflag_ich8lan(hw);
4718         e_dbg("Issuing a global reset to ich8lan\n");
4719         ew32(CTRL, (ctrl | E1000_CTRL_RST));
4720         /* cannot issue a flush here because it hangs the hardware */
4721         msleep(20);
4722
4723         /* Set Phy Config Counter to 50msec */
4724         if (hw->mac.type == e1000_pch2lan) {
4725                 reg = er32(FEXTNVM3);
4726                 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
4727                 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
4728                 ew32(FEXTNVM3, reg);
4729         }
4730
4731         if (!ret_val)
4732                 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
4733
4734         if (ctrl & E1000_CTRL_PHY_RST) {
4735                 ret_val = hw->phy.ops.get_cfg_done(hw);
4736                 if (ret_val)
4737                         return ret_val;
4738
4739                 ret_val = e1000_post_phy_reset_ich8lan(hw);
4740                 if (ret_val)
4741                         return ret_val;
4742         }
4743
4744         /* For PCH, this write will make sure that any noise
4745          * will be detected as a CRC error and be dropped rather than show up
4746          * as a bad packet to the DMA engine.
4747          */
4748         if (hw->mac.type == e1000_pchlan)
4749                 ew32(CRC_OFFSET, 0x65656565);
4750
4751         ew32(IMC, 0xffffffff);
4752         er32(ICR);
4753
4754         reg = er32(KABGTXD);
4755         reg |= E1000_KABGTXD_BGSQLBIAS;
4756         ew32(KABGTXD, reg);
4757
4758         return 0;
4759 }
4760
4761 /**
4762  *  e1000_init_hw_ich8lan - Initialize the hardware
4763  *  @hw: pointer to the HW structure
4764  *
4765  *  Prepares the hardware for transmit and receive by doing the following:
4766  *   - initialize hardware bits
4767  *   - initialize LED identification
4768  *   - setup receive address registers
4769  *   - setup flow control
4770  *   - setup transmit descriptors
4771  *   - clear statistics
4772  **/
4773 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
4774 {
4775         struct e1000_mac_info *mac = &hw->mac;
4776         u32 ctrl_ext, txdctl, snoop;
4777         s32 ret_val;
4778         u16 i;
4779
4780         e1000_initialize_hw_bits_ich8lan(hw);
4781
4782         /* Initialize identification LED */
4783         ret_val = mac->ops.id_led_init(hw);
4784         /* An error is not fatal and we should not stop init due to this */
4785         if (ret_val)
4786                 e_dbg("Error initializing identification LED\n");
4787
4788         /* Setup the receive address. */
4789         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
4790
4791         /* Zero out the Multicast HASH table */
4792         e_dbg("Zeroing the MTA\n");
4793         for (i = 0; i < mac->mta_reg_count; i++)
4794                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
4795
4796         /* The 82578 Rx buffer will stall if wakeup is enabled in host and
4797          * the ME.  Disable wakeup by clearing the host wakeup bit.
4798          * Reset the phy after disabling host wakeup to reset the Rx buffer.
4799          */
4800         if (hw->phy.type == e1000_phy_82578) {
4801                 e1e_rphy(hw, BM_PORT_GEN_CFG, &i);
4802                 i &= ~BM_WUC_HOST_WU_BIT;
4803                 e1e_wphy(hw, BM_PORT_GEN_CFG, i);
4804                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
4805                 if (ret_val)
4806                         return ret_val;
4807         }
4808
4809         /* Setup link and flow control */
4810         ret_val = mac->ops.setup_link(hw);
4811
4812         /* Set the transmit descriptor write-back policy for both queues */
4813         txdctl = er32(TXDCTL(0));
4814         txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4815                   E1000_TXDCTL_FULL_TX_DESC_WB);
4816         txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4817                   E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4818         ew32(TXDCTL(0), txdctl);
4819         txdctl = er32(TXDCTL(1));
4820         txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4821                   E1000_TXDCTL_FULL_TX_DESC_WB);
4822         txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4823                   E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4824         ew32(TXDCTL(1), txdctl);
4825
4826         /* ICH8 has opposite polarity of no_snoop bits.
4827          * By default, we should use snoop behavior.
4828          */
4829         if (mac->type == e1000_ich8lan)
4830                 snoop = PCIE_ICH8_SNOOP_ALL;
4831         else
4832                 snoop = (u32)~(PCIE_NO_SNOOP_ALL);
4833         e1000e_set_pcie_no_snoop(hw, snoop);
4834
4835         ctrl_ext = er32(CTRL_EXT);
4836         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
4837         ew32(CTRL_EXT, ctrl_ext);
4838
4839         /* Clear all of the statistics registers (clear on read).  It is
4840          * important that we do this after we have tried to establish link
4841          * because the symbol error count will increment wildly if there
4842          * is no link.
4843          */
4844         e1000_clear_hw_cntrs_ich8lan(hw);
4845
4846         return ret_val;
4847 }
4848
4849 /**
4850  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
4851  *  @hw: pointer to the HW structure
4852  *
4853  *  Sets/Clears required hardware bits necessary for correctly setting up the
4854  *  hardware for transmit and receive.
4855  **/
4856 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
4857 {
4858         u32 reg;
4859
4860         /* Extended Device Control */
4861         reg = er32(CTRL_EXT);
4862         reg |= BIT(22);
4863         /* Enable PHY low-power state when MAC is at D3 w/o WoL */
4864         if (hw->mac.type >= e1000_pchlan)
4865                 reg |= E1000_CTRL_EXT_PHYPDEN;
4866         ew32(CTRL_EXT, reg);
4867
4868         /* Transmit Descriptor Control 0 */
4869         reg = er32(TXDCTL(0));
4870         reg |= BIT(22);
4871         ew32(TXDCTL(0), reg);
4872
4873         /* Transmit Descriptor Control 1 */
4874         reg = er32(TXDCTL(1));
4875         reg |= BIT(22);
4876         ew32(TXDCTL(1), reg);
4877
4878         /* Transmit Arbitration Control 0 */
4879         reg = er32(TARC(0));
4880         if (hw->mac.type == e1000_ich8lan)
4881                 reg |= BIT(28) | BIT(29);
4882         reg |= BIT(23) | BIT(24) | BIT(26) | BIT(27);
4883         ew32(TARC(0), reg);
4884
4885         /* Transmit Arbitration Control 1 */
4886         reg = er32(TARC(1));
4887         if (er32(TCTL) & E1000_TCTL_MULR)
4888                 reg &= ~BIT(28);
4889         else
4890                 reg |= BIT(28);
4891         reg |= BIT(24) | BIT(26) | BIT(30);
4892         ew32(TARC(1), reg);
4893
4894         /* Device Status */
4895         if (hw->mac.type == e1000_ich8lan) {
4896                 reg = er32(STATUS);
4897                 reg &= ~BIT(31);
4898                 ew32(STATUS, reg);
4899         }
4900
4901         /* work-around descriptor data corruption issue during nfs v2 udp
4902          * traffic, just disable the nfs filtering capability
4903          */
4904         reg = er32(RFCTL);
4905         reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
4906
4907         /* Disable IPv6 extension header parsing because some malformed
4908          * IPv6 headers can hang the Rx.
4909          */
4910         if (hw->mac.type == e1000_ich8lan)
4911                 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
4912         ew32(RFCTL, reg);
4913
4914         /* Enable ECC on Lynxpoint */
4915         if (hw->mac.type >= e1000_pch_lpt) {
4916                 reg = er32(PBECCSTS);
4917                 reg |= E1000_PBECCSTS_ECC_ENABLE;
4918                 ew32(PBECCSTS, reg);
4919
4920                 reg = er32(CTRL);
4921                 reg |= E1000_CTRL_MEHE;
4922                 ew32(CTRL, reg);
4923         }
4924 }
4925
4926 /**
4927  *  e1000_setup_link_ich8lan - Setup flow control and link settings
4928  *  @hw: pointer to the HW structure
4929  *
4930  *  Determines which flow control settings to use, then configures flow
4931  *  control.  Calls the appropriate media-specific link configuration
4932  *  function.  Assuming the adapter has a valid link partner, a valid link
4933  *  should be established.  Assumes the hardware has previously been reset
4934  *  and the transmitter and receiver are not enabled.
4935  **/
4936 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
4937 {
4938         s32 ret_val;
4939
4940         if (hw->phy.ops.check_reset_block(hw))
4941                 return 0;
4942
4943         /* ICH parts do not have a word in the NVM to determine
4944          * the default flow control setting, so we explicitly
4945          * set it to full.
4946          */
4947         if (hw->fc.requested_mode == e1000_fc_default) {
4948                 /* Workaround h/w hang when Tx flow control enabled */
4949                 if (hw->mac.type == e1000_pchlan)
4950                         hw->fc.requested_mode = e1000_fc_rx_pause;
4951                 else
4952                         hw->fc.requested_mode = e1000_fc_full;
4953         }
4954
4955         /* Save off the requested flow control mode for use later.  Depending
4956          * on the link partner's capabilities, we may or may not use this mode.
4957          */
4958         hw->fc.current_mode = hw->fc.requested_mode;
4959
4960         e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);
4961
4962         /* Continue to configure the copper link. */
4963         ret_val = hw->mac.ops.setup_physical_interface(hw);
4964         if (ret_val)
4965                 return ret_val;
4966
4967         ew32(FCTTV, hw->fc.pause_time);
4968         if ((hw->phy.type == e1000_phy_82578) ||
4969             (hw->phy.type == e1000_phy_82579) ||
4970             (hw->phy.type == e1000_phy_i217) ||
4971             (hw->phy.type == e1000_phy_82577)) {
4972                 ew32(FCRTV_PCH, hw->fc.refresh_time);
4973
4974                 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
4975                                    hw->fc.pause_time);
4976                 if (ret_val)
4977                         return ret_val;
4978         }
4979
4980         return e1000e_set_fc_watermarks(hw);
4981 }
4982
4983 /**
4984  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
4985  *  @hw: pointer to the HW structure
4986  *
4987  *  Configures the kumeran interface to the PHY to wait the appropriate time
4988  *  when polling the PHY, then call the generic setup_copper_link to finish
4989  *  configuring the copper link.
4990  **/
4991 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
4992 {
4993         u32 ctrl;
4994         s32 ret_val;
4995         u16 reg_data;
4996
4997         ctrl = er32(CTRL);
4998         ctrl |= E1000_CTRL_SLU;
4999         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5000         ew32(CTRL, ctrl);
5001
5002         /* Set the mac to wait the maximum time between each iteration
5003          * and increase the max iterations when polling the phy;
5004          * this fixes erroneous timeouts at 10Mbps.
5005          */
5006         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
5007         if (ret_val)
5008                 return ret_val;
5009         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
5010                                        &reg_data);
5011         if (ret_val)
5012                 return ret_val;
5013         reg_data |= 0x3F;
5014         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
5015                                         reg_data);
5016         if (ret_val)
5017                 return ret_val;
5018
5019         switch (hw->phy.type) {
5020         case e1000_phy_igp_3:
5021                 ret_val = e1000e_copper_link_setup_igp(hw);
5022                 if (ret_val)
5023                         return ret_val;
5024                 break;
5025         case e1000_phy_bm:
5026         case e1000_phy_82578:
5027                 ret_val = e1000e_copper_link_setup_m88(hw);
5028                 if (ret_val)
5029                         return ret_val;
5030                 break;
5031         case e1000_phy_82577:
5032         case e1000_phy_82579:
5033                 ret_val = e1000_copper_link_setup_82577(hw);
5034                 if (ret_val)
5035                         return ret_val;
5036                 break;
5037         case e1000_phy_ife:
5038                 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
5039                 if (ret_val)
5040                         return ret_val;
5041
5042                 reg_data &= ~IFE_PMC_AUTO_MDIX;
5043
5044                 switch (hw->phy.mdix) {
5045                 case 1:
5046                         reg_data &= ~IFE_PMC_FORCE_MDIX;
5047                         break;
5048                 case 2:
5049                         reg_data |= IFE_PMC_FORCE_MDIX;
5050                         break;
5051                 case 0:
5052                 default:
5053                         reg_data |= IFE_PMC_AUTO_MDIX;
5054                         break;
5055                 }
5056                 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
5057                 if (ret_val)
5058                         return ret_val;
5059                 break;
5060         default:
5061                 break;
5062         }
5063
5064         return e1000e_setup_copper_link(hw);
5065 }
5066
5067 /**
5068  *  e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
5069  *  @hw: pointer to the HW structure
5070  *
5071  *  Calls the PHY specific link setup function and then calls the
5072  *  generic setup_copper_link to finish configuring the link for
5073  *  Lynxpoint PCH devices
5074  **/
5075 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
5076 {
5077         u32 ctrl;
5078         s32 ret_val;
5079
5080         ctrl = er32(CTRL);
5081         ctrl |= E1000_CTRL_SLU;
5082         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5083         ew32(CTRL, ctrl);
5084
5085         ret_val = e1000_copper_link_setup_82577(hw);
5086         if (ret_val)
5087                 return ret_val;
5088
5089         return e1000e_setup_copper_link(hw);
5090 }
5091
5092 /**
5093  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
5094  *  @hw: pointer to the HW structure
5095  *  @speed: pointer to store current link speed
5096  *  @duplex: pointer to store the current link duplex
5097  *
5098  *  Calls the generic get_speed_and_duplex to retrieve the current link
5099  *  information and then calls the Kumeran lock loss workaround for links at
5100  *  gigabit speeds.
5101  **/
5102 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
5103                                           u16 *duplex)
5104 {
5105         s32 ret_val;
5106
5107         ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
5108         if (ret_val)
5109                 return ret_val;
5110
5111         if ((hw->mac.type == e1000_ich8lan) &&
5112             (hw->phy.type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
5113                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
5114         }
5115
5116         return ret_val;
5117 }
5118
5119 /**
5120  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
5121  *  @hw: pointer to the HW structure
5122  *
5123  *  Work-around for 82566 Kumeran PCS lock loss:
5124  *  On link status change (i.e. PCI reset, speed change) and link is up and
5125  *  speed is gigabit-
5126  *    0) if workaround is optionally disabled do nothing
5127  *    1) wait 1ms for Kumeran link to come up
5128  *    2) check Kumeran Diagnostic register PCS lock loss bit
5129  *    3) if not set the link is locked (all is good), otherwise...
5130  *    4) reset the PHY
5131  *    5) repeat up to 10 times
5132  *  Note: this is only called for IGP3 copper when speed is 1gb.
5133  **/
5134 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
5135 {
5136         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5137         u32 phy_ctrl;
5138         s32 ret_val;
5139         u16 i, data;
5140         bool link;
5141
5142         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
5143                 return 0;
5144
5145         /* Make sure link is up before proceeding.  If not just return.
5146          * Attempting this while link is negotiating fouled up link
5147          * stability
5148          */
5149         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
5150         if (!link)
5151                 return 0;
5152
5153         for (i = 0; i < 10; i++) {
5154                 /* read once to clear */
5155                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
5156                 if (ret_val)
5157                         return ret_val;
5158                 /* and again to get new status */
5159                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
5160                 if (ret_val)
5161                         return ret_val;
5162
5163                 /* check for PCS lock */
5164                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
5165                         return 0;
5166
5167                 /* Issue PHY reset */
5168                 e1000_phy_hw_reset(hw);
5169                 mdelay(5);
5170         }
5171         /* Disable GigE link negotiation */
5172         phy_ctrl = er32(PHY_CTRL);
5173         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
5174                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5175         ew32(PHY_CTRL, phy_ctrl);
5176
5177         /* Call gig speed drop workaround on Gig disable before accessing
5178          * any PHY registers
5179          */
5180         e1000e_gig_downshift_workaround_ich8lan(hw);
5181
5182         /* unable to acquire PCS lock */
5183         return -E1000_ERR_PHY;
5184 }
5185
5186 /**
5187  *  e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
5188  *  @hw: pointer to the HW structure
5189  *  @state: boolean value used to set the current Kumeran workaround state
5190  *
5191  *  If ICH8, set the current Kumeran workaround state (enabled - true
5192  *  /disabled - false).
5193  **/
5194 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
5195                                                   bool state)
5196 {
5197         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5198
5199         if (hw->mac.type != e1000_ich8lan) {
5200                 e_dbg("Workaround applies to ICH8 only.\n");
5201                 return;
5202         }
5203
5204         dev_spec->kmrn_lock_loss_workaround_enabled = state;
5205 }
5206
5207 /**
5208  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
5209  *  @hw: pointer to the HW structure
5210  *
5211  *  Workaround for 82566 power-down on D3 entry:
5212  *    1) disable gigabit link
5213  *    2) write VR power-down enable
5214  *    3) read it back
5215  *  Continue if successful, else issue LCD reset and repeat
5216  **/
5217 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
5218 {
5219         u32 reg;
5220         u16 data;
5221         u8 retry = 0;
5222
5223         if (hw->phy.type != e1000_phy_igp_3)
5224                 return;
5225
5226         /* Try the workaround twice (if needed) */
5227         do {
5228                 /* Disable link */
5229                 reg = er32(PHY_CTRL);
5230                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
5231                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5232                 ew32(PHY_CTRL, reg);
5233
5234                 /* Call gig speed drop workaround on Gig disable before
5235                  * accessing any PHY registers
5236                  */
5237                 if (hw->mac.type == e1000_ich8lan)
5238                         e1000e_gig_downshift_workaround_ich8lan(hw);
5239
5240                 /* Write VR power-down enable */
5241                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
5242                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5243                 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
5244
5245                 /* Read it back and test */
5246                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
5247                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5248                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
5249                         break;
5250
5251                 /* Issue PHY reset and repeat at most one more time */
5252                 reg = er32(CTRL);
5253                 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
5254                 retry++;
5255         } while (retry);
5256 }
5257
5258 /**
5259  *  e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
5260  *  @hw: pointer to the HW structure
5261  *
5262  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
5263  *  LPLU, Gig disable, MDIC PHY reset):
5264  *    1) Set Kumeran Near-end loopback
5265  *    2) Clear Kumeran Near-end loopback
5266  *  Should only be called for ICH8[m] devices with any 1G Phy.
5267  **/
5268 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
5269 {
5270         s32 ret_val;
5271         u16 reg_data;
5272
5273         if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife))
5274                 return;
5275
5276         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5277                                        &reg_data);
5278         if (ret_val)
5279                 return;
5280         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
5281         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5282                                         reg_data);
5283         if (ret_val)
5284                 return;
5285         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
5286         e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, reg_data);
5287 }
5288
5289 /**
5290  *  e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
5291  *  @hw: pointer to the HW structure
5292  *
5293  *  During S0 to Sx transition, it is possible the link remains at gig
5294  *  instead of negotiating to a lower speed.  Before going to Sx, set
5295  *  'Gig Disable' to force link speed negotiation to a lower speed based on
5296  *  the LPLU setting in the NVM or custom setting.  For PCH and newer parts,
5297  *  the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
5298  *  needs to be written.
5299  *  Parts that support (and are linked to a partner which support) EEE in
5300  *  100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
5301  *  than 10Mbps w/o EEE.
5302  **/
5303 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
5304 {
5305         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5306         u32 phy_ctrl;
5307         s32 ret_val;
5308
5309         phy_ctrl = er32(PHY_CTRL);
5310         phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
5311
5312         if (hw->phy.type == e1000_phy_i217) {
5313                 u16 phy_reg, device_id = hw->adapter->pdev->device;
5314
5315                 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
5316                     (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
5317                     (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
5318                     (device_id == E1000_DEV_ID_PCH_I218_V3) ||
5319                     (hw->mac.type >= e1000_pch_spt)) {
5320                         u32 fextnvm6 = er32(FEXTNVM6);
5321
5322                         ew32(FEXTNVM6, fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
5323                 }
5324
5325                 ret_val = hw->phy.ops.acquire(hw);
5326                 if (ret_val)
5327                         goto out;
5328
5329                 if (!dev_spec->eee_disable) {
5330                         u16 eee_advert;
5331
5332                         ret_val =
5333                             e1000_read_emi_reg_locked(hw,
5334                                                       I217_EEE_ADVERTISEMENT,
5335                                                       &eee_advert);
5336                         if (ret_val)
5337                                 goto release;
5338
5339                         /* Disable LPLU if both link partners support 100BaseT
5340                          * EEE and 100Full is advertised on both ends of the
5341                          * link, and enable Auto Enable LPI since there will
5342                          * be no driver to enable LPI while in Sx.
5343                          */
5344                         if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
5345                             (dev_spec->eee_lp_ability &
5346                              I82579_EEE_100_SUPPORTED) &&
5347                             (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {
5348                                 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
5349                                               E1000_PHY_CTRL_NOND0A_LPLU);
5350
5351                                 /* Set Auto Enable LPI after link up */
5352                                 e1e_rphy_locked(hw,
5353                                                 I217_LPI_GPIO_CTRL, &phy_reg);
5354                                 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5355                                 e1e_wphy_locked(hw,
5356                                                 I217_LPI_GPIO_CTRL, phy_reg);
5357                         }
5358                 }
5359
5360                 /* For i217 Intel Rapid Start Technology support,
5361                  * when the system is going into Sx and no manageability engine
5362                  * is present, the driver must configure proxy to reset only on
5363                  * power good.  LPI (Low Power Idle) state must also reset only
5364                  * on power good, as well as the MTA (Multicast table array).
5365                  * The SMBus release must also be disabled on LCD reset.
5366                  */
5367                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
5368                         /* Enable proxy to reset only on power good. */
5369                         e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg);
5370                         phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
5371                         e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg);
5372
5373                         /* Set bit enable LPI (EEE) to reset only on
5374                          * power good.
5375                          */
5376                         e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg);
5377                         phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
5378                         e1e_wphy_locked(hw, I217_SxCTRL, phy_reg);
5379
5380                         /* Disable the SMB release on LCD reset. */
5381                         e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
5382                         phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
5383                         e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
5384                 }
5385
5386                 /* Enable MTA to reset for Intel Rapid Start Technology
5387                  * Support
5388                  */
5389                 e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
5390                 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
5391                 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
5392
5393 release:
5394                 hw->phy.ops.release(hw);
5395         }
5396 out:
5397         ew32(PHY_CTRL, phy_ctrl);
5398
5399         if (hw->mac.type == e1000_ich8lan)
5400                 e1000e_gig_downshift_workaround_ich8lan(hw);
5401
5402         if (hw->mac.type >= e1000_pchlan) {
5403                 e1000_oem_bits_config_ich8lan(hw, false);
5404
5405                 /* Reset PHY to activate OEM bits on 82577/8 */
5406                 if (hw->mac.type == e1000_pchlan)
5407                         e1000e_phy_hw_reset_generic(hw);
5408
5409                 ret_val = hw->phy.ops.acquire(hw);
5410                 if (ret_val)
5411                         return;
5412                 e1000_write_smbus_addr(hw);
5413                 hw->phy.ops.release(hw);
5414         }
5415 }
5416
5417 /**
5418  *  e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
5419  *  @hw: pointer to the HW structure
5420  *
5421  *  During Sx to S0 transitions on non-managed devices or managed devices
5422  *  on which PHY resets are not blocked, if the PHY registers cannot be
5423  *  accessed properly by the s/w toggle the LANPHYPC value to power cycle
5424  *  the PHY.
5425  *  On i217, setup Intel Rapid Start Technology.
5426  **/
5427 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
5428 {
5429         s32 ret_val;
5430
5431         if (hw->mac.type < e1000_pch2lan)
5432                 return;
5433
5434         ret_val = e1000_init_phy_workarounds_pchlan(hw);
5435         if (ret_val) {
5436                 e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val);
5437                 return;
5438         }
5439
5440         /* For i217 Intel Rapid Start Technology support when the system
5441          * is transitioning from Sx and no manageability engine is present
5442          * configure SMBus to restore on reset, disable proxy, and enable
5443          * the reset on MTA (Multicast table array).
5444          */
5445         if (hw->phy.type == e1000_phy_i217) {
5446                 u16 phy_reg;
5447
5448                 ret_val = hw->phy.ops.acquire(hw);
5449                 if (ret_val) {
5450                         e_dbg("Failed to setup iRST\n");
5451                         return;
5452                 }
5453
5454                 /* Clear Auto Enable LPI after link up */
5455                 e1e_rphy_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
5456                 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5457                 e1e_wphy_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
5458
5459                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
5460                         /* Restore clear on SMB if no manageability engine
5461                          * is present
5462                          */
5463                         ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
5464                         if (ret_val)
5465                                 goto release;
5466                         phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
5467                         e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
5468
5469                         /* Disable Proxy */
5470                         e1e_wphy_locked(hw, I217_PROXY_CTRL, 0);
5471                 }
5472                 /* Enable reset on MTA */
5473                 ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
5474                 if (ret_val)
5475                         goto release;
5476                 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
5477                 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
5478 release:
5479                 if (ret_val)
5480                         e_dbg("Error %d in resume workarounds\n", ret_val);
5481                 hw->phy.ops.release(hw);
5482         }
5483 }
5484
5485 /**
5486  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
5487  *  @hw: pointer to the HW structure
5488  *
5489  *  Return the LED back to the default configuration.
5490  **/
5491 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
5492 {
5493         if (hw->phy.type == e1000_phy_ife)
5494                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
5495
5496         ew32(LEDCTL, hw->mac.ledctl_default);
5497         return 0;
5498 }
5499
5500 /**
5501  *  e1000_led_on_ich8lan - Turn LEDs on
5502  *  @hw: pointer to the HW structure
5503  *
5504  *  Turn on the LEDs.
5505  **/
5506 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
5507 {
5508         if (hw->phy.type == e1000_phy_ife)
5509                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5510                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
5511
5512         ew32(LEDCTL, hw->mac.ledctl_mode2);
5513         return 0;
5514 }
5515
5516 /**
5517  *  e1000_led_off_ich8lan - Turn LEDs off
5518  *  @hw: pointer to the HW structure
5519  *
5520  *  Turn off the LEDs.
5521  **/
5522 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
5523 {
5524         if (hw->phy.type == e1000_phy_ife)
5525                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5526                                 (IFE_PSCL_PROBE_MODE |
5527                                  IFE_PSCL_PROBE_LEDS_OFF));
5528
5529         ew32(LEDCTL, hw->mac.ledctl_mode1);
5530         return 0;
5531 }
5532
5533 /**
5534  *  e1000_setup_led_pchlan - Configures SW controllable LED
5535  *  @hw: pointer to the HW structure
5536  *
5537  *  This prepares the SW controllable LED for use.
5538  **/
5539 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
5540 {
5541         return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);
5542 }
5543
5544 /**
5545  *  e1000_cleanup_led_pchlan - Restore the default LED operation
5546  *  @hw: pointer to the HW structure
5547  *
5548  *  Return the LED back to the default configuration.
5549  **/
5550 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
5551 {
5552         return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);
5553 }
5554
5555 /**
5556  *  e1000_led_on_pchlan - Turn LEDs on
5557  *  @hw: pointer to the HW structure
5558  *
5559  *  Turn on the LEDs.
5560  **/
5561 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
5562 {
5563         u16 data = (u16)hw->mac.ledctl_mode2;
5564         u32 i, led;
5565
5566         /* If no link, then turn LED on by setting the invert bit
5567          * for each LED that's mode is "link_up" in ledctl_mode2.
5568          */
5569         if (!(er32(STATUS) & E1000_STATUS_LU)) {
5570                 for (i = 0; i < 3; i++) {
5571                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5572                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
5573                             E1000_LEDCTL_MODE_LINK_UP)
5574                                 continue;
5575                         if (led & E1000_PHY_LED0_IVRT)
5576                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5577                         else
5578                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5579                 }
5580         }
5581
5582         return e1e_wphy(hw, HV_LED_CONFIG, data);
5583 }
5584
5585 /**
5586  *  e1000_led_off_pchlan - Turn LEDs off
5587  *  @hw: pointer to the HW structure
5588  *
5589  *  Turn off the LEDs.
5590  **/
5591 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
5592 {
5593         u16 data = (u16)hw->mac.ledctl_mode1;
5594         u32 i, led;
5595
5596         /* If no link, then turn LED off by clearing the invert bit
5597          * for each LED that's mode is "link_up" in ledctl_mode1.
5598          */
5599         if (!(er32(STATUS) & E1000_STATUS_LU)) {
5600                 for (i = 0; i < 3; i++) {
5601                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5602                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
5603                             E1000_LEDCTL_MODE_LINK_UP)
5604                                 continue;
5605                         if (led & E1000_PHY_LED0_IVRT)
5606                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5607                         else
5608                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5609                 }
5610         }
5611
5612         return e1e_wphy(hw, HV_LED_CONFIG, data);
5613 }
5614
5615 /**
5616  *  e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
5617  *  @hw: pointer to the HW structure
5618  *
5619  *  Read appropriate register for the config done bit for completion status
5620  *  and configure the PHY through s/w for EEPROM-less parts.
5621  *
5622  *  NOTE: some silicon which is EEPROM-less will fail trying to read the
5623  *  config done bit, so only an error is logged and continues.  If we were
5624  *  to return with error, EEPROM-less silicon would not be able to be reset
5625  *  or change link.
5626  **/
5627 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
5628 {
5629         s32 ret_val = 0;
5630         u32 bank = 0;
5631         u32 status;
5632
5633         e1000e_get_cfg_done_generic(hw);
5634
5635         /* Wait for indication from h/w that it has completed basic config */
5636         if (hw->mac.type >= e1000_ich10lan) {
5637                 e1000_lan_init_done_ich8lan(hw);
5638         } else {
5639                 ret_val = e1000e_get_auto_rd_done(hw);
5640                 if (ret_val) {
5641                         /* When auto config read does not complete, do not
5642                          * return with an error. This can happen in situations
5643                          * where there is no eeprom and prevents getting link.
5644                          */
5645                         e_dbg("Auto Read Done did not complete\n");
5646                         ret_val = 0;
5647                 }
5648         }
5649
5650         /* Clear PHY Reset Asserted bit */
5651         status = er32(STATUS);
5652         if (status & E1000_STATUS_PHYRA)
5653                 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
5654         else
5655                 e_dbg("PHY Reset Asserted not set - needs delay\n");
5656
5657         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
5658         if (hw->mac.type <= e1000_ich9lan) {
5659                 if (!(er32(EECD) & E1000_EECD_PRES) &&
5660                     (hw->phy.type == e1000_phy_igp_3)) {
5661                         e1000e_phy_init_script_igp3(hw);
5662                 }
5663         } else {
5664                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
5665                         /* Maybe we should do a basic PHY config */
5666                         e_dbg("EEPROM not present\n");
5667                         ret_val = -E1000_ERR_CONFIG;
5668                 }
5669         }
5670
5671         return ret_val;
5672 }
5673
5674 /**
5675  * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
5676  * @hw: pointer to the HW structure
5677  *
5678  * In the case of a PHY power down to save power, or to turn off link during a
5679  * driver unload, or wake on lan is not enabled, remove the link.
5680  **/
5681 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
5682 {
5683         /* If the management interface is not enabled, then power down */
5684         if (!(hw->mac.ops.check_mng_mode(hw) ||
5685               hw->phy.ops.check_reset_block(hw)))
5686                 e1000_power_down_phy_copper(hw);
5687 }
5688
5689 /**
5690  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
5691  *  @hw: pointer to the HW structure
5692  *
5693  *  Clears hardware counters specific to the silicon family and calls
5694  *  clear_hw_cntrs_generic to clear all general purpose counters.
5695  **/
5696 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
5697 {
5698         u16 phy_data;
5699         s32 ret_val;
5700
5701         e1000e_clear_hw_cntrs_base(hw);
5702
5703         er32(ALGNERRC);
5704         er32(RXERRC);
5705         er32(TNCRS);
5706         er32(CEXTERR);
5707         er32(TSCTC);
5708         er32(TSCTFC);
5709
5710         er32(MGTPRC);
5711         er32(MGTPDC);
5712         er32(MGTPTC);
5713
5714         er32(IAC);
5715         er32(ICRXOC);
5716
5717         /* Clear PHY statistics registers */
5718         if ((hw->phy.type == e1000_phy_82578) ||
5719             (hw->phy.type == e1000_phy_82579) ||
5720             (hw->phy.type == e1000_phy_i217) ||
5721             (hw->phy.type == e1000_phy_82577)) {
5722                 ret_val = hw->phy.ops.acquire(hw);
5723                 if (ret_val)
5724                         return;
5725                 ret_val = hw->phy.ops.set_page(hw,
5726                                                HV_STATS_PAGE << IGP_PAGE_SHIFT);
5727                 if (ret_val)
5728                         goto release;
5729                 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
5730                 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
5731                 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
5732                 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
5733                 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
5734                 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
5735                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
5736                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
5737                 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
5738                 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
5739                 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
5740                 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
5741                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
5742                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
5743 release:
5744                 hw->phy.ops.release(hw);
5745         }
5746 }
5747
5748 static const struct e1000_mac_operations ich8_mac_ops = {
5749         /* check_mng_mode dependent on mac type */
5750         .check_for_link         = e1000_check_for_copper_link_ich8lan,
5751         /* cleanup_led dependent on mac type */
5752         .clear_hw_cntrs         = e1000_clear_hw_cntrs_ich8lan,
5753         .get_bus_info           = e1000_get_bus_info_ich8lan,
5754         .set_lan_id             = e1000_set_lan_id_single_port,
5755         .get_link_up_info       = e1000_get_link_up_info_ich8lan,
5756         /* led_on dependent on mac type */
5757         /* led_off dependent on mac type */
5758         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
5759         .reset_hw               = e1000_reset_hw_ich8lan,
5760         .init_hw                = e1000_init_hw_ich8lan,
5761         .setup_link             = e1000_setup_link_ich8lan,
5762         .setup_physical_interface = e1000_setup_copper_link_ich8lan,
5763         /* id_led_init dependent on mac type */
5764         .config_collision_dist  = e1000e_config_collision_dist_generic,
5765         .rar_set                = e1000e_rar_set_generic,
5766         .rar_get_count          = e1000e_rar_get_count_generic,
5767 };
5768
5769 static const struct e1000_phy_operations ich8_phy_ops = {
5770         .acquire                = e1000_acquire_swflag_ich8lan,
5771         .check_reset_block      = e1000_check_reset_block_ich8lan,
5772         .commit                 = NULL,
5773         .get_cfg_done           = e1000_get_cfg_done_ich8lan,
5774         .get_cable_length       = e1000e_get_cable_length_igp_2,
5775         .read_reg               = e1000e_read_phy_reg_igp,
5776         .release                = e1000_release_swflag_ich8lan,
5777         .reset                  = e1000_phy_hw_reset_ich8lan,
5778         .set_d0_lplu_state      = e1000_set_d0_lplu_state_ich8lan,
5779         .set_d3_lplu_state      = e1000_set_d3_lplu_state_ich8lan,
5780         .write_reg              = e1000e_write_phy_reg_igp,
5781 };
5782
5783 static const struct e1000_nvm_operations ich8_nvm_ops = {
5784         .acquire                = e1000_acquire_nvm_ich8lan,
5785         .read                   = e1000_read_nvm_ich8lan,
5786         .release                = e1000_release_nvm_ich8lan,
5787         .reload                 = e1000e_reload_nvm_generic,
5788         .update                 = e1000_update_nvm_checksum_ich8lan,
5789         .valid_led_default      = e1000_valid_led_default_ich8lan,
5790         .validate               = e1000_validate_nvm_checksum_ich8lan,
5791         .write                  = e1000_write_nvm_ich8lan,
5792 };
5793
5794 static const struct e1000_nvm_operations spt_nvm_ops = {
5795         .acquire                = e1000_acquire_nvm_ich8lan,
5796         .release                = e1000_release_nvm_ich8lan,
5797         .read                   = e1000_read_nvm_spt,
5798         .update                 = e1000_update_nvm_checksum_spt,
5799         .reload                 = e1000e_reload_nvm_generic,
5800         .valid_led_default      = e1000_valid_led_default_ich8lan,
5801         .validate               = e1000_validate_nvm_checksum_ich8lan,
5802         .write                  = e1000_write_nvm_ich8lan,
5803 };
5804
5805 const struct e1000_info e1000_ich8_info = {
5806         .mac                    = e1000_ich8lan,
5807         .flags                  = FLAG_HAS_WOL
5808                                   | FLAG_IS_ICH
5809                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5810                                   | FLAG_HAS_AMT
5811                                   | FLAG_HAS_FLASH
5812                                   | FLAG_APME_IN_WUC,
5813         .pba                    = 8,
5814         .max_hw_frame_size      = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN,
5815         .get_variants           = e1000_get_variants_ich8lan,
5816         .mac_ops                = &ich8_mac_ops,
5817         .phy_ops                = &ich8_phy_ops,
5818         .nvm_ops                = &ich8_nvm_ops,
5819 };
5820
5821 const struct e1000_info e1000_ich9_info = {
5822         .mac                    = e1000_ich9lan,
5823         .flags                  = FLAG_HAS_JUMBO_FRAMES
5824                                   | FLAG_IS_ICH
5825                                   | FLAG_HAS_WOL
5826                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5827                                   | FLAG_HAS_AMT
5828                                   | FLAG_HAS_FLASH
5829                                   | FLAG_APME_IN_WUC,
5830         .pba                    = 18,
5831         .max_hw_frame_size      = DEFAULT_JUMBO,
5832         .get_variants           = e1000_get_variants_ich8lan,
5833         .mac_ops                = &ich8_mac_ops,
5834         .phy_ops                = &ich8_phy_ops,
5835         .nvm_ops                = &ich8_nvm_ops,
5836 };
5837
5838 const struct e1000_info e1000_ich10_info = {
5839         .mac                    = e1000_ich10lan,
5840         .flags                  = FLAG_HAS_JUMBO_FRAMES
5841                                   | FLAG_IS_ICH
5842                                   | FLAG_HAS_WOL
5843                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5844                                   | FLAG_HAS_AMT
5845                                   | FLAG_HAS_FLASH
5846                                   | FLAG_APME_IN_WUC,
5847         .pba                    = 18,
5848         .max_hw_frame_size      = DEFAULT_JUMBO,
5849         .get_variants           = e1000_get_variants_ich8lan,
5850         .mac_ops                = &ich8_mac_ops,
5851         .phy_ops                = &ich8_phy_ops,
5852         .nvm_ops                = &ich8_nvm_ops,
5853 };
5854
5855 const struct e1000_info e1000_pch_info = {
5856         .mac                    = e1000_pchlan,
5857         .flags                  = FLAG_IS_ICH
5858                                   | FLAG_HAS_WOL
5859                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5860                                   | FLAG_HAS_AMT
5861                                   | FLAG_HAS_FLASH
5862                                   | FLAG_HAS_JUMBO_FRAMES
5863                                   | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
5864                                   | FLAG_APME_IN_WUC,
5865         .flags2                 = FLAG2_HAS_PHY_STATS,
5866         .pba                    = 26,
5867         .max_hw_frame_size      = 4096,
5868         .get_variants           = e1000_get_variants_ich8lan,
5869         .mac_ops                = &ich8_mac_ops,
5870         .phy_ops                = &ich8_phy_ops,
5871         .nvm_ops                = &ich8_nvm_ops,
5872 };
5873
5874 const struct e1000_info e1000_pch2_info = {
5875         .mac                    = e1000_pch2lan,
5876         .flags                  = FLAG_IS_ICH
5877                                   | FLAG_HAS_WOL
5878                                   | FLAG_HAS_HW_TIMESTAMP
5879                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5880                                   | FLAG_HAS_AMT
5881                                   | FLAG_HAS_FLASH
5882                                   | FLAG_HAS_JUMBO_FRAMES
5883                                   | FLAG_APME_IN_WUC,
5884         .flags2                 = FLAG2_HAS_PHY_STATS
5885                                   | FLAG2_HAS_EEE
5886                                   | FLAG2_CHECK_SYSTIM_OVERFLOW,
5887         .pba                    = 26,
5888         .max_hw_frame_size      = 9022,
5889         .get_variants           = e1000_get_variants_ich8lan,
5890         .mac_ops                = &ich8_mac_ops,
5891         .phy_ops                = &ich8_phy_ops,
5892         .nvm_ops                = &ich8_nvm_ops,
5893 };
5894
5895 const struct e1000_info e1000_pch_lpt_info = {
5896         .mac                    = e1000_pch_lpt,
5897         .flags                  = FLAG_IS_ICH
5898                                   | FLAG_HAS_WOL
5899                                   | FLAG_HAS_HW_TIMESTAMP
5900                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5901                                   | FLAG_HAS_AMT
5902                                   | FLAG_HAS_FLASH
5903                                   | FLAG_HAS_JUMBO_FRAMES
5904                                   | FLAG_APME_IN_WUC,
5905         .flags2                 = FLAG2_HAS_PHY_STATS
5906                                   | FLAG2_HAS_EEE
5907                                   | FLAG2_CHECK_SYSTIM_OVERFLOW,
5908         .pba                    = 26,
5909         .max_hw_frame_size      = 9022,
5910         .get_variants           = e1000_get_variants_ich8lan,
5911         .mac_ops                = &ich8_mac_ops,
5912         .phy_ops                = &ich8_phy_ops,
5913         .nvm_ops                = &ich8_nvm_ops,
5914 };
5915
5916 const struct e1000_info e1000_pch_spt_info = {
5917         .mac                    = e1000_pch_spt,
5918         .flags                  = FLAG_IS_ICH
5919                                   | FLAG_HAS_WOL
5920                                   | FLAG_HAS_HW_TIMESTAMP
5921                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5922                                   | FLAG_HAS_AMT
5923                                   | FLAG_HAS_FLASH
5924                                   | FLAG_HAS_JUMBO_FRAMES
5925                                   | FLAG_APME_IN_WUC,
5926         .flags2                 = FLAG2_HAS_PHY_STATS
5927                                   | FLAG2_HAS_EEE,
5928         .pba                    = 26,
5929         .max_hw_frame_size      = 9022,
5930         .get_variants           = e1000_get_variants_ich8lan,
5931         .mac_ops                = &ich8_mac_ops,
5932         .phy_ops                = &ich8_phy_ops,
5933         .nvm_ops                = &spt_nvm_ops,
5934 };
5935
5936 const struct e1000_info e1000_pch_cnp_info = {
5937         .mac                    = e1000_pch_cnp,
5938         .flags                  = FLAG_IS_ICH
5939                                   | FLAG_HAS_WOL
5940                                   | FLAG_HAS_HW_TIMESTAMP
5941                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5942                                   | FLAG_HAS_AMT
5943                                   | FLAG_HAS_FLASH
5944                                   | FLAG_HAS_JUMBO_FRAMES
5945                                   | FLAG_APME_IN_WUC,
5946         .flags2                 = FLAG2_HAS_PHY_STATS
5947                                   | FLAG2_HAS_EEE,
5948         .pba                    = 26,
5949         .max_hw_frame_size      = 9022,
5950         .get_variants           = e1000_get_variants_ich8lan,
5951         .mac_ops                = &ich8_mac_ops,
5952         .phy_ops                = &ich8_phy_ops,
5953         .nvm_ops                = &spt_nvm_ops,
5954 };