drivers/net/ethernet/intel/e1000e/80003es2lan.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2013 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /* 80003ES2LAN Gigabit Ethernet Controller (Copper)
  30  * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
  31  */
  32
  33 #include "e1000.h"
  34
  35 #define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL       0x00
  36 #define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL        0x02
  37 #define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL         0x10
  38 #define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE  0x1F
  39
  40 #define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS    0x0008
  41 #define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS    0x0800
  42 #define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING   0x0010
  43
  44 #define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004
  45 #define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT   0x0000
  46 #define E1000_KMRNCTRLSTA_OPMODE_E_IDLE          0x2000
  47
  48 #define E1000_KMRNCTRLSTA_OPMODE_MASK            0x000C
  49 #define E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO     0x0004
  50
  51 #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
  52 #define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN        0x00010000
  53
  54 #define DEFAULT_TIPG_IPGT_1000_80003ES2LAN       0x8
  55 #define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN     0x9
  56
  57 /* GG82563 PHY Specific Status Register (Page 0, Register 16 */
  58 #define GG82563_PSCR_POLARITY_REVERSAL_DISABLE   0x0002 /* 1=Reversal Disab. */
  59 #define GG82563_PSCR_CROSSOVER_MODE_MASK         0x0060
  60 #define GG82563_PSCR_CROSSOVER_MODE_MDI          0x0000 /* 00=Manual MDI */
  61 #define GG82563_PSCR_CROSSOVER_MODE_MDIX         0x0020 /* 01=Manual MDIX */
  62 #define GG82563_PSCR_CROSSOVER_MODE_AUTO         0x0060 /* 11=Auto crossover */
  63
  64 /* PHY Specific Control Register 2 (Page 0, Register 26) */
  65 #define GG82563_PSCR2_REVERSE_AUTO_NEG           0x2000
  66                                                 /* 1=Reverse Auto-Negotiation */
  67
  68 /* MAC Specific Control Register (Page 2, Register 21) */
  69 /* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
  70 #define GG82563_MSCR_TX_CLK_MASK                 0x0007
  71 #define GG82563_MSCR_TX_CLK_10MBPS_2_5           0x0004
  72 #define GG82563_MSCR_TX_CLK_100MBPS_25           0x0005
  73 #define GG82563_MSCR_TX_CLK_1000MBPS_25          0x0007
  74
  75 #define GG82563_MSCR_ASSERT_CRS_ON_TX            0x0010 /* 1=Assert */
  76
  77 /* DSP Distance Register (Page 5, Register 26) */
  78 #define GG82563_DSPD_CABLE_LENGTH                0x0007 /* 0 = <50M
  79                                                            1 = 50-80M
  80                                                            2 = 80-110M
  81                                                            3 = 110-140M
  82                                                            4 = >140M
  83                                                         */
  84
  85 /* Kumeran Mode Control Register (Page 193, Register 16) */
  86 #define GG82563_KMCR_PASS_FALSE_CARRIER          0x0800
  87
  88 /* Max number of times Kumeran read/write should be validated */
  89 #define GG82563_MAX_KMRN_RETRY  0x5
  90
  91 /* Power Management Control Register (Page 193, Register 20) */
  92 #define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE      0x0001
  93                                            /* 1=Enable SERDES Electrical Idle */
  94
  95 /* In-Band Control Register (Page 194, Register 18) */
  96 #define GG82563_ICR_DIS_PADDING                  0x0010 /* Disable Padding */
  97
  98 /* A table for the GG82563 cable length where the range is defined
  99  * with a lower bound at "index" and the upper bound at
 100  * "index + 5".
 101  */
 102 static const u16 e1000_gg82563_cable_length_table[] = {
 103          0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };
 104 #define GG82563_CABLE_LENGTH_TABLE_SIZE \
 105                 ARRAY_SIZE(e1000_gg82563_cable_length_table)
 106
 107 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
 108 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
 109 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
 110 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
 111 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
 112 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
 113 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
 114 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
 115                                            u16 *data);
 116 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
 117                                             u16 data);
 118 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);
 119
 120 /**
 121  *  e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
 122  *  @hw: pointer to the HW structure
 123  **/
 124 static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
 125 {
 126         struct e1000_phy_info *phy = &hw->phy;
 127         s32 ret_val;
 128
 129         if (hw->phy.media_type != e1000_media_type_copper) {
 130                 phy->type       = e1000_phy_none;
 131                 return 0;
 132         } else {
 133                 phy->ops.power_up = e1000_power_up_phy_copper;
 134                 phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan;
 135         }
 136
 137         phy->addr               = 1;
 138         phy->autoneg_mask       = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 139         phy->reset_delay_us      = 100;
 140         phy->type               = e1000_phy_gg82563;
 141
 142         /* This can only be done after all function pointers are setup. */
 143         ret_val = e1000e_get_phy_id(hw);
 144
 145         /* Verify phy id */
 146         if (phy->id != GG82563_E_PHY_ID)
 147                 return -E1000_ERR_PHY;
 148
 149         return ret_val;
 150 }
 151
 152 /**
 153  *  e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
 154  *  @hw: pointer to the HW structure
 155  **/
 156 static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
 157 {
 158         struct e1000_nvm_info *nvm = &hw->nvm;
 159         u32 eecd = er32(EECD);
 160         u16 size;
 161
 162         nvm->opcode_bits        = 8;
 163         nvm->delay_usec  = 1;
 164         switch (nvm->override) {
 165         case e1000_nvm_override_spi_large:
 166                 nvm->page_size    = 32;
 167                 nvm->address_bits = 16;
 168                 break;
 169         case e1000_nvm_override_spi_small:
 170                 nvm->page_size    = 8;
 171                 nvm->address_bits = 8;
 172                 break;
 173         default:
 174                 nvm->page_size    = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 175                 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
 176                 break;
 177         }
 178
 179         nvm->type = e1000_nvm_eeprom_spi;
 180
 181         size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 182                           E1000_EECD_SIZE_EX_SHIFT);
 183
 184         /* Added to a constant, "size" becomes the left-shift value
 185          * for setting word_size.
 186          */
 187         size += NVM_WORD_SIZE_BASE_SHIFT;
 188
 189         /* EEPROM access above 16k is unsupported */
 190         if (size > 14)
 191                 size = 14;
 192         nvm->word_size  = 1 << size;
 193
 194         return 0;
 195 }
 196
 197 /**
 198  *  e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
 199  *  @hw: pointer to the HW structure
 200  **/
 201 static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw)
 202 {
 203         struct e1000_mac_info *mac = &hw->mac;
 204
 205         /* Set media type and media-dependent function pointers */
 206         switch (hw->adapter->pdev->device) {
 207         case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
 208                 hw->phy.media_type = e1000_media_type_internal_serdes;
 209                 mac->ops.check_for_link = e1000e_check_for_serdes_link;
 210                 mac->ops.setup_physical_interface =
 211                     e1000e_setup_fiber_serdes_link;
 212                 break;
 213         default:
 214                 hw->phy.media_type = e1000_media_type_copper;
 215                 mac->ops.check_for_link = e1000e_check_for_copper_link;
 216                 mac->ops.setup_physical_interface =
 217                     e1000_setup_copper_link_80003es2lan;
 218                 break;
 219         }
 220
 221         /* Set mta register count */
 222         mac->mta_reg_count = 128;
 223         /* Set rar entry count */
 224         mac->rar_entry_count = E1000_RAR_ENTRIES;
 225         /* FWSM register */
 226         mac->has_fwsm = true;
 227         /* ARC supported; valid only if manageability features are enabled. */
 228         mac->arc_subsystem_valid = !!(er32(FWSM) & E1000_FWSM_MODE_MASK);
 229         /* Adaptive IFS not supported */
 230         mac->adaptive_ifs = false;
 231
 232         /* set lan id for port to determine which phy lock to use */
 233         hw->mac.ops.set_lan_id(hw);
 234
 235         return 0;
 236 }
 237
 238 static s32 e1000_get_variants_80003es2lan(struct e1000_adapter *adapter)
 239 {
 240         struct e1000_hw *hw = &adapter->hw;
 241         s32 rc;
 242
 243         rc = e1000_init_mac_params_80003es2lan(hw);
 244         if (rc)
 245                 return rc;
 246
 247         rc = e1000_init_nvm_params_80003es2lan(hw);
 248         if (rc)
 249                 return rc;
 250
 251         rc = e1000_init_phy_params_80003es2lan(hw);
 252         if (rc)
 253                 return rc;
 254
 255         return 0;
 256 }
 257
 258 /**
 259  *  e1000_acquire_phy_80003es2lan - Acquire rights to access PHY
 260  *  @hw: pointer to the HW structure
 261  *
 262  *  A wrapper to acquire access rights to the correct PHY.
 263  **/
 264 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)
 265 {
 266         u16 mask;
 267
 268         mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
 269         return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
 270 }
 271
 272 /**
 273  *  e1000_release_phy_80003es2lan - Release rights to access PHY
 274  *  @hw: pointer to the HW structure
 275  *
 276  *  A wrapper to release access rights to the correct PHY.
 277  **/
 278 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw)
 279 {
 280         u16 mask;
 281
 282         mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
 283         e1000_release_swfw_sync_80003es2lan(hw, mask);
 284 }
 285
 286 /**
 287  *  e1000_acquire_mac_csr_80003es2lan - Acquire right to access Kumeran register
 288  *  @hw: pointer to the HW structure
 289  *
 290  *  Acquire the semaphore to access the Kumeran interface.
 291  *
 292  **/
 293 static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)
 294 {
 295         u16 mask;
 296
 297         mask = E1000_SWFW_CSR_SM;
 298
 299         return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
 300 }
 301
 302 /**
 303  *  e1000_release_mac_csr_80003es2lan - Release right to access Kumeran Register
 304  *  @hw: pointer to the HW structure
 305  *
 306  *  Release the semaphore used to access the Kumeran interface
 307  **/
 308 static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw)
 309 {
 310         u16 mask;
 311
 312         mask = E1000_SWFW_CSR_SM;
 313
 314         e1000_release_swfw_sync_80003es2lan(hw, mask);
 315 }
 316
 317 /**
 318  *  e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM
 319  *  @hw: pointer to the HW structure
 320  *
 321  *  Acquire the semaphore to access the EEPROM.
 322  **/
 323 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)
 324 {
 325         s32 ret_val;
 326
 327         ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
 328         if (ret_val)
 329                 return ret_val;
 330
 331         ret_val = e1000e_acquire_nvm(hw);
 332
 333         if (ret_val)
 334                 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
 335
 336         return ret_val;
 337 }
 338
 339 /**
 340  *  e1000_release_nvm_80003es2lan - Relinquish rights to access NVM
 341  *  @hw: pointer to the HW structure
 342  *
 343  *  Release the semaphore used to access the EEPROM.
 344  **/
 345 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)
 346 {
 347         e1000e_release_nvm(hw);
 348         e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
 349 }
 350
 351 /**
 352  *  e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore
 353  *  @hw: pointer to the HW structure
 354  *  @mask: specifies which semaphore to acquire
 355  *
 356  *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
 357  *  will also specify which port we're acquiring the lock for.
 358  **/
 359 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
 360 {
 361         u32 swfw_sync;
 362         u32 swmask = mask;
 363         u32 fwmask = mask << 16;
 364         s32 i = 0;
 365         s32 timeout = 50;
 366
 367         while (i < timeout) {
 368                 if (e1000e_get_hw_semaphore(hw))
 369                         return -E1000_ERR_SWFW_SYNC;
 370
 371                 swfw_sync = er32(SW_FW_SYNC);
 372                 if (!(swfw_sync & (fwmask | swmask)))
 373                         break;
 374
 375                 /* Firmware currently using resource (fwmask)
 376                  * or other software thread using resource (swmask)
 377                  */
 378                 e1000e_put_hw_semaphore(hw);
 379                 mdelay(5);
 380                 i++;
 381         }
 382
 383         if (i == timeout) {
 384                 e_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
 385                 return -E1000_ERR_SWFW_SYNC;
 386         }
 387
 388         swfw_sync |= swmask;
 389         ew32(SW_FW_SYNC, swfw_sync);
 390
 391         e1000e_put_hw_semaphore(hw);
 392
 393         return 0;
 394 }
 395
 396 /**
 397  *  e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore
 398  *  @hw: pointer to the HW structure
 399  *  @mask: specifies which semaphore to acquire
 400  *
 401  *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
 402  *  will also specify which port we're releasing the lock for.
 403  **/
 404 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
 405 {
 406         u32 swfw_sync;
 407
 408         while (e1000e_get_hw_semaphore(hw) != 0)
 409                 ; /* Empty */
 410
 411         swfw_sync = er32(SW_FW_SYNC);
 412         swfw_sync &= ~mask;
 413         ew32(SW_FW_SYNC, swfw_sync);
 414
 415         e1000e_put_hw_semaphore(hw);
 416 }
 417
 418 /**
 419  *  e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
 420  *  @hw: pointer to the HW structure
 421  *  @offset: offset of the register to read
 422  *  @data: pointer to the data returned from the operation
 423  *
 424  *  Read the GG82563 PHY register.
 425  **/
 426 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
 427                                                   u32 offset, u16 *data)
 428 {
 429         s32 ret_val;
 430         u32 page_select;
 431         u16 temp;
 432
 433         ret_val = e1000_acquire_phy_80003es2lan(hw);
 434         if (ret_val)
 435                 return ret_val;
 436
 437         /* Select Configuration Page */
 438         if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
 439                 page_select = GG82563_PHY_PAGE_SELECT;
 440         } else {
 441                 /* Use Alternative Page Select register to access
 442                  * registers 30 and 31
 443                  */
 444                 page_select = GG82563_PHY_PAGE_SELECT_ALT;
 445         }
 446
 447         temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
 448         ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
 449         if (ret_val) {
 450                 e1000_release_phy_80003es2lan(hw);
 451                 return ret_val;
 452         }
 453
 454         if (hw->dev_spec.e80003es2lan.mdic_wa_enable) {
 455                 /* The "ready" bit in the MDIC register may be incorrectly set
 456                  * before the device has completed the "Page Select" MDI
 457                  * transaction.  So we wait 200us after each MDI command...
 458                  */
 459                 udelay(200);
 460
 461                 /* ...and verify the command was successful. */
 462                 ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
 463
 464                 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
 465                         e1000_release_phy_80003es2lan(hw);
 466                         return -E1000_ERR_PHY;
 467                 }
 468
 469                 udelay(200);
 470
 471                 ret_val = e1000e_read_phy_reg_mdic(hw,
 472                                                   MAX_PHY_REG_ADDRESS & offset,
 473                                                   data);
 474
 475                 udelay(200);
 476         } else {
 477                 ret_val = e1000e_read_phy_reg_mdic(hw,
 478                                                   MAX_PHY_REG_ADDRESS & offset,
 479                                                   data);
 480         }
 481
 482         e1000_release_phy_80003es2lan(hw);
 483
 484         return ret_val;
 485 }
 486
 487 /**
 488  *  e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
 489  *  @hw: pointer to the HW structure
 490  *  @offset: offset of the register to read
 491  *  @data: value to write to the register
 492  *
 493  *  Write to the GG82563 PHY register.
 494  **/
 495 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
 496                                                    u32 offset, u16 data)
 497 {
 498         s32 ret_val;
 499         u32 page_select;
 500         u16 temp;
 501
 502         ret_val = e1000_acquire_phy_80003es2lan(hw);
 503         if (ret_val)
 504                 return ret_val;
 505
 506         /* Select Configuration Page */
 507         if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
 508                 page_select = GG82563_PHY_PAGE_SELECT;
 509         } else {
 510                 /* Use Alternative Page Select register to access
 511                  * registers 30 and 31
 512                  */
 513                 page_select = GG82563_PHY_PAGE_SELECT_ALT;
 514         }
 515
 516         temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
 517         ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
 518         if (ret_val) {
 519                 e1000_release_phy_80003es2lan(hw);
 520                 return ret_val;
 521         }
 522
 523         if (hw->dev_spec.e80003es2lan.mdic_wa_enable) {
 524                 /* The "ready" bit in the MDIC register may be incorrectly set
 525                  * before the device has completed the "Page Select" MDI
 526                  * transaction.  So we wait 200us after each MDI command...
 527                  */
 528                 udelay(200);
 529
 530                 /* ...and verify the command was successful. */
 531                 ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
 532
 533                 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
 534                         e1000_release_phy_80003es2lan(hw);
 535                         return -E1000_ERR_PHY;
 536                 }
 537
 538                 udelay(200);
 539
 540                 ret_val = e1000e_write_phy_reg_mdic(hw,
 541                                                   MAX_PHY_REG_ADDRESS & offset,
 542                                                   data);
 543
 544                 udelay(200);
 545         } else {
 546                 ret_val = e1000e_write_phy_reg_mdic(hw,
 547                                                   MAX_PHY_REG_ADDRESS & offset,
 548                                                   data);
 549         }
 550
 551         e1000_release_phy_80003es2lan(hw);
 552
 553         return ret_val;
 554 }
 555
 556 /**
 557  *  e1000_write_nvm_80003es2lan - Write to ESB2 NVM
 558  *  @hw: pointer to the HW structure
 559  *  @offset: offset of the register to read
 560  *  @words: number of words to write
 561  *  @data: buffer of data to write to the NVM
 562  *
 563  *  Write "words" of data to the ESB2 NVM.
 564  **/
 565 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
 566                                        u16 words, u16 *data)
 567 {
 568         return e1000e_write_nvm_spi(hw, offset, words, data);
 569 }
 570
 571 /**
 572  *  e1000_get_cfg_done_80003es2lan - Wait for configuration to complete
 573  *  @hw: pointer to the HW structure
 574  *
 575  *  Wait a specific amount of time for manageability processes to complete.
 576  *  This is a function pointer entry point called by the phy module.
 577  **/
 578 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)
 579 {
 580         s32 timeout = PHY_CFG_TIMEOUT;
 581         u32 mask = E1000_NVM_CFG_DONE_PORT_0;
 582
 583         if (hw->bus.func == 1)
 584                 mask = E1000_NVM_CFG_DONE_PORT_1;
 585
 586         while (timeout) {
 587                 if (er32(EEMNGCTL) & mask)
 588                         break;
 589                 usleep_range(1000, 2000);
 590                 timeout--;
 591         }
 592         if (!timeout) {
 593                 e_dbg("MNG configuration cycle has not completed.\n");
 594                 return -E1000_ERR_RESET;
 595         }
 596
 597         return 0;
 598 }
 599
 600 /**
 601  *  e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex
 602  *  @hw: pointer to the HW structure
 603  *
 604  *  Force the speed and duplex settings onto the PHY.  This is a
 605  *  function pointer entry point called by the phy module.
 606  **/
 607 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
 608 {
 609         s32 ret_val;
 610         u16 phy_data;
 611         bool link;
 612
 613         /* Clear Auto-Crossover to force MDI manually.  M88E1000 requires MDI
 614          * forced whenever speed and duplex are forced.
 615          */
 616         ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
 617         if (ret_val)
 618                 return ret_val;
 619
 620         phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO;
 621         ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, phy_data);
 622         if (ret_val)
 623                 return ret_val;
 624
 625         e_dbg("GG82563 PSCR: %X\n", phy_data);
 626
 627         ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
 628         if (ret_val)
 629                 return ret_val;
 630
 631         e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
 632
 633         /* Reset the phy to commit changes. */
 634         phy_data |= MII_CR_RESET;
 635
 636         ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
 637         if (ret_val)
 638                 return ret_val;
 639
 640         udelay(1);
 641
 642         if (hw->phy.autoneg_wait_to_complete) {
 643                 e_dbg("Waiting for forced speed/duplex link on GG82563 phy.\n");
 644
 645                 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
 646                                                      100000, &link);
 647                 if (ret_val)
 648                         return ret_val;
 649
 650                 if (!link) {
 651                         /* We didn't get link.
 652                          * Reset the DSP and cross our fingers.
 653                          */
 654                         ret_val = e1000e_phy_reset_dsp(hw);
 655                         if (ret_val)
 656                                 return ret_val;
 657                 }
 658
 659                 /* Try once more */
 660                 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
 661                                                      100000, &link);
 662                 if (ret_val)
 663                         return ret_val;
 664         }
 665
 666         ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
 667         if (ret_val)
 668                 return ret_val;
 669
 670         /* Resetting the phy means we need to verify the TX_CLK corresponds
 671          * to the link speed.  10Mbps -> 2.5MHz, else 25MHz.
 672          */
 673         phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
 674         if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
 675                 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;
 676         else
 677                 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
 678
 679         /* In addition, we must re-enable CRS on Tx for both half and full
 680          * duplex.
 681          */
 682         phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
 683         ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
 684
 685         return ret_val;
 686 }
 687
 688 /**
 689  *  e1000_get_cable_length_80003es2lan - Set approximate cable length
 690  *  @hw: pointer to the HW structure
 691  *
 692  *  Find the approximate cable length as measured by the GG82563 PHY.
 693  *  This is a function pointer entry point called by the phy module.
 694  **/
 695 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)
 696 {
 697         struct e1000_phy_info *phy = &hw->phy;
 698         s32 ret_val;
 699         u16 phy_data, index;
 700
 701         ret_val = e1e_rphy(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
 702         if (ret_val)
 703                 return ret_val;
 704
 705         index = phy_data & GG82563_DSPD_CABLE_LENGTH;
 706
 707         if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5)
 708                 return -E1000_ERR_PHY;
 709
 710         phy->min_cable_length = e1000_gg82563_cable_length_table[index];
 711         phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5];
 712
 713         phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
 714
 715         return 0;
 716 }
 717
 718 /**
 719  *  e1000_get_link_up_info_80003es2lan - Report speed and duplex
 720  *  @hw: pointer to the HW structure
 721  *  @speed: pointer to speed buffer
 722  *  @duplex: pointer to duplex buffer
 723  *
 724  *  Retrieve the current speed and duplex configuration.
 725  **/
 726 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
 727                                               u16 *duplex)
 728 {
 729         s32 ret_val;
 730
 731         if (hw->phy.media_type == e1000_media_type_copper) {
 732                 ret_val = e1000e_get_speed_and_duplex_copper(hw,
 733                                                                     speed,
 734                                                                     duplex);
 735                 hw->phy.ops.cfg_on_link_up(hw);
 736         } else {
 737                 ret_val = e1000e_get_speed_and_duplex_fiber_serdes(hw,
 738                                                                   speed,
 739                                                                   duplex);
 740         }
 741
 742         return ret_val;
 743 }
 744
 745 /**
 746  *  e1000_reset_hw_80003es2lan - Reset the ESB2 controller
 747  *  @hw: pointer to the HW structure
 748  *
 749  *  Perform a global reset to the ESB2 controller.
 750  **/
 751 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
 752 {
 753         u32 ctrl;
 754         s32 ret_val;
 755         u16 kum_reg_data;
 756
 757         /* Prevent the PCI-E bus from sticking if there is no TLP connection
 758          * on the last TLP read/write transaction when MAC is reset.
 759          */
 760         ret_val = e1000e_disable_pcie_master(hw);
 761         if (ret_val)
 762                 e_dbg("PCI-E Master disable polling has failed.\n");
 763
 764         e_dbg("Masking off all interrupts\n");
 765         ew32(IMC, 0xffffffff);
 766
 767         ew32(RCTL, 0);
 768         ew32(TCTL, E1000_TCTL_PSP);
 769         e1e_flush();
 770
 771         usleep_range(10000, 20000);
 772
 773         ctrl = er32(CTRL);
 774
 775         ret_val = e1000_acquire_phy_80003es2lan(hw);
 776         if (ret_val)
 777                 return ret_val;
 778
 779         e_dbg("Issuing a global reset to MAC\n");
 780         ew32(CTRL, ctrl | E1000_CTRL_RST);
 781         e1000_release_phy_80003es2lan(hw);
 782
 783         /* Disable IBIST slave mode (far-end loopback) */
 784         e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
 785                                         &kum_reg_data);
 786         kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
 787         e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
 788                                          kum_reg_data);
 789
 790         ret_val = e1000e_get_auto_rd_done(hw);
 791         if (ret_val)
 792                 /* We don't want to continue accessing MAC registers. */
 793                 return ret_val;
 794
 795         /* Clear any pending interrupt events. */
 796         ew32(IMC, 0xffffffff);
 797         er32(ICR);
 798
 799         return e1000_check_alt_mac_addr_generic(hw);
 800 }
 801
 802 /**
 803  *  e1000_init_hw_80003es2lan - Initialize the ESB2 controller
 804  *  @hw: pointer to the HW structure
 805  *
 806  *  Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
 807  **/
 808 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
 809 {
 810         struct e1000_mac_info *mac = &hw->mac;
 811         u32 reg_data;
 812         s32 ret_val;
 813         u16 kum_reg_data;
 814         u16 i;
 815
 816         e1000_initialize_hw_bits_80003es2lan(hw);
 817
 818         /* Initialize identification LED */
 819         ret_val = mac->ops.id_led_init(hw);
 820         if (ret_val)
 821                 e_dbg("Error initializing identification LED\n");
 822                 /* This is not fatal and we should not stop init due to this */
 823
 824         /* Disabling VLAN filtering */
 825         e_dbg("Initializing the IEEE VLAN\n");
 826         mac->ops.clear_vfta(hw);
 827
 828         /* Setup the receive address. */
 829         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
 830
 831         /* Zero out the Multicast HASH table */
 832         e_dbg("Zeroing the MTA\n");
 833         for (i = 0; i < mac->mta_reg_count; i++)
 834                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
 835
 836         /* Setup link and flow control */
 837         ret_val = mac->ops.setup_link(hw);
 838         if (ret_val)
 839                 return ret_val;
 840
 841         /* Disable IBIST slave mode (far-end loopback) */
 842         e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
 843                                         &kum_reg_data);
 844         kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
 845         e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
 846                                          kum_reg_data);
 847
 848         /* Set the transmit descriptor write-back policy */
 849         reg_data = er32(TXDCTL(0));
 850         reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
 851                    E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
 852         ew32(TXDCTL(0), reg_data);
 853
 854         /* ...for both queues. */
 855         reg_data = er32(TXDCTL(1));
 856         reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
 857                    E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
 858         ew32(TXDCTL(1), reg_data);
 859
 860         /* Enable retransmit on late collisions */
 861         reg_data = er32(TCTL);
 862         reg_data |= E1000_TCTL_RTLC;
 863         ew32(TCTL, reg_data);
 864
 865         /* Configure Gigabit Carry Extend Padding */
 866         reg_data = er32(TCTL_EXT);
 867         reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
 868         reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN;
 869         ew32(TCTL_EXT, reg_data);
 870
 871         /* Configure Transmit Inter-Packet Gap */
 872         reg_data = er32(TIPG);
 873         reg_data &= ~E1000_TIPG_IPGT_MASK;
 874         reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
 875         ew32(TIPG, reg_data);
 876
 877         reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
 878         reg_data &= ~0x00100000;
 879         E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
 880
 881         /* default to true to enable the MDIC W/A */
 882         hw->dev_spec.e80003es2lan.mdic_wa_enable = true;
 883
 884         ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
 885                                       E1000_KMRNCTRLSTA_OFFSET >>
 886                                       E1000_KMRNCTRLSTA_OFFSET_SHIFT,
 887                                       &i);
 888         if (!ret_val) {
 889                 if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) ==
 890                      E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO)
 891                         hw->dev_spec.e80003es2lan.mdic_wa_enable = false;
 892         }
 893
 894         /* Clear all of the statistics registers (clear on read).  It is
 895          * important that we do this after we have tried to establish link
 896          * because the symbol error count will increment wildly if there
 897          * is no link.
 898          */
 899         e1000_clear_hw_cntrs_80003es2lan(hw);
 900
 901         return ret_val;
 902 }
 903
 904 /**
 905  *  e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
 906  *  @hw: pointer to the HW structure
 907  *
 908  *  Initializes required hardware-dependent bits needed for normal operation.
 909  **/
 910 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
 911 {
 912         u32 reg;
 913
 914         /* Transmit Descriptor Control 0 */
 915         reg = er32(TXDCTL(0));
 916         reg |= (1 << 22);
 917         ew32(TXDCTL(0), reg);
 918
 919         /* Transmit Descriptor Control 1 */
 920         reg = er32(TXDCTL(1));
 921         reg |= (1 << 22);
 922         ew32(TXDCTL(1), reg);
 923
 924         /* Transmit Arbitration Control 0 */
 925         reg = er32(TARC(0));
 926         reg &= ~(0xF << 27); /* 30:27 */
 927         if (hw->phy.media_type != e1000_media_type_copper)
 928                 reg &= ~(1 << 20);
 929         ew32(TARC(0), reg);
 930
 931         /* Transmit Arbitration Control 1 */
 932         reg = er32(TARC(1));
 933         if (er32(TCTL) & E1000_TCTL_MULR)
 934                 reg &= ~(1 << 28);
 935         else
 936                 reg |= (1 << 28);
 937         ew32(TARC(1), reg);
 938
 939         /* Disable IPv6 extension header parsing because some malformed
 940          * IPv6 headers can hang the Rx.
 941          */
 942         reg = er32(RFCTL);
 943         reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
 944         ew32(RFCTL, reg);
 945 }
 946
 947 /**
 948  *  e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link
 949  *  @hw: pointer to the HW structure
 950  *
 951  *  Setup some GG82563 PHY registers for obtaining link
 952  **/
 953 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
 954 {
 955         struct e1000_phy_info *phy = &hw->phy;
 956         s32 ret_val;
 957         u32 ctrl_ext;
 958         u16 data;
 959
 960         ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &data);
 961         if (ret_val)
 962                 return ret_val;
 963
 964         data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
 965         /* Use 25MHz for both link down and 1000Base-T for Tx clock. */
 966         data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
 967
 968         ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, data);
 969         if (ret_val)
 970                 return ret_val;
 971
 972         /* Options:
 973          *   MDI/MDI-X = 0 (default)
 974          *   0 - Auto for all speeds
 975          *   1 - MDI mode
 976          *   2 - MDI-X mode
 977          *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
 978          */
 979         ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL, &data);
 980         if (ret_val)
 981                 return ret_val;
 982
 983         data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
 984
 985         switch (phy->mdix) {
 986         case 1:
 987                 data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
 988                 break;
 989         case 2:
 990                 data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
 991                 break;
 992         case 0:
 993         default:
 994                 data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
 995                 break;
 996         }
 997
 998         /* Options:
 999          *   disable_polarity_correction = 0 (default)
1000          *       Automatic Correction for Reversed Cable Polarity
1001          *   0 - Disabled
1002          *   1 - Enabled
1003          */
1004         data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1005         if (phy->disable_polarity_correction)
1006                 data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1007
1008         ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, data);
1009         if (ret_val)
1010                 return ret_val;
1011
1012         /* SW Reset the PHY so all changes take effect */
1013         ret_val = hw->phy.ops.commit(hw);
1014         if (ret_val) {
1015                 e_dbg("Error Resetting the PHY\n");
1016                 return ret_val;
1017         }
1018
1019         /* Bypass Rx and Tx FIFO's */
1020         ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1021                                         E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL,
1022                                         E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
1023                                         E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
1024         if (ret_val)
1025                 return ret_val;
1026
1027         ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
1028                                        E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
1029                                        &data);
1030         if (ret_val)
1031                 return ret_val;
1032         data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;
1033         ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1034                                         E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
1035                                         data);
1036         if (ret_val)
1037                 return ret_val;
1038
1039         ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL_2, &data);
1040         if (ret_val)
1041                 return ret_val;
1042
1043         data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
1044         ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL_2, data);
1045         if (ret_val)
1046                 return ret_val;
1047
1048         ctrl_ext = er32(CTRL_EXT);
1049         ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
1050         ew32(CTRL_EXT, ctrl_ext);
1051
1052         ret_val = e1e_rphy(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
1053         if (ret_val)
1054                 return ret_val;
1055
1056         /* Do not init these registers when the HW is in IAMT mode, since the
1057          * firmware will have already initialized them.  We only initialize
1058          * them if the HW is not in IAMT mode.
1059          */
1060         if (!hw->mac.ops.check_mng_mode(hw)) {
1061                 /* Enable Electrical Idle on the PHY */
1062                 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
1063                 ret_val = e1e_wphy(hw, GG82563_PHY_PWR_MGMT_CTRL, data);
1064                 if (ret_val)
1065                         return ret_val;
1066
1067                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &data);
1068                 if (ret_val)
1069                         return ret_val;
1070
1071                 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1072                 ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, data);
1073                 if (ret_val)
1074                         return ret_val;
1075         }
1076
1077         /* Workaround: Disable padding in Kumeran interface in the MAC
1078          * and in the PHY to avoid CRC errors.
1079          */
1080         ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data);
1081         if (ret_val)
1082                 return ret_val;
1083
1084         data |= GG82563_ICR_DIS_PADDING;
1085         ret_val = e1e_wphy(hw, GG82563_PHY_INBAND_CTRL, data);
1086         if (ret_val)
1087                 return ret_val;
1088
1089         return 0;
1090 }
1091
1092 /**
1093  *  e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2
1094  *  @hw: pointer to the HW structure
1095  *
1096  *  Essentially a wrapper for setting up all things "copper" related.
1097  *  This is a function pointer entry point called by the mac module.
1098  **/
1099 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
1100 {
1101         u32 ctrl;
1102         s32 ret_val;
1103         u16 reg_data;
1104
1105         ctrl = er32(CTRL);
1106         ctrl |= E1000_CTRL_SLU;
1107         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1108         ew32(CTRL, ctrl);
1109
1110         /* Set the mac to wait the maximum time between each
1111          * iteration and increase the max iterations when
1112          * polling the phy; this fixes erroneous timeouts at 10Mbps.
1113          */
1114         ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4),
1115                                                    0xFFFF);
1116         if (ret_val)
1117                 return ret_val;
1118         ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1119                                                   &reg_data);
1120         if (ret_val)
1121                 return ret_val;
1122         reg_data |= 0x3F;
1123         ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1124                                                    reg_data);
1125         if (ret_val)
1126                 return ret_val;
1127         ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
1128                                       E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1129                                       &reg_data);
1130         if (ret_val)
1131                 return ret_val;
1132         reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
1133         ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1134                                         E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1135                                         reg_data);
1136         if (ret_val)
1137                 return ret_val;
1138
1139         ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
1140         if (ret_val)
1141                 return ret_val;
1142
1143         return e1000e_setup_copper_link(hw);
1144 }
1145
1146 /**
1147  *  e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up
1148  *  @hw: pointer to the HW structure
1149  *  @duplex: current duplex setting
1150  *
1151  *  Configure the KMRN interface by applying last minute quirks for
1152  *  10/100 operation.
1153  **/
1154 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw)
1155 {
1156         s32 ret_val = 0;
1157         u16 speed;
1158         u16 duplex;
1159
1160         if (hw->phy.media_type == e1000_media_type_copper) {
1161                 ret_val = e1000e_get_speed_and_duplex_copper(hw, &speed,
1162                                                              &duplex);
1163                 if (ret_val)
1164                         return ret_val;
1165
1166                 if (speed == SPEED_1000)
1167                         ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
1168                 else
1169                         ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex);
1170         }
1171
1172         return ret_val;
1173 }
1174
1175 /**
1176  *  e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation
1177  *  @hw: pointer to the HW structure
1178  *  @duplex: current duplex setting
1179  *
1180  *  Configure the KMRN interface by applying last minute quirks for
1181  *  10/100 operation.
1182  **/
1183 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
1184 {
1185         s32 ret_val;
1186         u32 tipg;
1187         u32 i = 0;
1188         u16 reg_data, reg_data2;
1189
1190         reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
1191         ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1192                                        E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1193                                        reg_data);
1194         if (ret_val)
1195                 return ret_val;
1196
1197         /* Configure Transmit Inter-Packet Gap */
1198         tipg = er32(TIPG);
1199         tipg &= ~E1000_TIPG_IPGT_MASK;
1200         tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
1201         ew32(TIPG, tipg);
1202
1203         do {
1204                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
1205                 if (ret_val)
1206                         return ret_val;
1207
1208                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data2);
1209                 if (ret_val)
1210                         return ret_val;
1211                 i++;
1212         } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1213
1214         if (duplex == HALF_DUPLEX)
1215                 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1216         else
1217                 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1218
1219         return e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1220 }
1221
1222 /**
1223  *  e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
1224  *  @hw: pointer to the HW structure
1225  *
1226  *  Configure the KMRN interface by applying last minute quirks for
1227  *  gigabit operation.
1228  **/
1229 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
1230 {
1231         s32 ret_val;
1232         u16 reg_data, reg_data2;
1233         u32 tipg;
1234         u32 i = 0;
1235
1236         reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
1237         ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1238                                        E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1239                                        reg_data);
1240         if (ret_val)
1241                 return ret_val;
1242
1243         /* Configure Transmit Inter-Packet Gap */
1244         tipg = er32(TIPG);
1245         tipg &= ~E1000_TIPG_IPGT_MASK;
1246         tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
1247         ew32(TIPG, tipg);
1248
1249         do {
1250                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
1251                 if (ret_val)
1252                         return ret_val;
1253
1254                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data2);
1255                 if (ret_val)
1256                         return ret_val;
1257                 i++;
1258         } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1259
1260         reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1261
1262         return e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1263 }
1264
1265 /**
1266  *  e1000_read_kmrn_reg_80003es2lan - Read kumeran register
1267  *  @hw: pointer to the HW structure
1268  *  @offset: register offset to be read
1269  *  @data: pointer to the read data
1270  *
1271  *  Acquire semaphore, then read the PHY register at offset
1272  *  using the kumeran interface.  The information retrieved is stored in data.
1273  *  Release the semaphore before exiting.
1274  **/
1275 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1276                                            u16 *data)
1277 {
1278         u32 kmrnctrlsta;
1279         s32 ret_val;
1280
1281         ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1282         if (ret_val)
1283                 return ret_val;
1284
1285         kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1286                        E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
1287         ew32(KMRNCTRLSTA, kmrnctrlsta);
1288         e1e_flush();
1289
1290         udelay(2);
1291
1292         kmrnctrlsta = er32(KMRNCTRLSTA);
1293         *data = (u16)kmrnctrlsta;
1294
1295         e1000_release_mac_csr_80003es2lan(hw);
1296
1297         return ret_val;
1298 }
1299
1300 /**
1301  *  e1000_write_kmrn_reg_80003es2lan - Write kumeran register
1302  *  @hw: pointer to the HW structure
1303  *  @offset: register offset to write to
1304  *  @data: data to write at register offset
1305  *
1306  *  Acquire semaphore, then write the data to PHY register
1307  *  at the offset using the kumeran interface.  Release semaphore
1308  *  before exiting.
1309  **/
1310 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1311                                             u16 data)
1312 {
1313         u32 kmrnctrlsta;
1314         s32 ret_val;
1315
1316         ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1317         if (ret_val)
1318                 return ret_val;
1319
1320         kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1321                        E1000_KMRNCTRLSTA_OFFSET) | data;
1322         ew32(KMRNCTRLSTA, kmrnctrlsta);
1323         e1e_flush();
1324
1325         udelay(2);
1326
1327         e1000_release_mac_csr_80003es2lan(hw);
1328
1329         return ret_val;
1330 }
1331
1332 /**
1333  *  e1000_read_mac_addr_80003es2lan - Read device MAC address
1334  *  @hw: pointer to the HW structure
1335  **/
1336 static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw)
1337 {
1338         s32 ret_val;
1339
1340         /* If there's an alternate MAC address place it in RAR0
1341          * so that it will override the Si installed default perm
1342          * address.
1343          */
1344         ret_val = e1000_check_alt_mac_addr_generic(hw);
1345         if (ret_val)
1346                 return ret_val;
1347
1348         return e1000_read_mac_addr_generic(hw);
1349 }
1350
1351 /**
1352  * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down
1353  * @hw: pointer to the HW structure
1354  *
1355  * In the case of a PHY power down to save power, or to turn off link during a
1356  * driver unload, or wake on lan is not enabled, remove the link.
1357  **/
1358 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw)
1359 {
1360         /* If the management interface is not enabled, then power down */
1361         if (!(hw->mac.ops.check_mng_mode(hw) ||
1362               hw->phy.ops.check_reset_block(hw)))
1363                 e1000_power_down_phy_copper(hw);
1364 }
1365
1366 /**
1367  *  e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters
1368  *  @hw: pointer to the HW structure
1369  *
1370  *  Clears the hardware counters by reading the counter registers.
1371  **/
1372 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)
1373 {
1374         e1000e_clear_hw_cntrs_base(hw);
1375
1376         er32(PRC64);
1377         er32(PRC127);
1378         er32(PRC255);
1379         er32(PRC511);
1380         er32(PRC1023);
1381         er32(PRC1522);
1382         er32(PTC64);
1383         er32(PTC127);
1384         er32(PTC255);
1385         er32(PTC511);
1386         er32(PTC1023);
1387         er32(PTC1522);
1388
1389         er32(ALGNERRC);
1390         er32(RXERRC);
1391         er32(TNCRS);
1392         er32(CEXTERR);
1393         er32(TSCTC);
1394         er32(TSCTFC);
1395
1396         er32(MGTPRC);
1397         er32(MGTPDC);
1398         er32(MGTPTC);
1399
1400         er32(IAC);
1401         er32(ICRXOC);
1402
1403         er32(ICRXPTC);
1404         er32(ICRXATC);
1405         er32(ICTXPTC);
1406         er32(ICTXATC);
1407         er32(ICTXQEC);
1408         er32(ICTXQMTC);
1409         er32(ICRXDMTC);
1410 }
1411
1412 static const struct e1000_mac_operations es2_mac_ops = {
1413         .read_mac_addr          = e1000_read_mac_addr_80003es2lan,
1414         .id_led_init            = e1000e_id_led_init_generic,
1415         .blink_led              = e1000e_blink_led_generic,
1416         .check_mng_mode         = e1000e_check_mng_mode_generic,
1417         /* check_for_link dependent on media type */
1418         .cleanup_led            = e1000e_cleanup_led_generic,
1419         .clear_hw_cntrs         = e1000_clear_hw_cntrs_80003es2lan,
1420         .get_bus_info           = e1000e_get_bus_info_pcie,
1421         .set_lan_id             = e1000_set_lan_id_multi_port_pcie,
1422         .get_link_up_info       = e1000_get_link_up_info_80003es2lan,
1423         .led_on                 = e1000e_led_on_generic,
1424         .led_off                = e1000e_led_off_generic,
1425         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
1426         .write_vfta             = e1000_write_vfta_generic,
1427         .clear_vfta             = e1000_clear_vfta_generic,
1428         .reset_hw               = e1000_reset_hw_80003es2lan,
1429         .init_hw                = e1000_init_hw_80003es2lan,
1430         .setup_link             = e1000e_setup_link_generic,
1431         /* setup_physical_interface dependent on media type */
1432         .setup_led              = e1000e_setup_led_generic,
1433         .config_collision_dist  = e1000e_config_collision_dist_generic,
1434         .rar_set                = e1000e_rar_set_generic,
1435 };
1436
1437 static const struct e1000_phy_operations es2_phy_ops = {
1438         .acquire                = e1000_acquire_phy_80003es2lan,
1439         .check_polarity         = e1000_check_polarity_m88,
1440         .check_reset_block      = e1000e_check_reset_block_generic,
1441         .commit                 = e1000e_phy_sw_reset,
1442         .force_speed_duplex     = e1000_phy_force_speed_duplex_80003es2lan,
1443         .get_cfg_done           = e1000_get_cfg_done_80003es2lan,
1444         .get_cable_length       = e1000_get_cable_length_80003es2lan,
1445         .get_info               = e1000e_get_phy_info_m88,
1446         .read_reg               = e1000_read_phy_reg_gg82563_80003es2lan,
1447         .release                = e1000_release_phy_80003es2lan,
1448         .reset                  = e1000e_phy_hw_reset_generic,
1449         .set_d0_lplu_state      = NULL,
1450         .set_d3_lplu_state      = e1000e_set_d3_lplu_state,
1451         .write_reg              = e1000_write_phy_reg_gg82563_80003es2lan,
1452         .cfg_on_link_up         = e1000_cfg_on_link_up_80003es2lan,
1453 };
1454
1455 static const struct e1000_nvm_operations es2_nvm_ops = {
1456         .acquire                = e1000_acquire_nvm_80003es2lan,
1457         .read                   = e1000e_read_nvm_eerd,
1458         .release                = e1000_release_nvm_80003es2lan,
1459         .reload                 = e1000e_reload_nvm_generic,
1460         .update                 = e1000e_update_nvm_checksum_generic,
1461         .valid_led_default      = e1000e_valid_led_default,
1462         .validate               = e1000e_validate_nvm_checksum_generic,
1463         .write                  = e1000_write_nvm_80003es2lan,
1464 };
1465
1466 const struct e1000_info e1000_es2_info = {
1467         .mac                    = e1000_80003es2lan,
1468         .flags                  = FLAG_HAS_HW_VLAN_FILTER
1469                                   | FLAG_HAS_JUMBO_FRAMES
1470                                   | FLAG_HAS_WOL
1471                                   | FLAG_APME_IN_CTRL3
1472                                   | FLAG_HAS_CTRLEXT_ON_LOAD
1473                                   | FLAG_RX_NEEDS_RESTART /* errata */
1474                                   | FLAG_TARC_SET_BIT_ZERO /* errata */
1475                                   | FLAG_APME_CHECK_PORT_B
1476                                   | FLAG_DISABLE_FC_PAUSE_TIME, /* errata */
1477         .flags2                 = FLAG2_DMA_BURST,
1478         .pba                    = 38,
1479         .max_hw_frame_size      = DEFAULT_JUMBO,
1480         .get_variants           = e1000_get_variants_80003es2lan,
1481         .mac_ops                = &es2_mac_ops,
1482         .phy_ops                = &es2_phy_ops,
1483         .nvm_ops                = &es2_nvm_ops,
1484 };
1485