1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Huawei HiNIC PCI Express Linux driver
4 * Copyright(c) 2017 Huawei Technologies Co., Ltd
10 #include <linux/pci.h>
12 #include <linux/types.h>
13 #include <asm/byteorder.h>
15 #define HINIC_DMA_ATTR_ST_SHIFT 0
16 #define HINIC_DMA_ATTR_AT_SHIFT 8
17 #define HINIC_DMA_ATTR_PH_SHIFT 10
18 #define HINIC_DMA_ATTR_NO_SNOOPING_SHIFT 12
19 #define HINIC_DMA_ATTR_TPH_EN_SHIFT 13
21 #define HINIC_DMA_ATTR_ST_MASK 0xFF
22 #define HINIC_DMA_ATTR_AT_MASK 0x3
23 #define HINIC_DMA_ATTR_PH_MASK 0x3
24 #define HINIC_DMA_ATTR_NO_SNOOPING_MASK 0x1
25 #define HINIC_DMA_ATTR_TPH_EN_MASK 0x1
27 #define HINIC_DMA_ATTR_SET(val, member) \
28 (((u32)(val) & HINIC_DMA_ATTR_##member##_MASK) << \
29 HINIC_DMA_ATTR_##member##_SHIFT)
31 #define HINIC_DMA_ATTR_CLEAR(val, member) \
32 ((val) & (~(HINIC_DMA_ATTR_##member##_MASK \
33 << HINIC_DMA_ATTR_##member##_SHIFT)))
35 #define HINIC_FA0_FUNC_IDX_SHIFT 0
36 #define HINIC_FA0_PF_IDX_SHIFT 10
37 #define HINIC_FA0_PCI_INTF_IDX_SHIFT 14
38 /* reserved members - off 16 */
39 #define HINIC_FA0_FUNC_TYPE_SHIFT 24
41 #define HINIC_FA0_FUNC_IDX_MASK 0x3FF
42 #define HINIC_FA0_PF_IDX_MASK 0xF
43 #define HINIC_FA0_PCI_INTF_IDX_MASK 0x3
44 #define HINIC_FA0_FUNC_TYPE_MASK 0x1
46 #define HINIC_FA0_GET(val, member) \
47 (((val) >> HINIC_FA0_##member##_SHIFT) & HINIC_FA0_##member##_MASK)
49 #define HINIC_FA1_AEQS_PER_FUNC_SHIFT 8
50 /* reserved members - off 10 */
51 #define HINIC_FA1_CEQS_PER_FUNC_SHIFT 12
52 /* reserved members - off 15 */
53 #define HINIC_FA1_IRQS_PER_FUNC_SHIFT 20
54 #define HINIC_FA1_DMA_ATTR_PER_FUNC_SHIFT 24
55 /* reserved members - off 27 */
56 #define HINIC_FA1_INIT_STATUS_SHIFT 30
58 #define HINIC_FA1_AEQS_PER_FUNC_MASK 0x3
59 #define HINIC_FA1_CEQS_PER_FUNC_MASK 0x7
60 #define HINIC_FA1_IRQS_PER_FUNC_MASK 0xF
61 #define HINIC_FA1_DMA_ATTR_PER_FUNC_MASK 0x7
62 #define HINIC_FA1_INIT_STATUS_MASK 0x1
64 #define HINIC_FA1_GET(val, member) \
65 (((val) >> HINIC_FA1_##member##_SHIFT) & HINIC_FA1_##member##_MASK)
67 #define HINIC_FA4_OUTBOUND_STATE_SHIFT 0
68 #define HINIC_FA4_DB_STATE_SHIFT 1
70 #define HINIC_FA4_OUTBOUND_STATE_MASK 0x1
71 #define HINIC_FA4_DB_STATE_MASK 0x1
73 #define HINIC_FA4_GET(val, member) \
74 (((val) >> HINIC_FA4_##member##_SHIFT) & HINIC_FA4_##member##_MASK)
76 #define HINIC_FA4_SET(val, member) \
77 ((((u32)val) & HINIC_FA4_##member##_MASK) << HINIC_FA4_##member##_SHIFT)
79 #define HINIC_FA4_CLEAR(val, member) \
80 ((val) & (~(HINIC_FA4_##member##_MASK << HINIC_FA4_##member##_SHIFT)))
82 #define HINIC_FA5_PF_ACTION_SHIFT 0
83 #define HINIC_FA5_PF_ACTION_MASK 0xFFFF
85 #define HINIC_FA5_SET(val, member) \
86 (((u32)(val) & HINIC_FA5_##member##_MASK) << HINIC_FA5_##member##_SHIFT)
88 #define HINIC_FA5_CLEAR(val, member) \
89 ((val) & (~(HINIC_FA5_##member##_MASK << HINIC_FA5_##member##_SHIFT)))
91 #define HINIC_PPF_ELECTION_IDX_SHIFT 0
92 #define HINIC_PPF_ELECTION_IDX_MASK 0x1F
94 #define HINIC_PPF_ELECTION_SET(val, member) \
95 (((u32)(val) & HINIC_PPF_ELECTION_##member##_MASK) << \
96 HINIC_PPF_ELECTION_##member##_SHIFT)
98 #define HINIC_PPF_ELECTION_GET(val, member) \
99 (((val) >> HINIC_PPF_ELECTION_##member##_SHIFT) & \
100 HINIC_PPF_ELECTION_##member##_MASK)
102 #define HINIC_PPF_ELECTION_CLEAR(val, member) \
103 ((val) & (~(HINIC_PPF_ELECTION_##member##_MASK \
104 << HINIC_PPF_ELECTION_##member##_SHIFT)))
106 #define HINIC_MSIX_PENDING_LIMIT_SHIFT 0
107 #define HINIC_MSIX_COALESC_TIMER_SHIFT 8
108 #define HINIC_MSIX_LLI_TIMER_SHIFT 16
109 #define HINIC_MSIX_LLI_CREDIT_SHIFT 24
110 #define HINIC_MSIX_RESEND_TIMER_SHIFT 29
112 #define HINIC_MSIX_PENDING_LIMIT_MASK 0xFF
113 #define HINIC_MSIX_COALESC_TIMER_MASK 0xFF
114 #define HINIC_MSIX_LLI_TIMER_MASK 0xFF
115 #define HINIC_MSIX_LLI_CREDIT_MASK 0x1F
116 #define HINIC_MSIX_RESEND_TIMER_MASK 0x7
118 #define HINIC_MSIX_ATTR_SET(val, member) \
119 (((u32)(val) & HINIC_MSIX_##member##_MASK) << \
120 HINIC_MSIX_##member##_SHIFT)
122 #define HINIC_MSIX_ATTR_GET(val, member) \
123 (((val) >> HINIC_MSIX_##member##_SHIFT) & \
124 HINIC_MSIX_##member##_MASK)
126 #define HINIC_MSIX_CNT_RESEND_TIMER_SHIFT 29
128 #define HINIC_MSIX_CNT_RESEND_TIMER_MASK 0x1
130 #define HINIC_MSIX_CNT_SET(val, member) \
131 (((u32)(val) & HINIC_MSIX_CNT_##member##_MASK) << \
132 HINIC_MSIX_CNT_##member##_SHIFT)
134 #define HINIC_HWIF_NUM_AEQS(hwif) ((hwif)->attr.num_aeqs)
135 #define HINIC_HWIF_NUM_CEQS(hwif) ((hwif)->attr.num_ceqs)
136 #define HINIC_HWIF_NUM_IRQS(hwif) ((hwif)->attr.num_irqs)
137 #define HINIC_HWIF_FUNC_IDX(hwif) ((hwif)->attr.func_idx)
138 #define HINIC_HWIF_PCI_INTF(hwif) ((hwif)->attr.pci_intf_idx)
139 #define HINIC_HWIF_PF_IDX(hwif) ((hwif)->attr.pf_idx)
140 #define HINIC_HWIF_PPF_IDX(hwif) ((hwif)->attr.ppf_idx)
142 #define HINIC_FUNC_TYPE(hwif) ((hwif)->attr.func_type)
143 #define HINIC_IS_PF(hwif) (HINIC_FUNC_TYPE(hwif) == HINIC_PF)
144 #define HINIC_IS_PPF(hwif) (HINIC_FUNC_TYPE(hwif) == HINIC_PPF)
146 #define HINIC_PCI_CFG_REGS_BAR 0
147 #define HINIC_PCI_INTR_REGS_BAR 2
148 #define HINIC_PCI_DB_BAR 4
150 #define HINIC_PCIE_ST_DISABLE 0
151 #define HINIC_PCIE_AT_DISABLE 0
152 #define HINIC_PCIE_PH_DISABLE 0
154 #define HINIC_EQ_MSIX_PENDING_LIMIT_DEFAULT 0 /* Disabled */
155 #define HINIC_EQ_MSIX_COALESC_TIMER_DEFAULT 0xFF /* max */
156 #define HINIC_EQ_MSIX_LLI_TIMER_DEFAULT 0 /* Disabled */
157 #define HINIC_EQ_MSIX_LLI_CREDIT_LIMIT_DEFAULT 0 /* Disabled */
158 #define HINIC_EQ_MSIX_RESEND_TIMER_DEFAULT 7 /* max */
160 #define HINIC_PCI_MSIX_ENTRY_SIZE 16
161 #define HINIC_PCI_MSIX_ENTRY_VECTOR_CTRL 12
162 #define HINIC_PCI_MSIX_ENTRY_CTRL_MASKBIT 1
164 enum hinic_pcie_nosnoop {
165 HINIC_PCIE_SNOOP = 0,
166 HINIC_PCIE_NO_SNOOP = 1,
169 enum hinic_pcie_tph {
170 HINIC_PCIE_TPH_DISABLE = 0,
171 HINIC_PCIE_TPH_ENABLE = 1,
174 enum hinic_func_type {
179 enum hinic_mod_type {
180 HINIC_MOD_COMM = 0, /* HW communication module */
181 HINIC_MOD_L2NIC = 1, /* L2NIC module */
182 HINIC_MOD_CFGM = 7, /* Configuration module */
188 HINIC_NODE_ID_MGMT = 21,
191 enum hinic_pf_action {
192 HINIC_PF_MGMT_INIT = 0x0,
194 HINIC_PF_MGMT_ACTIVE = 0x11,
197 enum hinic_outbound_state {
198 HINIC_OUTBOUND_ENABLE = 0,
199 HINIC_OUTBOUND_DISABLE = 1,
202 enum hinic_db_state {
204 HINIC_DB_DISABLE = 1,
207 enum hinic_msix_state {
212 struct hinic_func_attr {
217 enum hinic_func_type func_type;
229 struct pci_dev *pdev;
230 void __iomem *cfg_regs_bar;
231 void __iomem *intr_regs_base;
233 struct hinic_func_attr attr;
236 static inline u32 hinic_hwif_read_reg(struct hinic_hwif *hwif, u32 reg)
238 return be32_to_cpu(readl(hwif->cfg_regs_bar + reg));
241 static inline void hinic_hwif_write_reg(struct hinic_hwif *hwif, u32 reg,
244 writel(cpu_to_be32(val), hwif->cfg_regs_bar + reg);
247 int hinic_msix_attr_set(struct hinic_hwif *hwif, u16 msix_index,
248 u8 pending_limit, u8 coalesc_timer,
249 u8 lli_timer_cfg, u8 lli_credit_limit,
252 int hinic_msix_attr_get(struct hinic_hwif *hwif, u16 msix_index,
253 u8 *pending_limit, u8 *coalesc_timer_cfg,
254 u8 *lli_timer, u8 *lli_credit_limit,
257 void hinic_set_msix_state(struct hinic_hwif *hwif, u16 msix_idx,
258 enum hinic_msix_state flag);
260 int hinic_msix_attr_cnt_clear(struct hinic_hwif *hwif, u16 msix_index);
262 void hinic_set_pf_action(struct hinic_hwif *hwif, enum hinic_pf_action action);
264 enum hinic_outbound_state hinic_outbound_state_get(struct hinic_hwif *hwif);
266 void hinic_outbound_state_set(struct hinic_hwif *hwif,
267 enum hinic_outbound_state outbound_state);
269 enum hinic_db_state hinic_db_state_get(struct hinic_hwif *hwif);
271 void hinic_db_state_set(struct hinic_hwif *hwif,
272 enum hinic_db_state db_state);
274 int hinic_init_hwif(struct hinic_hwif *hwif, struct pci_dev *pdev);
276 void hinic_free_hwif(struct hinic_hwif *hwif);